Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4c38e0a4 JB |
4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, |
5 | 2010 Free Software Foundation, Inc. | |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 14 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 15 | (at your option) any later version. |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b | 22 | You should have received a copy of the GNU General Public License |
a9762ec7 | 23 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
24 | |
25 | #include "defs.h" | |
26 | #include "gdb_string.h" | |
5e2e9765 | 27 | #include "gdb_assert.h" |
c906108c SS |
28 | #include "frame.h" |
29 | #include "inferior.h" | |
30 | #include "symtab.h" | |
31 | #include "value.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "language.h" | |
34 | #include "gdbcore.h" | |
35 | #include "symfile.h" | |
36 | #include "objfiles.h" | |
37 | #include "gdbtypes.h" | |
38 | #include "target.h" | |
28d069e6 | 39 | #include "arch-utils.h" |
4e052eda | 40 | #include "regcache.h" |
70f80edf | 41 | #include "osabi.h" |
d1973055 | 42 | #include "mips-tdep.h" |
fe898f56 | 43 | #include "block.h" |
a4b8ebc8 | 44 | #include "reggroups.h" |
c906108c | 45 | #include "opcode/mips.h" |
c2d11a7d JM |
46 | #include "elf/mips.h" |
47 | #include "elf-bfd.h" | |
2475bac3 | 48 | #include "symcat.h" |
a4b8ebc8 | 49 | #include "sim-regno.h" |
a89aa300 | 50 | #include "dis-asm.h" |
edfae063 AC |
51 | #include "frame-unwind.h" |
52 | #include "frame-base.h" | |
53 | #include "trad-frame.h" | |
7d9b040b | 54 | #include "infcall.h" |
fed7ba43 | 55 | #include "floatformat.h" |
29709017 DJ |
56 | #include "remote.h" |
57 | #include "target-descriptions.h" | |
2bd0c3d7 | 58 | #include "dwarf2-frame.h" |
f8b73d13 | 59 | #include "user-regs.h" |
79a45b7d | 60 | #include "valprint.h" |
c906108c | 61 | |
8d5f9dcb DJ |
62 | static const struct objfile_data *mips_pdr_data; |
63 | ||
5bbcb741 | 64 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 65 | |
24e05951 | 66 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
67 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
68 | #define ST0_FR (1 << 26) | |
69 | ||
b0069a17 AC |
70 | /* The sizes of floating point registers. */ |
71 | ||
72 | enum | |
73 | { | |
74 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
75 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
76 | }; | |
77 | ||
1a69e1e4 DJ |
78 | enum |
79 | { | |
80 | MIPS32_REGSIZE = 4, | |
81 | MIPS64_REGSIZE = 8 | |
82 | }; | |
0dadbba0 | 83 | |
2e4ebe70 DJ |
84 | static const char *mips_abi_string; |
85 | ||
86 | static const char *mips_abi_strings[] = { | |
87 | "auto", | |
88 | "n32", | |
89 | "o32", | |
28d169de | 90 | "n64", |
2e4ebe70 DJ |
91 | "o64", |
92 | "eabi32", | |
93 | "eabi64", | |
94 | NULL | |
95 | }; | |
96 | ||
f8b73d13 DJ |
97 | /* The standard register names, and all the valid aliases for them. */ |
98 | struct register_alias | |
99 | { | |
100 | const char *name; | |
101 | int regnum; | |
102 | }; | |
103 | ||
104 | /* Aliases for o32 and most other ABIs. */ | |
105 | const struct register_alias mips_o32_aliases[] = { | |
106 | { "ta0", 12 }, | |
107 | { "ta1", 13 }, | |
108 | { "ta2", 14 }, | |
109 | { "ta3", 15 } | |
110 | }; | |
111 | ||
112 | /* Aliases for n32 and n64. */ | |
113 | const struct register_alias mips_n32_n64_aliases[] = { | |
114 | { "ta0", 8 }, | |
115 | { "ta1", 9 }, | |
116 | { "ta2", 10 }, | |
117 | { "ta3", 11 } | |
118 | }; | |
119 | ||
120 | /* Aliases for ABI-independent registers. */ | |
121 | const struct register_alias mips_register_aliases[] = { | |
122 | /* The architecture manuals specify these ABI-independent names for | |
123 | the GPRs. */ | |
124 | #define R(n) { "r" #n, n } | |
125 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
126 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
127 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
128 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
129 | #undef R | |
130 | ||
131 | /* k0 and k1 are sometimes called these instead (for "kernel | |
132 | temp"). */ | |
133 | { "kt0", 26 }, | |
134 | { "kt1", 27 }, | |
135 | ||
136 | /* This is the traditional GDB name for the CP0 status register. */ | |
137 | { "sr", MIPS_PS_REGNUM }, | |
138 | ||
139 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
140 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
141 | ||
142 | /* This is the traditional GDB name for the FCSR. */ | |
143 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
144 | }; | |
145 | ||
865093a3 AR |
146 | const struct register_alias mips_numeric_register_aliases[] = { |
147 | #define R(n) { #n, n } | |
148 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
149 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
150 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
151 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
152 | #undef R | |
153 | }; | |
154 | ||
c906108c SS |
155 | #ifndef MIPS_DEFAULT_FPU_TYPE |
156 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
157 | #endif | |
158 | static int mips_fpu_type_auto = 1; | |
159 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 160 | |
9ace0497 | 161 | static int mips_debug = 0; |
7a292a7a | 162 | |
29709017 DJ |
163 | /* Properties (for struct target_desc) describing the g/G packet |
164 | layout. */ | |
165 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
166 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
167 | ||
4eb0ad19 DJ |
168 | struct target_desc *mips_tdesc_gp32; |
169 | struct target_desc *mips_tdesc_gp64; | |
170 | ||
56cea623 AC |
171 | const struct mips_regnum * |
172 | mips_regnum (struct gdbarch *gdbarch) | |
173 | { | |
174 | return gdbarch_tdep (gdbarch)->regnum; | |
175 | } | |
176 | ||
177 | static int | |
178 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
179 | { | |
180 | return mips_regnum (gdbarch)->fp0 + 12; | |
181 | } | |
182 | ||
74ed0bb4 MD |
183 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
184 | == MIPS_ABI_EABI32 \ | |
185 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 186 | |
74ed0bb4 | 187 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 188 | |
74ed0bb4 | 189 | #define MIPS_LAST_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 190 | |
74ed0bb4 | 191 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 192 | |
95404a3e AC |
193 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
194 | functions to test, set, or clear bit 0 of addresses. */ | |
195 | ||
196 | static CORE_ADDR | |
197 | is_mips16_addr (CORE_ADDR addr) | |
198 | { | |
199 | return ((addr) & 1); | |
200 | } | |
201 | ||
95404a3e AC |
202 | static CORE_ADDR |
203 | unmake_mips16_addr (CORE_ADDR addr) | |
204 | { | |
5b652102 | 205 | return ((addr) & ~(CORE_ADDR) 1); |
95404a3e AC |
206 | } |
207 | ||
d1973055 KB |
208 | /* Return the MIPS ABI associated with GDBARCH. */ |
209 | enum mips_abi | |
210 | mips_abi (struct gdbarch *gdbarch) | |
211 | { | |
212 | return gdbarch_tdep (gdbarch)->mips_abi; | |
213 | } | |
214 | ||
4246e332 | 215 | int |
1b13c4f6 | 216 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 217 | { |
29709017 DJ |
218 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
219 | ||
220 | /* If we know how big the registers are, use that size. */ | |
221 | if (tdep->register_size_valid_p) | |
222 | return tdep->register_size; | |
223 | ||
224 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
225 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
226 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
227 | } | |
228 | ||
480d3dd2 AC |
229 | /* Return the currently configured (or set) saved register size. */ |
230 | ||
e6bc2e8a | 231 | unsigned int |
13326b4e | 232 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 233 | { |
1a69e1e4 DJ |
234 | switch (mips_abi (gdbarch)) |
235 | { | |
236 | case MIPS_ABI_EABI32: | |
237 | case MIPS_ABI_O32: | |
238 | return 4; | |
239 | case MIPS_ABI_N32: | |
240 | case MIPS_ABI_N64: | |
241 | case MIPS_ABI_O64: | |
242 | case MIPS_ABI_EABI64: | |
243 | return 8; | |
244 | case MIPS_ABI_UNKNOWN: | |
245 | case MIPS_ABI_LAST: | |
246 | default: | |
247 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
248 | } | |
d929b26f AC |
249 | } |
250 | ||
71b8ef93 | 251 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 252 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 253 | "info" field is used for this purpose. |
5a89d8aa | 254 | |
95f1da47 | 255 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
5a89d8aa MS |
256 | i.e. refers to a 16-bit function, and sets a "special" bit in a |
257 | minimal symbol to mark it as a 16-bit function | |
258 | ||
f594e5e9 | 259 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 260 | |
5a89d8aa | 261 | static void |
6d82d43b AC |
262 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
263 | { | |
264 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
265 | { | |
b887350f | 266 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; |
6d82d43b AC |
267 | SYMBOL_VALUE_ADDRESS (msym) |= 1; |
268 | } | |
5a89d8aa MS |
269 | } |
270 | ||
71b8ef93 MS |
271 | static int |
272 | msymbol_is_special (struct minimal_symbol *msym) | |
273 | { | |
b887350f | 274 | return MSYMBOL_TARGET_FLAG_1 (msym); |
71b8ef93 MS |
275 | } |
276 | ||
88658117 AC |
277 | /* XFER a value from the big/little/left end of the register. |
278 | Depending on the size of the value it might occupy the entire | |
279 | register or just part of it. Make an allowance for this, aligning | |
280 | things accordingly. */ | |
281 | ||
282 | static void | |
ba32f989 DJ |
283 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
284 | int reg_num, int length, | |
870cd05e MK |
285 | enum bfd_endian endian, gdb_byte *in, |
286 | const gdb_byte *out, int buf_offset) | |
88658117 | 287 | { |
88658117 | 288 | int reg_offset = 0; |
72a155b4 UW |
289 | |
290 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
291 | /* Need to transfer the left or right part of the register, based on |
292 | the targets byte order. */ | |
88658117 AC |
293 | switch (endian) |
294 | { | |
295 | case BFD_ENDIAN_BIG: | |
72a155b4 | 296 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
297 | break; |
298 | case BFD_ENDIAN_LITTLE: | |
299 | reg_offset = 0; | |
300 | break; | |
6d82d43b | 301 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
302 | reg_offset = 0; |
303 | break; | |
304 | default: | |
e2e0b3e5 | 305 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
306 | } |
307 | if (mips_debug) | |
cb1d2653 AC |
308 | fprintf_unfiltered (gdb_stderr, |
309 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
310 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
311 | if (mips_debug && out != NULL) |
312 | { | |
313 | int i; | |
cb1d2653 | 314 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 315 | for (i = 0; i < length; i++) |
cb1d2653 | 316 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
317 | } |
318 | if (in != NULL) | |
6d82d43b AC |
319 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
320 | in + buf_offset); | |
88658117 | 321 | if (out != NULL) |
6d82d43b AC |
322 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
323 | out + buf_offset); | |
88658117 AC |
324 | if (mips_debug && in != NULL) |
325 | { | |
326 | int i; | |
cb1d2653 | 327 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 328 | for (i = 0; i < length; i++) |
cb1d2653 | 329 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
330 | } |
331 | if (mips_debug) | |
332 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
333 | } | |
334 | ||
dd824b04 DJ |
335 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
336 | compatiblity mode. A return value of 1 means that we have | |
337 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
338 | ||
339 | static int | |
9c9acae0 | 340 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 341 | { |
72a155b4 | 342 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
343 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
344 | meaningful. */ | |
72a155b4 | 345 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
346 | return 0; |
347 | ||
348 | #if 0 | |
349 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
350 | in all the places we deal with FP registers. PR gdb/413. */ | |
351 | /* Otherwise check the FR bit in the status register - it controls | |
352 | the FP compatiblity mode. If it is clear we are in compatibility | |
353 | mode. */ | |
9c9acae0 | 354 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
355 | return 1; |
356 | #endif | |
361d1df0 | 357 | |
dd824b04 DJ |
358 | return 0; |
359 | } | |
360 | ||
7a292a7a | 361 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 362 | |
74ed0bb4 | 363 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 364 | |
a14ed312 | 365 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 366 | |
acdb74a0 AC |
367 | /* The list of available "set mips " and "show mips " commands */ |
368 | ||
369 | static struct cmd_list_element *setmipscmdlist = NULL; | |
370 | static struct cmd_list_element *showmipscmdlist = NULL; | |
371 | ||
5e2e9765 KB |
372 | /* Integer registers 0 thru 31 are handled explicitly by |
373 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 374 | are listed in the following tables. */ |
691c0433 | 375 | |
6d82d43b AC |
376 | enum |
377 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
378 | |
379 | /* Generic MIPS. */ | |
380 | ||
381 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
382 | "sr", "lo", "hi", "bad", "cause", "pc", |
383 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
384 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
385 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
386 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
387 | "fsr", "fir", "" /*"fp" */ , "", | |
388 | "", "", "", "", "", "", "", "", | |
389 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
390 | }; |
391 | ||
392 | /* Names of IDT R3041 registers. */ | |
393 | ||
394 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
395 | "sr", "lo", "hi", "bad", "cause", "pc", |
396 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
397 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
398 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
399 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
400 | "fsr", "fir", "", /*"fp" */ "", | |
401 | "", "", "bus", "ccfg", "", "", "", "", | |
402 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
403 | }; |
404 | ||
405 | /* Names of tx39 registers. */ | |
406 | ||
407 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
408 | "sr", "lo", "hi", "bad", "cause", "pc", |
409 | "", "", "", "", "", "", "", "", | |
410 | "", "", "", "", "", "", "", "", | |
411 | "", "", "", "", "", "", "", "", | |
412 | "", "", "", "", "", "", "", "", | |
413 | "", "", "", "", | |
414 | "", "", "", "", "", "", "", "", | |
415 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
416 | }; |
417 | ||
418 | /* Names of IRIX registers. */ | |
419 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
420 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
421 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
422 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
423 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
424 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
425 | }; |
426 | ||
cce74817 | 427 | |
5e2e9765 | 428 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 429 | static const char * |
d93859e2 | 430 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 431 | { |
d93859e2 | 432 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 KB |
433 | /* GPR names for all ABIs other than n32/n64. */ |
434 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
435 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
436 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
437 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
438 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
439 | }; |
440 | ||
441 | /* GPR names for n32 and n64 ABIs. */ | |
442 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
443 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
444 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
445 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
446 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
447 | }; |
448 | ||
d93859e2 | 449 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 450 | |
f57d151a UW |
451 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
452 | but then don't make the raw register names visible. */ | |
d93859e2 UW |
453 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
454 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
455 | return ""; |
456 | ||
5e2e9765 KB |
457 | /* The MIPS integer registers are always mapped from 0 to 31. The |
458 | names of the registers (which reflects the conventions regarding | |
459 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 460 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
461 | { |
462 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 463 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 464 | else |
a4b8ebc8 | 465 | return mips_gpr_names[rawnum]; |
5e2e9765 | 466 | } |
d93859e2 UW |
467 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
468 | return tdesc_register_name (gdbarch, rawnum); | |
469 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
470 | { |
471 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
472 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
473 | } | |
5e2e9765 KB |
474 | else |
475 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 476 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 477 | } |
5e2e9765 | 478 | |
a4b8ebc8 | 479 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 480 | |
a4b8ebc8 AC |
481 | static int |
482 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
483 | struct reggroup *reggroup) | |
484 | { | |
485 | int vector_p; | |
486 | int float_p; | |
487 | int raw_p; | |
72a155b4 UW |
488 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
489 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
490 | if (reggroup == all_reggroup) |
491 | return pseudo; | |
492 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
493 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
494 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
495 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
496 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
497 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
498 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
499 | return 0; |
500 | if (reggroup == float_reggroup) | |
501 | return float_p && pseudo; | |
502 | if (reggroup == vector_reggroup) | |
503 | return vector_p && pseudo; | |
504 | if (reggroup == general_reggroup) | |
505 | return (!vector_p && !float_p) && pseudo; | |
506 | /* Save the pseudo registers. Need to make certain that any code | |
507 | extracting register values from a saved register cache also uses | |
508 | pseudo registers. */ | |
509 | if (reggroup == save_reggroup) | |
510 | return raw_p && pseudo; | |
511 | /* Restore the same pseudo register. */ | |
512 | if (reggroup == restore_reggroup) | |
513 | return raw_p && pseudo; | |
6d82d43b | 514 | return 0; |
a4b8ebc8 AC |
515 | } |
516 | ||
f8b73d13 DJ |
517 | /* Return the groups that a MIPS register can be categorised into. |
518 | This version is only used if we have a target description which | |
519 | describes real registers (and their groups). */ | |
520 | ||
521 | static int | |
522 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
523 | struct reggroup *reggroup) | |
524 | { | |
525 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
526 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
527 | int ret; | |
528 | ||
529 | /* Only save, restore, and display the pseudo registers. Need to | |
530 | make certain that any code extracting register values from a | |
531 | saved register cache also uses pseudo registers. | |
532 | ||
533 | Note: saving and restoring the pseudo registers is slightly | |
534 | strange; if we have 64 bits, we should save and restore all | |
535 | 64 bits. But this is hard and has little benefit. */ | |
536 | if (!pseudo) | |
537 | return 0; | |
538 | ||
539 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
540 | if (ret != -1) | |
541 | return ret; | |
542 | ||
543 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
544 | } | |
545 | ||
a4b8ebc8 | 546 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 547 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 548 | registers. Take care of alignment and size problems. */ |
c5aa993b | 549 | |
a4b8ebc8 AC |
550 | static void |
551 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
47a35522 | 552 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 553 | { |
72a155b4 UW |
554 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
555 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
556 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 557 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 558 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
559 | else if (register_size (gdbarch, rawnum) > |
560 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 561 | { |
8bdf35dc | 562 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
47ebcfbe AC |
563 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
564 | else | |
8bdf35dc KB |
565 | { |
566 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
567 | LONGEST regval; | |
568 | regcache_raw_read_signed (regcache, rawnum, ®val); | |
569 | store_signed_integer (buf, 4, byte_order, regval); | |
570 | } | |
47ebcfbe AC |
571 | } |
572 | else | |
e2e0b3e5 | 573 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
574 | } |
575 | ||
576 | static void | |
6d82d43b AC |
577 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
578 | struct regcache *regcache, int cookednum, | |
47a35522 | 579 | const gdb_byte *buf) |
a4b8ebc8 | 580 | { |
72a155b4 UW |
581 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
582 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
583 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 584 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 585 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
586 | else if (register_size (gdbarch, rawnum) > |
587 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 588 | { |
8bdf35dc | 589 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
47ebcfbe AC |
590 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
591 | else | |
8bdf35dc KB |
592 | { |
593 | /* Sign extend the shortened version of the register prior | |
594 | to placing it in the raw register. This is required for | |
595 | some mips64 parts in order to avoid unpredictable behavior. */ | |
596 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
597 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); | |
598 | regcache_raw_write_signed (regcache, rawnum, regval); | |
599 | } | |
47ebcfbe AC |
600 | } |
601 | else | |
e2e0b3e5 | 602 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 603 | } |
c5aa993b | 604 | |
c906108c | 605 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 606 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
607 | |
608 | /* Heuristic_proc_start may hunt through the text section for a long | |
609 | time across a 2400 baud serial line. Allows the user to limit this | |
610 | search. */ | |
611 | ||
612 | static unsigned int heuristic_fence_post = 0; | |
613 | ||
46cd78fb | 614 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
615 | register N. NOTE: This defines the pseudo register type so need to |
616 | rebuild the architecture vector. */ | |
43e526b9 JM |
617 | |
618 | static int mips64_transfers_32bit_regs_p = 0; | |
619 | ||
719ec221 AC |
620 | static void |
621 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
622 | struct cmd_list_element *c) | |
43e526b9 | 623 | { |
719ec221 AC |
624 | struct gdbarch_info info; |
625 | gdbarch_info_init (&info); | |
626 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
627 | instead of relying on globals. Doing that would let generic code | |
628 | handle the search for this specific architecture. */ | |
629 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 630 | { |
719ec221 | 631 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 632 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 633 | } |
a4b8ebc8 AC |
634 | } |
635 | ||
47ebcfbe | 636 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 637 | |
ff2e87ac | 638 | static int |
0abe36f5 | 639 | mips_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type) |
ff2e87ac | 640 | { |
0abe36f5 MD |
641 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
642 | && register_size (gdbarch, regnum) == 4 | |
643 | && (regnum % gdbarch_num_regs (gdbarch)) | |
644 | >= mips_regnum (gdbarch)->fp0 | |
645 | && (regnum % gdbarch_num_regs (gdbarch)) | |
646 | < mips_regnum (gdbarch)->fp0 + 32 | |
6d82d43b | 647 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
648 | } |
649 | ||
42c466d7 | 650 | static void |
ff2e87ac | 651 | mips_register_to_value (struct frame_info *frame, int regnum, |
47a35522 | 652 | struct type *type, gdb_byte *to) |
102182a9 | 653 | { |
47a35522 MK |
654 | get_frame_register (frame, regnum + 0, to + 4); |
655 | get_frame_register (frame, regnum + 1, to + 0); | |
102182a9 MS |
656 | } |
657 | ||
42c466d7 | 658 | static void |
ff2e87ac | 659 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 660 | struct type *type, const gdb_byte *from) |
102182a9 | 661 | { |
47a35522 MK |
662 | put_frame_register (frame, regnum + 0, from + 4); |
663 | put_frame_register (frame, regnum + 1, from + 0); | |
102182a9 MS |
664 | } |
665 | ||
a4b8ebc8 AC |
666 | /* Return the GDB type object for the "standard" data type of data in |
667 | register REG. */ | |
78fde5f8 KB |
668 | |
669 | static struct type * | |
a4b8ebc8 AC |
670 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
671 | { | |
72a155b4 UW |
672 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
673 | if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0 | |
674 | && (regnum % gdbarch_num_regs (gdbarch)) | |
675 | < mips_regnum (gdbarch)->fp0 + 32) | |
a6425924 | 676 | { |
5ef80fb0 | 677 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 678 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 679 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 680 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 681 | else |
27067745 | 682 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 683 | } |
72a155b4 | 684 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
685 | { |
686 | /* The raw or ISA registers. These are all sized according to | |
687 | the ISA regsize. */ | |
688 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 689 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 690 | else |
df4df182 | 691 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 692 | } |
78fde5f8 | 693 | else |
d5ac5a39 AC |
694 | { |
695 | /* The cooked or ABI registers. These are sized according to | |
696 | the ABI (with a few complications). */ | |
72a155b4 UW |
697 | if (regnum >= (gdbarch_num_regs (gdbarch) |
698 | + mips_regnum (gdbarch)->fp_control_status) | |
699 | && regnum <= gdbarch_num_regs (gdbarch) + MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
700 | /* The pseudo/cooked view of the embedded registers is always |
701 | 32-bit. The raw view is handled below. */ | |
df4df182 | 702 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
703 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
704 | /* The target, while possibly using a 64-bit register buffer, | |
705 | is only transfering 32-bits of each integer register. | |
706 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 707 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
708 | else if (mips_abi_regsize (gdbarch) == 4) |
709 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
710 | 32- or 64-bit). */ | |
df4df182 | 711 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
712 | else |
713 | /* 64-bit ABI. */ | |
df4df182 | 714 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 715 | } |
78fde5f8 KB |
716 | } |
717 | ||
f8b73d13 DJ |
718 | /* Return the GDB type for the pseudo register REGNUM, which is the |
719 | ABI-level view. This function is only called if there is a target | |
720 | description which includes registers, so we know precisely the | |
721 | types of hardware registers. */ | |
722 | ||
723 | static struct type * | |
724 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
725 | { | |
726 | const int num_regs = gdbarch_num_regs (gdbarch); | |
727 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
728 | int rawnum = regnum % num_regs; | |
729 | struct type *rawtype; | |
730 | ||
731 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
732 | ||
733 | /* Absent registers are still absent. */ | |
734 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
735 | if (TYPE_LENGTH (rawtype) == 0) | |
736 | return rawtype; | |
737 | ||
738 | if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32) | |
739 | /* Present the floating point registers however the hardware did; | |
740 | do not try to convert between FPU layouts. */ | |
741 | return rawtype; | |
742 | ||
743 | if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
744 | { | |
745 | /* The pseudo/cooked view of embedded registers is always | |
746 | 32-bit, even if the target transfers 64-bit values for them. | |
747 | New targets relying on XML descriptions should only transfer | |
748 | the necessary 32 bits, but older versions of GDB expected 64, | |
749 | so allow the target to provide 64 bits without interfering | |
750 | with the displayed type. */ | |
df4df182 | 751 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 DJ |
752 | } |
753 | ||
754 | /* Use pointer types for registers if we can. For n32 we can not, | |
755 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
756 | if (mips_abi_regsize (gdbarch) |
757 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 DJ |
758 | { |
759 | if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM) | |
0dfff4cb | 760 | return builtin_type (gdbarch)->builtin_data_ptr; |
f8b73d13 | 761 | else if (rawnum == MIPS_EMBED_PC_REGNUM) |
0dfff4cb | 762 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
763 | } |
764 | ||
765 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
766 | && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM) | |
df4df182 | 767 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 DJ |
768 | |
769 | /* For all other registers, pass through the hardware type. */ | |
770 | return rawtype; | |
771 | } | |
bcb0cc15 | 772 | |
c906108c | 773 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 774 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
775 | |
776 | static int | |
480d3dd2 | 777 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
778 | { |
779 | switch (mask_address_var) | |
780 | { | |
7f19b9a2 | 781 | case AUTO_BOOLEAN_TRUE: |
4014092b | 782 | return 1; |
7f19b9a2 | 783 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
784 | return 0; |
785 | break; | |
7f19b9a2 | 786 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 787 | return tdep->default_mask_address_p; |
4014092b | 788 | default: |
e2e0b3e5 | 789 | internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch")); |
4014092b | 790 | return -1; |
361d1df0 | 791 | } |
4014092b AC |
792 | } |
793 | ||
794 | static void | |
08546159 AC |
795 | show_mask_address (struct ui_file *file, int from_tty, |
796 | struct cmd_list_element *c, const char *value) | |
4014092b | 797 | { |
1cf3db46 | 798 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
08546159 AC |
799 | |
800 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
801 | switch (mask_address_var) |
802 | { | |
7f19b9a2 | 803 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
804 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
805 | break; | |
7f19b9a2 | 806 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
807 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
808 | break; | |
7f19b9a2 | 809 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
810 | printf_filtered |
811 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
812 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
813 | break; |
814 | default: | |
e2e0b3e5 | 815 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 816 | break; |
361d1df0 | 817 | } |
4014092b | 818 | } |
c906108c | 819 | |
c906108c SS |
820 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
821 | ||
0fe7e7c8 AC |
822 | int |
823 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
824 | { |
825 | struct minimal_symbol *sym; | |
826 | ||
827 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 828 | if (is_mips16_addr (memaddr)) |
c906108c SS |
829 | return 1; |
830 | ||
831 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
832 | the high bit of the info field. Use this to decide if the function is | |
833 | MIPS16 or normal MIPS. */ | |
834 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
835 | if (sym) | |
71b8ef93 | 836 | return msymbol_is_special (sym); |
c906108c SS |
837 | else |
838 | return 0; | |
839 | } | |
840 | ||
b2fa5097 | 841 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
842 | all registers should be sign extended for simplicity? */ |
843 | ||
844 | static CORE_ADDR | |
61a1198a | 845 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 846 | { |
61a1198a UW |
847 | ULONGEST pc; |
848 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; | |
849 | regcache_cooked_read_signed (regcache, regnum, &pc); | |
850 | return pc; | |
b6cb9035 AC |
851 | } |
852 | ||
58dfe9ff AC |
853 | static CORE_ADDR |
854 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
855 | { | |
72a155b4 UW |
856 | return frame_unwind_register_signed |
857 | (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc); | |
edfae063 AC |
858 | } |
859 | ||
30244cd8 UW |
860 | static CORE_ADDR |
861 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
862 | { | |
72a155b4 UW |
863 | return frame_unwind_register_signed |
864 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
865 | } |
866 | ||
b8a22b94 | 867 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
868 | dummy frame. The frame ID's base needs to match the TOS value |
869 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
870 | breakpoint. */ | |
871 | ||
872 | static struct frame_id | |
b8a22b94 | 873 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 874 | { |
f57d151a | 875 | return frame_id_build |
b8a22b94 DJ |
876 | (get_frame_register_signed (this_frame, |
877 | gdbarch_num_regs (gdbarch) | |
878 | + MIPS_SP_REGNUM), | |
879 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
880 | } |
881 | ||
b6cb9035 | 882 | static void |
61a1198a | 883 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 884 | { |
61a1198a UW |
885 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; |
886 | regcache_cooked_write_unsigned (regcache, regnum, pc); | |
6c997a34 | 887 | } |
c906108c | 888 | |
c906108c SS |
889 | /* Fetch and return instruction from the specified location. If the PC |
890 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
891 | ||
d37cca3d | 892 | static ULONGEST |
e17a4113 | 893 | mips_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr) |
c906108c | 894 | { |
e17a4113 | 895 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 896 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
897 | int instlen; |
898 | int status; | |
899 | ||
0fe7e7c8 | 900 | if (mips_pc_is_mips16 (addr)) |
c906108c | 901 | { |
95ac2dcf | 902 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 903 | addr = unmake_mips16_addr (addr); |
c906108c SS |
904 | } |
905 | else | |
95ac2dcf | 906 | instlen = MIPS_INSN32_SIZE; |
8defab1a | 907 | status = target_read_memory (addr, buf, instlen); |
c906108c SS |
908 | if (status) |
909 | memory_error (status, addr); | |
e17a4113 | 910 | return extract_unsigned_integer (buf, instlen, byte_order); |
c906108c SS |
911 | } |
912 | ||
c906108c | 913 | /* These the fields of 32 bit mips instructions */ |
e135b889 DJ |
914 | #define mips32_op(x) (x >> 26) |
915 | #define itype_op(x) (x >> 26) | |
916 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 917 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 918 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 919 | |
e135b889 DJ |
920 | #define jtype_op(x) (x >> 26) |
921 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 922 | |
e135b889 DJ |
923 | #define rtype_op(x) (x >> 26) |
924 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
925 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
926 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
927 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
928 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 929 | |
06987e64 MK |
930 | static LONGEST |
931 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 932 | { |
06987e64 | 933 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
934 | } |
935 | ||
f49e4e6d MS |
936 | /* Determine where to set a single step breakpoint while considering |
937 | branch prediction. */ | |
5a89d8aa | 938 | static CORE_ADDR |
0b1b3e42 | 939 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b | 940 | { |
e17a4113 | 941 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c5aa993b JM |
942 | unsigned long inst; |
943 | int op; | |
e17a4113 | 944 | inst = mips_fetch_instruction (gdbarch, pc); |
e135b889 | 945 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 946 | { |
e135b889 | 947 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 948 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 949 | { |
e135b889 | 950 | op = (itype_op (inst) & 0x03); |
c906108c SS |
951 | switch (op) |
952 | { | |
e135b889 DJ |
953 | case 0: /* BEQL */ |
954 | goto equal_branch; | |
955 | case 1: /* BNEL */ | |
956 | goto neq_branch; | |
957 | case 2: /* BLEZL */ | |
958 | goto less_branch; | |
313628cc | 959 | case 3: /* BGTZL */ |
e135b889 | 960 | goto greater_branch; |
c5aa993b JM |
961 | default: |
962 | pc += 4; | |
c906108c SS |
963 | } |
964 | } | |
e135b889 | 965 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 966 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
967 | { |
968 | int tf = itype_rt (inst) & 0x01; | |
969 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b | 970 | int fcrcs = |
72a155b4 UW |
971 | get_frame_register_signed (frame, |
972 | mips_regnum (get_frame_arch (frame))-> | |
0b1b3e42 | 973 | fp_control_status); |
e135b889 DJ |
974 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
975 | ||
976 | if (((cond >> cnum) & 0x01) == tf) | |
977 | pc += mips32_relative_offset (inst) + 4; | |
978 | else | |
979 | pc += 8; | |
980 | } | |
c5aa993b JM |
981 | else |
982 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
983 | } |
984 | else | |
c5aa993b JM |
985 | { /* This gets way messy */ |
986 | ||
c906108c | 987 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 988 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 989 | { |
c5aa993b JM |
990 | case 0: /* SPECIAL */ |
991 | op = rtype_funct (inst); | |
992 | switch (op) | |
993 | { | |
994 | case 8: /* JR */ | |
995 | case 9: /* JALR */ | |
6c997a34 | 996 | /* Set PC to that address */ |
0b1b3e42 | 997 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b | 998 | break; |
e38d4e1a DJ |
999 | case 12: /* SYSCALL */ |
1000 | { | |
1001 | struct gdbarch_tdep *tdep; | |
1002 | ||
1003 | tdep = gdbarch_tdep (get_frame_arch (frame)); | |
1004 | if (tdep->syscall_next_pc != NULL) | |
1005 | pc = tdep->syscall_next_pc (frame); | |
1006 | else | |
1007 | pc += 4; | |
1008 | } | |
1009 | break; | |
c5aa993b JM |
1010 | default: |
1011 | pc += 4; | |
1012 | } | |
1013 | ||
6d82d43b | 1014 | break; /* end SPECIAL */ |
c5aa993b | 1015 | case 1: /* REGIMM */ |
c906108c | 1016 | { |
e135b889 DJ |
1017 | op = itype_rt (inst); /* branch condition */ |
1018 | switch (op) | |
c906108c | 1019 | { |
c5aa993b | 1020 | case 0: /* BLTZ */ |
e135b889 DJ |
1021 | case 2: /* BLTZL */ |
1022 | case 16: /* BLTZAL */ | |
c5aa993b | 1023 | case 18: /* BLTZALL */ |
c906108c | 1024 | less_branch: |
0b1b3e42 | 1025 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1026 | pc += mips32_relative_offset (inst) + 4; |
1027 | else | |
1028 | pc += 8; /* after the delay slot */ | |
1029 | break; | |
e135b889 | 1030 | case 1: /* BGEZ */ |
c5aa993b JM |
1031 | case 3: /* BGEZL */ |
1032 | case 17: /* BGEZAL */ | |
1033 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1034 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1035 | pc += mips32_relative_offset (inst) + 4; |
1036 | else | |
1037 | pc += 8; /* after the delay slot */ | |
1038 | break; | |
e135b889 | 1039 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1040 | default: |
1041 | pc += 4; | |
c906108c SS |
1042 | } |
1043 | } | |
6d82d43b | 1044 | break; /* end REGIMM */ |
c5aa993b JM |
1045 | case 2: /* J */ |
1046 | case 3: /* JAL */ | |
1047 | { | |
1048 | unsigned long reg; | |
1049 | reg = jtype_target (inst) << 2; | |
e135b889 | 1050 | /* Upper four bits get never changed... */ |
5b652102 | 1051 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1052 | } |
c5aa993b JM |
1053 | break; |
1054 | /* FIXME case JALX : */ | |
1055 | { | |
1056 | unsigned long reg; | |
1057 | reg = jtype_target (inst) << 2; | |
5b652102 | 1058 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ |
c906108c SS |
1059 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1060 | } | |
c5aa993b | 1061 | break; /* The new PC will be alternate mode */ |
e135b889 | 1062 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1063 | equal_branch: |
0b1b3e42 UW |
1064 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1065 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1066 | pc += mips32_relative_offset (inst) + 4; |
1067 | else | |
1068 | pc += 8; | |
1069 | break; | |
e135b889 | 1070 | case 5: /* BNE, BNEL */ |
c5aa993b | 1071 | neq_branch: |
0b1b3e42 UW |
1072 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1073 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1074 | pc += mips32_relative_offset (inst) + 4; |
1075 | else | |
1076 | pc += 8; | |
1077 | break; | |
e135b889 | 1078 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1079 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1080 | pc += mips32_relative_offset (inst) + 4; |
1081 | else | |
1082 | pc += 8; | |
1083 | break; | |
1084 | case 7: | |
e135b889 DJ |
1085 | default: |
1086 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1087 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1088 | pc += mips32_relative_offset (inst) + 4; |
1089 | else | |
1090 | pc += 8; | |
1091 | break; | |
c5aa993b JM |
1092 | } /* switch */ |
1093 | } /* else */ | |
1094 | return pc; | |
1095 | } /* mips32_next_pc */ | |
c906108c SS |
1096 | |
1097 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1098 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1099 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1100 | We dont want to set a single step instruction on the extend instruction | |
1101 | either. | |
c5aa993b | 1102 | */ |
c906108c SS |
1103 | |
1104 | /* Lots of mips16 instruction formats */ | |
1105 | /* Predicting jumps requires itype,ritype,i8type | |
1106 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1107 | */ |
c906108c SS |
1108 | enum mips16_inst_fmts |
1109 | { | |
c5aa993b JM |
1110 | itype, /* 0 immediate 5,10 */ |
1111 | ritype, /* 1 5,3,8 */ | |
1112 | rrtype, /* 2 5,3,3,5 */ | |
1113 | rritype, /* 3 5,3,3,5 */ | |
1114 | rrrtype, /* 4 5,3,3,3,2 */ | |
1115 | rriatype, /* 5 5,3,3,1,4 */ | |
1116 | shifttype, /* 6 5,3,3,3,2 */ | |
1117 | i8type, /* 7 5,3,8 */ | |
1118 | i8movtype, /* 8 5,3,3,5 */ | |
1119 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1120 | i64type, /* 10 5,3,8 */ | |
1121 | ri64type, /* 11 5,3,3,5 */ | |
1122 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1123 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1124 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1125 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1126 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1127 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1128 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1129 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1130 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1131 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1132 | }; | |
12f02c2a AC |
1133 | /* I am heaping all the fields of the formats into one structure and |
1134 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1135 | struct upk_mips16 |
6d82d43b AC |
1136 | { |
1137 | CORE_ADDR offset; | |
1138 | unsigned int regx; /* Function in i8 type */ | |
1139 | unsigned int regy; | |
1140 | }; | |
c906108c SS |
1141 | |
1142 | ||
12f02c2a | 1143 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 1144 | for the bits which make up the immediate extension. */ |
c906108c | 1145 | |
12f02c2a AC |
1146 | static CORE_ADDR |
1147 | extended_offset (unsigned int extension) | |
c906108c | 1148 | { |
12f02c2a | 1149 | CORE_ADDR value; |
c5aa993b JM |
1150 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1151 | value = value << 6; | |
1152 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1153 | value = value << 5; | |
1154 | value |= extension & 0x01f; /* extract 4:0 */ | |
1155 | return value; | |
c906108c SS |
1156 | } |
1157 | ||
1158 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
1159 | instruction. It won't malfunction, but why make excess remote memory |
1160 | references? If the immediate operands get sign extended or something, | |
1161 | do it after the extension is performed. */ | |
c906108c | 1162 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 1163 | when the offset is to be used in relative addressing. */ |
c906108c | 1164 | |
12f02c2a | 1165 | static unsigned int |
e17a4113 | 1166 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 1167 | { |
e17a4113 | 1168 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1169 | gdb_byte buf[8]; |
c5aa993b JM |
1170 | pc &= 0xfffffffe; /* clear the low order bit */ |
1171 | target_read_memory (pc, buf, 2); | |
e17a4113 | 1172 | return extract_unsigned_integer (buf, 2, byte_order); |
c906108c SS |
1173 | } |
1174 | ||
1175 | static void | |
e17a4113 | 1176 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
12f02c2a AC |
1177 | unsigned int extension, |
1178 | unsigned int inst, | |
6d82d43b | 1179 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1180 | { |
12f02c2a AC |
1181 | CORE_ADDR offset; |
1182 | int regx; | |
1183 | int regy; | |
1184 | switch (insn_format) | |
c906108c | 1185 | { |
c5aa993b | 1186 | case itype: |
c906108c | 1187 | { |
12f02c2a AC |
1188 | CORE_ADDR value; |
1189 | if (extension) | |
c5aa993b JM |
1190 | { |
1191 | value = extended_offset (extension); | |
1192 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1193 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1194 | } |
1195 | else | |
c5aa993b | 1196 | { |
12f02c2a | 1197 | value = inst & 0x7ff; |
c5aa993b | 1198 | /* FIXME : Consider sign extension */ |
c906108c | 1199 | } |
12f02c2a AC |
1200 | offset = value; |
1201 | regx = -1; | |
1202 | regy = -1; | |
c906108c | 1203 | } |
c5aa993b JM |
1204 | break; |
1205 | case ritype: | |
1206 | case i8type: | |
1207 | { /* A register identifier and an offset */ | |
c906108c SS |
1208 | /* Most of the fields are the same as I type but the |
1209 | immediate value is of a different length */ | |
12f02c2a AC |
1210 | CORE_ADDR value; |
1211 | if (extension) | |
c906108c | 1212 | { |
c5aa993b JM |
1213 | value = extended_offset (extension); |
1214 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1215 | value |= inst & 0xff; /* eleven bits from instruction */ |
1216 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1217 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1218 | { | |
1219 | value &= ~0x3fff; /* remove the sign bit */ | |
1220 | value = -value; | |
c906108c SS |
1221 | } |
1222 | } | |
c5aa993b JM |
1223 | else |
1224 | { | |
12f02c2a AC |
1225 | value = inst & 0xff; /* 8 bits */ |
1226 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1227 | /* FIXME: Do sign extension , this format needs it */ |
1228 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1229 | { | |
1230 | value &= 0xef; /* remove the sign bit */ | |
1231 | value = -value; | |
1232 | } | |
c5aa993b | 1233 | } |
12f02c2a AC |
1234 | offset = value; |
1235 | regy = -1; | |
c5aa993b | 1236 | break; |
c906108c | 1237 | } |
c5aa993b | 1238 | case jalxtype: |
c906108c | 1239 | { |
c5aa993b | 1240 | unsigned long value; |
12f02c2a AC |
1241 | unsigned int nexthalf; |
1242 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b | 1243 | value = value << 16; |
e17a4113 | 1244 | nexthalf = mips_fetch_instruction (gdbarch, pc + 2); /* low bit still set */ |
c5aa993b | 1245 | value |= nexthalf; |
12f02c2a AC |
1246 | offset = value; |
1247 | regx = -1; | |
1248 | regy = -1; | |
c5aa993b | 1249 | break; |
c906108c SS |
1250 | } |
1251 | default: | |
e2e0b3e5 | 1252 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1253 | } |
12f02c2a AC |
1254 | upk->offset = offset; |
1255 | upk->regx = regx; | |
1256 | upk->regy = regy; | |
c906108c SS |
1257 | } |
1258 | ||
1259 | ||
c5aa993b JM |
1260 | static CORE_ADDR |
1261 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1262 | { |
5b652102 | 1263 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
1264 | } |
1265 | ||
12f02c2a | 1266 | static CORE_ADDR |
0b1b3e42 | 1267 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 1268 | unsigned int extension, unsigned int insn) |
c906108c | 1269 | { |
e17a4113 | 1270 | struct gdbarch *gdbarch = get_frame_arch (frame); |
12f02c2a AC |
1271 | int op = (insn >> 11); |
1272 | switch (op) | |
c906108c | 1273 | { |
6d82d43b | 1274 | case 2: /* Branch */ |
12f02c2a AC |
1275 | { |
1276 | CORE_ADDR offset; | |
1277 | struct upk_mips16 upk; | |
e17a4113 | 1278 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
12f02c2a AC |
1279 | offset = upk.offset; |
1280 | if (offset & 0x800) | |
1281 | { | |
1282 | offset &= 0xeff; | |
1283 | offset = -offset; | |
1284 | } | |
1285 | pc += (offset << 1) + 2; | |
1286 | break; | |
1287 | } | |
6d82d43b | 1288 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1289 | { |
1290 | struct upk_mips16 upk; | |
e17a4113 | 1291 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
12f02c2a AC |
1292 | pc = add_offset_16 (pc, upk.offset); |
1293 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1294 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1295 | else | |
1296 | pc |= 0x01; | |
1297 | break; | |
1298 | } | |
6d82d43b | 1299 | case 4: /* beqz */ |
12f02c2a AC |
1300 | { |
1301 | struct upk_mips16 upk; | |
1302 | int reg; | |
e17a4113 | 1303 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
0b1b3e42 | 1304 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1305 | if (reg == 0) |
1306 | pc += (upk.offset << 1) + 2; | |
1307 | else | |
1308 | pc += 2; | |
1309 | break; | |
1310 | } | |
6d82d43b | 1311 | case 5: /* bnez */ |
12f02c2a AC |
1312 | { |
1313 | struct upk_mips16 upk; | |
1314 | int reg; | |
e17a4113 | 1315 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
0b1b3e42 | 1316 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1317 | if (reg != 0) |
1318 | pc += (upk.offset << 1) + 2; | |
1319 | else | |
1320 | pc += 2; | |
1321 | break; | |
1322 | } | |
6d82d43b | 1323 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1324 | { |
1325 | struct upk_mips16 upk; | |
1326 | int reg; | |
e17a4113 | 1327 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
12f02c2a | 1328 | /* upk.regx contains the opcode */ |
0b1b3e42 | 1329 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
1330 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
1331 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1332 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1333 | pc += (upk.offset << 1) + 2; | |
1334 | else | |
1335 | pc += 2; | |
1336 | break; | |
1337 | } | |
6d82d43b | 1338 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1339 | { |
1340 | struct upk_mips16 upk; | |
1341 | /* upk.fmt = rrtype; */ | |
1342 | op = insn & 0x1f; | |
1343 | if (op == 0) | |
c5aa993b | 1344 | { |
12f02c2a AC |
1345 | int reg; |
1346 | upk.regx = (insn >> 8) & 0x07; | |
1347 | upk.regy = (insn >> 5) & 0x07; | |
1348 | switch (upk.regy) | |
c5aa993b | 1349 | { |
12f02c2a AC |
1350 | case 0: |
1351 | reg = upk.regx; | |
1352 | break; | |
1353 | case 1: | |
1354 | reg = 31; | |
6d82d43b | 1355 | break; /* Function return instruction */ |
12f02c2a AC |
1356 | case 2: |
1357 | reg = upk.regx; | |
1358 | break; | |
1359 | default: | |
1360 | reg = 31; | |
6d82d43b | 1361 | break; /* BOGUS Guess */ |
c906108c | 1362 | } |
0b1b3e42 | 1363 | pc = get_frame_register_signed (frame, reg); |
c906108c | 1364 | } |
12f02c2a | 1365 | else |
c5aa993b | 1366 | pc += 2; |
12f02c2a AC |
1367 | break; |
1368 | } | |
1369 | case 30: | |
1370 | /* This is an instruction extension. Fetch the real instruction | |
1371 | (which follows the extension) and decode things based on | |
1372 | that. */ | |
1373 | { | |
1374 | pc += 2; | |
e17a4113 UW |
1375 | pc = extended_mips16_next_pc (frame, pc, insn, |
1376 | fetch_mips_16 (gdbarch, pc)); | |
12f02c2a AC |
1377 | break; |
1378 | } | |
1379 | default: | |
1380 | { | |
1381 | pc += 2; | |
1382 | break; | |
1383 | } | |
c906108c | 1384 | } |
c5aa993b | 1385 | return pc; |
12f02c2a | 1386 | } |
c906108c | 1387 | |
5a89d8aa | 1388 | static CORE_ADDR |
0b1b3e42 | 1389 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a | 1390 | { |
e17a4113 UW |
1391 | struct gdbarch *gdbarch = get_frame_arch (frame); |
1392 | unsigned int insn = fetch_mips_16 (gdbarch, pc); | |
0b1b3e42 | 1393 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
1394 | } |
1395 | ||
1396 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1397 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1398 | It works by decoding the current instruction and predicting where a |
1399 | branch will go. This isnt hard because all the data is available. | |
ce1f96de | 1400 | The MIPS32 and MIPS16 variants are quite different. */ |
ad527d2e | 1401 | static CORE_ADDR |
0b1b3e42 | 1402 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1403 | { |
ce1f96de | 1404 | if (is_mips16_addr (pc)) |
0b1b3e42 | 1405 | return mips16_next_pc (frame, pc); |
c5aa993b | 1406 | else |
0b1b3e42 | 1407 | return mips32_next_pc (frame, pc); |
12f02c2a | 1408 | } |
c906108c | 1409 | |
edfae063 AC |
1410 | struct mips_frame_cache |
1411 | { | |
1412 | CORE_ADDR base; | |
1413 | struct trad_frame_saved_reg *saved_regs; | |
1414 | }; | |
1415 | ||
29639122 JB |
1416 | /* Set a register's saved stack address in temp_saved_regs. If an |
1417 | address has already been set for this register, do nothing; this | |
1418 | way we will only recognize the first save of a given register in a | |
1419 | function prologue. | |
eec63939 | 1420 | |
f57d151a UW |
1421 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
1422 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
1423 | Strictly speaking, only the second range is used as it is only second | |
1424 | range (the ABI instead of ISA registers) that comes into play when finding | |
1425 | saved registers in a frame. */ | |
eec63939 AC |
1426 | |
1427 | static void | |
74ed0bb4 MD |
1428 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
1429 | int regnum, CORE_ADDR offset) | |
eec63939 | 1430 | { |
29639122 JB |
1431 | if (this_cache != NULL |
1432 | && this_cache->saved_regs[regnum].addr == -1) | |
1433 | { | |
74ed0bb4 MD |
1434 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
1435 | = offset; | |
1436 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr | |
1437 | = offset; | |
29639122 | 1438 | } |
eec63939 AC |
1439 | } |
1440 | ||
eec63939 | 1441 | |
29639122 JB |
1442 | /* Fetch the immediate value from a MIPS16 instruction. |
1443 | If the previous instruction was an EXTEND, use it to extend | |
1444 | the upper bits of the immediate value. This is a helper function | |
1445 | for mips16_scan_prologue. */ | |
eec63939 | 1446 | |
29639122 JB |
1447 | static int |
1448 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1449 | unsigned short inst, /* current instruction */ | |
1450 | int nbits, /* number of bits in imm field */ | |
1451 | int scale, /* scale factor to be applied to imm */ | |
1452 | int is_signed) /* is the imm field signed? */ | |
eec63939 | 1453 | { |
29639122 | 1454 | int offset; |
eec63939 | 1455 | |
29639122 JB |
1456 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1457 | { | |
1458 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1459 | if (offset & 0x8000) /* check for negative extend */ | |
1460 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1461 | return offset | (inst & 0x1f); | |
1462 | } | |
eec63939 | 1463 | else |
29639122 JB |
1464 | { |
1465 | int max_imm = 1 << nbits; | |
1466 | int mask = max_imm - 1; | |
1467 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1468 | |
29639122 JB |
1469 | offset = inst & mask; |
1470 | if (is_signed && (offset & sign_bit)) | |
1471 | offset = 0 - (max_imm - offset); | |
1472 | return offset * scale; | |
1473 | } | |
1474 | } | |
eec63939 | 1475 | |
65596487 | 1476 | |
29639122 JB |
1477 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1478 | the associated FRAME_CACHE if not null. | |
1479 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1480 | |
29639122 | 1481 | static CORE_ADDR |
e17a4113 UW |
1482 | mips16_scan_prologue (struct gdbarch *gdbarch, |
1483 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 1484 | struct frame_info *this_frame, |
29639122 JB |
1485 | struct mips_frame_cache *this_cache) |
1486 | { | |
1487 | CORE_ADDR cur_pc; | |
1488 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1489 | CORE_ADDR sp; | |
1490 | long frame_offset = 0; /* Size of stack frame. */ | |
1491 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1492 | int frame_reg = MIPS_SP_REGNUM; | |
1493 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1494 | unsigned inst = 0; /* current instruction */ | |
1495 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 1496 | unsigned save_inst = 0; /* the save instruction */ |
29639122 | 1497 | int reg, offset; |
a343eb3c | 1498 | |
29639122 JB |
1499 | int extend_bytes = 0; |
1500 | int prev_extend_bytes; | |
1501 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 1502 | |
29639122 | 1503 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
1504 | THIS_FRAME. */ |
1505 | if (this_frame != NULL) | |
1506 | sp = get_frame_register_signed (this_frame, | |
1507 | gdbarch_num_regs (gdbarch) | |
1508 | + MIPS_SP_REGNUM); | |
29639122 JB |
1509 | else |
1510 | sp = 0; | |
eec63939 | 1511 | |
29639122 JB |
1512 | if (limit_pc > start_pc + 200) |
1513 | limit_pc = start_pc + 200; | |
eec63939 | 1514 | |
95ac2dcf | 1515 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1516 | { |
1517 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1518 | the immediate offset extension from it in mips16_get_imm. */ | |
1519 | prev_inst = inst; | |
eec63939 | 1520 | |
29639122 | 1521 | /* Fetch and decode the instruction. */ |
e17a4113 | 1522 | inst = (unsigned short) mips_fetch_instruction (gdbarch, cur_pc); |
eec63939 | 1523 | |
29639122 JB |
1524 | /* Normally we ignore extend instructions. However, if it is |
1525 | not followed by a valid prologue instruction, then this | |
1526 | instruction is not part of the prologue either. We must | |
1527 | remember in this case to adjust the end_prologue_addr back | |
1528 | over the extend. */ | |
1529 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1530 | { | |
95ac2dcf | 1531 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1532 | continue; |
1533 | } | |
eec63939 | 1534 | |
29639122 JB |
1535 | prev_extend_bytes = extend_bytes; |
1536 | extend_bytes = 0; | |
eec63939 | 1537 | |
29639122 JB |
1538 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1539 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1540 | { | |
1541 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
1542 | if (offset < 0) /* negative stack adjustment? */ | |
1543 | frame_offset -= offset; | |
1544 | else | |
1545 | /* Exit loop if a positive stack adjustment is found, which | |
1546 | usually means that the stack cleanup code in the function | |
1547 | epilogue is reached. */ | |
1548 | break; | |
1549 | } | |
1550 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1551 | { | |
1552 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1553 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
74ed0bb4 | 1554 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1555 | } |
1556 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1557 | { | |
1558 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1559 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1560 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1561 | } |
1562 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1563 | { | |
1564 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 1565 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1566 | } |
1567 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1568 | { | |
1569 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 1570 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1571 | } |
1572 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1573 | { | |
1574 | frame_addr = sp; | |
1575 | frame_reg = 17; | |
1576 | } | |
1577 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1578 | { | |
1579 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1580 | frame_addr = sp + offset; | |
1581 | frame_reg = 17; | |
1582 | frame_adjust = offset; | |
1583 | } | |
1584 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1585 | { | |
1586 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1587 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1588 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1589 | } |
1590 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1591 | { | |
1592 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1593 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1594 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1595 | } |
1596 | else if ((inst & 0xf81f) == 0xe809 | |
1597 | && (inst & 0x700) != 0x700) /* entry */ | |
1598 | entry_inst = inst; /* save for later processing */ | |
2207132d MR |
1599 | else if ((inst & 0xff80) == 0x6480) /* save */ |
1600 | { | |
1601 | save_inst = inst; /* save for later processing */ | |
1602 | if (prev_extend_bytes) /* extend */ | |
1603 | save_inst |= prev_inst << 16; | |
1604 | } | |
29639122 | 1605 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
95ac2dcf | 1606 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1607 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1608 | { | |
1609 | /* This instruction is part of the prologue, but we don't | |
1610 | need to do anything special to handle it. */ | |
1611 | } | |
1612 | else | |
1613 | { | |
1614 | /* This instruction is not an instruction typically found | |
1615 | in a prologue, so we must have reached the end of the | |
1616 | prologue. */ | |
1617 | if (end_prologue_addr == 0) | |
1618 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1619 | } | |
1620 | } | |
eec63939 | 1621 | |
29639122 JB |
1622 | /* The entry instruction is typically the first instruction in a function, |
1623 | and it stores registers at offsets relative to the value of the old SP | |
1624 | (before the prologue). But the value of the sp parameter to this | |
1625 | function is the new SP (after the prologue has been executed). So we | |
1626 | can't calculate those offsets until we've seen the entire prologue, | |
1627 | and can calculate what the old SP must have been. */ | |
1628 | if (entry_inst != 0) | |
1629 | { | |
1630 | int areg_count = (entry_inst >> 8) & 7; | |
1631 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1632 | |
29639122 JB |
1633 | /* The entry instruction always subtracts 32 from the SP. */ |
1634 | frame_offset += 32; | |
1635 | ||
1636 | /* Now we can calculate what the SP must have been at the | |
1637 | start of the function prologue. */ | |
1638 | sp += frame_offset; | |
1639 | ||
1640 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1641 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1642 | { | |
74ed0bb4 | 1643 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1644 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
1645 | } |
1646 | ||
1647 | /* Check if the ra register was pushed on the stack. */ | |
1648 | offset = -4; | |
1649 | if (entry_inst & 0x20) | |
1650 | { | |
74ed0bb4 | 1651 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 1652 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1653 | } |
1654 | ||
1655 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1656 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1657 | { | |
74ed0bb4 | 1658 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1659 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1660 | } |
1661 | } | |
1662 | ||
2207132d MR |
1663 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
1664 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
1665 | size of the frame is specified as an immediate field of instruction | |
1666 | and an extended variation exists which lets additional registers and | |
1667 | frame space to be specified. The instruction always treats registers | |
1668 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
1669 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
1670 | { | |
1671 | static int args_table[16] = { | |
1672 | 0, 0, 0, 0, 1, 1, 1, 1, | |
1673 | 2, 2, 2, 0, 3, 3, 4, -1, | |
1674 | }; | |
1675 | static int astatic_table[16] = { | |
1676 | 0, 1, 2, 3, 0, 1, 2, 3, | |
1677 | 0, 1, 2, 4, 0, 1, 0, -1, | |
1678 | }; | |
1679 | int aregs = (save_inst >> 16) & 0xf; | |
1680 | int xsregs = (save_inst >> 24) & 0x7; | |
1681 | int args = args_table[aregs]; | |
1682 | int astatic = astatic_table[aregs]; | |
1683 | long frame_size; | |
1684 | ||
1685 | if (args < 0) | |
1686 | { | |
1687 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
1688 | args = 0; | |
1689 | } | |
1690 | if (astatic < 0) | |
1691 | { | |
1692 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
1693 | astatic = 0; | |
1694 | } | |
1695 | ||
1696 | /* For standard SAVE the frame size of 0 means 128. */ | |
1697 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
1698 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
1699 | frame_size = 16; | |
1700 | frame_size *= 8; | |
1701 | frame_offset += frame_size; | |
1702 | ||
1703 | /* Now we can calculate what the SP must have been at the | |
1704 | start of the function prologue. */ | |
1705 | sp += frame_offset; | |
1706 | ||
1707 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
1708 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
1709 | { | |
74ed0bb4 | 1710 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1711 | offset += mips_abi_regsize (gdbarch); |
1712 | } | |
1713 | ||
1714 | offset = -4; | |
1715 | ||
1716 | /* Check if the RA register was pushed on the stack. */ | |
1717 | if (save_inst & 0x40) | |
1718 | { | |
74ed0bb4 | 1719 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
1720 | offset -= mips_abi_regsize (gdbarch); |
1721 | } | |
1722 | ||
1723 | /* Check if the S8 register was pushed on the stack. */ | |
1724 | if (xsregs > 6) | |
1725 | { | |
74ed0bb4 | 1726 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
1727 | offset -= mips_abi_regsize (gdbarch); |
1728 | xsregs--; | |
1729 | } | |
1730 | /* Check if S2-S7 were pushed on the stack. */ | |
1731 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
1732 | { | |
74ed0bb4 | 1733 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1734 | offset -= mips_abi_regsize (gdbarch); |
1735 | } | |
1736 | ||
1737 | /* Check if the S1 register was pushed on the stack. */ | |
1738 | if (save_inst & 0x10) | |
1739 | { | |
74ed0bb4 | 1740 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
1741 | offset -= mips_abi_regsize (gdbarch); |
1742 | } | |
1743 | /* Check if the S0 register was pushed on the stack. */ | |
1744 | if (save_inst & 0x20) | |
1745 | { | |
74ed0bb4 | 1746 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
1747 | offset -= mips_abi_regsize (gdbarch); |
1748 | } | |
1749 | ||
1750 | /* Check if A0-A3 were pushed on the stack. */ | |
1751 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
1752 | { | |
74ed0bb4 | 1753 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1754 | offset -= mips_abi_regsize (gdbarch); |
1755 | } | |
1756 | } | |
1757 | ||
29639122 JB |
1758 | if (this_cache != NULL) |
1759 | { | |
1760 | this_cache->base = | |
b8a22b94 DJ |
1761 | (get_frame_register_signed (this_frame, |
1762 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
1763 | + frame_offset - frame_adjust); |
1764 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
1765 | be able to get rid of the assignment below, evetually. But it's | |
1766 | still needed for now. */ | |
72a155b4 UW |
1767 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
1768 | + mips_regnum (gdbarch)->pc] | |
1769 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
29639122 JB |
1770 | } |
1771 | ||
1772 | /* If we didn't reach the end of the prologue when scanning the function | |
1773 | instructions, then set end_prologue_addr to the address of the | |
1774 | instruction immediately after the last one we scanned. */ | |
1775 | if (end_prologue_addr == 0) | |
1776 | end_prologue_addr = cur_pc; | |
1777 | ||
1778 | return end_prologue_addr; | |
eec63939 AC |
1779 | } |
1780 | ||
29639122 JB |
1781 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1782 | Procedures that use the 32-bit instruction set are handled by the | |
1783 | mips_insn32 unwinder. */ | |
1784 | ||
1785 | static struct mips_frame_cache * | |
b8a22b94 | 1786 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 1787 | { |
e17a4113 | 1788 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 1789 | struct mips_frame_cache *cache; |
eec63939 AC |
1790 | |
1791 | if ((*this_cache) != NULL) | |
1792 | return (*this_cache); | |
29639122 JB |
1793 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1794 | (*this_cache) = cache; | |
b8a22b94 | 1795 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 1796 | |
29639122 JB |
1797 | /* Analyze the function prologue. */ |
1798 | { | |
b8a22b94 | 1799 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 1800 | CORE_ADDR start_addr; |
eec63939 | 1801 | |
29639122 JB |
1802 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1803 | if (start_addr == 0) | |
e17a4113 | 1804 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
1805 | /* We can't analyze the prologue if we couldn't find the begining |
1806 | of the function. */ | |
1807 | if (start_addr == 0) | |
1808 | return cache; | |
eec63939 | 1809 | |
e17a4113 | 1810 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
1811 | } |
1812 | ||
3e8c568d | 1813 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 | 1814 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 1815 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
72a155b4 | 1816 | cache->base); |
eec63939 | 1817 | |
29639122 | 1818 | return (*this_cache); |
eec63939 AC |
1819 | } |
1820 | ||
1821 | static void | |
b8a22b94 | 1822 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 1823 | struct frame_id *this_id) |
eec63939 | 1824 | { |
b8a22b94 | 1825 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 1826 | this_cache); |
21327321 DJ |
1827 | /* This marks the outermost frame. */ |
1828 | if (info->base == 0) | |
1829 | return; | |
b8a22b94 | 1830 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
1831 | } |
1832 | ||
b8a22b94 DJ |
1833 | static struct value * |
1834 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
1835 | void **this_cache, int regnum) | |
eec63939 | 1836 | { |
b8a22b94 | 1837 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 1838 | this_cache); |
b8a22b94 DJ |
1839 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
1840 | } | |
1841 | ||
1842 | static int | |
1843 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
1844 | struct frame_info *this_frame, void **this_cache) | |
1845 | { | |
1846 | CORE_ADDR pc = get_frame_pc (this_frame); | |
1847 | if (mips_pc_is_mips16 (pc)) | |
1848 | return 1; | |
1849 | return 0; | |
eec63939 AC |
1850 | } |
1851 | ||
29639122 | 1852 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
1853 | { |
1854 | NORMAL_FRAME, | |
29639122 | 1855 | mips_insn16_frame_this_id, |
b8a22b94 DJ |
1856 | mips_insn16_frame_prev_register, |
1857 | NULL, | |
1858 | mips_insn16_frame_sniffer | |
eec63939 AC |
1859 | }; |
1860 | ||
eec63939 | 1861 | static CORE_ADDR |
b8a22b94 | 1862 | mips_insn16_frame_base_address (struct frame_info *this_frame, |
29639122 | 1863 | void **this_cache) |
eec63939 | 1864 | { |
b8a22b94 | 1865 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 JB |
1866 | this_cache); |
1867 | return info->base; | |
eec63939 AC |
1868 | } |
1869 | ||
29639122 | 1870 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 1871 | { |
29639122 JB |
1872 | &mips_insn16_frame_unwind, |
1873 | mips_insn16_frame_base_address, | |
1874 | mips_insn16_frame_base_address, | |
1875 | mips_insn16_frame_base_address | |
eec63939 AC |
1876 | }; |
1877 | ||
1878 | static const struct frame_base * | |
b8a22b94 | 1879 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 1880 | { |
b8a22b94 DJ |
1881 | CORE_ADDR pc = get_frame_pc (this_frame); |
1882 | if (mips_pc_is_mips16 (pc)) | |
29639122 | 1883 | return &mips_insn16_frame_base; |
eec63939 AC |
1884 | else |
1885 | return NULL; | |
edfae063 AC |
1886 | } |
1887 | ||
29639122 JB |
1888 | /* Mark all the registers as unset in the saved_regs array |
1889 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
1890 | ||
74ed0bb4 MD |
1891 | static void |
1892 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 1893 | { |
29639122 JB |
1894 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
1895 | return; | |
1896 | ||
1897 | { | |
74ed0bb4 | 1898 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 1899 | int i; |
64159455 | 1900 | |
29639122 JB |
1901 | for (i = 0; i < num_regs; i++) |
1902 | { | |
1903 | this_cache->saved_regs[i].addr = -1; | |
1904 | } | |
1905 | } | |
c906108c SS |
1906 | } |
1907 | ||
29639122 JB |
1908 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1909 | the associated FRAME_CACHE if not null. | |
1910 | Return the address of the first instruction past the prologue. */ | |
c906108c | 1911 | |
875e1767 | 1912 | static CORE_ADDR |
e17a4113 UW |
1913 | mips32_scan_prologue (struct gdbarch *gdbarch, |
1914 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 1915 | struct frame_info *this_frame, |
29639122 | 1916 | struct mips_frame_cache *this_cache) |
c906108c | 1917 | { |
29639122 JB |
1918 | CORE_ADDR cur_pc; |
1919 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
1920 | CORE_ADDR sp; | |
1921 | long frame_offset; | |
1922 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 1923 | |
29639122 JB |
1924 | CORE_ADDR end_prologue_addr = 0; |
1925 | int seen_sp_adjust = 0; | |
1926 | int load_immediate_bytes = 0; | |
db5f024e | 1927 | int in_delay_slot = 0; |
7d1e6fb8 | 1928 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 1929 | |
29639122 | 1930 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
1931 | THIS_FRAME. */ |
1932 | if (this_frame != NULL) | |
1933 | sp = get_frame_register_signed (this_frame, | |
1934 | gdbarch_num_regs (gdbarch) | |
1935 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 1936 | else |
29639122 | 1937 | sp = 0; |
9022177c | 1938 | |
29639122 JB |
1939 | if (limit_pc > start_pc + 200) |
1940 | limit_pc = start_pc + 200; | |
9022177c | 1941 | |
29639122 | 1942 | restart: |
9022177c | 1943 | |
29639122 | 1944 | frame_offset = 0; |
95ac2dcf | 1945 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 1946 | { |
29639122 JB |
1947 | unsigned long inst, high_word, low_word; |
1948 | int reg; | |
9022177c | 1949 | |
29639122 | 1950 | /* Fetch the instruction. */ |
e17a4113 | 1951 | inst = (unsigned long) mips_fetch_instruction (gdbarch, cur_pc); |
9022177c | 1952 | |
29639122 JB |
1953 | /* Save some code by pre-extracting some useful fields. */ |
1954 | high_word = (inst >> 16) & 0xffff; | |
1955 | low_word = inst & 0xffff; | |
1956 | reg = high_word & 0x1f; | |
fe29b929 | 1957 | |
29639122 JB |
1958 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
1959 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
1960 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1961 | { | |
1962 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
1963 | frame_offset += 0x10000 - low_word; | |
1964 | else | |
1965 | /* Exit loop if a positive stack adjustment is found, which | |
1966 | usually means that the stack cleanup code in the function | |
1967 | epilogue is reached. */ | |
1968 | break; | |
1969 | seen_sp_adjust = 1; | |
1970 | } | |
7d1e6fb8 KB |
1971 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
1972 | && !regsize_is_64_bits) | |
29639122 | 1973 | { |
74ed0bb4 | 1974 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 | 1975 | } |
7d1e6fb8 KB |
1976 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
1977 | && regsize_is_64_bits) | |
29639122 JB |
1978 | { |
1979 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
74ed0bb4 | 1980 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 JB |
1981 | } |
1982 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
1983 | { | |
1984 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
1985 | if ((long) low_word != frame_offset) | |
1986 | frame_addr = sp + low_word; | |
b8a22b94 | 1987 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
1988 | { |
1989 | unsigned alloca_adjust; | |
a4b8ebc8 | 1990 | |
29639122 | 1991 | frame_reg = 30; |
b8a22b94 DJ |
1992 | frame_addr = get_frame_register_signed |
1993 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 1994 | |
29639122 JB |
1995 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
1996 | if (alloca_adjust > 0) | |
1997 | { | |
1998 | /* FP > SP + frame_size. This may be because of | |
1999 | an alloca or somethings similar. Fix sp to | |
2000 | "pre-alloca" value, and try again. */ | |
2001 | sp += alloca_adjust; | |
2002 | /* Need to reset the status of all registers. Otherwise, | |
2003 | we will hit a guard that prevents the new address | |
2004 | for each register to be recomputed during the second | |
2005 | pass. */ | |
74ed0bb4 | 2006 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2007 | goto restart; |
2008 | } | |
2009 | } | |
2010 | } | |
2011 | /* move $30,$sp. With different versions of gas this will be either | |
2012 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2013 | Accept any one of these. */ | |
2014 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
2015 | { | |
2016 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 2017 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
2018 | { |
2019 | unsigned alloca_adjust; | |
c906108c | 2020 | |
29639122 | 2021 | frame_reg = 30; |
b8a22b94 DJ |
2022 | frame_addr = get_frame_register_signed |
2023 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 2024 | |
29639122 JB |
2025 | alloca_adjust = (unsigned) (frame_addr - sp); |
2026 | if (alloca_adjust > 0) | |
2027 | { | |
2028 | /* FP > SP + frame_size. This may be because of | |
2029 | an alloca or somethings similar. Fix sp to | |
2030 | "pre-alloca" value, and try again. */ | |
2031 | sp = frame_addr; | |
2032 | /* Need to reset the status of all registers. Otherwise, | |
2033 | we will hit a guard that prevents the new address | |
2034 | for each register to be recomputed during the second | |
2035 | pass. */ | |
74ed0bb4 | 2036 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2037 | goto restart; |
2038 | } | |
2039 | } | |
2040 | } | |
7d1e6fb8 KB |
2041 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
2042 | && !regsize_is_64_bits) | |
29639122 | 2043 | { |
74ed0bb4 | 2044 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word); |
29639122 JB |
2045 | } |
2046 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
2047 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
2048 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
2049 | || high_word == 0x3c1c /* lui $gp,n */ | |
2050 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
2051 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
2052 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
2053 | ) | |
2054 | { | |
2055 | /* These instructions are part of the prologue, but we don't | |
2056 | need to do anything special to handle them. */ | |
2057 | } | |
2058 | /* The instructions below load $at or $t0 with an immediate | |
2059 | value in preparation for a stack adjustment via | |
2060 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
2061 | initialize a local variable, so we accept them only before | |
2062 | a stack adjustment instruction was seen. */ | |
2063 | else if (!seen_sp_adjust | |
2064 | && (high_word == 0x3c01 /* lui $at,n */ | |
2065 | || high_word == 0x3c08 /* lui $t0,n */ | |
2066 | || high_word == 0x3421 /* ori $at,$at,n */ | |
2067 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
2068 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
2069 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
2070 | )) | |
2071 | { | |
95ac2dcf | 2072 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
29639122 JB |
2073 | } |
2074 | else | |
2075 | { | |
2076 | /* This instruction is not an instruction typically found | |
2077 | in a prologue, so we must have reached the end of the | |
2078 | prologue. */ | |
2079 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
2080 | loop now? Why would we need to continue scanning the function | |
2081 | instructions? */ | |
2082 | if (end_prologue_addr == 0) | |
2083 | end_prologue_addr = cur_pc; | |
db5f024e DJ |
2084 | |
2085 | /* Check for branches and jumps. For now, only jump to | |
2086 | register are caught (i.e. returns). */ | |
2087 | if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8) | |
2088 | in_delay_slot = 1; | |
29639122 | 2089 | } |
db5f024e DJ |
2090 | |
2091 | /* If the previous instruction was a jump, we must have reached | |
2092 | the end of the prologue by now. Stop scanning so that we do | |
2093 | not go past the function return. */ | |
2094 | if (in_delay_slot) | |
2095 | break; | |
a4b8ebc8 | 2096 | } |
c906108c | 2097 | |
29639122 JB |
2098 | if (this_cache != NULL) |
2099 | { | |
2100 | this_cache->base = | |
b8a22b94 DJ |
2101 | (get_frame_register_signed (this_frame, |
2102 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
2103 | + frame_offset); |
2104 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2105 | this assignment below, eventually. But it's still needed | |
2106 | for now. */ | |
72a155b4 UW |
2107 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
2108 | + mips_regnum (gdbarch)->pc] | |
2109 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 2110 | + MIPS_RA_REGNUM]; |
29639122 | 2111 | } |
c906108c | 2112 | |
29639122 JB |
2113 | /* If we didn't reach the end of the prologue when scanning the function |
2114 | instructions, then set end_prologue_addr to the address of the | |
2115 | instruction immediately after the last one we scanned. */ | |
2116 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2117 | we may as well be careful and do our best if we have a null | |
2118 | end_prologue_addr. */ | |
2119 | if (end_prologue_addr == 0) | |
2120 | end_prologue_addr = cur_pc; | |
2121 | ||
2122 | /* In a frameless function, we might have incorrectly | |
2123 | skipped some load immediate instructions. Undo the skipping | |
2124 | if the load immediate was not followed by a stack adjustment. */ | |
2125 | if (load_immediate_bytes && !seen_sp_adjust) | |
2126 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2127 | |
29639122 | 2128 | return end_prologue_addr; |
c906108c SS |
2129 | } |
2130 | ||
29639122 JB |
2131 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2132 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2133 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2134 | unwinder. */ | |
c906108c | 2135 | |
29639122 | 2136 | static struct mips_frame_cache * |
b8a22b94 | 2137 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 2138 | { |
e17a4113 | 2139 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 2140 | struct mips_frame_cache *cache; |
c906108c | 2141 | |
29639122 JB |
2142 | if ((*this_cache) != NULL) |
2143 | return (*this_cache); | |
c5aa993b | 2144 | |
29639122 JB |
2145 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2146 | (*this_cache) = cache; | |
b8a22b94 | 2147 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 2148 | |
29639122 JB |
2149 | /* Analyze the function prologue. */ |
2150 | { | |
b8a22b94 | 2151 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 2152 | CORE_ADDR start_addr; |
c906108c | 2153 | |
29639122 JB |
2154 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2155 | if (start_addr == 0) | |
e17a4113 | 2156 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
2157 | /* We can't analyze the prologue if we couldn't find the begining |
2158 | of the function. */ | |
2159 | if (start_addr == 0) | |
2160 | return cache; | |
c5aa993b | 2161 | |
e17a4113 | 2162 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
2163 | } |
2164 | ||
3e8c568d | 2165 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 2166 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 2167 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
f57d151a | 2168 | cache->base); |
c5aa993b | 2169 | |
29639122 | 2170 | return (*this_cache); |
c906108c SS |
2171 | } |
2172 | ||
29639122 | 2173 | static void |
b8a22b94 | 2174 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 2175 | struct frame_id *this_id) |
c906108c | 2176 | { |
b8a22b94 | 2177 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2178 | this_cache); |
21327321 DJ |
2179 | /* This marks the outermost frame. */ |
2180 | if (info->base == 0) | |
2181 | return; | |
b8a22b94 | 2182 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 2183 | } |
c906108c | 2184 | |
b8a22b94 DJ |
2185 | static struct value * |
2186 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
2187 | void **this_cache, int regnum) | |
29639122 | 2188 | { |
b8a22b94 | 2189 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2190 | this_cache); |
b8a22b94 DJ |
2191 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
2192 | } | |
2193 | ||
2194 | static int | |
2195 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
2196 | struct frame_info *this_frame, void **this_cache) | |
2197 | { | |
2198 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2199 | if (! mips_pc_is_mips16 (pc)) | |
2200 | return 1; | |
2201 | return 0; | |
c906108c SS |
2202 | } |
2203 | ||
29639122 JB |
2204 | static const struct frame_unwind mips_insn32_frame_unwind = |
2205 | { | |
2206 | NORMAL_FRAME, | |
2207 | mips_insn32_frame_this_id, | |
b8a22b94 DJ |
2208 | mips_insn32_frame_prev_register, |
2209 | NULL, | |
2210 | mips_insn32_frame_sniffer | |
29639122 | 2211 | }; |
c906108c | 2212 | |
1c645fec | 2213 | static CORE_ADDR |
b8a22b94 | 2214 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 2215 | void **this_cache) |
c906108c | 2216 | { |
b8a22b94 | 2217 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
2218 | this_cache); |
2219 | return info->base; | |
2220 | } | |
c906108c | 2221 | |
29639122 JB |
2222 | static const struct frame_base mips_insn32_frame_base = |
2223 | { | |
2224 | &mips_insn32_frame_unwind, | |
2225 | mips_insn32_frame_base_address, | |
2226 | mips_insn32_frame_base_address, | |
2227 | mips_insn32_frame_base_address | |
2228 | }; | |
1c645fec | 2229 | |
29639122 | 2230 | static const struct frame_base * |
b8a22b94 | 2231 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2232 | { |
b8a22b94 DJ |
2233 | CORE_ADDR pc = get_frame_pc (this_frame); |
2234 | if (! mips_pc_is_mips16 (pc)) | |
29639122 | 2235 | return &mips_insn32_frame_base; |
a65bbe44 | 2236 | else |
29639122 JB |
2237 | return NULL; |
2238 | } | |
a65bbe44 | 2239 | |
29639122 | 2240 | static struct trad_frame_cache * |
b8a22b94 | 2241 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
2242 | { |
2243 | CORE_ADDR pc; | |
2244 | CORE_ADDR start_addr; | |
2245 | CORE_ADDR stack_addr; | |
2246 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
2247 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2248 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 2249 | |
29639122 JB |
2250 | if ((*this_cache) != NULL) |
2251 | return (*this_cache); | |
b8a22b94 | 2252 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 2253 | (*this_cache) = this_trad_cache; |
1c645fec | 2254 | |
29639122 | 2255 | /* The return address is in the link register. */ |
3e8c568d | 2256 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 2257 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 2258 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 2259 | |
29639122 JB |
2260 | /* Frame ID, since it's a frameless / stackless function, no stack |
2261 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 2262 | pc = get_frame_pc (this_frame); |
29639122 | 2263 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
2264 | stack_addr = get_frame_register_signed (this_frame, |
2265 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 2266 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 2267 | |
29639122 JB |
2268 | /* Assume that the frame's base is the same as the |
2269 | stack-pointer. */ | |
2270 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2271 | |
29639122 JB |
2272 | return this_trad_cache; |
2273 | } | |
c906108c | 2274 | |
29639122 | 2275 | static void |
b8a22b94 | 2276 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
2277 | struct frame_id *this_id) |
2278 | { | |
2279 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2280 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2281 | trad_frame_get_id (this_trad_cache, this_id); |
2282 | } | |
c906108c | 2283 | |
b8a22b94 DJ |
2284 | static struct value * |
2285 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
2286 | void **this_cache, int regnum) | |
29639122 JB |
2287 | { |
2288 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
2289 | = mips_stub_frame_cache (this_frame, this_cache); |
2290 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 2291 | } |
c906108c | 2292 | |
b8a22b94 DJ |
2293 | static int |
2294 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
2295 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 2296 | { |
aa6c981f | 2297 | gdb_byte dummy[4]; |
979b38e0 | 2298 | struct obj_section *s; |
b8a22b94 | 2299 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
db5f024e | 2300 | struct minimal_symbol *msym; |
979b38e0 | 2301 | |
aa6c981f | 2302 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
2303 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
2304 | return 1; | |
aa6c981f | 2305 | |
29639122 | 2306 | if (in_plt_section (pc, NULL)) |
b8a22b94 | 2307 | return 1; |
979b38e0 DJ |
2308 | |
2309 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2310 | s = find_pc_section (pc); | |
2311 | ||
2312 | if (s != NULL | |
2313 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2314 | ".MIPS.stubs") == 0) | |
b8a22b94 | 2315 | return 1; |
979b38e0 | 2316 | |
db5f024e DJ |
2317 | /* Calling a PIC function from a non-PIC function passes through a |
2318 | stub. The stub for foo is named ".pic.foo". */ | |
2319 | msym = lookup_minimal_symbol_by_pc (pc); | |
2320 | if (msym != NULL | |
2321 | && SYMBOL_LINKAGE_NAME (msym) != NULL | |
2322 | && strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) == 0) | |
2323 | return 1; | |
2324 | ||
b8a22b94 | 2325 | return 0; |
29639122 | 2326 | } |
c906108c | 2327 | |
b8a22b94 DJ |
2328 | static const struct frame_unwind mips_stub_frame_unwind = |
2329 | { | |
2330 | NORMAL_FRAME, | |
2331 | mips_stub_frame_this_id, | |
2332 | mips_stub_frame_prev_register, | |
2333 | NULL, | |
2334 | mips_stub_frame_sniffer | |
2335 | }; | |
2336 | ||
29639122 | 2337 | static CORE_ADDR |
b8a22b94 | 2338 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
2339 | void **this_cache) |
2340 | { | |
2341 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2342 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2343 | return trad_frame_get_this_base (this_trad_cache); |
2344 | } | |
0fce0821 | 2345 | |
29639122 JB |
2346 | static const struct frame_base mips_stub_frame_base = |
2347 | { | |
2348 | &mips_stub_frame_unwind, | |
2349 | mips_stub_frame_base_address, | |
2350 | mips_stub_frame_base_address, | |
2351 | mips_stub_frame_base_address | |
2352 | }; | |
2353 | ||
2354 | static const struct frame_base * | |
b8a22b94 | 2355 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2356 | { |
b8a22b94 | 2357 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
2358 | return &mips_stub_frame_base; |
2359 | else | |
2360 | return NULL; | |
2361 | } | |
2362 | ||
29639122 | 2363 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2364 | |
29639122 | 2365 | static CORE_ADDR |
24568a2c | 2366 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 2367 | { |
24568a2c | 2368 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
29639122 JB |
2369 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
2370 | /* This hack is a work-around for existing boards using PMON, the | |
2371 | simulator, and any other 64-bit targets that doesn't have true | |
2372 | 64-bit addressing. On these targets, the upper 32 bits of | |
2373 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2374 | likely to have been sign extended to all 1s by instruction | |
2375 | sequences that load 32-bit addresses. For example, a typical | |
2376 | piece of code that loads an address is this: | |
65596487 | 2377 | |
29639122 JB |
2378 | lui $r2, <upper 16 bits> |
2379 | ori $r2, <lower 16 bits> | |
65596487 | 2380 | |
29639122 JB |
2381 | But the lui sign-extends the value such that the upper 32 bits |
2382 | may be all 1s. The workaround is simply to mask off these | |
2383 | bits. In the future, gcc may be changed to support true 64-bit | |
2384 | addressing, and this masking will have to be disabled. */ | |
2385 | return addr &= 0xffffffffUL; | |
2386 | else | |
2387 | return addr; | |
65596487 JB |
2388 | } |
2389 | ||
3d5f6d12 DJ |
2390 | /* Instructions used during single-stepping of atomic sequences. */ |
2391 | #define LL_OPCODE 0x30 | |
2392 | #define LLD_OPCODE 0x34 | |
2393 | #define SC_OPCODE 0x38 | |
2394 | #define SCD_OPCODE 0x3c | |
2395 | ||
2396 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
2397 | instruction and ending with a SC/SCD instruction. If such a sequence | |
2398 | is found, attempt to step through it. A breakpoint is placed at the end of | |
2399 | the sequence. */ | |
2400 | ||
2401 | static int | |
6c95b8df PA |
2402 | deal_with_atomic_sequence (struct gdbarch *gdbarch, |
2403 | struct address_space *aspace, CORE_ADDR pc) | |
3d5f6d12 DJ |
2404 | { |
2405 | CORE_ADDR breaks[2] = {-1, -1}; | |
2406 | CORE_ADDR loc = pc; | |
2407 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
2408 | unsigned long insn; | |
2409 | int insn_count; | |
2410 | int index; | |
2411 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
2412 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
2413 | ||
2414 | if (pc & 0x01) | |
2415 | return 0; | |
2416 | ||
e17a4113 | 2417 | insn = mips_fetch_instruction (gdbarch, loc); |
3d5f6d12 DJ |
2418 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
2419 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
2420 | return 0; | |
2421 | ||
2422 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
2423 | instructions. */ | |
2424 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
2425 | { | |
2426 | int is_branch = 0; | |
2427 | loc += MIPS_INSN32_SIZE; | |
e17a4113 | 2428 | insn = mips_fetch_instruction (gdbarch, loc); |
3d5f6d12 DJ |
2429 | |
2430 | /* Assume that there is at most one branch in the atomic | |
2431 | sequence. If a branch is found, put a breakpoint in its | |
2432 | destination address. */ | |
2433 | switch (itype_op (insn)) | |
2434 | { | |
2435 | case 0: /* SPECIAL */ | |
2436 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
2437 | return 0; /* fallback to the standard single-step code. */ | |
2438 | break; | |
2439 | case 1: /* REGIMM */ | |
2440 | is_branch = ((itype_rt (insn) & 0xc0) == 0); /* B{LT,GE}Z* */ | |
2441 | break; | |
2442 | case 2: /* J */ | |
2443 | case 3: /* JAL */ | |
2444 | return 0; /* fallback to the standard single-step code. */ | |
2445 | case 4: /* BEQ */ | |
2446 | case 5: /* BNE */ | |
2447 | case 6: /* BLEZ */ | |
2448 | case 7: /* BGTZ */ | |
2449 | case 20: /* BEQL */ | |
2450 | case 21: /* BNEL */ | |
2451 | case 22: /* BLEZL */ | |
2452 | case 23: /* BGTTL */ | |
2453 | is_branch = 1; | |
2454 | break; | |
2455 | case 17: /* COP1 */ | |
2456 | case 18: /* COP2 */ | |
2457 | case 19: /* COP3 */ | |
2458 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
2459 | break; | |
2460 | } | |
2461 | if (is_branch) | |
2462 | { | |
2463 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
2464 | if (last_breakpoint >= 1) | |
2465 | return 0; /* More than one branch found, fallback to the | |
2466 | standard single-step code. */ | |
2467 | breaks[1] = branch_bp; | |
2468 | last_breakpoint++; | |
2469 | } | |
2470 | ||
2471 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
2472 | break; | |
2473 | } | |
2474 | ||
2475 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
2476 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
2477 | return 0; | |
2478 | ||
2479 | loc += MIPS_INSN32_SIZE; | |
2480 | ||
2481 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
2482 | breaks[0] = loc; | |
2483 | ||
2484 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
2485 | placed (branch instruction's destination) in the atomic sequence */ | |
2486 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) | |
2487 | last_breakpoint = 0; | |
2488 | ||
2489 | /* Effectively inserts the breakpoints. */ | |
2490 | for (index = 0; index <= last_breakpoint; index++) | |
6c95b8df | 2491 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
3d5f6d12 DJ |
2492 | |
2493 | return 1; | |
2494 | } | |
2495 | ||
29639122 JB |
2496 | /* mips_software_single_step() is called just before we want to resume |
2497 | the inferior, if we want to single-step it but there is no hardware | |
2498 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 2499 | the target of the coming instruction and breakpoint it. */ |
29639122 | 2500 | |
e6590a1b | 2501 | int |
0b1b3e42 | 2502 | mips_software_single_step (struct frame_info *frame) |
c906108c | 2503 | { |
a6d9a66e | 2504 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6c95b8df | 2505 | struct address_space *aspace = get_frame_address_space (frame); |
8181d85f | 2506 | CORE_ADDR pc, next_pc; |
65596487 | 2507 | |
0b1b3e42 | 2508 | pc = get_frame_pc (frame); |
6c95b8df | 2509 | if (deal_with_atomic_sequence (gdbarch, aspace, pc)) |
3d5f6d12 DJ |
2510 | return 1; |
2511 | ||
0b1b3e42 | 2512 | next_pc = mips_next_pc (frame, pc); |
e6590a1b | 2513 | |
6c95b8df | 2514 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
e6590a1b | 2515 | return 1; |
29639122 | 2516 | } |
a65bbe44 | 2517 | |
29639122 JB |
2518 | /* Test whether the PC points to the return instruction at the |
2519 | end of a function. */ | |
65596487 | 2520 | |
29639122 | 2521 | static int |
e17a4113 | 2522 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 | 2523 | { |
0fe7e7c8 | 2524 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2525 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2526 | generates a "jr $ra"; other times it generates code to load | |
2527 | the return address from the stack to an accessible register (such | |
2528 | as $a3), then a "jr" using that register. This second case | |
2529 | is almost impossible to distinguish from an indirect jump | |
2530 | used for switch statements, so we don't even try. */ | |
e17a4113 | 2531 | return mips_fetch_instruction (gdbarch, pc) == 0xe820; /* jr $ra */ |
29639122 | 2532 | else |
e17a4113 | 2533 | return mips_fetch_instruction (gdbarch, pc) == 0x3e00008; /* jr $ra */ |
29639122 | 2534 | } |
c906108c | 2535 | |
c906108c | 2536 | |
29639122 JB |
2537 | /* This fencepost looks highly suspicious to me. Removing it also |
2538 | seems suspicious as it could affect remote debugging across serial | |
2539 | lines. */ | |
c906108c | 2540 | |
29639122 | 2541 | static CORE_ADDR |
74ed0bb4 | 2542 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
2543 | { |
2544 | CORE_ADDR start_pc; | |
2545 | CORE_ADDR fence; | |
2546 | int instlen; | |
2547 | int seen_adjsp = 0; | |
d6b48e9c | 2548 | struct inferior *inf; |
65596487 | 2549 | |
74ed0bb4 | 2550 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
2551 | start_pc = pc; |
2552 | fence = start_pc - heuristic_fence_post; | |
2553 | if (start_pc == 0) | |
2554 | return 0; | |
65596487 | 2555 | |
29639122 JB |
2556 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2557 | fence = VM_MIN_ADDRESS; | |
65596487 | 2558 | |
95ac2dcf | 2559 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2560 | |
d6b48e9c PA |
2561 | inf = current_inferior (); |
2562 | ||
29639122 JB |
2563 | /* search back for previous return */ |
2564 | for (start_pc -= instlen;; start_pc -= instlen) | |
2565 | if (start_pc < fence) | |
2566 | { | |
2567 | /* It's not clear to me why we reach this point when | |
2568 | stop_soon, but with this test, at least we | |
2569 | don't print out warnings for every child forked (eg, on | |
2570 | decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 2571 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
2572 | { |
2573 | static int blurb_printed = 0; | |
98b4dd94 | 2574 | |
5af949e3 UW |
2575 | warning (_("GDB can't find the start of the function at %s."), |
2576 | paddress (gdbarch, pc)); | |
29639122 JB |
2577 | |
2578 | if (!blurb_printed) | |
2579 | { | |
2580 | /* This actually happens frequently in embedded | |
2581 | development, when you first connect to a board | |
2582 | and your stack pointer and pc are nowhere in | |
2583 | particular. This message needs to give people | |
2584 | in that situation enough information to | |
2585 | determine that it's no big deal. */ | |
2586 | printf_filtered ("\n\ | |
5af949e3 | 2587 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
2588 | and thus can't determine the size of that function's stack frame.\n\ |
2589 | This means that GDB may be unable to access that stack frame, or\n\ | |
2590 | the frames below it.\n\ | |
2591 | This problem is most likely caused by an invalid program counter or\n\ | |
2592 | stack pointer.\n\ | |
2593 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 2594 | from %s for code which looks like the beginning of a\n\ |
29639122 | 2595 | function, you can increase the range of the search using the `set\n\ |
5af949e3 UW |
2596 | heuristic-fence-post' command.\n", |
2597 | paddress (gdbarch, pc), paddress (gdbarch, pc)); | |
29639122 JB |
2598 | blurb_printed = 1; |
2599 | } | |
2600 | } | |
2601 | ||
2602 | return 0; | |
2603 | } | |
0fe7e7c8 | 2604 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2605 | { |
2606 | unsigned short inst; | |
2607 | ||
2608 | /* On MIPS16, any one of the following is likely to be the | |
2609 | start of a function: | |
193774b3 MR |
2610 | extend save |
2611 | save | |
29639122 JB |
2612 | entry |
2613 | addiu sp,-n | |
2614 | daddiu sp,-n | |
2615 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
e17a4113 | 2616 | inst = mips_fetch_instruction (gdbarch, start_pc); |
193774b3 MR |
2617 | if ((inst & 0xff80) == 0x6480) /* save */ |
2618 | { | |
2619 | if (start_pc - instlen >= fence) | |
2620 | { | |
e17a4113 | 2621 | inst = mips_fetch_instruction (gdbarch, start_pc - instlen); |
193774b3 MR |
2622 | if ((inst & 0xf800) == 0xf000) /* extend */ |
2623 | start_pc -= instlen; | |
2624 | } | |
2625 | break; | |
2626 | } | |
2627 | else if (((inst & 0xf81f) == 0xe809 | |
2628 | && (inst & 0x700) != 0x700) /* entry */ | |
2629 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2630 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2631 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
2632 | break; |
2633 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2634 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2635 | seen_adjsp = 1; | |
2636 | else | |
2637 | seen_adjsp = 0; | |
2638 | } | |
e17a4113 | 2639 | else if (mips_about_to_return (gdbarch, start_pc)) |
29639122 | 2640 | { |
4c7d22cb | 2641 | /* Skip return and its delay slot. */ |
95ac2dcf | 2642 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2643 | break; |
2644 | } | |
2645 | ||
2646 | return start_pc; | |
c906108c SS |
2647 | } |
2648 | ||
6c0d6680 DJ |
2649 | struct mips_objfile_private |
2650 | { | |
2651 | bfd_size_type size; | |
2652 | char *contents; | |
2653 | }; | |
2654 | ||
f09ded24 AC |
2655 | /* According to the current ABI, should the type be passed in a |
2656 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 2657 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 AC |
2658 | FP registers and, consequently this returns false - forces FP |
2659 | arguments into integer registers. */ | |
2660 | ||
2661 | static int | |
74ed0bb4 MD |
2662 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
2663 | struct type *arg_type) | |
f09ded24 AC |
2664 | { |
2665 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 2666 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
2667 | && (typecode == TYPE_CODE_STRUCT |
2668 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 2669 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
2670 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
2671 | == TYPE_CODE_FLT)) | |
74ed0bb4 | 2672 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
2673 | } |
2674 | ||
49e790b0 DJ |
2675 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2676 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2677 | ||
2678 | static int | |
2679 | mips_type_needs_double_align (struct type *type) | |
2680 | { | |
2681 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2682 | |
49e790b0 DJ |
2683 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2684 | return 1; | |
2685 | else if (typecode == TYPE_CODE_STRUCT) | |
2686 | { | |
2687 | if (TYPE_NFIELDS (type) < 1) | |
2688 | return 0; | |
2689 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2690 | } | |
2691 | else if (typecode == TYPE_CODE_UNION) | |
2692 | { | |
361d1df0 | 2693 | int i, n; |
49e790b0 DJ |
2694 | |
2695 | n = TYPE_NFIELDS (type); | |
2696 | for (i = 0; i < n; i++) | |
2697 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2698 | return 1; | |
2699 | return 0; | |
2700 | } | |
2701 | return 0; | |
2702 | } | |
2703 | ||
dc604539 AC |
2704 | /* Adjust the address downward (direction of stack growth) so that it |
2705 | is correctly aligned for a new stack frame. */ | |
2706 | static CORE_ADDR | |
2707 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2708 | { | |
5b03f266 | 2709 | return align_down (addr, 16); |
dc604539 AC |
2710 | } |
2711 | ||
f7ab6ec6 | 2712 | static CORE_ADDR |
7d9b040b | 2713 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2714 | struct regcache *regcache, CORE_ADDR bp_addr, |
2715 | int nargs, struct value **args, CORE_ADDR sp, | |
2716 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2717 | { |
2718 | int argreg; | |
2719 | int float_argreg; | |
2720 | int argnum; | |
2721 | int len = 0; | |
2722 | int stack_offset = 0; | |
480d3dd2 | 2723 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 2724 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 2725 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 2726 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 2727 | |
25ab4790 AC |
2728 | /* For shared libraries, "t9" needs to point at the function |
2729 | address. */ | |
4c7d22cb | 2730 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2731 | |
2732 | /* Set the return address register to point to the entry point of | |
2733 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2734 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2735 | |
c906108c | 2736 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2737 | are properly aligned. The stack has to be at least 64-bit |
2738 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2739 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2740 | aligned, so we round to this widest known alignment. */ | |
2741 | ||
5b03f266 AC |
2742 | sp = align_down (sp, 16); |
2743 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2744 | |
46e0f506 | 2745 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2746 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2747 | passed in registers, but that's OK. */ |
c906108c | 2748 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 2749 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 2750 | sp -= align_up (len, 16); |
c906108c | 2751 | |
9ace0497 | 2752 | if (mips_debug) |
6d82d43b | 2753 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
2754 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
2755 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
9ace0497 | 2756 | |
c906108c | 2757 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2758 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 2759 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 2760 | |
46e0f506 | 2761 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2762 | if (struct_return) |
9ace0497 AC |
2763 | { |
2764 | if (mips_debug) | |
2765 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
2766 | "mips_eabi_push_dummy_call: struct_return reg=%d %s\n", |
2767 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 2768 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 2769 | } |
c906108c SS |
2770 | |
2771 | /* Now load as many as possible of the first arguments into | |
2772 | registers, and push the rest onto the stack. Loop thru args | |
2773 | from first to last. */ | |
2774 | for (argnum = 0; argnum < nargs; argnum++) | |
2775 | { | |
47a35522 MK |
2776 | const gdb_byte *val; |
2777 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 2778 | struct value *arg = args[argnum]; |
4991999e | 2779 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
2780 | int len = TYPE_LENGTH (arg_type); |
2781 | enum type_code typecode = TYPE_CODE (arg_type); | |
2782 | ||
9ace0497 AC |
2783 | if (mips_debug) |
2784 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2785 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2786 | argnum + 1, len, (int) typecode); |
9ace0497 | 2787 | |
c906108c | 2788 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2789 | reference. */ |
1a69e1e4 | 2790 | if (len > regsize |
9ace0497 | 2791 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2792 | { |
e17a4113 UW |
2793 | store_unsigned_integer (valbuf, regsize, byte_order, |
2794 | value_address (arg)); | |
c906108c | 2795 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 2796 | len = regsize; |
c906108c | 2797 | val = valbuf; |
9ace0497 AC |
2798 | if (mips_debug) |
2799 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2800 | } |
2801 | else | |
47a35522 | 2802 | val = value_contents (arg); |
c906108c SS |
2803 | |
2804 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2805 | even-numbered floating point register. Round the FP register |
2806 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2807 | left. Non MIPS_EABI targets also pass the FP in the integer |
2808 | registers so also round up normal registers. */ | |
74ed0bb4 | 2809 | if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
2810 | { |
2811 | if ((float_argreg & 1)) | |
2812 | float_argreg++; | |
2813 | } | |
c906108c SS |
2814 | |
2815 | /* Floating point arguments passed in registers have to be | |
2816 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2817 | are passed in register pairs; the even register gets |
2818 | the low word, and the odd register gets the high word. | |
2819 | On non-EABI processors, the first two floating point arguments are | |
2820 | also copied to general registers, because MIPS16 functions | |
2821 | don't use float registers for arguments. This duplication of | |
2822 | arguments in general registers can't hurt non-MIPS16 functions | |
2823 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2824 | /* MIPS_EABI squeezes a struct that contains a single floating |
2825 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2826 | stack. */ |
74ed0bb4 MD |
2827 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
2828 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 2829 | { |
6da397e0 KB |
2830 | /* EABI32 will pass doubles in consecutive registers, even on |
2831 | 64-bit cores. At one time, we used to check the size of | |
2832 | `float_argreg' to determine whether or not to pass doubles | |
2833 | in consecutive registers, but this is not sufficient for | |
2834 | making the ABI determination. */ | |
2835 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 2836 | { |
72a155b4 | 2837 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 2838 | == BFD_ENDIAN_BIG ? 4 : 0; |
a8852dc5 | 2839 | long regval; |
c906108c SS |
2840 | |
2841 | /* Write the low word of the double to the even register(s). */ | |
a8852dc5 KB |
2842 | regval = extract_signed_integer (val + low_offset, |
2843 | 4, byte_order); | |
9ace0497 | 2844 | if (mips_debug) |
acdb74a0 | 2845 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2846 | float_argreg, phex (regval, 4)); |
a8852dc5 | 2847 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
2848 | |
2849 | /* Write the high word of the double to the odd register(s). */ | |
a8852dc5 KB |
2850 | regval = extract_signed_integer (val + 4 - low_offset, |
2851 | 4, byte_order); | |
9ace0497 | 2852 | if (mips_debug) |
acdb74a0 | 2853 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2854 | float_argreg, phex (regval, 4)); |
a8852dc5 | 2855 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
2856 | } |
2857 | else | |
2858 | { | |
2859 | /* This is a floating point value that fits entirely | |
2860 | in a single register. */ | |
53a5351d | 2861 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 2862 | above to ensure that it is even register aligned. */ |
a8852dc5 | 2863 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
9ace0497 | 2864 | if (mips_debug) |
acdb74a0 | 2865 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2866 | float_argreg, phex (regval, len)); |
a8852dc5 | 2867 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
2868 | } |
2869 | } | |
2870 | else | |
2871 | { | |
2872 | /* Copy the argument to general registers or the stack in | |
2873 | register-sized pieces. Large arguments are split between | |
2874 | registers and stack. */ | |
1a69e1e4 DJ |
2875 | /* Note: structs whose size is not a multiple of regsize |
2876 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
2877 | them in registers where gcc sometimes puts them on the |
2878 | stack. For maximum compatibility, we will put them in | |
2879 | both places. */ | |
1a69e1e4 | 2880 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 2881 | |
f09ded24 | 2882 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2883 | register are only written to memory. */ |
c906108c SS |
2884 | while (len > 0) |
2885 | { | |
ebafbe83 | 2886 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2887 | int stack_used_p = 0; |
1a69e1e4 | 2888 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 2889 | |
acdb74a0 AC |
2890 | if (mips_debug) |
2891 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2892 | partial_len); | |
2893 | ||
566f0f7a | 2894 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 2895 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 2896 | || odd_sized_struct |
74ed0bb4 | 2897 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 2898 | { |
c906108c SS |
2899 | /* Should shorter than int integer values be |
2900 | promoted to int before being stored? */ | |
c906108c | 2901 | int longword_offset = 0; |
9ace0497 | 2902 | CORE_ADDR addr; |
566f0f7a | 2903 | stack_used_p = 1; |
72a155b4 | 2904 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 2905 | { |
1a69e1e4 | 2906 | if (regsize == 8 |
480d3dd2 AC |
2907 | && (typecode == TYPE_CODE_INT |
2908 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 2909 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 2910 | longword_offset = regsize - len; |
480d3dd2 AC |
2911 | else if ((typecode == TYPE_CODE_STRUCT |
2912 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
2913 | && TYPE_LENGTH (arg_type) < regsize) |
2914 | longword_offset = regsize - len; | |
7a292a7a | 2915 | } |
c5aa993b | 2916 | |
9ace0497 AC |
2917 | if (mips_debug) |
2918 | { | |
5af949e3 UW |
2919 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
2920 | paddress (gdbarch, stack_offset)); | |
2921 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
2922 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 2923 | } |
361d1df0 | 2924 | |
9ace0497 AC |
2925 | addr = sp + stack_offset + longword_offset; |
2926 | ||
2927 | if (mips_debug) | |
2928 | { | |
2929 | int i; | |
5af949e3 UW |
2930 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
2931 | paddress (gdbarch, addr)); | |
9ace0497 AC |
2932 | for (i = 0; i < partial_len; i++) |
2933 | { | |
6d82d43b | 2934 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 2935 | val[i] & 0xff); |
9ace0497 AC |
2936 | } |
2937 | } | |
2938 | write_memory (addr, val, partial_len); | |
c906108c SS |
2939 | } |
2940 | ||
f09ded24 AC |
2941 | /* Note!!! This is NOT an else clause. Odd sized |
2942 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2943 | arguments will not. */ |
566f0f7a | 2944 | /* Write this portion of the argument to a general |
6d82d43b | 2945 | purpose register. */ |
74ed0bb4 MD |
2946 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
2947 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 2948 | { |
6d82d43b | 2949 | LONGEST regval = |
a8852dc5 | 2950 | extract_signed_integer (val, partial_len, byte_order); |
c906108c | 2951 | |
9ace0497 | 2952 | if (mips_debug) |
acdb74a0 | 2953 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 2954 | argreg, |
1a69e1e4 | 2955 | phex (regval, regsize)); |
a8852dc5 | 2956 | regcache_cooked_write_signed (regcache, argreg, regval); |
c906108c | 2957 | argreg++; |
c906108c | 2958 | } |
c5aa993b | 2959 | |
c906108c SS |
2960 | len -= partial_len; |
2961 | val += partial_len; | |
2962 | ||
566f0f7a | 2963 | /* Compute the the offset into the stack at which we |
6d82d43b | 2964 | will copy the next parameter. |
566f0f7a | 2965 | |
566f0f7a | 2966 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2967 | only needs to be adjusted when it has been used. */ |
c906108c | 2968 | |
46e0f506 | 2969 | if (stack_used_p) |
1a69e1e4 | 2970 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
2971 | } |
2972 | } | |
9ace0497 AC |
2973 | if (mips_debug) |
2974 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2975 | } |
2976 | ||
f10683bb | 2977 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 2978 | |
0f71a2f6 JM |
2979 | /* Return adjusted stack pointer. */ |
2980 | return sp; | |
2981 | } | |
2982 | ||
a1f5b845 | 2983 | /* Determine the return value convention being used. */ |
6d82d43b | 2984 | |
9c8fdbfa | 2985 | static enum return_value_convention |
c055b101 | 2986 | mips_eabi_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 2987 | struct type *type, struct regcache *regcache, |
47a35522 | 2988 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 2989 | { |
609ba780 JM |
2990 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2991 | int fp_return_type = 0; | |
2992 | int offset, regnum, xfer; | |
2993 | ||
9c8fdbfa AC |
2994 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
2995 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
2996 | |
2997 | /* Floating point type? */ | |
2998 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
2999 | { | |
3000 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
3001 | fp_return_type = 1; | |
3002 | /* Structs with a single field of float type | |
3003 | are returned in a floating point register. */ | |
3004 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3005 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3006 | && TYPE_NFIELDS (type) == 1) | |
3007 | { | |
3008 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); | |
3009 | ||
3010 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) | |
3011 | fp_return_type = 1; | |
3012 | } | |
3013 | } | |
3014 | ||
3015 | if (fp_return_type) | |
3016 | { | |
3017 | /* A floating-point value belongs in the least significant part | |
3018 | of FP0/FP1. */ | |
3019 | if (mips_debug) | |
3020 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3021 | regnum = mips_regnum (gdbarch)->fp0; | |
3022 | } | |
3023 | else | |
3024 | { | |
3025 | /* An integer value goes in V0/V1. */ | |
3026 | if (mips_debug) | |
3027 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
3028 | regnum = MIPS_V0_REGNUM; | |
3029 | } | |
3030 | for (offset = 0; | |
3031 | offset < TYPE_LENGTH (type); | |
3032 | offset += mips_abi_regsize (gdbarch), regnum++) | |
3033 | { | |
3034 | xfer = mips_abi_regsize (gdbarch); | |
3035 | if (offset + xfer > TYPE_LENGTH (type)) | |
3036 | xfer = TYPE_LENGTH (type) - offset; | |
3037 | mips_xfer_register (gdbarch, regcache, | |
3038 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
3039 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
3040 | offset); | |
3041 | } | |
3042 | ||
9c8fdbfa | 3043 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
3044 | } |
3045 | ||
6d82d43b AC |
3046 | |
3047 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 3048 | |
8d26208a DJ |
3049 | /* Search for a naturally aligned double at OFFSET inside a struct |
3050 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
3051 | registers. */ | |
3052 | ||
3053 | static int | |
74ed0bb4 MD |
3054 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
3055 | int offset) | |
8d26208a DJ |
3056 | { |
3057 | int i; | |
3058 | ||
3059 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
3060 | return 0; | |
3061 | ||
74ed0bb4 | 3062 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
3063 | return 0; |
3064 | ||
3065 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
3066 | return 0; | |
3067 | ||
3068 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
3069 | { | |
3070 | int pos; | |
3071 | struct type *field_type; | |
3072 | ||
3073 | /* We're only looking at normal fields. */ | |
5bc60cfb | 3074 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
8d26208a DJ |
3075 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
3076 | continue; | |
3077 | ||
3078 | /* If we have gone past the offset, there is no double to pass. */ | |
3079 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
3080 | if (pos > offset) | |
3081 | return 0; | |
3082 | ||
3083 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
3084 | ||
3085 | /* If this field is entirely before the requested offset, go | |
3086 | on to the next one. */ | |
3087 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
3088 | continue; | |
3089 | ||
3090 | /* If this is our special aligned double, we can stop. */ | |
3091 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
3092 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
3093 | return 1; | |
3094 | ||
3095 | /* This field starts at or before the requested offset, and | |
3096 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 3097 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
3098 | } |
3099 | ||
3100 | return 0; | |
3101 | } | |
3102 | ||
f7ab6ec6 | 3103 | static CORE_ADDR |
7d9b040b | 3104 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3105 | struct regcache *regcache, CORE_ADDR bp_addr, |
3106 | int nargs, struct value **args, CORE_ADDR sp, | |
3107 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3108 | { |
3109 | int argreg; | |
3110 | int float_argreg; | |
3111 | int argnum; | |
3112 | int len = 0; | |
3113 | int stack_offset = 0; | |
480d3dd2 | 3114 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 3115 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 3116 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 3117 | |
25ab4790 AC |
3118 | /* For shared libraries, "t9" needs to point at the function |
3119 | address. */ | |
4c7d22cb | 3120 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3121 | |
3122 | /* Set the return address register to point to the entry point of | |
3123 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3124 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3125 | |
cb3d25d1 MS |
3126 | /* First ensure that the stack and structure return address (if any) |
3127 | are properly aligned. The stack has to be at least 64-bit | |
3128 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3129 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3130 | aligned, so we round to this widest known alignment. */ | |
3131 | ||
5b03f266 AC |
3132 | sp = align_down (sp, 16); |
3133 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3134 | |
3135 | /* Now make space on the stack for the args. */ | |
3136 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 3137 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 3138 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3139 | |
3140 | if (mips_debug) | |
6d82d43b | 3141 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3142 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
3143 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3144 | |
3145 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3146 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3147 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 3148 | |
46e0f506 | 3149 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3150 | if (struct_return) |
3151 | { | |
3152 | if (mips_debug) | |
3153 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
3154 | "mips_n32n64_push_dummy_call: struct_return reg=%d %s\n", |
3155 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 3156 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
3157 | } |
3158 | ||
3159 | /* Now load as many as possible of the first arguments into | |
3160 | registers, and push the rest onto the stack. Loop thru args | |
3161 | from first to last. */ | |
3162 | for (argnum = 0; argnum < nargs; argnum++) | |
3163 | { | |
47a35522 | 3164 | const gdb_byte *val; |
cb3d25d1 | 3165 | struct value *arg = args[argnum]; |
4991999e | 3166 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
3167 | int len = TYPE_LENGTH (arg_type); |
3168 | enum type_code typecode = TYPE_CODE (arg_type); | |
3169 | ||
3170 | if (mips_debug) | |
3171 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3172 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3173 | argnum + 1, len, (int) typecode); |
3174 | ||
47a35522 | 3175 | val = value_contents (arg); |
cb3d25d1 | 3176 | |
5b68030f JM |
3177 | /* A 128-bit long double value requires an even-odd pair of |
3178 | floating-point registers. */ | |
3179 | if (len == 16 | |
3180 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
3181 | && (float_argreg & 1)) | |
3182 | { | |
3183 | float_argreg++; | |
3184 | argreg++; | |
3185 | } | |
3186 | ||
74ed0bb4 MD |
3187 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3188 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
3189 | { |
3190 | /* This is a floating point value that fits entirely | |
5b68030f JM |
3191 | in a single register or a pair of registers. */ |
3192 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
e17a4113 | 3193 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
cb3d25d1 MS |
3194 | if (mips_debug) |
3195 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 3196 | float_argreg, phex (regval, reglen)); |
8d26208a | 3197 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
3198 | |
3199 | if (mips_debug) | |
3200 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 3201 | argreg, phex (regval, reglen)); |
9c9acae0 | 3202 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
3203 | float_argreg++; |
3204 | argreg++; | |
5b68030f JM |
3205 | if (len == 16) |
3206 | { | |
e17a4113 UW |
3207 | regval = extract_unsigned_integer (val + reglen, |
3208 | reglen, byte_order); | |
5b68030f JM |
3209 | if (mips_debug) |
3210 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3211 | float_argreg, phex (regval, reglen)); | |
3212 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
3213 | ||
3214 | if (mips_debug) | |
3215 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3216 | argreg, phex (regval, reglen)); | |
3217 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
3218 | float_argreg++; | |
3219 | argreg++; | |
3220 | } | |
cb3d25d1 MS |
3221 | } |
3222 | else | |
3223 | { | |
3224 | /* Copy the argument to general registers or the stack in | |
3225 | register-sized pieces. Large arguments are split between | |
3226 | registers and stack. */ | |
ab2e1992 MR |
3227 | /* For N32/N64, structs, unions, or other composite types are |
3228 | treated as a sequence of doublewords, and are passed in integer | |
3229 | or floating point registers as though they were simple scalar | |
3230 | parameters to the extent that they fit, with any excess on the | |
3231 | stack packed according to the normal memory layout of the | |
3232 | object. | |
3233 | The caller does not reserve space for the register arguments; | |
3234 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 3235 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3236 | register are only written to memory. */ |
cb3d25d1 MS |
3237 | while (len > 0) |
3238 | { | |
ad018eee | 3239 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 3240 | int stack_used_p = 0; |
1a69e1e4 | 3241 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
3242 | |
3243 | if (mips_debug) | |
3244 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3245 | partial_len); | |
3246 | ||
74ed0bb4 MD |
3247 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
3248 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 3249 | |
cb3d25d1 | 3250 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 3251 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
3252 | { |
3253 | /* Should shorter than int integer values be | |
3254 | promoted to int before being stored? */ | |
3255 | int longword_offset = 0; | |
3256 | CORE_ADDR addr; | |
3257 | stack_used_p = 1; | |
72a155b4 | 3258 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 3259 | { |
1a69e1e4 | 3260 | if ((typecode == TYPE_CODE_INT |
5b68030f | 3261 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
3262 | && len <= 4) |
3263 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
3264 | } |
3265 | ||
3266 | if (mips_debug) | |
3267 | { | |
5af949e3 UW |
3268 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3269 | paddress (gdbarch, stack_offset)); | |
3270 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3271 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
3272 | } |
3273 | ||
3274 | addr = sp + stack_offset + longword_offset; | |
3275 | ||
3276 | if (mips_debug) | |
3277 | { | |
3278 | int i; | |
5af949e3 UW |
3279 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3280 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
3281 | for (i = 0; i < partial_len; i++) |
3282 | { | |
6d82d43b | 3283 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3284 | val[i] & 0xff); |
3285 | } | |
3286 | } | |
3287 | write_memory (addr, val, partial_len); | |
3288 | } | |
3289 | ||
3290 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 3291 | structs may go thru BOTH paths. */ |
cb3d25d1 | 3292 | /* Write this portion of the argument to a general |
6d82d43b | 3293 | purpose register. */ |
74ed0bb4 | 3294 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 3295 | { |
5863b5d5 MR |
3296 | LONGEST regval; |
3297 | ||
3298 | /* Sign extend pointers, 32-bit integers and signed | |
3299 | 16-bit and 8-bit integers; everything else is taken | |
3300 | as is. */ | |
3301 | ||
3302 | if ((partial_len == 4 | |
3303 | && (typecode == TYPE_CODE_PTR | |
3304 | || typecode == TYPE_CODE_INT)) | |
3305 | || (partial_len < 4 | |
3306 | && typecode == TYPE_CODE_INT | |
3307 | && !TYPE_UNSIGNED (arg_type))) | |
e17a4113 UW |
3308 | regval = extract_signed_integer (val, partial_len, |
3309 | byte_order); | |
5863b5d5 | 3310 | else |
e17a4113 UW |
3311 | regval = extract_unsigned_integer (val, partial_len, |
3312 | byte_order); | |
cb3d25d1 MS |
3313 | |
3314 | /* A non-floating-point argument being passed in a | |
3315 | general register. If a struct or union, and if | |
3316 | the remaining length is smaller than the register | |
3317 | size, we have to adjust the register value on | |
3318 | big endian targets. | |
3319 | ||
3320 | It does not seem to be necessary to do the | |
1a69e1e4 | 3321 | same for integral types. */ |
cb3d25d1 | 3322 | |
72a155b4 | 3323 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3324 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3325 | && (typecode == TYPE_CODE_STRUCT |
3326 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3327 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3328 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
3329 | |
3330 | if (mips_debug) | |
3331 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3332 | argreg, | |
1a69e1e4 | 3333 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3334 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 3335 | |
74ed0bb4 | 3336 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
3337 | TYPE_LENGTH (arg_type) - len)) |
3338 | { | |
3339 | if (mips_debug) | |
3340 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
3341 | float_argreg, | |
3342 | phex (regval, MIPS64_REGSIZE)); | |
3343 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
3344 | regval); | |
3345 | } | |
3346 | ||
3347 | float_argreg++; | |
cb3d25d1 MS |
3348 | argreg++; |
3349 | } | |
3350 | ||
3351 | len -= partial_len; | |
3352 | val += partial_len; | |
3353 | ||
3354 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3355 | will copy the next parameter. |
cb3d25d1 MS |
3356 | |
3357 | In N32 (N64?), the stack_offset only needs to be | |
3358 | adjusted when it has been used. */ | |
3359 | ||
3360 | if (stack_used_p) | |
1a69e1e4 | 3361 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
3362 | } |
3363 | } | |
3364 | if (mips_debug) | |
3365 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3366 | } | |
3367 | ||
f10683bb | 3368 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3369 | |
cb3d25d1 MS |
3370 | /* Return adjusted stack pointer. */ |
3371 | return sp; | |
3372 | } | |
3373 | ||
6d82d43b | 3374 | static enum return_value_convention |
c055b101 | 3375 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
6d82d43b | 3376 | struct type *type, struct regcache *regcache, |
47a35522 | 3377 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 3378 | { |
72a155b4 | 3379 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
3380 | |
3381 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
3382 | ||
3383 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
3384 | if needed), as appropriate for the type. Composite results (struct, | |
3385 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
3386 | following rules: | |
3387 | ||
3388 | * A struct with only one or two floating point fields is returned in $f0 | |
3389 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
3390 | case. | |
3391 | ||
f08877ba | 3392 | * Any other composite results of at most 128 bits are returned in |
b18bb924 MR |
3393 | $2 (first 64 bits) and $3 (remainder, if necessary). |
3394 | ||
3395 | * Larger composite results are handled by converting the function to a | |
3396 | procedure with an implicit first parameter, which is a pointer to an area | |
3397 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
3398 | that all composite results be handled by conversion to implicit first | |
3399 | parameters. The MIPS/SGI Fortran implementation has always made a | |
3400 | specific exception to return COMPLEX results in the floating point | |
3401 | registers.] */ | |
3402 | ||
f08877ba | 3403 | if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 3404 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
3405 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3406 | && TYPE_LENGTH (type) == 16 | |
3407 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3408 | { | |
3409 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
3410 | two registers are used in the same as memory order, so the | |
3411 | eight bytes with the lower memory address are in $f0. */ | |
3412 | if (mips_debug) | |
3413 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 3414 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3415 | gdbarch_num_regs (gdbarch) |
3416 | + mips_regnum (gdbarch)->fp0, | |
3417 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3418 | readbuf, writebuf, 0); |
ba32f989 | 3419 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3420 | gdbarch_num_regs (gdbarch) |
3421 | + mips_regnum (gdbarch)->fp0 + 2, | |
3422 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3423 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
3424 | writebuf ? writebuf + 8 : writebuf, 0); |
3425 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3426 | } | |
6d82d43b AC |
3427 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3428 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3429 | { | |
59aa1faa | 3430 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
3431 | if (mips_debug) |
3432 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3433 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3434 | gdbarch_num_regs (gdbarch) |
3435 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3436 | TYPE_LENGTH (type), |
72a155b4 | 3437 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3438 | readbuf, writebuf, 0); |
6d82d43b AC |
3439 | return RETURN_VALUE_REGISTER_CONVENTION; |
3440 | } | |
3441 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3442 | && TYPE_NFIELDS (type) <= 2 | |
3443 | && TYPE_NFIELDS (type) >= 1 | |
3444 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 3445 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
3446 | == TYPE_CODE_FLT)) |
3447 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 3448 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 3449 | == TYPE_CODE_FLT) |
b18bb924 | 3450 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
5b68030f | 3451 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
3452 | { |
3453 | /* A struct that contains one or two floats. Each value is part | |
3454 | in the least significant part of their floating point | |
5b68030f | 3455 | register (or GPR, for soft float). */ |
6d82d43b AC |
3456 | int regnum; |
3457 | int field; | |
5b68030f JM |
3458 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
3459 | ? mips_regnum (gdbarch)->fp0 | |
3460 | : MIPS_V0_REGNUM); | |
6d82d43b AC |
3461 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3462 | { | |
3463 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3464 | / TARGET_CHAR_BIT); | |
3465 | if (mips_debug) | |
3466 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3467 | offset); | |
5b68030f JM |
3468 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
3469 | { | |
3470 | /* A 16-byte long double field goes in two consecutive | |
3471 | registers. */ | |
3472 | mips_xfer_register (gdbarch, regcache, | |
3473 | gdbarch_num_regs (gdbarch) + regnum, | |
3474 | 8, | |
3475 | gdbarch_byte_order (gdbarch), | |
3476 | readbuf, writebuf, offset); | |
3477 | mips_xfer_register (gdbarch, regcache, | |
3478 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
3479 | 8, | |
3480 | gdbarch_byte_order (gdbarch), | |
3481 | readbuf, writebuf, offset + 8); | |
3482 | } | |
3483 | else | |
3484 | mips_xfer_register (gdbarch, regcache, | |
3485 | gdbarch_num_regs (gdbarch) + regnum, | |
3486 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3487 | gdbarch_byte_order (gdbarch), | |
3488 | readbuf, writebuf, offset); | |
6d82d43b AC |
3489 | } |
3490 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3491 | } | |
3492 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
f08877ba JB |
3493 | || TYPE_CODE (type) == TYPE_CODE_UNION |
3494 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
6d82d43b | 3495 | { |
f08877ba | 3496 | /* A composite type. Extract the left justified value, |
6d82d43b AC |
3497 | regardless of the byte order. I.e. DO NOT USE |
3498 | mips_xfer_lower. */ | |
3499 | int offset; | |
3500 | int regnum; | |
4c7d22cb | 3501 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3502 | offset < TYPE_LENGTH (type); |
72a155b4 | 3503 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3504 | { |
72a155b4 | 3505 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3506 | if (offset + xfer > TYPE_LENGTH (type)) |
3507 | xfer = TYPE_LENGTH (type) - offset; | |
3508 | if (mips_debug) | |
3509 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3510 | offset, xfer, regnum); | |
ba32f989 DJ |
3511 | mips_xfer_register (gdbarch, regcache, |
3512 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
3513 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
3514 | offset); | |
6d82d43b AC |
3515 | } |
3516 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3517 | } | |
3518 | else | |
3519 | { | |
3520 | /* A scalar extract each part but least-significant-byte | |
3521 | justified. */ | |
3522 | int offset; | |
3523 | int regnum; | |
4c7d22cb | 3524 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3525 | offset < TYPE_LENGTH (type); |
72a155b4 | 3526 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3527 | { |
72a155b4 | 3528 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3529 | if (offset + xfer > TYPE_LENGTH (type)) |
3530 | xfer = TYPE_LENGTH (type) - offset; | |
3531 | if (mips_debug) | |
3532 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3533 | offset, xfer, regnum); | |
ba32f989 DJ |
3534 | mips_xfer_register (gdbarch, regcache, |
3535 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 3536 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 3537 | readbuf, writebuf, offset); |
6d82d43b AC |
3538 | } |
3539 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3540 | } | |
3541 | } | |
3542 | ||
3543 | /* O32 ABI stuff. */ | |
3544 | ||
3545 | static CORE_ADDR | |
7d9b040b | 3546 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3547 | struct regcache *regcache, CORE_ADDR bp_addr, |
3548 | int nargs, struct value **args, CORE_ADDR sp, | |
3549 | int struct_return, CORE_ADDR struct_addr) | |
3550 | { | |
3551 | int argreg; | |
3552 | int float_argreg; | |
3553 | int argnum; | |
3554 | int len = 0; | |
3555 | int stack_offset = 0; | |
3556 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
e17a4113 | 3557 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 3558 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3559 | |
3560 | /* For shared libraries, "t9" needs to point at the function | |
3561 | address. */ | |
4c7d22cb | 3562 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3563 | |
3564 | /* Set the return address register to point to the entry point of | |
3565 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3566 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3567 | |
3568 | /* First ensure that the stack and structure return address (if any) | |
3569 | are properly aligned. The stack has to be at least 64-bit | |
3570 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3571 | aligned. For n32 and n64, stack frames need to be 128-bit |
3572 | aligned, so we round to this widest known alignment. */ | |
3573 | ||
5b03f266 AC |
3574 | sp = align_down (sp, 16); |
3575 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3576 | |
3577 | /* Now make space on the stack for the args. */ | |
3578 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3579 | { |
3580 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3581 | int arglen = TYPE_LENGTH (arg_type); | |
3582 | ||
3583 | /* Align to double-word if necessary. */ | |
2afd3f0a | 3584 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 3585 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 3586 | /* Allocate space on the stack. */ |
1a69e1e4 | 3587 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 3588 | } |
5b03f266 | 3589 | sp -= align_up (len, 16); |
ebafbe83 MS |
3590 | |
3591 | if (mips_debug) | |
6d82d43b | 3592 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3593 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
3594 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3595 | |
3596 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3597 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3598 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 3599 | |
bcb0cc15 | 3600 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3601 | if (struct_return) |
3602 | { | |
3603 | if (mips_debug) | |
3604 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
3605 | "mips_o32_push_dummy_call: struct_return reg=%d %s\n", |
3606 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 3607 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3608 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
3609 | } |
3610 | ||
3611 | /* Now load as many as possible of the first arguments into | |
3612 | registers, and push the rest onto the stack. Loop thru args | |
3613 | from first to last. */ | |
3614 | for (argnum = 0; argnum < nargs; argnum++) | |
3615 | { | |
47a35522 | 3616 | const gdb_byte *val; |
ebafbe83 | 3617 | struct value *arg = args[argnum]; |
4991999e | 3618 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3619 | int len = TYPE_LENGTH (arg_type); |
3620 | enum type_code typecode = TYPE_CODE (arg_type); | |
3621 | ||
3622 | if (mips_debug) | |
3623 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3624 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3625 | argnum + 1, len, (int) typecode); |
3626 | ||
47a35522 | 3627 | val = value_contents (arg); |
46cac009 AC |
3628 | |
3629 | /* 32-bit ABIs always start floating point arguments in an | |
3630 | even-numbered floating point register. Round the FP register | |
3631 | up before the check to see if there are any FP registers | |
3632 | left. O32/O64 targets also pass the FP in the integer | |
3633 | registers so also round up normal registers. */ | |
74ed0bb4 | 3634 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
3635 | { |
3636 | if ((float_argreg & 1)) | |
3637 | float_argreg++; | |
3638 | } | |
3639 | ||
3640 | /* Floating point arguments passed in registers have to be | |
3641 | treated specially. On 32-bit architectures, doubles | |
3642 | are passed in register pairs; the even register gets | |
3643 | the low word, and the odd register gets the high word. | |
3644 | On O32/O64, the first two floating point arguments are | |
3645 | also copied to general registers, because MIPS16 functions | |
3646 | don't use float registers for arguments. This duplication of | |
3647 | arguments in general registers can't hurt non-MIPS16 functions | |
3648 | because those registers are normally skipped. */ | |
3649 | ||
74ed0bb4 MD |
3650 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3651 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 3652 | { |
8b07f6d8 | 3653 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 3654 | { |
72a155b4 | 3655 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 3656 | == BFD_ENDIAN_BIG ? 4 : 0; |
46cac009 AC |
3657 | unsigned long regval; |
3658 | ||
3659 | /* Write the low word of the double to the even register(s). */ | |
e17a4113 UW |
3660 | regval = extract_unsigned_integer (val + low_offset, |
3661 | 4, byte_order); | |
46cac009 AC |
3662 | if (mips_debug) |
3663 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3664 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3665 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3666 | if (mips_debug) |
3667 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3668 | argreg, phex (regval, 4)); | |
9c9acae0 | 3669 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3670 | |
3671 | /* Write the high word of the double to the odd register(s). */ | |
e17a4113 UW |
3672 | regval = extract_unsigned_integer (val + 4 - low_offset, |
3673 | 4, byte_order); | |
46cac009 AC |
3674 | if (mips_debug) |
3675 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3676 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3677 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3678 | |
3679 | if (mips_debug) | |
3680 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3681 | argreg, phex (regval, 4)); | |
9c9acae0 | 3682 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3683 | } |
3684 | else | |
3685 | { | |
3686 | /* This is a floating point value that fits entirely | |
3687 | in a single register. */ | |
3688 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3689 | above to ensure that it is even register aligned. */ |
e17a4113 | 3690 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
46cac009 AC |
3691 | if (mips_debug) |
3692 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3693 | float_argreg, phex (regval, len)); | |
9c9acae0 | 3694 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
5b68030f JM |
3695 | /* Although two FP registers are reserved for each |
3696 | argument, only one corresponding integer register is | |
3697 | reserved. */ | |
46cac009 AC |
3698 | if (mips_debug) |
3699 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3700 | argreg, phex (regval, len)); | |
5b68030f | 3701 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3702 | } |
3703 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 3704 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
3705 | } |
3706 | else | |
3707 | { | |
3708 | /* Copy the argument to general registers or the stack in | |
3709 | register-sized pieces. Large arguments are split between | |
3710 | registers and stack. */ | |
1a69e1e4 DJ |
3711 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
3712 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3713 | them in registers where gcc sometimes puts them on the |
3714 | stack. For maximum compatibility, we will put them in | |
3715 | both places. */ | |
1a69e1e4 DJ |
3716 | int odd_sized_struct = (len > MIPS32_REGSIZE |
3717 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
3718 | /* Structures should be aligned to eight bytes (even arg registers) |
3719 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 3720 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
3721 | { |
3722 | if ((argreg & 1)) | |
968b5391 MR |
3723 | { |
3724 | argreg++; | |
1a69e1e4 | 3725 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 3726 | } |
46cac009 | 3727 | } |
46cac009 AC |
3728 | while (len > 0) |
3729 | { | |
3730 | /* Remember if the argument was written to the stack. */ | |
3731 | int stack_used_p = 0; | |
1a69e1e4 | 3732 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
3733 | |
3734 | if (mips_debug) | |
3735 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3736 | partial_len); | |
3737 | ||
3738 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 3739 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 3740 | || odd_sized_struct) |
46cac009 AC |
3741 | { |
3742 | /* Should shorter than int integer values be | |
3743 | promoted to int before being stored? */ | |
3744 | int longword_offset = 0; | |
3745 | CORE_ADDR addr; | |
3746 | stack_used_p = 1; | |
46cac009 AC |
3747 | |
3748 | if (mips_debug) | |
3749 | { | |
5af949e3 UW |
3750 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3751 | paddress (gdbarch, stack_offset)); | |
3752 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3753 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
3754 | } |
3755 | ||
3756 | addr = sp + stack_offset + longword_offset; | |
3757 | ||
3758 | if (mips_debug) | |
3759 | { | |
3760 | int i; | |
5af949e3 UW |
3761 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3762 | paddress (gdbarch, addr)); | |
46cac009 AC |
3763 | for (i = 0; i < partial_len; i++) |
3764 | { | |
6d82d43b | 3765 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3766 | val[i] & 0xff); |
3767 | } | |
3768 | } | |
3769 | write_memory (addr, val, partial_len); | |
3770 | } | |
3771 | ||
3772 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3773 | structs may go thru BOTH paths. */ |
46cac009 | 3774 | /* Write this portion of the argument to a general |
6d82d43b | 3775 | purpose register. */ |
74ed0bb4 | 3776 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 | 3777 | { |
e17a4113 UW |
3778 | LONGEST regval = extract_signed_integer (val, partial_len, |
3779 | byte_order); | |
4246e332 | 3780 | /* Value may need to be sign extended, because |
1b13c4f6 | 3781 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3782 | |
3783 | /* A non-floating-point argument being passed in a | |
3784 | general register. If a struct or union, and if | |
3785 | the remaining length is smaller than the register | |
3786 | size, we have to adjust the register value on | |
3787 | big endian targets. | |
3788 | ||
3789 | It does not seem to be necessary to do the | |
3790 | same for integral types. | |
3791 | ||
3792 | Also don't do this adjustment on O64 binaries. | |
3793 | ||
3794 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3795 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
3796 | mips_abi_regsize(), generates a left shift |
3797 | as part of storing the argument in a register | |
3798 | (the left shift isn't generated when | |
1b13c4f6 | 3799 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3800 | it is quite possible that this is GCC |
3801 | contradicting the LE/O32 ABI, GDB has not been | |
3802 | adjusted to accommodate this. Either someone | |
3803 | needs to demonstrate that the LE/O32 ABI | |
3804 | specifies such a left shift OR this new ABI gets | |
3805 | identified as such and GDB gets tweaked | |
3806 | accordingly. */ | |
3807 | ||
72a155b4 | 3808 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3809 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
3810 | && (typecode == TYPE_CODE_STRUCT |
3811 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3812 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 3813 | * TARGET_CHAR_BIT); |
46cac009 AC |
3814 | |
3815 | if (mips_debug) | |
3816 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3817 | argreg, | |
1a69e1e4 | 3818 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 3819 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
3820 | argreg++; |
3821 | ||
3822 | /* Prevent subsequent floating point arguments from | |
3823 | being passed in floating point registers. */ | |
74ed0bb4 | 3824 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
3825 | } |
3826 | ||
3827 | len -= partial_len; | |
3828 | val += partial_len; | |
3829 | ||
3830 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3831 | will copy the next parameter. |
46cac009 | 3832 | |
6d82d43b AC |
3833 | In older ABIs, the caller reserved space for |
3834 | registers that contained arguments. This was loosely | |
3835 | refered to as their "home". Consequently, space is | |
3836 | always allocated. */ | |
46cac009 | 3837 | |
1a69e1e4 | 3838 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
3839 | } |
3840 | } | |
3841 | if (mips_debug) | |
3842 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3843 | } | |
3844 | ||
f10683bb | 3845 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3846 | |
46cac009 AC |
3847 | /* Return adjusted stack pointer. */ |
3848 | return sp; | |
3849 | } | |
3850 | ||
6d82d43b | 3851 | static enum return_value_convention |
c055b101 CV |
3852 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *func_type, |
3853 | struct type *type, struct regcache *regcache, | |
47a35522 | 3854 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3855 | { |
72a155b4 | 3856 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6d82d43b AC |
3857 | |
3858 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3859 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3860 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3861 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3862 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3863 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3864 | { | |
3865 | /* A single-precision floating-point value. It fits in the | |
3866 | least significant part of FP0. */ | |
3867 | if (mips_debug) | |
3868 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3869 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3870 | gdbarch_num_regs (gdbarch) |
3871 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3872 | TYPE_LENGTH (type), |
72a155b4 | 3873 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3874 | readbuf, writebuf, 0); |
6d82d43b AC |
3875 | return RETURN_VALUE_REGISTER_CONVENTION; |
3876 | } | |
3877 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3878 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3879 | { | |
3880 | /* A double-precision floating-point value. The most | |
3881 | significant part goes in FP1, and the least significant in | |
3882 | FP0. */ | |
3883 | if (mips_debug) | |
3884 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
72a155b4 | 3885 | switch (gdbarch_byte_order (gdbarch)) |
6d82d43b AC |
3886 | { |
3887 | case BFD_ENDIAN_LITTLE: | |
ba32f989 | 3888 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3889 | gdbarch_num_regs (gdbarch) |
3890 | + mips_regnum (gdbarch)->fp0 + | |
3891 | 0, 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3892 | readbuf, writebuf, 0); |
ba32f989 | 3893 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3894 | gdbarch_num_regs (gdbarch) |
3895 | + mips_regnum (gdbarch)->fp0 + 1, | |
3896 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3897 | readbuf, writebuf, 4); |
6d82d43b AC |
3898 | break; |
3899 | case BFD_ENDIAN_BIG: | |
ba32f989 | 3900 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3901 | gdbarch_num_regs (gdbarch) |
3902 | + mips_regnum (gdbarch)->fp0 + 1, | |
3903 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3904 | readbuf, writebuf, 0); |
ba32f989 | 3905 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3906 | gdbarch_num_regs (gdbarch) |
3907 | + mips_regnum (gdbarch)->fp0 + 0, | |
3908 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3909 | readbuf, writebuf, 4); |
6d82d43b AC |
3910 | break; |
3911 | default: | |
e2e0b3e5 | 3912 | internal_error (__FILE__, __LINE__, _("bad switch")); |
6d82d43b AC |
3913 | } |
3914 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3915 | } | |
3916 | #if 0 | |
3917 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3918 | && TYPE_NFIELDS (type) <= 2 | |
3919 | && TYPE_NFIELDS (type) >= 1 | |
3920 | && ((TYPE_NFIELDS (type) == 1 | |
3921 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3922 | == TYPE_CODE_FLT)) | |
3923 | || (TYPE_NFIELDS (type) == 2 | |
3924 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3925 | == TYPE_CODE_FLT) | |
3926 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3927 | == TYPE_CODE_FLT))) | |
3928 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3929 | { | |
3930 | /* A struct that contains one or two floats. Each value is part | |
3931 | in the least significant part of their floating point | |
3932 | register.. */ | |
870cd05e | 3933 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
3934 | int regnum; |
3935 | int field; | |
72a155b4 | 3936 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
3937 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3938 | { | |
3939 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3940 | / TARGET_CHAR_BIT); | |
3941 | if (mips_debug) | |
3942 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3943 | offset); | |
ba32f989 DJ |
3944 | mips_xfer_register (gdbarch, regcache, |
3945 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 3946 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 3947 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3948 | readbuf, writebuf, offset); |
6d82d43b AC |
3949 | } |
3950 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3951 | } | |
3952 | #endif | |
3953 | #if 0 | |
3954 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3955 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3956 | { | |
3957 | /* A structure or union. Extract the left justified value, | |
3958 | regardless of the byte order. I.e. DO NOT USE | |
3959 | mips_xfer_lower. */ | |
3960 | int offset; | |
3961 | int regnum; | |
4c7d22cb | 3962 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3963 | offset < TYPE_LENGTH (type); |
72a155b4 | 3964 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3965 | { |
72a155b4 | 3966 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3967 | if (offset + xfer > TYPE_LENGTH (type)) |
3968 | xfer = TYPE_LENGTH (type) - offset; | |
3969 | if (mips_debug) | |
3970 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3971 | offset, xfer, regnum); | |
ba32f989 DJ |
3972 | mips_xfer_register (gdbarch, regcache, |
3973 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
3974 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
3975 | } | |
3976 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3977 | } | |
3978 | #endif | |
3979 | else | |
3980 | { | |
3981 | /* A scalar extract each part but least-significant-byte | |
3982 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 3983 | the ISA. */ |
6d82d43b AC |
3984 | int offset; |
3985 | int regnum; | |
4c7d22cb | 3986 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3987 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 3988 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 3989 | { |
1a69e1e4 | 3990 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
3991 | if (offset + xfer > TYPE_LENGTH (type)) |
3992 | xfer = TYPE_LENGTH (type) - offset; | |
3993 | if (mips_debug) | |
3994 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3995 | offset, xfer, regnum); | |
ba32f989 DJ |
3996 | mips_xfer_register (gdbarch, regcache, |
3997 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 3998 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3999 | readbuf, writebuf, offset); |
6d82d43b AC |
4000 | } |
4001 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4002 | } | |
4003 | } | |
4004 | ||
4005 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
4006 | ABI. */ | |
46cac009 AC |
4007 | |
4008 | static CORE_ADDR | |
7d9b040b | 4009 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4010 | struct regcache *regcache, CORE_ADDR bp_addr, |
4011 | int nargs, | |
4012 | struct value **args, CORE_ADDR sp, | |
4013 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
4014 | { |
4015 | int argreg; | |
4016 | int float_argreg; | |
4017 | int argnum; | |
4018 | int len = 0; | |
4019 | int stack_offset = 0; | |
480d3dd2 | 4020 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 4021 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4022 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 4023 | |
25ab4790 AC |
4024 | /* For shared libraries, "t9" needs to point at the function |
4025 | address. */ | |
4c7d22cb | 4026 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4027 | |
4028 | /* Set the return address register to point to the entry point of | |
4029 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4030 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4031 | |
46cac009 AC |
4032 | /* First ensure that the stack and structure return address (if any) |
4033 | are properly aligned. The stack has to be at least 64-bit | |
4034 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4035 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4036 | aligned, so we round to this widest known alignment. */ | |
4037 | ||
5b03f266 AC |
4038 | sp = align_down (sp, 16); |
4039 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
4040 | |
4041 | /* Now make space on the stack for the args. */ | |
4042 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
4043 | { |
4044 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
4045 | int arglen = TYPE_LENGTH (arg_type); | |
4046 | ||
968b5391 | 4047 | /* Allocate space on the stack. */ |
1a69e1e4 | 4048 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 4049 | } |
5b03f266 | 4050 | sp -= align_up (len, 16); |
46cac009 AC |
4051 | |
4052 | if (mips_debug) | |
6d82d43b | 4053 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4054 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
4055 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
46cac009 AC |
4056 | |
4057 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4058 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4059 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
4060 | |
4061 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
4062 | if (struct_return) | |
4063 | { | |
4064 | if (mips_debug) | |
4065 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
4066 | "mips_o64_push_dummy_call: struct_return reg=%d %s\n", |
4067 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 4068 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 4069 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
4070 | } |
4071 | ||
4072 | /* Now load as many as possible of the first arguments into | |
4073 | registers, and push the rest onto the stack. Loop thru args | |
4074 | from first to last. */ | |
4075 | for (argnum = 0; argnum < nargs; argnum++) | |
4076 | { | |
47a35522 | 4077 | const gdb_byte *val; |
46cac009 | 4078 | struct value *arg = args[argnum]; |
4991999e | 4079 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
4080 | int len = TYPE_LENGTH (arg_type); |
4081 | enum type_code typecode = TYPE_CODE (arg_type); | |
4082 | ||
4083 | if (mips_debug) | |
4084 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4085 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
4086 | argnum + 1, len, (int) typecode); |
4087 | ||
47a35522 | 4088 | val = value_contents (arg); |
ebafbe83 | 4089 | |
ebafbe83 MS |
4090 | /* Floating point arguments passed in registers have to be |
4091 | treated specially. On 32-bit architectures, doubles | |
4092 | are passed in register pairs; the even register gets | |
4093 | the low word, and the odd register gets the high word. | |
4094 | On O32/O64, the first two floating point arguments are | |
4095 | also copied to general registers, because MIPS16 functions | |
4096 | don't use float registers for arguments. This duplication of | |
4097 | arguments in general registers can't hurt non-MIPS16 functions | |
4098 | because those registers are normally skipped. */ | |
4099 | ||
74ed0bb4 MD |
4100 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4101 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 4102 | { |
e17a4113 | 4103 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
2afd3f0a MR |
4104 | if (mips_debug) |
4105 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4106 | float_argreg, phex (regval, len)); | |
9c9acae0 | 4107 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
4108 | if (mips_debug) |
4109 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4110 | argreg, phex (regval, len)); | |
9c9acae0 | 4111 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 4112 | argreg++; |
ebafbe83 | 4113 | /* Reserve space for the FP register. */ |
1a69e1e4 | 4114 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
4115 | } |
4116 | else | |
4117 | { | |
4118 | /* Copy the argument to general registers or the stack in | |
4119 | register-sized pieces. Large arguments are split between | |
4120 | registers and stack. */ | |
1a69e1e4 | 4121 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
4122 | are treated specially: Irix cc passes them in registers |
4123 | where gcc sometimes puts them on the stack. For maximum | |
4124 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
4125 | int odd_sized_struct = (len > MIPS64_REGSIZE |
4126 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
4127 | while (len > 0) |
4128 | { | |
4129 | /* Remember if the argument was written to the stack. */ | |
4130 | int stack_used_p = 0; | |
1a69e1e4 | 4131 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
4132 | |
4133 | if (mips_debug) | |
4134 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4135 | partial_len); | |
4136 | ||
4137 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 4138 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 4139 | || odd_sized_struct) |
ebafbe83 MS |
4140 | { |
4141 | /* Should shorter than int integer values be | |
4142 | promoted to int before being stored? */ | |
4143 | int longword_offset = 0; | |
4144 | CORE_ADDR addr; | |
4145 | stack_used_p = 1; | |
72a155b4 | 4146 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 4147 | { |
1a69e1e4 DJ |
4148 | if ((typecode == TYPE_CODE_INT |
4149 | || typecode == TYPE_CODE_PTR | |
4150 | || typecode == TYPE_CODE_FLT) | |
4151 | && len <= 4) | |
4152 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
4153 | } |
4154 | ||
4155 | if (mips_debug) | |
4156 | { | |
5af949e3 UW |
4157 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4158 | paddress (gdbarch, stack_offset)); | |
4159 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4160 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
4161 | } |
4162 | ||
4163 | addr = sp + stack_offset + longword_offset; | |
4164 | ||
4165 | if (mips_debug) | |
4166 | { | |
4167 | int i; | |
5af949e3 UW |
4168 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4169 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
4170 | for (i = 0; i < partial_len; i++) |
4171 | { | |
6d82d43b | 4172 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4173 | val[i] & 0xff); |
4174 | } | |
4175 | } | |
4176 | write_memory (addr, val, partial_len); | |
4177 | } | |
4178 | ||
4179 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 4180 | structs may go thru BOTH paths. */ |
ebafbe83 | 4181 | /* Write this portion of the argument to a general |
6d82d43b | 4182 | purpose register. */ |
74ed0bb4 | 4183 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 | 4184 | { |
e17a4113 UW |
4185 | LONGEST regval = extract_signed_integer (val, partial_len, |
4186 | byte_order); | |
4246e332 | 4187 | /* Value may need to be sign extended, because |
1b13c4f6 | 4188 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
4189 | |
4190 | /* A non-floating-point argument being passed in a | |
4191 | general register. If a struct or union, and if | |
4192 | the remaining length is smaller than the register | |
4193 | size, we have to adjust the register value on | |
4194 | big endian targets. | |
4195 | ||
4196 | It does not seem to be necessary to do the | |
401835eb | 4197 | same for integral types. */ |
480d3dd2 | 4198 | |
72a155b4 | 4199 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4200 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
4201 | && (typecode == TYPE_CODE_STRUCT |
4202 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4203 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 4204 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
4205 | |
4206 | if (mips_debug) | |
4207 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4208 | argreg, | |
1a69e1e4 | 4209 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 4210 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
4211 | argreg++; |
4212 | ||
4213 | /* Prevent subsequent floating point arguments from | |
4214 | being passed in floating point registers. */ | |
74ed0bb4 | 4215 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
4216 | } |
4217 | ||
4218 | len -= partial_len; | |
4219 | val += partial_len; | |
4220 | ||
4221 | /* Compute the the offset into the stack at which we | |
6d82d43b | 4222 | will copy the next parameter. |
ebafbe83 | 4223 | |
6d82d43b AC |
4224 | In older ABIs, the caller reserved space for |
4225 | registers that contained arguments. This was loosely | |
4226 | refered to as their "home". Consequently, space is | |
4227 | always allocated. */ | |
ebafbe83 | 4228 | |
1a69e1e4 | 4229 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
4230 | } |
4231 | } | |
4232 | if (mips_debug) | |
4233 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4234 | } | |
4235 | ||
f10683bb | 4236 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4237 | |
ebafbe83 MS |
4238 | /* Return adjusted stack pointer. */ |
4239 | return sp; | |
4240 | } | |
4241 | ||
9c8fdbfa | 4242 | static enum return_value_convention |
c055b101 | 4243 | mips_o64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 4244 | struct type *type, struct regcache *regcache, |
47a35522 | 4245 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4246 | { |
72a155b4 | 4247 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a076fd2 FF |
4248 | |
4249 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4250 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4251 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4252 | return RETURN_VALUE_STRUCT_CONVENTION; | |
74ed0bb4 | 4253 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
7a076fd2 FF |
4254 | { |
4255 | /* A floating-point value. It fits in the least significant | |
4256 | part of FP0. */ | |
4257 | if (mips_debug) | |
4258 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 4259 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4260 | gdbarch_num_regs (gdbarch) |
4261 | + mips_regnum (gdbarch)->fp0, | |
7a076fd2 | 4262 | TYPE_LENGTH (type), |
72a155b4 | 4263 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4264 | readbuf, writebuf, 0); |
7a076fd2 FF |
4265 | return RETURN_VALUE_REGISTER_CONVENTION; |
4266 | } | |
4267 | else | |
4268 | { | |
4269 | /* A scalar extract each part but least-significant-byte | |
4270 | justified. */ | |
4271 | int offset; | |
4272 | int regnum; | |
4273 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
4274 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 4275 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 4276 | { |
1a69e1e4 | 4277 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
4278 | if (offset + xfer > TYPE_LENGTH (type)) |
4279 | xfer = TYPE_LENGTH (type) - offset; | |
4280 | if (mips_debug) | |
4281 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4282 | offset, xfer, regnum); | |
ba32f989 DJ |
4283 | mips_xfer_register (gdbarch, regcache, |
4284 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 4285 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4286 | readbuf, writebuf, offset); |
7a076fd2 FF |
4287 | } |
4288 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4289 | } | |
6d82d43b AC |
4290 | } |
4291 | ||
dd824b04 DJ |
4292 | /* Floating point register management. |
4293 | ||
4294 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4295 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4296 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4297 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4298 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4299 | double precision floats into two 32-bit chunks and store them in | |
4300 | consecutive fp regs. To display 64-bit floats stored in this | |
4301 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4302 | Throw in user-configurable endianness and you have a real mess. | |
4303 | ||
4304 | The way this works is: | |
4305 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4306 | double-precision value will be split across two logical registers. | |
4307 | The lower-numbered logical register will hold the low-order bits, | |
4308 | regardless of the processor's endianness. | |
4309 | - If we are on a 64-bit processor, and we are looking for a | |
4310 | single-precision value, it will be in the low ordered bits | |
4311 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4312 | save slot in memory. | |
4313 | - If we are in 64-bit mode, everything is straightforward. | |
4314 | ||
4315 | Note that this code only deals with "live" registers at the top of the | |
4316 | stack. We will attempt to deal with saved registers later, when | |
4317 | the raw/cooked register interface is in place. (We need a general | |
4318 | interface that can deal with dynamic saved register sizes -- fp | |
4319 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4320 | and below). */ | |
4321 | ||
4322 | /* Copy a 32-bit single-precision value from the current frame | |
4323 | into rare_buffer. */ | |
4324 | ||
4325 | static void | |
e11c53d2 | 4326 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 4327 | gdb_byte *rare_buffer) |
dd824b04 | 4328 | { |
72a155b4 UW |
4329 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4330 | int raw_size = register_size (gdbarch, regno); | |
47a35522 | 4331 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 4332 | |
e11c53d2 | 4333 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 4334 | error (_("can't read register %d (%s)"), |
72a155b4 | 4335 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4336 | if (raw_size == 8) |
4337 | { | |
4338 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4339 | 32 bits. */ |
dd824b04 DJ |
4340 | int offset; |
4341 | ||
72a155b4 | 4342 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
4343 | offset = 4; |
4344 | else | |
4345 | offset = 0; | |
4346 | ||
4347 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4348 | } | |
4349 | else | |
4350 | { | |
4351 | memcpy (rare_buffer, raw_buffer, 4); | |
4352 | } | |
4353 | } | |
4354 | ||
4355 | /* Copy a 64-bit double-precision value from the current frame into | |
4356 | rare_buffer. This may include getting half of it from the next | |
4357 | register. */ | |
4358 | ||
4359 | static void | |
e11c53d2 | 4360 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 4361 | gdb_byte *rare_buffer) |
dd824b04 | 4362 | { |
72a155b4 UW |
4363 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4364 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 4365 | |
9c9acae0 | 4366 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
4367 | { |
4368 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4369 | all 64 bits. */ |
e11c53d2 | 4370 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 4371 | error (_("can't read register %d (%s)"), |
72a155b4 | 4372 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4373 | } |
4374 | else | |
4375 | { | |
72a155b4 | 4376 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 4377 | |
72a155b4 | 4378 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 4379 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
4380 | _("mips_read_fp_register_double: bad access to " |
4381 | "odd-numbered FP register")); | |
dd824b04 DJ |
4382 | |
4383 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4384 | each register. */ |
72a155b4 | 4385 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 4386 | { |
e11c53d2 AC |
4387 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4388 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4389 | } |
361d1df0 | 4390 | else |
dd824b04 | 4391 | { |
e11c53d2 AC |
4392 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4393 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4394 | } |
4395 | } | |
4396 | } | |
4397 | ||
c906108c | 4398 | static void |
e11c53d2 AC |
4399 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4400 | int regnum) | |
c5aa993b | 4401 | { /* do values for FP (float) regs */ |
72a155b4 | 4402 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4403 | gdb_byte *raw_buffer; |
3903d437 AC |
4404 | double doub, flt1; /* doubles extracted from raw hex data */ |
4405 | int inv1, inv2; | |
c5aa993b | 4406 | |
72a155b4 | 4407 | raw_buffer = alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0)); |
c906108c | 4408 | |
72a155b4 | 4409 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 4410 | fprintf_filtered (file, "%*s", |
72a155b4 | 4411 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 4412 | ""); |
f0ef6b29 | 4413 | |
72a155b4 | 4414 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 4415 | { |
79a45b7d TT |
4416 | struct value_print_options opts; |
4417 | ||
f0ef6b29 KB |
4418 | /* 4-byte registers: Print hex and floating. Also print even |
4419 | numbered registers as doubles. */ | |
e11c53d2 | 4420 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 | 4421 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, raw_buffer, &inv1); |
c5aa993b | 4422 | |
79a45b7d | 4423 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4424 | print_scalar_formatted (raw_buffer, |
4425 | builtin_type (gdbarch)->builtin_uint32, | |
4426 | &opts, 'w', file); | |
dd824b04 | 4427 | |
e11c53d2 | 4428 | fprintf_filtered (file, " flt: "); |
1adad886 | 4429 | if (inv1) |
e11c53d2 | 4430 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4431 | else |
e11c53d2 | 4432 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4433 | |
72a155b4 | 4434 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 4435 | { |
e11c53d2 | 4436 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4437 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4438 | raw_buffer, &inv2); | |
1adad886 | 4439 | |
e11c53d2 | 4440 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4441 | if (inv2) |
e11c53d2 | 4442 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4443 | else |
e11c53d2 | 4444 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4445 | } |
c906108c SS |
4446 | } |
4447 | else | |
dd824b04 | 4448 | { |
79a45b7d TT |
4449 | struct value_print_options opts; |
4450 | ||
f0ef6b29 | 4451 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4452 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 UW |
4453 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
4454 | raw_buffer, &inv1); | |
c906108c | 4455 | |
e11c53d2 | 4456 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4457 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4458 | raw_buffer, &inv2); | |
f0ef6b29 | 4459 | |
79a45b7d | 4460 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4461 | print_scalar_formatted (raw_buffer, |
4462 | builtin_type (gdbarch)->builtin_uint64, | |
4463 | &opts, 'g', file); | |
f0ef6b29 | 4464 | |
e11c53d2 | 4465 | fprintf_filtered (file, " flt: "); |
1adad886 | 4466 | if (inv1) |
e11c53d2 | 4467 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4468 | else |
e11c53d2 | 4469 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4470 | |
e11c53d2 | 4471 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4472 | if (inv2) |
e11c53d2 | 4473 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4474 | else |
e11c53d2 | 4475 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4476 | } |
4477 | } | |
4478 | ||
4479 | static void | |
e11c53d2 | 4480 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 4481 | int regnum) |
f0ef6b29 | 4482 | { |
a4b8ebc8 | 4483 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4484 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4485 | int offset; |
79a45b7d | 4486 | struct value_print_options opts; |
1adad886 | 4487 | |
7b9ee6a8 | 4488 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4489 | { |
e11c53d2 | 4490 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4491 | return; |
4492 | } | |
4493 | ||
4494 | /* Get the data in raw format. */ | |
e11c53d2 | 4495 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4496 | { |
c9f4d572 | 4497 | fprintf_filtered (file, "%s: [Invalid]", |
72a155b4 | 4498 | gdbarch_register_name (gdbarch, regnum)); |
f0ef6b29 | 4499 | return; |
c906108c | 4500 | } |
f0ef6b29 | 4501 | |
72a155b4 | 4502 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
4503 | |
4504 | /* The problem with printing numeric register names (r26, etc.) is that | |
4505 | the user can't use them on input. Probably the best solution is to | |
4506 | fix it so that either the numeric or the funky (a2, etc.) names | |
4507 | are accepted on input. */ | |
4508 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4509 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4510 | else |
e11c53d2 | 4511 | fprintf_filtered (file, ": "); |
f0ef6b29 | 4512 | |
72a155b4 | 4513 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4514 | offset = |
72a155b4 | 4515 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
f0ef6b29 KB |
4516 | else |
4517 | offset = 0; | |
4518 | ||
79a45b7d | 4519 | get_formatted_print_options (&opts, 'x'); |
6d82d43b | 4520 | print_scalar_formatted (raw_buffer + offset, |
79a45b7d | 4521 | register_type (gdbarch, regnum), &opts, 0, |
6d82d43b | 4522 | file); |
c906108c SS |
4523 | } |
4524 | ||
f0ef6b29 KB |
4525 | /* Replacement for generic do_registers_info. |
4526 | Print regs in pretty columns. */ | |
4527 | ||
4528 | static int | |
e11c53d2 AC |
4529 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4530 | int regnum) | |
f0ef6b29 | 4531 | { |
e11c53d2 AC |
4532 | fprintf_filtered (file, " "); |
4533 | mips_print_fp_register (file, frame, regnum); | |
4534 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4535 | return regnum + 1; |
4536 | } | |
4537 | ||
4538 | ||
c906108c SS |
4539 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4540 | ||
4541 | static int | |
e11c53d2 | 4542 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4543 | int start_regnum) |
c906108c | 4544 | { |
a4b8ebc8 | 4545 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4546 | /* do values for GP (int) regs */ |
47a35522 | 4547 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 4548 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4549 | int col, byte; |
a4b8ebc8 | 4550 | int regnum; |
c906108c SS |
4551 | |
4552 | /* For GP registers, we print a separate row of names above the vals */ | |
a4b8ebc8 | 4553 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4554 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4555 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4556 | regnum++) |
c906108c | 4557 | { |
72a155b4 | 4558 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4559 | continue; /* unused register */ |
7b9ee6a8 | 4560 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4561 | TYPE_CODE_FLT) |
c5aa993b | 4562 | break; /* end the row: reached FP register */ |
0cc93a06 | 4563 | /* Large registers are handled separately. */ |
72a155b4 | 4564 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4565 | { |
4566 | if (col > 0) | |
4567 | break; /* End the row before this register. */ | |
4568 | ||
4569 | /* Print this register on a row by itself. */ | |
4570 | mips_print_register (file, frame, regnum); | |
4571 | fprintf_filtered (file, "\n"); | |
4572 | return regnum + 1; | |
4573 | } | |
d05f6826 DJ |
4574 | if (col == 0) |
4575 | fprintf_filtered (file, " "); | |
6d82d43b | 4576 | fprintf_filtered (file, |
72a155b4 UW |
4577 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
4578 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
4579 | col++; |
4580 | } | |
d05f6826 DJ |
4581 | |
4582 | if (col == 0) | |
4583 | return regnum; | |
4584 | ||
a4b8ebc8 | 4585 | /* print the R0 to R31 names */ |
72a155b4 | 4586 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 4587 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 4588 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
4589 | else |
4590 | fprintf_filtered (file, "\n "); | |
c906108c | 4591 | |
c906108c | 4592 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4593 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4594 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4595 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4596 | regnum++) |
c906108c | 4597 | { |
72a155b4 | 4598 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4599 | continue; /* unused register */ |
7b9ee6a8 | 4600 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4601 | TYPE_CODE_FLT) |
c5aa993b | 4602 | break; /* end row: reached FP register */ |
72a155b4 | 4603 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4604 | break; /* End row: large register. */ |
4605 | ||
c906108c | 4606 | /* OK: get the data in raw format. */ |
e11c53d2 | 4607 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 | 4608 | error (_("can't read register %d (%s)"), |
72a155b4 | 4609 | regnum, gdbarch_register_name (gdbarch, regnum)); |
c906108c | 4610 | /* pad small registers */ |
4246e332 | 4611 | for (byte = 0; |
72a155b4 UW |
4612 | byte < (mips_abi_regsize (gdbarch) |
4613 | - register_size (gdbarch, regnum)); byte++) | |
c906108c SS |
4614 | printf_filtered (" "); |
4615 | /* Now print the register value in hex, endian order. */ | |
72a155b4 | 4616 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4617 | for (byte = |
72a155b4 UW |
4618 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
4619 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 4620 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 4621 | else |
72a155b4 | 4622 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 4623 | byte >= 0; byte--) |
47a35522 | 4624 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 4625 | fprintf_filtered (file, " "); |
c906108c SS |
4626 | col++; |
4627 | } | |
c5aa993b | 4628 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4629 | fprintf_filtered (file, "\n"); |
c906108c SS |
4630 | |
4631 | return regnum; | |
4632 | } | |
4633 | ||
4634 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4635 | ||
bf1f5b4c | 4636 | static void |
e11c53d2 AC |
4637 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4638 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4639 | { |
c5aa993b | 4640 | if (regnum != -1) /* do one specified register */ |
c906108c | 4641 | { |
72a155b4 UW |
4642 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
4643 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 4644 | error (_("Not a valid register for the current processor type")); |
c906108c | 4645 | |
0cc93a06 | 4646 | mips_print_register (file, frame, regnum); |
e11c53d2 | 4647 | fprintf_filtered (file, "\n"); |
c906108c | 4648 | } |
c5aa993b JM |
4649 | else |
4650 | /* do all (or most) registers */ | |
c906108c | 4651 | { |
72a155b4 UW |
4652 | regnum = gdbarch_num_regs (gdbarch); |
4653 | while (regnum < gdbarch_num_regs (gdbarch) | |
4654 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 4655 | { |
7b9ee6a8 | 4656 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4657 | TYPE_CODE_FLT) |
e11c53d2 AC |
4658 | { |
4659 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4660 | regnum = print_fp_register_row (file, frame, regnum); | |
4661 | else | |
4662 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4663 | } | |
c906108c | 4664 | else |
e11c53d2 | 4665 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4666 | } |
4667 | } | |
4668 | } | |
4669 | ||
c906108c SS |
4670 | /* Is this a branch with a delay slot? */ |
4671 | ||
c906108c | 4672 | static int |
acdb74a0 | 4673 | is_delayed (unsigned long insn) |
c906108c SS |
4674 | { |
4675 | int i; | |
4676 | for (i = 0; i < NUMOPCODES; ++i) | |
4677 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4678 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4679 | break; | |
4680 | return (i < NUMOPCODES | |
4681 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4682 | | INSN_COND_BRANCH_DELAY | |
4683 | | INSN_COND_BRANCH_LIKELY))); | |
4684 | } | |
4685 | ||
63807e1d | 4686 | static int |
3352ef37 AC |
4687 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
4688 | struct frame_info *frame) | |
c906108c | 4689 | { |
e17a4113 | 4690 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3352ef37 | 4691 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 4692 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
4693 | |
4694 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4695 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4696 | return 0; |
4697 | ||
6c95b8df | 4698 | if (!breakpoint_here_p (get_frame_address_space (frame), pc + 4)) |
06648491 MK |
4699 | return 0; |
4700 | ||
3352ef37 AC |
4701 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
4702 | /* If error reading memory, guess that it is not a delayed | |
4703 | branch. */ | |
c906108c | 4704 | return 0; |
e17a4113 | 4705 | return is_delayed (extract_unsigned_integer (buf, sizeof buf, byte_order)); |
c906108c SS |
4706 | } |
4707 | ||
6d82d43b AC |
4708 | /* To skip prologues, I use this predicate. Returns either PC itself |
4709 | if the code at PC does not look like a function prologue; otherwise | |
4710 | returns an address that (if we're lucky) follows the prologue. If | |
4711 | LENIENT, then we must skip everything which is involved in setting | |
4712 | up the frame (it's OK to skip more, just so long as we don't skip | |
4713 | anything which might clobber the registers which are being saved. | |
4714 | We must skip more in the case where part of the prologue is in the | |
4715 | delay slot of a non-prologue instruction). */ | |
4716 | ||
4717 | static CORE_ADDR | |
6093d2eb | 4718 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 4719 | { |
8b622e6a AC |
4720 | CORE_ADDR limit_pc; |
4721 | CORE_ADDR func_addr; | |
4722 | ||
6d82d43b AC |
4723 | /* See if we can determine the end of the prologue via the symbol table. |
4724 | If so, then return either PC, or the PC after the prologue, whichever | |
4725 | is greater. */ | |
8b622e6a AC |
4726 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4727 | { | |
d80b854b UW |
4728 | CORE_ADDR post_prologue_pc |
4729 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a AC |
4730 | if (post_prologue_pc != 0) |
4731 | return max (pc, post_prologue_pc); | |
4732 | } | |
6d82d43b AC |
4733 | |
4734 | /* Can't determine prologue from the symbol table, need to examine | |
4735 | instructions. */ | |
4736 | ||
98b4dd94 JB |
4737 | /* Find an upper limit on the function prologue using the debug |
4738 | information. If the debug information could not be used to provide | |
4739 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 4740 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
4741 | if (limit_pc == 0) |
4742 | limit_pc = pc + 100; /* Magic. */ | |
4743 | ||
0fe7e7c8 | 4744 | if (mips_pc_is_mips16 (pc)) |
e17a4113 | 4745 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
6d82d43b | 4746 | else |
e17a4113 | 4747 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
88658117 AC |
4748 | } |
4749 | ||
97ab0fdd MR |
4750 | /* Check whether the PC is in a function epilogue (32-bit version). |
4751 | This is a helper function for mips_in_function_epilogue_p. */ | |
4752 | static int | |
e17a4113 | 4753 | mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
4754 | { |
4755 | CORE_ADDR func_addr = 0, func_end = 0; | |
4756 | ||
4757 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4758 | { | |
4759 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4760 | CORE_ADDR addr = func_end - 12; | |
4761 | ||
4762 | if (addr < func_addr + 4) | |
4763 | addr = func_addr + 4; | |
4764 | if (pc < addr) | |
4765 | return 0; | |
4766 | ||
4767 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
4768 | { | |
4769 | unsigned long high_word; | |
4770 | unsigned long inst; | |
4771 | ||
e17a4113 | 4772 | inst = mips_fetch_instruction (gdbarch, pc); |
97ab0fdd MR |
4773 | high_word = (inst >> 16) & 0xffff; |
4774 | ||
4775 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
4776 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
4777 | && inst != 0x03e00008 /* jr $ra */ | |
4778 | && inst != 0x00000000) /* nop */ | |
4779 | return 0; | |
4780 | } | |
4781 | ||
4782 | return 1; | |
4783 | } | |
4784 | ||
4785 | return 0; | |
4786 | } | |
4787 | ||
4788 | /* Check whether the PC is in a function epilogue (16-bit version). | |
4789 | This is a helper function for mips_in_function_epilogue_p. */ | |
4790 | static int | |
e17a4113 | 4791 | mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
4792 | { |
4793 | CORE_ADDR func_addr = 0, func_end = 0; | |
4794 | ||
4795 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4796 | { | |
4797 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4798 | CORE_ADDR addr = func_end - 12; | |
4799 | ||
4800 | if (addr < func_addr + 4) | |
4801 | addr = func_addr + 4; | |
4802 | if (pc < addr) | |
4803 | return 0; | |
4804 | ||
4805 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
4806 | { | |
4807 | unsigned short inst; | |
4808 | ||
e17a4113 | 4809 | inst = mips_fetch_instruction (gdbarch, pc); |
97ab0fdd MR |
4810 | |
4811 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
4812 | continue; | |
4813 | ||
4814 | if (inst != 0x6300 /* addiu $sp,offset */ | |
4815 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
4816 | && inst != 0xe820 /* jr $ra */ | |
4817 | && inst != 0xe8a0 /* jrc $ra */ | |
4818 | && inst != 0x6500) /* nop */ | |
4819 | return 0; | |
4820 | } | |
4821 | ||
4822 | return 1; | |
4823 | } | |
4824 | ||
4825 | return 0; | |
4826 | } | |
4827 | ||
4828 | /* The epilogue is defined here as the area at the end of a function, | |
4829 | after an instruction which destroys the function's stack frame. */ | |
4830 | static int | |
4831 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
4832 | { | |
4833 | if (mips_pc_is_mips16 (pc)) | |
e17a4113 | 4834 | return mips16_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd | 4835 | else |
e17a4113 | 4836 | return mips32_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd MR |
4837 | } |
4838 | ||
a5ea2558 AC |
4839 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4840 | used for all MIPS-specific commands. */ | |
4841 | ||
a5ea2558 | 4842 | static void |
acdb74a0 | 4843 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4844 | { |
4845 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4846 | } | |
4847 | ||
a5ea2558 | 4848 | static void |
acdb74a0 | 4849 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 4850 | { |
6d82d43b AC |
4851 | printf_unfiltered |
4852 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
4853 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
4854 | } | |
4855 | ||
c906108c SS |
4856 | /* Commands to show/set the MIPS FPU type. */ |
4857 | ||
c906108c | 4858 | static void |
acdb74a0 | 4859 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4860 | { |
c906108c | 4861 | char *fpu; |
6ca0852e | 4862 | |
1cf3db46 | 4863 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
6ca0852e UW |
4864 | { |
4865 | printf_unfiltered | |
4866 | ("The MIPS floating-point coprocessor is unknown " | |
4867 | "because the current architecture is not MIPS.\n"); | |
4868 | return; | |
4869 | } | |
4870 | ||
1cf3db46 | 4871 | switch (MIPS_FPU_TYPE (target_gdbarch)) |
c906108c SS |
4872 | { |
4873 | case MIPS_FPU_SINGLE: | |
4874 | fpu = "single-precision"; | |
4875 | break; | |
4876 | case MIPS_FPU_DOUBLE: | |
4877 | fpu = "double-precision"; | |
4878 | break; | |
4879 | case MIPS_FPU_NONE: | |
4880 | fpu = "absent (none)"; | |
4881 | break; | |
93d56215 | 4882 | default: |
e2e0b3e5 | 4883 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
4884 | } |
4885 | if (mips_fpu_type_auto) | |
6d82d43b AC |
4886 | printf_unfiltered |
4887 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4888 | fpu); | |
c906108c | 4889 | else |
6d82d43b AC |
4890 | printf_unfiltered |
4891 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
4892 | } |
4893 | ||
4894 | ||
c906108c | 4895 | static void |
acdb74a0 | 4896 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 4897 | { |
6d82d43b AC |
4898 | printf_unfiltered |
4899 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
4900 | show_mipsfpu_command (args, from_tty); |
4901 | } | |
4902 | ||
c906108c | 4903 | static void |
acdb74a0 | 4904 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 4905 | { |
8d5838b5 AC |
4906 | struct gdbarch_info info; |
4907 | gdbarch_info_init (&info); | |
c906108c SS |
4908 | mips_fpu_type = MIPS_FPU_SINGLE; |
4909 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4910 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4911 | instead of relying on globals. Doing that would let generic code | |
4912 | handle the search for this specific architecture. */ | |
4913 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4914 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4915 | } |
4916 | ||
c906108c | 4917 | static void |
acdb74a0 | 4918 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 4919 | { |
8d5838b5 AC |
4920 | struct gdbarch_info info; |
4921 | gdbarch_info_init (&info); | |
c906108c SS |
4922 | mips_fpu_type = MIPS_FPU_DOUBLE; |
4923 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4924 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4925 | instead of relying on globals. Doing that would let generic code | |
4926 | handle the search for this specific architecture. */ | |
4927 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4928 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4929 | } |
4930 | ||
c906108c | 4931 | static void |
acdb74a0 | 4932 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 4933 | { |
8d5838b5 AC |
4934 | struct gdbarch_info info; |
4935 | gdbarch_info_init (&info); | |
c906108c SS |
4936 | mips_fpu_type = MIPS_FPU_NONE; |
4937 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4938 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4939 | instead of relying on globals. Doing that would let generic code | |
4940 | handle the search for this specific architecture. */ | |
4941 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4942 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4943 | } |
4944 | ||
c906108c | 4945 | static void |
acdb74a0 | 4946 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
4947 | { |
4948 | mips_fpu_type_auto = 1; | |
4949 | } | |
4950 | ||
c906108c | 4951 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
4952 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
4953 | the relevant processor still exists (it dates back to '94) and | |
4954 | secondly this is not the way to do this. The processor type should | |
4955 | be set by forcing an architecture change. */ | |
c906108c | 4956 | |
691c0433 AC |
4957 | void |
4958 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 4959 | { |
bb486190 UW |
4960 | struct regcache *regcache = get_current_regcache (); |
4961 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
4962 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
a9614958 | 4963 | ULONGEST prid; |
c906108c | 4964 | |
bb486190 | 4965 | regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid); |
c906108c | 4966 | if ((prid & ~0xf) == 0x700) |
691c0433 | 4967 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
4968 | } |
4969 | ||
4970 | /* Just like reinit_frame_cache, but with the right arguments to be | |
4971 | callable as an sfunc. */ | |
4972 | ||
4973 | static void | |
acdb74a0 AC |
4974 | reinit_frame_cache_sfunc (char *args, int from_tty, |
4975 | struct cmd_list_element *c) | |
c906108c SS |
4976 | { |
4977 | reinit_frame_cache (); | |
4978 | } | |
4979 | ||
a89aa300 AC |
4980 | static int |
4981 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 4982 | { |
d31431ed AC |
4983 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
4984 | disassembler needs to be able to locally determine the ISA, and | |
4985 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
4986 | work. */ | |
ec4045ea AC |
4987 | if (mips_pc_is_mips16 (memaddr)) |
4988 | info->mach = bfd_mach_mips16; | |
c906108c SS |
4989 | |
4990 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 4991 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 4992 | |
e5ab0dce | 4993 | /* Set the disassembler options. */ |
9dae60cc | 4994 | if (!info->disassembler_options) |
e5ab0dce AC |
4995 | /* This string is not recognized explicitly by the disassembler, |
4996 | but it tells the disassembler to not try to guess the ABI from | |
4997 | the bfd elf headers, such that, if the user overrides the ABI | |
4998 | of a program linked as NewABI, the disassembly will follow the | |
4999 | register naming conventions specified by the user. */ | |
5000 | info->disassembler_options = "gpr-names=32"; | |
5001 | ||
c906108c | 5002 | /* Call the appropriate disassembler based on the target endian-ness. */ |
40887e1a | 5003 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
5004 | return print_insn_big_mips (memaddr, info); |
5005 | else | |
5006 | return print_insn_little_mips (memaddr, info); | |
5007 | } | |
5008 | ||
9dae60cc UW |
5009 | static int |
5010 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) | |
5011 | { | |
5012 | /* Set up the disassembler info, so that we get the right | |
5013 | register names from libopcodes. */ | |
5014 | info->disassembler_options = "gpr-names=n32"; | |
5015 | info->flavour = bfd_target_elf_flavour; | |
5016 | ||
5017 | return gdb_print_insn_mips (memaddr, info); | |
5018 | } | |
5019 | ||
5020 | static int | |
5021 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) | |
5022 | { | |
5023 | /* Set up the disassembler info, so that we get the right | |
5024 | register names from libopcodes. */ | |
5025 | info->disassembler_options = "gpr-names=64"; | |
5026 | info->flavour = bfd_target_elf_flavour; | |
5027 | ||
5028 | return gdb_print_insn_mips (memaddr, info); | |
5029 | } | |
5030 | ||
3b3b875c UW |
5031 | /* This function implements gdbarch_breakpoint_from_pc. It uses the program |
5032 | counter value to determine whether a 16- or 32-bit breakpoint should be used. | |
5033 | It returns a pointer to a string of bytes that encode a breakpoint | |
5034 | instruction, stores the length of the string to *lenptr, and adjusts pc (if | |
5035 | necessary) to point to the actual memory location where the breakpoint | |
5036 | should be inserted. */ | |
c906108c | 5037 | |
47a35522 | 5038 | static const gdb_byte * |
67d57894 | 5039 | mips_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) |
c906108c | 5040 | { |
67d57894 | 5041 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 5042 | { |
0fe7e7c8 | 5043 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5044 | { |
47a35522 | 5045 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 5046 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5047 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5048 | return mips16_big_breakpoint; |
5049 | } | |
5050 | else | |
5051 | { | |
aaab4dba AC |
5052 | /* The IDT board uses an unusual breakpoint value, and |
5053 | sometimes gets confused when it sees the usual MIPS | |
5054 | breakpoint instruction. */ | |
47a35522 MK |
5055 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
5056 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
5057 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
f2ec0ecf JB |
5058 | /* Likewise, IRIX appears to expect a different breakpoint, |
5059 | although this is not apparent until you try to use pthreads. */ | |
5060 | static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
c906108c | 5061 | |
c5aa993b | 5062 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5063 | |
5064 | if (strcmp (target_shortname, "mips") == 0) | |
5065 | return idt_big_breakpoint; | |
5066 | else if (strcmp (target_shortname, "ddb") == 0 | |
5067 | || strcmp (target_shortname, "pmon") == 0 | |
5068 | || strcmp (target_shortname, "lsi") == 0) | |
5069 | return pmon_big_breakpoint; | |
f2ec0ecf JB |
5070 | else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX) |
5071 | return irix_big_breakpoint; | |
c906108c SS |
5072 | else |
5073 | return big_breakpoint; | |
5074 | } | |
5075 | } | |
5076 | else | |
5077 | { | |
0fe7e7c8 | 5078 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5079 | { |
47a35522 | 5080 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 5081 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5082 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5083 | return mips16_little_breakpoint; |
5084 | } | |
5085 | else | |
5086 | { | |
47a35522 MK |
5087 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5088 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
5089 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 5090 | |
c5aa993b | 5091 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5092 | |
5093 | if (strcmp (target_shortname, "mips") == 0) | |
5094 | return idt_little_breakpoint; | |
5095 | else if (strcmp (target_shortname, "ddb") == 0 | |
5096 | || strcmp (target_shortname, "pmon") == 0 | |
5097 | || strcmp (target_shortname, "lsi") == 0) | |
5098 | return pmon_little_breakpoint; | |
5099 | else | |
5100 | return little_breakpoint; | |
5101 | } | |
5102 | } | |
5103 | } | |
5104 | ||
5105 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5106 | PC, which is either the callee or the caller. There are several | |
5107 | cases which must be handled: | |
5108 | ||
5109 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5110 | target PC is in $31 ($ra). |
c906108c | 5111 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5112 | and the target PC is in $2. |
c906108c | 5113 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5114 | before the jal instruction, this is effectively a call stub |
5115 | and the the target PC is in $2. Otherwise this is effectively | |
5116 | a return stub and the target PC is in $18. | |
c906108c SS |
5117 | |
5118 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 5119 | gory details. */ |
c906108c | 5120 | |
757a7cc6 | 5121 | static CORE_ADDR |
db5f024e | 5122 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 5123 | { |
e17a4113 | 5124 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c SS |
5125 | char *name; |
5126 | CORE_ADDR start_addr; | |
5127 | ||
5128 | /* Find the starting address and name of the function containing the PC. */ | |
5129 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5130 | return 0; | |
5131 | ||
5132 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5133 | target PC is in $31 ($ra). */ | |
5134 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5135 | || strcmp (name, "__mips16_ret_df") == 0) | |
52f729a7 | 5136 | return get_frame_register_signed (frame, MIPS_RA_REGNUM); |
c906108c SS |
5137 | |
5138 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5139 | { | |
5140 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5141 | and the target PC is in $2. */ | |
5142 | if (name[19] >= '0' && name[19] <= '9') | |
52f729a7 | 5143 | return get_frame_register_signed (frame, 2); |
c906108c SS |
5144 | |
5145 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5146 | before the jal instruction, this is effectively a call stub |
5147 | and the the target PC is in $2. Otherwise this is effectively | |
5148 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5149 | else if (name[19] == 's' || name[19] == 'd') |
5150 | { | |
5151 | if (pc == start_addr) | |
5152 | { | |
5153 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5154 | stub. Such a stub for a function bar might have a name |
5155 | like __fn_stub_bar, and might look like this: | |
5156 | mfc1 $4,$f13 | |
5157 | mfc1 $5,$f12 | |
5158 | mfc1 $6,$f15 | |
5159 | mfc1 $7,$f14 | |
5160 | la $1,bar (becomes a lui/addiu pair) | |
5161 | jr $1 | |
5162 | So scan down to the lui/addi and extract the target | |
5163 | address from those two instructions. */ | |
c906108c | 5164 | |
52f729a7 | 5165 | CORE_ADDR target_pc = get_frame_register_signed (frame, 2); |
d37cca3d | 5166 | ULONGEST inst; |
c906108c SS |
5167 | int i; |
5168 | ||
5169 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
5170 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
5171 | 0) | |
c906108c SS |
5172 | return target_pc; |
5173 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5174 | && strcmp (name, "etext") != 0 | |
5175 | && strcmp (name, "_etext") != 0) | |
5176 | return target_pc; | |
5177 | ||
5178 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5179 | The limit on the search is arbitrarily set to 20 |
5180 | instructions. FIXME. */ | |
95ac2dcf | 5181 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
c906108c | 5182 | { |
e17a4113 | 5183 | inst = mips_fetch_instruction (gdbarch, target_pc); |
c5aa993b JM |
5184 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ |
5185 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5186 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5187 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5188 | } |
5189 | ||
5190 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5191 | return target_pc; | |
5192 | } | |
5193 | else | |
5194 | /* This is the 'return' part of a call stub. The return | |
5195 | address is in $r18. */ | |
52f729a7 | 5196 | return get_frame_register_signed (frame, 18); |
c906108c SS |
5197 | } |
5198 | } | |
c5aa993b | 5199 | return 0; /* not a stub */ |
c906108c SS |
5200 | } |
5201 | ||
db5f024e DJ |
5202 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
5203 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
5204 | so that $t9 has the correct value at function entry. */ | |
5205 | ||
5206 | static CORE_ADDR | |
5207 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5208 | { | |
e17a4113 UW |
5209 | struct gdbarch *gdbarch = get_frame_arch (frame); |
5210 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
db5f024e DJ |
5211 | struct minimal_symbol *msym; |
5212 | int i; | |
5213 | gdb_byte stub_code[16]; | |
5214 | int32_t stub_words[4]; | |
5215 | ||
5216 | /* The stub for foo is named ".pic.foo", and is either two | |
5217 | instructions inserted before foo or a three instruction sequence | |
5218 | which jumps to foo. */ | |
5219 | msym = lookup_minimal_symbol_by_pc (pc); | |
5220 | if (msym == NULL | |
5221 | || SYMBOL_VALUE_ADDRESS (msym) != pc | |
5222 | || SYMBOL_LINKAGE_NAME (msym) == NULL | |
5223 | || strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) != 0) | |
5224 | return 0; | |
5225 | ||
5226 | /* A two-instruction header. */ | |
5227 | if (MSYMBOL_SIZE (msym) == 8) | |
5228 | return pc + 8; | |
5229 | ||
5230 | /* A three-instruction (plus delay slot) trampoline. */ | |
5231 | if (MSYMBOL_SIZE (msym) == 16) | |
5232 | { | |
5233 | if (target_read_memory (pc, stub_code, 16) != 0) | |
5234 | return 0; | |
5235 | for (i = 0; i < 4; i++) | |
e17a4113 UW |
5236 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
5237 | 4, byte_order); | |
db5f024e DJ |
5238 | |
5239 | /* A stub contains these instructions: | |
5240 | lui t9, %hi(target) | |
5241 | j target | |
5242 | addiu t9, t9, %lo(target) | |
5243 | nop | |
5244 | ||
5245 | This works even for N64, since stubs are only generated with | |
5246 | -msym32. */ | |
5247 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
5248 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
5249 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
5250 | && stub_words[3] == 0x00000000) | |
5251 | return (((stub_words[0] & 0x0000ffff) << 16) | |
5252 | + (stub_words[2] & 0x0000ffff)); | |
5253 | } | |
5254 | ||
5255 | /* Not a recognized stub. */ | |
5256 | return 0; | |
5257 | } | |
5258 | ||
5259 | static CORE_ADDR | |
5260 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5261 | { | |
5262 | CORE_ADDR target_pc; | |
5263 | ||
5264 | target_pc = mips_skip_mips16_trampoline_code (frame, pc); | |
5265 | if (target_pc) | |
5266 | return target_pc; | |
5267 | ||
5268 | target_pc = find_solib_trampoline_target (frame, pc); | |
5269 | if (target_pc) | |
5270 | return target_pc; | |
5271 | ||
5272 | target_pc = mips_skip_pic_trampoline_code (frame, pc); | |
5273 | if (target_pc) | |
5274 | return target_pc; | |
5275 | ||
5276 | return 0; | |
5277 | } | |
5278 | ||
a4b8ebc8 | 5279 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 5280 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5281 | |
5282 | static int | |
d3f73121 | 5283 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5284 | { |
a4b8ebc8 | 5285 | int regnum; |
2f38ef89 | 5286 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5287 | regnum = num; |
2f38ef89 | 5288 | else if (num >= 38 && num < 70) |
d3f73121 | 5289 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 5290 | else if (num == 70) |
d3f73121 | 5291 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5292 | else if (num == 71) |
d3f73121 | 5293 | regnum = mips_regnum (gdbarch)->lo; |
2f38ef89 | 5294 | else |
a4b8ebc8 AC |
5295 | /* This will hopefully (eventually) provoke a warning. Should |
5296 | we be calling complaint() here? */ | |
d3f73121 MD |
5297 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5298 | return gdbarch_num_regs (gdbarch) + regnum; | |
88c72b7d AC |
5299 | } |
5300 | ||
2f38ef89 | 5301 | |
a4b8ebc8 | 5302 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 5303 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5304 | |
5305 | static int | |
d3f73121 | 5306 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5307 | { |
a4b8ebc8 | 5308 | int regnum; |
2f38ef89 | 5309 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5310 | regnum = num; |
2f38ef89 | 5311 | else if (num >= 32 && num < 64) |
d3f73121 | 5312 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 5313 | else if (num == 64) |
d3f73121 | 5314 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5315 | else if (num == 65) |
d3f73121 | 5316 | regnum = mips_regnum (gdbarch)->lo; |
2f38ef89 | 5317 | else |
a4b8ebc8 AC |
5318 | /* This will hopefully (eventually) provoke a warning. Should we |
5319 | be calling complaint() here? */ | |
d3f73121 MD |
5320 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5321 | return gdbarch_num_regs (gdbarch) + regnum; | |
a4b8ebc8 AC |
5322 | } |
5323 | ||
5324 | static int | |
e7faf938 | 5325 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
5326 | { |
5327 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 5328 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
5329 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
5330 | decide if it is valid. Should instead define a standard sim/gdb | |
5331 | register numbering scheme. */ | |
e7faf938 MD |
5332 | if (gdbarch_register_name (gdbarch, |
5333 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
5334 | && gdbarch_register_name (gdbarch, | |
5335 | gdbarch_num_regs (gdbarch) + regnum)[0] != '\0') | |
a4b8ebc8 AC |
5336 | return regnum; |
5337 | else | |
6d82d43b | 5338 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
5339 | } |
5340 | ||
2f38ef89 | 5341 | |
4844f454 CV |
5342 | /* Convert an integer into an address. Extracting the value signed |
5343 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
5344 | |
5345 | static CORE_ADDR | |
79dd2d24 | 5346 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 5347 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 5348 | { |
e17a4113 UW |
5349 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
5350 | return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); | |
fc0c74b1 AC |
5351 | } |
5352 | ||
82e91389 DJ |
5353 | /* Dummy virtual frame pointer method. This is no more or less accurate |
5354 | than most other architectures; we just need to be explicit about it, | |
5355 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
5356 | an assertion failure. */ | |
5357 | ||
5358 | static void | |
a54fba4c MD |
5359 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
5360 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
5361 | { |
5362 | *reg = MIPS_SP_REGNUM; | |
5363 | *offset = 0; | |
5364 | } | |
5365 | ||
caaa3122 DJ |
5366 | static void |
5367 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5368 | { | |
5369 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5370 | const char *name = bfd_get_section_name (abfd, sect); | |
5371 | ||
5372 | if (*abip != MIPS_ABI_UNKNOWN) | |
5373 | return; | |
5374 | ||
5375 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5376 | return; | |
5377 | ||
5378 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5379 | *abip = MIPS_ABI_O32; | |
5380 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5381 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5382 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5383 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5384 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5385 | *abip = MIPS_ABI_O64; | |
5386 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5387 | *abip = MIPS_ABI_EABI32; | |
5388 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5389 | *abip = MIPS_ABI_EABI64; | |
5390 | else | |
8a3fe4f8 | 5391 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
5392 | } |
5393 | ||
22e47e37 FF |
5394 | static void |
5395 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
5396 | { | |
5397 | int *lbp = (int *) obj; | |
5398 | const char *name = bfd_get_section_name (abfd, sect); | |
5399 | ||
5400 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
5401 | *lbp = 32; | |
5402 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
5403 | *lbp = 64; | |
5404 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
5405 | warning (_("unrecognized .gcc_compiled_longXX")); | |
5406 | } | |
5407 | ||
2e4ebe70 DJ |
5408 | static enum mips_abi |
5409 | global_mips_abi (void) | |
5410 | { | |
5411 | int i; | |
5412 | ||
5413 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5414 | if (mips_abi_strings[i] == mips_abi_string) | |
5415 | return (enum mips_abi) i; | |
5416 | ||
e2e0b3e5 | 5417 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
5418 | } |
5419 | ||
29709017 DJ |
5420 | static void |
5421 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
5422 | { | |
29709017 DJ |
5423 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
5424 | assume that's what we've got. */ | |
4eb0ad19 DJ |
5425 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
5426 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5427 | |
5428 | /* If the size matches the full set of registers GDB traditionally | |
5429 | knows about, including floating point, for either 32-bit or | |
5430 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
5431 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
5432 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5433 | |
5434 | /* Otherwise we don't have a useful guess. */ | |
5435 | } | |
5436 | ||
f8b73d13 DJ |
5437 | static struct value * |
5438 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
5439 | { | |
5440 | const int *reg_p = baton; | |
5441 | return value_of_register (*reg_p, frame); | |
5442 | } | |
5443 | ||
c2d11a7d | 5444 | static struct gdbarch * |
6d82d43b | 5445 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5446 | { |
c2d11a7d JM |
5447 | struct gdbarch *gdbarch; |
5448 | struct gdbarch_tdep *tdep; | |
5449 | int elf_flags; | |
2e4ebe70 | 5450 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 5451 | int i, num_regs; |
8d5838b5 | 5452 | enum mips_fpu_type fpu_type; |
f8b73d13 | 5453 | struct tdesc_arch_data *tdesc_data = NULL; |
609ca2b9 | 5454 | int elf_fpu_type = 0; |
f8b73d13 DJ |
5455 | |
5456 | /* Check any target description for validity. */ | |
5457 | if (tdesc_has_registers (info.target_desc)) | |
5458 | { | |
5459 | static const char *const mips_gprs[] = { | |
5460 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
5461 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
5462 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
5463 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
5464 | }; | |
5465 | static const char *const mips_fprs[] = { | |
5466 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
5467 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
5468 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
5469 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
5470 | }; | |
5471 | ||
5472 | const struct tdesc_feature *feature; | |
5473 | int valid_p; | |
5474 | ||
5475 | feature = tdesc_find_feature (info.target_desc, | |
5476 | "org.gnu.gdb.mips.cpu"); | |
5477 | if (feature == NULL) | |
5478 | return NULL; | |
5479 | ||
5480 | tdesc_data = tdesc_data_alloc (); | |
5481 | ||
5482 | valid_p = 1; | |
5483 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
5484 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
5485 | mips_gprs[i]); | |
5486 | ||
5487 | ||
5488 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5489 | MIPS_EMBED_LO_REGNUM, "lo"); | |
5490 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5491 | MIPS_EMBED_HI_REGNUM, "hi"); | |
5492 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5493 | MIPS_EMBED_PC_REGNUM, "pc"); | |
5494 | ||
5495 | if (!valid_p) | |
5496 | { | |
5497 | tdesc_data_cleanup (tdesc_data); | |
5498 | return NULL; | |
5499 | } | |
5500 | ||
5501 | feature = tdesc_find_feature (info.target_desc, | |
5502 | "org.gnu.gdb.mips.cp0"); | |
5503 | if (feature == NULL) | |
5504 | { | |
5505 | tdesc_data_cleanup (tdesc_data); | |
5506 | return NULL; | |
5507 | } | |
5508 | ||
5509 | valid_p = 1; | |
5510 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5511 | MIPS_EMBED_BADVADDR_REGNUM, | |
5512 | "badvaddr"); | |
5513 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5514 | MIPS_PS_REGNUM, "status"); | |
5515 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5516 | MIPS_EMBED_CAUSE_REGNUM, "cause"); | |
5517 | ||
5518 | if (!valid_p) | |
5519 | { | |
5520 | tdesc_data_cleanup (tdesc_data); | |
5521 | return NULL; | |
5522 | } | |
5523 | ||
5524 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
5525 | backend is not prepared for that, though. */ | |
5526 | feature = tdesc_find_feature (info.target_desc, | |
5527 | "org.gnu.gdb.mips.fpu"); | |
5528 | if (feature == NULL) | |
5529 | { | |
5530 | tdesc_data_cleanup (tdesc_data); | |
5531 | return NULL; | |
5532 | } | |
5533 | ||
5534 | valid_p = 1; | |
5535 | for (i = 0; i < 32; i++) | |
5536 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5537 | i + MIPS_EMBED_FP0_REGNUM, | |
5538 | mips_fprs[i]); | |
5539 | ||
5540 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5541 | MIPS_EMBED_FP0_REGNUM + 32, "fcsr"); | |
5542 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5543 | MIPS_EMBED_FP0_REGNUM + 33, "fir"); | |
5544 | ||
5545 | if (!valid_p) | |
5546 | { | |
5547 | tdesc_data_cleanup (tdesc_data); | |
5548 | return NULL; | |
5549 | } | |
5550 | ||
5551 | /* It would be nice to detect an attempt to use a 64-bit ABI | |
5552 | when only 32-bit registers are provided. */ | |
5553 | } | |
c2d11a7d | 5554 | |
ec03c1ac AC |
5555 | /* First of all, extract the elf_flags, if available. */ |
5556 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5557 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5558 | else if (arches != NULL) |
5559 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5560 | else |
5561 | elf_flags = 0; | |
5562 | if (gdbarch_debug) | |
5563 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5564 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5565 | |
102182a9 | 5566 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5567 | switch ((elf_flags & EF_MIPS_ABI)) |
5568 | { | |
5569 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5570 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5571 | break; |
5572 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5573 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5574 | break; |
5575 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5576 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5577 | break; |
5578 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5579 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5580 | break; |
5581 | default: | |
acdb74a0 | 5582 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5583 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5584 | else |
ec03c1ac | 5585 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5586 | break; |
5587 | } | |
acdb74a0 | 5588 | |
caaa3122 | 5589 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5590 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5591 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5592 | |
dc305454 | 5593 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
5594 | MIPS architecture (if there is one). */ |
5595 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5596 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5597 | |
32a6503c | 5598 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5599 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5600 | && info.bfd_arch_info != NULL |
5601 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5602 | { | |
5603 | switch (info.bfd_arch_info->mach) | |
5604 | { | |
5605 | case bfd_mach_mips3900: | |
ec03c1ac | 5606 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5607 | break; |
5608 | case bfd_mach_mips4100: | |
5609 | case bfd_mach_mips5000: | |
ec03c1ac | 5610 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5611 | break; |
1d06468c EZ |
5612 | case bfd_mach_mips8000: |
5613 | case bfd_mach_mips10000: | |
32a6503c KB |
5614 | /* On Irix, ELF64 executables use the N64 ABI. The |
5615 | pseudo-sections which describe the ABI aren't present | |
5616 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5617 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5618 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5619 | found_abi = MIPS_ABI_N64; |
28d169de | 5620 | else |
ec03c1ac | 5621 | found_abi = MIPS_ABI_N32; |
1d06468c | 5622 | break; |
bf64bfd6 AC |
5623 | } |
5624 | } | |
2e4ebe70 | 5625 | |
26c53e50 DJ |
5626 | /* Default 64-bit objects to N64 instead of O32. */ |
5627 | if (found_abi == MIPS_ABI_UNKNOWN | |
5628 | && info.abfd != NULL | |
5629 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
5630 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5631 | found_abi = MIPS_ABI_N64; | |
5632 | ||
ec03c1ac AC |
5633 | if (gdbarch_debug) |
5634 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5635 | found_abi); | |
5636 | ||
5637 | /* What has the user specified from the command line? */ | |
5638 | wanted_abi = global_mips_abi (); | |
5639 | if (gdbarch_debug) | |
5640 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5641 | wanted_abi); | |
2e4ebe70 DJ |
5642 | |
5643 | /* Now that we have found what the ABI for this binary would be, | |
5644 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5645 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5646 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5647 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5648 | mips_abi = found_abi; | |
5649 | else | |
5650 | mips_abi = MIPS_ABI_O32; | |
5651 | if (gdbarch_debug) | |
5652 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5653 | mips_abi); | |
2e4ebe70 | 5654 | |
ec03c1ac | 5655 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5656 | if (gdbarch_debug) |
ec03c1ac AC |
5657 | fprintf_unfiltered (gdb_stdlog, |
5658 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
5659 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 5660 | |
8d5838b5 | 5661 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
5662 | #ifdef HAVE_ELF |
5663 | if (info.abfd | |
5664 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5665 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
5666 | Tag_GNU_MIPS_ABI_FP); | |
5667 | #endif /* HAVE_ELF */ | |
5668 | ||
8d5838b5 AC |
5669 | if (!mips_fpu_type_auto) |
5670 | fpu_type = mips_fpu_type; | |
609ca2b9 DJ |
5671 | else if (elf_fpu_type != 0) |
5672 | { | |
5673 | switch (elf_fpu_type) | |
5674 | { | |
5675 | case 1: | |
5676 | fpu_type = MIPS_FPU_DOUBLE; | |
5677 | break; | |
5678 | case 2: | |
5679 | fpu_type = MIPS_FPU_SINGLE; | |
5680 | break; | |
5681 | case 3: | |
5682 | default: | |
5683 | /* Soft float or unknown. */ | |
5684 | fpu_type = MIPS_FPU_NONE; | |
5685 | break; | |
5686 | } | |
5687 | } | |
8d5838b5 AC |
5688 | else if (info.bfd_arch_info != NULL |
5689 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5690 | switch (info.bfd_arch_info->mach) | |
5691 | { | |
5692 | case bfd_mach_mips3900: | |
5693 | case bfd_mach_mips4100: | |
5694 | case bfd_mach_mips4111: | |
a9d61c86 | 5695 | case bfd_mach_mips4120: |
8d5838b5 AC |
5696 | fpu_type = MIPS_FPU_NONE; |
5697 | break; | |
5698 | case bfd_mach_mips4650: | |
5699 | fpu_type = MIPS_FPU_SINGLE; | |
5700 | break; | |
5701 | default: | |
5702 | fpu_type = MIPS_FPU_DOUBLE; | |
5703 | break; | |
5704 | } | |
5705 | else if (arches != NULL) | |
5706 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5707 | else | |
5708 | fpu_type = MIPS_FPU_DOUBLE; | |
5709 | if (gdbarch_debug) | |
5710 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5711 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5712 | |
29709017 DJ |
5713 | /* Check for blatant incompatibilities. */ |
5714 | ||
5715 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
5716 | ABI. */ | |
5717 | if (info.target_desc | |
5718 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
5719 | && mips_abi != MIPS_ABI_EABI32 | |
5720 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
5721 | { |
5722 | if (tdesc_data != NULL) | |
5723 | tdesc_data_cleanup (tdesc_data); | |
5724 | return NULL; | |
5725 | } | |
29709017 | 5726 | |
c2d11a7d JM |
5727 | /* try to find a pre-existing architecture */ |
5728 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5729 | arches != NULL; | |
5730 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5731 | { | |
5732 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5733 | using. */ |
9103eae0 | 5734 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5735 | continue; |
9103eae0 | 5736 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5737 | continue; |
719ec221 AC |
5738 | /* Need to be pedantic about which register virtual size is |
5739 | used. */ | |
5740 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5741 | != mips64_transfers_32bit_regs_p) | |
5742 | continue; | |
8d5838b5 AC |
5743 | /* Be pedantic about which FPU is selected. */ |
5744 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5745 | continue; | |
f8b73d13 DJ |
5746 | |
5747 | if (tdesc_data != NULL) | |
5748 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 5749 | return arches->gdbarch; |
c2d11a7d JM |
5750 | } |
5751 | ||
102182a9 | 5752 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5753 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5754 | gdbarch = gdbarch_alloc (&info, tdep); | |
5755 | tdep->elf_flags = elf_flags; | |
719ec221 | 5756 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5757 | tdep->found_abi = found_abi; |
5758 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5759 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
5760 | tdep->register_size_valid_p = 0; |
5761 | tdep->register_size = 0; | |
50e8a0d5 HZ |
5762 | tdep->gregset = NULL; |
5763 | tdep->gregset64 = NULL; | |
5764 | tdep->fpregset = NULL; | |
5765 | tdep->fpregset64 = NULL; | |
29709017 DJ |
5766 | |
5767 | if (info.target_desc) | |
5768 | { | |
5769 | /* Some useful properties can be inferred from the target. */ | |
5770 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
5771 | { | |
5772 | tdep->register_size_valid_p = 1; | |
5773 | tdep->register_size = 4; | |
5774 | } | |
5775 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
5776 | { | |
5777 | tdep->register_size_valid_p = 1; | |
5778 | tdep->register_size = 8; | |
5779 | } | |
5780 | } | |
c2d11a7d | 5781 | |
102182a9 | 5782 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5783 | set_gdbarch_short_bit (gdbarch, 16); |
5784 | set_gdbarch_int_bit (gdbarch, 32); | |
5785 | set_gdbarch_float_bit (gdbarch, 32); | |
5786 | set_gdbarch_double_bit (gdbarch, 64); | |
5787 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5788 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5789 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5790 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5791 | |
6d82d43b | 5792 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
5793 | mips_elf_make_msymbol_special); |
5794 | ||
16e109ca | 5795 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5796 | { |
16e109ca | 5797 | const char **reg_names; |
56cea623 AC |
5798 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5799 | struct mips_regnum); | |
f8b73d13 DJ |
5800 | if (tdesc_has_registers (info.target_desc)) |
5801 | { | |
5802 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5803 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5804 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5805 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5806 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5807 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5808 | regnum->fp_control_status = 70; | |
5809 | regnum->fp_implementation_revision = 71; | |
5810 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
5811 | reg_names = NULL; | |
5812 | } | |
5813 | else if (info.osabi == GDB_OSABI_IRIX) | |
56cea623 AC |
5814 | { |
5815 | regnum->fp0 = 32; | |
5816 | regnum->pc = 64; | |
5817 | regnum->cause = 65; | |
5818 | regnum->badvaddr = 66; | |
5819 | regnum->hi = 67; | |
5820 | regnum->lo = 68; | |
5821 | regnum->fp_control_status = 69; | |
5822 | regnum->fp_implementation_revision = 70; | |
5823 | num_regs = 71; | |
16e109ca | 5824 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5825 | } |
5826 | else | |
5827 | { | |
5828 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5829 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5830 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5831 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5832 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5833 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5834 | regnum->fp_control_status = 70; | |
5835 | regnum->fp_implementation_revision = 71; | |
5836 | num_regs = 90; | |
16e109ca AC |
5837 | if (info.bfd_arch_info != NULL |
5838 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5839 | reg_names = mips_tx39_reg_names; | |
5840 | else | |
5841 | reg_names = mips_generic_reg_names; | |
56cea623 | 5842 | } |
3e8c568d | 5843 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been |
fb14de7b | 5844 | replaced by gdbarch_read_pc? */ |
f10683bb MH |
5845 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
5846 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
5847 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
5848 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5849 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca | 5850 | set_gdbarch_register_name (gdbarch, mips_register_name); |
82e91389 | 5851 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); |
16e109ca AC |
5852 | tdep->mips_processor_reg_names = reg_names; |
5853 | tdep->regnum = regnum; | |
56cea623 | 5854 | } |
fe29b929 | 5855 | |
0dadbba0 | 5856 | switch (mips_abi) |
c2d11a7d | 5857 | { |
0dadbba0 | 5858 | case MIPS_ABI_O32: |
25ab4790 | 5859 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5860 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 5861 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5862 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5863 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5864 | set_gdbarch_long_bit (gdbarch, 32); |
5865 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5866 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5867 | break; | |
0dadbba0 | 5868 | case MIPS_ABI_O64: |
25ab4790 | 5869 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 5870 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 5871 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5872 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5873 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5874 | set_gdbarch_long_bit (gdbarch, 32); |
5875 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5876 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5877 | break; | |
0dadbba0 | 5878 | case MIPS_ABI_EABI32: |
25ab4790 | 5879 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5880 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5881 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5882 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5883 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5884 | set_gdbarch_long_bit (gdbarch, 32); |
5885 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5886 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5887 | break; | |
0dadbba0 | 5888 | case MIPS_ABI_EABI64: |
25ab4790 | 5889 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5890 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5891 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5892 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5893 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5894 | set_gdbarch_long_bit (gdbarch, 64); |
5895 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5896 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5897 | break; | |
0dadbba0 | 5898 | case MIPS_ABI_N32: |
25ab4790 | 5899 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5900 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5901 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5902 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5903 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5904 | set_gdbarch_long_bit (gdbarch, 32); |
5905 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5906 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5907 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 5908 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
5909 | break; |
5910 | case MIPS_ABI_N64: | |
25ab4790 | 5911 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5912 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5913 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5914 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5915 | tdep->default_mask_address_p = 0; |
5916 | set_gdbarch_long_bit (gdbarch, 64); | |
5917 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5918 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5919 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 5920 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 5921 | break; |
c2d11a7d | 5922 | default: |
e2e0b3e5 | 5923 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
5924 | } |
5925 | ||
22e47e37 FF |
5926 | /* GCC creates a pseudo-section whose name specifies the size of |
5927 | longs, since -mlong32 or -mlong64 may be used independent of | |
5928 | other options. How those options affect pointer sizes is ABI and | |
5929 | architecture dependent, so use them to override the default sizes | |
5930 | set by the ABI. This table shows the relationship between ABI, | |
5931 | -mlongXX, and size of pointers: | |
5932 | ||
5933 | ABI -mlongXX ptr bits | |
5934 | --- -------- -------- | |
5935 | o32 32 32 | |
5936 | o32 64 32 | |
5937 | n32 32 32 | |
5938 | n32 64 64 | |
5939 | o64 32 32 | |
5940 | o64 64 64 | |
5941 | n64 32 32 | |
5942 | n64 64 64 | |
5943 | eabi32 32 32 | |
5944 | eabi32 64 32 | |
5945 | eabi64 32 32 | |
5946 | eabi64 64 64 | |
5947 | ||
5948 | Note that for o32 and eabi32, pointers are always 32 bits | |
5949 | regardless of any -mlongXX option. For all others, pointers and | |
5950 | longs are the same, as set by -mlongXX or set by defaults. | |
5951 | */ | |
5952 | ||
5953 | if (info.abfd != NULL) | |
5954 | { | |
5955 | int long_bit = 0; | |
5956 | ||
5957 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
5958 | if (long_bit) | |
5959 | { | |
5960 | set_gdbarch_long_bit (gdbarch, long_bit); | |
5961 | switch (mips_abi) | |
5962 | { | |
5963 | case MIPS_ABI_O32: | |
5964 | case MIPS_ABI_EABI32: | |
5965 | break; | |
5966 | case MIPS_ABI_N32: | |
5967 | case MIPS_ABI_O64: | |
5968 | case MIPS_ABI_N64: | |
5969 | case MIPS_ABI_EABI64: | |
5970 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
5971 | break; | |
5972 | default: | |
5973 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
5974 | } | |
5975 | } | |
5976 | } | |
5977 | ||
a5ea2558 AC |
5978 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5979 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5980 | comment: | |
5981 | ||
5982 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5983 | flag in object files because to do so would make it impossible to | |
102182a9 | 5984 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5985 | unnecessarily restrictive. |
361d1df0 | 5986 | |
a5ea2558 AC |
5987 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5988 | but to set this flag before gcc is built with such multilibs will | |
5989 | break too many systems.'' | |
5990 | ||
5991 | But even more unhelpfully, the default linker output target for | |
5992 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5993 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5994 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5995 | this flag to detect 32-bit mode would do the wrong thing given |
5996 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5997 | as 32-bit programs by default. */ |
a5ea2558 | 5998 | |
6c997a34 | 5999 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 6000 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 6001 | |
102182a9 MS |
6002 | /* Add/remove bits from an address. The MIPS needs be careful to |
6003 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
6004 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
6005 | ||
58dfe9ff AC |
6006 | /* Unwind the frame. */ |
6007 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 6008 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 6009 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 6010 | |
102182a9 | 6011 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 6012 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
6013 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
6014 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
6015 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
6016 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 6017 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 6018 | |
c2d11a7d JM |
6019 | /* MIPS version of CALL_DUMMY */ |
6020 | ||
9710e734 AC |
6021 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
6022 | replaced by a command, and all targets will default to on stack | |
6023 | (regardless of the stack's execute status). */ | |
6024 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 6025 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 6026 | |
87783b8b AC |
6027 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
6028 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
6029 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
6030 | ||
f7b9e9fc AC |
6031 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
6032 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
6033 | |
6034 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 6035 | |
97ab0fdd MR |
6036 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
6037 | ||
fc0c74b1 AC |
6038 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
6039 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
6040 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 6041 | |
a4b8ebc8 | 6042 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 6043 | |
e11c53d2 | 6044 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 6045 | |
9dae60cc UW |
6046 | if (mips_abi == MIPS_ABI_N32) |
6047 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); | |
6048 | else if (mips_abi == MIPS_ABI_N64) | |
6049 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); | |
6050 | else | |
6051 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); | |
e5ab0dce | 6052 | |
d92524f1 PM |
6053 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
6054 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 6055 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
6056 | being used as guards for target_stopped_by_watchpoint, why not have |
6057 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
6058 | is sitting on? */ |
6059 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6060 | ||
e7d6a6d2 | 6061 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 6062 | |
3352ef37 AC |
6063 | set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay); |
6064 | ||
0d5de010 DJ |
6065 | /* Virtual tables. */ |
6066 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
6067 | ||
29709017 DJ |
6068 | mips_register_g_packet_guesses (gdbarch); |
6069 | ||
6de918a6 | 6070 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 6071 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 6072 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 6073 | |
5792a79b | 6074 | /* Unwind the frame. */ |
b8a22b94 DJ |
6075 | dwarf2_append_unwinders (gdbarch); |
6076 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
6077 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
6078 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); | |
2bd0c3d7 | 6079 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 6080 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
6081 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
6082 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 6083 | |
f8b73d13 DJ |
6084 | if (tdesc_data) |
6085 | { | |
6086 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 6087 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
6088 | |
6089 | /* Override the normal target description methods to handle our | |
6090 | dual real and pseudo registers. */ | |
6091 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
6092 | set_gdbarch_register_reggroup_p (gdbarch, mips_tdesc_register_reggroup_p); | |
6093 | ||
6094 | num_regs = gdbarch_num_regs (gdbarch); | |
6095 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
6096 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
6097 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
6098 | } | |
6099 | ||
6100 | /* Add ABI-specific aliases for the registers. */ | |
6101 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
6102 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
6103 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
6104 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
6105 | else | |
6106 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
6107 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
6108 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
6109 | ||
6110 | /* Add some other standard aliases. */ | |
6111 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
6112 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
6113 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
6114 | ||
865093a3 AR |
6115 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
6116 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
6117 | value_of_mips_user_reg, | |
6118 | &mips_numeric_register_aliases[i].regnum); | |
6119 | ||
4b9b3959 AC |
6120 | return gdbarch; |
6121 | } | |
6122 | ||
2e4ebe70 | 6123 | static void |
6d82d43b | 6124 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
6125 | { |
6126 | struct gdbarch_info info; | |
6127 | ||
6128 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6129 | mips_gdbarch_init will take care of the rest. */ | |
6130 | gdbarch_info_init (&info); | |
6131 | gdbarch_update_p (info); | |
6132 | } | |
6133 | ||
ad188201 KB |
6134 | /* Print out which MIPS ABI is in use. */ |
6135 | ||
6136 | static void | |
1f8ca57c JB |
6137 | show_mips_abi (struct ui_file *file, |
6138 | int from_tty, | |
6139 | struct cmd_list_element *ignored_cmd, | |
6140 | const char *ignored_value) | |
ad188201 | 6141 | { |
1cf3db46 | 6142 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
1f8ca57c JB |
6143 | fprintf_filtered |
6144 | (file, | |
6145 | "The MIPS ABI is unknown because the current architecture " | |
6146 | "is not MIPS.\n"); | |
ad188201 KB |
6147 | else |
6148 | { | |
6149 | enum mips_abi global_abi = global_mips_abi (); | |
1cf3db46 | 6150 | enum mips_abi actual_abi = mips_abi (target_gdbarch); |
ad188201 KB |
6151 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
6152 | ||
6153 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
6154 | fprintf_filtered |
6155 | (file, | |
6156 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 6157 | actual_abi_str); |
ad188201 | 6158 | else if (global_abi == actual_abi) |
1f8ca57c JB |
6159 | fprintf_filtered |
6160 | (file, | |
6161 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 6162 | actual_abi_str); |
ad188201 KB |
6163 | else |
6164 | { | |
6165 | /* Probably shouldn't happen... */ | |
1f8ca57c JB |
6166 | fprintf_filtered |
6167 | (file, | |
6168 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6d82d43b | 6169 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
6170 | } |
6171 | } | |
6172 | } | |
6173 | ||
4b9b3959 | 6174 | static void |
72a155b4 | 6175 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 6176 | { |
72a155b4 | 6177 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 6178 | if (tdep != NULL) |
c2d11a7d | 6179 | { |
acdb74a0 AC |
6180 | int ef_mips_arch; |
6181 | int ef_mips_32bitmode; | |
f49e4e6d | 6182 | /* Determine the ISA. */ |
acdb74a0 AC |
6183 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
6184 | { | |
6185 | case E_MIPS_ARCH_1: | |
6186 | ef_mips_arch = 1; | |
6187 | break; | |
6188 | case E_MIPS_ARCH_2: | |
6189 | ef_mips_arch = 2; | |
6190 | break; | |
6191 | case E_MIPS_ARCH_3: | |
6192 | ef_mips_arch = 3; | |
6193 | break; | |
6194 | case E_MIPS_ARCH_4: | |
93d56215 | 6195 | ef_mips_arch = 4; |
acdb74a0 AC |
6196 | break; |
6197 | default: | |
93d56215 | 6198 | ef_mips_arch = 0; |
acdb74a0 AC |
6199 | break; |
6200 | } | |
f49e4e6d | 6201 | /* Determine the size of a pointer. */ |
acdb74a0 | 6202 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
6203 | fprintf_unfiltered (file, |
6204 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6205 | tdep->elf_flags); |
4b9b3959 | 6206 | fprintf_unfiltered (file, |
acdb74a0 AC |
6207 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6208 | ef_mips_32bitmode); | |
6209 | fprintf_unfiltered (file, | |
6210 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6211 | ef_mips_arch); | |
6212 | fprintf_unfiltered (file, | |
6213 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 6214 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6215 | fprintf_unfiltered (file, |
6216 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 6217 | mips_mask_address_p (tdep), |
4014092b | 6218 | tdep->default_mask_address_p); |
c2d11a7d | 6219 | } |
4b9b3959 AC |
6220 | fprintf_unfiltered (file, |
6221 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6222 | MIPS_DEFAULT_FPU_TYPE, | |
6223 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6224 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6225 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6226 | : "???")); | |
74ed0bb4 MD |
6227 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
6228 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
6229 | fprintf_unfiltered (file, |
6230 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 MD |
6231 | MIPS_FPU_TYPE (gdbarch), |
6232 | (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" | |
6233 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" | |
6234 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" | |
4b9b3959 | 6235 | : "???")); |
c2d11a7d JM |
6236 | } |
6237 | ||
6d82d43b | 6238 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 6239 | |
c906108c | 6240 | void |
acdb74a0 | 6241 | _initialize_mips_tdep (void) |
c906108c SS |
6242 | { |
6243 | static struct cmd_list_element *mipsfpulist = NULL; | |
6244 | struct cmd_list_element *c; | |
6245 | ||
6d82d43b | 6246 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
6247 | if (MIPS_ABI_LAST + 1 |
6248 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 6249 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 6250 | |
4b9b3959 | 6251 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6252 | |
8d5f9dcb DJ |
6253 | mips_pdr_data = register_objfile_data (); |
6254 | ||
4eb0ad19 DJ |
6255 | /* Create feature sets with the appropriate properties. The values |
6256 | are not important. */ | |
6257 | mips_tdesc_gp32 = allocate_target_description (); | |
6258 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
6259 | ||
6260 | mips_tdesc_gp64 = allocate_target_description (); | |
6261 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
6262 | ||
a5ea2558 AC |
6263 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6264 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
1bedd215 | 6265 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6266 | &setmipscmdlist, "set mips ", 0, &setlist); |
6267 | ||
6268 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 6269 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6270 | &showmipscmdlist, "show mips ", 0, &showlist); |
6271 | ||
2e4ebe70 | 6272 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
6273 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
6274 | &mips_abi_string, _("\ | |
6275 | Set the MIPS ABI used by this program."), _("\ | |
6276 | Show the MIPS ABI used by this program."), _("\ | |
6277 | This option can be set to one of:\n\ | |
6278 | auto - the default ABI associated with the current binary\n\ | |
6279 | o32\n\ | |
6280 | o64\n\ | |
6281 | n32\n\ | |
6282 | n64\n\ | |
6283 | eabi32\n\ | |
6284 | eabi64"), | |
6285 | mips_abi_update, | |
6286 | show_mips_abi, | |
6287 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 6288 | |
c906108c SS |
6289 | /* Let the user turn off floating point and set the fence post for |
6290 | heuristic_proc_start. */ | |
6291 | ||
6292 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 6293 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
6294 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
6295 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 6296 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
6297 | &mipsfpulist); |
6298 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 6299 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
6300 | &mipsfpulist); |
6301 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6302 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6303 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6304 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 6305 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
6306 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
6307 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6308 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6309 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 6310 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
6311 | &mipsfpulist); |
6312 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 6313 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
6314 | &showlist); |
6315 | ||
c906108c SS |
6316 | /* We really would like to have both "0" and "unlimited" work, but |
6317 | command.c doesn't deal with that. So make it a var_zinteger | |
6318 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 6319 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
6320 | &heuristic_fence_post, _("\ |
6321 | Set the distance searched for the start of a function."), _("\ | |
6322 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
6323 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
6324 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 6325 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 6326 | reinit_frame_cache_sfunc, |
7915a72c | 6327 | NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */ |
6bcadd06 | 6328 | &setlist, &showlist); |
c906108c SS |
6329 | |
6330 | /* Allow the user to control whether the upper bits of 64-bit | |
6331 | addresses should be zeroed. */ | |
7915a72c AC |
6332 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
6333 | &mask_address_var, _("\ | |
6334 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
6335 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
cce7e648 | 6336 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
7915a72c | 6337 | allow GDB to determine the correct value."), |
08546159 AC |
6338 | NULL, show_mask_address, |
6339 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6340 | |
6341 | /* Allow the user to control the size of 32 bit registers within the | |
6342 | raw remote packet. */ | |
b3f42336 | 6343 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
6344 | &mips64_transfers_32bit_regs_p, _("\ |
6345 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6346 | _("\ | |
6347 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6348 | _("\ | |
719ec221 AC |
6349 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6350 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 6351 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 6352 | set_mips64_transfers_32bit_regs, |
7915a72c | 6353 | NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */ |
7915a72c | 6354 | &setlist, &showlist); |
9ace0497 AC |
6355 | |
6356 | /* Debug this files internals. */ | |
6bcadd06 | 6357 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
6358 | &mips_debug, _("\ |
6359 | Set mips debugging."), _("\ | |
6360 | Show mips debugging."), _("\ | |
6361 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 6362 | NULL, |
7915a72c | 6363 | NULL, /* FIXME: i18n: Mips debugging is currently %s. */ |
6bcadd06 | 6364 | &setdebuglist, &showdebuglist); |
c906108c | 6365 | } |