Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
6aba47ca DJ |
3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 | |
47a35522 | 5 | Free Software Foundation, Inc. |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2 of the License, or | |
15 | (at your option) any later version. | |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b JM |
22 | You should have received a copy of the GNU General Public License |
23 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
24 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
25 | Boston, MA 02110-1301, USA. */ | |
c906108c SS |
26 | |
27 | #include "defs.h" | |
28 | #include "gdb_string.h" | |
5e2e9765 | 29 | #include "gdb_assert.h" |
c906108c SS |
30 | #include "frame.h" |
31 | #include "inferior.h" | |
32 | #include "symtab.h" | |
33 | #include "value.h" | |
34 | #include "gdbcmd.h" | |
35 | #include "language.h" | |
36 | #include "gdbcore.h" | |
37 | #include "symfile.h" | |
38 | #include "objfiles.h" | |
39 | #include "gdbtypes.h" | |
40 | #include "target.h" | |
28d069e6 | 41 | #include "arch-utils.h" |
4e052eda | 42 | #include "regcache.h" |
70f80edf | 43 | #include "osabi.h" |
d1973055 | 44 | #include "mips-tdep.h" |
fe898f56 | 45 | #include "block.h" |
a4b8ebc8 | 46 | #include "reggroups.h" |
c906108c | 47 | #include "opcode/mips.h" |
c2d11a7d JM |
48 | #include "elf/mips.h" |
49 | #include "elf-bfd.h" | |
2475bac3 | 50 | #include "symcat.h" |
a4b8ebc8 | 51 | #include "sim-regno.h" |
a89aa300 | 52 | #include "dis-asm.h" |
edfae063 AC |
53 | #include "frame-unwind.h" |
54 | #include "frame-base.h" | |
55 | #include "trad-frame.h" | |
7d9b040b | 56 | #include "infcall.h" |
fed7ba43 | 57 | #include "floatformat.h" |
29709017 DJ |
58 | #include "remote.h" |
59 | #include "target-descriptions.h" | |
2bd0c3d7 | 60 | #include "dwarf2-frame.h" |
f8b73d13 | 61 | #include "user-regs.h" |
c906108c | 62 | |
8d5f9dcb DJ |
63 | static const struct objfile_data *mips_pdr_data; |
64 | ||
5bbcb741 | 65 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 66 | |
24e05951 | 67 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
68 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
69 | #define ST0_FR (1 << 26) | |
70 | ||
b0069a17 AC |
71 | /* The sizes of floating point registers. */ |
72 | ||
73 | enum | |
74 | { | |
75 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
76 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
77 | }; | |
78 | ||
1a69e1e4 DJ |
79 | enum |
80 | { | |
81 | MIPS32_REGSIZE = 4, | |
82 | MIPS64_REGSIZE = 8 | |
83 | }; | |
0dadbba0 | 84 | |
2e4ebe70 DJ |
85 | static const char *mips_abi_string; |
86 | ||
87 | static const char *mips_abi_strings[] = { | |
88 | "auto", | |
89 | "n32", | |
90 | "o32", | |
28d169de | 91 | "n64", |
2e4ebe70 DJ |
92 | "o64", |
93 | "eabi32", | |
94 | "eabi64", | |
95 | NULL | |
96 | }; | |
97 | ||
f8b73d13 DJ |
98 | /* The standard register names, and all the valid aliases for them. */ |
99 | struct register_alias | |
100 | { | |
101 | const char *name; | |
102 | int regnum; | |
103 | }; | |
104 | ||
105 | /* Aliases for o32 and most other ABIs. */ | |
106 | const struct register_alias mips_o32_aliases[] = { | |
107 | { "ta0", 12 }, | |
108 | { "ta1", 13 }, | |
109 | { "ta2", 14 }, | |
110 | { "ta3", 15 } | |
111 | }; | |
112 | ||
113 | /* Aliases for n32 and n64. */ | |
114 | const struct register_alias mips_n32_n64_aliases[] = { | |
115 | { "ta0", 8 }, | |
116 | { "ta1", 9 }, | |
117 | { "ta2", 10 }, | |
118 | { "ta3", 11 } | |
119 | }; | |
120 | ||
121 | /* Aliases for ABI-independent registers. */ | |
122 | const struct register_alias mips_register_aliases[] = { | |
123 | /* The architecture manuals specify these ABI-independent names for | |
124 | the GPRs. */ | |
125 | #define R(n) { "r" #n, n } | |
126 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
127 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
128 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
129 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
130 | #undef R | |
131 | ||
132 | /* k0 and k1 are sometimes called these instead (for "kernel | |
133 | temp"). */ | |
134 | { "kt0", 26 }, | |
135 | { "kt1", 27 }, | |
136 | ||
137 | /* This is the traditional GDB name for the CP0 status register. */ | |
138 | { "sr", MIPS_PS_REGNUM }, | |
139 | ||
140 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
141 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
142 | ||
143 | /* This is the traditional GDB name for the FCSR. */ | |
144 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
145 | }; | |
146 | ||
7a292a7a | 147 | /* Some MIPS boards don't support floating point while others only |
ceae6e75 | 148 | support single-precision floating-point operations. */ |
c906108c SS |
149 | |
150 | enum mips_fpu_type | |
6d82d43b AC |
151 | { |
152 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
153 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
154 | MIPS_FPU_NONE /* No floating point. */ | |
155 | }; | |
c906108c SS |
156 | |
157 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
158 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
159 | #endif | |
160 | static int mips_fpu_type_auto = 1; | |
161 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 162 | |
9ace0497 | 163 | static int mips_debug = 0; |
7a292a7a | 164 | |
29709017 DJ |
165 | /* Properties (for struct target_desc) describing the g/G packet |
166 | layout. */ | |
167 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
168 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
169 | ||
c2d11a7d JM |
170 | /* MIPS specific per-architecture information */ |
171 | struct gdbarch_tdep | |
6d82d43b AC |
172 | { |
173 | /* from the elf header */ | |
174 | int elf_flags; | |
175 | ||
176 | /* mips options */ | |
177 | enum mips_abi mips_abi; | |
178 | enum mips_abi found_abi; | |
179 | enum mips_fpu_type mips_fpu_type; | |
180 | int mips_last_arg_regnum; | |
181 | int mips_last_fp_arg_regnum; | |
6d82d43b AC |
182 | int default_mask_address_p; |
183 | /* Is the target using 64-bit raw integer registers but only | |
184 | storing a left-aligned 32-bit value in each? */ | |
185 | int mips64_transfers_32bit_regs_p; | |
186 | /* Indexes for various registers. IRIX and embedded have | |
187 | different values. This contains the "public" fields. Don't | |
188 | add any that do not need to be public. */ | |
189 | const struct mips_regnum *regnum; | |
190 | /* Register names table for the current register set. */ | |
191 | const char **mips_processor_reg_names; | |
29709017 DJ |
192 | |
193 | /* The size of register data available from the target, if known. | |
194 | This doesn't quite obsolete the manual | |
195 | mips64_transfers_32bit_regs_p, since that is documented to force | |
196 | left alignment even for big endian (very strange). */ | |
197 | int register_size_valid_p; | |
198 | int register_size; | |
6d82d43b | 199 | }; |
c2d11a7d | 200 | |
fed7ba43 JB |
201 | static int |
202 | n32n64_floatformat_always_valid (const struct floatformat *fmt, | |
2244f671 | 203 | const void *from) |
fed7ba43 JB |
204 | { |
205 | return 1; | |
206 | } | |
207 | ||
208 | /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long. | |
209 | They are implemented as a pair of 64bit doubles where the high | |
210 | part holds the result of the operation rounded to double, and | |
211 | the low double holds the difference between the exact result and | |
212 | the rounded result. So "high" + "low" contains the result with | |
213 | added precision. Unfortunately, the floatformat structure used | |
214 | by GDB is not powerful enough to describe this format. As a temporary | |
215 | measure, we define a 128bit floatformat that only uses the high part. | |
216 | We lose a bit of precision but that's probably the best we can do | |
217 | for now with the current infrastructure. */ | |
218 | ||
219 | static const struct floatformat floatformat_n32n64_long_double_big = | |
220 | { | |
221 | floatformat_big, 128, 0, 1, 11, 1023, 2047, 12, 52, | |
222 | floatformat_intbit_no, | |
8da61cc4 | 223 | "floatformat_n32n64_long_double_big", |
fed7ba43 JB |
224 | n32n64_floatformat_always_valid |
225 | }; | |
226 | ||
8da61cc4 DJ |
227 | static const struct floatformat *floatformats_n32n64_long[BFD_ENDIAN_UNKNOWN] = |
228 | { | |
229 | &floatformat_n32n64_long_double_big, | |
230 | &floatformat_n32n64_long_double_big | |
231 | }; | |
232 | ||
56cea623 AC |
233 | const struct mips_regnum * |
234 | mips_regnum (struct gdbarch *gdbarch) | |
235 | { | |
236 | return gdbarch_tdep (gdbarch)->regnum; | |
237 | } | |
238 | ||
239 | static int | |
240 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
241 | { | |
242 | return mips_regnum (gdbarch)->fp0 + 12; | |
243 | } | |
244 | ||
0dadbba0 | 245 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 246 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 247 | |
c2d11a7d | 248 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 249 | |
c2d11a7d | 250 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 251 | |
c2d11a7d | 252 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 253 | |
95404a3e AC |
254 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
255 | functions to test, set, or clear bit 0 of addresses. */ | |
256 | ||
257 | static CORE_ADDR | |
258 | is_mips16_addr (CORE_ADDR addr) | |
259 | { | |
260 | return ((addr) & 1); | |
261 | } | |
262 | ||
95404a3e AC |
263 | static CORE_ADDR |
264 | unmake_mips16_addr (CORE_ADDR addr) | |
265 | { | |
5b652102 | 266 | return ((addr) & ~(CORE_ADDR) 1); |
95404a3e AC |
267 | } |
268 | ||
22540ece AC |
269 | /* Return the contents of register REGNUM as a signed integer. */ |
270 | ||
271 | static LONGEST | |
272 | read_signed_register (int regnum) | |
273 | { | |
1d93fe1a AC |
274 | LONGEST val; |
275 | regcache_cooked_read_signed (current_regcache, regnum, &val); | |
276 | return val; | |
22540ece AC |
277 | } |
278 | ||
279 | static LONGEST | |
280 | read_signed_register_pid (int regnum, ptid_t ptid) | |
281 | { | |
282 | ptid_t save_ptid; | |
283 | LONGEST retval; | |
284 | ||
285 | if (ptid_equal (ptid, inferior_ptid)) | |
286 | return read_signed_register (regnum); | |
287 | ||
288 | save_ptid = inferior_ptid; | |
289 | ||
290 | inferior_ptid = ptid; | |
291 | ||
292 | retval = read_signed_register (regnum); | |
293 | ||
294 | inferior_ptid = save_ptid; | |
295 | ||
296 | return retval; | |
297 | } | |
298 | ||
d1973055 KB |
299 | /* Return the MIPS ABI associated with GDBARCH. */ |
300 | enum mips_abi | |
301 | mips_abi (struct gdbarch *gdbarch) | |
302 | { | |
303 | return gdbarch_tdep (gdbarch)->mips_abi; | |
304 | } | |
305 | ||
4246e332 | 306 | int |
1b13c4f6 | 307 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 308 | { |
29709017 DJ |
309 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
310 | ||
311 | /* If we know how big the registers are, use that size. */ | |
312 | if (tdep->register_size_valid_p) | |
313 | return tdep->register_size; | |
314 | ||
315 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
316 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
317 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
318 | } | |
319 | ||
480d3dd2 AC |
320 | /* Return the currently configured (or set) saved register size. */ |
321 | ||
e6bc2e8a | 322 | unsigned int |
13326b4e | 323 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 324 | { |
1a69e1e4 DJ |
325 | switch (mips_abi (gdbarch)) |
326 | { | |
327 | case MIPS_ABI_EABI32: | |
328 | case MIPS_ABI_O32: | |
329 | return 4; | |
330 | case MIPS_ABI_N32: | |
331 | case MIPS_ABI_N64: | |
332 | case MIPS_ABI_O64: | |
333 | case MIPS_ABI_EABI64: | |
334 | return 8; | |
335 | case MIPS_ABI_UNKNOWN: | |
336 | case MIPS_ABI_LAST: | |
337 | default: | |
338 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
339 | } | |
d929b26f AC |
340 | } |
341 | ||
71b8ef93 | 342 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 343 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 344 | "info" field is used for this purpose. |
5a89d8aa | 345 | |
95f1da47 | 346 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
5a89d8aa MS |
347 | i.e. refers to a 16-bit function, and sets a "special" bit in a |
348 | minimal symbol to mark it as a 16-bit function | |
349 | ||
f594e5e9 | 350 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 351 | |
5a89d8aa | 352 | static void |
6d82d43b AC |
353 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
354 | { | |
355 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
356 | { | |
357 | MSYMBOL_INFO (msym) = (char *) | |
358 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
359 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
360 | } | |
5a89d8aa MS |
361 | } |
362 | ||
71b8ef93 MS |
363 | static int |
364 | msymbol_is_special (struct minimal_symbol *msym) | |
365 | { | |
366 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
367 | } | |
368 | ||
88658117 AC |
369 | /* XFER a value from the big/little/left end of the register. |
370 | Depending on the size of the value it might occupy the entire | |
371 | register or just part of it. Make an allowance for this, aligning | |
372 | things accordingly. */ | |
373 | ||
374 | static void | |
375 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
870cd05e MK |
376 | enum bfd_endian endian, gdb_byte *in, |
377 | const gdb_byte *out, int buf_offset) | |
88658117 | 378 | { |
88658117 | 379 | int reg_offset = 0; |
f57d151a | 380 | gdb_assert (reg_num >= gdbarch_num_regs (current_gdbarch)); |
cb1d2653 AC |
381 | /* Need to transfer the left or right part of the register, based on |
382 | the targets byte order. */ | |
88658117 AC |
383 | switch (endian) |
384 | { | |
385 | case BFD_ENDIAN_BIG: | |
719ec221 | 386 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
387 | break; |
388 | case BFD_ENDIAN_LITTLE: | |
389 | reg_offset = 0; | |
390 | break; | |
6d82d43b | 391 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
392 | reg_offset = 0; |
393 | break; | |
394 | default: | |
e2e0b3e5 | 395 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
396 | } |
397 | if (mips_debug) | |
cb1d2653 AC |
398 | fprintf_unfiltered (gdb_stderr, |
399 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
400 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
401 | if (mips_debug && out != NULL) |
402 | { | |
403 | int i; | |
cb1d2653 | 404 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 405 | for (i = 0; i < length; i++) |
cb1d2653 | 406 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
407 | } |
408 | if (in != NULL) | |
6d82d43b AC |
409 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
410 | in + buf_offset); | |
88658117 | 411 | if (out != NULL) |
6d82d43b AC |
412 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
413 | out + buf_offset); | |
88658117 AC |
414 | if (mips_debug && in != NULL) |
415 | { | |
416 | int i; | |
cb1d2653 | 417 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 418 | for (i = 0; i < length; i++) |
cb1d2653 | 419 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
420 | } |
421 | if (mips_debug) | |
422 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
423 | } | |
424 | ||
dd824b04 DJ |
425 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
426 | compatiblity mode. A return value of 1 means that we have | |
427 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
428 | ||
429 | static int | |
430 | mips2_fp_compat (void) | |
431 | { | |
432 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
433 | meaningful. */ | |
6d82d43b AC |
434 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == |
435 | 4) | |
dd824b04 DJ |
436 | return 0; |
437 | ||
438 | #if 0 | |
439 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
440 | in all the places we deal with FP registers. PR gdb/413. */ | |
441 | /* Otherwise check the FR bit in the status register - it controls | |
442 | the FP compatiblity mode. If it is clear we are in compatibility | |
443 | mode. */ | |
24e05951 | 444 | if ((read_register (MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
445 | return 1; |
446 | #endif | |
361d1df0 | 447 | |
dd824b04 DJ |
448 | return 0; |
449 | } | |
450 | ||
7a292a7a | 451 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 452 | |
a14ed312 | 453 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 454 | |
a14ed312 | 455 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 456 | |
67b2c998 DJ |
457 | static struct type *mips_float_register_type (void); |
458 | static struct type *mips_double_register_type (void); | |
459 | ||
acdb74a0 AC |
460 | /* The list of available "set mips " and "show mips " commands */ |
461 | ||
462 | static struct cmd_list_element *setmipscmdlist = NULL; | |
463 | static struct cmd_list_element *showmipscmdlist = NULL; | |
464 | ||
5e2e9765 KB |
465 | /* Integer registers 0 thru 31 are handled explicitly by |
466 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 467 | are listed in the following tables. */ |
691c0433 | 468 | |
6d82d43b AC |
469 | enum |
470 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
471 | |
472 | /* Generic MIPS. */ | |
473 | ||
474 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
475 | "sr", "lo", "hi", "bad", "cause", "pc", |
476 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
477 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
478 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
479 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
480 | "fsr", "fir", "" /*"fp" */ , "", | |
481 | "", "", "", "", "", "", "", "", | |
482 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
483 | }; |
484 | ||
485 | /* Names of IDT R3041 registers. */ | |
486 | ||
487 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
488 | "sr", "lo", "hi", "bad", "cause", "pc", |
489 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
490 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
491 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
492 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
493 | "fsr", "fir", "", /*"fp" */ "", | |
494 | "", "", "bus", "ccfg", "", "", "", "", | |
495 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
496 | }; |
497 | ||
498 | /* Names of tx39 registers. */ | |
499 | ||
500 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
501 | "sr", "lo", "hi", "bad", "cause", "pc", |
502 | "", "", "", "", "", "", "", "", | |
503 | "", "", "", "", "", "", "", "", | |
504 | "", "", "", "", "", "", "", "", | |
505 | "", "", "", "", "", "", "", "", | |
506 | "", "", "", "", | |
507 | "", "", "", "", "", "", "", "", | |
508 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
509 | }; |
510 | ||
511 | /* Names of IRIX registers. */ | |
512 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
513 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
514 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
515 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
516 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
517 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
518 | }; |
519 | ||
cce74817 | 520 | |
5e2e9765 | 521 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 522 | static const char * |
5e2e9765 | 523 | mips_register_name (int regno) |
cce74817 | 524 | { |
691c0433 | 525 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
526 | /* GPR names for all ABIs other than n32/n64. */ |
527 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
528 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
529 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
530 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
531 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
532 | }; |
533 | ||
534 | /* GPR names for n32 and n64 ABIs. */ | |
535 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
536 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
537 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
538 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
539 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
540 | }; |
541 | ||
542 | enum mips_abi abi = mips_abi (current_gdbarch); | |
543 | ||
f57d151a UW |
544 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
545 | but then don't make the raw register names visible. */ | |
546 | int rawnum = regno % gdbarch_num_regs (current_gdbarch); | |
547 | if (regno < gdbarch_num_regs (current_gdbarch)) | |
a4b8ebc8 AC |
548 | return ""; |
549 | ||
5e2e9765 KB |
550 | /* The MIPS integer registers are always mapped from 0 to 31. The |
551 | names of the registers (which reflects the conventions regarding | |
552 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 553 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
554 | { |
555 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 556 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 557 | else |
a4b8ebc8 | 558 | return mips_gpr_names[rawnum]; |
5e2e9765 | 559 | } |
f8b73d13 DJ |
560 | else if (tdesc_has_registers (gdbarch_target_desc (current_gdbarch))) |
561 | return tdesc_register_name (rawnum); | |
f57d151a | 562 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (current_gdbarch)) |
691c0433 AC |
563 | { |
564 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
565 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
566 | } | |
5e2e9765 KB |
567 | else |
568 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 569 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 570 | } |
5e2e9765 | 571 | |
a4b8ebc8 | 572 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 573 | |
a4b8ebc8 AC |
574 | static int |
575 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
576 | struct reggroup *reggroup) | |
577 | { | |
578 | int vector_p; | |
579 | int float_p; | |
580 | int raw_p; | |
f57d151a UW |
581 | int rawnum = regnum % gdbarch_num_regs (current_gdbarch); |
582 | int pseudo = regnum / gdbarch_num_regs (current_gdbarch); | |
a4b8ebc8 AC |
583 | if (reggroup == all_reggroup) |
584 | return pseudo; | |
585 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
586 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
587 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
588 | (gdbarch), as not all architectures are multi-arch. */ | |
f57d151a | 589 | raw_p = rawnum < gdbarch_num_regs (current_gdbarch); |
c9f4d572 UW |
590 | if (gdbarch_register_name (current_gdbarch, regnum) == NULL |
591 | || gdbarch_register_name (current_gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
592 | return 0; |
593 | if (reggroup == float_reggroup) | |
594 | return float_p && pseudo; | |
595 | if (reggroup == vector_reggroup) | |
596 | return vector_p && pseudo; | |
597 | if (reggroup == general_reggroup) | |
598 | return (!vector_p && !float_p) && pseudo; | |
599 | /* Save the pseudo registers. Need to make certain that any code | |
600 | extracting register values from a saved register cache also uses | |
601 | pseudo registers. */ | |
602 | if (reggroup == save_reggroup) | |
603 | return raw_p && pseudo; | |
604 | /* Restore the same pseudo register. */ | |
605 | if (reggroup == restore_reggroup) | |
606 | return raw_p && pseudo; | |
6d82d43b | 607 | return 0; |
a4b8ebc8 AC |
608 | } |
609 | ||
f8b73d13 DJ |
610 | /* Return the groups that a MIPS register can be categorised into. |
611 | This version is only used if we have a target description which | |
612 | describes real registers (and their groups). */ | |
613 | ||
614 | static int | |
615 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
616 | struct reggroup *reggroup) | |
617 | { | |
618 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
619 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
620 | int ret; | |
621 | ||
622 | /* Only save, restore, and display the pseudo registers. Need to | |
623 | make certain that any code extracting register values from a | |
624 | saved register cache also uses pseudo registers. | |
625 | ||
626 | Note: saving and restoring the pseudo registers is slightly | |
627 | strange; if we have 64 bits, we should save and restore all | |
628 | 64 bits. But this is hard and has little benefit. */ | |
629 | if (!pseudo) | |
630 | return 0; | |
631 | ||
632 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
633 | if (ret != -1) | |
634 | return ret; | |
635 | ||
636 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
637 | } | |
638 | ||
a4b8ebc8 | 639 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 640 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 641 | registers. Take care of alignment and size problems. */ |
c5aa993b | 642 | |
a4b8ebc8 AC |
643 | static void |
644 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
47a35522 | 645 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 646 | { |
f57d151a UW |
647 | int rawnum = cookednum % gdbarch_num_regs (current_gdbarch); |
648 | gdb_assert (cookednum >= gdbarch_num_regs (current_gdbarch) | |
649 | && cookednum < 2 * gdbarch_num_regs (current_gdbarch)); | |
47ebcfbe | 650 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 651 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
652 | else if (register_size (gdbarch, rawnum) > |
653 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
654 | { |
655 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
4c6b5505 | 656 | || gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
657 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
658 | else | |
659 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
660 | } | |
661 | else | |
e2e0b3e5 | 662 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
663 | } |
664 | ||
665 | static void | |
6d82d43b AC |
666 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
667 | struct regcache *regcache, int cookednum, | |
47a35522 | 668 | const gdb_byte *buf) |
a4b8ebc8 | 669 | { |
f57d151a UW |
670 | int rawnum = cookednum % gdbarch_num_regs (current_gdbarch); |
671 | gdb_assert (cookednum >= gdbarch_num_regs (current_gdbarch) | |
672 | && cookednum < 2 * gdbarch_num_regs (current_gdbarch)); | |
47ebcfbe | 673 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 674 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
675 | else if (register_size (gdbarch, rawnum) > |
676 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
677 | { |
678 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
4c6b5505 | 679 | || gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
680 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
681 | else | |
682 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
683 | } | |
684 | else | |
e2e0b3e5 | 685 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 686 | } |
c5aa993b | 687 | |
c906108c | 688 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 689 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
690 | |
691 | /* Heuristic_proc_start may hunt through the text section for a long | |
692 | time across a 2400 baud serial line. Allows the user to limit this | |
693 | search. */ | |
694 | ||
695 | static unsigned int heuristic_fence_post = 0; | |
696 | ||
46cd78fb | 697 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
698 | register N. NOTE: This defines the pseudo register type so need to |
699 | rebuild the architecture vector. */ | |
43e526b9 JM |
700 | |
701 | static int mips64_transfers_32bit_regs_p = 0; | |
702 | ||
719ec221 AC |
703 | static void |
704 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
705 | struct cmd_list_element *c) | |
43e526b9 | 706 | { |
719ec221 AC |
707 | struct gdbarch_info info; |
708 | gdbarch_info_init (&info); | |
709 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
710 | instead of relying on globals. Doing that would let generic code | |
711 | handle the search for this specific architecture. */ | |
712 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 713 | { |
719ec221 | 714 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 715 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 716 | } |
a4b8ebc8 AC |
717 | } |
718 | ||
47ebcfbe | 719 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 720 | |
ff2e87ac AC |
721 | static int |
722 | mips_convert_register_p (int regnum, struct type *type) | |
723 | { | |
4c6b5505 | 724 | return (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
719ec221 | 725 | && register_size (current_gdbarch, regnum) == 4 |
f57d151a UW |
726 | && (regnum % gdbarch_num_regs (current_gdbarch)) |
727 | >= mips_regnum (current_gdbarch)->fp0 | |
728 | && (regnum % gdbarch_num_regs (current_gdbarch)) | |
729 | < mips_regnum (current_gdbarch)->fp0 + 32 | |
6d82d43b | 730 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
731 | } |
732 | ||
42c466d7 | 733 | static void |
ff2e87ac | 734 | mips_register_to_value (struct frame_info *frame, int regnum, |
47a35522 | 735 | struct type *type, gdb_byte *to) |
102182a9 | 736 | { |
47a35522 MK |
737 | get_frame_register (frame, regnum + 0, to + 4); |
738 | get_frame_register (frame, regnum + 1, to + 0); | |
102182a9 MS |
739 | } |
740 | ||
42c466d7 | 741 | static void |
ff2e87ac | 742 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 743 | struct type *type, const gdb_byte *from) |
102182a9 | 744 | { |
47a35522 MK |
745 | put_frame_register (frame, regnum + 0, from + 4); |
746 | put_frame_register (frame, regnum + 1, from + 0); | |
102182a9 MS |
747 | } |
748 | ||
a4b8ebc8 AC |
749 | /* Return the GDB type object for the "standard" data type of data in |
750 | register REG. */ | |
78fde5f8 KB |
751 | |
752 | static struct type * | |
a4b8ebc8 AC |
753 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
754 | { | |
f57d151a UW |
755 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (current_gdbarch)); |
756 | if ((regnum % gdbarch_num_regs (current_gdbarch)) | |
757 | >= mips_regnum (current_gdbarch)->fp0 | |
758 | && (regnum % gdbarch_num_regs (current_gdbarch)) | |
759 | < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 760 | { |
5ef80fb0 | 761 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 762 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 DJ |
763 | if (mips_isa_regsize (gdbarch) == 4) |
764 | return builtin_type_ieee_single; | |
765 | else | |
766 | return builtin_type_ieee_double; | |
a6425924 | 767 | } |
f57d151a | 768 | else if (regnum < gdbarch_num_regs (current_gdbarch)) |
d5ac5a39 AC |
769 | { |
770 | /* The raw or ISA registers. These are all sized according to | |
771 | the ISA regsize. */ | |
772 | if (mips_isa_regsize (gdbarch) == 4) | |
773 | return builtin_type_int32; | |
774 | else | |
775 | return builtin_type_int64; | |
776 | } | |
78fde5f8 | 777 | else |
d5ac5a39 AC |
778 | { |
779 | /* The cooked or ABI registers. These are sized according to | |
780 | the ABI (with a few complications). */ | |
f57d151a | 781 | if (regnum >= (gdbarch_num_regs (current_gdbarch) |
d5ac5a39 | 782 | + mips_regnum (current_gdbarch)->fp_control_status) |
f57d151a UW |
783 | && regnum <= gdbarch_num_regs (current_gdbarch) |
784 | + MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
785 | /* The pseudo/cooked view of the embedded registers is always |
786 | 32-bit. The raw view is handled below. */ | |
787 | return builtin_type_int32; | |
788 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
789 | /* The target, while possibly using a 64-bit register buffer, | |
790 | is only transfering 32-bits of each integer register. | |
791 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
792 | return builtin_type_int32; | |
793 | else if (mips_abi_regsize (gdbarch) == 4) | |
794 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
795 | 32- or 64-bit). */ | |
796 | return builtin_type_int32; | |
797 | else | |
798 | /* 64-bit ABI. */ | |
799 | return builtin_type_int64; | |
800 | } | |
78fde5f8 KB |
801 | } |
802 | ||
f8b73d13 DJ |
803 | /* Return the GDB type for the pseudo register REGNUM, which is the |
804 | ABI-level view. This function is only called if there is a target | |
805 | description which includes registers, so we know precisely the | |
806 | types of hardware registers. */ | |
807 | ||
808 | static struct type * | |
809 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
810 | { | |
811 | const int num_regs = gdbarch_num_regs (gdbarch); | |
812 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
813 | int rawnum = regnum % num_regs; | |
814 | struct type *rawtype; | |
815 | ||
816 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
817 | ||
818 | /* Absent registers are still absent. */ | |
819 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
820 | if (TYPE_LENGTH (rawtype) == 0) | |
821 | return rawtype; | |
822 | ||
823 | if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32) | |
824 | /* Present the floating point registers however the hardware did; | |
825 | do not try to convert between FPU layouts. */ | |
826 | return rawtype; | |
827 | ||
828 | if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
829 | { | |
830 | /* The pseudo/cooked view of embedded registers is always | |
831 | 32-bit, even if the target transfers 64-bit values for them. | |
832 | New targets relying on XML descriptions should only transfer | |
833 | the necessary 32 bits, but older versions of GDB expected 64, | |
834 | so allow the target to provide 64 bits without interfering | |
835 | with the displayed type. */ | |
836 | return builtin_type_int32; | |
837 | } | |
838 | ||
839 | /* Use pointer types for registers if we can. For n32 we can not, | |
840 | since we do not have a 64-bit pointer type. */ | |
841 | if (mips_abi_regsize (gdbarch) == TYPE_LENGTH (builtin_type_void_data_ptr)) | |
842 | { | |
843 | if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM) | |
844 | return builtin_type_void_data_ptr; | |
845 | else if (rawnum == MIPS_EMBED_PC_REGNUM) | |
846 | return builtin_type_void_func_ptr; | |
847 | } | |
848 | ||
849 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
850 | && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM) | |
851 | return builtin_type_int32; | |
852 | ||
853 | /* For all other registers, pass through the hardware type. */ | |
854 | return rawtype; | |
855 | } | |
bcb0cc15 | 856 | |
c906108c | 857 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 858 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
859 | |
860 | static int | |
480d3dd2 | 861 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
862 | { |
863 | switch (mask_address_var) | |
864 | { | |
7f19b9a2 | 865 | case AUTO_BOOLEAN_TRUE: |
4014092b | 866 | return 1; |
7f19b9a2 | 867 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
868 | return 0; |
869 | break; | |
7f19b9a2 | 870 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 871 | return tdep->default_mask_address_p; |
4014092b | 872 | default: |
e2e0b3e5 | 873 | internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch")); |
4014092b | 874 | return -1; |
361d1df0 | 875 | } |
4014092b AC |
876 | } |
877 | ||
878 | static void | |
08546159 AC |
879 | show_mask_address (struct ui_file *file, int from_tty, |
880 | struct cmd_list_element *c, const char *value) | |
4014092b | 881 | { |
480d3dd2 | 882 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
08546159 AC |
883 | |
884 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
885 | switch (mask_address_var) |
886 | { | |
7f19b9a2 | 887 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
888 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
889 | break; | |
7f19b9a2 | 890 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
891 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
892 | break; | |
7f19b9a2 | 893 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
894 | printf_filtered |
895 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
896 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
897 | break; |
898 | default: | |
e2e0b3e5 | 899 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 900 | break; |
361d1df0 | 901 | } |
4014092b | 902 | } |
c906108c | 903 | |
c906108c SS |
904 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
905 | ||
0fe7e7c8 AC |
906 | int |
907 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
908 | { |
909 | struct minimal_symbol *sym; | |
910 | ||
911 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 912 | if (is_mips16_addr (memaddr)) |
c906108c SS |
913 | return 1; |
914 | ||
915 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
916 | the high bit of the info field. Use this to decide if the function is | |
917 | MIPS16 or normal MIPS. */ | |
918 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
919 | if (sym) | |
71b8ef93 | 920 | return msymbol_is_special (sym); |
c906108c SS |
921 | else |
922 | return 0; | |
923 | } | |
924 | ||
b2fa5097 | 925 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
926 | all registers should be sign extended for simplicity? */ |
927 | ||
928 | static CORE_ADDR | |
39f77062 | 929 | mips_read_pc (ptid_t ptid) |
6c997a34 | 930 | { |
b6cb9035 AC |
931 | return read_signed_register_pid (mips_regnum (current_gdbarch)->pc, ptid); |
932 | } | |
933 | ||
58dfe9ff AC |
934 | static CORE_ADDR |
935 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
936 | { | |
edfae063 | 937 | return frame_unwind_register_signed (next_frame, |
f57d151a UW |
938 | gdbarch_num_regs (current_gdbarch) |
939 | + mips_regnum (gdbarch)->pc); | |
edfae063 AC |
940 | } |
941 | ||
30244cd8 UW |
942 | static CORE_ADDR |
943 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
944 | { | |
f57d151a UW |
945 | return frame_unwind_register_signed (next_frame, |
946 | gdbarch_num_regs (current_gdbarch) | |
947 | + MIPS_SP_REGNUM); | |
30244cd8 UW |
948 | } |
949 | ||
edfae063 AC |
950 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
951 | dummy frame. The frame ID's base needs to match the TOS value | |
952 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
953 | breakpoint. */ | |
954 | ||
955 | static struct frame_id | |
956 | mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
957 | { | |
f57d151a UW |
958 | return frame_id_build |
959 | (frame_unwind_register_signed (next_frame, | |
960 | gdbarch_num_regs (current_gdbarch) | |
961 | + MIPS_SP_REGNUM), | |
962 | frame_pc_unwind (next_frame)); | |
58dfe9ff AC |
963 | } |
964 | ||
b6cb9035 AC |
965 | static void |
966 | mips_write_pc (CORE_ADDR pc, ptid_t ptid) | |
967 | { | |
968 | write_register_pid (mips_regnum (current_gdbarch)->pc, pc, ptid); | |
6c997a34 | 969 | } |
c906108c | 970 | |
c906108c SS |
971 | /* Fetch and return instruction from the specified location. If the PC |
972 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
973 | ||
d37cca3d | 974 | static ULONGEST |
acdb74a0 | 975 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c | 976 | { |
47a35522 | 977 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
978 | int instlen; |
979 | int status; | |
980 | ||
0fe7e7c8 | 981 | if (mips_pc_is_mips16 (addr)) |
c906108c | 982 | { |
95ac2dcf | 983 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 984 | addr = unmake_mips16_addr (addr); |
c906108c SS |
985 | } |
986 | else | |
95ac2dcf | 987 | instlen = MIPS_INSN32_SIZE; |
359a9262 | 988 | status = read_memory_nobpt (addr, buf, instlen); |
c906108c SS |
989 | if (status) |
990 | memory_error (status, addr); | |
991 | return extract_unsigned_integer (buf, instlen); | |
992 | } | |
993 | ||
c906108c | 994 | /* These the fields of 32 bit mips instructions */ |
e135b889 DJ |
995 | #define mips32_op(x) (x >> 26) |
996 | #define itype_op(x) (x >> 26) | |
997 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 998 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 999 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1000 | |
e135b889 DJ |
1001 | #define jtype_op(x) (x >> 26) |
1002 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1003 | |
e135b889 DJ |
1004 | #define rtype_op(x) (x >> 26) |
1005 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1006 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1007 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1008 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1009 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 1010 | |
06987e64 MK |
1011 | static LONGEST |
1012 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 1013 | { |
06987e64 | 1014 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
1015 | } |
1016 | ||
f49e4e6d MS |
1017 | /* Determine where to set a single step breakpoint while considering |
1018 | branch prediction. */ | |
5a89d8aa | 1019 | static CORE_ADDR |
c5aa993b JM |
1020 | mips32_next_pc (CORE_ADDR pc) |
1021 | { | |
1022 | unsigned long inst; | |
1023 | int op; | |
1024 | inst = mips_fetch_instruction (pc); | |
e135b889 | 1025 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 1026 | { |
e135b889 | 1027 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1028 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1029 | { |
e135b889 | 1030 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1031 | switch (op) |
1032 | { | |
e135b889 DJ |
1033 | case 0: /* BEQL */ |
1034 | goto equal_branch; | |
1035 | case 1: /* BNEL */ | |
1036 | goto neq_branch; | |
1037 | case 2: /* BLEZL */ | |
1038 | goto less_branch; | |
1039 | case 3: /* BGTZ */ | |
1040 | goto greater_branch; | |
c5aa993b JM |
1041 | default: |
1042 | pc += 4; | |
c906108c SS |
1043 | } |
1044 | } | |
e135b889 | 1045 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1046 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
1047 | { |
1048 | int tf = itype_rt (inst) & 0x01; | |
1049 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b AC |
1050 | int fcrcs = |
1051 | read_signed_register (mips_regnum (current_gdbarch)-> | |
1052 | fp_control_status); | |
e135b889 DJ |
1053 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1054 | ||
1055 | if (((cond >> cnum) & 0x01) == tf) | |
1056 | pc += mips32_relative_offset (inst) + 4; | |
1057 | else | |
1058 | pc += 8; | |
1059 | } | |
c5aa993b JM |
1060 | else |
1061 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1062 | } |
1063 | else | |
c5aa993b JM |
1064 | { /* This gets way messy */ |
1065 | ||
c906108c | 1066 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1067 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1068 | { |
c5aa993b JM |
1069 | case 0: /* SPECIAL */ |
1070 | op = rtype_funct (inst); | |
1071 | switch (op) | |
1072 | { | |
1073 | case 8: /* JR */ | |
1074 | case 9: /* JALR */ | |
6c997a34 AC |
1075 | /* Set PC to that address */ |
1076 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
1077 | break; |
1078 | default: | |
1079 | pc += 4; | |
1080 | } | |
1081 | ||
6d82d43b | 1082 | break; /* end SPECIAL */ |
c5aa993b | 1083 | case 1: /* REGIMM */ |
c906108c | 1084 | { |
e135b889 DJ |
1085 | op = itype_rt (inst); /* branch condition */ |
1086 | switch (op) | |
c906108c | 1087 | { |
c5aa993b | 1088 | case 0: /* BLTZ */ |
e135b889 DJ |
1089 | case 2: /* BLTZL */ |
1090 | case 16: /* BLTZAL */ | |
c5aa993b | 1091 | case 18: /* BLTZALL */ |
c906108c | 1092 | less_branch: |
6c997a34 | 1093 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
1094 | pc += mips32_relative_offset (inst) + 4; |
1095 | else | |
1096 | pc += 8; /* after the delay slot */ | |
1097 | break; | |
e135b889 | 1098 | case 1: /* BGEZ */ |
c5aa993b JM |
1099 | case 3: /* BGEZL */ |
1100 | case 17: /* BGEZAL */ | |
1101 | case 19: /* BGEZALL */ | |
6c997a34 | 1102 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
1103 | pc += mips32_relative_offset (inst) + 4; |
1104 | else | |
1105 | pc += 8; /* after the delay slot */ | |
1106 | break; | |
e135b889 | 1107 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1108 | default: |
1109 | pc += 4; | |
c906108c SS |
1110 | } |
1111 | } | |
6d82d43b | 1112 | break; /* end REGIMM */ |
c5aa993b JM |
1113 | case 2: /* J */ |
1114 | case 3: /* JAL */ | |
1115 | { | |
1116 | unsigned long reg; | |
1117 | reg = jtype_target (inst) << 2; | |
e135b889 | 1118 | /* Upper four bits get never changed... */ |
5b652102 | 1119 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1120 | } |
c5aa993b JM |
1121 | break; |
1122 | /* FIXME case JALX : */ | |
1123 | { | |
1124 | unsigned long reg; | |
1125 | reg = jtype_target (inst) << 2; | |
5b652102 | 1126 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ |
c906108c SS |
1127 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1128 | } | |
c5aa993b | 1129 | break; /* The new PC will be alternate mode */ |
e135b889 | 1130 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1131 | equal_branch: |
6c997a34 AC |
1132 | if (read_signed_register (itype_rs (inst)) == |
1133 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1134 | pc += mips32_relative_offset (inst) + 4; |
1135 | else | |
1136 | pc += 8; | |
1137 | break; | |
e135b889 | 1138 | case 5: /* BNE, BNEL */ |
c5aa993b | 1139 | neq_branch: |
6c997a34 | 1140 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1141 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1142 | pc += mips32_relative_offset (inst) + 4; |
1143 | else | |
1144 | pc += 8; | |
1145 | break; | |
e135b889 | 1146 | case 6: /* BLEZ, BLEZL */ |
1fd8cd20 | 1147 | if (read_signed_register (itype_rs (inst)) <= 0) |
c5aa993b JM |
1148 | pc += mips32_relative_offset (inst) + 4; |
1149 | else | |
1150 | pc += 8; | |
1151 | break; | |
1152 | case 7: | |
e135b889 DJ |
1153 | default: |
1154 | greater_branch: /* BGTZ, BGTZL */ | |
1fd8cd20 | 1155 | if (read_signed_register (itype_rs (inst)) > 0) |
c5aa993b JM |
1156 | pc += mips32_relative_offset (inst) + 4; |
1157 | else | |
1158 | pc += 8; | |
1159 | break; | |
c5aa993b JM |
1160 | } /* switch */ |
1161 | } /* else */ | |
1162 | return pc; | |
1163 | } /* mips32_next_pc */ | |
c906108c SS |
1164 | |
1165 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1166 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1167 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1168 | We dont want to set a single step instruction on the extend instruction | |
1169 | either. | |
c5aa993b | 1170 | */ |
c906108c SS |
1171 | |
1172 | /* Lots of mips16 instruction formats */ | |
1173 | /* Predicting jumps requires itype,ritype,i8type | |
1174 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1175 | */ |
c906108c SS |
1176 | enum mips16_inst_fmts |
1177 | { | |
c5aa993b JM |
1178 | itype, /* 0 immediate 5,10 */ |
1179 | ritype, /* 1 5,3,8 */ | |
1180 | rrtype, /* 2 5,3,3,5 */ | |
1181 | rritype, /* 3 5,3,3,5 */ | |
1182 | rrrtype, /* 4 5,3,3,3,2 */ | |
1183 | rriatype, /* 5 5,3,3,1,4 */ | |
1184 | shifttype, /* 6 5,3,3,3,2 */ | |
1185 | i8type, /* 7 5,3,8 */ | |
1186 | i8movtype, /* 8 5,3,3,5 */ | |
1187 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1188 | i64type, /* 10 5,3,8 */ | |
1189 | ri64type, /* 11 5,3,3,5 */ | |
1190 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1191 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1192 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1193 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1194 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1195 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1196 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1197 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1198 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1199 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1200 | }; | |
12f02c2a AC |
1201 | /* I am heaping all the fields of the formats into one structure and |
1202 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1203 | struct upk_mips16 |
6d82d43b AC |
1204 | { |
1205 | CORE_ADDR offset; | |
1206 | unsigned int regx; /* Function in i8 type */ | |
1207 | unsigned int regy; | |
1208 | }; | |
c906108c SS |
1209 | |
1210 | ||
12f02c2a AC |
1211 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1212 | for the bits which make up the immediatate extension. */ | |
c906108c | 1213 | |
12f02c2a AC |
1214 | static CORE_ADDR |
1215 | extended_offset (unsigned int extension) | |
c906108c | 1216 | { |
12f02c2a | 1217 | CORE_ADDR value; |
c5aa993b JM |
1218 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1219 | value = value << 6; | |
1220 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1221 | value = value << 5; | |
1222 | value |= extension & 0x01f; /* extract 4:0 */ | |
1223 | return value; | |
c906108c SS |
1224 | } |
1225 | ||
1226 | /* Only call this function if you know that this is an extendable | |
1227 | instruction, It wont malfunction, but why make excess remote memory references? | |
1228 | If the immediate operands get sign extended or somthing, do it after | |
1229 | the extension is performed. | |
c5aa993b | 1230 | */ |
c906108c SS |
1231 | /* FIXME: Every one of these cases needs to worry about sign extension |
1232 | when the offset is to be used in relative addressing */ | |
1233 | ||
1234 | ||
12f02c2a | 1235 | static unsigned int |
c5aa993b | 1236 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1237 | { |
47a35522 | 1238 | gdb_byte buf[8]; |
c5aa993b JM |
1239 | pc &= 0xfffffffe; /* clear the low order bit */ |
1240 | target_read_memory (pc, buf, 2); | |
1241 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1242 | } |
1243 | ||
1244 | static void | |
c5aa993b | 1245 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1246 | unsigned int extension, |
1247 | unsigned int inst, | |
6d82d43b | 1248 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1249 | { |
12f02c2a AC |
1250 | CORE_ADDR offset; |
1251 | int regx; | |
1252 | int regy; | |
1253 | switch (insn_format) | |
c906108c | 1254 | { |
c5aa993b | 1255 | case itype: |
c906108c | 1256 | { |
12f02c2a AC |
1257 | CORE_ADDR value; |
1258 | if (extension) | |
c5aa993b JM |
1259 | { |
1260 | value = extended_offset (extension); | |
1261 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1262 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1263 | } |
1264 | else | |
c5aa993b | 1265 | { |
12f02c2a | 1266 | value = inst & 0x7ff; |
c5aa993b | 1267 | /* FIXME : Consider sign extension */ |
c906108c | 1268 | } |
12f02c2a AC |
1269 | offset = value; |
1270 | regx = -1; | |
1271 | regy = -1; | |
c906108c | 1272 | } |
c5aa993b JM |
1273 | break; |
1274 | case ritype: | |
1275 | case i8type: | |
1276 | { /* A register identifier and an offset */ | |
c906108c SS |
1277 | /* Most of the fields are the same as I type but the |
1278 | immediate value is of a different length */ | |
12f02c2a AC |
1279 | CORE_ADDR value; |
1280 | if (extension) | |
c906108c | 1281 | { |
c5aa993b JM |
1282 | value = extended_offset (extension); |
1283 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1284 | value |= inst & 0xff; /* eleven bits from instruction */ |
1285 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1286 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1287 | { | |
1288 | value &= ~0x3fff; /* remove the sign bit */ | |
1289 | value = -value; | |
c906108c SS |
1290 | } |
1291 | } | |
c5aa993b JM |
1292 | else |
1293 | { | |
12f02c2a AC |
1294 | value = inst & 0xff; /* 8 bits */ |
1295 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1296 | /* FIXME: Do sign extension , this format needs it */ |
1297 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1298 | { | |
1299 | value &= 0xef; /* remove the sign bit */ | |
1300 | value = -value; | |
1301 | } | |
c5aa993b | 1302 | } |
12f02c2a AC |
1303 | offset = value; |
1304 | regy = -1; | |
c5aa993b | 1305 | break; |
c906108c | 1306 | } |
c5aa993b | 1307 | case jalxtype: |
c906108c | 1308 | { |
c5aa993b | 1309 | unsigned long value; |
12f02c2a AC |
1310 | unsigned int nexthalf; |
1311 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1312 | value = value << 16; |
1313 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1314 | value |= nexthalf; | |
12f02c2a AC |
1315 | offset = value; |
1316 | regx = -1; | |
1317 | regy = -1; | |
c5aa993b | 1318 | break; |
c906108c SS |
1319 | } |
1320 | default: | |
e2e0b3e5 | 1321 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1322 | } |
12f02c2a AC |
1323 | upk->offset = offset; |
1324 | upk->regx = regx; | |
1325 | upk->regy = regy; | |
c906108c SS |
1326 | } |
1327 | ||
1328 | ||
c5aa993b JM |
1329 | static CORE_ADDR |
1330 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1331 | { |
5b652102 | 1332 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
1333 | } |
1334 | ||
12f02c2a AC |
1335 | static CORE_ADDR |
1336 | extended_mips16_next_pc (CORE_ADDR pc, | |
6d82d43b | 1337 | unsigned int extension, unsigned int insn) |
c906108c | 1338 | { |
12f02c2a AC |
1339 | int op = (insn >> 11); |
1340 | switch (op) | |
c906108c | 1341 | { |
6d82d43b | 1342 | case 2: /* Branch */ |
12f02c2a AC |
1343 | { |
1344 | CORE_ADDR offset; | |
1345 | struct upk_mips16 upk; | |
1346 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1347 | offset = upk.offset; | |
1348 | if (offset & 0x800) | |
1349 | { | |
1350 | offset &= 0xeff; | |
1351 | offset = -offset; | |
1352 | } | |
1353 | pc += (offset << 1) + 2; | |
1354 | break; | |
1355 | } | |
6d82d43b | 1356 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1357 | { |
1358 | struct upk_mips16 upk; | |
1359 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1360 | pc = add_offset_16 (pc, upk.offset); | |
1361 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1362 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1363 | else | |
1364 | pc |= 0x01; | |
1365 | break; | |
1366 | } | |
6d82d43b | 1367 | case 4: /* beqz */ |
12f02c2a AC |
1368 | { |
1369 | struct upk_mips16 upk; | |
1370 | int reg; | |
1371 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1372 | reg = read_signed_register (upk.regx); | |
1373 | if (reg == 0) | |
1374 | pc += (upk.offset << 1) + 2; | |
1375 | else | |
1376 | pc += 2; | |
1377 | break; | |
1378 | } | |
6d82d43b | 1379 | case 5: /* bnez */ |
12f02c2a AC |
1380 | { |
1381 | struct upk_mips16 upk; | |
1382 | int reg; | |
1383 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1384 | reg = read_signed_register (upk.regx); | |
1385 | if (reg != 0) | |
1386 | pc += (upk.offset << 1) + 2; | |
1387 | else | |
1388 | pc += 2; | |
1389 | break; | |
1390 | } | |
6d82d43b | 1391 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1392 | { |
1393 | struct upk_mips16 upk; | |
1394 | int reg; | |
1395 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1396 | /* upk.regx contains the opcode */ | |
1397 | reg = read_signed_register (24); /* Test register is 24 */ | |
1398 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1399 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1400 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1401 | pc += (upk.offset << 1) + 2; | |
1402 | else | |
1403 | pc += 2; | |
1404 | break; | |
1405 | } | |
6d82d43b | 1406 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1407 | { |
1408 | struct upk_mips16 upk; | |
1409 | /* upk.fmt = rrtype; */ | |
1410 | op = insn & 0x1f; | |
1411 | if (op == 0) | |
c5aa993b | 1412 | { |
12f02c2a AC |
1413 | int reg; |
1414 | upk.regx = (insn >> 8) & 0x07; | |
1415 | upk.regy = (insn >> 5) & 0x07; | |
1416 | switch (upk.regy) | |
c5aa993b | 1417 | { |
12f02c2a AC |
1418 | case 0: |
1419 | reg = upk.regx; | |
1420 | break; | |
1421 | case 1: | |
1422 | reg = 31; | |
6d82d43b | 1423 | break; /* Function return instruction */ |
12f02c2a AC |
1424 | case 2: |
1425 | reg = upk.regx; | |
1426 | break; | |
1427 | default: | |
1428 | reg = 31; | |
6d82d43b | 1429 | break; /* BOGUS Guess */ |
c906108c | 1430 | } |
12f02c2a | 1431 | pc = read_signed_register (reg); |
c906108c | 1432 | } |
12f02c2a | 1433 | else |
c5aa993b | 1434 | pc += 2; |
12f02c2a AC |
1435 | break; |
1436 | } | |
1437 | case 30: | |
1438 | /* This is an instruction extension. Fetch the real instruction | |
1439 | (which follows the extension) and decode things based on | |
1440 | that. */ | |
1441 | { | |
1442 | pc += 2; | |
1443 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1444 | break; | |
1445 | } | |
1446 | default: | |
1447 | { | |
1448 | pc += 2; | |
1449 | break; | |
1450 | } | |
c906108c | 1451 | } |
c5aa993b | 1452 | return pc; |
12f02c2a | 1453 | } |
c906108c | 1454 | |
5a89d8aa | 1455 | static CORE_ADDR |
12f02c2a AC |
1456 | mips16_next_pc (CORE_ADDR pc) |
1457 | { | |
1458 | unsigned int insn = fetch_mips_16 (pc); | |
1459 | return extended_mips16_next_pc (pc, 0, insn); | |
1460 | } | |
1461 | ||
1462 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1463 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1464 | It works by decoding the current instruction and predicting where a |
1465 | branch will go. This isnt hard because all the data is available. | |
1466 | The MIPS32 and MIPS16 variants are quite different */ | |
ad527d2e | 1467 | static CORE_ADDR |
c5aa993b | 1468 | mips_next_pc (CORE_ADDR pc) |
c906108c | 1469 | { |
c5aa993b JM |
1470 | if (pc & 0x01) |
1471 | return mips16_next_pc (pc); | |
1472 | else | |
1473 | return mips32_next_pc (pc); | |
12f02c2a | 1474 | } |
c906108c | 1475 | |
edfae063 AC |
1476 | struct mips_frame_cache |
1477 | { | |
1478 | CORE_ADDR base; | |
1479 | struct trad_frame_saved_reg *saved_regs; | |
1480 | }; | |
1481 | ||
29639122 JB |
1482 | /* Set a register's saved stack address in temp_saved_regs. If an |
1483 | address has already been set for this register, do nothing; this | |
1484 | way we will only recognize the first save of a given register in a | |
1485 | function prologue. | |
eec63939 | 1486 | |
f57d151a UW |
1487 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
1488 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
1489 | Strictly speaking, only the second range is used as it is only second | |
1490 | range (the ABI instead of ISA registers) that comes into play when finding | |
1491 | saved registers in a frame. */ | |
eec63939 AC |
1492 | |
1493 | static void | |
29639122 JB |
1494 | set_reg_offset (struct mips_frame_cache *this_cache, int regnum, |
1495 | CORE_ADDR offset) | |
eec63939 | 1496 | { |
29639122 JB |
1497 | if (this_cache != NULL |
1498 | && this_cache->saved_regs[regnum].addr == -1) | |
1499 | { | |
f57d151a UW |
1500 | this_cache->saved_regs[regnum |
1501 | + 0 * gdbarch_num_regs (current_gdbarch)].addr | |
1502 | = offset; | |
1503 | this_cache->saved_regs[regnum | |
1504 | + 1 * gdbarch_num_regs (current_gdbarch)].addr | |
1505 | = offset; | |
29639122 | 1506 | } |
eec63939 AC |
1507 | } |
1508 | ||
eec63939 | 1509 | |
29639122 JB |
1510 | /* Fetch the immediate value from a MIPS16 instruction. |
1511 | If the previous instruction was an EXTEND, use it to extend | |
1512 | the upper bits of the immediate value. This is a helper function | |
1513 | for mips16_scan_prologue. */ | |
eec63939 | 1514 | |
29639122 JB |
1515 | static int |
1516 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1517 | unsigned short inst, /* current instruction */ | |
1518 | int nbits, /* number of bits in imm field */ | |
1519 | int scale, /* scale factor to be applied to imm */ | |
1520 | int is_signed) /* is the imm field signed? */ | |
eec63939 | 1521 | { |
29639122 | 1522 | int offset; |
eec63939 | 1523 | |
29639122 JB |
1524 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1525 | { | |
1526 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1527 | if (offset & 0x8000) /* check for negative extend */ | |
1528 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1529 | return offset | (inst & 0x1f); | |
1530 | } | |
eec63939 | 1531 | else |
29639122 JB |
1532 | { |
1533 | int max_imm = 1 << nbits; | |
1534 | int mask = max_imm - 1; | |
1535 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1536 | |
29639122 JB |
1537 | offset = inst & mask; |
1538 | if (is_signed && (offset & sign_bit)) | |
1539 | offset = 0 - (max_imm - offset); | |
1540 | return offset * scale; | |
1541 | } | |
1542 | } | |
eec63939 | 1543 | |
65596487 | 1544 | |
29639122 JB |
1545 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1546 | the associated FRAME_CACHE if not null. | |
1547 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1548 | |
29639122 JB |
1549 | static CORE_ADDR |
1550 | mips16_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
1551 | struct frame_info *next_frame, | |
1552 | struct mips_frame_cache *this_cache) | |
1553 | { | |
1554 | CORE_ADDR cur_pc; | |
1555 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1556 | CORE_ADDR sp; | |
1557 | long frame_offset = 0; /* Size of stack frame. */ | |
1558 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1559 | int frame_reg = MIPS_SP_REGNUM; | |
1560 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1561 | unsigned inst = 0; /* current instruction */ | |
1562 | unsigned entry_inst = 0; /* the entry instruction */ | |
1563 | int reg, offset; | |
a343eb3c | 1564 | |
29639122 JB |
1565 | int extend_bytes = 0; |
1566 | int prev_extend_bytes; | |
1567 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 1568 | |
29639122 JB |
1569 | /* Can be called when there's no process, and hence when there's no |
1570 | NEXT_FRAME. */ | |
1571 | if (next_frame != NULL) | |
d2ca4222 UW |
1572 | sp = frame_unwind_register_signed (next_frame, |
1573 | gdbarch_num_regs (current_gdbarch) | |
1574 | + MIPS_SP_REGNUM); | |
29639122 JB |
1575 | else |
1576 | sp = 0; | |
eec63939 | 1577 | |
29639122 JB |
1578 | if (limit_pc > start_pc + 200) |
1579 | limit_pc = start_pc + 200; | |
eec63939 | 1580 | |
95ac2dcf | 1581 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1582 | { |
1583 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1584 | the immediate offset extension from it in mips16_get_imm. */ | |
1585 | prev_inst = inst; | |
eec63939 | 1586 | |
29639122 JB |
1587 | /* Fetch and decode the instruction. */ |
1588 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
eec63939 | 1589 | |
29639122 JB |
1590 | /* Normally we ignore extend instructions. However, if it is |
1591 | not followed by a valid prologue instruction, then this | |
1592 | instruction is not part of the prologue either. We must | |
1593 | remember in this case to adjust the end_prologue_addr back | |
1594 | over the extend. */ | |
1595 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1596 | { | |
95ac2dcf | 1597 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1598 | continue; |
1599 | } | |
eec63939 | 1600 | |
29639122 JB |
1601 | prev_extend_bytes = extend_bytes; |
1602 | extend_bytes = 0; | |
eec63939 | 1603 | |
29639122 JB |
1604 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1605 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1606 | { | |
1607 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
1608 | if (offset < 0) /* negative stack adjustment? */ | |
1609 | frame_offset -= offset; | |
1610 | else | |
1611 | /* Exit loop if a positive stack adjustment is found, which | |
1612 | usually means that the stack cleanup code in the function | |
1613 | epilogue is reached. */ | |
1614 | break; | |
1615 | } | |
1616 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1617 | { | |
1618 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1619 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
1620 | set_reg_offset (this_cache, reg, sp + offset); | |
1621 | } | |
1622 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1623 | { | |
1624 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1625 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1626 | set_reg_offset (this_cache, reg, sp + offset); | |
1627 | } | |
1628 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1629 | { | |
1630 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4c7d22cb | 1631 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1632 | } |
1633 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1634 | { | |
1635 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
4c7d22cb | 1636 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1637 | } |
1638 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1639 | { | |
1640 | frame_addr = sp; | |
1641 | frame_reg = 17; | |
1642 | } | |
1643 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1644 | { | |
1645 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1646 | frame_addr = sp + offset; | |
1647 | frame_reg = 17; | |
1648 | frame_adjust = offset; | |
1649 | } | |
1650 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1651 | { | |
1652 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1653 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1654 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1655 | } | |
1656 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1657 | { | |
1658 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1659 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1660 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1661 | } | |
1662 | else if ((inst & 0xf81f) == 0xe809 | |
1663 | && (inst & 0x700) != 0x700) /* entry */ | |
1664 | entry_inst = inst; /* save for later processing */ | |
1665 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ | |
95ac2dcf | 1666 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1667 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1668 | { | |
1669 | /* This instruction is part of the prologue, but we don't | |
1670 | need to do anything special to handle it. */ | |
1671 | } | |
1672 | else | |
1673 | { | |
1674 | /* This instruction is not an instruction typically found | |
1675 | in a prologue, so we must have reached the end of the | |
1676 | prologue. */ | |
1677 | if (end_prologue_addr == 0) | |
1678 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1679 | } | |
1680 | } | |
eec63939 | 1681 | |
29639122 JB |
1682 | /* The entry instruction is typically the first instruction in a function, |
1683 | and it stores registers at offsets relative to the value of the old SP | |
1684 | (before the prologue). But the value of the sp parameter to this | |
1685 | function is the new SP (after the prologue has been executed). So we | |
1686 | can't calculate those offsets until we've seen the entire prologue, | |
1687 | and can calculate what the old SP must have been. */ | |
1688 | if (entry_inst != 0) | |
1689 | { | |
1690 | int areg_count = (entry_inst >> 8) & 7; | |
1691 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1692 | |
29639122 JB |
1693 | /* The entry instruction always subtracts 32 from the SP. */ |
1694 | frame_offset += 32; | |
1695 | ||
1696 | /* Now we can calculate what the SP must have been at the | |
1697 | start of the function prologue. */ | |
1698 | sp += frame_offset; | |
1699 | ||
1700 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1701 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1702 | { | |
1703 | set_reg_offset (this_cache, reg, sp + offset); | |
1704 | offset += mips_abi_regsize (current_gdbarch); | |
1705 | } | |
1706 | ||
1707 | /* Check if the ra register was pushed on the stack. */ | |
1708 | offset = -4; | |
1709 | if (entry_inst & 0x20) | |
1710 | { | |
4c7d22cb | 1711 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1712 | offset -= mips_abi_regsize (current_gdbarch); |
1713 | } | |
1714 | ||
1715 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1716 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1717 | { | |
1718 | set_reg_offset (this_cache, reg, sp + offset); | |
1719 | offset -= mips_abi_regsize (current_gdbarch); | |
1720 | } | |
1721 | } | |
1722 | ||
1723 | if (this_cache != NULL) | |
1724 | { | |
1725 | this_cache->base = | |
f57d151a UW |
1726 | (frame_unwind_register_signed (next_frame, |
1727 | gdbarch_num_regs (current_gdbarch) | |
1728 | + frame_reg) | |
29639122 JB |
1729 | + frame_offset - frame_adjust); |
1730 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
1731 | be able to get rid of the assignment below, evetually. But it's | |
1732 | still needed for now. */ | |
f57d151a UW |
1733 | this_cache->saved_regs[gdbarch_num_regs (current_gdbarch) |
1734 | + mips_regnum (current_gdbarch)->pc] | |
1735 | = this_cache->saved_regs[gdbarch_num_regs (current_gdbarch) | |
1736 | + MIPS_RA_REGNUM]; | |
29639122 JB |
1737 | } |
1738 | ||
1739 | /* If we didn't reach the end of the prologue when scanning the function | |
1740 | instructions, then set end_prologue_addr to the address of the | |
1741 | instruction immediately after the last one we scanned. */ | |
1742 | if (end_prologue_addr == 0) | |
1743 | end_prologue_addr = cur_pc; | |
1744 | ||
1745 | return end_prologue_addr; | |
eec63939 AC |
1746 | } |
1747 | ||
29639122 JB |
1748 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1749 | Procedures that use the 32-bit instruction set are handled by the | |
1750 | mips_insn32 unwinder. */ | |
1751 | ||
1752 | static struct mips_frame_cache * | |
1753 | mips_insn16_frame_cache (struct frame_info *next_frame, void **this_cache) | |
eec63939 | 1754 | { |
29639122 | 1755 | struct mips_frame_cache *cache; |
eec63939 AC |
1756 | |
1757 | if ((*this_cache) != NULL) | |
1758 | return (*this_cache); | |
29639122 JB |
1759 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1760 | (*this_cache) = cache; | |
1761 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
eec63939 | 1762 | |
29639122 JB |
1763 | /* Analyze the function prologue. */ |
1764 | { | |
6de5b849 JB |
1765 | const CORE_ADDR pc = |
1766 | frame_unwind_address_in_block (next_frame, NORMAL_FRAME); | |
29639122 | 1767 | CORE_ADDR start_addr; |
eec63939 | 1768 | |
29639122 JB |
1769 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1770 | if (start_addr == 0) | |
1771 | start_addr = heuristic_proc_start (pc); | |
1772 | /* We can't analyze the prologue if we couldn't find the begining | |
1773 | of the function. */ | |
1774 | if (start_addr == 0) | |
1775 | return cache; | |
eec63939 | 1776 | |
29639122 JB |
1777 | mips16_scan_prologue (start_addr, pc, next_frame, *this_cache); |
1778 | } | |
1779 | ||
1780 | /* SP_REGNUM, contains the value and not the address. */ | |
f57d151a UW |
1781 | trad_frame_set_value (cache->saved_regs, gdbarch_num_regs (current_gdbarch) |
1782 | + MIPS_SP_REGNUM, cache->base); | |
eec63939 | 1783 | |
29639122 | 1784 | return (*this_cache); |
eec63939 AC |
1785 | } |
1786 | ||
1787 | static void | |
29639122 JB |
1788 | mips_insn16_frame_this_id (struct frame_info *next_frame, void **this_cache, |
1789 | struct frame_id *this_id) | |
eec63939 | 1790 | { |
29639122 JB |
1791 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1792 | this_cache); | |
93d42b30 DJ |
1793 | (*this_id) = frame_id_build (info->base, |
1794 | frame_func_unwind (next_frame, NORMAL_FRAME)); | |
eec63939 AC |
1795 | } |
1796 | ||
1797 | static void | |
29639122 | 1798 | mips_insn16_frame_prev_register (struct frame_info *next_frame, |
eec63939 AC |
1799 | void **this_cache, |
1800 | int regnum, int *optimizedp, | |
1801 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 1802 | int *realnump, gdb_byte *valuep) |
eec63939 | 1803 | { |
29639122 JB |
1804 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1805 | this_cache); | |
1806 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
1807 | optimizedp, lvalp, addrp, realnump, valuep); | |
eec63939 AC |
1808 | } |
1809 | ||
29639122 | 1810 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
1811 | { |
1812 | NORMAL_FRAME, | |
29639122 JB |
1813 | mips_insn16_frame_this_id, |
1814 | mips_insn16_frame_prev_register | |
eec63939 AC |
1815 | }; |
1816 | ||
1817 | static const struct frame_unwind * | |
29639122 | 1818 | mips_insn16_frame_sniffer (struct frame_info *next_frame) |
eec63939 | 1819 | { |
6de5b849 | 1820 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
0fe7e7c8 | 1821 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
1822 | return &mips_insn16_frame_unwind; |
1823 | return NULL; | |
eec63939 AC |
1824 | } |
1825 | ||
1826 | static CORE_ADDR | |
29639122 JB |
1827 | mips_insn16_frame_base_address (struct frame_info *next_frame, |
1828 | void **this_cache) | |
eec63939 | 1829 | { |
29639122 JB |
1830 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1831 | this_cache); | |
1832 | return info->base; | |
eec63939 AC |
1833 | } |
1834 | ||
29639122 | 1835 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 1836 | { |
29639122 JB |
1837 | &mips_insn16_frame_unwind, |
1838 | mips_insn16_frame_base_address, | |
1839 | mips_insn16_frame_base_address, | |
1840 | mips_insn16_frame_base_address | |
eec63939 AC |
1841 | }; |
1842 | ||
1843 | static const struct frame_base * | |
29639122 | 1844 | mips_insn16_frame_base_sniffer (struct frame_info *next_frame) |
eec63939 | 1845 | { |
29639122 JB |
1846 | if (mips_insn16_frame_sniffer (next_frame) != NULL) |
1847 | return &mips_insn16_frame_base; | |
eec63939 AC |
1848 | else |
1849 | return NULL; | |
edfae063 AC |
1850 | } |
1851 | ||
29639122 JB |
1852 | /* Mark all the registers as unset in the saved_regs array |
1853 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
1854 | ||
1855 | void | |
1856 | reset_saved_regs (struct mips_frame_cache *this_cache) | |
c906108c | 1857 | { |
29639122 JB |
1858 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
1859 | return; | |
1860 | ||
1861 | { | |
f57d151a | 1862 | const int num_regs = gdbarch_num_regs (current_gdbarch); |
29639122 | 1863 | int i; |
64159455 | 1864 | |
29639122 JB |
1865 | for (i = 0; i < num_regs; i++) |
1866 | { | |
1867 | this_cache->saved_regs[i].addr = -1; | |
1868 | } | |
1869 | } | |
c906108c SS |
1870 | } |
1871 | ||
29639122 JB |
1872 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1873 | the associated FRAME_CACHE if not null. | |
1874 | Return the address of the first instruction past the prologue. */ | |
c906108c | 1875 | |
875e1767 | 1876 | static CORE_ADDR |
29639122 JB |
1877 | mips32_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1878 | struct frame_info *next_frame, | |
1879 | struct mips_frame_cache *this_cache) | |
c906108c | 1880 | { |
29639122 JB |
1881 | CORE_ADDR cur_pc; |
1882 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
1883 | CORE_ADDR sp; | |
1884 | long frame_offset; | |
1885 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 1886 | |
29639122 JB |
1887 | CORE_ADDR end_prologue_addr = 0; |
1888 | int seen_sp_adjust = 0; | |
1889 | int load_immediate_bytes = 0; | |
8fa9cfa1 | 1890 | |
29639122 JB |
1891 | /* Can be called when there's no process, and hence when there's no |
1892 | NEXT_FRAME. */ | |
1893 | if (next_frame != NULL) | |
d2ca4222 UW |
1894 | sp = frame_unwind_register_signed (next_frame, |
1895 | gdbarch_num_regs (current_gdbarch) | |
1896 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 1897 | else |
29639122 | 1898 | sp = 0; |
9022177c | 1899 | |
29639122 JB |
1900 | if (limit_pc > start_pc + 200) |
1901 | limit_pc = start_pc + 200; | |
9022177c | 1902 | |
29639122 | 1903 | restart: |
9022177c | 1904 | |
29639122 | 1905 | frame_offset = 0; |
95ac2dcf | 1906 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 1907 | { |
29639122 JB |
1908 | unsigned long inst, high_word, low_word; |
1909 | int reg; | |
9022177c | 1910 | |
29639122 JB |
1911 | /* Fetch the instruction. */ |
1912 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
9022177c | 1913 | |
29639122 JB |
1914 | /* Save some code by pre-extracting some useful fields. */ |
1915 | high_word = (inst >> 16) & 0xffff; | |
1916 | low_word = inst & 0xffff; | |
1917 | reg = high_word & 0x1f; | |
fe29b929 | 1918 | |
29639122 JB |
1919 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
1920 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
1921 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1922 | { | |
1923 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
1924 | frame_offset += 0x10000 - low_word; | |
1925 | else | |
1926 | /* Exit loop if a positive stack adjustment is found, which | |
1927 | usually means that the stack cleanup code in the function | |
1928 | epilogue is reached. */ | |
1929 | break; | |
1930 | seen_sp_adjust = 1; | |
1931 | } | |
1932 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
1933 | { | |
1934 | set_reg_offset (this_cache, reg, sp + low_word); | |
1935 | } | |
1936 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
1937 | { | |
1938 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
1939 | set_reg_offset (this_cache, reg, sp + low_word); | |
1940 | } | |
1941 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
1942 | { | |
1943 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
1944 | if ((long) low_word != frame_offset) | |
1945 | frame_addr = sp + low_word; | |
d2ca4222 | 1946 | else if (next_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
1947 | { |
1948 | unsigned alloca_adjust; | |
a4b8ebc8 | 1949 | |
29639122 | 1950 | frame_reg = 30; |
d2ca4222 UW |
1951 | frame_addr = frame_unwind_register_signed |
1952 | (next_frame, | |
1953 | gdbarch_num_regs (current_gdbarch) + 30); | |
1954 | ||
29639122 JB |
1955 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
1956 | if (alloca_adjust > 0) | |
1957 | { | |
1958 | /* FP > SP + frame_size. This may be because of | |
1959 | an alloca or somethings similar. Fix sp to | |
1960 | "pre-alloca" value, and try again. */ | |
1961 | sp += alloca_adjust; | |
1962 | /* Need to reset the status of all registers. Otherwise, | |
1963 | we will hit a guard that prevents the new address | |
1964 | for each register to be recomputed during the second | |
1965 | pass. */ | |
1966 | reset_saved_regs (this_cache); | |
1967 | goto restart; | |
1968 | } | |
1969 | } | |
1970 | } | |
1971 | /* move $30,$sp. With different versions of gas this will be either | |
1972 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
1973 | Accept any one of these. */ | |
1974 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
1975 | { | |
1976 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
d2ca4222 | 1977 | if (next_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
1978 | { |
1979 | unsigned alloca_adjust; | |
c906108c | 1980 | |
29639122 | 1981 | frame_reg = 30; |
d2ca4222 UW |
1982 | frame_addr = frame_unwind_register_signed |
1983 | (next_frame, | |
1984 | gdbarch_num_regs (current_gdbarch) + 30); | |
1985 | ||
29639122 JB |
1986 | alloca_adjust = (unsigned) (frame_addr - sp); |
1987 | if (alloca_adjust > 0) | |
1988 | { | |
1989 | /* FP > SP + frame_size. This may be because of | |
1990 | an alloca or somethings similar. Fix sp to | |
1991 | "pre-alloca" value, and try again. */ | |
1992 | sp = frame_addr; | |
1993 | /* Need to reset the status of all registers. Otherwise, | |
1994 | we will hit a guard that prevents the new address | |
1995 | for each register to be recomputed during the second | |
1996 | pass. */ | |
1997 | reset_saved_regs (this_cache); | |
1998 | goto restart; | |
1999 | } | |
2000 | } | |
2001 | } | |
2002 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ | |
2003 | { | |
2004 | set_reg_offset (this_cache, reg, frame_addr + low_word); | |
2005 | } | |
2006 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
2007 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
2008 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
2009 | || high_word == 0x3c1c /* lui $gp,n */ | |
2010 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
2011 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
2012 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
2013 | ) | |
2014 | { | |
2015 | /* These instructions are part of the prologue, but we don't | |
2016 | need to do anything special to handle them. */ | |
2017 | } | |
2018 | /* The instructions below load $at or $t0 with an immediate | |
2019 | value in preparation for a stack adjustment via | |
2020 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
2021 | initialize a local variable, so we accept them only before | |
2022 | a stack adjustment instruction was seen. */ | |
2023 | else if (!seen_sp_adjust | |
2024 | && (high_word == 0x3c01 /* lui $at,n */ | |
2025 | || high_word == 0x3c08 /* lui $t0,n */ | |
2026 | || high_word == 0x3421 /* ori $at,$at,n */ | |
2027 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
2028 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
2029 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
2030 | )) | |
2031 | { | |
95ac2dcf | 2032 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
29639122 JB |
2033 | } |
2034 | else | |
2035 | { | |
2036 | /* This instruction is not an instruction typically found | |
2037 | in a prologue, so we must have reached the end of the | |
2038 | prologue. */ | |
2039 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
2040 | loop now? Why would we need to continue scanning the function | |
2041 | instructions? */ | |
2042 | if (end_prologue_addr == 0) | |
2043 | end_prologue_addr = cur_pc; | |
2044 | } | |
a4b8ebc8 | 2045 | } |
c906108c | 2046 | |
29639122 JB |
2047 | if (this_cache != NULL) |
2048 | { | |
2049 | this_cache->base = | |
f57d151a UW |
2050 | (frame_unwind_register_signed (next_frame, |
2051 | gdbarch_num_regs (current_gdbarch) | |
2052 | + frame_reg) | |
29639122 JB |
2053 | + frame_offset); |
2054 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2055 | this assignment below, eventually. But it's still needed | |
2056 | for now. */ | |
f57d151a UW |
2057 | this_cache->saved_regs[gdbarch_num_regs (current_gdbarch) |
2058 | + mips_regnum (current_gdbarch)->pc] | |
2059 | = this_cache->saved_regs[gdbarch_num_regs (current_gdbarch) | |
2060 | + MIPS_RA_REGNUM]; | |
29639122 | 2061 | } |
c906108c | 2062 | |
29639122 JB |
2063 | /* If we didn't reach the end of the prologue when scanning the function |
2064 | instructions, then set end_prologue_addr to the address of the | |
2065 | instruction immediately after the last one we scanned. */ | |
2066 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2067 | we may as well be careful and do our best if we have a null | |
2068 | end_prologue_addr. */ | |
2069 | if (end_prologue_addr == 0) | |
2070 | end_prologue_addr = cur_pc; | |
2071 | ||
2072 | /* In a frameless function, we might have incorrectly | |
2073 | skipped some load immediate instructions. Undo the skipping | |
2074 | if the load immediate was not followed by a stack adjustment. */ | |
2075 | if (load_immediate_bytes && !seen_sp_adjust) | |
2076 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2077 | |
29639122 | 2078 | return end_prologue_addr; |
c906108c SS |
2079 | } |
2080 | ||
29639122 JB |
2081 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2082 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2083 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2084 | unwinder. */ | |
c906108c | 2085 | |
29639122 JB |
2086 | static struct mips_frame_cache * |
2087 | mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache) | |
c906108c | 2088 | { |
29639122 | 2089 | struct mips_frame_cache *cache; |
c906108c | 2090 | |
29639122 JB |
2091 | if ((*this_cache) != NULL) |
2092 | return (*this_cache); | |
c5aa993b | 2093 | |
29639122 JB |
2094 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2095 | (*this_cache) = cache; | |
2096 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
c5aa993b | 2097 | |
29639122 JB |
2098 | /* Analyze the function prologue. */ |
2099 | { | |
6de5b849 JB |
2100 | const CORE_ADDR pc = |
2101 | frame_unwind_address_in_block (next_frame, NORMAL_FRAME); | |
29639122 | 2102 | CORE_ADDR start_addr; |
c906108c | 2103 | |
29639122 JB |
2104 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2105 | if (start_addr == 0) | |
2106 | start_addr = heuristic_proc_start (pc); | |
2107 | /* We can't analyze the prologue if we couldn't find the begining | |
2108 | of the function. */ | |
2109 | if (start_addr == 0) | |
2110 | return cache; | |
c5aa993b | 2111 | |
29639122 JB |
2112 | mips32_scan_prologue (start_addr, pc, next_frame, *this_cache); |
2113 | } | |
2114 | ||
2115 | /* SP_REGNUM, contains the value and not the address. */ | |
f57d151a UW |
2116 | trad_frame_set_value (cache->saved_regs, |
2117 | gdbarch_num_regs (current_gdbarch) + MIPS_SP_REGNUM, | |
2118 | cache->base); | |
c5aa993b | 2119 | |
29639122 | 2120 | return (*this_cache); |
c906108c SS |
2121 | } |
2122 | ||
29639122 JB |
2123 | static void |
2124 | mips_insn32_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2125 | struct frame_id *this_id) | |
c906108c | 2126 | { |
29639122 JB |
2127 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
2128 | this_cache); | |
93d42b30 DJ |
2129 | (*this_id) = frame_id_build (info->base, |
2130 | frame_func_unwind (next_frame, NORMAL_FRAME)); | |
29639122 | 2131 | } |
c906108c | 2132 | |
29639122 JB |
2133 | static void |
2134 | mips_insn32_frame_prev_register (struct frame_info *next_frame, | |
2135 | void **this_cache, | |
2136 | int regnum, int *optimizedp, | |
2137 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 2138 | int *realnump, gdb_byte *valuep) |
29639122 JB |
2139 | { |
2140 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, | |
2141 | this_cache); | |
2142 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
2143 | optimizedp, lvalp, addrp, realnump, valuep); | |
c906108c SS |
2144 | } |
2145 | ||
29639122 JB |
2146 | static const struct frame_unwind mips_insn32_frame_unwind = |
2147 | { | |
2148 | NORMAL_FRAME, | |
2149 | mips_insn32_frame_this_id, | |
2150 | mips_insn32_frame_prev_register | |
2151 | }; | |
c906108c | 2152 | |
29639122 JB |
2153 | static const struct frame_unwind * |
2154 | mips_insn32_frame_sniffer (struct frame_info *next_frame) | |
2155 | { | |
6de5b849 | 2156 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
0fe7e7c8 | 2157 | if (! mips_pc_is_mips16 (pc)) |
29639122 JB |
2158 | return &mips_insn32_frame_unwind; |
2159 | return NULL; | |
2160 | } | |
c906108c | 2161 | |
1c645fec | 2162 | static CORE_ADDR |
29639122 JB |
2163 | mips_insn32_frame_base_address (struct frame_info *next_frame, |
2164 | void **this_cache) | |
c906108c | 2165 | { |
29639122 JB |
2166 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
2167 | this_cache); | |
2168 | return info->base; | |
2169 | } | |
c906108c | 2170 | |
29639122 JB |
2171 | static const struct frame_base mips_insn32_frame_base = |
2172 | { | |
2173 | &mips_insn32_frame_unwind, | |
2174 | mips_insn32_frame_base_address, | |
2175 | mips_insn32_frame_base_address, | |
2176 | mips_insn32_frame_base_address | |
2177 | }; | |
1c645fec | 2178 | |
29639122 JB |
2179 | static const struct frame_base * |
2180 | mips_insn32_frame_base_sniffer (struct frame_info *next_frame) | |
2181 | { | |
2182 | if (mips_insn32_frame_sniffer (next_frame) != NULL) | |
2183 | return &mips_insn32_frame_base; | |
a65bbe44 | 2184 | else |
29639122 JB |
2185 | return NULL; |
2186 | } | |
a65bbe44 | 2187 | |
29639122 JB |
2188 | static struct trad_frame_cache * |
2189 | mips_stub_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2190 | { | |
2191 | CORE_ADDR pc; | |
2192 | CORE_ADDR start_addr; | |
2193 | CORE_ADDR stack_addr; | |
2194 | struct trad_frame_cache *this_trad_cache; | |
c906108c | 2195 | |
29639122 JB |
2196 | if ((*this_cache) != NULL) |
2197 | return (*this_cache); | |
2198 | this_trad_cache = trad_frame_cache_zalloc (next_frame); | |
2199 | (*this_cache) = this_trad_cache; | |
1c645fec | 2200 | |
29639122 | 2201 | /* The return address is in the link register. */ |
4c7d22cb | 2202 | trad_frame_set_reg_realreg (this_trad_cache, PC_REGNUM, MIPS_RA_REGNUM); |
1c645fec | 2203 | |
29639122 JB |
2204 | /* Frame ID, since it's a frameless / stackless function, no stack |
2205 | space is allocated and SP on entry is the current SP. */ | |
2206 | pc = frame_pc_unwind (next_frame); | |
2207 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
4c7d22cb | 2208 | stack_addr = frame_unwind_register_signed (next_frame, MIPS_SP_REGNUM); |
29639122 | 2209 | trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr)); |
1c645fec | 2210 | |
29639122 JB |
2211 | /* Assume that the frame's base is the same as the |
2212 | stack-pointer. */ | |
2213 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2214 | |
29639122 JB |
2215 | return this_trad_cache; |
2216 | } | |
c906108c | 2217 | |
29639122 JB |
2218 | static void |
2219 | mips_stub_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2220 | struct frame_id *this_id) | |
2221 | { | |
2222 | struct trad_frame_cache *this_trad_cache | |
2223 | = mips_stub_frame_cache (next_frame, this_cache); | |
2224 | trad_frame_get_id (this_trad_cache, this_id); | |
2225 | } | |
c906108c | 2226 | |
29639122 JB |
2227 | static void |
2228 | mips_stub_frame_prev_register (struct frame_info *next_frame, | |
2229 | void **this_cache, | |
2230 | int regnum, int *optimizedp, | |
2231 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 2232 | int *realnump, gdb_byte *valuep) |
29639122 JB |
2233 | { |
2234 | struct trad_frame_cache *this_trad_cache | |
2235 | = mips_stub_frame_cache (next_frame, this_cache); | |
2236 | trad_frame_get_register (this_trad_cache, next_frame, regnum, optimizedp, | |
2237 | lvalp, addrp, realnump, valuep); | |
2238 | } | |
c906108c | 2239 | |
29639122 JB |
2240 | static const struct frame_unwind mips_stub_frame_unwind = |
2241 | { | |
2242 | NORMAL_FRAME, | |
2243 | mips_stub_frame_this_id, | |
2244 | mips_stub_frame_prev_register | |
2245 | }; | |
c906108c | 2246 | |
29639122 JB |
2247 | static const struct frame_unwind * |
2248 | mips_stub_frame_sniffer (struct frame_info *next_frame) | |
2249 | { | |
979b38e0 | 2250 | struct obj_section *s; |
93d42b30 | 2251 | CORE_ADDR pc = frame_unwind_address_in_block (next_frame, NORMAL_FRAME); |
979b38e0 | 2252 | |
29639122 JB |
2253 | if (in_plt_section (pc, NULL)) |
2254 | return &mips_stub_frame_unwind; | |
979b38e0 DJ |
2255 | |
2256 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2257 | s = find_pc_section (pc); | |
2258 | ||
2259 | if (s != NULL | |
2260 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2261 | ".MIPS.stubs") == 0) | |
2262 | return &mips_stub_frame_unwind; | |
2263 | ||
2264 | return NULL; | |
29639122 | 2265 | } |
c906108c | 2266 | |
29639122 JB |
2267 | static CORE_ADDR |
2268 | mips_stub_frame_base_address (struct frame_info *next_frame, | |
2269 | void **this_cache) | |
2270 | { | |
2271 | struct trad_frame_cache *this_trad_cache | |
2272 | = mips_stub_frame_cache (next_frame, this_cache); | |
2273 | return trad_frame_get_this_base (this_trad_cache); | |
2274 | } | |
0fce0821 | 2275 | |
29639122 JB |
2276 | static const struct frame_base mips_stub_frame_base = |
2277 | { | |
2278 | &mips_stub_frame_unwind, | |
2279 | mips_stub_frame_base_address, | |
2280 | mips_stub_frame_base_address, | |
2281 | mips_stub_frame_base_address | |
2282 | }; | |
2283 | ||
2284 | static const struct frame_base * | |
2285 | mips_stub_frame_base_sniffer (struct frame_info *next_frame) | |
2286 | { | |
2287 | if (mips_stub_frame_sniffer (next_frame) != NULL) | |
2288 | return &mips_stub_frame_base; | |
2289 | else | |
2290 | return NULL; | |
2291 | } | |
2292 | ||
29639122 | 2293 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2294 | |
29639122 JB |
2295 | static CORE_ADDR |
2296 | mips_addr_bits_remove (CORE_ADDR addr) | |
65596487 | 2297 | { |
29639122 JB |
2298 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2299 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) | |
2300 | /* This hack is a work-around for existing boards using PMON, the | |
2301 | simulator, and any other 64-bit targets that doesn't have true | |
2302 | 64-bit addressing. On these targets, the upper 32 bits of | |
2303 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2304 | likely to have been sign extended to all 1s by instruction | |
2305 | sequences that load 32-bit addresses. For example, a typical | |
2306 | piece of code that loads an address is this: | |
65596487 | 2307 | |
29639122 JB |
2308 | lui $r2, <upper 16 bits> |
2309 | ori $r2, <lower 16 bits> | |
65596487 | 2310 | |
29639122 JB |
2311 | But the lui sign-extends the value such that the upper 32 bits |
2312 | may be all 1s. The workaround is simply to mask off these | |
2313 | bits. In the future, gcc may be changed to support true 64-bit | |
2314 | addressing, and this masking will have to be disabled. */ | |
2315 | return addr &= 0xffffffffUL; | |
2316 | else | |
2317 | return addr; | |
65596487 JB |
2318 | } |
2319 | ||
29639122 JB |
2320 | /* mips_software_single_step() is called just before we want to resume |
2321 | the inferior, if we want to single-step it but there is no hardware | |
2322 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 2323 | the target of the coming instruction and breakpoint it. */ |
29639122 | 2324 | |
e6590a1b | 2325 | int |
e0cd558a | 2326 | mips_software_single_step (struct regcache *regcache) |
c906108c | 2327 | { |
8181d85f | 2328 | CORE_ADDR pc, next_pc; |
65596487 | 2329 | |
e0cd558a UW |
2330 | pc = read_register (mips_regnum (current_gdbarch)->pc); |
2331 | next_pc = mips_next_pc (pc); | |
e6590a1b | 2332 | |
e0cd558a | 2333 | insert_single_step_breakpoint (next_pc); |
e6590a1b | 2334 | return 1; |
29639122 | 2335 | } |
a65bbe44 | 2336 | |
29639122 JB |
2337 | /* Test whether the PC points to the return instruction at the |
2338 | end of a function. */ | |
65596487 | 2339 | |
29639122 JB |
2340 | static int |
2341 | mips_about_to_return (CORE_ADDR pc) | |
2342 | { | |
0fe7e7c8 | 2343 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2344 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2345 | generates a "jr $ra"; other times it generates code to load | |
2346 | the return address from the stack to an accessible register (such | |
2347 | as $a3), then a "jr" using that register. This second case | |
2348 | is almost impossible to distinguish from an indirect jump | |
2349 | used for switch statements, so we don't even try. */ | |
2350 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
2351 | else | |
2352 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
2353 | } | |
c906108c | 2354 | |
c906108c | 2355 | |
29639122 JB |
2356 | /* This fencepost looks highly suspicious to me. Removing it also |
2357 | seems suspicious as it could affect remote debugging across serial | |
2358 | lines. */ | |
c906108c | 2359 | |
29639122 JB |
2360 | static CORE_ADDR |
2361 | heuristic_proc_start (CORE_ADDR pc) | |
2362 | { | |
2363 | CORE_ADDR start_pc; | |
2364 | CORE_ADDR fence; | |
2365 | int instlen; | |
2366 | int seen_adjsp = 0; | |
65596487 | 2367 | |
bf6ae464 | 2368 | pc = gdbarch_addr_bits_remove (current_gdbarch, pc); |
29639122 JB |
2369 | start_pc = pc; |
2370 | fence = start_pc - heuristic_fence_post; | |
2371 | if (start_pc == 0) | |
2372 | return 0; | |
65596487 | 2373 | |
29639122 JB |
2374 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2375 | fence = VM_MIN_ADDRESS; | |
65596487 | 2376 | |
95ac2dcf | 2377 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2378 | |
29639122 JB |
2379 | /* search back for previous return */ |
2380 | for (start_pc -= instlen;; start_pc -= instlen) | |
2381 | if (start_pc < fence) | |
2382 | { | |
2383 | /* It's not clear to me why we reach this point when | |
2384 | stop_soon, but with this test, at least we | |
2385 | don't print out warnings for every child forked (eg, on | |
2386 | decstation). 22apr93 rich@cygnus.com. */ | |
2387 | if (stop_soon == NO_STOP_QUIETLY) | |
2388 | { | |
2389 | static int blurb_printed = 0; | |
98b4dd94 | 2390 | |
8a3fe4f8 | 2391 | warning (_("GDB can't find the start of the function at 0x%s."), |
29639122 JB |
2392 | paddr_nz (pc)); |
2393 | ||
2394 | if (!blurb_printed) | |
2395 | { | |
2396 | /* This actually happens frequently in embedded | |
2397 | development, when you first connect to a board | |
2398 | and your stack pointer and pc are nowhere in | |
2399 | particular. This message needs to give people | |
2400 | in that situation enough information to | |
2401 | determine that it's no big deal. */ | |
2402 | printf_filtered ("\n\ | |
2403 | GDB is unable to find the start of the function at 0x%s\n\ | |
2404 | and thus can't determine the size of that function's stack frame.\n\ | |
2405 | This means that GDB may be unable to access that stack frame, or\n\ | |
2406 | the frames below it.\n\ | |
2407 | This problem is most likely caused by an invalid program counter or\n\ | |
2408 | stack pointer.\n\ | |
2409 | However, if you think GDB should simply search farther back\n\ | |
2410 | from 0x%s for code which looks like the beginning of a\n\ | |
2411 | function, you can increase the range of the search using the `set\n\ | |
2412 | heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); | |
2413 | blurb_printed = 1; | |
2414 | } | |
2415 | } | |
2416 | ||
2417 | return 0; | |
2418 | } | |
0fe7e7c8 | 2419 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2420 | { |
2421 | unsigned short inst; | |
2422 | ||
2423 | /* On MIPS16, any one of the following is likely to be the | |
2424 | start of a function: | |
2425 | entry | |
2426 | addiu sp,-n | |
2427 | daddiu sp,-n | |
2428 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
2429 | inst = mips_fetch_instruction (start_pc); | |
2430 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
2431 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2432 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2433 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
2434 | break; | |
2435 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2436 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2437 | seen_adjsp = 1; | |
2438 | else | |
2439 | seen_adjsp = 0; | |
2440 | } | |
2441 | else if (mips_about_to_return (start_pc)) | |
2442 | { | |
4c7d22cb | 2443 | /* Skip return and its delay slot. */ |
95ac2dcf | 2444 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2445 | break; |
2446 | } | |
2447 | ||
2448 | return start_pc; | |
c906108c SS |
2449 | } |
2450 | ||
6c0d6680 DJ |
2451 | struct mips_objfile_private |
2452 | { | |
2453 | bfd_size_type size; | |
2454 | char *contents; | |
2455 | }; | |
2456 | ||
f09ded24 AC |
2457 | /* According to the current ABI, should the type be passed in a |
2458 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 2459 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 AC |
2460 | FP registers and, consequently this returns false - forces FP |
2461 | arguments into integer registers. */ | |
2462 | ||
2463 | static int | |
2464 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2465 | { | |
2466 | return ((typecode == TYPE_CODE_FLT | |
2467 | || (MIPS_EABI | |
6d82d43b AC |
2468 | && (typecode == TYPE_CODE_STRUCT |
2469 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 2470 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
2471 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
2472 | == TYPE_CODE_FLT)) | |
c86b5b38 | 2473 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2474 | } |
2475 | ||
49e790b0 DJ |
2476 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2477 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2478 | ||
2479 | static int | |
2480 | mips_type_needs_double_align (struct type *type) | |
2481 | { | |
2482 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2483 | |
49e790b0 DJ |
2484 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2485 | return 1; | |
2486 | else if (typecode == TYPE_CODE_STRUCT) | |
2487 | { | |
2488 | if (TYPE_NFIELDS (type) < 1) | |
2489 | return 0; | |
2490 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2491 | } | |
2492 | else if (typecode == TYPE_CODE_UNION) | |
2493 | { | |
361d1df0 | 2494 | int i, n; |
49e790b0 DJ |
2495 | |
2496 | n = TYPE_NFIELDS (type); | |
2497 | for (i = 0; i < n; i++) | |
2498 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2499 | return 1; | |
2500 | return 0; | |
2501 | } | |
2502 | return 0; | |
2503 | } | |
2504 | ||
dc604539 AC |
2505 | /* Adjust the address downward (direction of stack growth) so that it |
2506 | is correctly aligned for a new stack frame. */ | |
2507 | static CORE_ADDR | |
2508 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2509 | { | |
5b03f266 | 2510 | return align_down (addr, 16); |
dc604539 AC |
2511 | } |
2512 | ||
f7ab6ec6 | 2513 | static CORE_ADDR |
7d9b040b | 2514 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2515 | struct regcache *regcache, CORE_ADDR bp_addr, |
2516 | int nargs, struct value **args, CORE_ADDR sp, | |
2517 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2518 | { |
2519 | int argreg; | |
2520 | int float_argreg; | |
2521 | int argnum; | |
2522 | int len = 0; | |
2523 | int stack_offset = 0; | |
480d3dd2 | 2524 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2525 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 2526 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 2527 | |
25ab4790 AC |
2528 | /* For shared libraries, "t9" needs to point at the function |
2529 | address. */ | |
4c7d22cb | 2530 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2531 | |
2532 | /* Set the return address register to point to the entry point of | |
2533 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2534 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2535 | |
c906108c | 2536 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2537 | are properly aligned. The stack has to be at least 64-bit |
2538 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2539 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2540 | aligned, so we round to this widest known alignment. */ | |
2541 | ||
5b03f266 AC |
2542 | sp = align_down (sp, 16); |
2543 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2544 | |
46e0f506 | 2545 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2546 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2547 | passed in registers, but that's OK. */ |
c906108c | 2548 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 2549 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 2550 | sp -= align_up (len, 16); |
c906108c | 2551 | |
9ace0497 | 2552 | if (mips_debug) |
6d82d43b | 2553 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2554 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2555 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2556 | |
c906108c | 2557 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2558 | argreg = MIPS_A0_REGNUM; |
56cea623 | 2559 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 2560 | |
46e0f506 | 2561 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2562 | if (struct_return) |
9ace0497 AC |
2563 | { |
2564 | if (mips_debug) | |
2565 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2566 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2567 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
2568 | write_register (argreg++, struct_addr); |
2569 | } | |
c906108c SS |
2570 | |
2571 | /* Now load as many as possible of the first arguments into | |
2572 | registers, and push the rest onto the stack. Loop thru args | |
2573 | from first to last. */ | |
2574 | for (argnum = 0; argnum < nargs; argnum++) | |
2575 | { | |
47a35522 MK |
2576 | const gdb_byte *val; |
2577 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 2578 | struct value *arg = args[argnum]; |
4991999e | 2579 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
2580 | int len = TYPE_LENGTH (arg_type); |
2581 | enum type_code typecode = TYPE_CODE (arg_type); | |
2582 | ||
9ace0497 AC |
2583 | if (mips_debug) |
2584 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2585 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2586 | argnum + 1, len, (int) typecode); |
9ace0497 | 2587 | |
c906108c | 2588 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2589 | reference. */ |
1a69e1e4 | 2590 | if (len > regsize |
9ace0497 | 2591 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2592 | { |
1a69e1e4 | 2593 | store_unsigned_integer (valbuf, regsize, VALUE_ADDRESS (arg)); |
c906108c | 2594 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 2595 | len = regsize; |
c906108c | 2596 | val = valbuf; |
9ace0497 AC |
2597 | if (mips_debug) |
2598 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2599 | } |
2600 | else | |
47a35522 | 2601 | val = value_contents (arg); |
c906108c SS |
2602 | |
2603 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2604 | even-numbered floating point register. Round the FP register |
2605 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2606 | left. Non MIPS_EABI targets also pass the FP in the integer |
2607 | registers so also round up normal registers. */ | |
1a69e1e4 | 2608 | if (regsize < 8 && fp_register_arg_p (typecode, arg_type)) |
acdb74a0 AC |
2609 | { |
2610 | if ((float_argreg & 1)) | |
2611 | float_argreg++; | |
2612 | } | |
c906108c SS |
2613 | |
2614 | /* Floating point arguments passed in registers have to be | |
2615 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2616 | are passed in register pairs; the even register gets |
2617 | the low word, and the odd register gets the high word. | |
2618 | On non-EABI processors, the first two floating point arguments are | |
2619 | also copied to general registers, because MIPS16 functions | |
2620 | don't use float registers for arguments. This duplication of | |
2621 | arguments in general registers can't hurt non-MIPS16 functions | |
2622 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2623 | /* MIPS_EABI squeezes a struct that contains a single floating |
2624 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2625 | stack. */ |
f09ded24 AC |
2626 | if (fp_register_arg_p (typecode, arg_type) |
2627 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c | 2628 | { |
6da397e0 KB |
2629 | /* EABI32 will pass doubles in consecutive registers, even on |
2630 | 64-bit cores. At one time, we used to check the size of | |
2631 | `float_argreg' to determine whether or not to pass doubles | |
2632 | in consecutive registers, but this is not sufficient for | |
2633 | making the ABI determination. */ | |
2634 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 2635 | { |
4c6b5505 UW |
2636 | int low_offset = gdbarch_byte_order (current_gdbarch) |
2637 | == BFD_ENDIAN_BIG ? 4 : 0; | |
c906108c SS |
2638 | unsigned long regval; |
2639 | ||
2640 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2641 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2642 | if (mips_debug) |
acdb74a0 | 2643 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2644 | float_argreg, phex (regval, 4)); |
c906108c | 2645 | write_register (float_argreg++, regval); |
c906108c SS |
2646 | |
2647 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2648 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2649 | if (mips_debug) |
acdb74a0 | 2650 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2651 | float_argreg, phex (regval, 4)); |
c906108c | 2652 | write_register (float_argreg++, regval); |
c906108c SS |
2653 | } |
2654 | else | |
2655 | { | |
2656 | /* This is a floating point value that fits entirely | |
2657 | in a single register. */ | |
53a5351d | 2658 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 2659 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2660 | LONGEST regval = extract_unsigned_integer (val, len); |
2661 | if (mips_debug) | |
acdb74a0 | 2662 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2663 | float_argreg, phex (regval, len)); |
c906108c | 2664 | write_register (float_argreg++, regval); |
c906108c SS |
2665 | } |
2666 | } | |
2667 | else | |
2668 | { | |
2669 | /* Copy the argument to general registers or the stack in | |
2670 | register-sized pieces. Large arguments are split between | |
2671 | registers and stack. */ | |
1a69e1e4 DJ |
2672 | /* Note: structs whose size is not a multiple of regsize |
2673 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
2674 | them in registers where gcc sometimes puts them on the |
2675 | stack. For maximum compatibility, we will put them in | |
2676 | both places. */ | |
1a69e1e4 | 2677 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 2678 | |
f09ded24 | 2679 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2680 | register are only written to memory. */ |
c906108c SS |
2681 | while (len > 0) |
2682 | { | |
ebafbe83 | 2683 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2684 | int stack_used_p = 0; |
1a69e1e4 | 2685 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 2686 | |
acdb74a0 AC |
2687 | if (mips_debug) |
2688 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2689 | partial_len); | |
2690 | ||
566f0f7a | 2691 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2692 | if (argreg > MIPS_LAST_ARG_REGNUM |
2693 | || odd_sized_struct | |
2694 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2695 | { |
c906108c SS |
2696 | /* Should shorter than int integer values be |
2697 | promoted to int before being stored? */ | |
c906108c | 2698 | int longword_offset = 0; |
9ace0497 | 2699 | CORE_ADDR addr; |
566f0f7a | 2700 | stack_used_p = 1; |
4c6b5505 | 2701 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 2702 | { |
1a69e1e4 | 2703 | if (regsize == 8 |
480d3dd2 AC |
2704 | && (typecode == TYPE_CODE_INT |
2705 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 2706 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 2707 | longword_offset = regsize - len; |
480d3dd2 AC |
2708 | else if ((typecode == TYPE_CODE_STRUCT |
2709 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
2710 | && TYPE_LENGTH (arg_type) < regsize) |
2711 | longword_offset = regsize - len; | |
7a292a7a | 2712 | } |
c5aa993b | 2713 | |
9ace0497 AC |
2714 | if (mips_debug) |
2715 | { | |
cb3d25d1 MS |
2716 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2717 | paddr_nz (stack_offset)); | |
2718 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2719 | paddr_nz (longword_offset)); | |
9ace0497 | 2720 | } |
361d1df0 | 2721 | |
9ace0497 AC |
2722 | addr = sp + stack_offset + longword_offset; |
2723 | ||
2724 | if (mips_debug) | |
2725 | { | |
2726 | int i; | |
6d82d43b | 2727 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 | 2728 | paddr_nz (addr)); |
9ace0497 AC |
2729 | for (i = 0; i < partial_len; i++) |
2730 | { | |
6d82d43b | 2731 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 2732 | val[i] & 0xff); |
9ace0497 AC |
2733 | } |
2734 | } | |
2735 | write_memory (addr, val, partial_len); | |
c906108c SS |
2736 | } |
2737 | ||
f09ded24 AC |
2738 | /* Note!!! This is NOT an else clause. Odd sized |
2739 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2740 | arguments will not. */ |
566f0f7a | 2741 | /* Write this portion of the argument to a general |
6d82d43b | 2742 | purpose register. */ |
f09ded24 AC |
2743 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2744 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2745 | { |
6d82d43b AC |
2746 | LONGEST regval = |
2747 | extract_unsigned_integer (val, partial_len); | |
c906108c | 2748 | |
9ace0497 | 2749 | if (mips_debug) |
acdb74a0 | 2750 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 2751 | argreg, |
1a69e1e4 | 2752 | phex (regval, regsize)); |
c906108c SS |
2753 | write_register (argreg, regval); |
2754 | argreg++; | |
c906108c | 2755 | } |
c5aa993b | 2756 | |
c906108c SS |
2757 | len -= partial_len; |
2758 | val += partial_len; | |
2759 | ||
566f0f7a | 2760 | /* Compute the the offset into the stack at which we |
6d82d43b | 2761 | will copy the next parameter. |
566f0f7a | 2762 | |
566f0f7a | 2763 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2764 | only needs to be adjusted when it has been used. */ |
c906108c | 2765 | |
46e0f506 | 2766 | if (stack_used_p) |
1a69e1e4 | 2767 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
2768 | } |
2769 | } | |
9ace0497 AC |
2770 | if (mips_debug) |
2771 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2772 | } |
2773 | ||
f10683bb | 2774 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 2775 | |
0f71a2f6 JM |
2776 | /* Return adjusted stack pointer. */ |
2777 | return sp; | |
2778 | } | |
2779 | ||
a1f5b845 | 2780 | /* Determine the return value convention being used. */ |
6d82d43b | 2781 | |
9c8fdbfa AC |
2782 | static enum return_value_convention |
2783 | mips_eabi_return_value (struct gdbarch *gdbarch, | |
2784 | struct type *type, struct regcache *regcache, | |
47a35522 | 2785 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 2786 | { |
9c8fdbfa AC |
2787 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
2788 | return RETURN_VALUE_STRUCT_CONVENTION; | |
2789 | if (readbuf) | |
2790 | memset (readbuf, 0, TYPE_LENGTH (type)); | |
2791 | return RETURN_VALUE_REGISTER_CONVENTION; | |
6d82d43b AC |
2792 | } |
2793 | ||
6d82d43b AC |
2794 | |
2795 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 2796 | |
f7ab6ec6 | 2797 | static CORE_ADDR |
7d9b040b | 2798 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2799 | struct regcache *regcache, CORE_ADDR bp_addr, |
2800 | int nargs, struct value **args, CORE_ADDR sp, | |
2801 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
2802 | { |
2803 | int argreg; | |
2804 | int float_argreg; | |
2805 | int argnum; | |
2806 | int len = 0; | |
2807 | int stack_offset = 0; | |
480d3dd2 | 2808 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2809 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 2810 | |
25ab4790 AC |
2811 | /* For shared libraries, "t9" needs to point at the function |
2812 | address. */ | |
4c7d22cb | 2813 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2814 | |
2815 | /* Set the return address register to point to the entry point of | |
2816 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2817 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2818 | |
cb3d25d1 MS |
2819 | /* First ensure that the stack and structure return address (if any) |
2820 | are properly aligned. The stack has to be at least 64-bit | |
2821 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2822 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2823 | aligned, so we round to this widest known alignment. */ | |
2824 | ||
5b03f266 AC |
2825 | sp = align_down (sp, 16); |
2826 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
2827 | |
2828 | /* Now make space on the stack for the args. */ | |
2829 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 2830 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 2831 | sp -= align_up (len, 16); |
cb3d25d1 MS |
2832 | |
2833 | if (mips_debug) | |
6d82d43b | 2834 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2835 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
2836 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
2837 | |
2838 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 2839 | argreg = MIPS_A0_REGNUM; |
56cea623 | 2840 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 2841 | |
46e0f506 | 2842 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
2843 | if (struct_return) |
2844 | { | |
2845 | if (mips_debug) | |
2846 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2847 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
2848 | argreg, paddr_nz (struct_addr)); |
2849 | write_register (argreg++, struct_addr); | |
2850 | } | |
2851 | ||
2852 | /* Now load as many as possible of the first arguments into | |
2853 | registers, and push the rest onto the stack. Loop thru args | |
2854 | from first to last. */ | |
2855 | for (argnum = 0; argnum < nargs; argnum++) | |
2856 | { | |
47a35522 | 2857 | const gdb_byte *val; |
cb3d25d1 | 2858 | struct value *arg = args[argnum]; |
4991999e | 2859 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
2860 | int len = TYPE_LENGTH (arg_type); |
2861 | enum type_code typecode = TYPE_CODE (arg_type); | |
2862 | ||
2863 | if (mips_debug) | |
2864 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2865 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
2866 | argnum + 1, len, (int) typecode); |
2867 | ||
47a35522 | 2868 | val = value_contents (arg); |
cb3d25d1 MS |
2869 | |
2870 | if (fp_register_arg_p (typecode, arg_type) | |
2871 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
2872 | { | |
2873 | /* This is a floating point value that fits entirely | |
2874 | in a single register. */ | |
2875 | /* On 32 bit ABI's the float_argreg is further adjusted | |
2876 | above to ensure that it is even register aligned. */ | |
2877 | LONGEST regval = extract_unsigned_integer (val, len); | |
2878 | if (mips_debug) | |
2879 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
2880 | float_argreg, phex (regval, len)); | |
2881 | write_register (float_argreg++, regval); | |
2882 | ||
2883 | if (mips_debug) | |
2884 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
2885 | argreg, phex (regval, len)); | |
2886 | write_register (argreg, regval); | |
2887 | argreg += 1; | |
2888 | } | |
2889 | else | |
2890 | { | |
2891 | /* Copy the argument to general registers or the stack in | |
2892 | register-sized pieces. Large arguments are split between | |
2893 | registers and stack. */ | |
1a69e1e4 | 2894 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
2895 | are treated specially: Irix cc passes them in registers |
2896 | where gcc sometimes puts them on the stack. For maximum | |
2897 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
2898 | int odd_sized_struct = (len > MIPS64_REGSIZE |
2899 | && len % MIPS64_REGSIZE != 0); | |
cb3d25d1 | 2900 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2901 | register are only written to memory. */ |
cb3d25d1 MS |
2902 | while (len > 0) |
2903 | { | |
ad018eee | 2904 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 2905 | int stack_used_p = 0; |
1a69e1e4 | 2906 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
2907 | |
2908 | if (mips_debug) | |
2909 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2910 | partial_len); | |
2911 | ||
2912 | /* Write this portion of the argument to the stack. */ | |
2913 | if (argreg > MIPS_LAST_ARG_REGNUM | |
2914 | || odd_sized_struct | |
2915 | || fp_register_arg_p (typecode, arg_type)) | |
2916 | { | |
2917 | /* Should shorter than int integer values be | |
2918 | promoted to int before being stored? */ | |
2919 | int longword_offset = 0; | |
2920 | CORE_ADDR addr; | |
2921 | stack_used_p = 1; | |
4c6b5505 | 2922 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 2923 | { |
1a69e1e4 DJ |
2924 | if ((typecode == TYPE_CODE_INT |
2925 | || typecode == TYPE_CODE_PTR | |
2926 | || typecode == TYPE_CODE_FLT) | |
2927 | && len <= 4) | |
2928 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
2929 | } |
2930 | ||
2931 | if (mips_debug) | |
2932 | { | |
2933 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
2934 | paddr_nz (stack_offset)); | |
2935 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2936 | paddr_nz (longword_offset)); | |
2937 | } | |
2938 | ||
2939 | addr = sp + stack_offset + longword_offset; | |
2940 | ||
2941 | if (mips_debug) | |
2942 | { | |
2943 | int i; | |
6d82d43b | 2944 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 MS |
2945 | paddr_nz (addr)); |
2946 | for (i = 0; i < partial_len; i++) | |
2947 | { | |
6d82d43b | 2948 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
2949 | val[i] & 0xff); |
2950 | } | |
2951 | } | |
2952 | write_memory (addr, val, partial_len); | |
2953 | } | |
2954 | ||
2955 | /* Note!!! This is NOT an else clause. Odd sized | |
2956 | structs may go thru BOTH paths. Floating point | |
2957 | arguments will not. */ | |
2958 | /* Write this portion of the argument to a general | |
6d82d43b | 2959 | purpose register. */ |
cb3d25d1 MS |
2960 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2961 | && !fp_register_arg_p (typecode, arg_type)) | |
2962 | { | |
6d82d43b AC |
2963 | LONGEST regval = |
2964 | extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
2965 | |
2966 | /* A non-floating-point argument being passed in a | |
2967 | general register. If a struct or union, and if | |
2968 | the remaining length is smaller than the register | |
2969 | size, we have to adjust the register value on | |
2970 | big endian targets. | |
2971 | ||
2972 | It does not seem to be necessary to do the | |
1a69e1e4 | 2973 | same for integral types. */ |
cb3d25d1 | 2974 | |
4c6b5505 | 2975 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 2976 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
2977 | && (typecode == TYPE_CODE_STRUCT |
2978 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 2979 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 2980 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
2981 | |
2982 | if (mips_debug) | |
2983 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
2984 | argreg, | |
1a69e1e4 | 2985 | phex (regval, MIPS64_REGSIZE)); |
cb3d25d1 MS |
2986 | write_register (argreg, regval); |
2987 | argreg++; | |
2988 | } | |
2989 | ||
2990 | len -= partial_len; | |
2991 | val += partial_len; | |
2992 | ||
2993 | /* Compute the the offset into the stack at which we | |
6d82d43b | 2994 | will copy the next parameter. |
cb3d25d1 MS |
2995 | |
2996 | In N32 (N64?), the stack_offset only needs to be | |
2997 | adjusted when it has been used. */ | |
2998 | ||
2999 | if (stack_used_p) | |
1a69e1e4 | 3000 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
3001 | } |
3002 | } | |
3003 | if (mips_debug) | |
3004 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3005 | } | |
3006 | ||
f10683bb | 3007 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3008 | |
cb3d25d1 MS |
3009 | /* Return adjusted stack pointer. */ |
3010 | return sp; | |
3011 | } | |
3012 | ||
6d82d43b AC |
3013 | static enum return_value_convention |
3014 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
3015 | struct type *type, struct regcache *regcache, | |
47a35522 | 3016 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 3017 | { |
6d82d43b AC |
3018 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3019 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3020 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3021 | || TYPE_CODE (type) == TYPE_CODE_ARRAY | |
1a69e1e4 | 3022 | || TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 3023 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
3024 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3025 | && TYPE_LENGTH (type) == 16 | |
3026 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3027 | { | |
3028 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
3029 | two registers are used in the same as memory order, so the | |
3030 | eight bytes with the lower memory address are in $f0. */ | |
3031 | if (mips_debug) | |
3032 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
3033 | mips_xfer_register (regcache, | |
f57d151a UW |
3034 | gdbarch_num_regs (current_gdbarch) |
3035 | + mips_regnum (current_gdbarch)->fp0, | |
4c6b5505 UW |
3036 | 8, gdbarch_byte_order (current_gdbarch), |
3037 | readbuf, writebuf, 0); | |
d05f6826 | 3038 | mips_xfer_register (regcache, |
f57d151a UW |
3039 | gdbarch_num_regs (current_gdbarch) |
3040 | + mips_regnum (current_gdbarch)->fp0 + 2, | |
4c6b5505 UW |
3041 | 8, gdbarch_byte_order (current_gdbarch), |
3042 | readbuf ? readbuf + 8 : readbuf, | |
d05f6826 DJ |
3043 | writebuf ? writebuf + 8 : writebuf, 0); |
3044 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3045 | } | |
6d82d43b AC |
3046 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3047 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3048 | { | |
3049 | /* A floating-point value belongs in the least significant part | |
3050 | of FP0. */ | |
3051 | if (mips_debug) | |
3052 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3053 | mips_xfer_register (regcache, | |
f57d151a UW |
3054 | gdbarch_num_regs (current_gdbarch) |
3055 | + mips_regnum (current_gdbarch)->fp0, | |
6d82d43b | 3056 | TYPE_LENGTH (type), |
4c6b5505 UW |
3057 | gdbarch_byte_order (current_gdbarch), |
3058 | readbuf, writebuf, 0); | |
6d82d43b AC |
3059 | return RETURN_VALUE_REGISTER_CONVENTION; |
3060 | } | |
3061 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3062 | && TYPE_NFIELDS (type) <= 2 | |
3063 | && TYPE_NFIELDS (type) >= 1 | |
3064 | && ((TYPE_NFIELDS (type) == 1 | |
3065 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3066 | == TYPE_CODE_FLT)) | |
3067 | || (TYPE_NFIELDS (type) == 2 | |
3068 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3069 | == TYPE_CODE_FLT) | |
3070 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3071 | == TYPE_CODE_FLT))) | |
3072 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3073 | { | |
3074 | /* A struct that contains one or two floats. Each value is part | |
3075 | in the least significant part of their floating point | |
3076 | register.. */ | |
6d82d43b AC |
3077 | int regnum; |
3078 | int field; | |
3079 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3080 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3081 | { | |
3082 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3083 | / TARGET_CHAR_BIT); | |
3084 | if (mips_debug) | |
3085 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3086 | offset); | |
f57d151a UW |
3087 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3088 | + regnum, | |
6d82d43b | 3089 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
4c6b5505 UW |
3090 | gdbarch_byte_order (current_gdbarch), |
3091 | readbuf, writebuf, offset); | |
6d82d43b AC |
3092 | } |
3093 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3094 | } | |
3095 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3096 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3097 | { | |
3098 | /* A structure or union. Extract the left justified value, | |
3099 | regardless of the byte order. I.e. DO NOT USE | |
3100 | mips_xfer_lower. */ | |
3101 | int offset; | |
3102 | int regnum; | |
4c7d22cb | 3103 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3104 | offset < TYPE_LENGTH (type); |
3105 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3106 | { | |
3107 | int xfer = register_size (current_gdbarch, regnum); | |
3108 | if (offset + xfer > TYPE_LENGTH (type)) | |
3109 | xfer = TYPE_LENGTH (type) - offset; | |
3110 | if (mips_debug) | |
3111 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3112 | offset, xfer, regnum); | |
f57d151a UW |
3113 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3114 | + regnum, xfer, | |
6d82d43b AC |
3115 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
3116 | } | |
3117 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3118 | } | |
3119 | else | |
3120 | { | |
3121 | /* A scalar extract each part but least-significant-byte | |
3122 | justified. */ | |
3123 | int offset; | |
3124 | int regnum; | |
4c7d22cb | 3125 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3126 | offset < TYPE_LENGTH (type); |
3127 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3128 | { | |
3129 | int xfer = register_size (current_gdbarch, regnum); | |
6d82d43b AC |
3130 | if (offset + xfer > TYPE_LENGTH (type)) |
3131 | xfer = TYPE_LENGTH (type) - offset; | |
3132 | if (mips_debug) | |
3133 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3134 | offset, xfer, regnum); | |
f57d151a UW |
3135 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3136 | + regnum, xfer, | |
4c6b5505 UW |
3137 | gdbarch_byte_order (current_gdbarch), |
3138 | readbuf, writebuf, offset); | |
6d82d43b AC |
3139 | } |
3140 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3141 | } | |
3142 | } | |
3143 | ||
3144 | /* O32 ABI stuff. */ | |
3145 | ||
3146 | static CORE_ADDR | |
7d9b040b | 3147 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3148 | struct regcache *regcache, CORE_ADDR bp_addr, |
3149 | int nargs, struct value **args, CORE_ADDR sp, | |
3150 | int struct_return, CORE_ADDR struct_addr) | |
3151 | { | |
3152 | int argreg; | |
3153 | int float_argreg; | |
3154 | int argnum; | |
3155 | int len = 0; | |
3156 | int stack_offset = 0; | |
3157 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7d9b040b | 3158 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3159 | |
3160 | /* For shared libraries, "t9" needs to point at the function | |
3161 | address. */ | |
4c7d22cb | 3162 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3163 | |
3164 | /* Set the return address register to point to the entry point of | |
3165 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3166 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3167 | |
3168 | /* First ensure that the stack and structure return address (if any) | |
3169 | are properly aligned. The stack has to be at least 64-bit | |
3170 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3171 | aligned. For n32 and n64, stack frames need to be 128-bit |
3172 | aligned, so we round to this widest known alignment. */ | |
3173 | ||
5b03f266 AC |
3174 | sp = align_down (sp, 16); |
3175 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3176 | |
3177 | /* Now make space on the stack for the args. */ | |
3178 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3179 | { |
3180 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3181 | int arglen = TYPE_LENGTH (arg_type); | |
3182 | ||
3183 | /* Align to double-word if necessary. */ | |
2afd3f0a | 3184 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 3185 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 3186 | /* Allocate space on the stack. */ |
1a69e1e4 | 3187 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 3188 | } |
5b03f266 | 3189 | sp -= align_up (len, 16); |
ebafbe83 MS |
3190 | |
3191 | if (mips_debug) | |
6d82d43b | 3192 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3193 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3194 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3195 | |
3196 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3197 | argreg = MIPS_A0_REGNUM; |
56cea623 | 3198 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 3199 | |
bcb0cc15 | 3200 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3201 | if (struct_return) |
3202 | { | |
3203 | if (mips_debug) | |
3204 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3205 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
3206 | argreg, paddr_nz (struct_addr)); |
3207 | write_register (argreg++, struct_addr); | |
1a69e1e4 | 3208 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
3209 | } |
3210 | ||
3211 | /* Now load as many as possible of the first arguments into | |
3212 | registers, and push the rest onto the stack. Loop thru args | |
3213 | from first to last. */ | |
3214 | for (argnum = 0; argnum < nargs; argnum++) | |
3215 | { | |
47a35522 | 3216 | const gdb_byte *val; |
ebafbe83 | 3217 | struct value *arg = args[argnum]; |
4991999e | 3218 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3219 | int len = TYPE_LENGTH (arg_type); |
3220 | enum type_code typecode = TYPE_CODE (arg_type); | |
3221 | ||
3222 | if (mips_debug) | |
3223 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3224 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3225 | argnum + 1, len, (int) typecode); |
3226 | ||
47a35522 | 3227 | val = value_contents (arg); |
46cac009 AC |
3228 | |
3229 | /* 32-bit ABIs always start floating point arguments in an | |
3230 | even-numbered floating point register. Round the FP register | |
3231 | up before the check to see if there are any FP registers | |
3232 | left. O32/O64 targets also pass the FP in the integer | |
3233 | registers so also round up normal registers. */ | |
2afd3f0a | 3234 | if (fp_register_arg_p (typecode, arg_type)) |
46cac009 AC |
3235 | { |
3236 | if ((float_argreg & 1)) | |
3237 | float_argreg++; | |
3238 | } | |
3239 | ||
3240 | /* Floating point arguments passed in registers have to be | |
3241 | treated specially. On 32-bit architectures, doubles | |
3242 | are passed in register pairs; the even register gets | |
3243 | the low word, and the odd register gets the high word. | |
3244 | On O32/O64, the first two floating point arguments are | |
3245 | also copied to general registers, because MIPS16 functions | |
3246 | don't use float registers for arguments. This duplication of | |
3247 | arguments in general registers can't hurt non-MIPS16 functions | |
3248 | because those registers are normally skipped. */ | |
3249 | ||
3250 | if (fp_register_arg_p (typecode, arg_type) | |
3251 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3252 | { | |
8b07f6d8 | 3253 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 3254 | { |
4c6b5505 UW |
3255 | int low_offset = gdbarch_byte_order (current_gdbarch) |
3256 | == BFD_ENDIAN_BIG ? 4 : 0; | |
46cac009 AC |
3257 | unsigned long regval; |
3258 | ||
3259 | /* Write the low word of the double to the even register(s). */ | |
3260 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3261 | if (mips_debug) | |
3262 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3263 | float_argreg, phex (regval, 4)); | |
3264 | write_register (float_argreg++, regval); | |
3265 | if (mips_debug) | |
3266 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3267 | argreg, phex (regval, 4)); | |
3268 | write_register (argreg++, regval); | |
3269 | ||
3270 | /* Write the high word of the double to the odd register(s). */ | |
3271 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3272 | if (mips_debug) | |
3273 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3274 | float_argreg, phex (regval, 4)); | |
3275 | write_register (float_argreg++, regval); | |
3276 | ||
3277 | if (mips_debug) | |
3278 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3279 | argreg, phex (regval, 4)); | |
3280 | write_register (argreg++, regval); | |
3281 | } | |
3282 | else | |
3283 | { | |
3284 | /* This is a floating point value that fits entirely | |
3285 | in a single register. */ | |
3286 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3287 | above to ensure that it is even register aligned. */ |
46cac009 AC |
3288 | LONGEST regval = extract_unsigned_integer (val, len); |
3289 | if (mips_debug) | |
3290 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3291 | float_argreg, phex (regval, len)); | |
3292 | write_register (float_argreg++, regval); | |
3293 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
3294 | registers for each argument. The below is (my |
3295 | guess) to ensure that the corresponding integer | |
3296 | register has reserved the same space. */ | |
46cac009 AC |
3297 | if (mips_debug) |
3298 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3299 | argreg, phex (regval, len)); | |
3300 | write_register (argreg, regval); | |
2afd3f0a | 3301 | argreg += 2; |
46cac009 AC |
3302 | } |
3303 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 3304 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
3305 | } |
3306 | else | |
3307 | { | |
3308 | /* Copy the argument to general registers or the stack in | |
3309 | register-sized pieces. Large arguments are split between | |
3310 | registers and stack. */ | |
1a69e1e4 DJ |
3311 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
3312 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3313 | them in registers where gcc sometimes puts them on the |
3314 | stack. For maximum compatibility, we will put them in | |
3315 | both places. */ | |
1a69e1e4 DJ |
3316 | int odd_sized_struct = (len > MIPS32_REGSIZE |
3317 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
3318 | /* Structures should be aligned to eight bytes (even arg registers) |
3319 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 3320 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
3321 | { |
3322 | if ((argreg & 1)) | |
968b5391 MR |
3323 | { |
3324 | argreg++; | |
1a69e1e4 | 3325 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 3326 | } |
46cac009 | 3327 | } |
46cac009 AC |
3328 | while (len > 0) |
3329 | { | |
3330 | /* Remember if the argument was written to the stack. */ | |
3331 | int stack_used_p = 0; | |
1a69e1e4 | 3332 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
3333 | |
3334 | if (mips_debug) | |
3335 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3336 | partial_len); | |
3337 | ||
3338 | /* Write this portion of the argument to the stack. */ | |
3339 | if (argreg > MIPS_LAST_ARG_REGNUM | |
968b5391 | 3340 | || odd_sized_struct) |
46cac009 AC |
3341 | { |
3342 | /* Should shorter than int integer values be | |
3343 | promoted to int before being stored? */ | |
3344 | int longword_offset = 0; | |
3345 | CORE_ADDR addr; | |
3346 | stack_used_p = 1; | |
46cac009 AC |
3347 | |
3348 | if (mips_debug) | |
3349 | { | |
3350 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3351 | paddr_nz (stack_offset)); | |
3352 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3353 | paddr_nz (longword_offset)); | |
3354 | } | |
3355 | ||
3356 | addr = sp + stack_offset + longword_offset; | |
3357 | ||
3358 | if (mips_debug) | |
3359 | { | |
3360 | int i; | |
6d82d43b | 3361 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
46cac009 AC |
3362 | paddr_nz (addr)); |
3363 | for (i = 0; i < partial_len; i++) | |
3364 | { | |
6d82d43b | 3365 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3366 | val[i] & 0xff); |
3367 | } | |
3368 | } | |
3369 | write_memory (addr, val, partial_len); | |
3370 | } | |
3371 | ||
3372 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3373 | structs may go thru BOTH paths. */ |
46cac009 | 3374 | /* Write this portion of the argument to a general |
6d82d43b | 3375 | purpose register. */ |
968b5391 | 3376 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
46cac009 AC |
3377 | { |
3378 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3379 | /* Value may need to be sign extended, because |
1b13c4f6 | 3380 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3381 | |
3382 | /* A non-floating-point argument being passed in a | |
3383 | general register. If a struct or union, and if | |
3384 | the remaining length is smaller than the register | |
3385 | size, we have to adjust the register value on | |
3386 | big endian targets. | |
3387 | ||
3388 | It does not seem to be necessary to do the | |
3389 | same for integral types. | |
3390 | ||
3391 | Also don't do this adjustment on O64 binaries. | |
3392 | ||
3393 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3394 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
3395 | mips_abi_regsize(), generates a left shift |
3396 | as part of storing the argument in a register | |
3397 | (the left shift isn't generated when | |
1b13c4f6 | 3398 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3399 | it is quite possible that this is GCC |
3400 | contradicting the LE/O32 ABI, GDB has not been | |
3401 | adjusted to accommodate this. Either someone | |
3402 | needs to demonstrate that the LE/O32 ABI | |
3403 | specifies such a left shift OR this new ABI gets | |
3404 | identified as such and GDB gets tweaked | |
3405 | accordingly. */ | |
3406 | ||
4c6b5505 | 3407 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3408 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
3409 | && (typecode == TYPE_CODE_STRUCT |
3410 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3411 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 3412 | * TARGET_CHAR_BIT); |
46cac009 AC |
3413 | |
3414 | if (mips_debug) | |
3415 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3416 | argreg, | |
1a69e1e4 | 3417 | phex (regval, MIPS32_REGSIZE)); |
46cac009 AC |
3418 | write_register (argreg, regval); |
3419 | argreg++; | |
3420 | ||
3421 | /* Prevent subsequent floating point arguments from | |
3422 | being passed in floating point registers. */ | |
3423 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3424 | } | |
3425 | ||
3426 | len -= partial_len; | |
3427 | val += partial_len; | |
3428 | ||
3429 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3430 | will copy the next parameter. |
46cac009 | 3431 | |
6d82d43b AC |
3432 | In older ABIs, the caller reserved space for |
3433 | registers that contained arguments. This was loosely | |
3434 | refered to as their "home". Consequently, space is | |
3435 | always allocated. */ | |
46cac009 | 3436 | |
1a69e1e4 | 3437 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
3438 | } |
3439 | } | |
3440 | if (mips_debug) | |
3441 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3442 | } | |
3443 | ||
f10683bb | 3444 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3445 | |
46cac009 AC |
3446 | /* Return adjusted stack pointer. */ |
3447 | return sp; | |
3448 | } | |
3449 | ||
6d82d43b AC |
3450 | static enum return_value_convention |
3451 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
3452 | struct regcache *regcache, | |
47a35522 | 3453 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b AC |
3454 | { |
3455 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3456 | ||
3457 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3458 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3459 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3460 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3461 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3462 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3463 | { | |
3464 | /* A single-precision floating-point value. It fits in the | |
3465 | least significant part of FP0. */ | |
3466 | if (mips_debug) | |
3467 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3468 | mips_xfer_register (regcache, | |
f57d151a UW |
3469 | gdbarch_num_regs (current_gdbarch) |
3470 | + mips_regnum (current_gdbarch)->fp0, | |
6d82d43b | 3471 | TYPE_LENGTH (type), |
4c6b5505 UW |
3472 | gdbarch_byte_order (current_gdbarch), |
3473 | readbuf, writebuf, 0); | |
6d82d43b AC |
3474 | return RETURN_VALUE_REGISTER_CONVENTION; |
3475 | } | |
3476 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3477 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3478 | { | |
3479 | /* A double-precision floating-point value. The most | |
3480 | significant part goes in FP1, and the least significant in | |
3481 | FP0. */ | |
3482 | if (mips_debug) | |
3483 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
4c6b5505 | 3484 | switch (gdbarch_byte_order (current_gdbarch)) |
6d82d43b AC |
3485 | { |
3486 | case BFD_ENDIAN_LITTLE: | |
3487 | mips_xfer_register (regcache, | |
f57d151a UW |
3488 | gdbarch_num_regs (current_gdbarch) |
3489 | + mips_regnum (current_gdbarch)->fp0 + | |
4c6b5505 UW |
3490 | 0, 4, gdbarch_byte_order (current_gdbarch), |
3491 | readbuf, writebuf, 0); | |
6d82d43b | 3492 | mips_xfer_register (regcache, |
f57d151a UW |
3493 | gdbarch_num_regs (current_gdbarch) |
3494 | + mips_regnum (current_gdbarch)->fp0 + 1, | |
4c6b5505 UW |
3495 | 4, gdbarch_byte_order (current_gdbarch), |
3496 | readbuf, writebuf, 4); | |
6d82d43b AC |
3497 | break; |
3498 | case BFD_ENDIAN_BIG: | |
3499 | mips_xfer_register (regcache, | |
f57d151a UW |
3500 | gdbarch_num_regs (current_gdbarch) |
3501 | + mips_regnum (current_gdbarch)->fp0 + 1, | |
4c6b5505 UW |
3502 | 4, gdbarch_byte_order (current_gdbarch), |
3503 | readbuf, writebuf, 0); | |
6d82d43b | 3504 | mips_xfer_register (regcache, |
f57d151a UW |
3505 | gdbarch_num_regs (current_gdbarch) |
3506 | + mips_regnum (current_gdbarch)->fp0 + 0, | |
4c6b5505 UW |
3507 | 4, gdbarch_byte_order (current_gdbarch), |
3508 | readbuf, writebuf, 4); | |
6d82d43b AC |
3509 | break; |
3510 | default: | |
e2e0b3e5 | 3511 | internal_error (__FILE__, __LINE__, _("bad switch")); |
6d82d43b AC |
3512 | } |
3513 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3514 | } | |
3515 | #if 0 | |
3516 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3517 | && TYPE_NFIELDS (type) <= 2 | |
3518 | && TYPE_NFIELDS (type) >= 1 | |
3519 | && ((TYPE_NFIELDS (type) == 1 | |
3520 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3521 | == TYPE_CODE_FLT)) | |
3522 | || (TYPE_NFIELDS (type) == 2 | |
3523 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3524 | == TYPE_CODE_FLT) | |
3525 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3526 | == TYPE_CODE_FLT))) | |
3527 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3528 | { | |
3529 | /* A struct that contains one or two floats. Each value is part | |
3530 | in the least significant part of their floating point | |
3531 | register.. */ | |
870cd05e | 3532 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
3533 | int regnum; |
3534 | int field; | |
3535 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3536 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3537 | { | |
3538 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3539 | / TARGET_CHAR_BIT); | |
3540 | if (mips_debug) | |
3541 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3542 | offset); | |
f57d151a UW |
3543 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3544 | + regnum, | |
6d82d43b | 3545 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
4c6b5505 UW |
3546 | gdbarch_byte_order (current_gdbarch), |
3547 | readbuf, writebuf, offset); | |
6d82d43b AC |
3548 | } |
3549 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3550 | } | |
3551 | #endif | |
3552 | #if 0 | |
3553 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3554 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3555 | { | |
3556 | /* A structure or union. Extract the left justified value, | |
3557 | regardless of the byte order. I.e. DO NOT USE | |
3558 | mips_xfer_lower. */ | |
3559 | int offset; | |
3560 | int regnum; | |
4c7d22cb | 3561 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3562 | offset < TYPE_LENGTH (type); |
3563 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3564 | { | |
3565 | int xfer = register_size (current_gdbarch, regnum); | |
3566 | if (offset + xfer > TYPE_LENGTH (type)) | |
3567 | xfer = TYPE_LENGTH (type) - offset; | |
3568 | if (mips_debug) | |
3569 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3570 | offset, xfer, regnum); | |
f57d151a UW |
3571 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3572 | + regnum, xfer, | |
6d82d43b AC |
3573 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
3574 | } | |
3575 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3576 | } | |
3577 | #endif | |
3578 | else | |
3579 | { | |
3580 | /* A scalar extract each part but least-significant-byte | |
3581 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 3582 | the ISA. */ |
6d82d43b AC |
3583 | int offset; |
3584 | int regnum; | |
4c7d22cb | 3585 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3586 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 3587 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 3588 | { |
1a69e1e4 | 3589 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
3590 | if (offset + xfer > TYPE_LENGTH (type)) |
3591 | xfer = TYPE_LENGTH (type) - offset; | |
3592 | if (mips_debug) | |
3593 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3594 | offset, xfer, regnum); | |
f57d151a UW |
3595 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3596 | + regnum, xfer, | |
4c6b5505 UW |
3597 | gdbarch_byte_order (current_gdbarch), |
3598 | readbuf, writebuf, offset); | |
6d82d43b AC |
3599 | } |
3600 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3601 | } | |
3602 | } | |
3603 | ||
3604 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
3605 | ABI. */ | |
46cac009 AC |
3606 | |
3607 | static CORE_ADDR | |
7d9b040b | 3608 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3609 | struct regcache *regcache, CORE_ADDR bp_addr, |
3610 | int nargs, | |
3611 | struct value **args, CORE_ADDR sp, | |
3612 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
3613 | { |
3614 | int argreg; | |
3615 | int float_argreg; | |
3616 | int argnum; | |
3617 | int len = 0; | |
3618 | int stack_offset = 0; | |
480d3dd2 | 3619 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3620 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 3621 | |
25ab4790 AC |
3622 | /* For shared libraries, "t9" needs to point at the function |
3623 | address. */ | |
4c7d22cb | 3624 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3625 | |
3626 | /* Set the return address register to point to the entry point of | |
3627 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3628 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3629 | |
46cac009 AC |
3630 | /* First ensure that the stack and structure return address (if any) |
3631 | are properly aligned. The stack has to be at least 64-bit | |
3632 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3633 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3634 | aligned, so we round to this widest known alignment. */ | |
3635 | ||
5b03f266 AC |
3636 | sp = align_down (sp, 16); |
3637 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3638 | |
3639 | /* Now make space on the stack for the args. */ | |
3640 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3641 | { |
3642 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3643 | int arglen = TYPE_LENGTH (arg_type); | |
3644 | ||
968b5391 | 3645 | /* Allocate space on the stack. */ |
1a69e1e4 | 3646 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 3647 | } |
5b03f266 | 3648 | sp -= align_up (len, 16); |
46cac009 AC |
3649 | |
3650 | if (mips_debug) | |
6d82d43b | 3651 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3652 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
3653 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
3654 | |
3655 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3656 | argreg = MIPS_A0_REGNUM; |
56cea623 | 3657 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
3658 | |
3659 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3660 | if (struct_return) | |
3661 | { | |
3662 | if (mips_debug) | |
3663 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3664 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
3665 | argreg, paddr_nz (struct_addr)); |
3666 | write_register (argreg++, struct_addr); | |
1a69e1e4 | 3667 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
3668 | } |
3669 | ||
3670 | /* Now load as many as possible of the first arguments into | |
3671 | registers, and push the rest onto the stack. Loop thru args | |
3672 | from first to last. */ | |
3673 | for (argnum = 0; argnum < nargs; argnum++) | |
3674 | { | |
47a35522 | 3675 | const gdb_byte *val; |
46cac009 | 3676 | struct value *arg = args[argnum]; |
4991999e | 3677 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
3678 | int len = TYPE_LENGTH (arg_type); |
3679 | enum type_code typecode = TYPE_CODE (arg_type); | |
3680 | ||
3681 | if (mips_debug) | |
3682 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3683 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
3684 | argnum + 1, len, (int) typecode); |
3685 | ||
47a35522 | 3686 | val = value_contents (arg); |
ebafbe83 | 3687 | |
ebafbe83 MS |
3688 | /* Floating point arguments passed in registers have to be |
3689 | treated specially. On 32-bit architectures, doubles | |
3690 | are passed in register pairs; the even register gets | |
3691 | the low word, and the odd register gets the high word. | |
3692 | On O32/O64, the first two floating point arguments are | |
3693 | also copied to general registers, because MIPS16 functions | |
3694 | don't use float registers for arguments. This duplication of | |
3695 | arguments in general registers can't hurt non-MIPS16 functions | |
3696 | because those registers are normally skipped. */ | |
3697 | ||
3698 | if (fp_register_arg_p (typecode, arg_type) | |
3699 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3700 | { | |
2afd3f0a MR |
3701 | LONGEST regval = extract_unsigned_integer (val, len); |
3702 | if (mips_debug) | |
3703 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3704 | float_argreg, phex (regval, len)); | |
3705 | write_register (float_argreg++, regval); | |
3706 | if (mips_debug) | |
3707 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3708 | argreg, phex (regval, len)); | |
3709 | write_register (argreg, regval); | |
3710 | argreg++; | |
ebafbe83 | 3711 | /* Reserve space for the FP register. */ |
1a69e1e4 | 3712 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
3713 | } |
3714 | else | |
3715 | { | |
3716 | /* Copy the argument to general registers or the stack in | |
3717 | register-sized pieces. Large arguments are split between | |
3718 | registers and stack. */ | |
1a69e1e4 | 3719 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
3720 | are treated specially: Irix cc passes them in registers |
3721 | where gcc sometimes puts them on the stack. For maximum | |
3722 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
3723 | int odd_sized_struct = (len > MIPS64_REGSIZE |
3724 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
3725 | while (len > 0) |
3726 | { | |
3727 | /* Remember if the argument was written to the stack. */ | |
3728 | int stack_used_p = 0; | |
1a69e1e4 | 3729 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
3730 | |
3731 | if (mips_debug) | |
3732 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3733 | partial_len); | |
3734 | ||
3735 | /* Write this portion of the argument to the stack. */ | |
3736 | if (argreg > MIPS_LAST_ARG_REGNUM | |
968b5391 | 3737 | || odd_sized_struct) |
ebafbe83 MS |
3738 | { |
3739 | /* Should shorter than int integer values be | |
3740 | promoted to int before being stored? */ | |
3741 | int longword_offset = 0; | |
3742 | CORE_ADDR addr; | |
3743 | stack_used_p = 1; | |
4c6b5505 | 3744 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 3745 | { |
1a69e1e4 DJ |
3746 | if ((typecode == TYPE_CODE_INT |
3747 | || typecode == TYPE_CODE_PTR | |
3748 | || typecode == TYPE_CODE_FLT) | |
3749 | && len <= 4) | |
3750 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
3751 | } |
3752 | ||
3753 | if (mips_debug) | |
3754 | { | |
3755 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3756 | paddr_nz (stack_offset)); | |
3757 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3758 | paddr_nz (longword_offset)); | |
3759 | } | |
3760 | ||
3761 | addr = sp + stack_offset + longword_offset; | |
3762 | ||
3763 | if (mips_debug) | |
3764 | { | |
3765 | int i; | |
6d82d43b | 3766 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
ebafbe83 MS |
3767 | paddr_nz (addr)); |
3768 | for (i = 0; i < partial_len; i++) | |
3769 | { | |
6d82d43b | 3770 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
3771 | val[i] & 0xff); |
3772 | } | |
3773 | } | |
3774 | write_memory (addr, val, partial_len); | |
3775 | } | |
3776 | ||
3777 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3778 | structs may go thru BOTH paths. */ |
ebafbe83 | 3779 | /* Write this portion of the argument to a general |
6d82d43b | 3780 | purpose register. */ |
968b5391 | 3781 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
ebafbe83 MS |
3782 | { |
3783 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3784 | /* Value may need to be sign extended, because |
1b13c4f6 | 3785 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
3786 | |
3787 | /* A non-floating-point argument being passed in a | |
3788 | general register. If a struct or union, and if | |
3789 | the remaining length is smaller than the register | |
3790 | size, we have to adjust the register value on | |
3791 | big endian targets. | |
3792 | ||
3793 | It does not seem to be necessary to do the | |
401835eb | 3794 | same for integral types. */ |
480d3dd2 | 3795 | |
4c6b5505 | 3796 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3797 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3798 | && (typecode == TYPE_CODE_STRUCT |
3799 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3800 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3801 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
3802 | |
3803 | if (mips_debug) | |
3804 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3805 | argreg, | |
1a69e1e4 | 3806 | phex (regval, MIPS64_REGSIZE)); |
ebafbe83 MS |
3807 | write_register (argreg, regval); |
3808 | argreg++; | |
3809 | ||
3810 | /* Prevent subsequent floating point arguments from | |
3811 | being passed in floating point registers. */ | |
3812 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3813 | } | |
3814 | ||
3815 | len -= partial_len; | |
3816 | val += partial_len; | |
3817 | ||
3818 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3819 | will copy the next parameter. |
ebafbe83 | 3820 | |
6d82d43b AC |
3821 | In older ABIs, the caller reserved space for |
3822 | registers that contained arguments. This was loosely | |
3823 | refered to as their "home". Consequently, space is | |
3824 | always allocated. */ | |
ebafbe83 | 3825 | |
1a69e1e4 | 3826 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
3827 | } |
3828 | } | |
3829 | if (mips_debug) | |
3830 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3831 | } | |
3832 | ||
f10683bb | 3833 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3834 | |
ebafbe83 MS |
3835 | /* Return adjusted stack pointer. */ |
3836 | return sp; | |
3837 | } | |
3838 | ||
9c8fdbfa AC |
3839 | static enum return_value_convention |
3840 | mips_o64_return_value (struct gdbarch *gdbarch, | |
3841 | struct type *type, struct regcache *regcache, | |
47a35522 | 3842 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3843 | { |
7a076fd2 FF |
3844 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3845 | ||
3846 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3847 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3848 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3849 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3850 | else if (fp_register_arg_p (TYPE_CODE (type), type)) | |
3851 | { | |
3852 | /* A floating-point value. It fits in the least significant | |
3853 | part of FP0. */ | |
3854 | if (mips_debug) | |
3855 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3856 | mips_xfer_register (regcache, | |
f57d151a UW |
3857 | gdbarch_num_regs (current_gdbarch) |
3858 | + mips_regnum (current_gdbarch)->fp0, | |
7a076fd2 | 3859 | TYPE_LENGTH (type), |
4c6b5505 UW |
3860 | gdbarch_byte_order (current_gdbarch), |
3861 | readbuf, writebuf, 0); | |
7a076fd2 FF |
3862 | return RETURN_VALUE_REGISTER_CONVENTION; |
3863 | } | |
3864 | else | |
3865 | { | |
3866 | /* A scalar extract each part but least-significant-byte | |
3867 | justified. */ | |
3868 | int offset; | |
3869 | int regnum; | |
3870 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
3871 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 3872 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 3873 | { |
1a69e1e4 | 3874 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
3875 | if (offset + xfer > TYPE_LENGTH (type)) |
3876 | xfer = TYPE_LENGTH (type) - offset; | |
3877 | if (mips_debug) | |
3878 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3879 | offset, xfer, regnum); | |
f57d151a UW |
3880 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3881 | + regnum, xfer, | |
4c6b5505 UW |
3882 | gdbarch_byte_order (current_gdbarch), |
3883 | readbuf, writebuf, offset); | |
7a076fd2 FF |
3884 | } |
3885 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3886 | } | |
6d82d43b AC |
3887 | } |
3888 | ||
dd824b04 DJ |
3889 | /* Floating point register management. |
3890 | ||
3891 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
3892 | 64bit operations, these early MIPS cpus treat fp register pairs | |
3893 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
3894 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
3895 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
3896 | double precision floats into two 32-bit chunks and store them in | |
3897 | consecutive fp regs. To display 64-bit floats stored in this | |
3898 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
3899 | Throw in user-configurable endianness and you have a real mess. | |
3900 | ||
3901 | The way this works is: | |
3902 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
3903 | double-precision value will be split across two logical registers. | |
3904 | The lower-numbered logical register will hold the low-order bits, | |
3905 | regardless of the processor's endianness. | |
3906 | - If we are on a 64-bit processor, and we are looking for a | |
3907 | single-precision value, it will be in the low ordered bits | |
3908 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
3909 | save slot in memory. | |
3910 | - If we are in 64-bit mode, everything is straightforward. | |
3911 | ||
3912 | Note that this code only deals with "live" registers at the top of the | |
3913 | stack. We will attempt to deal with saved registers later, when | |
3914 | the raw/cooked register interface is in place. (We need a general | |
3915 | interface that can deal with dynamic saved register sizes -- fp | |
3916 | regs could be 32 bits wide in one frame and 64 on the frame above | |
3917 | and below). */ | |
3918 | ||
67b2c998 DJ |
3919 | static struct type * |
3920 | mips_float_register_type (void) | |
3921 | { | |
8da61cc4 | 3922 | return builtin_type_ieee_single; |
67b2c998 DJ |
3923 | } |
3924 | ||
3925 | static struct type * | |
3926 | mips_double_register_type (void) | |
3927 | { | |
8da61cc4 | 3928 | return builtin_type_ieee_double; |
67b2c998 DJ |
3929 | } |
3930 | ||
dd824b04 DJ |
3931 | /* Copy a 32-bit single-precision value from the current frame |
3932 | into rare_buffer. */ | |
3933 | ||
3934 | static void | |
e11c53d2 | 3935 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 3936 | gdb_byte *rare_buffer) |
dd824b04 | 3937 | { |
719ec221 | 3938 | int raw_size = register_size (current_gdbarch, regno); |
47a35522 | 3939 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 3940 | |
e11c53d2 | 3941 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 UW |
3942 | error (_("can't read register %d (%s)"), |
3943 | regno, gdbarch_register_name (current_gdbarch, regno)); | |
dd824b04 DJ |
3944 | if (raw_size == 8) |
3945 | { | |
3946 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 3947 | 32 bits. */ |
dd824b04 DJ |
3948 | int offset; |
3949 | ||
4c6b5505 | 3950 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
3951 | offset = 4; |
3952 | else | |
3953 | offset = 0; | |
3954 | ||
3955 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
3956 | } | |
3957 | else | |
3958 | { | |
3959 | memcpy (rare_buffer, raw_buffer, 4); | |
3960 | } | |
3961 | } | |
3962 | ||
3963 | /* Copy a 64-bit double-precision value from the current frame into | |
3964 | rare_buffer. This may include getting half of it from the next | |
3965 | register. */ | |
3966 | ||
3967 | static void | |
e11c53d2 | 3968 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 3969 | gdb_byte *rare_buffer) |
dd824b04 | 3970 | { |
719ec221 | 3971 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
3972 | |
3973 | if (raw_size == 8 && !mips2_fp_compat ()) | |
3974 | { | |
3975 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 3976 | all 64 bits. */ |
e11c53d2 | 3977 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 UW |
3978 | error (_("can't read register %d (%s)"), |
3979 | regno, gdbarch_register_name (current_gdbarch, regno)); | |
dd824b04 DJ |
3980 | } |
3981 | else | |
3982 | { | |
56cea623 | 3983 | if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) |
dd824b04 | 3984 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
3985 | _("mips_read_fp_register_double: bad access to " |
3986 | "odd-numbered FP register")); | |
dd824b04 DJ |
3987 | |
3988 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 3989 | each register. */ |
4c6b5505 | 3990 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 3991 | { |
e11c53d2 AC |
3992 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
3993 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 3994 | } |
361d1df0 | 3995 | else |
dd824b04 | 3996 | { |
e11c53d2 AC |
3997 | mips_read_fp_register_single (frame, regno, rare_buffer); |
3998 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
3999 | } |
4000 | } | |
4001 | } | |
4002 | ||
c906108c | 4003 | static void |
e11c53d2 AC |
4004 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4005 | int regnum) | |
c5aa993b | 4006 | { /* do values for FP (float) regs */ |
47a35522 | 4007 | gdb_byte *raw_buffer; |
3903d437 AC |
4008 | double doub, flt1; /* doubles extracted from raw hex data */ |
4009 | int inv1, inv2; | |
c5aa993b | 4010 | |
47a35522 MK |
4011 | raw_buffer = alloca (2 * register_size (current_gdbarch, |
4012 | mips_regnum (current_gdbarch)->fp0)); | |
c906108c | 4013 | |
c9f4d572 UW |
4014 | fprintf_filtered (file, "%s:", |
4015 | gdbarch_register_name (current_gdbarch, regnum)); | |
4016 | fprintf_filtered (file, "%*s", | |
4017 | 4 - (int) strlen (gdbarch_register_name | |
4018 | (current_gdbarch, regnum)), | |
e11c53d2 | 4019 | ""); |
f0ef6b29 | 4020 | |
719ec221 | 4021 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ()) |
c906108c | 4022 | { |
f0ef6b29 KB |
4023 | /* 4-byte registers: Print hex and floating. Also print even |
4024 | numbered registers as doubles. */ | |
e11c53d2 | 4025 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4026 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4027 | |
6d82d43b AC |
4028 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', |
4029 | file); | |
dd824b04 | 4030 | |
e11c53d2 | 4031 | fprintf_filtered (file, " flt: "); |
1adad886 | 4032 | if (inv1) |
e11c53d2 | 4033 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4034 | else |
e11c53d2 | 4035 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4036 | |
f0ef6b29 KB |
4037 | if (regnum % 2 == 0) |
4038 | { | |
e11c53d2 | 4039 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 | 4040 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
6d82d43b | 4041 | &inv2); |
1adad886 | 4042 | |
e11c53d2 | 4043 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4044 | if (inv2) |
e11c53d2 | 4045 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4046 | else |
e11c53d2 | 4047 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4048 | } |
c906108c SS |
4049 | } |
4050 | else | |
dd824b04 | 4051 | { |
f0ef6b29 | 4052 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4053 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4054 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4055 | |
e11c53d2 | 4056 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4057 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4058 | ||
361d1df0 | 4059 | |
6d82d43b AC |
4060 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', |
4061 | file); | |
f0ef6b29 | 4062 | |
e11c53d2 | 4063 | fprintf_filtered (file, " flt: "); |
1adad886 | 4064 | if (inv1) |
e11c53d2 | 4065 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4066 | else |
e11c53d2 | 4067 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4068 | |
e11c53d2 | 4069 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4070 | if (inv2) |
e11c53d2 | 4071 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4072 | else |
e11c53d2 | 4073 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4074 | } |
4075 | } | |
4076 | ||
4077 | static void | |
e11c53d2 | 4078 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 4079 | int regnum) |
f0ef6b29 | 4080 | { |
a4b8ebc8 | 4081 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4082 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4083 | int offset; |
1adad886 | 4084 | |
7b9ee6a8 | 4085 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4086 | { |
e11c53d2 | 4087 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4088 | return; |
4089 | } | |
4090 | ||
4091 | /* Get the data in raw format. */ | |
e11c53d2 | 4092 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4093 | { |
c9f4d572 UW |
4094 | fprintf_filtered (file, "%s: [Invalid]", |
4095 | gdbarch_register_name (current_gdbarch, regnum)); | |
f0ef6b29 | 4096 | return; |
c906108c | 4097 | } |
f0ef6b29 | 4098 | |
c9f4d572 | 4099 | fputs_filtered (gdbarch_register_name (current_gdbarch, regnum), file); |
f0ef6b29 KB |
4100 | |
4101 | /* The problem with printing numeric register names (r26, etc.) is that | |
4102 | the user can't use them on input. Probably the best solution is to | |
4103 | fix it so that either the numeric or the funky (a2, etc.) names | |
4104 | are accepted on input. */ | |
4105 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4106 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4107 | else |
e11c53d2 | 4108 | fprintf_filtered (file, ": "); |
f0ef6b29 | 4109 | |
4c6b5505 | 4110 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b AC |
4111 | offset = |
4112 | register_size (current_gdbarch, | |
4113 | regnum) - register_size (current_gdbarch, regnum); | |
f0ef6b29 KB |
4114 | else |
4115 | offset = 0; | |
4116 | ||
6d82d43b | 4117 | print_scalar_formatted (raw_buffer + offset, |
7b9ee6a8 | 4118 | register_type (gdbarch, regnum), 'x', 0, |
6d82d43b | 4119 | file); |
c906108c SS |
4120 | } |
4121 | ||
f0ef6b29 KB |
4122 | /* Replacement for generic do_registers_info. |
4123 | Print regs in pretty columns. */ | |
4124 | ||
4125 | static int | |
e11c53d2 AC |
4126 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4127 | int regnum) | |
f0ef6b29 | 4128 | { |
e11c53d2 AC |
4129 | fprintf_filtered (file, " "); |
4130 | mips_print_fp_register (file, frame, regnum); | |
4131 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4132 | return regnum + 1; |
4133 | } | |
4134 | ||
4135 | ||
c906108c SS |
4136 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4137 | ||
4138 | static int | |
e11c53d2 | 4139 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4140 | int start_regnum) |
c906108c | 4141 | { |
a4b8ebc8 | 4142 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4143 | /* do values for GP (int) regs */ |
47a35522 | 4144 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 4145 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4146 | int col, byte; |
a4b8ebc8 | 4147 | int regnum; |
c906108c SS |
4148 | |
4149 | /* For GP registers, we print a separate row of names above the vals */ | |
a4b8ebc8 | 4150 | for (col = 0, regnum = start_regnum; |
f57d151a UW |
4151 | col < ncols && regnum < gdbarch_num_regs (current_gdbarch) |
4152 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4153 | regnum++) | |
c906108c | 4154 | { |
c9f4d572 | 4155 | if (*gdbarch_register_name (current_gdbarch, regnum) == '\0') |
c5aa993b | 4156 | continue; /* unused register */ |
7b9ee6a8 | 4157 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4158 | TYPE_CODE_FLT) |
c5aa993b | 4159 | break; /* end the row: reached FP register */ |
0cc93a06 DJ |
4160 | /* Large registers are handled separately. */ |
4161 | if (register_size (current_gdbarch, regnum) | |
4162 | > mips_abi_regsize (current_gdbarch)) | |
4163 | { | |
4164 | if (col > 0) | |
4165 | break; /* End the row before this register. */ | |
4166 | ||
4167 | /* Print this register on a row by itself. */ | |
4168 | mips_print_register (file, frame, regnum); | |
4169 | fprintf_filtered (file, "\n"); | |
4170 | return regnum + 1; | |
4171 | } | |
d05f6826 DJ |
4172 | if (col == 0) |
4173 | fprintf_filtered (file, " "); | |
6d82d43b | 4174 | fprintf_filtered (file, |
d5ac5a39 | 4175 | mips_abi_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", |
c9f4d572 | 4176 | gdbarch_register_name (current_gdbarch, regnum)); |
c906108c SS |
4177 | col++; |
4178 | } | |
d05f6826 DJ |
4179 | |
4180 | if (col == 0) | |
4181 | return regnum; | |
4182 | ||
a4b8ebc8 | 4183 | /* print the R0 to R31 names */ |
f57d151a UW |
4184 | if ((start_regnum % gdbarch_num_regs (current_gdbarch)) < MIPS_NUMREGS) |
4185 | fprintf_filtered (file, "\n R%-4d", | |
4186 | start_regnum % gdbarch_num_regs (current_gdbarch)); | |
20e6603c AC |
4187 | else |
4188 | fprintf_filtered (file, "\n "); | |
c906108c | 4189 | |
c906108c | 4190 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4191 | for (col = 0, regnum = start_regnum; |
f57d151a UW |
4192 | col < ncols && regnum < gdbarch_num_regs (current_gdbarch) |
4193 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4194 | regnum++) | |
c906108c | 4195 | { |
c9f4d572 | 4196 | if (*gdbarch_register_name (current_gdbarch, regnum) == '\0') |
c5aa993b | 4197 | continue; /* unused register */ |
7b9ee6a8 | 4198 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4199 | TYPE_CODE_FLT) |
c5aa993b | 4200 | break; /* end row: reached FP register */ |
0cc93a06 DJ |
4201 | if (register_size (current_gdbarch, regnum) |
4202 | > mips_abi_regsize (current_gdbarch)) | |
4203 | break; /* End row: large register. */ | |
4204 | ||
c906108c | 4205 | /* OK: get the data in raw format. */ |
e11c53d2 | 4206 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 UW |
4207 | error (_("can't read register %d (%s)"), |
4208 | regnum, gdbarch_register_name (current_gdbarch, regnum)); | |
c906108c | 4209 | /* pad small registers */ |
4246e332 | 4210 | for (byte = 0; |
d5ac5a39 | 4211 | byte < (mips_abi_regsize (current_gdbarch) |
6d82d43b | 4212 | - register_size (current_gdbarch, regnum)); byte++) |
c906108c SS |
4213 | printf_filtered (" "); |
4214 | /* Now print the register value in hex, endian order. */ | |
4c6b5505 | 4215 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b AC |
4216 | for (byte = |
4217 | register_size (current_gdbarch, | |
4218 | regnum) - register_size (current_gdbarch, regnum); | |
4219 | byte < register_size (current_gdbarch, regnum); byte++) | |
47a35522 | 4220 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 4221 | else |
c73e8f27 | 4222 | for (byte = register_size (current_gdbarch, regnum) - 1; |
6d82d43b | 4223 | byte >= 0; byte--) |
47a35522 | 4224 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 4225 | fprintf_filtered (file, " "); |
c906108c SS |
4226 | col++; |
4227 | } | |
c5aa993b | 4228 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4229 | fprintf_filtered (file, "\n"); |
c906108c SS |
4230 | |
4231 | return regnum; | |
4232 | } | |
4233 | ||
4234 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4235 | ||
bf1f5b4c | 4236 | static void |
e11c53d2 AC |
4237 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4238 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4239 | { |
c5aa993b | 4240 | if (regnum != -1) /* do one specified register */ |
c906108c | 4241 | { |
f57d151a | 4242 | gdb_assert (regnum >= gdbarch_num_regs (current_gdbarch)); |
c9f4d572 | 4243 | if (*(gdbarch_register_name (current_gdbarch, regnum)) == '\0') |
8a3fe4f8 | 4244 | error (_("Not a valid register for the current processor type")); |
c906108c | 4245 | |
0cc93a06 | 4246 | mips_print_register (file, frame, regnum); |
e11c53d2 | 4247 | fprintf_filtered (file, "\n"); |
c906108c | 4248 | } |
c5aa993b JM |
4249 | else |
4250 | /* do all (or most) registers */ | |
c906108c | 4251 | { |
f57d151a UW |
4252 | regnum = gdbarch_num_regs (current_gdbarch); |
4253 | while (regnum < gdbarch_num_regs (current_gdbarch) | |
4254 | + gdbarch_num_pseudo_regs (current_gdbarch)) | |
c906108c | 4255 | { |
7b9ee6a8 | 4256 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4257 | TYPE_CODE_FLT) |
e11c53d2 AC |
4258 | { |
4259 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4260 | regnum = print_fp_register_row (file, frame, regnum); | |
4261 | else | |
4262 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4263 | } | |
c906108c | 4264 | else |
e11c53d2 | 4265 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4266 | } |
4267 | } | |
4268 | } | |
4269 | ||
c906108c SS |
4270 | /* Is this a branch with a delay slot? */ |
4271 | ||
c906108c | 4272 | static int |
acdb74a0 | 4273 | is_delayed (unsigned long insn) |
c906108c SS |
4274 | { |
4275 | int i; | |
4276 | for (i = 0; i < NUMOPCODES; ++i) | |
4277 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4278 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4279 | break; | |
4280 | return (i < NUMOPCODES | |
4281 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4282 | | INSN_COND_BRANCH_DELAY | |
4283 | | INSN_COND_BRANCH_LIKELY))); | |
4284 | } | |
4285 | ||
4286 | int | |
3352ef37 AC |
4287 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
4288 | struct frame_info *frame) | |
c906108c | 4289 | { |
3352ef37 | 4290 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 4291 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
4292 | |
4293 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4294 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4295 | return 0; |
4296 | ||
06648491 MK |
4297 | if (!breakpoint_here_p (pc + 4)) |
4298 | return 0; | |
4299 | ||
3352ef37 AC |
4300 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
4301 | /* If error reading memory, guess that it is not a delayed | |
4302 | branch. */ | |
c906108c | 4303 | return 0; |
4c7d22cb | 4304 | return is_delayed (extract_unsigned_integer (buf, sizeof buf)); |
c906108c SS |
4305 | } |
4306 | ||
6d82d43b AC |
4307 | /* To skip prologues, I use this predicate. Returns either PC itself |
4308 | if the code at PC does not look like a function prologue; otherwise | |
4309 | returns an address that (if we're lucky) follows the prologue. If | |
4310 | LENIENT, then we must skip everything which is involved in setting | |
4311 | up the frame (it's OK to skip more, just so long as we don't skip | |
4312 | anything which might clobber the registers which are being saved. | |
4313 | We must skip more in the case where part of the prologue is in the | |
4314 | delay slot of a non-prologue instruction). */ | |
4315 | ||
4316 | static CORE_ADDR | |
4317 | mips_skip_prologue (CORE_ADDR pc) | |
4318 | { | |
8b622e6a AC |
4319 | CORE_ADDR limit_pc; |
4320 | CORE_ADDR func_addr; | |
4321 | ||
6d82d43b AC |
4322 | /* See if we can determine the end of the prologue via the symbol table. |
4323 | If so, then return either PC, or the PC after the prologue, whichever | |
4324 | is greater. */ | |
8b622e6a AC |
4325 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4326 | { | |
4327 | CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr); | |
4328 | if (post_prologue_pc != 0) | |
4329 | return max (pc, post_prologue_pc); | |
4330 | } | |
6d82d43b AC |
4331 | |
4332 | /* Can't determine prologue from the symbol table, need to examine | |
4333 | instructions. */ | |
4334 | ||
98b4dd94 JB |
4335 | /* Find an upper limit on the function prologue using the debug |
4336 | information. If the debug information could not be used to provide | |
4337 | that bound, then use an arbitrary large number as the upper bound. */ | |
4338 | limit_pc = skip_prologue_using_sal (pc); | |
4339 | if (limit_pc == 0) | |
4340 | limit_pc = pc + 100; /* Magic. */ | |
4341 | ||
0fe7e7c8 | 4342 | if (mips_pc_is_mips16 (pc)) |
a65bbe44 | 4343 | return mips16_scan_prologue (pc, limit_pc, NULL, NULL); |
6d82d43b | 4344 | else |
a65bbe44 | 4345 | return mips32_scan_prologue (pc, limit_pc, NULL, NULL); |
88658117 AC |
4346 | } |
4347 | ||
a5ea2558 AC |
4348 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4349 | used for all MIPS-specific commands. */ | |
4350 | ||
a5ea2558 | 4351 | static void |
acdb74a0 | 4352 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4353 | { |
4354 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4355 | } | |
4356 | ||
a5ea2558 | 4357 | static void |
acdb74a0 | 4358 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 4359 | { |
6d82d43b AC |
4360 | printf_unfiltered |
4361 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
4362 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
4363 | } | |
4364 | ||
c906108c SS |
4365 | /* Commands to show/set the MIPS FPU type. */ |
4366 | ||
c906108c | 4367 | static void |
acdb74a0 | 4368 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4369 | { |
c906108c SS |
4370 | char *fpu; |
4371 | switch (MIPS_FPU_TYPE) | |
4372 | { | |
4373 | case MIPS_FPU_SINGLE: | |
4374 | fpu = "single-precision"; | |
4375 | break; | |
4376 | case MIPS_FPU_DOUBLE: | |
4377 | fpu = "double-precision"; | |
4378 | break; | |
4379 | case MIPS_FPU_NONE: | |
4380 | fpu = "absent (none)"; | |
4381 | break; | |
93d56215 | 4382 | default: |
e2e0b3e5 | 4383 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
4384 | } |
4385 | if (mips_fpu_type_auto) | |
6d82d43b AC |
4386 | printf_unfiltered |
4387 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4388 | fpu); | |
c906108c | 4389 | else |
6d82d43b AC |
4390 | printf_unfiltered |
4391 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
4392 | } |
4393 | ||
4394 | ||
c906108c | 4395 | static void |
acdb74a0 | 4396 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 4397 | { |
6d82d43b AC |
4398 | printf_unfiltered |
4399 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
4400 | show_mipsfpu_command (args, from_tty); |
4401 | } | |
4402 | ||
c906108c | 4403 | static void |
acdb74a0 | 4404 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 4405 | { |
8d5838b5 AC |
4406 | struct gdbarch_info info; |
4407 | gdbarch_info_init (&info); | |
c906108c SS |
4408 | mips_fpu_type = MIPS_FPU_SINGLE; |
4409 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4410 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4411 | instead of relying on globals. Doing that would let generic code | |
4412 | handle the search for this specific architecture. */ | |
4413 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4414 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4415 | } |
4416 | ||
c906108c | 4417 | static void |
acdb74a0 | 4418 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 4419 | { |
8d5838b5 AC |
4420 | struct gdbarch_info info; |
4421 | gdbarch_info_init (&info); | |
c906108c SS |
4422 | mips_fpu_type = MIPS_FPU_DOUBLE; |
4423 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4424 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4425 | instead of relying on globals. Doing that would let generic code | |
4426 | handle the search for this specific architecture. */ | |
4427 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4428 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4429 | } |
4430 | ||
c906108c | 4431 | static void |
acdb74a0 | 4432 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 4433 | { |
8d5838b5 AC |
4434 | struct gdbarch_info info; |
4435 | gdbarch_info_init (&info); | |
c906108c SS |
4436 | mips_fpu_type = MIPS_FPU_NONE; |
4437 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4438 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4439 | instead of relying on globals. Doing that would let generic code | |
4440 | handle the search for this specific architecture. */ | |
4441 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4442 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4443 | } |
4444 | ||
c906108c | 4445 | static void |
acdb74a0 | 4446 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
4447 | { |
4448 | mips_fpu_type_auto = 1; | |
4449 | } | |
4450 | ||
c906108c | 4451 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
4452 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
4453 | the relevant processor still exists (it dates back to '94) and | |
4454 | secondly this is not the way to do this. The processor type should | |
4455 | be set by forcing an architecture change. */ | |
c906108c | 4456 | |
691c0433 AC |
4457 | void |
4458 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 4459 | { |
691c0433 | 4460 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
a9614958 | 4461 | ULONGEST prid; |
c906108c | 4462 | |
a9614958 UW |
4463 | regcache_cooked_read_unsigned (current_regcache, |
4464 | MIPS_PRID_REGNUM, &prid); | |
c906108c | 4465 | if ((prid & ~0xf) == 0x700) |
691c0433 | 4466 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
4467 | } |
4468 | ||
4469 | /* Just like reinit_frame_cache, but with the right arguments to be | |
4470 | callable as an sfunc. */ | |
4471 | ||
4472 | static void | |
acdb74a0 AC |
4473 | reinit_frame_cache_sfunc (char *args, int from_tty, |
4474 | struct cmd_list_element *c) | |
c906108c SS |
4475 | { |
4476 | reinit_frame_cache (); | |
4477 | } | |
4478 | ||
a89aa300 AC |
4479 | static int |
4480 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 4481 | { |
e5ab0dce | 4482 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 4483 | |
d31431ed AC |
4484 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
4485 | disassembler needs to be able to locally determine the ISA, and | |
4486 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
4487 | work. */ | |
ec4045ea AC |
4488 | if (mips_pc_is_mips16 (memaddr)) |
4489 | info->mach = bfd_mach_mips16; | |
c906108c SS |
4490 | |
4491 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 4492 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 4493 | |
e5ab0dce | 4494 | /* Set the disassembler options. */ |
6d82d43b | 4495 | if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64) |
e5ab0dce AC |
4496 | { |
4497 | /* Set up the disassembler info, so that we get the right | |
6d82d43b | 4498 | register names from libopcodes. */ |
e5ab0dce AC |
4499 | if (tdep->mips_abi == MIPS_ABI_N32) |
4500 | info->disassembler_options = "gpr-names=n32"; | |
4501 | else | |
4502 | info->disassembler_options = "gpr-names=64"; | |
4503 | info->flavour = bfd_target_elf_flavour; | |
4504 | } | |
4505 | else | |
4506 | /* This string is not recognized explicitly by the disassembler, | |
4507 | but it tells the disassembler to not try to guess the ABI from | |
4508 | the bfd elf headers, such that, if the user overrides the ABI | |
4509 | of a program linked as NewABI, the disassembly will follow the | |
4510 | register naming conventions specified by the user. */ | |
4511 | info->disassembler_options = "gpr-names=32"; | |
4512 | ||
c906108c | 4513 | /* Call the appropriate disassembler based on the target endian-ness. */ |
4c6b5505 | 4514 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
c906108c SS |
4515 | return print_insn_big_mips (memaddr, info); |
4516 | else | |
4517 | return print_insn_little_mips (memaddr, info); | |
4518 | } | |
4519 | ||
3b3b875c UW |
4520 | /* This function implements gdbarch_breakpoint_from_pc. It uses the program |
4521 | counter value to determine whether a 16- or 32-bit breakpoint should be used. | |
4522 | It returns a pointer to a string of bytes that encode a breakpoint | |
4523 | instruction, stores the length of the string to *lenptr, and adjusts pc (if | |
4524 | necessary) to point to the actual memory location where the breakpoint | |
4525 | should be inserted. */ | |
c906108c | 4526 | |
47a35522 | 4527 | static const gdb_byte * |
6d82d43b | 4528 | mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 4529 | { |
4c6b5505 | 4530 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 4531 | { |
0fe7e7c8 | 4532 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4533 | { |
47a35522 | 4534 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 4535 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4536 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
4537 | return mips16_big_breakpoint; |
4538 | } | |
4539 | else | |
4540 | { | |
aaab4dba AC |
4541 | /* The IDT board uses an unusual breakpoint value, and |
4542 | sometimes gets confused when it sees the usual MIPS | |
4543 | breakpoint instruction. */ | |
47a35522 MK |
4544 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
4545 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
4546 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 4547 | |
c5aa993b | 4548 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
4549 | |
4550 | if (strcmp (target_shortname, "mips") == 0) | |
4551 | return idt_big_breakpoint; | |
4552 | else if (strcmp (target_shortname, "ddb") == 0 | |
4553 | || strcmp (target_shortname, "pmon") == 0 | |
4554 | || strcmp (target_shortname, "lsi") == 0) | |
4555 | return pmon_big_breakpoint; | |
4556 | else | |
4557 | return big_breakpoint; | |
4558 | } | |
4559 | } | |
4560 | else | |
4561 | { | |
0fe7e7c8 | 4562 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4563 | { |
47a35522 | 4564 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 4565 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4566 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
4567 | return mips16_little_breakpoint; |
4568 | } | |
4569 | else | |
4570 | { | |
47a35522 MK |
4571 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
4572 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
4573 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 4574 | |
c5aa993b | 4575 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
4576 | |
4577 | if (strcmp (target_shortname, "mips") == 0) | |
4578 | return idt_little_breakpoint; | |
4579 | else if (strcmp (target_shortname, "ddb") == 0 | |
4580 | || strcmp (target_shortname, "pmon") == 0 | |
4581 | || strcmp (target_shortname, "lsi") == 0) | |
4582 | return pmon_little_breakpoint; | |
4583 | else | |
4584 | return little_breakpoint; | |
4585 | } | |
4586 | } | |
4587 | } | |
4588 | ||
4589 | /* If PC is in a mips16 call or return stub, return the address of the target | |
4590 | PC, which is either the callee or the caller. There are several | |
4591 | cases which must be handled: | |
4592 | ||
4593 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 4594 | target PC is in $31 ($ra). |
c906108c | 4595 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 4596 | and the target PC is in $2. |
c906108c | 4597 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
4598 | before the jal instruction, this is effectively a call stub |
4599 | and the the target PC is in $2. Otherwise this is effectively | |
4600 | a return stub and the target PC is in $18. | |
c906108c SS |
4601 | |
4602 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 4603 | gory details. */ |
c906108c | 4604 | |
757a7cc6 | 4605 | static CORE_ADDR |
e7d6a6d2 | 4606 | mips_skip_trampoline_code (CORE_ADDR pc) |
c906108c SS |
4607 | { |
4608 | char *name; | |
4609 | CORE_ADDR start_addr; | |
4610 | ||
4611 | /* Find the starting address and name of the function containing the PC. */ | |
4612 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
4613 | return 0; | |
4614 | ||
4615 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
4616 | target PC is in $31 ($ra). */ | |
4617 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
4618 | || strcmp (name, "__mips16_ret_df") == 0) | |
4c7d22cb | 4619 | return read_signed_register (MIPS_RA_REGNUM); |
c906108c SS |
4620 | |
4621 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
4622 | { | |
4623 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
4624 | and the target PC is in $2. */ | |
4625 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 4626 | return read_signed_register (2); |
c906108c SS |
4627 | |
4628 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
4629 | before the jal instruction, this is effectively a call stub |
4630 | and the the target PC is in $2. Otherwise this is effectively | |
4631 | a return stub and the target PC is in $18. */ | |
c906108c SS |
4632 | else if (name[19] == 's' || name[19] == 'd') |
4633 | { | |
4634 | if (pc == start_addr) | |
4635 | { | |
4636 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
4637 | stub. Such a stub for a function bar might have a name |
4638 | like __fn_stub_bar, and might look like this: | |
4639 | mfc1 $4,$f13 | |
4640 | mfc1 $5,$f12 | |
4641 | mfc1 $6,$f15 | |
4642 | mfc1 $7,$f14 | |
4643 | la $1,bar (becomes a lui/addiu pair) | |
4644 | jr $1 | |
4645 | So scan down to the lui/addi and extract the target | |
4646 | address from those two instructions. */ | |
c906108c | 4647 | |
6c997a34 | 4648 | CORE_ADDR target_pc = read_signed_register (2); |
d37cca3d | 4649 | ULONGEST inst; |
c906108c SS |
4650 | int i; |
4651 | ||
4652 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
4653 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
4654 | 0) | |
c906108c SS |
4655 | return target_pc; |
4656 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
4657 | && strcmp (name, "etext") != 0 | |
4658 | && strcmp (name, "_etext") != 0) | |
4659 | return target_pc; | |
4660 | ||
4661 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
4662 | The limit on the search is arbitrarily set to 20 |
4663 | instructions. FIXME. */ | |
95ac2dcf | 4664 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
c906108c | 4665 | { |
c5aa993b JM |
4666 | inst = mips_fetch_instruction (target_pc); |
4667 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
4668 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
4669 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
4670 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
4671 | } |
4672 | ||
4673 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
4674 | return target_pc; | |
4675 | } | |
4676 | else | |
4677 | /* This is the 'return' part of a call stub. The return | |
4678 | address is in $r18. */ | |
6c997a34 | 4679 | return read_signed_register (18); |
c906108c SS |
4680 | } |
4681 | } | |
c5aa993b | 4682 | return 0; /* not a stub */ |
c906108c SS |
4683 | } |
4684 | ||
a4b8ebc8 | 4685 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 4686 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
4687 | |
4688 | static int | |
4689 | mips_stab_reg_to_regnum (int num) | |
4690 | { | |
a4b8ebc8 | 4691 | int regnum; |
2f38ef89 | 4692 | if (num >= 0 && num < 32) |
a4b8ebc8 | 4693 | regnum = num; |
2f38ef89 | 4694 | else if (num >= 38 && num < 70) |
56cea623 | 4695 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 4696 | else if (num == 70) |
56cea623 | 4697 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 4698 | else if (num == 71) |
56cea623 | 4699 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 4700 | else |
a4b8ebc8 AC |
4701 | /* This will hopefully (eventually) provoke a warning. Should |
4702 | we be calling complaint() here? */ | |
f57d151a UW |
4703 | return gdbarch_num_regs (current_gdbarch) |
4704 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4705 | return gdbarch_num_regs (current_gdbarch) + regnum; | |
88c72b7d AC |
4706 | } |
4707 | ||
2f38ef89 | 4708 | |
a4b8ebc8 | 4709 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 4710 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
4711 | |
4712 | static int | |
2f38ef89 | 4713 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 4714 | { |
a4b8ebc8 | 4715 | int regnum; |
2f38ef89 | 4716 | if (num >= 0 && num < 32) |
a4b8ebc8 | 4717 | regnum = num; |
2f38ef89 | 4718 | else if (num >= 32 && num < 64) |
56cea623 | 4719 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 4720 | else if (num == 64) |
56cea623 | 4721 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 4722 | else if (num == 65) |
56cea623 | 4723 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 4724 | else |
a4b8ebc8 AC |
4725 | /* This will hopefully (eventually) provoke a warning. Should we |
4726 | be calling complaint() here? */ | |
f57d151a UW |
4727 | return gdbarch_num_regs (current_gdbarch) |
4728 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4729 | return gdbarch_num_regs (current_gdbarch) + regnum; | |
a4b8ebc8 AC |
4730 | } |
4731 | ||
4732 | static int | |
4733 | mips_register_sim_regno (int regnum) | |
4734 | { | |
4735 | /* Only makes sense to supply raw registers. */ | |
f57d151a | 4736 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch)); |
a4b8ebc8 AC |
4737 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
4738 | decide if it is valid. Should instead define a standard sim/gdb | |
4739 | register numbering scheme. */ | |
c9f4d572 UW |
4740 | if (gdbarch_register_name (current_gdbarch, |
4741 | gdbarch_num_regs | |
4742 | (current_gdbarch) + regnum) != NULL | |
4743 | && gdbarch_register_name (current_gdbarch, | |
4744 | gdbarch_num_regs | |
4745 | (current_gdbarch) + regnum)[0] != '\0') | |
a4b8ebc8 AC |
4746 | return regnum; |
4747 | else | |
6d82d43b | 4748 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
4749 | } |
4750 | ||
2f38ef89 | 4751 | |
4844f454 CV |
4752 | /* Convert an integer into an address. Extracting the value signed |
4753 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
4754 | |
4755 | static CORE_ADDR | |
79dd2d24 | 4756 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 4757 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 4758 | { |
4844f454 | 4759 | return (CORE_ADDR) extract_signed_integer (buf, TYPE_LENGTH (type)); |
fc0c74b1 AC |
4760 | } |
4761 | ||
caaa3122 DJ |
4762 | static void |
4763 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
4764 | { | |
4765 | enum mips_abi *abip = (enum mips_abi *) obj; | |
4766 | const char *name = bfd_get_section_name (abfd, sect); | |
4767 | ||
4768 | if (*abip != MIPS_ABI_UNKNOWN) | |
4769 | return; | |
4770 | ||
4771 | if (strncmp (name, ".mdebug.", 8) != 0) | |
4772 | return; | |
4773 | ||
4774 | if (strcmp (name, ".mdebug.abi32") == 0) | |
4775 | *abip = MIPS_ABI_O32; | |
4776 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
4777 | *abip = MIPS_ABI_N32; | |
62a49b2c | 4778 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 4779 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
4780 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
4781 | *abip = MIPS_ABI_O64; | |
4782 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
4783 | *abip = MIPS_ABI_EABI32; | |
4784 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
4785 | *abip = MIPS_ABI_EABI64; | |
4786 | else | |
8a3fe4f8 | 4787 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
4788 | } |
4789 | ||
22e47e37 FF |
4790 | static void |
4791 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
4792 | { | |
4793 | int *lbp = (int *) obj; | |
4794 | const char *name = bfd_get_section_name (abfd, sect); | |
4795 | ||
4796 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
4797 | *lbp = 32; | |
4798 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
4799 | *lbp = 64; | |
4800 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
4801 | warning (_("unrecognized .gcc_compiled_longXX")); | |
4802 | } | |
4803 | ||
2e4ebe70 DJ |
4804 | static enum mips_abi |
4805 | global_mips_abi (void) | |
4806 | { | |
4807 | int i; | |
4808 | ||
4809 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
4810 | if (mips_abi_strings[i] == mips_abi_string) | |
4811 | return (enum mips_abi) i; | |
4812 | ||
e2e0b3e5 | 4813 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
4814 | } |
4815 | ||
29709017 DJ |
4816 | static void |
4817 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
4818 | { | |
4819 | static struct target_desc *tdesc_gp32, *tdesc_gp64; | |
4820 | ||
4821 | if (tdesc_gp32 == NULL) | |
4822 | { | |
4823 | /* Create feature sets with the appropriate properties. The values | |
4824 | are not important. */ | |
4825 | ||
4826 | tdesc_gp32 = allocate_target_description (); | |
4827 | set_tdesc_property (tdesc_gp32, PROPERTY_GP32, ""); | |
4828 | ||
4829 | tdesc_gp64 = allocate_target_description (); | |
4830 | set_tdesc_property (tdesc_gp64, PROPERTY_GP64, ""); | |
4831 | } | |
4832 | ||
4833 | /* If the size matches the set of 32-bit or 64-bit integer registers, | |
4834 | assume that's what we've got. */ | |
4835 | register_remote_g_packet_guess (gdbarch, 38 * 4, tdesc_gp32); | |
4836 | register_remote_g_packet_guess (gdbarch, 38 * 8, tdesc_gp64); | |
4837 | ||
4838 | /* If the size matches the full set of registers GDB traditionally | |
4839 | knows about, including floating point, for either 32-bit or | |
4840 | 64-bit, assume that's what we've got. */ | |
4841 | register_remote_g_packet_guess (gdbarch, 90 * 4, tdesc_gp32); | |
4842 | register_remote_g_packet_guess (gdbarch, 90 * 8, tdesc_gp64); | |
4843 | ||
4844 | /* Otherwise we don't have a useful guess. */ | |
4845 | } | |
4846 | ||
f8b73d13 DJ |
4847 | static struct value * |
4848 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
4849 | { | |
4850 | const int *reg_p = baton; | |
4851 | return value_of_register (*reg_p, frame); | |
4852 | } | |
4853 | ||
c2d11a7d | 4854 | static struct gdbarch * |
6d82d43b | 4855 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 4856 | { |
c2d11a7d JM |
4857 | struct gdbarch *gdbarch; |
4858 | struct gdbarch_tdep *tdep; | |
4859 | int elf_flags; | |
2e4ebe70 | 4860 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 4861 | int i, num_regs; |
8d5838b5 | 4862 | enum mips_fpu_type fpu_type; |
f8b73d13 DJ |
4863 | struct tdesc_arch_data *tdesc_data = NULL; |
4864 | ||
4865 | /* Check any target description for validity. */ | |
4866 | if (tdesc_has_registers (info.target_desc)) | |
4867 | { | |
4868 | static const char *const mips_gprs[] = { | |
4869 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
4870 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
4871 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
4872 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
4873 | }; | |
4874 | static const char *const mips_fprs[] = { | |
4875 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
4876 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
4877 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
4878 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
4879 | }; | |
4880 | ||
4881 | const struct tdesc_feature *feature; | |
4882 | int valid_p; | |
4883 | ||
4884 | feature = tdesc_find_feature (info.target_desc, | |
4885 | "org.gnu.gdb.mips.cpu"); | |
4886 | if (feature == NULL) | |
4887 | return NULL; | |
4888 | ||
4889 | tdesc_data = tdesc_data_alloc (); | |
4890 | ||
4891 | valid_p = 1; | |
4892 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
4893 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
4894 | mips_gprs[i]); | |
4895 | ||
4896 | ||
4897 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4898 | MIPS_EMBED_LO_REGNUM, "lo"); | |
4899 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4900 | MIPS_EMBED_HI_REGNUM, "hi"); | |
4901 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4902 | MIPS_EMBED_PC_REGNUM, "pc"); | |
4903 | ||
4904 | if (!valid_p) | |
4905 | { | |
4906 | tdesc_data_cleanup (tdesc_data); | |
4907 | return NULL; | |
4908 | } | |
4909 | ||
4910 | feature = tdesc_find_feature (info.target_desc, | |
4911 | "org.gnu.gdb.mips.cp0"); | |
4912 | if (feature == NULL) | |
4913 | { | |
4914 | tdesc_data_cleanup (tdesc_data); | |
4915 | return NULL; | |
4916 | } | |
4917 | ||
4918 | valid_p = 1; | |
4919 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4920 | MIPS_EMBED_BADVADDR_REGNUM, | |
4921 | "badvaddr"); | |
4922 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4923 | MIPS_PS_REGNUM, "status"); | |
4924 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4925 | MIPS_EMBED_CAUSE_REGNUM, "cause"); | |
4926 | ||
4927 | if (!valid_p) | |
4928 | { | |
4929 | tdesc_data_cleanup (tdesc_data); | |
4930 | return NULL; | |
4931 | } | |
4932 | ||
4933 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
4934 | backend is not prepared for that, though. */ | |
4935 | feature = tdesc_find_feature (info.target_desc, | |
4936 | "org.gnu.gdb.mips.fpu"); | |
4937 | if (feature == NULL) | |
4938 | { | |
4939 | tdesc_data_cleanup (tdesc_data); | |
4940 | return NULL; | |
4941 | } | |
4942 | ||
4943 | valid_p = 1; | |
4944 | for (i = 0; i < 32; i++) | |
4945 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4946 | i + MIPS_EMBED_FP0_REGNUM, | |
4947 | mips_fprs[i]); | |
4948 | ||
4949 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4950 | MIPS_EMBED_FP0_REGNUM + 32, "fcsr"); | |
4951 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4952 | MIPS_EMBED_FP0_REGNUM + 33, "fir"); | |
4953 | ||
4954 | if (!valid_p) | |
4955 | { | |
4956 | tdesc_data_cleanup (tdesc_data); | |
4957 | return NULL; | |
4958 | } | |
4959 | ||
4960 | /* It would be nice to detect an attempt to use a 64-bit ABI | |
4961 | when only 32-bit registers are provided. */ | |
4962 | } | |
c2d11a7d | 4963 | |
ec03c1ac AC |
4964 | /* First of all, extract the elf_flags, if available. */ |
4965 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
4966 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
4967 | else if (arches != NULL) |
4968 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
4969 | else |
4970 | elf_flags = 0; | |
4971 | if (gdbarch_debug) | |
4972 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 4973 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 4974 | |
102182a9 | 4975 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
4976 | switch ((elf_flags & EF_MIPS_ABI)) |
4977 | { | |
4978 | case E_MIPS_ABI_O32: | |
ec03c1ac | 4979 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
4980 | break; |
4981 | case E_MIPS_ABI_O64: | |
ec03c1ac | 4982 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
4983 | break; |
4984 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 4985 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
4986 | break; |
4987 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 4988 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
4989 | break; |
4990 | default: | |
acdb74a0 | 4991 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 4992 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 4993 | else |
ec03c1ac | 4994 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
4995 | break; |
4996 | } | |
acdb74a0 | 4997 | |
caaa3122 | 4998 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
4999 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5000 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5001 | |
dc305454 | 5002 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
5003 | MIPS architecture (if there is one). */ |
5004 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5005 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5006 | |
32a6503c | 5007 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5008 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5009 | && info.bfd_arch_info != NULL |
5010 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5011 | { | |
5012 | switch (info.bfd_arch_info->mach) | |
5013 | { | |
5014 | case bfd_mach_mips3900: | |
ec03c1ac | 5015 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5016 | break; |
5017 | case bfd_mach_mips4100: | |
5018 | case bfd_mach_mips5000: | |
ec03c1ac | 5019 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5020 | break; |
1d06468c EZ |
5021 | case bfd_mach_mips8000: |
5022 | case bfd_mach_mips10000: | |
32a6503c KB |
5023 | /* On Irix, ELF64 executables use the N64 ABI. The |
5024 | pseudo-sections which describe the ABI aren't present | |
5025 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5026 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5027 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5028 | found_abi = MIPS_ABI_N64; |
28d169de | 5029 | else |
ec03c1ac | 5030 | found_abi = MIPS_ABI_N32; |
1d06468c | 5031 | break; |
bf64bfd6 AC |
5032 | } |
5033 | } | |
2e4ebe70 | 5034 | |
26c53e50 DJ |
5035 | /* Default 64-bit objects to N64 instead of O32. */ |
5036 | if (found_abi == MIPS_ABI_UNKNOWN | |
5037 | && info.abfd != NULL | |
5038 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
5039 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5040 | found_abi = MIPS_ABI_N64; | |
5041 | ||
ec03c1ac AC |
5042 | if (gdbarch_debug) |
5043 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5044 | found_abi); | |
5045 | ||
5046 | /* What has the user specified from the command line? */ | |
5047 | wanted_abi = global_mips_abi (); | |
5048 | if (gdbarch_debug) | |
5049 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5050 | wanted_abi); | |
2e4ebe70 DJ |
5051 | |
5052 | /* Now that we have found what the ABI for this binary would be, | |
5053 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5054 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5055 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5056 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5057 | mips_abi = found_abi; | |
5058 | else | |
5059 | mips_abi = MIPS_ABI_O32; | |
5060 | if (gdbarch_debug) | |
5061 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5062 | mips_abi); | |
2e4ebe70 | 5063 | |
ec03c1ac | 5064 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5065 | if (gdbarch_debug) |
ec03c1ac AC |
5066 | fprintf_unfiltered (gdb_stdlog, |
5067 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
5068 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 5069 | |
8d5838b5 AC |
5070 | /* Determine the MIPS FPU type. */ |
5071 | if (!mips_fpu_type_auto) | |
5072 | fpu_type = mips_fpu_type; | |
5073 | else if (info.bfd_arch_info != NULL | |
5074 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5075 | switch (info.bfd_arch_info->mach) | |
5076 | { | |
5077 | case bfd_mach_mips3900: | |
5078 | case bfd_mach_mips4100: | |
5079 | case bfd_mach_mips4111: | |
a9d61c86 | 5080 | case bfd_mach_mips4120: |
8d5838b5 AC |
5081 | fpu_type = MIPS_FPU_NONE; |
5082 | break; | |
5083 | case bfd_mach_mips4650: | |
5084 | fpu_type = MIPS_FPU_SINGLE; | |
5085 | break; | |
5086 | default: | |
5087 | fpu_type = MIPS_FPU_DOUBLE; | |
5088 | break; | |
5089 | } | |
5090 | else if (arches != NULL) | |
5091 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5092 | else | |
5093 | fpu_type = MIPS_FPU_DOUBLE; | |
5094 | if (gdbarch_debug) | |
5095 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5096 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5097 | |
29709017 DJ |
5098 | /* Check for blatant incompatibilities. */ |
5099 | ||
5100 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
5101 | ABI. */ | |
5102 | if (info.target_desc | |
5103 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
5104 | && mips_abi != MIPS_ABI_EABI32 | |
5105 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
5106 | { |
5107 | if (tdesc_data != NULL) | |
5108 | tdesc_data_cleanup (tdesc_data); | |
5109 | return NULL; | |
5110 | } | |
29709017 | 5111 | |
c2d11a7d JM |
5112 | /* try to find a pre-existing architecture */ |
5113 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5114 | arches != NULL; | |
5115 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5116 | { | |
5117 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5118 | using. */ |
9103eae0 | 5119 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5120 | continue; |
9103eae0 | 5121 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5122 | continue; |
719ec221 AC |
5123 | /* Need to be pedantic about which register virtual size is |
5124 | used. */ | |
5125 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5126 | != mips64_transfers_32bit_regs_p) | |
5127 | continue; | |
8d5838b5 AC |
5128 | /* Be pedantic about which FPU is selected. */ |
5129 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5130 | continue; | |
f8b73d13 DJ |
5131 | |
5132 | if (tdesc_data != NULL) | |
5133 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 5134 | return arches->gdbarch; |
c2d11a7d JM |
5135 | } |
5136 | ||
102182a9 | 5137 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5138 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5139 | gdbarch = gdbarch_alloc (&info, tdep); | |
5140 | tdep->elf_flags = elf_flags; | |
719ec221 | 5141 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5142 | tdep->found_abi = found_abi; |
5143 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5144 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
5145 | tdep->register_size_valid_p = 0; |
5146 | tdep->register_size = 0; | |
5147 | ||
5148 | if (info.target_desc) | |
5149 | { | |
5150 | /* Some useful properties can be inferred from the target. */ | |
5151 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
5152 | { | |
5153 | tdep->register_size_valid_p = 1; | |
5154 | tdep->register_size = 4; | |
5155 | } | |
5156 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
5157 | { | |
5158 | tdep->register_size_valid_p = 1; | |
5159 | tdep->register_size = 8; | |
5160 | } | |
5161 | } | |
c2d11a7d | 5162 | |
102182a9 | 5163 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5164 | set_gdbarch_short_bit (gdbarch, 16); |
5165 | set_gdbarch_int_bit (gdbarch, 32); | |
5166 | set_gdbarch_float_bit (gdbarch, 32); | |
5167 | set_gdbarch_double_bit (gdbarch, 64); | |
5168 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5169 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5170 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5171 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5172 | |
6d82d43b | 5173 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
5174 | mips_elf_make_msymbol_special); |
5175 | ||
16e109ca | 5176 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5177 | { |
16e109ca | 5178 | const char **reg_names; |
56cea623 AC |
5179 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5180 | struct mips_regnum); | |
f8b73d13 DJ |
5181 | if (tdesc_has_registers (info.target_desc)) |
5182 | { | |
5183 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5184 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5185 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5186 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5187 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5188 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5189 | regnum->fp_control_status = 70; | |
5190 | regnum->fp_implementation_revision = 71; | |
5191 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
5192 | reg_names = NULL; | |
5193 | } | |
5194 | else if (info.osabi == GDB_OSABI_IRIX) | |
56cea623 AC |
5195 | { |
5196 | regnum->fp0 = 32; | |
5197 | regnum->pc = 64; | |
5198 | regnum->cause = 65; | |
5199 | regnum->badvaddr = 66; | |
5200 | regnum->hi = 67; | |
5201 | regnum->lo = 68; | |
5202 | regnum->fp_control_status = 69; | |
5203 | regnum->fp_implementation_revision = 70; | |
5204 | num_regs = 71; | |
16e109ca | 5205 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5206 | } |
5207 | else | |
5208 | { | |
5209 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5210 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5211 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5212 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5213 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5214 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5215 | regnum->fp_control_status = 70; | |
5216 | regnum->fp_implementation_revision = 71; | |
5217 | num_regs = 90; | |
16e109ca AC |
5218 | if (info.bfd_arch_info != NULL |
5219 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5220 | reg_names = mips_tx39_reg_names; | |
5221 | else | |
5222 | reg_names = mips_generic_reg_names; | |
56cea623 AC |
5223 | } |
5224 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been | |
5225 | replaced by read_pc? */ | |
f10683bb MH |
5226 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
5227 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
5228 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
5229 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5230 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca AC |
5231 | set_gdbarch_register_name (gdbarch, mips_register_name); |
5232 | tdep->mips_processor_reg_names = reg_names; | |
5233 | tdep->regnum = regnum; | |
56cea623 | 5234 | } |
fe29b929 | 5235 | |
0dadbba0 | 5236 | switch (mips_abi) |
c2d11a7d | 5237 | { |
0dadbba0 | 5238 | case MIPS_ABI_O32: |
25ab4790 | 5239 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5240 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 5241 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5242 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5243 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5244 | set_gdbarch_long_bit (gdbarch, 32); |
5245 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5246 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5247 | break; | |
0dadbba0 | 5248 | case MIPS_ABI_O64: |
25ab4790 | 5249 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 5250 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 5251 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5252 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5253 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5254 | set_gdbarch_long_bit (gdbarch, 32); |
5255 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5256 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5257 | break; | |
0dadbba0 | 5258 | case MIPS_ABI_EABI32: |
25ab4790 | 5259 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5260 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5261 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5262 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5263 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5264 | set_gdbarch_long_bit (gdbarch, 32); |
5265 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5266 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5267 | break; | |
0dadbba0 | 5268 | case MIPS_ABI_EABI64: |
25ab4790 | 5269 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5270 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5271 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5272 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5273 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5274 | set_gdbarch_long_bit (gdbarch, 64); |
5275 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5276 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5277 | break; | |
0dadbba0 | 5278 | case MIPS_ABI_N32: |
25ab4790 | 5279 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5280 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5281 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5282 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5283 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5284 | set_gdbarch_long_bit (gdbarch, 32); |
5285 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5286 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5287 | set_gdbarch_long_double_bit (gdbarch, 128); |
8da61cc4 | 5288 | set_gdbarch_long_double_format (gdbarch, floatformats_n32n64_long); |
28d169de KB |
5289 | break; |
5290 | case MIPS_ABI_N64: | |
25ab4790 | 5291 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5292 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5293 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5294 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5295 | tdep->default_mask_address_p = 0; |
5296 | set_gdbarch_long_bit (gdbarch, 64); | |
5297 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5298 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5299 | set_gdbarch_long_double_bit (gdbarch, 128); |
8da61cc4 | 5300 | set_gdbarch_long_double_format (gdbarch, floatformats_n32n64_long); |
0dadbba0 | 5301 | break; |
c2d11a7d | 5302 | default: |
e2e0b3e5 | 5303 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
5304 | } |
5305 | ||
22e47e37 FF |
5306 | /* GCC creates a pseudo-section whose name specifies the size of |
5307 | longs, since -mlong32 or -mlong64 may be used independent of | |
5308 | other options. How those options affect pointer sizes is ABI and | |
5309 | architecture dependent, so use them to override the default sizes | |
5310 | set by the ABI. This table shows the relationship between ABI, | |
5311 | -mlongXX, and size of pointers: | |
5312 | ||
5313 | ABI -mlongXX ptr bits | |
5314 | --- -------- -------- | |
5315 | o32 32 32 | |
5316 | o32 64 32 | |
5317 | n32 32 32 | |
5318 | n32 64 64 | |
5319 | o64 32 32 | |
5320 | o64 64 64 | |
5321 | n64 32 32 | |
5322 | n64 64 64 | |
5323 | eabi32 32 32 | |
5324 | eabi32 64 32 | |
5325 | eabi64 32 32 | |
5326 | eabi64 64 64 | |
5327 | ||
5328 | Note that for o32 and eabi32, pointers are always 32 bits | |
5329 | regardless of any -mlongXX option. For all others, pointers and | |
5330 | longs are the same, as set by -mlongXX or set by defaults. | |
5331 | */ | |
5332 | ||
5333 | if (info.abfd != NULL) | |
5334 | { | |
5335 | int long_bit = 0; | |
5336 | ||
5337 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
5338 | if (long_bit) | |
5339 | { | |
5340 | set_gdbarch_long_bit (gdbarch, long_bit); | |
5341 | switch (mips_abi) | |
5342 | { | |
5343 | case MIPS_ABI_O32: | |
5344 | case MIPS_ABI_EABI32: | |
5345 | break; | |
5346 | case MIPS_ABI_N32: | |
5347 | case MIPS_ABI_O64: | |
5348 | case MIPS_ABI_N64: | |
5349 | case MIPS_ABI_EABI64: | |
5350 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
5351 | break; | |
5352 | default: | |
5353 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
5354 | } | |
5355 | } | |
5356 | } | |
5357 | ||
a5ea2558 AC |
5358 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5359 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5360 | comment: | |
5361 | ||
5362 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5363 | flag in object files because to do so would make it impossible to | |
102182a9 | 5364 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5365 | unnecessarily restrictive. |
361d1df0 | 5366 | |
a5ea2558 AC |
5367 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5368 | but to set this flag before gcc is built with such multilibs will | |
5369 | break too many systems.'' | |
5370 | ||
5371 | But even more unhelpfully, the default linker output target for | |
5372 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5373 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5374 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5375 | this flag to detect 32-bit mode would do the wrong thing given |
5376 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5377 | as 32-bit programs by default. */ |
a5ea2558 | 5378 | |
6c997a34 | 5379 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 5380 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 5381 | |
102182a9 MS |
5382 | /* Add/remove bits from an address. The MIPS needs be careful to |
5383 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5384 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5385 | ||
58dfe9ff AC |
5386 | /* Unwind the frame. */ |
5387 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 5388 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
edfae063 | 5389 | set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id); |
10312cc4 | 5390 | |
102182a9 | 5391 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5392 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
5393 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
5394 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5395 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, | |
5396 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5397 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, | |
5398 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5399 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5400 | |
c2d11a7d JM |
5401 | /* MIPS version of CALL_DUMMY */ |
5402 | ||
9710e734 AC |
5403 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
5404 | replaced by a command, and all targets will default to on stack | |
5405 | (regardless of the stack's execute status). */ | |
5406 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 5407 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 5408 | |
87783b8b AC |
5409 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
5410 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
5411 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
5412 | ||
f7b9e9fc AC |
5413 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5414 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
5415 | |
5416 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 5417 | |
fc0c74b1 AC |
5418 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5419 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5420 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5421 | |
a4b8ebc8 | 5422 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 5423 | |
e11c53d2 | 5424 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 5425 | |
e5ab0dce AC |
5426 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
5427 | ||
3a3bc038 AC |
5428 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
5429 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
5430 | need to all be folded into the target vector. Since they are | |
5431 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
5432 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
5433 | is sitting on? */ | |
5434 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
5435 | ||
e7d6a6d2 | 5436 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 5437 | |
3352ef37 AC |
5438 | set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay); |
5439 | ||
0d5de010 DJ |
5440 | /* Virtual tables. */ |
5441 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
5442 | ||
29709017 DJ |
5443 | mips_register_g_packet_guesses (gdbarch); |
5444 | ||
6de918a6 | 5445 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 5446 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 5447 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 5448 | |
5792a79b | 5449 | /* Unwind the frame. */ |
2bd0c3d7 | 5450 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
eec63939 | 5451 | frame_unwind_append_sniffer (gdbarch, mips_stub_frame_sniffer); |
45c9dd44 AC |
5452 | frame_unwind_append_sniffer (gdbarch, mips_insn16_frame_sniffer); |
5453 | frame_unwind_append_sniffer (gdbarch, mips_insn32_frame_sniffer); | |
2bd0c3d7 | 5454 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 5455 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
5456 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
5457 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 5458 | |
f8b73d13 DJ |
5459 | if (tdesc_data) |
5460 | { | |
5461 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
5462 | tdesc_use_registers (gdbarch, tdesc_data); | |
5463 | ||
5464 | /* Override the normal target description methods to handle our | |
5465 | dual real and pseudo registers. */ | |
5466 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
5467 | set_gdbarch_register_reggroup_p (gdbarch, mips_tdesc_register_reggroup_p); | |
5468 | ||
5469 | num_regs = gdbarch_num_regs (gdbarch); | |
5470 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
5471 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
5472 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
5473 | } | |
5474 | ||
5475 | /* Add ABI-specific aliases for the registers. */ | |
5476 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
5477 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
5478 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
5479 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
5480 | else | |
5481 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
5482 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
5483 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
5484 | ||
5485 | /* Add some other standard aliases. */ | |
5486 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
5487 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
5488 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
5489 | ||
4b9b3959 AC |
5490 | return gdbarch; |
5491 | } | |
5492 | ||
2e4ebe70 | 5493 | static void |
6d82d43b | 5494 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
5495 | { |
5496 | struct gdbarch_info info; | |
5497 | ||
5498 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
5499 | mips_gdbarch_init will take care of the rest. */ | |
5500 | gdbarch_info_init (&info); | |
5501 | gdbarch_update_p (info); | |
5502 | } | |
5503 | ||
ad188201 KB |
5504 | /* Print out which MIPS ABI is in use. */ |
5505 | ||
5506 | static void | |
1f8ca57c JB |
5507 | show_mips_abi (struct ui_file *file, |
5508 | int from_tty, | |
5509 | struct cmd_list_element *ignored_cmd, | |
5510 | const char *ignored_value) | |
ad188201 KB |
5511 | { |
5512 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
1f8ca57c JB |
5513 | fprintf_filtered |
5514 | (file, | |
5515 | "The MIPS ABI is unknown because the current architecture " | |
5516 | "is not MIPS.\n"); | |
ad188201 KB |
5517 | else |
5518 | { | |
5519 | enum mips_abi global_abi = global_mips_abi (); | |
5520 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
5521 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
5522 | ||
5523 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
5524 | fprintf_filtered |
5525 | (file, | |
5526 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 5527 | actual_abi_str); |
ad188201 | 5528 | else if (global_abi == actual_abi) |
1f8ca57c JB |
5529 | fprintf_filtered |
5530 | (file, | |
5531 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 5532 | actual_abi_str); |
ad188201 KB |
5533 | else |
5534 | { | |
5535 | /* Probably shouldn't happen... */ | |
1f8ca57c JB |
5536 | fprintf_filtered |
5537 | (file, | |
5538 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6d82d43b | 5539 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
5540 | } |
5541 | } | |
5542 | } | |
5543 | ||
4b9b3959 AC |
5544 | static void |
5545 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
5546 | { | |
5547 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
5548 | if (tdep != NULL) | |
c2d11a7d | 5549 | { |
acdb74a0 AC |
5550 | int ef_mips_arch; |
5551 | int ef_mips_32bitmode; | |
f49e4e6d | 5552 | /* Determine the ISA. */ |
acdb74a0 AC |
5553 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
5554 | { | |
5555 | case E_MIPS_ARCH_1: | |
5556 | ef_mips_arch = 1; | |
5557 | break; | |
5558 | case E_MIPS_ARCH_2: | |
5559 | ef_mips_arch = 2; | |
5560 | break; | |
5561 | case E_MIPS_ARCH_3: | |
5562 | ef_mips_arch = 3; | |
5563 | break; | |
5564 | case E_MIPS_ARCH_4: | |
93d56215 | 5565 | ef_mips_arch = 4; |
acdb74a0 AC |
5566 | break; |
5567 | default: | |
93d56215 | 5568 | ef_mips_arch = 0; |
acdb74a0 AC |
5569 | break; |
5570 | } | |
f49e4e6d | 5571 | /* Determine the size of a pointer. */ |
acdb74a0 | 5572 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
5573 | fprintf_unfiltered (file, |
5574 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 5575 | tdep->elf_flags); |
4b9b3959 | 5576 | fprintf_unfiltered (file, |
acdb74a0 AC |
5577 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
5578 | ef_mips_32bitmode); | |
5579 | fprintf_unfiltered (file, | |
5580 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
5581 | ef_mips_arch); | |
5582 | fprintf_unfiltered (file, | |
5583 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 5584 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
5585 | fprintf_unfiltered (file, |
5586 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 5587 | mips_mask_address_p (tdep), |
4014092b | 5588 | tdep->default_mask_address_p); |
c2d11a7d | 5589 | } |
4b9b3959 AC |
5590 | fprintf_unfiltered (file, |
5591 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
5592 | MIPS_DEFAULT_FPU_TYPE, | |
5593 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5594 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5595 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5596 | : "???")); | |
6d82d43b | 5597 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI); |
4b9b3959 AC |
5598 | fprintf_unfiltered (file, |
5599 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
5600 | MIPS_FPU_TYPE, | |
5601 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5602 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5603 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5604 | : "???")); | |
c2d11a7d JM |
5605 | } |
5606 | ||
6d82d43b | 5607 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 5608 | |
c906108c | 5609 | void |
acdb74a0 | 5610 | _initialize_mips_tdep (void) |
c906108c SS |
5611 | { |
5612 | static struct cmd_list_element *mipsfpulist = NULL; | |
5613 | struct cmd_list_element *c; | |
5614 | ||
6d82d43b | 5615 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
5616 | if (MIPS_ABI_LAST + 1 |
5617 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 5618 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 5619 | |
4b9b3959 | 5620 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 5621 | |
8d5f9dcb DJ |
5622 | mips_pdr_data = register_objfile_data (); |
5623 | ||
a5ea2558 AC |
5624 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
5625 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
1bedd215 | 5626 | _("Various MIPS specific commands."), |
a5ea2558 AC |
5627 | &setmipscmdlist, "set mips ", 0, &setlist); |
5628 | ||
5629 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 5630 | _("Various MIPS specific commands."), |
a5ea2558 AC |
5631 | &showmipscmdlist, "show mips ", 0, &showlist); |
5632 | ||
2e4ebe70 | 5633 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
5634 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
5635 | &mips_abi_string, _("\ | |
5636 | Set the MIPS ABI used by this program."), _("\ | |
5637 | Show the MIPS ABI used by this program."), _("\ | |
5638 | This option can be set to one of:\n\ | |
5639 | auto - the default ABI associated with the current binary\n\ | |
5640 | o32\n\ | |
5641 | o64\n\ | |
5642 | n32\n\ | |
5643 | n64\n\ | |
5644 | eabi32\n\ | |
5645 | eabi64"), | |
5646 | mips_abi_update, | |
5647 | show_mips_abi, | |
5648 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 5649 | |
c906108c SS |
5650 | /* Let the user turn off floating point and set the fence post for |
5651 | heuristic_proc_start. */ | |
5652 | ||
5653 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 5654 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
5655 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
5656 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 5657 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
5658 | &mipsfpulist); |
5659 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 5660 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
5661 | &mipsfpulist); |
5662 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
5663 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
5664 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
5665 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 5666 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
5667 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
5668 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
5669 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
5670 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 5671 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
5672 | &mipsfpulist); |
5673 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 5674 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
5675 | &showlist); |
5676 | ||
c906108c SS |
5677 | /* We really would like to have both "0" and "unlimited" work, but |
5678 | command.c doesn't deal with that. So make it a var_zinteger | |
5679 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 5680 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
5681 | &heuristic_fence_post, _("\ |
5682 | Set the distance searched for the start of a function."), _("\ | |
5683 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
5684 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
5685 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 5686 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 5687 | reinit_frame_cache_sfunc, |
7915a72c | 5688 | NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */ |
6bcadd06 | 5689 | &setlist, &showlist); |
c906108c SS |
5690 | |
5691 | /* Allow the user to control whether the upper bits of 64-bit | |
5692 | addresses should be zeroed. */ | |
7915a72c AC |
5693 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
5694 | &mask_address_var, _("\ | |
5695 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
5696 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
e9e68a56 | 5697 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ |
7915a72c | 5698 | allow GDB to determine the correct value."), |
08546159 AC |
5699 | NULL, show_mask_address, |
5700 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
5701 | |
5702 | /* Allow the user to control the size of 32 bit registers within the | |
5703 | raw remote packet. */ | |
b3f42336 | 5704 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
5705 | &mips64_transfers_32bit_regs_p, _("\ |
5706 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
5707 | _("\ | |
5708 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
5709 | _("\ | |
719ec221 AC |
5710 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
5711 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 5712 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 5713 | set_mips64_transfers_32bit_regs, |
7915a72c | 5714 | NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */ |
7915a72c | 5715 | &setlist, &showlist); |
9ace0497 AC |
5716 | |
5717 | /* Debug this files internals. */ | |
6bcadd06 | 5718 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
5719 | &mips_debug, _("\ |
5720 | Set mips debugging."), _("\ | |
5721 | Show mips debugging."), _("\ | |
5722 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 5723 | NULL, |
7915a72c | 5724 | NULL, /* FIXME: i18n: Mips debugging is currently %s. */ |
6bcadd06 | 5725 | &setdebuglist, &showdebuglist); |
c906108c | 5726 | } |