Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
0b302171 | 3 | Copyright (C) 1988-2012 Free Software Foundation, Inc. |
bf64bfd6 | 4 | |
c906108c SS |
5 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
6 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
7 | ||
c5aa993b | 8 | This file is part of GDB. |
c906108c | 9 | |
c5aa993b JM |
10 | This program is free software; you can redistribute it and/or modify |
11 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 12 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 13 | (at your option) any later version. |
c906108c | 14 | |
c5aa993b JM |
15 | This program is distributed in the hope that it will be useful, |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
c906108c | 19 | |
c5aa993b | 20 | You should have received a copy of the GNU General Public License |
a9762ec7 | 21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
22 | |
23 | #include "defs.h" | |
24 | #include "gdb_string.h" | |
5e2e9765 | 25 | #include "gdb_assert.h" |
c906108c SS |
26 | #include "frame.h" |
27 | #include "inferior.h" | |
28 | #include "symtab.h" | |
29 | #include "value.h" | |
30 | #include "gdbcmd.h" | |
31 | #include "language.h" | |
32 | #include "gdbcore.h" | |
33 | #include "symfile.h" | |
34 | #include "objfiles.h" | |
35 | #include "gdbtypes.h" | |
36 | #include "target.h" | |
28d069e6 | 37 | #include "arch-utils.h" |
4e052eda | 38 | #include "regcache.h" |
70f80edf | 39 | #include "osabi.h" |
d1973055 | 40 | #include "mips-tdep.h" |
fe898f56 | 41 | #include "block.h" |
a4b8ebc8 | 42 | #include "reggroups.h" |
c906108c | 43 | #include "opcode/mips.h" |
c2d11a7d JM |
44 | #include "elf/mips.h" |
45 | #include "elf-bfd.h" | |
2475bac3 | 46 | #include "symcat.h" |
a4b8ebc8 | 47 | #include "sim-regno.h" |
a89aa300 | 48 | #include "dis-asm.h" |
edfae063 AC |
49 | #include "frame-unwind.h" |
50 | #include "frame-base.h" | |
51 | #include "trad-frame.h" | |
7d9b040b | 52 | #include "infcall.h" |
fed7ba43 | 53 | #include "floatformat.h" |
29709017 DJ |
54 | #include "remote.h" |
55 | #include "target-descriptions.h" | |
2bd0c3d7 | 56 | #include "dwarf2-frame.h" |
f8b73d13 | 57 | #include "user-regs.h" |
79a45b7d | 58 | #include "valprint.h" |
175ff332 | 59 | #include "ax.h" |
c906108c | 60 | |
8d5f9dcb DJ |
61 | static const struct objfile_data *mips_pdr_data; |
62 | ||
5bbcb741 | 63 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 64 | |
4cc0665f MR |
65 | static int mips32_instruction_has_delay_slot (struct gdbarch *, CORE_ADDR); |
66 | static int micromips_instruction_has_delay_slot (struct gdbarch *, CORE_ADDR, | |
67 | int); | |
68 | static int mips16_instruction_has_delay_slot (struct gdbarch *, CORE_ADDR, | |
69 | int); | |
70 | ||
24e05951 | 71 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
72 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
73 | #define ST0_FR (1 << 26) | |
74 | ||
b0069a17 AC |
75 | /* The sizes of floating point registers. */ |
76 | ||
77 | enum | |
78 | { | |
79 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
80 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
81 | }; | |
82 | ||
1a69e1e4 DJ |
83 | enum |
84 | { | |
85 | MIPS32_REGSIZE = 4, | |
86 | MIPS64_REGSIZE = 8 | |
87 | }; | |
0dadbba0 | 88 | |
2e4ebe70 DJ |
89 | static const char *mips_abi_string; |
90 | ||
40478521 | 91 | static const char *const mips_abi_strings[] = { |
2e4ebe70 DJ |
92 | "auto", |
93 | "n32", | |
94 | "o32", | |
28d169de | 95 | "n64", |
2e4ebe70 DJ |
96 | "o64", |
97 | "eabi32", | |
98 | "eabi64", | |
99 | NULL | |
100 | }; | |
101 | ||
4cc0665f MR |
102 | /* For backwards compatibility we default to MIPS16. This flag is |
103 | overridden as soon as unambiguous ELF file flags tell us the | |
104 | compressed ISA encoding used. */ | |
105 | static const char mips_compression_mips16[] = "mips16"; | |
106 | static const char mips_compression_micromips[] = "micromips"; | |
107 | static const char *const mips_compression_strings[] = | |
108 | { | |
109 | mips_compression_mips16, | |
110 | mips_compression_micromips, | |
111 | NULL | |
112 | }; | |
113 | ||
114 | static const char *mips_compression_string = mips_compression_mips16; | |
115 | ||
f8b73d13 DJ |
116 | /* The standard register names, and all the valid aliases for them. */ |
117 | struct register_alias | |
118 | { | |
119 | const char *name; | |
120 | int regnum; | |
121 | }; | |
122 | ||
123 | /* Aliases for o32 and most other ABIs. */ | |
124 | const struct register_alias mips_o32_aliases[] = { | |
125 | { "ta0", 12 }, | |
126 | { "ta1", 13 }, | |
127 | { "ta2", 14 }, | |
128 | { "ta3", 15 } | |
129 | }; | |
130 | ||
131 | /* Aliases for n32 and n64. */ | |
132 | const struct register_alias mips_n32_n64_aliases[] = { | |
133 | { "ta0", 8 }, | |
134 | { "ta1", 9 }, | |
135 | { "ta2", 10 }, | |
136 | { "ta3", 11 } | |
137 | }; | |
138 | ||
139 | /* Aliases for ABI-independent registers. */ | |
140 | const struct register_alias mips_register_aliases[] = { | |
141 | /* The architecture manuals specify these ABI-independent names for | |
142 | the GPRs. */ | |
143 | #define R(n) { "r" #n, n } | |
144 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
145 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
146 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
147 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
148 | #undef R | |
149 | ||
150 | /* k0 and k1 are sometimes called these instead (for "kernel | |
151 | temp"). */ | |
152 | { "kt0", 26 }, | |
153 | { "kt1", 27 }, | |
154 | ||
155 | /* This is the traditional GDB name for the CP0 status register. */ | |
156 | { "sr", MIPS_PS_REGNUM }, | |
157 | ||
158 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
159 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
160 | ||
161 | /* This is the traditional GDB name for the FCSR. */ | |
162 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
163 | }; | |
164 | ||
865093a3 AR |
165 | const struct register_alias mips_numeric_register_aliases[] = { |
166 | #define R(n) { #n, n } | |
167 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
168 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
169 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
170 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
171 | #undef R | |
172 | }; | |
173 | ||
c906108c SS |
174 | #ifndef MIPS_DEFAULT_FPU_TYPE |
175 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
176 | #endif | |
177 | static int mips_fpu_type_auto = 1; | |
178 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 179 | |
9ace0497 | 180 | static int mips_debug = 0; |
7a292a7a | 181 | |
29709017 DJ |
182 | /* Properties (for struct target_desc) describing the g/G packet |
183 | layout. */ | |
184 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
185 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
186 | ||
4eb0ad19 DJ |
187 | struct target_desc *mips_tdesc_gp32; |
188 | struct target_desc *mips_tdesc_gp64; | |
189 | ||
56cea623 AC |
190 | const struct mips_regnum * |
191 | mips_regnum (struct gdbarch *gdbarch) | |
192 | { | |
193 | return gdbarch_tdep (gdbarch)->regnum; | |
194 | } | |
195 | ||
196 | static int | |
197 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
198 | { | |
199 | return mips_regnum (gdbarch)->fp0 + 12; | |
200 | } | |
201 | ||
004159a2 MR |
202 | /* Return 1 if REGNUM refers to a floating-point general register, raw |
203 | or cooked. Otherwise return 0. */ | |
204 | ||
205 | static int | |
206 | mips_float_register_p (struct gdbarch *gdbarch, int regnum) | |
207 | { | |
208 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
209 | ||
210 | return (rawnum >= mips_regnum (gdbarch)->fp0 | |
211 | && rawnum < mips_regnum (gdbarch)->fp0 + 32); | |
212 | } | |
213 | ||
74ed0bb4 MD |
214 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
215 | == MIPS_ABI_EABI32 \ | |
216 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 217 | |
025bb325 MS |
218 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \ |
219 | (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) | |
c2d11a7d | 220 | |
025bb325 MS |
221 | #define MIPS_LAST_ARG_REGNUM(gdbarch) \ |
222 | (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) | |
c2d11a7d | 223 | |
74ed0bb4 | 224 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 225 | |
d1973055 KB |
226 | /* Return the MIPS ABI associated with GDBARCH. */ |
227 | enum mips_abi | |
228 | mips_abi (struct gdbarch *gdbarch) | |
229 | { | |
230 | return gdbarch_tdep (gdbarch)->mips_abi; | |
231 | } | |
232 | ||
4246e332 | 233 | int |
1b13c4f6 | 234 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 235 | { |
29709017 DJ |
236 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
237 | ||
238 | /* If we know how big the registers are, use that size. */ | |
239 | if (tdep->register_size_valid_p) | |
240 | return tdep->register_size; | |
241 | ||
242 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
243 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
244 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
245 | } | |
246 | ||
025bb325 | 247 | /* Return the currently configured (or set) saved register size. */ |
480d3dd2 | 248 | |
e6bc2e8a | 249 | unsigned int |
13326b4e | 250 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 251 | { |
1a69e1e4 DJ |
252 | switch (mips_abi (gdbarch)) |
253 | { | |
254 | case MIPS_ABI_EABI32: | |
255 | case MIPS_ABI_O32: | |
256 | return 4; | |
257 | case MIPS_ABI_N32: | |
258 | case MIPS_ABI_N64: | |
259 | case MIPS_ABI_O64: | |
260 | case MIPS_ABI_EABI64: | |
261 | return 8; | |
262 | case MIPS_ABI_UNKNOWN: | |
263 | case MIPS_ABI_LAST: | |
264 | default: | |
265 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
266 | } | |
d929b26f AC |
267 | } |
268 | ||
4cc0665f MR |
269 | /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here |
270 | are some functions to handle addresses associated with compressed | |
271 | code including but not limited to testing, setting, or clearing | |
272 | bit 0 of such addresses. */ | |
742c84f6 | 273 | |
4cc0665f MR |
274 | /* Return one iff compressed code is the MIPS16 instruction set. */ |
275 | ||
276 | static int | |
277 | is_mips16_isa (struct gdbarch *gdbarch) | |
278 | { | |
279 | return gdbarch_tdep (gdbarch)->mips_isa == ISA_MIPS16; | |
280 | } | |
281 | ||
282 | /* Return one iff compressed code is the microMIPS instruction set. */ | |
283 | ||
284 | static int | |
285 | is_micromips_isa (struct gdbarch *gdbarch) | |
286 | { | |
287 | return gdbarch_tdep (gdbarch)->mips_isa == ISA_MICROMIPS; | |
288 | } | |
289 | ||
290 | /* Return one iff ADDR denotes compressed code. */ | |
291 | ||
292 | static int | |
293 | is_compact_addr (CORE_ADDR addr) | |
742c84f6 MR |
294 | { |
295 | return ((addr) & 1); | |
296 | } | |
297 | ||
4cc0665f MR |
298 | /* Return one iff ADDR denotes standard ISA code. */ |
299 | ||
300 | static int | |
301 | is_mips_addr (CORE_ADDR addr) | |
302 | { | |
303 | return !is_compact_addr (addr); | |
304 | } | |
305 | ||
306 | /* Return one iff ADDR denotes MIPS16 code. */ | |
307 | ||
308 | static int | |
309 | is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
310 | { | |
311 | return is_compact_addr (addr) && is_mips16_isa (gdbarch); | |
312 | } | |
313 | ||
314 | /* Return one iff ADDR denotes microMIPS code. */ | |
315 | ||
316 | static int | |
317 | is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
318 | { | |
319 | return is_compact_addr (addr) && is_micromips_isa (gdbarch); | |
320 | } | |
321 | ||
322 | /* Strip the ISA (compression) bit off from ADDR. */ | |
323 | ||
742c84f6 | 324 | static CORE_ADDR |
4cc0665f | 325 | unmake_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
326 | { |
327 | return ((addr) & ~(CORE_ADDR) 1); | |
328 | } | |
329 | ||
4cc0665f MR |
330 | /* Add the ISA (compression) bit to ADDR. */ |
331 | ||
742c84f6 | 332 | static CORE_ADDR |
4cc0665f | 333 | make_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
334 | { |
335 | return ((addr) | (CORE_ADDR) 1); | |
336 | } | |
337 | ||
71b8ef93 | 338 | /* Functions for setting and testing a bit in a minimal symbol that |
4cc0665f MR |
339 | marks it as MIPS16 or microMIPS function. The MSB of the minimal |
340 | symbol's "info" field is used for this purpose. | |
5a89d8aa | 341 | |
4cc0665f MR |
342 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is |
343 | "special", i.e. refers to a MIPS16 or microMIPS function, and sets | |
344 | one of the "special" bits in a minimal symbol to mark it accordingly. | |
345 | The test checks an ELF-private flag that is valid for true function | |
346 | symbols only; in particular synthetic symbols such as for PLT stubs | |
347 | have no ELF-private part at all. | |
5a89d8aa | 348 | |
4cc0665f MR |
349 | msymbol_is_mips16 and msymbol_is_micromips test the "special" bit |
350 | in a minimal symbol. */ | |
5a89d8aa | 351 | |
5a89d8aa | 352 | static void |
6d82d43b AC |
353 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
354 | { | |
4cc0665f MR |
355 | elf_symbol_type *elfsym = (elf_symbol_type *) sym; |
356 | ||
357 | if ((sym->flags & BSF_SYNTHETIC) != 0) | |
358 | return; | |
359 | ||
360 | if (ELF_ST_IS_MICROMIPS (elfsym->internal_elf_sym.st_other)) | |
361 | MSYMBOL_TARGET_FLAG_2 (msym) = 1; | |
362 | else if (ELF_ST_IS_MIPS16 (elfsym->internal_elf_sym.st_other)) | |
363 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; | |
364 | } | |
365 | ||
366 | /* Return one iff MSYM refers to standard ISA code. */ | |
367 | ||
368 | static int | |
369 | msymbol_is_mips (struct minimal_symbol *msym) | |
370 | { | |
371 | return !(MSYMBOL_TARGET_FLAG_1 (msym) | MSYMBOL_TARGET_FLAG_2 (msym)); | |
5a89d8aa MS |
372 | } |
373 | ||
4cc0665f MR |
374 | /* Return one iff MSYM refers to MIPS16 code. */ |
375 | ||
71b8ef93 | 376 | static int |
4cc0665f | 377 | msymbol_is_mips16 (struct minimal_symbol *msym) |
71b8ef93 | 378 | { |
b887350f | 379 | return MSYMBOL_TARGET_FLAG_1 (msym); |
71b8ef93 MS |
380 | } |
381 | ||
4cc0665f MR |
382 | /* Return one iff MSYM refers to microMIPS code. */ |
383 | ||
384 | static int | |
385 | msymbol_is_micromips (struct minimal_symbol *msym) | |
386 | { | |
387 | return MSYMBOL_TARGET_FLAG_2 (msym); | |
388 | } | |
389 | ||
88658117 AC |
390 | /* XFER a value from the big/little/left end of the register. |
391 | Depending on the size of the value it might occupy the entire | |
392 | register or just part of it. Make an allowance for this, aligning | |
393 | things accordingly. */ | |
394 | ||
395 | static void | |
ba32f989 DJ |
396 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
397 | int reg_num, int length, | |
870cd05e MK |
398 | enum bfd_endian endian, gdb_byte *in, |
399 | const gdb_byte *out, int buf_offset) | |
88658117 | 400 | { |
88658117 | 401 | int reg_offset = 0; |
72a155b4 UW |
402 | |
403 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
404 | /* Need to transfer the left or right part of the register, based on |
405 | the targets byte order. */ | |
88658117 AC |
406 | switch (endian) |
407 | { | |
408 | case BFD_ENDIAN_BIG: | |
72a155b4 | 409 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
410 | break; |
411 | case BFD_ENDIAN_LITTLE: | |
412 | reg_offset = 0; | |
413 | break; | |
6d82d43b | 414 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
415 | reg_offset = 0; |
416 | break; | |
417 | default: | |
e2e0b3e5 | 418 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
419 | } |
420 | if (mips_debug) | |
cb1d2653 AC |
421 | fprintf_unfiltered (gdb_stderr, |
422 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
423 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
424 | if (mips_debug && out != NULL) |
425 | { | |
426 | int i; | |
cb1d2653 | 427 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 428 | for (i = 0; i < length; i++) |
cb1d2653 | 429 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
430 | } |
431 | if (in != NULL) | |
6d82d43b AC |
432 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
433 | in + buf_offset); | |
88658117 | 434 | if (out != NULL) |
6d82d43b AC |
435 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
436 | out + buf_offset); | |
88658117 AC |
437 | if (mips_debug && in != NULL) |
438 | { | |
439 | int i; | |
cb1d2653 | 440 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 441 | for (i = 0; i < length; i++) |
cb1d2653 | 442 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
443 | } |
444 | if (mips_debug) | |
445 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
446 | } | |
447 | ||
dd824b04 DJ |
448 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
449 | compatiblity mode. A return value of 1 means that we have | |
450 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
451 | ||
452 | static int | |
9c9acae0 | 453 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 454 | { |
72a155b4 | 455 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
456 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
457 | meaningful. */ | |
72a155b4 | 458 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
459 | return 0; |
460 | ||
461 | #if 0 | |
462 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
463 | in all the places we deal with FP registers. PR gdb/413. */ | |
464 | /* Otherwise check the FR bit in the status register - it controls | |
465 | the FP compatiblity mode. If it is clear we are in compatibility | |
466 | mode. */ | |
9c9acae0 | 467 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
468 | return 1; |
469 | #endif | |
361d1df0 | 470 | |
dd824b04 DJ |
471 | return 0; |
472 | } | |
473 | ||
7a292a7a | 474 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 475 | |
74ed0bb4 | 476 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 477 | |
a14ed312 | 478 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 479 | |
025bb325 | 480 | /* The list of available "set mips " and "show mips " commands. */ |
acdb74a0 AC |
481 | |
482 | static struct cmd_list_element *setmipscmdlist = NULL; | |
483 | static struct cmd_list_element *showmipscmdlist = NULL; | |
484 | ||
5e2e9765 KB |
485 | /* Integer registers 0 thru 31 are handled explicitly by |
486 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 487 | are listed in the following tables. */ |
691c0433 | 488 | |
6d82d43b AC |
489 | enum |
490 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
491 | |
492 | /* Generic MIPS. */ | |
493 | ||
494 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
495 | "sr", "lo", "hi", "bad", "cause", "pc", |
496 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
497 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
498 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
499 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
1faeff08 | 500 | "fsr", "fir", |
691c0433 AC |
501 | }; |
502 | ||
503 | /* Names of IDT R3041 registers. */ | |
504 | ||
505 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
506 | "sr", "lo", "hi", "bad", "cause", "pc", |
507 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
508 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
509 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
510 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
511 | "fsr", "fir", "", /*"fp" */ "", | |
512 | "", "", "bus", "ccfg", "", "", "", "", | |
513 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
514 | }; |
515 | ||
516 | /* Names of tx39 registers. */ | |
517 | ||
518 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
519 | "sr", "lo", "hi", "bad", "cause", "pc", |
520 | "", "", "", "", "", "", "", "", | |
521 | "", "", "", "", "", "", "", "", | |
522 | "", "", "", "", "", "", "", "", | |
523 | "", "", "", "", "", "", "", "", | |
524 | "", "", "", "", | |
525 | "", "", "", "", "", "", "", "", | |
1faeff08 | 526 | "", "", "config", "cache", "debug", "depc", "epc", |
691c0433 AC |
527 | }; |
528 | ||
529 | /* Names of IRIX registers. */ | |
530 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
531 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
532 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
533 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
534 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
535 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
536 | }; |
537 | ||
44099a67 | 538 | /* Names of registers with Linux kernels. */ |
1faeff08 MR |
539 | static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
540 | "sr", "lo", "hi", "bad", "cause", "pc", | |
541 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
542 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
543 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
544 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
545 | "fsr", "fir" | |
546 | }; | |
547 | ||
cce74817 | 548 | |
5e2e9765 | 549 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 550 | static const char * |
d93859e2 | 551 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 552 | { |
d93859e2 | 553 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 KB |
554 | /* GPR names for all ABIs other than n32/n64. */ |
555 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
556 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
557 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
558 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
559 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
560 | }; |
561 | ||
562 | /* GPR names for n32 and n64 ABIs. */ | |
563 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
564 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
565 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
566 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
567 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
568 | }; |
569 | ||
d93859e2 | 570 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 571 | |
f57d151a | 572 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
6229fbea HZ |
573 | but then don't make the raw register names visible. This (upper) |
574 | range of user visible register numbers are the pseudo-registers. | |
575 | ||
576 | This approach was adopted accommodate the following scenario: | |
577 | It is possible to debug a 64-bit device using a 32-bit | |
578 | programming model. In such instances, the raw registers are | |
579 | configured to be 64-bits wide, while the pseudo registers are | |
580 | configured to be 32-bits wide. The registers that the user | |
581 | sees - the pseudo registers - match the users expectations | |
582 | given the programming model being used. */ | |
d93859e2 UW |
583 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
584 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
585 | return ""; |
586 | ||
5e2e9765 KB |
587 | /* The MIPS integer registers are always mapped from 0 to 31. The |
588 | names of the registers (which reflects the conventions regarding | |
589 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 590 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
591 | { |
592 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 593 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 594 | else |
a4b8ebc8 | 595 | return mips_gpr_names[rawnum]; |
5e2e9765 | 596 | } |
d93859e2 UW |
597 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
598 | return tdesc_register_name (gdbarch, rawnum); | |
599 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
600 | { |
601 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
1faeff08 MR |
602 | if (tdep->mips_processor_reg_names[rawnum - 32]) |
603 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
604 | return ""; | |
691c0433 | 605 | } |
5e2e9765 KB |
606 | else |
607 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 608 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 609 | } |
5e2e9765 | 610 | |
a4b8ebc8 | 611 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 612 | |
a4b8ebc8 AC |
613 | static int |
614 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
615 | struct reggroup *reggroup) | |
616 | { | |
617 | int vector_p; | |
618 | int float_p; | |
619 | int raw_p; | |
72a155b4 UW |
620 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
621 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
622 | if (reggroup == all_reggroup) |
623 | return pseudo; | |
624 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
625 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
626 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
627 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
628 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
629 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
630 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
631 | return 0; |
632 | if (reggroup == float_reggroup) | |
633 | return float_p && pseudo; | |
634 | if (reggroup == vector_reggroup) | |
635 | return vector_p && pseudo; | |
636 | if (reggroup == general_reggroup) | |
637 | return (!vector_p && !float_p) && pseudo; | |
638 | /* Save the pseudo registers. Need to make certain that any code | |
639 | extracting register values from a saved register cache also uses | |
640 | pseudo registers. */ | |
641 | if (reggroup == save_reggroup) | |
642 | return raw_p && pseudo; | |
643 | /* Restore the same pseudo register. */ | |
644 | if (reggroup == restore_reggroup) | |
645 | return raw_p && pseudo; | |
6d82d43b | 646 | return 0; |
a4b8ebc8 AC |
647 | } |
648 | ||
f8b73d13 DJ |
649 | /* Return the groups that a MIPS register can be categorised into. |
650 | This version is only used if we have a target description which | |
651 | describes real registers (and their groups). */ | |
652 | ||
653 | static int | |
654 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
655 | struct reggroup *reggroup) | |
656 | { | |
657 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
658 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
659 | int ret; | |
660 | ||
661 | /* Only save, restore, and display the pseudo registers. Need to | |
662 | make certain that any code extracting register values from a | |
663 | saved register cache also uses pseudo registers. | |
664 | ||
665 | Note: saving and restoring the pseudo registers is slightly | |
666 | strange; if we have 64 bits, we should save and restore all | |
667 | 64 bits. But this is hard and has little benefit. */ | |
668 | if (!pseudo) | |
669 | return 0; | |
670 | ||
671 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
672 | if (ret != -1) | |
673 | return ret; | |
674 | ||
675 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
676 | } | |
677 | ||
a4b8ebc8 | 678 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 679 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 680 | registers. Take care of alignment and size problems. */ |
c5aa993b | 681 | |
05d1431c | 682 | static enum register_status |
a4b8ebc8 | 683 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
47a35522 | 684 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 685 | { |
72a155b4 UW |
686 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
687 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
688 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 689 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
05d1431c | 690 | return regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
691 | else if (register_size (gdbarch, rawnum) > |
692 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 693 | { |
8bdf35dc | 694 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
05d1431c | 695 | return regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
47ebcfbe | 696 | else |
8bdf35dc KB |
697 | { |
698 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
699 | LONGEST regval; | |
05d1431c PA |
700 | enum register_status status; |
701 | ||
702 | status = regcache_raw_read_signed (regcache, rawnum, ®val); | |
703 | if (status == REG_VALID) | |
704 | store_signed_integer (buf, 4, byte_order, regval); | |
705 | return status; | |
8bdf35dc | 706 | } |
47ebcfbe AC |
707 | } |
708 | else | |
e2e0b3e5 | 709 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
710 | } |
711 | ||
712 | static void | |
6d82d43b AC |
713 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
714 | struct regcache *regcache, int cookednum, | |
47a35522 | 715 | const gdb_byte *buf) |
a4b8ebc8 | 716 | { |
72a155b4 UW |
717 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
718 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
719 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 720 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 721 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
722 | else if (register_size (gdbarch, rawnum) > |
723 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 724 | { |
8bdf35dc | 725 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
47ebcfbe AC |
726 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
727 | else | |
8bdf35dc KB |
728 | { |
729 | /* Sign extend the shortened version of the register prior | |
730 | to placing it in the raw register. This is required for | |
731 | some mips64 parts in order to avoid unpredictable behavior. */ | |
732 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
733 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); | |
734 | regcache_raw_write_signed (regcache, rawnum, regval); | |
735 | } | |
47ebcfbe AC |
736 | } |
737 | else | |
e2e0b3e5 | 738 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 739 | } |
c5aa993b | 740 | |
175ff332 HZ |
741 | static int |
742 | mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
743 | struct agent_expr *ax, int reg) | |
744 | { | |
745 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
746 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
747 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
748 | ||
749 | ax_reg_mask (ax, rawnum); | |
750 | ||
751 | return 0; | |
752 | } | |
753 | ||
754 | static int | |
755 | mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, | |
756 | struct agent_expr *ax, int reg) | |
757 | { | |
758 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
759 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
760 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
761 | if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) | |
762 | { | |
763 | ax_reg (ax, rawnum); | |
764 | ||
765 | if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) | |
766 | { | |
767 | if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
768 | || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) | |
769 | { | |
770 | ax_const_l (ax, 32); | |
771 | ax_simple (ax, aop_lsh); | |
772 | } | |
773 | ax_const_l (ax, 32); | |
774 | ax_simple (ax, aop_rsh_signed); | |
775 | } | |
776 | } | |
777 | else | |
778 | internal_error (__FILE__, __LINE__, _("bad register size")); | |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
4cc0665f | 783 | /* Table to translate 3-bit register field to actual register number. */ |
d467df4e | 784 | static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
785 | |
786 | /* Heuristic_proc_start may hunt through the text section for a long | |
787 | time across a 2400 baud serial line. Allows the user to limit this | |
788 | search. */ | |
789 | ||
790 | static unsigned int heuristic_fence_post = 0; | |
791 | ||
46cd78fb | 792 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
793 | register N. NOTE: This defines the pseudo register type so need to |
794 | rebuild the architecture vector. */ | |
43e526b9 JM |
795 | |
796 | static int mips64_transfers_32bit_regs_p = 0; | |
797 | ||
719ec221 AC |
798 | static void |
799 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
800 | struct cmd_list_element *c) | |
43e526b9 | 801 | { |
719ec221 AC |
802 | struct gdbarch_info info; |
803 | gdbarch_info_init (&info); | |
804 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
805 | instead of relying on globals. Doing that would let generic code | |
806 | handle the search for this specific architecture. */ | |
807 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 808 | { |
719ec221 | 809 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 810 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 811 | } |
a4b8ebc8 AC |
812 | } |
813 | ||
47ebcfbe | 814 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 815 | |
ee51a8c7 KB |
816 | /* This predicate tests for the case of an 8 byte floating point |
817 | value that is being transferred to or from a pair of floating point | |
818 | registers each of which are (or are considered to be) only 4 bytes | |
819 | wide. */ | |
ff2e87ac | 820 | static int |
ee51a8c7 KB |
821 | mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
822 | struct type *type) | |
ff2e87ac | 823 | { |
0abe36f5 MD |
824 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
825 | && register_size (gdbarch, regnum) == 4 | |
004159a2 | 826 | && mips_float_register_p (gdbarch, regnum) |
6d82d43b | 827 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
828 | } |
829 | ||
ee51a8c7 KB |
830 | /* This predicate tests for the case of a value of less than 8 |
831 | bytes in width that is being transfered to or from an 8 byte | |
832 | general purpose register. */ | |
833 | static int | |
834 | mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, | |
835 | struct type *type) | |
836 | { | |
837 | int num_regs = gdbarch_num_regs (gdbarch); | |
838 | ||
839 | return (register_size (gdbarch, regnum) == 8 | |
840 | && regnum % num_regs > 0 && regnum % num_regs < 32 | |
841 | && TYPE_LENGTH (type) < 8); | |
842 | } | |
843 | ||
844 | static int | |
025bb325 MS |
845 | mips_convert_register_p (struct gdbarch *gdbarch, |
846 | int regnum, struct type *type) | |
ee51a8c7 KB |
847 | { |
848 | return mips_convert_register_float_case_p (gdbarch, regnum, type) | |
849 | || mips_convert_register_gpreg_case_p (gdbarch, regnum, type); | |
850 | } | |
851 | ||
8dccd430 | 852 | static int |
ff2e87ac | 853 | mips_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
854 | struct type *type, gdb_byte *to, |
855 | int *optimizedp, int *unavailablep) | |
102182a9 | 856 | { |
ee51a8c7 KB |
857 | struct gdbarch *gdbarch = get_frame_arch (frame); |
858 | ||
859 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
860 | { | |
861 | get_frame_register (frame, regnum + 0, to + 4); | |
862 | get_frame_register (frame, regnum + 1, to + 0); | |
8dccd430 PA |
863 | |
864 | if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4, | |
865 | optimizedp, unavailablep)) | |
866 | return 0; | |
867 | ||
868 | if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0, | |
869 | optimizedp, unavailablep)) | |
870 | return 0; | |
871 | *optimizedp = *unavailablep = 0; | |
872 | return 1; | |
ee51a8c7 KB |
873 | } |
874 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
875 | { | |
876 | int len = TYPE_LENGTH (type); | |
8dccd430 PA |
877 | CORE_ADDR offset; |
878 | ||
879 | offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; | |
880 | if (!get_frame_register_bytes (frame, regnum, offset, len, to, | |
881 | optimizedp, unavailablep)) | |
882 | return 0; | |
883 | ||
884 | *optimizedp = *unavailablep = 0; | |
885 | return 1; | |
ee51a8c7 KB |
886 | } |
887 | else | |
888 | { | |
889 | internal_error (__FILE__, __LINE__, | |
890 | _("mips_register_to_value: unrecognized case")); | |
891 | } | |
102182a9 MS |
892 | } |
893 | ||
42c466d7 | 894 | static void |
ff2e87ac | 895 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 896 | struct type *type, const gdb_byte *from) |
102182a9 | 897 | { |
ee51a8c7 KB |
898 | struct gdbarch *gdbarch = get_frame_arch (frame); |
899 | ||
900 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
901 | { | |
902 | put_frame_register (frame, regnum + 0, from + 4); | |
903 | put_frame_register (frame, regnum + 1, from + 0); | |
904 | } | |
905 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
906 | { | |
907 | gdb_byte fill[8]; | |
908 | int len = TYPE_LENGTH (type); | |
909 | ||
910 | /* Sign extend values, irrespective of type, that are stored to | |
911 | a 64-bit general purpose register. (32-bit unsigned values | |
912 | are stored as signed quantities within a 64-bit register. | |
913 | When performing an operation, in compiled code, that combines | |
914 | a 32-bit unsigned value with a signed 64-bit value, a type | |
915 | conversion is first performed that zeroes out the high 32 bits.) */ | |
916 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
917 | { | |
918 | if (from[0] & 0x80) | |
919 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); | |
920 | else | |
921 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); | |
922 | put_frame_register_bytes (frame, regnum, 0, 8 - len, fill); | |
923 | put_frame_register_bytes (frame, regnum, 8 - len, len, from); | |
924 | } | |
925 | else | |
926 | { | |
927 | if (from[len-1] & 0x80) | |
928 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); | |
929 | else | |
930 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); | |
931 | put_frame_register_bytes (frame, regnum, 0, len, from); | |
932 | put_frame_register_bytes (frame, regnum, len, 8 - len, fill); | |
933 | } | |
934 | } | |
935 | else | |
936 | { | |
937 | internal_error (__FILE__, __LINE__, | |
938 | _("mips_value_to_register: unrecognized case")); | |
939 | } | |
102182a9 MS |
940 | } |
941 | ||
a4b8ebc8 AC |
942 | /* Return the GDB type object for the "standard" data type of data in |
943 | register REG. */ | |
78fde5f8 KB |
944 | |
945 | static struct type * | |
a4b8ebc8 AC |
946 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
947 | { | |
72a155b4 | 948 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
004159a2 | 949 | if (mips_float_register_p (gdbarch, regnum)) |
a6425924 | 950 | { |
5ef80fb0 | 951 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 952 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 953 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 954 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 955 | else |
27067745 | 956 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 957 | } |
72a155b4 | 958 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
959 | { |
960 | /* The raw or ISA registers. These are all sized according to | |
961 | the ISA regsize. */ | |
962 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 963 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 964 | else |
df4df182 | 965 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 966 | } |
78fde5f8 | 967 | else |
d5ac5a39 | 968 | { |
1faeff08 MR |
969 | int rawnum = regnum - gdbarch_num_regs (gdbarch); |
970 | ||
d5ac5a39 AC |
971 | /* The cooked or ABI registers. These are sized according to |
972 | the ABI (with a few complications). */ | |
1faeff08 MR |
973 | if (rawnum == mips_regnum (gdbarch)->fp_control_status |
974 | || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) | |
975 | return builtin_type (gdbarch)->builtin_int32; | |
976 | else if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX | |
977 | && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX | |
978 | && rawnum >= MIPS_FIRST_EMBED_REGNUM | |
979 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
980 | /* The pseudo/cooked view of the embedded registers is always |
981 | 32-bit. The raw view is handled below. */ | |
df4df182 | 982 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
983 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
984 | /* The target, while possibly using a 64-bit register buffer, | |
985 | is only transfering 32-bits of each integer register. | |
986 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 987 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
988 | else if (mips_abi_regsize (gdbarch) == 4) |
989 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
990 | 32- or 64-bit). */ | |
df4df182 | 991 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
992 | else |
993 | /* 64-bit ABI. */ | |
df4df182 | 994 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 995 | } |
78fde5f8 KB |
996 | } |
997 | ||
f8b73d13 DJ |
998 | /* Return the GDB type for the pseudo register REGNUM, which is the |
999 | ABI-level view. This function is only called if there is a target | |
1000 | description which includes registers, so we know precisely the | |
1001 | types of hardware registers. */ | |
1002 | ||
1003 | static struct type * | |
1004 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
1005 | { | |
1006 | const int num_regs = gdbarch_num_regs (gdbarch); | |
1007 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1008 | int rawnum = regnum % num_regs; | |
1009 | struct type *rawtype; | |
1010 | ||
1011 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
1012 | ||
1013 | /* Absent registers are still absent. */ | |
1014 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
1015 | if (TYPE_LENGTH (rawtype) == 0) | |
1016 | return rawtype; | |
1017 | ||
de13fcf2 | 1018 | if (mips_float_register_p (gdbarch, rawnum)) |
f8b73d13 DJ |
1019 | /* Present the floating point registers however the hardware did; |
1020 | do not try to convert between FPU layouts. */ | |
1021 | return rawtype; | |
1022 | ||
f8b73d13 DJ |
1023 | /* Use pointer types for registers if we can. For n32 we can not, |
1024 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
1025 | if (mips_abi_regsize (gdbarch) |
1026 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 | 1027 | { |
1faeff08 MR |
1028 | if (rawnum == MIPS_SP_REGNUM |
1029 | || rawnum == mips_regnum (gdbarch)->badvaddr) | |
0dfff4cb | 1030 | return builtin_type (gdbarch)->builtin_data_ptr; |
1faeff08 | 1031 | else if (rawnum == mips_regnum (gdbarch)->pc) |
0dfff4cb | 1032 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
1033 | } |
1034 | ||
1035 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
1faeff08 MR |
1036 | && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM) |
1037 | || rawnum == mips_regnum (gdbarch)->lo | |
1038 | || rawnum == mips_regnum (gdbarch)->hi | |
1039 | || rawnum == mips_regnum (gdbarch)->badvaddr | |
1040 | || rawnum == mips_regnum (gdbarch)->cause | |
1041 | || rawnum == mips_regnum (gdbarch)->pc | |
1042 | || (mips_regnum (gdbarch)->dspacc != -1 | |
1043 | && rawnum >= mips_regnum (gdbarch)->dspacc | |
1044 | && rawnum < mips_regnum (gdbarch)->dspacc + 6))) | |
df4df182 | 1045 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 | 1046 | |
1faeff08 MR |
1047 | if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX |
1048 | && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX | |
1049 | && rawnum >= MIPS_EMBED_FP0_REGNUM + 32 | |
1050 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
1051 | { | |
1052 | /* The pseudo/cooked view of embedded registers is always | |
1053 | 32-bit, even if the target transfers 64-bit values for them. | |
1054 | New targets relying on XML descriptions should only transfer | |
1055 | the necessary 32 bits, but older versions of GDB expected 64, | |
1056 | so allow the target to provide 64 bits without interfering | |
1057 | with the displayed type. */ | |
1058 | return builtin_type (gdbarch)->builtin_int32; | |
1059 | } | |
1060 | ||
f8b73d13 DJ |
1061 | /* For all other registers, pass through the hardware type. */ |
1062 | return rawtype; | |
1063 | } | |
bcb0cc15 | 1064 | |
025bb325 | 1065 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 1066 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
1067 | |
1068 | static int | |
480d3dd2 | 1069 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
1070 | { |
1071 | switch (mask_address_var) | |
1072 | { | |
7f19b9a2 | 1073 | case AUTO_BOOLEAN_TRUE: |
4014092b | 1074 | return 1; |
7f19b9a2 | 1075 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
1076 | return 0; |
1077 | break; | |
7f19b9a2 | 1078 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 1079 | return tdep->default_mask_address_p; |
4014092b | 1080 | default: |
025bb325 MS |
1081 | internal_error (__FILE__, __LINE__, |
1082 | _("mips_mask_address_p: bad switch")); | |
4014092b | 1083 | return -1; |
361d1df0 | 1084 | } |
4014092b AC |
1085 | } |
1086 | ||
1087 | static void | |
08546159 AC |
1088 | show_mask_address (struct ui_file *file, int from_tty, |
1089 | struct cmd_list_element *c, const char *value) | |
4014092b | 1090 | { |
1cf3db46 | 1091 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
08546159 AC |
1092 | |
1093 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
1094 | switch (mask_address_var) |
1095 | { | |
7f19b9a2 | 1096 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
1097 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
1098 | break; | |
7f19b9a2 | 1099 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
1100 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
1101 | break; | |
7f19b9a2 | 1102 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
1103 | printf_filtered |
1104 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
1105 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
1106 | break; |
1107 | default: | |
e2e0b3e5 | 1108 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 1109 | break; |
361d1df0 | 1110 | } |
4014092b | 1111 | } |
c906108c | 1112 | |
4cc0665f MR |
1113 | /* Tell if the program counter value in MEMADDR is in a standard ISA |
1114 | function. */ | |
1115 | ||
1116 | int | |
1117 | mips_pc_is_mips (CORE_ADDR memaddr) | |
1118 | { | |
1119 | struct minimal_symbol *sym; | |
1120 | ||
1121 | /* Flags indicating that this is a MIPS16 or microMIPS function is | |
1122 | stored by elfread.c in the high bit of the info field. Use this | |
1123 | to decide if the function is standard MIPS. Otherwise if bit 0 | |
1124 | of the address is clear, then this is a standard MIPS function. */ | |
1125 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
1126 | if (sym) | |
1127 | return msymbol_is_mips (sym); | |
1128 | else | |
1129 | return is_mips_addr (memaddr); | |
1130 | } | |
1131 | ||
c906108c SS |
1132 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
1133 | ||
0fe7e7c8 | 1134 | int |
4cc0665f | 1135 | mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
c906108c SS |
1136 | { |
1137 | struct minimal_symbol *sym; | |
1138 | ||
91912e4d MR |
1139 | /* A flag indicating that this is a MIPS16 function is stored by |
1140 | elfread.c in the high bit of the info field. Use this to decide | |
4cc0665f MR |
1141 | if the function is MIPS16. Otherwise if bit 0 of the address is |
1142 | set, then ELF file flags will tell if this is a MIPS16 function. */ | |
1143 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
1144 | if (sym) | |
1145 | return msymbol_is_mips16 (sym); | |
1146 | else | |
1147 | return is_mips16_addr (gdbarch, memaddr); | |
1148 | } | |
1149 | ||
1150 | /* Tell if the program counter value in MEMADDR is in a microMIPS function. */ | |
1151 | ||
1152 | int | |
1153 | mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1154 | { | |
1155 | struct minimal_symbol *sym; | |
1156 | ||
1157 | /* A flag indicating that this is a microMIPS function is stored by | |
1158 | elfread.c in the high bit of the info field. Use this to decide | |
1159 | if the function is microMIPS. Otherwise if bit 0 of the address | |
1160 | is set, then ELF file flags will tell if this is a microMIPS | |
1161 | function. */ | |
1162 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
1163 | if (sym) | |
1164 | return msymbol_is_micromips (sym); | |
1165 | else | |
1166 | return is_micromips_addr (gdbarch, memaddr); | |
1167 | } | |
1168 | ||
1169 | /* Tell the ISA type of the function the program counter value in MEMADDR | |
1170 | is in. */ | |
1171 | ||
1172 | static enum mips_isa | |
1173 | mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1174 | { | |
1175 | struct minimal_symbol *sym; | |
1176 | ||
1177 | /* A flag indicating that this is a MIPS16 or a microMIPS function | |
1178 | is stored by elfread.c in the high bit of the info field. Use | |
1179 | this to decide if the function is MIPS16 or microMIPS or normal | |
1180 | MIPS. Otherwise if bit 0 of the address is set, then ELF file | |
1181 | flags will tell if this is a MIPS16 or a microMIPS function. */ | |
c906108c SS |
1182 | sym = lookup_minimal_symbol_by_pc (memaddr); |
1183 | if (sym) | |
4cc0665f MR |
1184 | { |
1185 | if (msymbol_is_micromips (sym)) | |
1186 | return ISA_MICROMIPS; | |
1187 | else if (msymbol_is_mips16 (sym)) | |
1188 | return ISA_MIPS16; | |
1189 | else | |
1190 | return ISA_MIPS; | |
1191 | } | |
c906108c | 1192 | else |
4cc0665f MR |
1193 | { |
1194 | if (is_mips_addr (memaddr)) | |
1195 | return ISA_MIPS; | |
1196 | else if (is_micromips_addr (gdbarch, memaddr)) | |
1197 | return ISA_MICROMIPS; | |
1198 | else | |
1199 | return ISA_MIPS16; | |
1200 | } | |
c906108c SS |
1201 | } |
1202 | ||
14132e89 MR |
1203 | /* Various MIPS16 thunk (aka stub or trampoline) names. */ |
1204 | ||
1205 | static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_"; | |
1206 | static const char mips_str_mips16_ret_stub[] = "__mips16_ret_"; | |
1207 | static const char mips_str_call_fp_stub[] = "__call_stub_fp_"; | |
1208 | static const char mips_str_call_stub[] = "__call_stub_"; | |
1209 | static const char mips_str_fn_stub[] = "__fn_stub_"; | |
1210 | ||
1211 | /* This is used as a PIC thunk prefix. */ | |
1212 | ||
1213 | static const char mips_str_pic[] = ".pic."; | |
1214 | ||
1215 | /* Return non-zero if the PC is inside a call thunk (aka stub or | |
1216 | trampoline) that should be treated as a temporary frame. */ | |
1217 | ||
1218 | static int | |
1219 | mips_in_frame_stub (CORE_ADDR pc) | |
1220 | { | |
1221 | CORE_ADDR start_addr; | |
1222 | const char *name; | |
1223 | ||
1224 | /* Find the starting address of the function containing the PC. */ | |
1225 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
1226 | return 0; | |
1227 | ||
1228 | /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */ | |
1229 | if (strncmp (name, mips_str_mips16_call_stub, | |
1230 | strlen (mips_str_mips16_call_stub)) == 0) | |
1231 | return 1; | |
1232 | /* If the PC is in __call_stub_*, this is a call/return or a call stub. */ | |
1233 | if (strncmp (name, mips_str_call_stub, strlen (mips_str_call_stub)) == 0) | |
1234 | return 1; | |
1235 | /* If the PC is in __fn_stub_*, this is a call stub. */ | |
1236 | if (strncmp (name, mips_str_fn_stub, strlen (mips_str_fn_stub)) == 0) | |
1237 | return 1; | |
1238 | ||
1239 | return 0; /* Not a stub. */ | |
1240 | } | |
1241 | ||
b2fa5097 | 1242 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
025bb325 | 1243 | all registers should be sign extended for simplicity? */ |
6c997a34 AC |
1244 | |
1245 | static CORE_ADDR | |
61a1198a | 1246 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 1247 | { |
8376de04 | 1248 | int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache)); |
61a1198a | 1249 | ULONGEST pc; |
8376de04 | 1250 | |
61a1198a | 1251 | regcache_cooked_read_signed (regcache, regnum, &pc); |
4cc0665f MR |
1252 | if (is_compact_addr (pc)) |
1253 | pc = unmake_compact_addr (pc); | |
61a1198a | 1254 | return pc; |
b6cb9035 AC |
1255 | } |
1256 | ||
58dfe9ff AC |
1257 | static CORE_ADDR |
1258 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1259 | { | |
14132e89 | 1260 | CORE_ADDR pc; |
930bd0e0 | 1261 | |
8376de04 | 1262 | pc = frame_unwind_register_signed (next_frame, gdbarch_pc_regnum (gdbarch)); |
4cc0665f MR |
1263 | if (is_compact_addr (pc)) |
1264 | pc = unmake_compact_addr (pc); | |
14132e89 MR |
1265 | /* macro/2012-04-20: This hack skips over MIPS16 call thunks as |
1266 | intermediate frames. In this case we can get the caller's address | |
1267 | from $ra, or if $ra contains an address within a thunk as well, then | |
1268 | it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10} | |
1269 | and thus the caller's address is in $s2. */ | |
1270 | if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc)) | |
1271 | { | |
1272 | pc = frame_unwind_register_signed | |
1273 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
4cc0665f MR |
1274 | if (is_compact_addr (pc)) |
1275 | pc = unmake_compact_addr (pc); | |
14132e89 MR |
1276 | if (mips_in_frame_stub (pc)) |
1277 | { | |
1278 | pc = frame_unwind_register_signed | |
1279 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
4cc0665f MR |
1280 | if (is_compact_addr (pc)) |
1281 | pc = unmake_compact_addr (pc); | |
14132e89 MR |
1282 | } |
1283 | } | |
930bd0e0 | 1284 | return pc; |
edfae063 AC |
1285 | } |
1286 | ||
30244cd8 UW |
1287 | static CORE_ADDR |
1288 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1289 | { | |
72a155b4 UW |
1290 | return frame_unwind_register_signed |
1291 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
1292 | } |
1293 | ||
b8a22b94 | 1294 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
1295 | dummy frame. The frame ID's base needs to match the TOS value |
1296 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1297 | breakpoint. */ | |
1298 | ||
1299 | static struct frame_id | |
b8a22b94 | 1300 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 1301 | { |
f57d151a | 1302 | return frame_id_build |
b8a22b94 DJ |
1303 | (get_frame_register_signed (this_frame, |
1304 | gdbarch_num_regs (gdbarch) | |
1305 | + MIPS_SP_REGNUM), | |
1306 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
1307 | } |
1308 | ||
5a439849 MR |
1309 | /* Implement the "write_pc" gdbarch method. */ |
1310 | ||
1311 | void | |
61a1198a | 1312 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 1313 | { |
8376de04 MR |
1314 | int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache)); |
1315 | ||
4cc0665f | 1316 | if (mips_pc_is_mips (pc)) |
930bd0e0 | 1317 | regcache_cooked_write_unsigned (regcache, regnum, pc); |
4cc0665f MR |
1318 | else |
1319 | regcache_cooked_write_unsigned (regcache, regnum, make_compact_addr (pc)); | |
6c997a34 | 1320 | } |
c906108c | 1321 | |
4cc0665f MR |
1322 | /* Fetch and return instruction from the specified location. Handle |
1323 | MIPS16/microMIPS as appropriate. */ | |
c906108c | 1324 | |
d37cca3d | 1325 | static ULONGEST |
4cc0665f MR |
1326 | mips_fetch_instruction (struct gdbarch *gdbarch, |
1327 | enum mips_isa isa, CORE_ADDR addr, int *statusp) | |
c906108c | 1328 | { |
e17a4113 | 1329 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1330 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
1331 | int instlen; |
1332 | int status; | |
1333 | ||
4cc0665f | 1334 | switch (isa) |
c906108c | 1335 | { |
4cc0665f MR |
1336 | case ISA_MICROMIPS: |
1337 | case ISA_MIPS16: | |
95ac2dcf | 1338 | instlen = MIPS_INSN16_SIZE; |
4cc0665f MR |
1339 | addr = unmake_compact_addr (addr); |
1340 | break; | |
1341 | case ISA_MIPS: | |
1342 | instlen = MIPS_INSN32_SIZE; | |
1343 | break; | |
1344 | default: | |
1345 | internal_error (__FILE__, __LINE__, _("invalid ISA")); | |
1346 | break; | |
c906108c | 1347 | } |
8defab1a | 1348 | status = target_read_memory (addr, buf, instlen); |
4cc0665f MR |
1349 | if (statusp != NULL) |
1350 | *statusp = status; | |
c906108c | 1351 | if (status) |
4cc0665f MR |
1352 | { |
1353 | if (statusp == NULL) | |
1354 | memory_error (status, addr); | |
1355 | return 0; | |
1356 | } | |
e17a4113 | 1357 | return extract_unsigned_integer (buf, instlen, byte_order); |
c906108c SS |
1358 | } |
1359 | ||
025bb325 | 1360 | /* These are the fields of 32 bit mips instructions. */ |
e135b889 DJ |
1361 | #define mips32_op(x) (x >> 26) |
1362 | #define itype_op(x) (x >> 26) | |
1363 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1364 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1365 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1366 | |
e135b889 DJ |
1367 | #define jtype_op(x) (x >> 26) |
1368 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1369 | |
e135b889 DJ |
1370 | #define rtype_op(x) (x >> 26) |
1371 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1372 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1373 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1374 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1375 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 1376 | |
4cc0665f MR |
1377 | /* MicroMIPS instruction fields. */ |
1378 | #define micromips_op(x) ((x) >> 10) | |
1379 | ||
1380 | /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest | |
1381 | bit and the size respectively of the field extracted. */ | |
1382 | #define b0s4_imm(x) ((x) & 0xf) | |
1383 | #define b0s5_imm(x) ((x) & 0x1f) | |
1384 | #define b0s5_reg(x) ((x) & 0x1f) | |
1385 | #define b0s7_imm(x) ((x) & 0x7f) | |
1386 | #define b0s10_imm(x) ((x) & 0x3ff) | |
1387 | #define b1s4_imm(x) (((x) >> 1) & 0xf) | |
1388 | #define b1s9_imm(x) (((x) >> 1) & 0x1ff) | |
1389 | #define b2s3_cc(x) (((x) >> 2) & 0x7) | |
1390 | #define b4s2_regl(x) (((x) >> 4) & 0x3) | |
1391 | #define b5s5_op(x) (((x) >> 5) & 0x1f) | |
1392 | #define b5s5_reg(x) (((x) >> 5) & 0x1f) | |
1393 | #define b6s4_op(x) (((x) >> 6) & 0xf) | |
1394 | #define b7s3_reg(x) (((x) >> 7) & 0x7) | |
1395 | ||
1396 | /* 32-bit instruction formats, B and S refer to the lowest bit and the size | |
1397 | respectively of the field extracted. */ | |
1398 | #define b0s6_op(x) ((x) & 0x3f) | |
1399 | #define b0s11_op(x) ((x) & 0x7ff) | |
1400 | #define b0s12_imm(x) ((x) & 0xfff) | |
1401 | #define b0s16_imm(x) ((x) & 0xffff) | |
1402 | #define b0s26_imm(x) ((x) & 0x3ffffff) | |
1403 | #define b6s10_ext(x) (((x) >> 6) & 0x3ff) | |
1404 | #define b11s5_reg(x) (((x) >> 11) & 0x1f) | |
1405 | #define b12s4_op(x) (((x) >> 12) & 0xf) | |
1406 | ||
1407 | /* Return the size in bytes of the instruction INSN encoded in the ISA | |
1408 | instruction set. */ | |
1409 | ||
1410 | static int | |
1411 | mips_insn_size (enum mips_isa isa, ULONGEST insn) | |
1412 | { | |
1413 | switch (isa) | |
1414 | { | |
1415 | case ISA_MICROMIPS: | |
1416 | if (micromips_op (insn) == 0x1f) | |
1417 | return 3 * MIPS_INSN16_SIZE; | |
1418 | else if (((micromips_op (insn) & 0x4) == 0x4) | |
1419 | || ((micromips_op (insn) & 0x7) == 0x0)) | |
1420 | return 2 * MIPS_INSN16_SIZE; | |
1421 | else | |
1422 | return MIPS_INSN16_SIZE; | |
1423 | case ISA_MIPS16: | |
1424 | if ((insn & 0xf800) == 0xf000) | |
1425 | return 2 * MIPS_INSN16_SIZE; | |
1426 | else | |
1427 | return MIPS_INSN16_SIZE; | |
1428 | case ISA_MIPS: | |
1429 | return MIPS_INSN32_SIZE; | |
1430 | } | |
1431 | internal_error (__FILE__, __LINE__, _("invalid ISA")); | |
1432 | } | |
1433 | ||
06987e64 MK |
1434 | static LONGEST |
1435 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 1436 | { |
06987e64 | 1437 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
1438 | } |
1439 | ||
a385295e MR |
1440 | /* Determine the address of the next instruction executed after the INST |
1441 | floating condition branch instruction at PC. COUNT specifies the | |
1442 | number of the floating condition bits tested by the branch. */ | |
1443 | ||
1444 | static CORE_ADDR | |
1445 | mips32_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame, | |
1446 | ULONGEST inst, CORE_ADDR pc, int count) | |
1447 | { | |
1448 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1449 | int cnum = (itype_rt (inst) >> 2) & (count - 1); | |
1450 | int tf = itype_rt (inst) & 1; | |
1451 | int mask = (1 << count) - 1; | |
1452 | ULONGEST fcs; | |
1453 | int cond; | |
1454 | ||
1455 | if (fcsr == -1) | |
1456 | /* No way to handle; it'll most likely trap anyway. */ | |
1457 | return pc; | |
1458 | ||
1459 | fcs = get_frame_register_unsigned (frame, fcsr); | |
1460 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); | |
1461 | ||
1462 | if (((cond >> cnum) & mask) != mask * !tf) | |
1463 | pc += mips32_relative_offset (inst); | |
1464 | else | |
1465 | pc += 4; | |
1466 | ||
1467 | return pc; | |
1468 | } | |
1469 | ||
f49e4e6d MS |
1470 | /* Determine where to set a single step breakpoint while considering |
1471 | branch prediction. */ | |
5a89d8aa | 1472 | static CORE_ADDR |
0b1b3e42 | 1473 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b | 1474 | { |
e17a4113 | 1475 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c5aa993b JM |
1476 | unsigned long inst; |
1477 | int op; | |
4cc0665f | 1478 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
025bb325 MS |
1479 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch |
1480 | instruction. */ | |
c5aa993b | 1481 | { |
e135b889 | 1482 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1483 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1484 | { |
e135b889 | 1485 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1486 | switch (op) |
1487 | { | |
e135b889 DJ |
1488 | case 0: /* BEQL */ |
1489 | goto equal_branch; | |
1490 | case 1: /* BNEL */ | |
1491 | goto neq_branch; | |
1492 | case 2: /* BLEZL */ | |
1493 | goto less_branch; | |
313628cc | 1494 | case 3: /* BGTZL */ |
e135b889 | 1495 | goto greater_branch; |
c5aa993b JM |
1496 | default: |
1497 | pc += 4; | |
c906108c SS |
1498 | } |
1499 | } | |
e135b889 | 1500 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1501 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e MR |
1502 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 1); |
1503 | else if (itype_op (inst) == 17 && itype_rs (inst) == 9 | |
1504 | && (itype_rt (inst) & 2) == 0) | |
1505 | /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ | |
1506 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 2); | |
1507 | else if (itype_op (inst) == 17 && itype_rs (inst) == 10 | |
1508 | && (itype_rt (inst) & 2) == 0) | |
1509 | /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ | |
1510 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 4); | |
9e8da49c MR |
1511 | else if (itype_op (inst) == 29) |
1512 | /* JALX: 011101 */ | |
1513 | /* The new PC will be alternate mode. */ | |
1514 | { | |
1515 | unsigned long reg; | |
1516 | ||
1517 | reg = jtype_target (inst) << 2; | |
1518 | /* Add 1 to indicate 16-bit mode -- invert ISA mode. */ | |
1519 | pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1; | |
1520 | } | |
c5aa993b | 1521 | else |
025bb325 | 1522 | pc += 4; /* Not a branch, next instruction is easy. */ |
c906108c SS |
1523 | } |
1524 | else | |
025bb325 | 1525 | { /* This gets way messy. */ |
c5aa993b | 1526 | |
025bb325 MS |
1527 | /* Further subdivide into SPECIAL, REGIMM and other. */ |
1528 | switch (op = itype_op (inst) & 0x07) /* Extract bits 28,27,26. */ | |
c906108c | 1529 | { |
c5aa993b JM |
1530 | case 0: /* SPECIAL */ |
1531 | op = rtype_funct (inst); | |
1532 | switch (op) | |
1533 | { | |
1534 | case 8: /* JR */ | |
1535 | case 9: /* JALR */ | |
025bb325 | 1536 | /* Set PC to that address. */ |
0b1b3e42 | 1537 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b | 1538 | break; |
e38d4e1a DJ |
1539 | case 12: /* SYSCALL */ |
1540 | { | |
1541 | struct gdbarch_tdep *tdep; | |
1542 | ||
1543 | tdep = gdbarch_tdep (get_frame_arch (frame)); | |
1544 | if (tdep->syscall_next_pc != NULL) | |
1545 | pc = tdep->syscall_next_pc (frame); | |
1546 | else | |
1547 | pc += 4; | |
1548 | } | |
1549 | break; | |
c5aa993b JM |
1550 | default: |
1551 | pc += 4; | |
1552 | } | |
1553 | ||
6d82d43b | 1554 | break; /* end SPECIAL */ |
025bb325 | 1555 | case 1: /* REGIMM */ |
c906108c | 1556 | { |
e135b889 DJ |
1557 | op = itype_rt (inst); /* branch condition */ |
1558 | switch (op) | |
c906108c | 1559 | { |
c5aa993b | 1560 | case 0: /* BLTZ */ |
e135b889 DJ |
1561 | case 2: /* BLTZL */ |
1562 | case 16: /* BLTZAL */ | |
c5aa993b | 1563 | case 18: /* BLTZALL */ |
c906108c | 1564 | less_branch: |
0b1b3e42 | 1565 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1566 | pc += mips32_relative_offset (inst) + 4; |
1567 | else | |
1568 | pc += 8; /* after the delay slot */ | |
1569 | break; | |
e135b889 | 1570 | case 1: /* BGEZ */ |
c5aa993b JM |
1571 | case 3: /* BGEZL */ |
1572 | case 17: /* BGEZAL */ | |
1573 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1574 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1575 | pc += mips32_relative_offset (inst) + 4; |
1576 | else | |
1577 | pc += 8; /* after the delay slot */ | |
1578 | break; | |
a385295e MR |
1579 | case 0x1c: /* BPOSGE32 */ |
1580 | case 0x1e: /* BPOSGE64 */ | |
1581 | pc += 4; | |
1582 | if (itype_rs (inst) == 0) | |
1583 | { | |
1584 | unsigned int pos = (op & 2) ? 64 : 32; | |
1585 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1586 | ||
1587 | if (dspctl == -1) | |
1588 | /* No way to handle; it'll most likely trap anyway. */ | |
1589 | break; | |
1590 | ||
1591 | if ((get_frame_register_unsigned (frame, | |
1592 | dspctl) & 0x7f) >= pos) | |
1593 | pc += mips32_relative_offset (inst); | |
1594 | else | |
1595 | pc += 4; | |
1596 | } | |
1597 | break; | |
e135b889 | 1598 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1599 | default: |
1600 | pc += 4; | |
c906108c SS |
1601 | } |
1602 | } | |
6d82d43b | 1603 | break; /* end REGIMM */ |
c5aa993b JM |
1604 | case 2: /* J */ |
1605 | case 3: /* JAL */ | |
1606 | { | |
1607 | unsigned long reg; | |
1608 | reg = jtype_target (inst) << 2; | |
025bb325 | 1609 | /* Upper four bits get never changed... */ |
5b652102 | 1610 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1611 | } |
c5aa993b | 1612 | break; |
e135b889 | 1613 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1614 | equal_branch: |
0b1b3e42 UW |
1615 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1616 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1617 | pc += mips32_relative_offset (inst) + 4; |
1618 | else | |
1619 | pc += 8; | |
1620 | break; | |
e135b889 | 1621 | case 5: /* BNE, BNEL */ |
c5aa993b | 1622 | neq_branch: |
0b1b3e42 UW |
1623 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1624 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1625 | pc += mips32_relative_offset (inst) + 4; |
1626 | else | |
1627 | pc += 8; | |
1628 | break; | |
e135b889 | 1629 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1630 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1631 | pc += mips32_relative_offset (inst) + 4; |
1632 | else | |
1633 | pc += 8; | |
1634 | break; | |
1635 | case 7: | |
e135b889 DJ |
1636 | default: |
1637 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1638 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1639 | pc += mips32_relative_offset (inst) + 4; |
1640 | else | |
1641 | pc += 8; | |
1642 | break; | |
c5aa993b JM |
1643 | } /* switch */ |
1644 | } /* else */ | |
1645 | return pc; | |
1646 | } /* mips32_next_pc */ | |
c906108c | 1647 | |
4cc0665f MR |
1648 | /* Extract the 7-bit signed immediate offset from the microMIPS instruction |
1649 | INSN. */ | |
1650 | ||
1651 | static LONGEST | |
1652 | micromips_relative_offset7 (ULONGEST insn) | |
1653 | { | |
1654 | return ((b0s7_imm (insn) ^ 0x40) - 0x40) << 1; | |
1655 | } | |
1656 | ||
1657 | /* Extract the 10-bit signed immediate offset from the microMIPS instruction | |
1658 | INSN. */ | |
1659 | ||
1660 | static LONGEST | |
1661 | micromips_relative_offset10 (ULONGEST insn) | |
1662 | { | |
1663 | return ((b0s10_imm (insn) ^ 0x200) - 0x200) << 1; | |
1664 | } | |
1665 | ||
1666 | /* Extract the 16-bit signed immediate offset from the microMIPS instruction | |
1667 | INSN. */ | |
1668 | ||
1669 | static LONGEST | |
1670 | micromips_relative_offset16 (ULONGEST insn) | |
1671 | { | |
1672 | return ((b0s16_imm (insn) ^ 0x8000) - 0x8000) << 1; | |
1673 | } | |
1674 | ||
1675 | /* Return the size in bytes of the microMIPS instruction at the address PC. */ | |
1676 | ||
1677 | static int | |
1678 | micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1679 | { | |
1680 | ULONGEST insn; | |
1681 | ||
1682 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1683 | return mips_insn_size (ISA_MICROMIPS, insn); | |
1684 | } | |
1685 | ||
1686 | /* Calculate the address of the next microMIPS instruction to execute | |
1687 | after the INSN coprocessor 1 conditional branch instruction at the | |
1688 | address PC. COUNT denotes the number of coprocessor condition bits | |
1689 | examined by the branch. */ | |
1690 | ||
1691 | static CORE_ADDR | |
1692 | micromips_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame, | |
1693 | ULONGEST insn, CORE_ADDR pc, int count) | |
1694 | { | |
1695 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1696 | int cnum = b2s3_cc (insn >> 16) & (count - 1); | |
1697 | int tf = b5s5_op (insn >> 16) & 1; | |
1698 | int mask = (1 << count) - 1; | |
1699 | ULONGEST fcs; | |
1700 | int cond; | |
1701 | ||
1702 | if (fcsr == -1) | |
1703 | /* No way to handle; it'll most likely trap anyway. */ | |
1704 | return pc; | |
1705 | ||
1706 | fcs = get_frame_register_unsigned (frame, fcsr); | |
1707 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); | |
1708 | ||
1709 | if (((cond >> cnum) & mask) != mask * !tf) | |
1710 | pc += micromips_relative_offset16 (insn); | |
1711 | else | |
1712 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1713 | ||
1714 | return pc; | |
1715 | } | |
1716 | ||
1717 | /* Calculate the address of the next microMIPS instruction to execute | |
1718 | after the instruction at the address PC. */ | |
1719 | ||
1720 | static CORE_ADDR | |
1721 | micromips_next_pc (struct frame_info *frame, CORE_ADDR pc) | |
1722 | { | |
1723 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
1724 | ULONGEST insn; | |
1725 | ||
1726 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1727 | pc += MIPS_INSN16_SIZE; | |
1728 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
1729 | { | |
1730 | /* 48-bit instructions. */ | |
1731 | case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */ | |
1732 | /* No branch or jump instructions in this category. */ | |
1733 | pc += 2 * MIPS_INSN16_SIZE; | |
1734 | break; | |
1735 | ||
1736 | /* 32-bit instructions. */ | |
1737 | case 2 * MIPS_INSN16_SIZE: | |
1738 | insn <<= 16; | |
1739 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1740 | pc += MIPS_INSN16_SIZE; | |
1741 | switch (micromips_op (insn >> 16)) | |
1742 | { | |
1743 | case 0x00: /* POOL32A: bits 000000 */ | |
1744 | if (b0s6_op (insn) == 0x3c | |
1745 | /* POOL32Axf: bits 000000 ... 111100 */ | |
1746 | && (b6s10_ext (insn) & 0x2bf) == 0x3c) | |
1747 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
1748 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
1749 | pc = get_frame_register_signed (frame, b0s5_reg (insn >> 16)); | |
1750 | break; | |
1751 | ||
1752 | case 0x10: /* POOL32I: bits 010000 */ | |
1753 | switch (b5s5_op (insn >> 16)) | |
1754 | { | |
1755 | case 0x00: /* BLTZ: bits 010000 00000 */ | |
1756 | case 0x01: /* BLTZAL: bits 010000 00001 */ | |
1757 | case 0x11: /* BLTZALS: bits 010000 10001 */ | |
1758 | if (get_frame_register_signed (frame, | |
1759 | b0s5_reg (insn >> 16)) < 0) | |
1760 | pc += micromips_relative_offset16 (insn); | |
1761 | else | |
1762 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1763 | break; | |
1764 | ||
1765 | case 0x02: /* BGEZ: bits 010000 00010 */ | |
1766 | case 0x03: /* BGEZAL: bits 010000 00011 */ | |
1767 | case 0x13: /* BGEZALS: bits 010000 10011 */ | |
1768 | if (get_frame_register_signed (frame, | |
1769 | b0s5_reg (insn >> 16)) >= 0) | |
1770 | pc += micromips_relative_offset16 (insn); | |
1771 | else | |
1772 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1773 | break; | |
1774 | ||
1775 | case 0x04: /* BLEZ: bits 010000 00100 */ | |
1776 | if (get_frame_register_signed (frame, | |
1777 | b0s5_reg (insn >> 16)) <= 0) | |
1778 | pc += micromips_relative_offset16 (insn); | |
1779 | else | |
1780 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1781 | break; | |
1782 | ||
1783 | case 0x05: /* BNEZC: bits 010000 00101 */ | |
1784 | if (get_frame_register_signed (frame, | |
1785 | b0s5_reg (insn >> 16)) != 0) | |
1786 | pc += micromips_relative_offset16 (insn); | |
1787 | break; | |
1788 | ||
1789 | case 0x06: /* BGTZ: bits 010000 00110 */ | |
1790 | if (get_frame_register_signed (frame, | |
1791 | b0s5_reg (insn >> 16)) > 0) | |
1792 | pc += micromips_relative_offset16 (insn); | |
1793 | else | |
1794 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1795 | break; | |
1796 | ||
1797 | case 0x07: /* BEQZC: bits 010000 00111 */ | |
1798 | if (get_frame_register_signed (frame, | |
1799 | b0s5_reg (insn >> 16)) == 0) | |
1800 | pc += micromips_relative_offset16 (insn); | |
1801 | break; | |
1802 | ||
1803 | case 0x14: /* BC2F: bits 010000 10100 xxx00 */ | |
1804 | case 0x15: /* BC2T: bits 010000 10101 xxx00 */ | |
1805 | if (((insn >> 16) & 0x3) == 0x0) | |
1806 | /* BC2F, BC2T: don't know how to handle these. */ | |
1807 | break; | |
1808 | break; | |
1809 | ||
1810 | case 0x1a: /* BPOSGE64: bits 010000 11010 */ | |
1811 | case 0x1b: /* BPOSGE32: bits 010000 11011 */ | |
1812 | { | |
1813 | unsigned int pos = (b5s5_op (insn >> 16) & 1) ? 32 : 64; | |
1814 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1815 | ||
1816 | if (dspctl == -1) | |
1817 | /* No way to handle; it'll most likely trap anyway. */ | |
1818 | break; | |
1819 | ||
1820 | if ((get_frame_register_unsigned (frame, | |
1821 | dspctl) & 0x7f) >= pos) | |
1822 | pc += micromips_relative_offset16 (insn); | |
1823 | else | |
1824 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1825 | } | |
1826 | break; | |
1827 | ||
1828 | case 0x1c: /* BC1F: bits 010000 11100 xxx00 */ | |
1829 | /* BC1ANY2F: bits 010000 11100 xxx01 */ | |
1830 | case 0x1d: /* BC1T: bits 010000 11101 xxx00 */ | |
1831 | /* BC1ANY2T: bits 010000 11101 xxx01 */ | |
1832 | if (((insn >> 16) & 0x2) == 0x0) | |
1833 | pc = micromips_bc1_pc (gdbarch, frame, insn, pc, | |
1834 | ((insn >> 16) & 0x1) + 1); | |
1835 | break; | |
1836 | ||
1837 | case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */ | |
1838 | case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */ | |
1839 | if (((insn >> 16) & 0x3) == 0x1) | |
1840 | pc = micromips_bc1_pc (gdbarch, frame, insn, pc, 4); | |
1841 | break; | |
1842 | } | |
1843 | break; | |
1844 | ||
1845 | case 0x1d: /* JALS: bits 011101 */ | |
1846 | case 0x35: /* J: bits 110101 */ | |
1847 | case 0x3d: /* JAL: bits 111101 */ | |
1848 | pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1); | |
1849 | break; | |
1850 | ||
1851 | case 0x25: /* BEQ: bits 100101 */ | |
1852 | if (get_frame_register_signed (frame, b0s5_reg (insn >> 16)) | |
1853 | == get_frame_register_signed (frame, b5s5_reg (insn >> 16))) | |
1854 | pc += micromips_relative_offset16 (insn); | |
1855 | else | |
1856 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1857 | break; | |
1858 | ||
1859 | case 0x2d: /* BNE: bits 101101 */ | |
1860 | if (get_frame_register_signed (frame, b0s5_reg (insn >> 16)) | |
1861 | != get_frame_register_signed (frame, b5s5_reg (insn >> 16))) | |
1862 | pc += micromips_relative_offset16 (insn); | |
1863 | else | |
1864 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1865 | break; | |
1866 | ||
1867 | case 0x3c: /* JALX: bits 111100 */ | |
1868 | pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2); | |
1869 | break; | |
1870 | } | |
1871 | break; | |
1872 | ||
1873 | /* 16-bit instructions. */ | |
1874 | case MIPS_INSN16_SIZE: | |
1875 | switch (micromips_op (insn)) | |
1876 | { | |
1877 | case 0x11: /* POOL16C: bits 010001 */ | |
1878 | if ((b5s5_op (insn) & 0x1c) == 0xc) | |
1879 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
1880 | pc = get_frame_register_signed (frame, b0s5_reg (insn)); | |
1881 | else if (b5s5_op (insn) == 0x18) | |
1882 | /* JRADDIUSP: bits 010001 11000 */ | |
1883 | pc = get_frame_register_signed (frame, MIPS_RA_REGNUM); | |
1884 | break; | |
1885 | ||
1886 | case 0x23: /* BEQZ16: bits 100011 */ | |
1887 | { | |
1888 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
1889 | ||
1890 | if (get_frame_register_signed (frame, rs) == 0) | |
1891 | pc += micromips_relative_offset7 (insn); | |
1892 | else | |
1893 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1894 | } | |
1895 | break; | |
1896 | ||
1897 | case 0x2b: /* BNEZ16: bits 101011 */ | |
1898 | { | |
1899 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
1900 | ||
1901 | if (get_frame_register_signed (frame, rs) != 0) | |
1902 | pc += micromips_relative_offset7 (insn); | |
1903 | else | |
1904 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1905 | } | |
1906 | break; | |
1907 | ||
1908 | case 0x33: /* B16: bits 110011 */ | |
1909 | pc += micromips_relative_offset10 (insn); | |
1910 | break; | |
1911 | } | |
1912 | break; | |
1913 | } | |
1914 | ||
1915 | return pc; | |
1916 | } | |
1917 | ||
c906108c | 1918 | /* Decoding the next place to set a breakpoint is irregular for the |
025bb325 MS |
1919 | mips 16 variant, but fortunately, there fewer instructions. We have |
1920 | to cope ith extensions for 16 bit instructions and a pair of actual | |
1921 | 32 bit instructions. We dont want to set a single step instruction | |
1922 | on the extend instruction either. */ | |
c906108c SS |
1923 | |
1924 | /* Lots of mips16 instruction formats */ | |
1925 | /* Predicting jumps requires itype,ritype,i8type | |
025bb325 | 1926 | and their extensions extItype,extritype,extI8type. */ |
c906108c SS |
1927 | enum mips16_inst_fmts |
1928 | { | |
c5aa993b JM |
1929 | itype, /* 0 immediate 5,10 */ |
1930 | ritype, /* 1 5,3,8 */ | |
1931 | rrtype, /* 2 5,3,3,5 */ | |
1932 | rritype, /* 3 5,3,3,5 */ | |
1933 | rrrtype, /* 4 5,3,3,3,2 */ | |
1934 | rriatype, /* 5 5,3,3,1,4 */ | |
1935 | shifttype, /* 6 5,3,3,3,2 */ | |
1936 | i8type, /* 7 5,3,8 */ | |
1937 | i8movtype, /* 8 5,3,3,5 */ | |
1938 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1939 | i64type, /* 10 5,3,8 */ | |
1940 | ri64type, /* 11 5,3,3,5 */ | |
1941 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1942 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1943 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1944 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1945 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1946 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1947 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1948 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1949 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1950 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1951 | }; | |
12f02c2a | 1952 | /* I am heaping all the fields of the formats into one structure and |
025bb325 | 1953 | then, only the fields which are involved in instruction extension. */ |
c906108c | 1954 | struct upk_mips16 |
6d82d43b AC |
1955 | { |
1956 | CORE_ADDR offset; | |
025bb325 | 1957 | unsigned int regx; /* Function in i8 type. */ |
6d82d43b AC |
1958 | unsigned int regy; |
1959 | }; | |
c906108c SS |
1960 | |
1961 | ||
12f02c2a | 1962 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 1963 | for the bits which make up the immediate extension. */ |
c906108c | 1964 | |
12f02c2a AC |
1965 | static CORE_ADDR |
1966 | extended_offset (unsigned int extension) | |
c906108c | 1967 | { |
12f02c2a | 1968 | CORE_ADDR value; |
130854df | 1969 | |
4c2051c6 | 1970 | value = (extension >> 16) & 0x1f; /* Extract 15:11. */ |
c5aa993b | 1971 | value = value << 6; |
4c2051c6 | 1972 | value |= (extension >> 21) & 0x3f; /* Extract 10:5. */ |
c5aa993b | 1973 | value = value << 5; |
130854df MR |
1974 | value |= extension & 0x1f; /* Extract 4:0. */ |
1975 | ||
c5aa993b | 1976 | return value; |
c906108c SS |
1977 | } |
1978 | ||
1979 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
1980 | instruction. It won't malfunction, but why make excess remote memory |
1981 | references? If the immediate operands get sign extended or something, | |
1982 | do it after the extension is performed. */ | |
c906108c | 1983 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 1984 | when the offset is to be used in relative addressing. */ |
c906108c | 1985 | |
12f02c2a | 1986 | static unsigned int |
e17a4113 | 1987 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 1988 | { |
e17a4113 | 1989 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1990 | gdb_byte buf[8]; |
025bb325 | 1991 | pc &= 0xfffffffe; /* Clear the low order bit. */ |
c5aa993b | 1992 | target_read_memory (pc, buf, 2); |
e17a4113 | 1993 | return extract_unsigned_integer (buf, 2, byte_order); |
c906108c SS |
1994 | } |
1995 | ||
1996 | static void | |
e17a4113 | 1997 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
12f02c2a AC |
1998 | unsigned int extension, |
1999 | unsigned int inst, | |
6d82d43b | 2000 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 2001 | { |
12f02c2a AC |
2002 | CORE_ADDR offset; |
2003 | int regx; | |
2004 | int regy; | |
2005 | switch (insn_format) | |
c906108c | 2006 | { |
c5aa993b | 2007 | case itype: |
c906108c | 2008 | { |
12f02c2a AC |
2009 | CORE_ADDR value; |
2010 | if (extension) | |
c5aa993b | 2011 | { |
4c2051c6 MR |
2012 | value = extended_offset ((extension << 16) | inst); |
2013 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c SS |
2014 | } |
2015 | else | |
c5aa993b | 2016 | { |
12f02c2a | 2017 | value = inst & 0x7ff; |
4c2051c6 | 2018 | value = (value ^ 0x400) - 0x400; /* Sign-extend. */ |
c906108c | 2019 | } |
12f02c2a AC |
2020 | offset = value; |
2021 | regx = -1; | |
2022 | regy = -1; | |
c906108c | 2023 | } |
c5aa993b JM |
2024 | break; |
2025 | case ritype: | |
2026 | case i8type: | |
025bb325 | 2027 | { /* A register identifier and an offset. */ |
c906108c | 2028 | /* Most of the fields are the same as I type but the |
025bb325 | 2029 | immediate value is of a different length. */ |
12f02c2a AC |
2030 | CORE_ADDR value; |
2031 | if (extension) | |
c906108c | 2032 | { |
4c2051c6 MR |
2033 | value = extended_offset ((extension << 16) | inst); |
2034 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c | 2035 | } |
c5aa993b JM |
2036 | else |
2037 | { | |
4c2051c6 MR |
2038 | value = inst & 0xff; /* 8 bits */ |
2039 | value = (value ^ 0x80) - 0x80; /* Sign-extend. */ | |
c5aa993b | 2040 | } |
12f02c2a | 2041 | offset = value; |
4c2051c6 | 2042 | regx = (inst >> 8) & 0x07; /* i8 funct */ |
12f02c2a | 2043 | regy = -1; |
c5aa993b | 2044 | break; |
c906108c | 2045 | } |
c5aa993b | 2046 | case jalxtype: |
c906108c | 2047 | { |
c5aa993b | 2048 | unsigned long value; |
12f02c2a AC |
2049 | unsigned int nexthalf; |
2050 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b | 2051 | value = value << 16; |
4cc0665f MR |
2052 | nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL); |
2053 | /* Low bit still set. */ | |
c5aa993b | 2054 | value |= nexthalf; |
12f02c2a AC |
2055 | offset = value; |
2056 | regx = -1; | |
2057 | regy = -1; | |
c5aa993b | 2058 | break; |
c906108c SS |
2059 | } |
2060 | default: | |
e2e0b3e5 | 2061 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 2062 | } |
12f02c2a AC |
2063 | upk->offset = offset; |
2064 | upk->regx = regx; | |
2065 | upk->regy = regy; | |
c906108c SS |
2066 | } |
2067 | ||
2068 | ||
c5aa993b JM |
2069 | static CORE_ADDR |
2070 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 2071 | { |
5b652102 | 2072 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
2073 | } |
2074 | ||
12f02c2a | 2075 | static CORE_ADDR |
0b1b3e42 | 2076 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 2077 | unsigned int extension, unsigned int insn) |
c906108c | 2078 | { |
e17a4113 | 2079 | struct gdbarch *gdbarch = get_frame_arch (frame); |
12f02c2a AC |
2080 | int op = (insn >> 11); |
2081 | switch (op) | |
c906108c | 2082 | { |
6d82d43b | 2083 | case 2: /* Branch */ |
12f02c2a | 2084 | { |
12f02c2a | 2085 | struct upk_mips16 upk; |
e17a4113 | 2086 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
4c2051c6 | 2087 | pc += (upk.offset << 1) + 2; |
12f02c2a AC |
2088 | break; |
2089 | } | |
025bb325 MS |
2090 | case 3: /* JAL , JALX - Watch out, these are 32 bit |
2091 | instructions. */ | |
12f02c2a AC |
2092 | { |
2093 | struct upk_mips16 upk; | |
e17a4113 | 2094 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
12f02c2a AC |
2095 | pc = add_offset_16 (pc, upk.offset); |
2096 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
025bb325 | 2097 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ |
12f02c2a AC |
2098 | else |
2099 | pc |= 0x01; | |
2100 | break; | |
2101 | } | |
6d82d43b | 2102 | case 4: /* beqz */ |
12f02c2a AC |
2103 | { |
2104 | struct upk_mips16 upk; | |
2105 | int reg; | |
e17a4113 | 2106 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
4cc0665f | 2107 | reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]); |
12f02c2a AC |
2108 | if (reg == 0) |
2109 | pc += (upk.offset << 1) + 2; | |
2110 | else | |
2111 | pc += 2; | |
2112 | break; | |
2113 | } | |
6d82d43b | 2114 | case 5: /* bnez */ |
12f02c2a AC |
2115 | { |
2116 | struct upk_mips16 upk; | |
2117 | int reg; | |
e17a4113 | 2118 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
4cc0665f | 2119 | reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]); |
12f02c2a AC |
2120 | if (reg != 0) |
2121 | pc += (upk.offset << 1) + 2; | |
2122 | else | |
2123 | pc += 2; | |
2124 | break; | |
2125 | } | |
6d82d43b | 2126 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
2127 | { |
2128 | struct upk_mips16 upk; | |
2129 | int reg; | |
e17a4113 | 2130 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
12f02c2a | 2131 | /* upk.regx contains the opcode */ |
0b1b3e42 | 2132 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
2133 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
2134 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
2135 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
2136 | pc += (upk.offset << 1) + 2; | |
2137 | else | |
2138 | pc += 2; | |
2139 | break; | |
2140 | } | |
6d82d43b | 2141 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
2142 | { |
2143 | struct upk_mips16 upk; | |
2144 | /* upk.fmt = rrtype; */ | |
2145 | op = insn & 0x1f; | |
2146 | if (op == 0) | |
c5aa993b | 2147 | { |
12f02c2a AC |
2148 | int reg; |
2149 | upk.regx = (insn >> 8) & 0x07; | |
2150 | upk.regy = (insn >> 5) & 0x07; | |
4c2051c6 | 2151 | if ((upk.regy & 1) == 0) |
4cc0665f | 2152 | reg = mips_reg3_to_reg[upk.regx]; |
4c2051c6 MR |
2153 | else |
2154 | reg = 31; /* Function return instruction. */ | |
0b1b3e42 | 2155 | pc = get_frame_register_signed (frame, reg); |
c906108c | 2156 | } |
12f02c2a | 2157 | else |
c5aa993b | 2158 | pc += 2; |
12f02c2a AC |
2159 | break; |
2160 | } | |
2161 | case 30: | |
2162 | /* This is an instruction extension. Fetch the real instruction | |
2163 | (which follows the extension) and decode things based on | |
025bb325 | 2164 | that. */ |
12f02c2a AC |
2165 | { |
2166 | pc += 2; | |
e17a4113 UW |
2167 | pc = extended_mips16_next_pc (frame, pc, insn, |
2168 | fetch_mips_16 (gdbarch, pc)); | |
12f02c2a AC |
2169 | break; |
2170 | } | |
2171 | default: | |
2172 | { | |
2173 | pc += 2; | |
2174 | break; | |
2175 | } | |
c906108c | 2176 | } |
c5aa993b | 2177 | return pc; |
12f02c2a | 2178 | } |
c906108c | 2179 | |
5a89d8aa | 2180 | static CORE_ADDR |
0b1b3e42 | 2181 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a | 2182 | { |
e17a4113 UW |
2183 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2184 | unsigned int insn = fetch_mips_16 (gdbarch, pc); | |
0b1b3e42 | 2185 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
2186 | } |
2187 | ||
2188 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 2189 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a | 2190 | It works by decoding the current instruction and predicting where a |
025bb325 | 2191 | branch will go. This isnt hard because all the data is available. |
4cc0665f | 2192 | The MIPS32, MIPS16 and microMIPS variants are quite different. */ |
ad527d2e | 2193 | static CORE_ADDR |
0b1b3e42 | 2194 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 2195 | { |
4cc0665f MR |
2196 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2197 | ||
2198 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
0b1b3e42 | 2199 | return mips16_next_pc (frame, pc); |
4cc0665f MR |
2200 | else if (mips_pc_is_micromips (gdbarch, pc)) |
2201 | return micromips_next_pc (frame, pc); | |
c5aa993b | 2202 | else |
0b1b3e42 | 2203 | return mips32_next_pc (frame, pc); |
12f02c2a | 2204 | } |
c906108c | 2205 | |
edfae063 AC |
2206 | struct mips_frame_cache |
2207 | { | |
2208 | CORE_ADDR base; | |
2209 | struct trad_frame_saved_reg *saved_regs; | |
2210 | }; | |
2211 | ||
29639122 JB |
2212 | /* Set a register's saved stack address in temp_saved_regs. If an |
2213 | address has already been set for this register, do nothing; this | |
2214 | way we will only recognize the first save of a given register in a | |
2215 | function prologue. | |
eec63939 | 2216 | |
f57d151a UW |
2217 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
2218 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
2219 | Strictly speaking, only the second range is used as it is only second | |
2220 | range (the ABI instead of ISA registers) that comes into play when finding | |
2221 | saved registers in a frame. */ | |
eec63939 AC |
2222 | |
2223 | static void | |
74ed0bb4 MD |
2224 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
2225 | int regnum, CORE_ADDR offset) | |
eec63939 | 2226 | { |
29639122 JB |
2227 | if (this_cache != NULL |
2228 | && this_cache->saved_regs[regnum].addr == -1) | |
2229 | { | |
74ed0bb4 MD |
2230 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
2231 | = offset; | |
2232 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr | |
2233 | = offset; | |
29639122 | 2234 | } |
eec63939 AC |
2235 | } |
2236 | ||
eec63939 | 2237 | |
29639122 JB |
2238 | /* Fetch the immediate value from a MIPS16 instruction. |
2239 | If the previous instruction was an EXTEND, use it to extend | |
2240 | the upper bits of the immediate value. This is a helper function | |
2241 | for mips16_scan_prologue. */ | |
eec63939 | 2242 | |
29639122 JB |
2243 | static int |
2244 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
2245 | unsigned short inst, /* current instruction */ | |
2246 | int nbits, /* number of bits in imm field */ | |
2247 | int scale, /* scale factor to be applied to imm */ | |
025bb325 | 2248 | int is_signed) /* is the imm field signed? */ |
eec63939 | 2249 | { |
29639122 | 2250 | int offset; |
eec63939 | 2251 | |
29639122 JB |
2252 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
2253 | { | |
2254 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
2255 | if (offset & 0x8000) /* check for negative extend */ | |
2256 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
2257 | return offset | (inst & 0x1f); | |
2258 | } | |
eec63939 | 2259 | else |
29639122 JB |
2260 | { |
2261 | int max_imm = 1 << nbits; | |
2262 | int mask = max_imm - 1; | |
2263 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 2264 | |
29639122 JB |
2265 | offset = inst & mask; |
2266 | if (is_signed && (offset & sign_bit)) | |
2267 | offset = 0 - (max_imm - offset); | |
2268 | return offset * scale; | |
2269 | } | |
2270 | } | |
eec63939 | 2271 | |
65596487 | 2272 | |
29639122 JB |
2273 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
2274 | the associated FRAME_CACHE if not null. | |
2275 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 2276 | |
29639122 | 2277 | static CORE_ADDR |
e17a4113 UW |
2278 | mips16_scan_prologue (struct gdbarch *gdbarch, |
2279 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 2280 | struct frame_info *this_frame, |
29639122 JB |
2281 | struct mips_frame_cache *this_cache) |
2282 | { | |
2283 | CORE_ADDR cur_pc; | |
025bb325 | 2284 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ |
29639122 JB |
2285 | CORE_ADDR sp; |
2286 | long frame_offset = 0; /* Size of stack frame. */ | |
2287 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
2288 | int frame_reg = MIPS_SP_REGNUM; | |
025bb325 | 2289 | unsigned short prev_inst = 0; /* saved copy of previous instruction. */ |
29639122 JB |
2290 | unsigned inst = 0; /* current instruction */ |
2291 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 2292 | unsigned save_inst = 0; /* the save instruction */ |
29639122 | 2293 | int reg, offset; |
a343eb3c | 2294 | |
29639122 JB |
2295 | int extend_bytes = 0; |
2296 | int prev_extend_bytes; | |
2297 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 2298 | |
29639122 | 2299 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
2300 | THIS_FRAME. */ |
2301 | if (this_frame != NULL) | |
2302 | sp = get_frame_register_signed (this_frame, | |
2303 | gdbarch_num_regs (gdbarch) | |
2304 | + MIPS_SP_REGNUM); | |
29639122 JB |
2305 | else |
2306 | sp = 0; | |
eec63939 | 2307 | |
29639122 JB |
2308 | if (limit_pc > start_pc + 200) |
2309 | limit_pc = start_pc + 200; | |
eec63939 | 2310 | |
95ac2dcf | 2311 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
2312 | { |
2313 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
2314 | the immediate offset extension from it in mips16_get_imm. */ | |
2315 | prev_inst = inst; | |
eec63939 | 2316 | |
025bb325 | 2317 | /* Fetch and decode the instruction. */ |
4cc0665f MR |
2318 | inst = (unsigned short) mips_fetch_instruction (gdbarch, ISA_MIPS16, |
2319 | cur_pc, NULL); | |
eec63939 | 2320 | |
29639122 JB |
2321 | /* Normally we ignore extend instructions. However, if it is |
2322 | not followed by a valid prologue instruction, then this | |
2323 | instruction is not part of the prologue either. We must | |
2324 | remember in this case to adjust the end_prologue_addr back | |
2325 | over the extend. */ | |
2326 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
2327 | { | |
95ac2dcf | 2328 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
2329 | continue; |
2330 | } | |
eec63939 | 2331 | |
29639122 JB |
2332 | prev_extend_bytes = extend_bytes; |
2333 | extend_bytes = 0; | |
eec63939 | 2334 | |
29639122 JB |
2335 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
2336 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2337 | { | |
2338 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
025bb325 | 2339 | if (offset < 0) /* Negative stack adjustment? */ |
29639122 JB |
2340 | frame_offset -= offset; |
2341 | else | |
2342 | /* Exit loop if a positive stack adjustment is found, which | |
2343 | usually means that the stack cleanup code in the function | |
2344 | epilogue is reached. */ | |
2345 | break; | |
2346 | } | |
2347 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2348 | { | |
2349 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4cc0665f | 2350 | reg = mips_reg3_to_reg[(inst & 0x700) >> 8]; |
74ed0bb4 | 2351 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2352 | } |
2353 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2354 | { | |
2355 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2356 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2357 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2358 | } |
2359 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2360 | { | |
2361 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 2362 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2363 | } |
2364 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2365 | { | |
2366 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 2367 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2368 | } |
2369 | else if (inst == 0x673d) /* move $s1, $sp */ | |
2370 | { | |
2371 | frame_addr = sp; | |
2372 | frame_reg = 17; | |
2373 | } | |
2374 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2375 | { | |
2376 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2377 | frame_addr = sp + offset; | |
2378 | frame_reg = 17; | |
2379 | frame_adjust = offset; | |
2380 | } | |
2381 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2382 | { | |
2383 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
4cc0665f | 2384 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2385 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2386 | } |
2387 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2388 | { | |
2389 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2390 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2391 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2392 | } |
2393 | else if ((inst & 0xf81f) == 0xe809 | |
2394 | && (inst & 0x700) != 0x700) /* entry */ | |
025bb325 | 2395 | entry_inst = inst; /* Save for later processing. */ |
2207132d MR |
2396 | else if ((inst & 0xff80) == 0x6480) /* save */ |
2397 | { | |
025bb325 | 2398 | save_inst = inst; /* Save for later processing. */ |
2207132d MR |
2399 | if (prev_extend_bytes) /* extend */ |
2400 | save_inst |= prev_inst << 16; | |
2401 | } | |
29639122 | 2402 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
95ac2dcf | 2403 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
2404 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
2405 | { | |
2406 | /* This instruction is part of the prologue, but we don't | |
2407 | need to do anything special to handle it. */ | |
2408 | } | |
2409 | else | |
2410 | { | |
2411 | /* This instruction is not an instruction typically found | |
2412 | in a prologue, so we must have reached the end of the | |
2413 | prologue. */ | |
2414 | if (end_prologue_addr == 0) | |
2415 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
2416 | } | |
2417 | } | |
eec63939 | 2418 | |
29639122 JB |
2419 | /* The entry instruction is typically the first instruction in a function, |
2420 | and it stores registers at offsets relative to the value of the old SP | |
2421 | (before the prologue). But the value of the sp parameter to this | |
2422 | function is the new SP (after the prologue has been executed). So we | |
2423 | can't calculate those offsets until we've seen the entire prologue, | |
025bb325 | 2424 | and can calculate what the old SP must have been. */ |
29639122 JB |
2425 | if (entry_inst != 0) |
2426 | { | |
2427 | int areg_count = (entry_inst >> 8) & 7; | |
2428 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 2429 | |
29639122 JB |
2430 | /* The entry instruction always subtracts 32 from the SP. */ |
2431 | frame_offset += 32; | |
2432 | ||
2433 | /* Now we can calculate what the SP must have been at the | |
2434 | start of the function prologue. */ | |
2435 | sp += frame_offset; | |
2436 | ||
2437 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
2438 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2439 | { | |
74ed0bb4 | 2440 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2441 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
2442 | } |
2443 | ||
2444 | /* Check if the ra register was pushed on the stack. */ | |
2445 | offset = -4; | |
2446 | if (entry_inst & 0x20) | |
2447 | { | |
74ed0bb4 | 2448 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 2449 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2450 | } |
2451 | ||
2452 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
2453 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2454 | { | |
74ed0bb4 | 2455 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2456 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2457 | } |
2458 | } | |
2459 | ||
2207132d MR |
2460 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
2461 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
2462 | size of the frame is specified as an immediate field of instruction | |
2463 | and an extended variation exists which lets additional registers and | |
2464 | frame space to be specified. The instruction always treats registers | |
2465 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
2466 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
2467 | { | |
2468 | static int args_table[16] = { | |
2469 | 0, 0, 0, 0, 1, 1, 1, 1, | |
2470 | 2, 2, 2, 0, 3, 3, 4, -1, | |
2471 | }; | |
2472 | static int astatic_table[16] = { | |
2473 | 0, 1, 2, 3, 0, 1, 2, 3, | |
2474 | 0, 1, 2, 4, 0, 1, 0, -1, | |
2475 | }; | |
2476 | int aregs = (save_inst >> 16) & 0xf; | |
2477 | int xsregs = (save_inst >> 24) & 0x7; | |
2478 | int args = args_table[aregs]; | |
2479 | int astatic = astatic_table[aregs]; | |
2480 | long frame_size; | |
2481 | ||
2482 | if (args < 0) | |
2483 | { | |
2484 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
2485 | args = 0; | |
2486 | } | |
2487 | if (astatic < 0) | |
2488 | { | |
2489 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
2490 | astatic = 0; | |
2491 | } | |
2492 | ||
2493 | /* For standard SAVE the frame size of 0 means 128. */ | |
2494 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
2495 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
2496 | frame_size = 16; | |
2497 | frame_size *= 8; | |
2498 | frame_offset += frame_size; | |
2499 | ||
2500 | /* Now we can calculate what the SP must have been at the | |
2501 | start of the function prologue. */ | |
2502 | sp += frame_offset; | |
2503 | ||
2504 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
2505 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
2506 | { | |
74ed0bb4 | 2507 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2508 | offset += mips_abi_regsize (gdbarch); |
2509 | } | |
2510 | ||
2511 | offset = -4; | |
2512 | ||
2513 | /* Check if the RA register was pushed on the stack. */ | |
2514 | if (save_inst & 0x40) | |
2515 | { | |
74ed0bb4 | 2516 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
2517 | offset -= mips_abi_regsize (gdbarch); |
2518 | } | |
2519 | ||
2520 | /* Check if the S8 register was pushed on the stack. */ | |
2521 | if (xsregs > 6) | |
2522 | { | |
74ed0bb4 | 2523 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
2524 | offset -= mips_abi_regsize (gdbarch); |
2525 | xsregs--; | |
2526 | } | |
2527 | /* Check if S2-S7 were pushed on the stack. */ | |
2528 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
2529 | { | |
74ed0bb4 | 2530 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2531 | offset -= mips_abi_regsize (gdbarch); |
2532 | } | |
2533 | ||
2534 | /* Check if the S1 register was pushed on the stack. */ | |
2535 | if (save_inst & 0x10) | |
2536 | { | |
74ed0bb4 | 2537 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
2538 | offset -= mips_abi_regsize (gdbarch); |
2539 | } | |
2540 | /* Check if the S0 register was pushed on the stack. */ | |
2541 | if (save_inst & 0x20) | |
2542 | { | |
74ed0bb4 | 2543 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
2544 | offset -= mips_abi_regsize (gdbarch); |
2545 | } | |
2546 | ||
4cc0665f MR |
2547 | /* Check if A0-A3 were pushed on the stack. */ |
2548 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
2549 | { | |
2550 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); | |
2551 | offset -= mips_abi_regsize (gdbarch); | |
2552 | } | |
2553 | } | |
2554 | ||
2555 | if (this_cache != NULL) | |
2556 | { | |
2557 | this_cache->base = | |
2558 | (get_frame_register_signed (this_frame, | |
2559 | gdbarch_num_regs (gdbarch) + frame_reg) | |
2560 | + frame_offset - frame_adjust); | |
2561 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
2562 | be able to get rid of the assignment below, evetually. But it's | |
2563 | still needed for now. */ | |
2564 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
2565 | + mips_regnum (gdbarch)->pc] | |
2566 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
2567 | } | |
2568 | ||
2569 | /* If we didn't reach the end of the prologue when scanning the function | |
2570 | instructions, then set end_prologue_addr to the address of the | |
2571 | instruction immediately after the last one we scanned. */ | |
2572 | if (end_prologue_addr == 0) | |
2573 | end_prologue_addr = cur_pc; | |
2574 | ||
2575 | return end_prologue_addr; | |
2576 | } | |
2577 | ||
2578 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). | |
2579 | Procedures that use the 32-bit instruction set are handled by the | |
2580 | mips_insn32 unwinder. */ | |
2581 | ||
2582 | static struct mips_frame_cache * | |
2583 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2584 | { | |
2585 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2586 | struct mips_frame_cache *cache; | |
2587 | ||
2588 | if ((*this_cache) != NULL) | |
2589 | return (*this_cache); | |
2590 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); | |
2591 | (*this_cache) = cache; | |
2592 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2593 | ||
2594 | /* Analyze the function prologue. */ | |
2595 | { | |
2596 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); | |
2597 | CORE_ADDR start_addr; | |
2598 | ||
2599 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
2600 | if (start_addr == 0) | |
2601 | start_addr = heuristic_proc_start (gdbarch, pc); | |
2602 | /* We can't analyze the prologue if we couldn't find the begining | |
2603 | of the function. */ | |
2604 | if (start_addr == 0) | |
2605 | return cache; | |
2606 | ||
2607 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); | |
2608 | } | |
2609 | ||
2610 | /* gdbarch_sp_regnum contains the value and not the address. */ | |
2611 | trad_frame_set_value (cache->saved_regs, | |
2612 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, | |
2613 | cache->base); | |
2614 | ||
2615 | return (*this_cache); | |
2616 | } | |
2617 | ||
2618 | static void | |
2619 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, | |
2620 | struct frame_id *this_id) | |
2621 | { | |
2622 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2623 | this_cache); | |
2624 | /* This marks the outermost frame. */ | |
2625 | if (info->base == 0) | |
2626 | return; | |
2627 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); | |
2628 | } | |
2629 | ||
2630 | static struct value * | |
2631 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
2632 | void **this_cache, int regnum) | |
2633 | { | |
2634 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2635 | this_cache); | |
2636 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
2637 | } | |
2638 | ||
2639 | static int | |
2640 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
2641 | struct frame_info *this_frame, void **this_cache) | |
2642 | { | |
2643 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2644 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2645 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2646 | return 1; | |
2647 | return 0; | |
2648 | } | |
2649 | ||
2650 | static const struct frame_unwind mips_insn16_frame_unwind = | |
2651 | { | |
2652 | NORMAL_FRAME, | |
2653 | default_frame_unwind_stop_reason, | |
2654 | mips_insn16_frame_this_id, | |
2655 | mips_insn16_frame_prev_register, | |
2656 | NULL, | |
2657 | mips_insn16_frame_sniffer | |
2658 | }; | |
2659 | ||
2660 | static CORE_ADDR | |
2661 | mips_insn16_frame_base_address (struct frame_info *this_frame, | |
2662 | void **this_cache) | |
2663 | { | |
2664 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2665 | this_cache); | |
2666 | return info->base; | |
2667 | } | |
2668 | ||
2669 | static const struct frame_base mips_insn16_frame_base = | |
2670 | { | |
2671 | &mips_insn16_frame_unwind, | |
2672 | mips_insn16_frame_base_address, | |
2673 | mips_insn16_frame_base_address, | |
2674 | mips_insn16_frame_base_address | |
2675 | }; | |
2676 | ||
2677 | static const struct frame_base * | |
2678 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) | |
2679 | { | |
2680 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2681 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2682 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2683 | return &mips_insn16_frame_base; | |
2684 | else | |
2685 | return NULL; | |
2686 | } | |
2687 | ||
2688 | /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped | |
2689 | to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are | |
2690 | interpreted directly, and then multiplied by 4. */ | |
2691 | ||
2692 | static int | |
2693 | micromips_decode_imm9 (int imm) | |
2694 | { | |
2695 | imm = (imm ^ 0x100) - 0x100; | |
2696 | if (imm > -3 && imm < 2) | |
2697 | imm ^= 0x100; | |
2698 | return imm << 2; | |
2699 | } | |
2700 | ||
2701 | /* Analyze the function prologue from START_PC to LIMIT_PC. Return | |
2702 | the address of the first instruction past the prologue. */ | |
2703 | ||
2704 | static CORE_ADDR | |
2705 | micromips_scan_prologue (struct gdbarch *gdbarch, | |
2706 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
2707 | struct frame_info *this_frame, | |
2708 | struct mips_frame_cache *this_cache) | |
2709 | { | |
2710 | CORE_ADDR end_prologue_addr = 0; | |
2711 | int prev_non_prologue_insn = 0; | |
2712 | int frame_reg = MIPS_SP_REGNUM; | |
2713 | int this_non_prologue_insn; | |
2714 | int non_prologue_insns = 0; | |
2715 | long frame_offset = 0; /* Size of stack frame. */ | |
2716 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
2717 | CORE_ADDR frame_addr = 0; /* Value of $30, used as frame pointer. */ | |
2718 | CORE_ADDR prev_pc; | |
2719 | CORE_ADDR cur_pc; | |
2720 | ULONGEST insn; /* current instruction */ | |
2721 | CORE_ADDR sp; | |
2722 | long offset; | |
2723 | long sp_adj; | |
2724 | long v1_off = 0; /* The assumption is LUI will replace it. */ | |
2725 | int reglist; | |
2726 | int breg; | |
2727 | int dreg; | |
2728 | int sreg; | |
2729 | int treg; | |
2730 | int loc; | |
2731 | int op; | |
2732 | int s; | |
2733 | int i; | |
2734 | ||
2735 | /* Can be called when there's no process, and hence when there's no | |
2736 | THIS_FRAME. */ | |
2737 | if (this_frame != NULL) | |
2738 | sp = get_frame_register_signed (this_frame, | |
2739 | gdbarch_num_regs (gdbarch) | |
2740 | + MIPS_SP_REGNUM); | |
2741 | else | |
2742 | sp = 0; | |
2743 | ||
2744 | if (limit_pc > start_pc + 200) | |
2745 | limit_pc = start_pc + 200; | |
2746 | prev_pc = start_pc; | |
2747 | ||
2748 | /* Permit at most one non-prologue non-control-transfer instruction | |
2749 | in the middle which may have been reordered by the compiler for | |
2750 | optimisation. */ | |
2751 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += loc) | |
2752 | { | |
2753 | this_non_prologue_insn = 0; | |
2754 | sp_adj = 0; | |
2755 | loc = 0; | |
2756 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc, NULL); | |
2757 | loc += MIPS_INSN16_SIZE; | |
2758 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
2759 | { | |
2760 | /* 48-bit instructions. */ | |
2761 | case 3 * MIPS_INSN16_SIZE: | |
2762 | /* No prologue instructions in this category. */ | |
2763 | this_non_prologue_insn = 1; | |
2764 | loc += 2 * MIPS_INSN16_SIZE; | |
2765 | break; | |
2766 | ||
2767 | /* 32-bit instructions. */ | |
2768 | case 2 * MIPS_INSN16_SIZE: | |
2769 | insn <<= 16; | |
2770 | insn |= mips_fetch_instruction (gdbarch, | |
2771 | ISA_MICROMIPS, cur_pc + loc, NULL); | |
2772 | loc += MIPS_INSN16_SIZE; | |
2773 | switch (micromips_op (insn >> 16)) | |
2774 | { | |
2775 | /* Record $sp/$fp adjustment. */ | |
2776 | /* Discard (D)ADDU $gp,$jp used for PIC code. */ | |
2777 | case 0x0: /* POOL32A: bits 000000 */ | |
2778 | case 0x16: /* POOL32S: bits 010110 */ | |
2779 | op = b0s11_op (insn); | |
2780 | sreg = b0s5_reg (insn >> 16); | |
2781 | treg = b5s5_reg (insn >> 16); | |
2782 | dreg = b11s5_reg (insn); | |
2783 | if (op == 0x1d0 | |
2784 | /* SUBU: bits 000000 00111010000 */ | |
2785 | /* DSUBU: bits 010110 00111010000 */ | |
2786 | && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM | |
2787 | && treg == 3) | |
2788 | /* (D)SUBU $sp, $v1 */ | |
2789 | sp_adj = v1_off; | |
2790 | else if (op != 0x150 | |
2791 | /* ADDU: bits 000000 00101010000 */ | |
2792 | /* DADDU: bits 010110 00101010000 */ | |
2793 | || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM) | |
2794 | this_non_prologue_insn = 1; | |
2795 | break; | |
2796 | ||
2797 | case 0x8: /* POOL32B: bits 001000 */ | |
2798 | op = b12s4_op (insn); | |
2799 | breg = b0s5_reg (insn >> 16); | |
2800 | reglist = sreg = b5s5_reg (insn >> 16); | |
2801 | offset = (b0s12_imm (insn) ^ 0x800) - 0x800; | |
2802 | if ((op == 0x9 || op == 0xc) | |
2803 | /* SWP: bits 001000 1001 */ | |
2804 | /* SDP: bits 001000 1100 */ | |
2805 | && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM) | |
2806 | /* S[DW]P reg,offset($sp) */ | |
2807 | { | |
2808 | s = 4 << ((b12s4_op (insn) & 0x4) == 0x4); | |
2809 | set_reg_offset (gdbarch, this_cache, | |
2810 | sreg, sp + offset); | |
2811 | set_reg_offset (gdbarch, this_cache, | |
2812 | sreg + 1, sp + offset + s); | |
2813 | } | |
2814 | else if ((op == 0xd || op == 0xf) | |
2815 | /* SWM: bits 001000 1101 */ | |
2816 | /* SDM: bits 001000 1111 */ | |
2817 | && breg == MIPS_SP_REGNUM | |
2818 | /* SWM reglist,offset($sp) */ | |
2819 | && ((reglist >= 1 && reglist <= 9) | |
2820 | || (reglist >= 16 && reglist <= 25))) | |
2821 | { | |
2822 | int sreglist = min(reglist & 0xf, 8); | |
2823 | ||
2824 | s = 4 << ((b12s4_op (insn) & 0x2) == 0x2); | |
2825 | for (i = 0; i < sreglist; i++) | |
2826 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + s * i); | |
2827 | if ((reglist & 0xf) > 8) | |
2828 | set_reg_offset (gdbarch, this_cache, 30, sp + s * i++); | |
2829 | if ((reglist & 0x10) == 0x10) | |
2830 | set_reg_offset (gdbarch, this_cache, | |
2831 | MIPS_RA_REGNUM, sp + s * i++); | |
2832 | } | |
2833 | else | |
2834 | this_non_prologue_insn = 1; | |
2835 | break; | |
2836 | ||
2837 | /* Record $sp/$fp adjustment. */ | |
2838 | /* Discard (D)ADDIU $gp used for PIC code. */ | |
2839 | case 0xc: /* ADDIU: bits 001100 */ | |
2840 | case 0x17: /* DADDIU: bits 010111 */ | |
2841 | sreg = b0s5_reg (insn >> 16); | |
2842 | dreg = b5s5_reg (insn >> 16); | |
2843 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
2844 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM) | |
2845 | /* (D)ADDIU $sp, imm */ | |
2846 | sp_adj = offset; | |
2847 | else if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
2848 | /* (D)ADDIU $fp, $sp, imm */ | |
2849 | { | |
2850 | frame_addr = sp + offset; | |
2851 | frame_adjust = offset; | |
2852 | frame_reg = 30; | |
2853 | } | |
2854 | else if (sreg != 28 || dreg != 28) | |
2855 | /* (D)ADDIU $gp, imm */ | |
2856 | this_non_prologue_insn = 1; | |
2857 | break; | |
2858 | ||
2859 | /* LUI $v1 is used for larger $sp adjustments. */ | |
2860 | /* Discard LUI $gp is used for PIC code. */ | |
2861 | case 0x10: /* POOL32I: bits 010000 */ | |
2862 | if (b5s5_op (insn >> 16) == 0xd | |
2863 | /* LUI: bits 010000 001101 */ | |
2864 | && b0s5_reg (insn >> 16) == 3) | |
2865 | /* LUI $v1, imm */ | |
2866 | v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000; | |
2867 | else if (b5s5_op (insn >> 16) != 0xd | |
2868 | /* LUI: bits 010000 001101 */ | |
2869 | || b0s5_reg (insn >> 16) != 28) | |
2870 | /* LUI $gp, imm */ | |
2871 | this_non_prologue_insn = 1; | |
2872 | break; | |
2873 | ||
2874 | /* ORI $v1 is used for larger $sp adjustments. */ | |
2875 | case 0x14: /* ORI: bits 010100 */ | |
2876 | sreg = b0s5_reg (insn >> 16); | |
2877 | dreg = b5s5_reg (insn >> 16); | |
2878 | if (sreg == 3 && dreg == 3) | |
2879 | /* ORI $v1, imm */ | |
2880 | v1_off |= b0s16_imm (insn); | |
2881 | else | |
2882 | this_non_prologue_insn = 1; | |
2883 | break; | |
2884 | ||
2885 | case 0x26: /* SWC1: bits 100110 */ | |
2886 | case 0x2e: /* SDC1: bits 101110 */ | |
2887 | breg = b0s5_reg (insn >> 16); | |
2888 | if (breg != MIPS_SP_REGNUM) | |
2889 | /* S[DW]C1 reg,offset($sp) */ | |
2890 | this_non_prologue_insn = 1; | |
2891 | break; | |
2892 | ||
2893 | case 0x36: /* SD: bits 110110 */ | |
2894 | case 0x3e: /* SW: bits 111110 */ | |
2895 | breg = b0s5_reg (insn >> 16); | |
2896 | sreg = b5s5_reg (insn >> 16); | |
2897 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
2898 | if (breg == MIPS_SP_REGNUM) | |
2899 | /* S[DW] reg,offset($sp) */ | |
2900 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
2901 | else | |
2902 | this_non_prologue_insn = 1; | |
2903 | break; | |
2904 | ||
2905 | default: | |
2906 | this_non_prologue_insn = 1; | |
2907 | break; | |
2908 | } | |
2909 | break; | |
2910 | ||
2911 | /* 16-bit instructions. */ | |
2912 | case MIPS_INSN16_SIZE: | |
2913 | switch (micromips_op (insn)) | |
2914 | { | |
2915 | case 0x3: /* MOVE: bits 000011 */ | |
2916 | sreg = b0s5_reg (insn); | |
2917 | dreg = b5s5_reg (insn); | |
2918 | if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
2919 | /* MOVE $fp, $sp */ | |
2920 | { | |
2921 | frame_addr = sp; | |
2922 | frame_reg = 30; | |
2923 | } | |
2924 | else if ((sreg & 0x1c) != 0x4) | |
2925 | /* MOVE reg, $a0-$a3 */ | |
2926 | this_non_prologue_insn = 1; | |
2927 | break; | |
2928 | ||
2929 | case 0x11: /* POOL16C: bits 010001 */ | |
2930 | if (b6s4_op (insn) == 0x5) | |
2931 | /* SWM: bits 010001 0101 */ | |
2932 | { | |
2933 | offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20; | |
2934 | reglist = b4s2_regl (insn); | |
2935 | for (i = 0; i <= reglist; i++) | |
2936 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i); | |
2937 | set_reg_offset (gdbarch, this_cache, | |
2938 | MIPS_RA_REGNUM, sp + 4 * i++); | |
2939 | } | |
2940 | else | |
2941 | this_non_prologue_insn = 1; | |
2942 | break; | |
2943 | ||
2944 | case 0x13: /* POOL16D: bits 010011 */ | |
2945 | if ((insn & 0x1) == 0x1) | |
2946 | /* ADDIUSP: bits 010011 1 */ | |
2947 | sp_adj = micromips_decode_imm9 (b1s9_imm (insn)); | |
2948 | else if (b5s5_reg (insn) == MIPS_SP_REGNUM) | |
2949 | /* ADDIUS5: bits 010011 0 */ | |
2950 | /* ADDIUS5 $sp, imm */ | |
2951 | sp_adj = (b1s4_imm (insn) ^ 8) - 8; | |
2952 | else | |
2953 | this_non_prologue_insn = 1; | |
2954 | break; | |
2955 | ||
2956 | case 0x32: /* SWSP: bits 110010 */ | |
2957 | offset = b0s5_imm (insn) << 2; | |
2958 | sreg = b5s5_reg (insn); | |
2959 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
2960 | break; | |
2961 | ||
2962 | default: | |
2963 | this_non_prologue_insn = 1; | |
2964 | break; | |
2965 | } | |
2966 | break; | |
2967 | } | |
2968 | if (sp_adj < 0) | |
2969 | frame_offset -= sp_adj; | |
2970 | ||
2971 | non_prologue_insns += this_non_prologue_insn; | |
2972 | /* Enough non-prologue insns seen or positive stack adjustment? */ | |
2973 | if (end_prologue_addr == 0 && (non_prologue_insns > 1 || sp_adj > 0)) | |
2207132d | 2974 | { |
4cc0665f MR |
2975 | end_prologue_addr = prev_non_prologue_insn ? prev_pc : cur_pc; |
2976 | break; | |
2207132d | 2977 | } |
4cc0665f MR |
2978 | prev_non_prologue_insn = this_non_prologue_insn; |
2979 | prev_pc = cur_pc; | |
2207132d MR |
2980 | } |
2981 | ||
29639122 JB |
2982 | if (this_cache != NULL) |
2983 | { | |
2984 | this_cache->base = | |
4cc0665f | 2985 | (get_frame_register_signed (this_frame, |
b8a22b94 | 2986 | gdbarch_num_regs (gdbarch) + frame_reg) |
4cc0665f | 2987 | + frame_offset - frame_adjust); |
29639122 | 2988 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should |
4cc0665f MR |
2989 | be able to get rid of the assignment below, evetually. But it's |
2990 | still needed for now. */ | |
72a155b4 UW |
2991 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
2992 | + mips_regnum (gdbarch)->pc] | |
4cc0665f | 2993 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; |
29639122 JB |
2994 | } |
2995 | ||
2996 | /* If we didn't reach the end of the prologue when scanning the function | |
2997 | instructions, then set end_prologue_addr to the address of the | |
4cc0665f MR |
2998 | instruction immediately after the last one we scanned. Unless the |
2999 | last one looked like a non-prologue instruction (and we looked ahead), | |
3000 | in which case use its address instead. */ | |
29639122 | 3001 | if (end_prologue_addr == 0) |
4cc0665f | 3002 | end_prologue_addr = prev_non_prologue_insn ? prev_pc : cur_pc; |
29639122 JB |
3003 | |
3004 | return end_prologue_addr; | |
eec63939 AC |
3005 | } |
3006 | ||
4cc0665f | 3007 | /* Heuristic unwinder for procedures using microMIPS instructions. |
29639122 | 3008 | Procedures that use the 32-bit instruction set are handled by the |
4cc0665f | 3009 | mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */ |
29639122 JB |
3010 | |
3011 | static struct mips_frame_cache * | |
4cc0665f | 3012 | mips_micro_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 3013 | { |
e17a4113 | 3014 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3015 | struct mips_frame_cache *cache; |
eec63939 AC |
3016 | |
3017 | if ((*this_cache) != NULL) | |
3018 | return (*this_cache); | |
4cc0665f | 3019 | |
29639122 JB |
3020 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3021 | (*this_cache) = cache; | |
b8a22b94 | 3022 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 3023 | |
29639122 JB |
3024 | /* Analyze the function prologue. */ |
3025 | { | |
b8a22b94 | 3026 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3027 | CORE_ADDR start_addr; |
eec63939 | 3028 | |
29639122 JB |
3029 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3030 | if (start_addr == 0) | |
4cc0665f | 3031 | start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); |
29639122 JB |
3032 | /* We can't analyze the prologue if we couldn't find the begining |
3033 | of the function. */ | |
3034 | if (start_addr == 0) | |
3035 | return cache; | |
eec63939 | 3036 | |
4cc0665f | 3037 | micromips_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 | 3038 | } |
4cc0665f | 3039 | |
3e8c568d | 3040 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 | 3041 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 3042 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
72a155b4 | 3043 | cache->base); |
eec63939 | 3044 | |
29639122 | 3045 | return (*this_cache); |
eec63939 AC |
3046 | } |
3047 | ||
3048 | static void | |
4cc0665f MR |
3049 | mips_micro_frame_this_id (struct frame_info *this_frame, void **this_cache, |
3050 | struct frame_id *this_id) | |
eec63939 | 3051 | { |
4cc0665f MR |
3052 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3053 | this_cache); | |
21327321 DJ |
3054 | /* This marks the outermost frame. */ |
3055 | if (info->base == 0) | |
3056 | return; | |
b8a22b94 | 3057 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
3058 | } |
3059 | ||
b8a22b94 | 3060 | static struct value * |
4cc0665f MR |
3061 | mips_micro_frame_prev_register (struct frame_info *this_frame, |
3062 | void **this_cache, int regnum) | |
eec63939 | 3063 | { |
4cc0665f MR |
3064 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3065 | this_cache); | |
b8a22b94 DJ |
3066 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3067 | } | |
3068 | ||
3069 | static int | |
4cc0665f MR |
3070 | mips_micro_frame_sniffer (const struct frame_unwind *self, |
3071 | struct frame_info *this_frame, void **this_cache) | |
b8a22b94 | 3072 | { |
4cc0665f | 3073 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3074 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3075 | |
3076 | if (mips_pc_is_micromips (gdbarch, pc)) | |
b8a22b94 DJ |
3077 | return 1; |
3078 | return 0; | |
eec63939 AC |
3079 | } |
3080 | ||
4cc0665f | 3081 | static const struct frame_unwind mips_micro_frame_unwind = |
eec63939 AC |
3082 | { |
3083 | NORMAL_FRAME, | |
8fbca658 | 3084 | default_frame_unwind_stop_reason, |
4cc0665f MR |
3085 | mips_micro_frame_this_id, |
3086 | mips_micro_frame_prev_register, | |
b8a22b94 | 3087 | NULL, |
4cc0665f | 3088 | mips_micro_frame_sniffer |
eec63939 AC |
3089 | }; |
3090 | ||
eec63939 | 3091 | static CORE_ADDR |
4cc0665f MR |
3092 | mips_micro_frame_base_address (struct frame_info *this_frame, |
3093 | void **this_cache) | |
eec63939 | 3094 | { |
4cc0665f MR |
3095 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3096 | this_cache); | |
29639122 | 3097 | return info->base; |
eec63939 AC |
3098 | } |
3099 | ||
4cc0665f | 3100 | static const struct frame_base mips_micro_frame_base = |
eec63939 | 3101 | { |
4cc0665f MR |
3102 | &mips_micro_frame_unwind, |
3103 | mips_micro_frame_base_address, | |
3104 | mips_micro_frame_base_address, | |
3105 | mips_micro_frame_base_address | |
eec63939 AC |
3106 | }; |
3107 | ||
3108 | static const struct frame_base * | |
4cc0665f | 3109 | mips_micro_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 3110 | { |
4cc0665f | 3111 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3112 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3113 | |
3114 | if (mips_pc_is_micromips (gdbarch, pc)) | |
3115 | return &mips_micro_frame_base; | |
eec63939 AC |
3116 | else |
3117 | return NULL; | |
edfae063 AC |
3118 | } |
3119 | ||
29639122 JB |
3120 | /* Mark all the registers as unset in the saved_regs array |
3121 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
3122 | ||
74ed0bb4 MD |
3123 | static void |
3124 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 3125 | { |
29639122 JB |
3126 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
3127 | return; | |
3128 | ||
3129 | { | |
74ed0bb4 | 3130 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 3131 | int i; |
64159455 | 3132 | |
29639122 JB |
3133 | for (i = 0; i < num_regs; i++) |
3134 | { | |
3135 | this_cache->saved_regs[i].addr = -1; | |
3136 | } | |
3137 | } | |
c906108c SS |
3138 | } |
3139 | ||
025bb325 | 3140 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
29639122 JB |
3141 | the associated FRAME_CACHE if not null. |
3142 | Return the address of the first instruction past the prologue. */ | |
c906108c | 3143 | |
875e1767 | 3144 | static CORE_ADDR |
e17a4113 UW |
3145 | mips32_scan_prologue (struct gdbarch *gdbarch, |
3146 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 3147 | struct frame_info *this_frame, |
29639122 | 3148 | struct mips_frame_cache *this_cache) |
c906108c | 3149 | { |
29639122 | 3150 | CORE_ADDR cur_pc; |
025bb325 MS |
3151 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for |
3152 | frame-pointer. */ | |
29639122 JB |
3153 | CORE_ADDR sp; |
3154 | long frame_offset; | |
3155 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 3156 | |
29639122 JB |
3157 | CORE_ADDR end_prologue_addr = 0; |
3158 | int seen_sp_adjust = 0; | |
3159 | int load_immediate_bytes = 0; | |
db5f024e | 3160 | int in_delay_slot = 0; |
7d1e6fb8 | 3161 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 3162 | |
29639122 | 3163 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
3164 | THIS_FRAME. */ |
3165 | if (this_frame != NULL) | |
3166 | sp = get_frame_register_signed (this_frame, | |
3167 | gdbarch_num_regs (gdbarch) | |
3168 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 3169 | else |
29639122 | 3170 | sp = 0; |
9022177c | 3171 | |
29639122 JB |
3172 | if (limit_pc > start_pc + 200) |
3173 | limit_pc = start_pc + 200; | |
9022177c | 3174 | |
29639122 | 3175 | restart: |
9022177c | 3176 | |
29639122 | 3177 | frame_offset = 0; |
95ac2dcf | 3178 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 3179 | { |
29639122 JB |
3180 | unsigned long inst, high_word, low_word; |
3181 | int reg; | |
9022177c | 3182 | |
025bb325 | 3183 | /* Fetch the instruction. */ |
4cc0665f MR |
3184 | inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS, |
3185 | cur_pc, NULL); | |
9022177c | 3186 | |
29639122 JB |
3187 | /* Save some code by pre-extracting some useful fields. */ |
3188 | high_word = (inst >> 16) & 0xffff; | |
3189 | low_word = inst & 0xffff; | |
3190 | reg = high_word & 0x1f; | |
fe29b929 | 3191 | |
025bb325 | 3192 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
29639122 JB |
3193 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
3194 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
3195 | { | |
025bb325 | 3196 | if (low_word & 0x8000) /* Negative stack adjustment? */ |
29639122 JB |
3197 | frame_offset += 0x10000 - low_word; |
3198 | else | |
3199 | /* Exit loop if a positive stack adjustment is found, which | |
3200 | usually means that the stack cleanup code in the function | |
3201 | epilogue is reached. */ | |
3202 | break; | |
3203 | seen_sp_adjust = 1; | |
3204 | } | |
7d1e6fb8 KB |
3205 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
3206 | && !regsize_is_64_bits) | |
29639122 | 3207 | { |
74ed0bb4 | 3208 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 | 3209 | } |
7d1e6fb8 KB |
3210 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
3211 | && regsize_is_64_bits) | |
29639122 JB |
3212 | { |
3213 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
74ed0bb4 | 3214 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 JB |
3215 | } |
3216 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
3217 | { | |
3218 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
3219 | if ((long) low_word != frame_offset) | |
3220 | frame_addr = sp + low_word; | |
b8a22b94 | 3221 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3222 | { |
3223 | unsigned alloca_adjust; | |
a4b8ebc8 | 3224 | |
29639122 | 3225 | frame_reg = 30; |
b8a22b94 DJ |
3226 | frame_addr = get_frame_register_signed |
3227 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 3228 | |
29639122 JB |
3229 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
3230 | if (alloca_adjust > 0) | |
3231 | { | |
025bb325 | 3232 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
3233 | an alloca or somethings similar. Fix sp to |
3234 | "pre-alloca" value, and try again. */ | |
3235 | sp += alloca_adjust; | |
3236 | /* Need to reset the status of all registers. Otherwise, | |
3237 | we will hit a guard that prevents the new address | |
3238 | for each register to be recomputed during the second | |
3239 | pass. */ | |
74ed0bb4 | 3240 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
3241 | goto restart; |
3242 | } | |
3243 | } | |
3244 | } | |
3245 | /* move $30,$sp. With different versions of gas this will be either | |
3246 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
3247 | Accept any one of these. */ | |
3248 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
3249 | { | |
3250 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 3251 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3252 | { |
3253 | unsigned alloca_adjust; | |
c906108c | 3254 | |
29639122 | 3255 | frame_reg = 30; |
b8a22b94 DJ |
3256 | frame_addr = get_frame_register_signed |
3257 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 3258 | |
29639122 JB |
3259 | alloca_adjust = (unsigned) (frame_addr - sp); |
3260 | if (alloca_adjust > 0) | |
3261 | { | |
025bb325 | 3262 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
3263 | an alloca or somethings similar. Fix sp to |
3264 | "pre-alloca" value, and try again. */ | |
3265 | sp = frame_addr; | |
3266 | /* Need to reset the status of all registers. Otherwise, | |
3267 | we will hit a guard that prevents the new address | |
3268 | for each register to be recomputed during the second | |
3269 | pass. */ | |
74ed0bb4 | 3270 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
3271 | goto restart; |
3272 | } | |
3273 | } | |
3274 | } | |
7d1e6fb8 KB |
3275 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
3276 | && !regsize_is_64_bits) | |
29639122 | 3277 | { |
74ed0bb4 | 3278 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word); |
29639122 JB |
3279 | } |
3280 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
3281 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
3282 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
3283 | || high_word == 0x3c1c /* lui $gp,n */ | |
3284 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
3285 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
3286 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
3287 | ) | |
19080931 MR |
3288 | { |
3289 | /* These instructions are part of the prologue, but we don't | |
3290 | need to do anything special to handle them. */ | |
3291 | } | |
29639122 JB |
3292 | /* The instructions below load $at or $t0 with an immediate |
3293 | value in preparation for a stack adjustment via | |
025bb325 | 3294 | subu $sp,$sp,[$at,$t0]. These instructions could also |
29639122 JB |
3295 | initialize a local variable, so we accept them only before |
3296 | a stack adjustment instruction was seen. */ | |
3297 | else if (!seen_sp_adjust | |
19080931 MR |
3298 | && (high_word == 0x3c01 /* lui $at,n */ |
3299 | || high_word == 0x3c08 /* lui $t0,n */ | |
3300 | || high_word == 0x3421 /* ori $at,$at,n */ | |
3301 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
3302 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
3303 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
3304 | )) | |
3305 | { | |
3306 | if (end_prologue_addr == 0) | |
3307 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ | |
3308 | } | |
29639122 | 3309 | else |
19080931 MR |
3310 | { |
3311 | /* This instruction is not an instruction typically found | |
3312 | in a prologue, so we must have reached the end of the | |
3313 | prologue. */ | |
3314 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
3315 | loop now? Why would we need to continue scanning the function | |
3316 | instructions? */ | |
3317 | if (end_prologue_addr == 0) | |
3318 | end_prologue_addr = cur_pc; | |
3319 | ||
3320 | /* Check for branches and jumps. For now, only jump to | |
3321 | register are caught (i.e. returns). */ | |
3322 | if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8) | |
3323 | in_delay_slot = 1; | |
3324 | } | |
db5f024e DJ |
3325 | |
3326 | /* If the previous instruction was a jump, we must have reached | |
3327 | the end of the prologue by now. Stop scanning so that we do | |
3328 | not go past the function return. */ | |
3329 | if (in_delay_slot) | |
3330 | break; | |
a4b8ebc8 | 3331 | } |
c906108c | 3332 | |
29639122 JB |
3333 | if (this_cache != NULL) |
3334 | { | |
3335 | this_cache->base = | |
b8a22b94 DJ |
3336 | (get_frame_register_signed (this_frame, |
3337 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
3338 | + frame_offset); |
3339 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
3340 | this assignment below, eventually. But it's still needed | |
3341 | for now. */ | |
72a155b4 UW |
3342 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
3343 | + mips_regnum (gdbarch)->pc] | |
3344 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 3345 | + MIPS_RA_REGNUM]; |
29639122 | 3346 | } |
c906108c | 3347 | |
29639122 JB |
3348 | /* If we didn't reach the end of the prologue when scanning the function |
3349 | instructions, then set end_prologue_addr to the address of the | |
3350 | instruction immediately after the last one we scanned. */ | |
3351 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
3352 | we may as well be careful and do our best if we have a null | |
3353 | end_prologue_addr. */ | |
3354 | if (end_prologue_addr == 0) | |
3355 | end_prologue_addr = cur_pc; | |
3356 | ||
3357 | /* In a frameless function, we might have incorrectly | |
025bb325 | 3358 | skipped some load immediate instructions. Undo the skipping |
29639122 JB |
3359 | if the load immediate was not followed by a stack adjustment. */ |
3360 | if (load_immediate_bytes && !seen_sp_adjust) | |
3361 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 3362 | |
29639122 | 3363 | return end_prologue_addr; |
c906108c SS |
3364 | } |
3365 | ||
29639122 JB |
3366 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
3367 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
3368 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
4cc0665f | 3369 | unwinder. Likewise microMIPS and the mips_micro unwinder. */ |
c906108c | 3370 | |
29639122 | 3371 | static struct mips_frame_cache * |
b8a22b94 | 3372 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 3373 | { |
e17a4113 | 3374 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3375 | struct mips_frame_cache *cache; |
c906108c | 3376 | |
29639122 JB |
3377 | if ((*this_cache) != NULL) |
3378 | return (*this_cache); | |
c5aa993b | 3379 | |
29639122 JB |
3380 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3381 | (*this_cache) = cache; | |
b8a22b94 | 3382 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 3383 | |
29639122 JB |
3384 | /* Analyze the function prologue. */ |
3385 | { | |
b8a22b94 | 3386 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3387 | CORE_ADDR start_addr; |
c906108c | 3388 | |
29639122 JB |
3389 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3390 | if (start_addr == 0) | |
e17a4113 | 3391 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
3392 | /* We can't analyze the prologue if we couldn't find the begining |
3393 | of the function. */ | |
3394 | if (start_addr == 0) | |
3395 | return cache; | |
c5aa993b | 3396 | |
e17a4113 | 3397 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
3398 | } |
3399 | ||
3e8c568d | 3400 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 3401 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 3402 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
f57d151a | 3403 | cache->base); |
c5aa993b | 3404 | |
29639122 | 3405 | return (*this_cache); |
c906108c SS |
3406 | } |
3407 | ||
29639122 | 3408 | static void |
b8a22b94 | 3409 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 3410 | struct frame_id *this_id) |
c906108c | 3411 | { |
b8a22b94 | 3412 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3413 | this_cache); |
21327321 DJ |
3414 | /* This marks the outermost frame. */ |
3415 | if (info->base == 0) | |
3416 | return; | |
b8a22b94 | 3417 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 3418 | } |
c906108c | 3419 | |
b8a22b94 DJ |
3420 | static struct value * |
3421 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
3422 | void **this_cache, int regnum) | |
29639122 | 3423 | { |
b8a22b94 | 3424 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3425 | this_cache); |
b8a22b94 DJ |
3426 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3427 | } | |
3428 | ||
3429 | static int | |
3430 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
3431 | struct frame_info *this_frame, void **this_cache) | |
3432 | { | |
3433 | CORE_ADDR pc = get_frame_pc (this_frame); | |
4cc0665f | 3434 | if (mips_pc_is_mips (pc)) |
b8a22b94 DJ |
3435 | return 1; |
3436 | return 0; | |
c906108c SS |
3437 | } |
3438 | ||
29639122 JB |
3439 | static const struct frame_unwind mips_insn32_frame_unwind = |
3440 | { | |
3441 | NORMAL_FRAME, | |
8fbca658 | 3442 | default_frame_unwind_stop_reason, |
29639122 | 3443 | mips_insn32_frame_this_id, |
b8a22b94 DJ |
3444 | mips_insn32_frame_prev_register, |
3445 | NULL, | |
3446 | mips_insn32_frame_sniffer | |
29639122 | 3447 | }; |
c906108c | 3448 | |
1c645fec | 3449 | static CORE_ADDR |
b8a22b94 | 3450 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 3451 | void **this_cache) |
c906108c | 3452 | { |
b8a22b94 | 3453 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
3454 | this_cache); |
3455 | return info->base; | |
3456 | } | |
c906108c | 3457 | |
29639122 JB |
3458 | static const struct frame_base mips_insn32_frame_base = |
3459 | { | |
3460 | &mips_insn32_frame_unwind, | |
3461 | mips_insn32_frame_base_address, | |
3462 | mips_insn32_frame_base_address, | |
3463 | mips_insn32_frame_base_address | |
3464 | }; | |
1c645fec | 3465 | |
29639122 | 3466 | static const struct frame_base * |
b8a22b94 | 3467 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 3468 | { |
b8a22b94 | 3469 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f | 3470 | if (mips_pc_is_mips (pc)) |
29639122 | 3471 | return &mips_insn32_frame_base; |
a65bbe44 | 3472 | else |
29639122 JB |
3473 | return NULL; |
3474 | } | |
a65bbe44 | 3475 | |
29639122 | 3476 | static struct trad_frame_cache * |
b8a22b94 | 3477 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
3478 | { |
3479 | CORE_ADDR pc; | |
3480 | CORE_ADDR start_addr; | |
3481 | CORE_ADDR stack_addr; | |
3482 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
3483 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3484 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 3485 | |
29639122 JB |
3486 | if ((*this_cache) != NULL) |
3487 | return (*this_cache); | |
b8a22b94 | 3488 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 3489 | (*this_cache) = this_trad_cache; |
1c645fec | 3490 | |
29639122 | 3491 | /* The return address is in the link register. */ |
3e8c568d | 3492 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 3493 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 3494 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 3495 | |
29639122 JB |
3496 | /* Frame ID, since it's a frameless / stackless function, no stack |
3497 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 3498 | pc = get_frame_pc (this_frame); |
29639122 | 3499 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
3500 | stack_addr = get_frame_register_signed (this_frame, |
3501 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 3502 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 3503 | |
29639122 JB |
3504 | /* Assume that the frame's base is the same as the |
3505 | stack-pointer. */ | |
3506 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 3507 | |
29639122 JB |
3508 | return this_trad_cache; |
3509 | } | |
c906108c | 3510 | |
29639122 | 3511 | static void |
b8a22b94 | 3512 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
3513 | struct frame_id *this_id) |
3514 | { | |
3515 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3516 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3517 | trad_frame_get_id (this_trad_cache, this_id); |
3518 | } | |
c906108c | 3519 | |
b8a22b94 DJ |
3520 | static struct value * |
3521 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
3522 | void **this_cache, int regnum) | |
29639122 JB |
3523 | { |
3524 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
3525 | = mips_stub_frame_cache (this_frame, this_cache); |
3526 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 3527 | } |
c906108c | 3528 | |
b8a22b94 DJ |
3529 | static int |
3530 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
3531 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 3532 | { |
aa6c981f | 3533 | gdb_byte dummy[4]; |
979b38e0 | 3534 | struct obj_section *s; |
b8a22b94 | 3535 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
db5f024e | 3536 | struct minimal_symbol *msym; |
979b38e0 | 3537 | |
aa6c981f | 3538 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
3539 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
3540 | return 1; | |
aa6c981f | 3541 | |
29639122 | 3542 | if (in_plt_section (pc, NULL)) |
b8a22b94 | 3543 | return 1; |
979b38e0 DJ |
3544 | |
3545 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
3546 | s = find_pc_section (pc); | |
3547 | ||
3548 | if (s != NULL | |
3549 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
3550 | ".MIPS.stubs") == 0) | |
b8a22b94 | 3551 | return 1; |
979b38e0 | 3552 | |
db5f024e DJ |
3553 | /* Calling a PIC function from a non-PIC function passes through a |
3554 | stub. The stub for foo is named ".pic.foo". */ | |
3555 | msym = lookup_minimal_symbol_by_pc (pc); | |
3556 | if (msym != NULL | |
3557 | && SYMBOL_LINKAGE_NAME (msym) != NULL | |
3558 | && strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) == 0) | |
3559 | return 1; | |
3560 | ||
b8a22b94 | 3561 | return 0; |
29639122 | 3562 | } |
c906108c | 3563 | |
b8a22b94 DJ |
3564 | static const struct frame_unwind mips_stub_frame_unwind = |
3565 | { | |
3566 | NORMAL_FRAME, | |
8fbca658 | 3567 | default_frame_unwind_stop_reason, |
b8a22b94 DJ |
3568 | mips_stub_frame_this_id, |
3569 | mips_stub_frame_prev_register, | |
3570 | NULL, | |
3571 | mips_stub_frame_sniffer | |
3572 | }; | |
3573 | ||
29639122 | 3574 | static CORE_ADDR |
b8a22b94 | 3575 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
3576 | void **this_cache) |
3577 | { | |
3578 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3579 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3580 | return trad_frame_get_this_base (this_trad_cache); |
3581 | } | |
0fce0821 | 3582 | |
29639122 JB |
3583 | static const struct frame_base mips_stub_frame_base = |
3584 | { | |
3585 | &mips_stub_frame_unwind, | |
3586 | mips_stub_frame_base_address, | |
3587 | mips_stub_frame_base_address, | |
3588 | mips_stub_frame_base_address | |
3589 | }; | |
3590 | ||
3591 | static const struct frame_base * | |
b8a22b94 | 3592 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 3593 | { |
b8a22b94 | 3594 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
3595 | return &mips_stub_frame_base; |
3596 | else | |
3597 | return NULL; | |
3598 | } | |
3599 | ||
29639122 | 3600 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 3601 | |
29639122 | 3602 | static CORE_ADDR |
24568a2c | 3603 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 3604 | { |
24568a2c | 3605 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
930bd0e0 | 3606 | |
4cc0665f MR |
3607 | if (is_compact_addr (addr)) |
3608 | addr = unmake_compact_addr (addr); | |
930bd0e0 | 3609 | |
29639122 JB |
3610 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
3611 | /* This hack is a work-around for existing boards using PMON, the | |
3612 | simulator, and any other 64-bit targets that doesn't have true | |
3613 | 64-bit addressing. On these targets, the upper 32 bits of | |
3614 | addresses are ignored by the hardware. Thus, the PC or SP are | |
3615 | likely to have been sign extended to all 1s by instruction | |
3616 | sequences that load 32-bit addresses. For example, a typical | |
3617 | piece of code that loads an address is this: | |
65596487 | 3618 | |
29639122 JB |
3619 | lui $r2, <upper 16 bits> |
3620 | ori $r2, <lower 16 bits> | |
65596487 | 3621 | |
29639122 JB |
3622 | But the lui sign-extends the value such that the upper 32 bits |
3623 | may be all 1s. The workaround is simply to mask off these | |
3624 | bits. In the future, gcc may be changed to support true 64-bit | |
3625 | addressing, and this masking will have to be disabled. */ | |
3626 | return addr &= 0xffffffffUL; | |
3627 | else | |
3628 | return addr; | |
65596487 JB |
3629 | } |
3630 | ||
3d5f6d12 DJ |
3631 | |
3632 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
3633 | instruction and ending with a SC/SCD instruction. If such a sequence | |
3634 | is found, attempt to step through it. A breakpoint is placed at the end of | |
3635 | the sequence. */ | |
3636 | ||
4cc0665f MR |
3637 | /* Instructions used during single-stepping of atomic sequences, standard |
3638 | ISA version. */ | |
3639 | #define LL_OPCODE 0x30 | |
3640 | #define LLD_OPCODE 0x34 | |
3641 | #define SC_OPCODE 0x38 | |
3642 | #define SCD_OPCODE 0x3c | |
3643 | ||
3d5f6d12 | 3644 | static int |
4cc0665f MR |
3645 | mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, |
3646 | struct address_space *aspace, CORE_ADDR pc) | |
3d5f6d12 DJ |
3647 | { |
3648 | CORE_ADDR breaks[2] = {-1, -1}; | |
3649 | CORE_ADDR loc = pc; | |
3650 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
4cc0665f | 3651 | ULONGEST insn; |
3d5f6d12 DJ |
3652 | int insn_count; |
3653 | int index; | |
3654 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
3655 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
3656 | ||
4cc0665f | 3657 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3658 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
3659 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
3660 | return 0; | |
3661 | ||
3662 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
3663 | instructions. */ | |
3664 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
3665 | { | |
3666 | int is_branch = 0; | |
3667 | loc += MIPS_INSN32_SIZE; | |
4cc0665f | 3668 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3669 | |
3670 | /* Assume that there is at most one branch in the atomic | |
3671 | sequence. If a branch is found, put a breakpoint in its | |
3672 | destination address. */ | |
3673 | switch (itype_op (insn)) | |
3674 | { | |
3675 | case 0: /* SPECIAL */ | |
3676 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
025bb325 | 3677 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3678 | break; |
3679 | case 1: /* REGIMM */ | |
a385295e MR |
3680 | is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */ |
3681 | || ((itype_rt (insn) & 0x1e) == 0 | |
3682 | && itype_rs (insn) == 0)); /* BPOSGE* */ | |
3d5f6d12 DJ |
3683 | break; |
3684 | case 2: /* J */ | |
3685 | case 3: /* JAL */ | |
025bb325 | 3686 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3687 | case 4: /* BEQ */ |
3688 | case 5: /* BNE */ | |
3689 | case 6: /* BLEZ */ | |
3690 | case 7: /* BGTZ */ | |
3691 | case 20: /* BEQL */ | |
3692 | case 21: /* BNEL */ | |
3693 | case 22: /* BLEZL */ | |
3694 | case 23: /* BGTTL */ | |
3695 | is_branch = 1; | |
3696 | break; | |
3697 | case 17: /* COP1 */ | |
a385295e MR |
3698 | is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10) |
3699 | && (itype_rt (insn) & 0x2) == 0); | |
3700 | if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ | |
3701 | break; | |
3702 | /* Fall through. */ | |
3d5f6d12 DJ |
3703 | case 18: /* COP2 */ |
3704 | case 19: /* COP3 */ | |
3705 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
3706 | break; | |
3707 | } | |
3708 | if (is_branch) | |
3709 | { | |
3710 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
3711 | if (last_breakpoint >= 1) | |
3712 | return 0; /* More than one branch found, fallback to the | |
3713 | standard single-step code. */ | |
3714 | breaks[1] = branch_bp; | |
3715 | last_breakpoint++; | |
3716 | } | |
3717 | ||
3718 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
3719 | break; | |
3720 | } | |
3721 | ||
3722 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
3723 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
3724 | return 0; | |
3725 | ||
3726 | loc += MIPS_INSN32_SIZE; | |
3727 | ||
3728 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
3729 | breaks[0] = loc; | |
3730 | ||
3731 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
025bb325 | 3732 | placed (branch instruction's destination) in the atomic sequence. */ |
3d5f6d12 DJ |
3733 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
3734 | last_breakpoint = 0; | |
3735 | ||
3736 | /* Effectively inserts the breakpoints. */ | |
3737 | for (index = 0; index <= last_breakpoint; index++) | |
6c95b8df | 3738 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
3d5f6d12 DJ |
3739 | |
3740 | return 1; | |
3741 | } | |
3742 | ||
4cc0665f MR |
3743 | static int |
3744 | micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, | |
3745 | struct address_space *aspace, | |
3746 | CORE_ADDR pc) | |
3747 | { | |
3748 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
3749 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
3750 | CORE_ADDR breaks[2] = {-1, -1}; | |
3751 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
3752 | CORE_ADDR loc = pc; | |
3753 | int sc_found = 0; | |
3754 | ULONGEST insn; | |
3755 | int insn_count; | |
3756 | int index; | |
3757 | ||
3758 | /* Assume all atomic sequences start with a ll/lld instruction. */ | |
3759 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
3760 | if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */ | |
3761 | return 0; | |
3762 | loc += MIPS_INSN16_SIZE; | |
3763 | insn <<= 16; | |
3764 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
3765 | if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */ | |
3766 | return 0; | |
3767 | loc += MIPS_INSN16_SIZE; | |
3768 | ||
3769 | /* Assume all atomic sequences end with an sc/scd instruction. Assume | |
3770 | that no atomic sequence is longer than "atomic_sequence_length" | |
3771 | instructions. */ | |
3772 | for (insn_count = 0; | |
3773 | !sc_found && insn_count < atomic_sequence_length; | |
3774 | ++insn_count) | |
3775 | { | |
3776 | int is_branch = 0; | |
3777 | ||
3778 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
3779 | loc += MIPS_INSN16_SIZE; | |
3780 | ||
3781 | /* Assume that there is at most one conditional branch in the | |
3782 | atomic sequence. If a branch is found, put a breakpoint in | |
3783 | its destination address. */ | |
3784 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
3785 | { | |
3786 | /* 48-bit instructions. */ | |
3787 | case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */ | |
3788 | loc += 2 * MIPS_INSN16_SIZE; | |
3789 | break; | |
3790 | ||
3791 | /* 32-bit instructions. */ | |
3792 | case 2 * MIPS_INSN16_SIZE: | |
3793 | switch (micromips_op (insn)) | |
3794 | { | |
3795 | case 0x10: /* POOL32I: bits 010000 */ | |
3796 | if ((b5s5_op (insn) & 0x18) != 0x0 | |
3797 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ | |
3798 | /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */ | |
3799 | && (b5s5_op (insn) & 0x1d) != 0x11 | |
3800 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ | |
3801 | && ((b5s5_op (insn) & 0x1e) != 0x14 | |
3802 | || (insn & 0x3) != 0x0) | |
3803 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ | |
3804 | && (b5s5_op (insn) & 0x1e) != 0x1a | |
3805 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ | |
3806 | && ((b5s5_op (insn) & 0x1e) != 0x1c | |
3807 | || (insn & 0x3) != 0x0) | |
3808 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ | |
3809 | && ((b5s5_op (insn) & 0x1c) != 0x1c | |
3810 | || (insn & 0x3) != 0x1)) | |
3811 | /* BC1ANY*: bits 010000 111xx xxx01 */ | |
3812 | break; | |
3813 | /* Fall through. */ | |
3814 | ||
3815 | case 0x25: /* BEQ: bits 100101 */ | |
3816 | case 0x2d: /* BNE: bits 101101 */ | |
3817 | insn <<= 16; | |
3818 | insn |= mips_fetch_instruction (gdbarch, | |
3819 | ISA_MICROMIPS, loc, NULL); | |
3820 | branch_bp = (loc + MIPS_INSN16_SIZE | |
3821 | + micromips_relative_offset16 (insn)); | |
3822 | is_branch = 1; | |
3823 | break; | |
3824 | ||
3825 | case 0x00: /* POOL32A: bits 000000 */ | |
3826 | insn <<= 16; | |
3827 | insn |= mips_fetch_instruction (gdbarch, | |
3828 | ISA_MICROMIPS, loc, NULL); | |
3829 | if (b0s6_op (insn) != 0x3c | |
3830 | /* POOL32Axf: bits 000000 ... 111100 */ | |
3831 | || (b6s10_ext (insn) & 0x2bf) != 0x3c) | |
3832 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
3833 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
3834 | break; | |
3835 | /* Fall through. */ | |
3836 | ||
3837 | case 0x1d: /* JALS: bits 011101 */ | |
3838 | case 0x35: /* J: bits 110101 */ | |
3839 | case 0x3d: /* JAL: bits 111101 */ | |
3840 | case 0x3c: /* JALX: bits 111100 */ | |
3841 | return 0; /* Fall back to the standard single-step code. */ | |
3842 | ||
3843 | case 0x18: /* POOL32C: bits 011000 */ | |
3844 | if ((b12s4_op (insn) & 0xb) == 0xb) | |
3845 | /* SC, SCD: bits 011000 1x11 */ | |
3846 | sc_found = 1; | |
3847 | break; | |
3848 | } | |
3849 | loc += MIPS_INSN16_SIZE; | |
3850 | break; | |
3851 | ||
3852 | /* 16-bit instructions. */ | |
3853 | case MIPS_INSN16_SIZE: | |
3854 | switch (micromips_op (insn)) | |
3855 | { | |
3856 | case 0x23: /* BEQZ16: bits 100011 */ | |
3857 | case 0x2b: /* BNEZ16: bits 101011 */ | |
3858 | branch_bp = loc + micromips_relative_offset7 (insn); | |
3859 | is_branch = 1; | |
3860 | break; | |
3861 | ||
3862 | case 0x11: /* POOL16C: bits 010001 */ | |
3863 | if ((b5s5_op (insn) & 0x1c) != 0xc | |
3864 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
3865 | && b5s5_op (insn) != 0x18) | |
3866 | /* JRADDIUSP: bits 010001 11000 */ | |
3867 | break; | |
3868 | return 0; /* Fall back to the standard single-step code. */ | |
3869 | ||
3870 | case 0x33: /* B16: bits 110011 */ | |
3871 | return 0; /* Fall back to the standard single-step code. */ | |
3872 | } | |
3873 | break; | |
3874 | } | |
3875 | if (is_branch) | |
3876 | { | |
3877 | if (last_breakpoint >= 1) | |
3878 | return 0; /* More than one branch found, fallback to the | |
3879 | standard single-step code. */ | |
3880 | breaks[1] = branch_bp; | |
3881 | last_breakpoint++; | |
3882 | } | |
3883 | } | |
3884 | if (!sc_found) | |
3885 | return 0; | |
3886 | ||
3887 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
3888 | breaks[0] = loc; | |
3889 | ||
3890 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
3891 | placed (branch instruction's destination) in the atomic sequence */ | |
3892 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) | |
3893 | last_breakpoint = 0; | |
3894 | ||
3895 | /* Effectively inserts the breakpoints. */ | |
3896 | for (index = 0; index <= last_breakpoint; index++) | |
3897 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); | |
3898 | ||
3899 | return 1; | |
3900 | } | |
3901 | ||
3902 | static int | |
3903 | deal_with_atomic_sequence (struct gdbarch *gdbarch, | |
3904 | struct address_space *aspace, CORE_ADDR pc) | |
3905 | { | |
3906 | if (mips_pc_is_mips (pc)) | |
3907 | return mips_deal_with_atomic_sequence (gdbarch, aspace, pc); | |
3908 | else if (mips_pc_is_micromips (gdbarch, pc)) | |
3909 | return micromips_deal_with_atomic_sequence (gdbarch, aspace, pc); | |
3910 | else | |
3911 | return 0; | |
3912 | } | |
3913 | ||
29639122 JB |
3914 | /* mips_software_single_step() is called just before we want to resume |
3915 | the inferior, if we want to single-step it but there is no hardware | |
3916 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 3917 | the target of the coming instruction and breakpoint it. */ |
29639122 | 3918 | |
e6590a1b | 3919 | int |
0b1b3e42 | 3920 | mips_software_single_step (struct frame_info *frame) |
c906108c | 3921 | { |
a6d9a66e | 3922 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6c95b8df | 3923 | struct address_space *aspace = get_frame_address_space (frame); |
8181d85f | 3924 | CORE_ADDR pc, next_pc; |
65596487 | 3925 | |
0b1b3e42 | 3926 | pc = get_frame_pc (frame); |
6c95b8df | 3927 | if (deal_with_atomic_sequence (gdbarch, aspace, pc)) |
3d5f6d12 DJ |
3928 | return 1; |
3929 | ||
0b1b3e42 | 3930 | next_pc = mips_next_pc (frame, pc); |
e6590a1b | 3931 | |
6c95b8df | 3932 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
e6590a1b | 3933 | return 1; |
29639122 | 3934 | } |
a65bbe44 | 3935 | |
29639122 | 3936 | /* Test whether the PC points to the return instruction at the |
025bb325 | 3937 | end of a function. */ |
65596487 | 3938 | |
29639122 | 3939 | static int |
e17a4113 | 3940 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 | 3941 | { |
6321c22a MR |
3942 | ULONGEST insn; |
3943 | ULONGEST hint; | |
3944 | ||
3945 | /* This used to check for MIPS16, but this piece of code is never | |
4cc0665f MR |
3946 | called for MIPS16 functions. And likewise microMIPS ones. */ |
3947 | gdb_assert (mips_pc_is_mips (pc)); | |
6321c22a | 3948 | |
4cc0665f | 3949 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
6321c22a MR |
3950 | hint = 0x7c0; |
3951 | return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */ | |
29639122 | 3952 | } |
c906108c | 3953 | |
c906108c | 3954 | |
29639122 JB |
3955 | /* This fencepost looks highly suspicious to me. Removing it also |
3956 | seems suspicious as it could affect remote debugging across serial | |
3957 | lines. */ | |
c906108c | 3958 | |
29639122 | 3959 | static CORE_ADDR |
74ed0bb4 | 3960 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
3961 | { |
3962 | CORE_ADDR start_pc; | |
3963 | CORE_ADDR fence; | |
3964 | int instlen; | |
3965 | int seen_adjsp = 0; | |
d6b48e9c | 3966 | struct inferior *inf; |
65596487 | 3967 | |
74ed0bb4 | 3968 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
3969 | start_pc = pc; |
3970 | fence = start_pc - heuristic_fence_post; | |
3971 | if (start_pc == 0) | |
3972 | return 0; | |
65596487 | 3973 | |
29639122 JB |
3974 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
3975 | fence = VM_MIN_ADDRESS; | |
65596487 | 3976 | |
4cc0665f | 3977 | instlen = mips_pc_is_mips (pc) ? MIPS_INSN32_SIZE : MIPS_INSN16_SIZE; |
98b4dd94 | 3978 | |
d6b48e9c PA |
3979 | inf = current_inferior (); |
3980 | ||
025bb325 | 3981 | /* Search back for previous return. */ |
29639122 JB |
3982 | for (start_pc -= instlen;; start_pc -= instlen) |
3983 | if (start_pc < fence) | |
3984 | { | |
3985 | /* It's not clear to me why we reach this point when | |
3986 | stop_soon, but with this test, at least we | |
3987 | don't print out warnings for every child forked (eg, on | |
3988 | decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 3989 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
3990 | { |
3991 | static int blurb_printed = 0; | |
98b4dd94 | 3992 | |
5af949e3 UW |
3993 | warning (_("GDB can't find the start of the function at %s."), |
3994 | paddress (gdbarch, pc)); | |
29639122 JB |
3995 | |
3996 | if (!blurb_printed) | |
3997 | { | |
3998 | /* This actually happens frequently in embedded | |
3999 | development, when you first connect to a board | |
4000 | and your stack pointer and pc are nowhere in | |
4001 | particular. This message needs to give people | |
4002 | in that situation enough information to | |
4003 | determine that it's no big deal. */ | |
4004 | printf_filtered ("\n\ | |
5af949e3 | 4005 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
4006 | and thus can't determine the size of that function's stack frame.\n\ |
4007 | This means that GDB may be unable to access that stack frame, or\n\ | |
4008 | the frames below it.\n\ | |
4009 | This problem is most likely caused by an invalid program counter or\n\ | |
4010 | stack pointer.\n\ | |
4011 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 4012 | from %s for code which looks like the beginning of a\n\ |
29639122 | 4013 | function, you can increase the range of the search using the `set\n\ |
5af949e3 UW |
4014 | heuristic-fence-post' command.\n", |
4015 | paddress (gdbarch, pc), paddress (gdbarch, pc)); | |
29639122 JB |
4016 | blurb_printed = 1; |
4017 | } | |
4018 | } | |
4019 | ||
4020 | return 0; | |
4021 | } | |
4cc0665f | 4022 | else if (mips_pc_is_mips16 (gdbarch, start_pc)) |
29639122 JB |
4023 | { |
4024 | unsigned short inst; | |
4025 | ||
4026 | /* On MIPS16, any one of the following is likely to be the | |
4027 | start of a function: | |
193774b3 MR |
4028 | extend save |
4029 | save | |
29639122 JB |
4030 | entry |
4031 | addiu sp,-n | |
4032 | daddiu sp,-n | |
025bb325 | 4033 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ |
4cc0665f | 4034 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL); |
193774b3 MR |
4035 | if ((inst & 0xff80) == 0x6480) /* save */ |
4036 | { | |
4037 | if (start_pc - instlen >= fence) | |
4038 | { | |
4cc0665f MR |
4039 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, |
4040 | start_pc - instlen, NULL); | |
193774b3 MR |
4041 | if ((inst & 0xf800) == 0xf000) /* extend */ |
4042 | start_pc -= instlen; | |
4043 | } | |
4044 | break; | |
4045 | } | |
4046 | else if (((inst & 0xf81f) == 0xe809 | |
4047 | && (inst & 0x700) != 0x700) /* entry */ | |
4048 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
4049 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
4050 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
4051 | break; |
4052 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
4053 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
4054 | seen_adjsp = 1; | |
4055 | else | |
4056 | seen_adjsp = 0; | |
4057 | } | |
4cc0665f MR |
4058 | else if (mips_pc_is_micromips (gdbarch, start_pc)) |
4059 | { | |
4060 | ULONGEST insn; | |
4061 | int stop = 0; | |
4062 | long offset; | |
4063 | int dreg; | |
4064 | int sreg; | |
4065 | ||
4066 | /* On microMIPS, any one of the following is likely to be the | |
4067 | start of a function: | |
4068 | ADDIUSP -imm | |
4069 | (D)ADDIU $sp, -imm | |
4070 | LUI $gp, imm */ | |
4071 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
4072 | switch (micromips_op (insn)) | |
4073 | { | |
4074 | case 0xc: /* ADDIU: bits 001100 */ | |
4075 | case 0x17: /* DADDIU: bits 010111 */ | |
4076 | sreg = b0s5_reg (insn); | |
4077 | dreg = b5s5_reg (insn); | |
4078 | insn <<= 16; | |
4079 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, | |
4080 | pc + MIPS_INSN16_SIZE, NULL); | |
4081 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
4082 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
4083 | /* (D)ADDIU $sp, imm */ | |
4084 | && offset < 0) | |
4085 | stop = 1; | |
4086 | break; | |
4087 | ||
4088 | case 0x10: /* POOL32I: bits 010000 */ | |
4089 | if (b5s5_op (insn) == 0xd | |
4090 | /* LUI: bits 010000 001101 */ | |
4091 | && b0s5_reg (insn >> 16) == 28) | |
4092 | /* LUI $gp, imm */ | |
4093 | stop = 1; | |
4094 | break; | |
4095 | ||
4096 | case 0x13: /* POOL16D: bits 010011 */ | |
4097 | if ((insn & 0x1) == 0x1) | |
4098 | /* ADDIUSP: bits 010011 1 */ | |
4099 | { | |
4100 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
4101 | if (offset < 0) | |
4102 | /* ADDIUSP -imm */ | |
4103 | stop = 1; | |
4104 | } | |
4105 | else | |
4106 | /* ADDIUS5: bits 010011 0 */ | |
4107 | { | |
4108 | dreg = b5s5_reg (insn); | |
4109 | offset = (b1s4_imm (insn) ^ 8) - 8; | |
4110 | if (dreg == MIPS_SP_REGNUM && offset < 0) | |
4111 | /* ADDIUS5 $sp, -imm */ | |
4112 | stop = 1; | |
4113 | } | |
4114 | break; | |
4115 | } | |
4116 | if (stop) | |
4117 | break; | |
4118 | } | |
e17a4113 | 4119 | else if (mips_about_to_return (gdbarch, start_pc)) |
29639122 | 4120 | { |
4c7d22cb | 4121 | /* Skip return and its delay slot. */ |
95ac2dcf | 4122 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
4123 | break; |
4124 | } | |
4125 | ||
4126 | return start_pc; | |
c906108c SS |
4127 | } |
4128 | ||
6c0d6680 DJ |
4129 | struct mips_objfile_private |
4130 | { | |
4131 | bfd_size_type size; | |
4132 | char *contents; | |
4133 | }; | |
4134 | ||
f09ded24 AC |
4135 | /* According to the current ABI, should the type be passed in a |
4136 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 4137 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 | 4138 | FP registers and, consequently this returns false - forces FP |
025bb325 | 4139 | arguments into integer registers. */ |
f09ded24 AC |
4140 | |
4141 | static int | |
74ed0bb4 MD |
4142 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
4143 | struct type *arg_type) | |
f09ded24 AC |
4144 | { |
4145 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 4146 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
4147 | && (typecode == TYPE_CODE_STRUCT |
4148 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 4149 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
4150 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
4151 | == TYPE_CODE_FLT)) | |
74ed0bb4 | 4152 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
4153 | } |
4154 | ||
49e790b0 | 4155 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
025bb325 | 4156 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ |
49e790b0 DJ |
4157 | |
4158 | static int | |
4159 | mips_type_needs_double_align (struct type *type) | |
4160 | { | |
4161 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 4162 | |
49e790b0 DJ |
4163 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
4164 | return 1; | |
4165 | else if (typecode == TYPE_CODE_STRUCT) | |
4166 | { | |
4167 | if (TYPE_NFIELDS (type) < 1) | |
4168 | return 0; | |
4169 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
4170 | } | |
4171 | else if (typecode == TYPE_CODE_UNION) | |
4172 | { | |
361d1df0 | 4173 | int i, n; |
49e790b0 DJ |
4174 | |
4175 | n = TYPE_NFIELDS (type); | |
4176 | for (i = 0; i < n; i++) | |
4177 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
4178 | return 1; | |
4179 | return 0; | |
4180 | } | |
4181 | return 0; | |
4182 | } | |
4183 | ||
dc604539 AC |
4184 | /* Adjust the address downward (direction of stack growth) so that it |
4185 | is correctly aligned for a new stack frame. */ | |
4186 | static CORE_ADDR | |
4187 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
4188 | { | |
5b03f266 | 4189 | return align_down (addr, 16); |
dc604539 AC |
4190 | } |
4191 | ||
8ae38c14 | 4192 | /* Implement the "push_dummy_code" gdbarch method. */ |
2c76a0c7 JB |
4193 | |
4194 | static CORE_ADDR | |
4195 | mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
4196 | CORE_ADDR funaddr, struct value **args, | |
4197 | int nargs, struct type *value_type, | |
4198 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
4199 | struct regcache *regcache) | |
4200 | { | |
4201 | CORE_ADDR nop_addr; | |
4202 | static gdb_byte nop_insn[] = { 0, 0, 0, 0 }; | |
4203 | ||
4204 | /* Reserve enough room on the stack for our breakpoint instruction. */ | |
4205 | *bp_addr = sp - sizeof (nop_insn); | |
4206 | ||
4207 | /* The breakpoint layer automatically adjusts the address of | |
4208 | breakpoints inserted in a branch delay slot. With enough | |
4209 | bad luck, the 4 bytes located just before our breakpoint | |
4210 | instruction could look like a branch instruction, and thus | |
4211 | trigger the adjustement, and break the function call entirely. | |
4212 | So, we reserve those 4 bytes and write a nop instruction | |
4213 | to prevent that from happening. */ | |
4214 | nop_addr = *bp_addr - sizeof (nop_insn); | |
4215 | write_memory (nop_addr, nop_insn, sizeof (nop_insn)); | |
4216 | sp = mips_frame_align (gdbarch, nop_addr); | |
4217 | ||
4218 | /* Inferior resumes at the function entry point. */ | |
4219 | *real_pc = funaddr; | |
4220 | ||
4221 | return sp; | |
4222 | } | |
4223 | ||
f7ab6ec6 | 4224 | static CORE_ADDR |
7d9b040b | 4225 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4226 | struct regcache *regcache, CORE_ADDR bp_addr, |
4227 | int nargs, struct value **args, CORE_ADDR sp, | |
4228 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
4229 | { |
4230 | int argreg; | |
4231 | int float_argreg; | |
4232 | int argnum; | |
4233 | int len = 0; | |
4234 | int stack_offset = 0; | |
480d3dd2 | 4235 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 4236 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4237 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 4238 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 4239 | |
25ab4790 AC |
4240 | /* For shared libraries, "t9" needs to point at the function |
4241 | address. */ | |
4c7d22cb | 4242 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4243 | |
4244 | /* Set the return address register to point to the entry point of | |
4245 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4246 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4247 | |
c906108c | 4248 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
4249 | are properly aligned. The stack has to be at least 64-bit |
4250 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4251 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4252 | aligned, so we round to this widest known alignment. */ | |
4253 | ||
5b03f266 AC |
4254 | sp = align_down (sp, 16); |
4255 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 4256 | |
46e0f506 | 4257 | /* Now make space on the stack for the args. We allocate more |
c906108c | 4258 | than necessary for EABI, because the first few arguments are |
46e0f506 | 4259 | passed in registers, but that's OK. */ |
c906108c | 4260 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 4261 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 4262 | sp -= align_up (len, 16); |
c906108c | 4263 | |
9ace0497 | 4264 | if (mips_debug) |
6d82d43b | 4265 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4266 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
4267 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
9ace0497 | 4268 | |
c906108c | 4269 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 4270 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4271 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 4272 | |
46e0f506 | 4273 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 4274 | if (struct_return) |
9ace0497 AC |
4275 | { |
4276 | if (mips_debug) | |
4277 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4278 | "mips_eabi_push_dummy_call: " |
4279 | "struct_return reg=%d %s\n", | |
5af949e3 | 4280 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4281 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 4282 | } |
c906108c SS |
4283 | |
4284 | /* Now load as many as possible of the first arguments into | |
4285 | registers, and push the rest onto the stack. Loop thru args | |
4286 | from first to last. */ | |
4287 | for (argnum = 0; argnum < nargs; argnum++) | |
4288 | { | |
47a35522 MK |
4289 | const gdb_byte *val; |
4290 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 4291 | struct value *arg = args[argnum]; |
4991999e | 4292 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
4293 | int len = TYPE_LENGTH (arg_type); |
4294 | enum type_code typecode = TYPE_CODE (arg_type); | |
4295 | ||
9ace0497 AC |
4296 | if (mips_debug) |
4297 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4298 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 4299 | argnum + 1, len, (int) typecode); |
9ace0497 | 4300 | |
930bd0e0 KB |
4301 | /* Function pointer arguments to mips16 code need to be made into |
4302 | mips16 pointers. */ | |
4303 | if (typecode == TYPE_CODE_PTR | |
4304 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
4305 | { | |
4306 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
4307 | len, byte_order); | |
4cc0665f MR |
4308 | if (mips_pc_is_mips (addr)) |
4309 | val = value_contents (arg); | |
4310 | else | |
930bd0e0 KB |
4311 | { |
4312 | store_signed_integer (valbuf, len, byte_order, | |
4cc0665f | 4313 | make_compact_addr (addr)); |
930bd0e0 KB |
4314 | val = valbuf; |
4315 | } | |
930bd0e0 | 4316 | } |
c906108c | 4317 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 4318 | reference. */ |
930bd0e0 | 4319 | else if (len > regsize |
9ace0497 | 4320 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 4321 | { |
e17a4113 UW |
4322 | store_unsigned_integer (valbuf, regsize, byte_order, |
4323 | value_address (arg)); | |
c906108c | 4324 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 4325 | len = regsize; |
c906108c | 4326 | val = valbuf; |
9ace0497 AC |
4327 | if (mips_debug) |
4328 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
4329 | } |
4330 | else | |
47a35522 | 4331 | val = value_contents (arg); |
c906108c SS |
4332 | |
4333 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
4334 | even-numbered floating point register. Round the FP register |
4335 | up before the check to see if there are any FP registers | |
46e0f506 MS |
4336 | left. Non MIPS_EABI targets also pass the FP in the integer |
4337 | registers so also round up normal registers. */ | |
74ed0bb4 | 4338 | if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
4339 | { |
4340 | if ((float_argreg & 1)) | |
4341 | float_argreg++; | |
4342 | } | |
c906108c SS |
4343 | |
4344 | /* Floating point arguments passed in registers have to be | |
4345 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
4346 | are passed in register pairs; the even register gets |
4347 | the low word, and the odd register gets the high word. | |
4348 | On non-EABI processors, the first two floating point arguments are | |
4349 | also copied to general registers, because MIPS16 functions | |
4350 | don't use float registers for arguments. This duplication of | |
4351 | arguments in general registers can't hurt non-MIPS16 functions | |
4352 | because those registers are normally skipped. */ | |
1012bd0e EZ |
4353 | /* MIPS_EABI squeezes a struct that contains a single floating |
4354 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 4355 | stack. */ |
74ed0bb4 MD |
4356 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4357 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 4358 | { |
6da397e0 KB |
4359 | /* EABI32 will pass doubles in consecutive registers, even on |
4360 | 64-bit cores. At one time, we used to check the size of | |
4361 | `float_argreg' to determine whether or not to pass doubles | |
4362 | in consecutive registers, but this is not sufficient for | |
4363 | making the ABI determination. */ | |
4364 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 4365 | { |
72a155b4 | 4366 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 4367 | == BFD_ENDIAN_BIG ? 4 : 0; |
a8852dc5 | 4368 | long regval; |
c906108c SS |
4369 | |
4370 | /* Write the low word of the double to the even register(s). */ | |
a8852dc5 KB |
4371 | regval = extract_signed_integer (val + low_offset, |
4372 | 4, byte_order); | |
9ace0497 | 4373 | if (mips_debug) |
acdb74a0 | 4374 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4375 | float_argreg, phex (regval, 4)); |
a8852dc5 | 4376 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4377 | |
4378 | /* Write the high word of the double to the odd register(s). */ | |
a8852dc5 KB |
4379 | regval = extract_signed_integer (val + 4 - low_offset, |
4380 | 4, byte_order); | |
9ace0497 | 4381 | if (mips_debug) |
acdb74a0 | 4382 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4383 | float_argreg, phex (regval, 4)); |
a8852dc5 | 4384 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4385 | } |
4386 | else | |
4387 | { | |
4388 | /* This is a floating point value that fits entirely | |
4389 | in a single register. */ | |
53a5351d | 4390 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 4391 | above to ensure that it is even register aligned. */ |
a8852dc5 | 4392 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
9ace0497 | 4393 | if (mips_debug) |
acdb74a0 | 4394 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 4395 | float_argreg, phex (regval, len)); |
a8852dc5 | 4396 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4397 | } |
4398 | } | |
4399 | else | |
4400 | { | |
4401 | /* Copy the argument to general registers or the stack in | |
4402 | register-sized pieces. Large arguments are split between | |
4403 | registers and stack. */ | |
1a69e1e4 DJ |
4404 | /* Note: structs whose size is not a multiple of regsize |
4405 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
4406 | them in registers where gcc sometimes puts them on the |
4407 | stack. For maximum compatibility, we will put them in | |
4408 | both places. */ | |
1a69e1e4 | 4409 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 4410 | |
f09ded24 | 4411 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 4412 | register are only written to memory. */ |
c906108c SS |
4413 | while (len > 0) |
4414 | { | |
ebafbe83 | 4415 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 4416 | int stack_used_p = 0; |
1a69e1e4 | 4417 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 4418 | |
acdb74a0 AC |
4419 | if (mips_debug) |
4420 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4421 | partial_len); | |
4422 | ||
566f0f7a | 4423 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 4424 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 4425 | || odd_sized_struct |
74ed0bb4 | 4426 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 4427 | { |
c906108c | 4428 | /* Should shorter than int integer values be |
025bb325 | 4429 | promoted to int before being stored? */ |
c906108c | 4430 | int longword_offset = 0; |
9ace0497 | 4431 | CORE_ADDR addr; |
566f0f7a | 4432 | stack_used_p = 1; |
72a155b4 | 4433 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 4434 | { |
1a69e1e4 | 4435 | if (regsize == 8 |
480d3dd2 AC |
4436 | && (typecode == TYPE_CODE_INT |
4437 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4438 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 4439 | longword_offset = regsize - len; |
480d3dd2 AC |
4440 | else if ((typecode == TYPE_CODE_STRUCT |
4441 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
4442 | && TYPE_LENGTH (arg_type) < regsize) |
4443 | longword_offset = regsize - len; | |
7a292a7a | 4444 | } |
c5aa993b | 4445 | |
9ace0497 AC |
4446 | if (mips_debug) |
4447 | { | |
5af949e3 UW |
4448 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4449 | paddress (gdbarch, stack_offset)); | |
4450 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4451 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 4452 | } |
361d1df0 | 4453 | |
9ace0497 AC |
4454 | addr = sp + stack_offset + longword_offset; |
4455 | ||
4456 | if (mips_debug) | |
4457 | { | |
4458 | int i; | |
5af949e3 UW |
4459 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4460 | paddress (gdbarch, addr)); | |
9ace0497 AC |
4461 | for (i = 0; i < partial_len; i++) |
4462 | { | |
6d82d43b | 4463 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 4464 | val[i] & 0xff); |
9ace0497 AC |
4465 | } |
4466 | } | |
4467 | write_memory (addr, val, partial_len); | |
c906108c SS |
4468 | } |
4469 | ||
f09ded24 AC |
4470 | /* Note!!! This is NOT an else clause. Odd sized |
4471 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 4472 | arguments will not. */ |
566f0f7a | 4473 | /* Write this portion of the argument to a general |
6d82d43b | 4474 | purpose register. */ |
74ed0bb4 MD |
4475 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
4476 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 4477 | { |
6d82d43b | 4478 | LONGEST regval = |
a8852dc5 | 4479 | extract_signed_integer (val, partial_len, byte_order); |
c906108c | 4480 | |
9ace0497 | 4481 | if (mips_debug) |
acdb74a0 | 4482 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 4483 | argreg, |
1a69e1e4 | 4484 | phex (regval, regsize)); |
a8852dc5 | 4485 | regcache_cooked_write_signed (regcache, argreg, regval); |
c906108c | 4486 | argreg++; |
c906108c | 4487 | } |
c5aa993b | 4488 | |
c906108c SS |
4489 | len -= partial_len; |
4490 | val += partial_len; | |
4491 | ||
b021a221 MS |
4492 | /* Compute the offset into the stack at which we will |
4493 | copy the next parameter. | |
566f0f7a | 4494 | |
566f0f7a | 4495 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 4496 | only needs to be adjusted when it has been used. */ |
c906108c | 4497 | |
46e0f506 | 4498 | if (stack_used_p) |
1a69e1e4 | 4499 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
4500 | } |
4501 | } | |
9ace0497 AC |
4502 | if (mips_debug) |
4503 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
4504 | } |
4505 | ||
f10683bb | 4506 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4507 | |
0f71a2f6 JM |
4508 | /* Return adjusted stack pointer. */ |
4509 | return sp; | |
4510 | } | |
4511 | ||
a1f5b845 | 4512 | /* Determine the return value convention being used. */ |
6d82d43b | 4513 | |
9c8fdbfa | 4514 | static enum return_value_convention |
6a3a010b | 4515 | mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 4516 | struct type *type, struct regcache *regcache, |
47a35522 | 4517 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4518 | { |
609ba780 JM |
4519 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4520 | int fp_return_type = 0; | |
4521 | int offset, regnum, xfer; | |
4522 | ||
9c8fdbfa AC |
4523 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
4524 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
4525 | |
4526 | /* Floating point type? */ | |
4527 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4528 | { | |
4529 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
4530 | fp_return_type = 1; | |
4531 | /* Structs with a single field of float type | |
4532 | are returned in a floating point register. */ | |
4533 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4534 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4535 | && TYPE_NFIELDS (type) == 1) | |
4536 | { | |
4537 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); | |
4538 | ||
4539 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) | |
4540 | fp_return_type = 1; | |
4541 | } | |
4542 | } | |
4543 | ||
4544 | if (fp_return_type) | |
4545 | { | |
4546 | /* A floating-point value belongs in the least significant part | |
4547 | of FP0/FP1. */ | |
4548 | if (mips_debug) | |
4549 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
4550 | regnum = mips_regnum (gdbarch)->fp0; | |
4551 | } | |
4552 | else | |
4553 | { | |
4554 | /* An integer value goes in V0/V1. */ | |
4555 | if (mips_debug) | |
4556 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
4557 | regnum = MIPS_V0_REGNUM; | |
4558 | } | |
4559 | for (offset = 0; | |
4560 | offset < TYPE_LENGTH (type); | |
4561 | offset += mips_abi_regsize (gdbarch), regnum++) | |
4562 | { | |
4563 | xfer = mips_abi_regsize (gdbarch); | |
4564 | if (offset + xfer > TYPE_LENGTH (type)) | |
4565 | xfer = TYPE_LENGTH (type) - offset; | |
4566 | mips_xfer_register (gdbarch, regcache, | |
4567 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
4568 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
4569 | offset); | |
4570 | } | |
4571 | ||
9c8fdbfa | 4572 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
4573 | } |
4574 | ||
6d82d43b AC |
4575 | |
4576 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 4577 | |
8d26208a DJ |
4578 | /* Search for a naturally aligned double at OFFSET inside a struct |
4579 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
4580 | registers. */ | |
4581 | ||
4582 | static int | |
74ed0bb4 MD |
4583 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
4584 | int offset) | |
8d26208a DJ |
4585 | { |
4586 | int i; | |
4587 | ||
4588 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
4589 | return 0; | |
4590 | ||
74ed0bb4 | 4591 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
4592 | return 0; |
4593 | ||
4594 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
4595 | return 0; | |
4596 | ||
4597 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
4598 | { | |
4599 | int pos; | |
4600 | struct type *field_type; | |
4601 | ||
4602 | /* We're only looking at normal fields. */ | |
5bc60cfb | 4603 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
8d26208a DJ |
4604 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
4605 | continue; | |
4606 | ||
4607 | /* If we have gone past the offset, there is no double to pass. */ | |
4608 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
4609 | if (pos > offset) | |
4610 | return 0; | |
4611 | ||
4612 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
4613 | ||
4614 | /* If this field is entirely before the requested offset, go | |
4615 | on to the next one. */ | |
4616 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
4617 | continue; | |
4618 | ||
4619 | /* If this is our special aligned double, we can stop. */ | |
4620 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
4621 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
4622 | return 1; | |
4623 | ||
4624 | /* This field starts at or before the requested offset, and | |
4625 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 4626 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
4627 | } |
4628 | ||
4629 | return 0; | |
4630 | } | |
4631 | ||
f7ab6ec6 | 4632 | static CORE_ADDR |
7d9b040b | 4633 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4634 | struct regcache *regcache, CORE_ADDR bp_addr, |
4635 | int nargs, struct value **args, CORE_ADDR sp, | |
4636 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
4637 | { |
4638 | int argreg; | |
4639 | int float_argreg; | |
4640 | int argnum; | |
4641 | int len = 0; | |
4642 | int stack_offset = 0; | |
480d3dd2 | 4643 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 4644 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4645 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 4646 | |
25ab4790 AC |
4647 | /* For shared libraries, "t9" needs to point at the function |
4648 | address. */ | |
4c7d22cb | 4649 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4650 | |
4651 | /* Set the return address register to point to the entry point of | |
4652 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4653 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4654 | |
cb3d25d1 MS |
4655 | /* First ensure that the stack and structure return address (if any) |
4656 | are properly aligned. The stack has to be at least 64-bit | |
4657 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4658 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4659 | aligned, so we round to this widest known alignment. */ | |
4660 | ||
5b03f266 AC |
4661 | sp = align_down (sp, 16); |
4662 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
4663 | |
4664 | /* Now make space on the stack for the args. */ | |
4665 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 4666 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 4667 | sp -= align_up (len, 16); |
cb3d25d1 MS |
4668 | |
4669 | if (mips_debug) | |
6d82d43b | 4670 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4671 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
4672 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
4673 | |
4674 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4675 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4676 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 4677 | |
46e0f506 | 4678 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
4679 | if (struct_return) |
4680 | { | |
4681 | if (mips_debug) | |
4682 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4683 | "mips_n32n64_push_dummy_call: " |
4684 | "struct_return reg=%d %s\n", | |
5af949e3 | 4685 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4686 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
4687 | } |
4688 | ||
4689 | /* Now load as many as possible of the first arguments into | |
4690 | registers, and push the rest onto the stack. Loop thru args | |
4691 | from first to last. */ | |
4692 | for (argnum = 0; argnum < nargs; argnum++) | |
4693 | { | |
47a35522 | 4694 | const gdb_byte *val; |
cb3d25d1 | 4695 | struct value *arg = args[argnum]; |
4991999e | 4696 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
4697 | int len = TYPE_LENGTH (arg_type); |
4698 | enum type_code typecode = TYPE_CODE (arg_type); | |
4699 | ||
4700 | if (mips_debug) | |
4701 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4702 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
4703 | argnum + 1, len, (int) typecode); |
4704 | ||
47a35522 | 4705 | val = value_contents (arg); |
cb3d25d1 | 4706 | |
5b68030f JM |
4707 | /* A 128-bit long double value requires an even-odd pair of |
4708 | floating-point registers. */ | |
4709 | if (len == 16 | |
4710 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
4711 | && (float_argreg & 1)) | |
4712 | { | |
4713 | float_argreg++; | |
4714 | argreg++; | |
4715 | } | |
4716 | ||
74ed0bb4 MD |
4717 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4718 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
4719 | { |
4720 | /* This is a floating point value that fits entirely | |
5b68030f JM |
4721 | in a single register or a pair of registers. */ |
4722 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
e17a4113 | 4723 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
cb3d25d1 MS |
4724 | if (mips_debug) |
4725 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 4726 | float_argreg, phex (regval, reglen)); |
8d26208a | 4727 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
4728 | |
4729 | if (mips_debug) | |
4730 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 4731 | argreg, phex (regval, reglen)); |
9c9acae0 | 4732 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
4733 | float_argreg++; |
4734 | argreg++; | |
5b68030f JM |
4735 | if (len == 16) |
4736 | { | |
e17a4113 UW |
4737 | regval = extract_unsigned_integer (val + reglen, |
4738 | reglen, byte_order); | |
5b68030f JM |
4739 | if (mips_debug) |
4740 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4741 | float_argreg, phex (regval, reglen)); | |
4742 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
4743 | ||
4744 | if (mips_debug) | |
4745 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4746 | argreg, phex (regval, reglen)); | |
4747 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
4748 | float_argreg++; | |
4749 | argreg++; | |
4750 | } | |
cb3d25d1 MS |
4751 | } |
4752 | else | |
4753 | { | |
4754 | /* Copy the argument to general registers or the stack in | |
4755 | register-sized pieces. Large arguments are split between | |
4756 | registers and stack. */ | |
ab2e1992 MR |
4757 | /* For N32/N64, structs, unions, or other composite types are |
4758 | treated as a sequence of doublewords, and are passed in integer | |
4759 | or floating point registers as though they were simple scalar | |
4760 | parameters to the extent that they fit, with any excess on the | |
4761 | stack packed according to the normal memory layout of the | |
4762 | object. | |
4763 | The caller does not reserve space for the register arguments; | |
4764 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 4765 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 4766 | register are only written to memory. */ |
cb3d25d1 MS |
4767 | while (len > 0) |
4768 | { | |
ad018eee | 4769 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 4770 | int stack_used_p = 0; |
1a69e1e4 | 4771 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
4772 | |
4773 | if (mips_debug) | |
4774 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4775 | partial_len); | |
4776 | ||
74ed0bb4 MD |
4777 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
4778 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 4779 | |
cb3d25d1 | 4780 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 4781 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
4782 | { |
4783 | /* Should shorter than int integer values be | |
025bb325 | 4784 | promoted to int before being stored? */ |
cb3d25d1 MS |
4785 | int longword_offset = 0; |
4786 | CORE_ADDR addr; | |
4787 | stack_used_p = 1; | |
72a155b4 | 4788 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 4789 | { |
1a69e1e4 | 4790 | if ((typecode == TYPE_CODE_INT |
5b68030f | 4791 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
4792 | && len <= 4) |
4793 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
4794 | } |
4795 | ||
4796 | if (mips_debug) | |
4797 | { | |
5af949e3 UW |
4798 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4799 | paddress (gdbarch, stack_offset)); | |
4800 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4801 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
4802 | } |
4803 | ||
4804 | addr = sp + stack_offset + longword_offset; | |
4805 | ||
4806 | if (mips_debug) | |
4807 | { | |
4808 | int i; | |
5af949e3 UW |
4809 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4810 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
4811 | for (i = 0; i < partial_len; i++) |
4812 | { | |
6d82d43b | 4813 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
4814 | val[i] & 0xff); |
4815 | } | |
4816 | } | |
4817 | write_memory (addr, val, partial_len); | |
4818 | } | |
4819 | ||
4820 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 4821 | structs may go thru BOTH paths. */ |
cb3d25d1 | 4822 | /* Write this portion of the argument to a general |
6d82d43b | 4823 | purpose register. */ |
74ed0bb4 | 4824 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 4825 | { |
5863b5d5 MR |
4826 | LONGEST regval; |
4827 | ||
4828 | /* Sign extend pointers, 32-bit integers and signed | |
4829 | 16-bit and 8-bit integers; everything else is taken | |
4830 | as is. */ | |
4831 | ||
4832 | if ((partial_len == 4 | |
4833 | && (typecode == TYPE_CODE_PTR | |
4834 | || typecode == TYPE_CODE_INT)) | |
4835 | || (partial_len < 4 | |
4836 | && typecode == TYPE_CODE_INT | |
4837 | && !TYPE_UNSIGNED (arg_type))) | |
e17a4113 UW |
4838 | regval = extract_signed_integer (val, partial_len, |
4839 | byte_order); | |
5863b5d5 | 4840 | else |
e17a4113 UW |
4841 | regval = extract_unsigned_integer (val, partial_len, |
4842 | byte_order); | |
cb3d25d1 MS |
4843 | |
4844 | /* A non-floating-point argument being passed in a | |
4845 | general register. If a struct or union, and if | |
4846 | the remaining length is smaller than the register | |
4847 | size, we have to adjust the register value on | |
4848 | big endian targets. | |
4849 | ||
4850 | It does not seem to be necessary to do the | |
1a69e1e4 | 4851 | same for integral types. */ |
cb3d25d1 | 4852 | |
72a155b4 | 4853 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4854 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
4855 | && (typecode == TYPE_CODE_STRUCT |
4856 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4857 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 4858 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
4859 | |
4860 | if (mips_debug) | |
4861 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4862 | argreg, | |
1a69e1e4 | 4863 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 4864 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 4865 | |
74ed0bb4 | 4866 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
4867 | TYPE_LENGTH (arg_type) - len)) |
4868 | { | |
4869 | if (mips_debug) | |
4870 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
4871 | float_argreg, | |
4872 | phex (regval, MIPS64_REGSIZE)); | |
4873 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
4874 | regval); | |
4875 | } | |
4876 | ||
4877 | float_argreg++; | |
cb3d25d1 MS |
4878 | argreg++; |
4879 | } | |
4880 | ||
4881 | len -= partial_len; | |
4882 | val += partial_len; | |
4883 | ||
b021a221 MS |
4884 | /* Compute the offset into the stack at which we will |
4885 | copy the next parameter. | |
cb3d25d1 MS |
4886 | |
4887 | In N32 (N64?), the stack_offset only needs to be | |
4888 | adjusted when it has been used. */ | |
4889 | ||
4890 | if (stack_used_p) | |
1a69e1e4 | 4891 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
4892 | } |
4893 | } | |
4894 | if (mips_debug) | |
4895 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4896 | } | |
4897 | ||
f10683bb | 4898 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4899 | |
cb3d25d1 MS |
4900 | /* Return adjusted stack pointer. */ |
4901 | return sp; | |
4902 | } | |
4903 | ||
6d82d43b | 4904 | static enum return_value_convention |
6a3a010b | 4905 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, |
6d82d43b | 4906 | struct type *type, struct regcache *regcache, |
47a35522 | 4907 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 4908 | { |
72a155b4 | 4909 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
4910 | |
4911 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
4912 | ||
4913 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
4914 | if needed), as appropriate for the type. Composite results (struct, | |
4915 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
4916 | following rules: | |
4917 | ||
4918 | * A struct with only one or two floating point fields is returned in $f0 | |
4919 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
4920 | case. | |
4921 | ||
f08877ba | 4922 | * Any other composite results of at most 128 bits are returned in |
b18bb924 MR |
4923 | $2 (first 64 bits) and $3 (remainder, if necessary). |
4924 | ||
4925 | * Larger composite results are handled by converting the function to a | |
4926 | procedure with an implicit first parameter, which is a pointer to an area | |
4927 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
4928 | that all composite results be handled by conversion to implicit first | |
4929 | parameters. The MIPS/SGI Fortran implementation has always made a | |
4930 | specific exception to return COMPLEX results in the floating point | |
4931 | registers.] */ | |
4932 | ||
f08877ba | 4933 | if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 4934 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
4935 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
4936 | && TYPE_LENGTH (type) == 16 | |
4937 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4938 | { | |
4939 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
4940 | two registers are used in the same as memory order, so the | |
4941 | eight bytes with the lower memory address are in $f0. */ | |
4942 | if (mips_debug) | |
4943 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 4944 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
4945 | (gdbarch_num_regs (gdbarch) |
4946 | + mips_regnum (gdbarch)->fp0), | |
72a155b4 | 4947 | 8, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4948 | readbuf, writebuf, 0); |
ba32f989 | 4949 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
4950 | (gdbarch_num_regs (gdbarch) |
4951 | + mips_regnum (gdbarch)->fp0 + 2), | |
72a155b4 | 4952 | 8, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4953 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
4954 | writebuf ? writebuf + 8 : writebuf, 0); |
4955 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4956 | } | |
6d82d43b AC |
4957 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
4958 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4959 | { | |
59aa1faa | 4960 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
4961 | if (mips_debug) |
4962 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 4963 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
4964 | (gdbarch_num_regs (gdbarch) |
4965 | + mips_regnum (gdbarch)->fp0), | |
6d82d43b | 4966 | TYPE_LENGTH (type), |
72a155b4 | 4967 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4968 | readbuf, writebuf, 0); |
6d82d43b AC |
4969 | return RETURN_VALUE_REGISTER_CONVENTION; |
4970 | } | |
4971 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4972 | && TYPE_NFIELDS (type) <= 2 | |
4973 | && TYPE_NFIELDS (type) >= 1 | |
4974 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 4975 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
4976 | == TYPE_CODE_FLT)) |
4977 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 4978 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 4979 | == TYPE_CODE_FLT) |
b18bb924 | 4980 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
5b68030f | 4981 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
4982 | { |
4983 | /* A struct that contains one or two floats. Each value is part | |
4984 | in the least significant part of their floating point | |
5b68030f | 4985 | register (or GPR, for soft float). */ |
6d82d43b AC |
4986 | int regnum; |
4987 | int field; | |
5b68030f JM |
4988 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
4989 | ? mips_regnum (gdbarch)->fp0 | |
4990 | : MIPS_V0_REGNUM); | |
6d82d43b AC |
4991 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
4992 | { | |
4993 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4994 | / TARGET_CHAR_BIT); | |
4995 | if (mips_debug) | |
4996 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
4997 | offset); | |
5b68030f JM |
4998 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
4999 | { | |
5000 | /* A 16-byte long double field goes in two consecutive | |
5001 | registers. */ | |
5002 | mips_xfer_register (gdbarch, regcache, | |
5003 | gdbarch_num_regs (gdbarch) + regnum, | |
5004 | 8, | |
5005 | gdbarch_byte_order (gdbarch), | |
5006 | readbuf, writebuf, offset); | |
5007 | mips_xfer_register (gdbarch, regcache, | |
5008 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
5009 | 8, | |
5010 | gdbarch_byte_order (gdbarch), | |
5011 | readbuf, writebuf, offset + 8); | |
5012 | } | |
5013 | else | |
5014 | mips_xfer_register (gdbarch, regcache, | |
5015 | gdbarch_num_regs (gdbarch) + regnum, | |
5016 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
5017 | gdbarch_byte_order (gdbarch), | |
5018 | readbuf, writebuf, offset); | |
6d82d43b AC |
5019 | } |
5020 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5021 | } | |
5022 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
f08877ba JB |
5023 | || TYPE_CODE (type) == TYPE_CODE_UNION |
5024 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
6d82d43b | 5025 | { |
f08877ba | 5026 | /* A composite type. Extract the left justified value, |
6d82d43b AC |
5027 | regardless of the byte order. I.e. DO NOT USE |
5028 | mips_xfer_lower. */ | |
5029 | int offset; | |
5030 | int regnum; | |
4c7d22cb | 5031 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5032 | offset < TYPE_LENGTH (type); |
72a155b4 | 5033 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5034 | { |
72a155b4 | 5035 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5036 | if (offset + xfer > TYPE_LENGTH (type)) |
5037 | xfer = TYPE_LENGTH (type) - offset; | |
5038 | if (mips_debug) | |
5039 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
5040 | offset, xfer, regnum); | |
ba32f989 DJ |
5041 | mips_xfer_register (gdbarch, regcache, |
5042 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
5043 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
5044 | offset); | |
6d82d43b AC |
5045 | } |
5046 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5047 | } | |
5048 | else | |
5049 | { | |
5050 | /* A scalar extract each part but least-significant-byte | |
5051 | justified. */ | |
5052 | int offset; | |
5053 | int regnum; | |
4c7d22cb | 5054 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5055 | offset < TYPE_LENGTH (type); |
72a155b4 | 5056 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5057 | { |
72a155b4 | 5058 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5059 | if (offset + xfer > TYPE_LENGTH (type)) |
5060 | xfer = TYPE_LENGTH (type) - offset; | |
5061 | if (mips_debug) | |
5062 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5063 | offset, xfer, regnum); | |
ba32f989 DJ |
5064 | mips_xfer_register (gdbarch, regcache, |
5065 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 5066 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5067 | readbuf, writebuf, offset); |
6d82d43b AC |
5068 | } |
5069 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5070 | } | |
5071 | } | |
5072 | ||
6a3a010b MR |
5073 | /* Which registers to use for passing floating-point values between |
5074 | function calls, one of floating-point, general and both kinds of | |
5075 | registers. O32 and O64 use different register kinds for standard | |
5076 | MIPS and MIPS16 code; to make the handling of cases where we may | |
5077 | not know what kind of code is being used (e.g. no debug information) | |
5078 | easier we sometimes use both kinds. */ | |
5079 | ||
5080 | enum mips_fval_reg | |
5081 | { | |
5082 | mips_fval_fpr, | |
5083 | mips_fval_gpr, | |
5084 | mips_fval_both | |
5085 | }; | |
5086 | ||
6d82d43b AC |
5087 | /* O32 ABI stuff. */ |
5088 | ||
5089 | static CORE_ADDR | |
7d9b040b | 5090 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5091 | struct regcache *regcache, CORE_ADDR bp_addr, |
5092 | int nargs, struct value **args, CORE_ADDR sp, | |
5093 | int struct_return, CORE_ADDR struct_addr) | |
5094 | { | |
5095 | int argreg; | |
5096 | int float_argreg; | |
5097 | int argnum; | |
5098 | int len = 0; | |
5099 | int stack_offset = 0; | |
5100 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
e17a4113 | 5101 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5102 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
5103 | |
5104 | /* For shared libraries, "t9" needs to point at the function | |
5105 | address. */ | |
4c7d22cb | 5106 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
5107 | |
5108 | /* Set the return address register to point to the entry point of | |
5109 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5110 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
5111 | |
5112 | /* First ensure that the stack and structure return address (if any) | |
5113 | are properly aligned. The stack has to be at least 64-bit | |
5114 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
5115 | aligned. For n32 and n64, stack frames need to be 128-bit |
5116 | aligned, so we round to this widest known alignment. */ | |
5117 | ||
5b03f266 AC |
5118 | sp = align_down (sp, 16); |
5119 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
5120 | |
5121 | /* Now make space on the stack for the args. */ | |
5122 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
5123 | { |
5124 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
5125 | int arglen = TYPE_LENGTH (arg_type); | |
5126 | ||
5127 | /* Align to double-word if necessary. */ | |
2afd3f0a | 5128 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 5129 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 5130 | /* Allocate space on the stack. */ |
1a69e1e4 | 5131 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 5132 | } |
5b03f266 | 5133 | sp -= align_up (len, 16); |
ebafbe83 MS |
5134 | |
5135 | if (mips_debug) | |
6d82d43b | 5136 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
5137 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
5138 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
5139 | |
5140 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5141 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5142 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 5143 | |
bcb0cc15 | 5144 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
5145 | if (struct_return) |
5146 | { | |
5147 | if (mips_debug) | |
5148 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
5149 | "mips_o32_push_dummy_call: " |
5150 | "struct_return reg=%d %s\n", | |
5af949e3 | 5151 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 5152 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5153 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
5154 | } |
5155 | ||
5156 | /* Now load as many as possible of the first arguments into | |
5157 | registers, and push the rest onto the stack. Loop thru args | |
5158 | from first to last. */ | |
5159 | for (argnum = 0; argnum < nargs; argnum++) | |
5160 | { | |
47a35522 | 5161 | const gdb_byte *val; |
ebafbe83 | 5162 | struct value *arg = args[argnum]; |
4991999e | 5163 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
5164 | int len = TYPE_LENGTH (arg_type); |
5165 | enum type_code typecode = TYPE_CODE (arg_type); | |
5166 | ||
5167 | if (mips_debug) | |
5168 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 5169 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
5170 | argnum + 1, len, (int) typecode); |
5171 | ||
47a35522 | 5172 | val = value_contents (arg); |
46cac009 AC |
5173 | |
5174 | /* 32-bit ABIs always start floating point arguments in an | |
5175 | even-numbered floating point register. Round the FP register | |
5176 | up before the check to see if there are any FP registers | |
6a3a010b MR |
5177 | left. O32 targets also pass the FP in the integer registers |
5178 | so also round up normal registers. */ | |
74ed0bb4 | 5179 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
5180 | { |
5181 | if ((float_argreg & 1)) | |
5182 | float_argreg++; | |
5183 | } | |
5184 | ||
5185 | /* Floating point arguments passed in registers have to be | |
6a3a010b MR |
5186 | treated specially. On 32-bit architectures, doubles are |
5187 | passed in register pairs; the even FP register gets the | |
5188 | low word, and the odd FP register gets the high word. | |
5189 | On O32, the first two floating point arguments are also | |
5190 | copied to general registers, following their memory order, | |
5191 | because MIPS16 functions don't use float registers for | |
5192 | arguments. This duplication of arguments in general | |
5193 | registers can't hurt non-MIPS16 functions, because those | |
5194 | registers are normally skipped. */ | |
46cac009 | 5195 | |
74ed0bb4 MD |
5196 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
5197 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 5198 | { |
8b07f6d8 | 5199 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 5200 | { |
6a3a010b MR |
5201 | int freg_offset = gdbarch_byte_order (gdbarch) |
5202 | == BFD_ENDIAN_BIG ? 1 : 0; | |
46cac009 AC |
5203 | unsigned long regval; |
5204 | ||
6a3a010b MR |
5205 | /* First word. */ |
5206 | regval = extract_unsigned_integer (val, 4, byte_order); | |
46cac009 AC |
5207 | if (mips_debug) |
5208 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
6a3a010b MR |
5209 | float_argreg + freg_offset, |
5210 | phex (regval, 4)); | |
025bb325 | 5211 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5212 | float_argreg++ + freg_offset, |
5213 | regval); | |
46cac009 AC |
5214 | if (mips_debug) |
5215 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5216 | argreg, phex (regval, 4)); | |
9c9acae0 | 5217 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 | 5218 | |
6a3a010b MR |
5219 | /* Second word. */ |
5220 | regval = extract_unsigned_integer (val + 4, 4, byte_order); | |
46cac009 AC |
5221 | if (mips_debug) |
5222 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
6a3a010b MR |
5223 | float_argreg - freg_offset, |
5224 | phex (regval, 4)); | |
025bb325 | 5225 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5226 | float_argreg++ - freg_offset, |
5227 | regval); | |
46cac009 AC |
5228 | if (mips_debug) |
5229 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5230 | argreg, phex (regval, 4)); | |
9c9acae0 | 5231 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5232 | } |
5233 | else | |
5234 | { | |
5235 | /* This is a floating point value that fits entirely | |
5236 | in a single register. */ | |
5237 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 5238 | above to ensure that it is even register aligned. */ |
e17a4113 | 5239 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
46cac009 AC |
5240 | if (mips_debug) |
5241 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5242 | float_argreg, phex (regval, len)); | |
025bb325 MS |
5243 | regcache_cooked_write_unsigned (regcache, |
5244 | float_argreg++, regval); | |
5b68030f JM |
5245 | /* Although two FP registers are reserved for each |
5246 | argument, only one corresponding integer register is | |
5247 | reserved. */ | |
46cac009 AC |
5248 | if (mips_debug) |
5249 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5250 | argreg, phex (regval, len)); | |
5b68030f | 5251 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5252 | } |
5253 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 5254 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
5255 | } |
5256 | else | |
5257 | { | |
5258 | /* Copy the argument to general registers or the stack in | |
5259 | register-sized pieces. Large arguments are split between | |
5260 | registers and stack. */ | |
1a69e1e4 DJ |
5261 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
5262 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
5263 | them in registers where gcc sometimes puts them on the |
5264 | stack. For maximum compatibility, we will put them in | |
5265 | both places. */ | |
1a69e1e4 DJ |
5266 | int odd_sized_struct = (len > MIPS32_REGSIZE |
5267 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
5268 | /* Structures should be aligned to eight bytes (even arg registers) |
5269 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 5270 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
5271 | { |
5272 | if ((argreg & 1)) | |
968b5391 MR |
5273 | { |
5274 | argreg++; | |
1a69e1e4 | 5275 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 5276 | } |
46cac009 | 5277 | } |
46cac009 AC |
5278 | while (len > 0) |
5279 | { | |
5280 | /* Remember if the argument was written to the stack. */ | |
5281 | int stack_used_p = 0; | |
1a69e1e4 | 5282 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
5283 | |
5284 | if (mips_debug) | |
5285 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
5286 | partial_len); | |
5287 | ||
5288 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 5289 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 5290 | || odd_sized_struct) |
46cac009 AC |
5291 | { |
5292 | /* Should shorter than int integer values be | |
025bb325 | 5293 | promoted to int before being stored? */ |
46cac009 AC |
5294 | int longword_offset = 0; |
5295 | CORE_ADDR addr; | |
5296 | stack_used_p = 1; | |
46cac009 AC |
5297 | |
5298 | if (mips_debug) | |
5299 | { | |
5af949e3 UW |
5300 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
5301 | paddress (gdbarch, stack_offset)); | |
5302 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
5303 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
5304 | } |
5305 | ||
5306 | addr = sp + stack_offset + longword_offset; | |
5307 | ||
5308 | if (mips_debug) | |
5309 | { | |
5310 | int i; | |
5af949e3 UW |
5311 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
5312 | paddress (gdbarch, addr)); | |
46cac009 AC |
5313 | for (i = 0; i < partial_len; i++) |
5314 | { | |
6d82d43b | 5315 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
5316 | val[i] & 0xff); |
5317 | } | |
5318 | } | |
5319 | write_memory (addr, val, partial_len); | |
5320 | } | |
5321 | ||
5322 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 5323 | structs may go thru BOTH paths. */ |
46cac009 | 5324 | /* Write this portion of the argument to a general |
6d82d43b | 5325 | purpose register. */ |
74ed0bb4 | 5326 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 | 5327 | { |
e17a4113 UW |
5328 | LONGEST regval = extract_signed_integer (val, partial_len, |
5329 | byte_order); | |
4246e332 | 5330 | /* Value may need to be sign extended, because |
1b13c4f6 | 5331 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
5332 | |
5333 | /* A non-floating-point argument being passed in a | |
5334 | general register. If a struct or union, and if | |
5335 | the remaining length is smaller than the register | |
5336 | size, we have to adjust the register value on | |
5337 | big endian targets. | |
5338 | ||
5339 | It does not seem to be necessary to do the | |
5340 | same for integral types. | |
5341 | ||
5342 | Also don't do this adjustment on O64 binaries. | |
5343 | ||
5344 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
5345 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
5346 | mips_abi_regsize(), generates a left shift |
5347 | as part of storing the argument in a register | |
5348 | (the left shift isn't generated when | |
1b13c4f6 | 5349 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
5350 | it is quite possible that this is GCC |
5351 | contradicting the LE/O32 ABI, GDB has not been | |
5352 | adjusted to accommodate this. Either someone | |
5353 | needs to demonstrate that the LE/O32 ABI | |
5354 | specifies such a left shift OR this new ABI gets | |
5355 | identified as such and GDB gets tweaked | |
5356 | accordingly. */ | |
5357 | ||
72a155b4 | 5358 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5359 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
5360 | && (typecode == TYPE_CODE_STRUCT |
5361 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5362 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 5363 | * TARGET_CHAR_BIT); |
46cac009 AC |
5364 | |
5365 | if (mips_debug) | |
5366 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
5367 | argreg, | |
1a69e1e4 | 5368 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 5369 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
5370 | argreg++; |
5371 | ||
5372 | /* Prevent subsequent floating point arguments from | |
5373 | being passed in floating point registers. */ | |
74ed0bb4 | 5374 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
5375 | } |
5376 | ||
5377 | len -= partial_len; | |
5378 | val += partial_len; | |
5379 | ||
b021a221 MS |
5380 | /* Compute the offset into the stack at which we will |
5381 | copy the next parameter. | |
46cac009 | 5382 | |
6d82d43b AC |
5383 | In older ABIs, the caller reserved space for |
5384 | registers that contained arguments. This was loosely | |
5385 | refered to as their "home". Consequently, space is | |
5386 | always allocated. */ | |
46cac009 | 5387 | |
1a69e1e4 | 5388 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
5389 | } |
5390 | } | |
5391 | if (mips_debug) | |
5392 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
5393 | } | |
5394 | ||
f10683bb | 5395 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5396 | |
46cac009 AC |
5397 | /* Return adjusted stack pointer. */ |
5398 | return sp; | |
5399 | } | |
5400 | ||
6d82d43b | 5401 | static enum return_value_convention |
6a3a010b | 5402 | mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 5403 | struct type *type, struct regcache *regcache, |
47a35522 | 5404 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 5405 | { |
6a3a010b | 5406 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 5407 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
72a155b4 | 5408 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6a3a010b | 5409 | enum mips_fval_reg fval_reg; |
6d82d43b | 5410 | |
6a3a010b | 5411 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
6d82d43b AC |
5412 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
5413 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
5414 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
5415 | return RETURN_VALUE_STRUCT_CONVENTION; | |
5416 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
5417 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5418 | { | |
6a3a010b MR |
5419 | /* A single-precision floating-point value. If reading in or copying, |
5420 | then we get it from/put it to FP0 for standard MIPS code or GPR2 | |
5421 | for MIPS16 code. If writing out only, then we put it to both FP0 | |
5422 | and GPR2. We do not support reading in with no function known, if | |
5423 | this safety check ever triggers, then we'll have to try harder. */ | |
5424 | gdb_assert (function || !readbuf); | |
6d82d43b | 5425 | if (mips_debug) |
6a3a010b MR |
5426 | switch (fval_reg) |
5427 | { | |
5428 | case mips_fval_fpr: | |
5429 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
5430 | break; | |
5431 | case mips_fval_gpr: | |
5432 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); | |
5433 | break; | |
5434 | case mips_fval_both: | |
5435 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); | |
5436 | break; | |
5437 | } | |
5438 | if (fval_reg != mips_fval_gpr) | |
5439 | mips_xfer_register (gdbarch, regcache, | |
5440 | (gdbarch_num_regs (gdbarch) | |
5441 | + mips_regnum (gdbarch)->fp0), | |
5442 | TYPE_LENGTH (type), | |
5443 | gdbarch_byte_order (gdbarch), | |
5444 | readbuf, writebuf, 0); | |
5445 | if (fval_reg != mips_fval_fpr) | |
5446 | mips_xfer_register (gdbarch, regcache, | |
5447 | gdbarch_num_regs (gdbarch) + 2, | |
5448 | TYPE_LENGTH (type), | |
5449 | gdbarch_byte_order (gdbarch), | |
5450 | readbuf, writebuf, 0); | |
6d82d43b AC |
5451 | return RETURN_VALUE_REGISTER_CONVENTION; |
5452 | } | |
5453 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
5454 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5455 | { | |
6a3a010b MR |
5456 | /* A double-precision floating-point value. If reading in or copying, |
5457 | then we get it from/put it to FP1 and FP0 for standard MIPS code or | |
5458 | GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it | |
5459 | to both FP1/FP0 and GPR2/GPR3. We do not support reading in with | |
5460 | no function known, if this safety check ever triggers, then we'll | |
5461 | have to try harder. */ | |
5462 | gdb_assert (function || !readbuf); | |
6d82d43b | 5463 | if (mips_debug) |
6a3a010b MR |
5464 | switch (fval_reg) |
5465 | { | |
5466 | case mips_fval_fpr: | |
5467 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
5468 | break; | |
5469 | case mips_fval_gpr: | |
5470 | fprintf_unfiltered (gdb_stderr, "Return float in $2/$3\n"); | |
5471 | break; | |
5472 | case mips_fval_both: | |
5473 | fprintf_unfiltered (gdb_stderr, | |
5474 | "Return float in $fp1/$fp0 and $2/$3\n"); | |
5475 | break; | |
5476 | } | |
5477 | if (fval_reg != mips_fval_gpr) | |
6d82d43b | 5478 | { |
6a3a010b MR |
5479 | /* The most significant part goes in FP1, and the least significant |
5480 | in FP0. */ | |
5481 | switch (gdbarch_byte_order (gdbarch)) | |
5482 | { | |
5483 | case BFD_ENDIAN_LITTLE: | |
5484 | mips_xfer_register (gdbarch, regcache, | |
5485 | (gdbarch_num_regs (gdbarch) | |
5486 | + mips_regnum (gdbarch)->fp0 + 0), | |
5487 | 4, gdbarch_byte_order (gdbarch), | |
5488 | readbuf, writebuf, 0); | |
5489 | mips_xfer_register (gdbarch, regcache, | |
5490 | (gdbarch_num_regs (gdbarch) | |
5491 | + mips_regnum (gdbarch)->fp0 + 1), | |
5492 | 4, gdbarch_byte_order (gdbarch), | |
5493 | readbuf, writebuf, 4); | |
5494 | break; | |
5495 | case BFD_ENDIAN_BIG: | |
5496 | mips_xfer_register (gdbarch, regcache, | |
5497 | (gdbarch_num_regs (gdbarch) | |
5498 | + mips_regnum (gdbarch)->fp0 + 1), | |
5499 | 4, gdbarch_byte_order (gdbarch), | |
5500 | readbuf, writebuf, 0); | |
5501 | mips_xfer_register (gdbarch, regcache, | |
5502 | (gdbarch_num_regs (gdbarch) | |
5503 | + mips_regnum (gdbarch)->fp0 + 0), | |
5504 | 4, gdbarch_byte_order (gdbarch), | |
5505 | readbuf, writebuf, 4); | |
5506 | break; | |
5507 | default: | |
5508 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
5509 | } | |
5510 | } | |
5511 | if (fval_reg != mips_fval_fpr) | |
5512 | { | |
5513 | /* The two 32-bit parts are always placed in GPR2 and GPR3 | |
5514 | following these registers' memory order. */ | |
ba32f989 | 5515 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5516 | gdbarch_num_regs (gdbarch) + 2, |
72a155b4 | 5517 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5518 | readbuf, writebuf, 0); |
ba32f989 | 5519 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5520 | gdbarch_num_regs (gdbarch) + 3, |
72a155b4 | 5521 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5522 | readbuf, writebuf, 4); |
6d82d43b AC |
5523 | } |
5524 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5525 | } | |
5526 | #if 0 | |
5527 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
5528 | && TYPE_NFIELDS (type) <= 2 | |
5529 | && TYPE_NFIELDS (type) >= 1 | |
5530 | && ((TYPE_NFIELDS (type) == 1 | |
5531 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
5532 | == TYPE_CODE_FLT)) | |
5533 | || (TYPE_NFIELDS (type) == 2 | |
5534 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
5535 | == TYPE_CODE_FLT) | |
5536 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
5537 | == TYPE_CODE_FLT))) | |
5538 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5539 | { | |
5540 | /* A struct that contains one or two floats. Each value is part | |
5541 | in the least significant part of their floating point | |
5542 | register.. */ | |
870cd05e | 5543 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
5544 | int regnum; |
5545 | int field; | |
72a155b4 | 5546 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
5547 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
5548 | { | |
5549 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
5550 | / TARGET_CHAR_BIT); | |
5551 | if (mips_debug) | |
5552 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
5553 | offset); | |
ba32f989 DJ |
5554 | mips_xfer_register (gdbarch, regcache, |
5555 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 5556 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 5557 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5558 | readbuf, writebuf, offset); |
6d82d43b AC |
5559 | } |
5560 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5561 | } | |
5562 | #endif | |
5563 | #if 0 | |
5564 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
5565 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
5566 | { | |
5567 | /* A structure or union. Extract the left justified value, | |
5568 | regardless of the byte order. I.e. DO NOT USE | |
5569 | mips_xfer_lower. */ | |
5570 | int offset; | |
5571 | int regnum; | |
4c7d22cb | 5572 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5573 | offset < TYPE_LENGTH (type); |
72a155b4 | 5574 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5575 | { |
72a155b4 | 5576 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
5577 | if (offset + xfer > TYPE_LENGTH (type)) |
5578 | xfer = TYPE_LENGTH (type) - offset; | |
5579 | if (mips_debug) | |
5580 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
5581 | offset, xfer, regnum); | |
ba32f989 DJ |
5582 | mips_xfer_register (gdbarch, regcache, |
5583 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
5584 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
5585 | } | |
5586 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5587 | } | |
5588 | #endif | |
5589 | else | |
5590 | { | |
5591 | /* A scalar extract each part but least-significant-byte | |
5592 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 5593 | the ISA. */ |
6d82d43b AC |
5594 | int offset; |
5595 | int regnum; | |
4c7d22cb | 5596 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 5597 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 5598 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 5599 | { |
1a69e1e4 | 5600 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
5601 | if (offset + xfer > TYPE_LENGTH (type)) |
5602 | xfer = TYPE_LENGTH (type) - offset; | |
5603 | if (mips_debug) | |
5604 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5605 | offset, xfer, regnum); | |
ba32f989 DJ |
5606 | mips_xfer_register (gdbarch, regcache, |
5607 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 5608 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5609 | readbuf, writebuf, offset); |
6d82d43b AC |
5610 | } |
5611 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5612 | } | |
5613 | } | |
5614 | ||
5615 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
5616 | ABI. */ | |
46cac009 AC |
5617 | |
5618 | static CORE_ADDR | |
7d9b040b | 5619 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5620 | struct regcache *regcache, CORE_ADDR bp_addr, |
5621 | int nargs, | |
5622 | struct value **args, CORE_ADDR sp, | |
5623 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
5624 | { |
5625 | int argreg; | |
5626 | int float_argreg; | |
5627 | int argnum; | |
5628 | int len = 0; | |
5629 | int stack_offset = 0; | |
480d3dd2 | 5630 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 5631 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5632 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 5633 | |
25ab4790 AC |
5634 | /* For shared libraries, "t9" needs to point at the function |
5635 | address. */ | |
4c7d22cb | 5636 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
5637 | |
5638 | /* Set the return address register to point to the entry point of | |
5639 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5640 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 5641 | |
46cac009 AC |
5642 | /* First ensure that the stack and structure return address (if any) |
5643 | are properly aligned. The stack has to be at least 64-bit | |
5644 | aligned even on 32-bit machines, because doubles must be 64-bit | |
5645 | aligned. For n32 and n64, stack frames need to be 128-bit | |
5646 | aligned, so we round to this widest known alignment. */ | |
5647 | ||
5b03f266 AC |
5648 | sp = align_down (sp, 16); |
5649 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
5650 | |
5651 | /* Now make space on the stack for the args. */ | |
5652 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
5653 | { |
5654 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
5655 | int arglen = TYPE_LENGTH (arg_type); | |
5656 | ||
968b5391 | 5657 | /* Allocate space on the stack. */ |
1a69e1e4 | 5658 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 5659 | } |
5b03f266 | 5660 | sp -= align_up (len, 16); |
46cac009 AC |
5661 | |
5662 | if (mips_debug) | |
6d82d43b | 5663 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
5664 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
5665 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
46cac009 AC |
5666 | |
5667 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5668 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5669 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
5670 | |
5671 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
5672 | if (struct_return) | |
5673 | { | |
5674 | if (mips_debug) | |
5675 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
5676 | "mips_o64_push_dummy_call: " |
5677 | "struct_return reg=%d %s\n", | |
5af949e3 | 5678 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 5679 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5680 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
5681 | } |
5682 | ||
5683 | /* Now load as many as possible of the first arguments into | |
5684 | registers, and push the rest onto the stack. Loop thru args | |
5685 | from first to last. */ | |
5686 | for (argnum = 0; argnum < nargs; argnum++) | |
5687 | { | |
47a35522 | 5688 | const gdb_byte *val; |
930bd0e0 | 5689 | gdb_byte valbuf[MAX_REGISTER_SIZE]; |
46cac009 | 5690 | struct value *arg = args[argnum]; |
4991999e | 5691 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
5692 | int len = TYPE_LENGTH (arg_type); |
5693 | enum type_code typecode = TYPE_CODE (arg_type); | |
5694 | ||
5695 | if (mips_debug) | |
5696 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 5697 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
5698 | argnum + 1, len, (int) typecode); |
5699 | ||
47a35522 | 5700 | val = value_contents (arg); |
ebafbe83 | 5701 | |
930bd0e0 KB |
5702 | /* Function pointer arguments to mips16 code need to be made into |
5703 | mips16 pointers. */ | |
5704 | if (typecode == TYPE_CODE_PTR | |
5705 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
5706 | { | |
5707 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
5708 | len, byte_order); | |
4cc0665f | 5709 | if (!mips_pc_is_mips (addr)) |
930bd0e0 KB |
5710 | { |
5711 | store_signed_integer (valbuf, len, byte_order, | |
4cc0665f | 5712 | make_compact_addr (addr)); |
930bd0e0 KB |
5713 | val = valbuf; |
5714 | } | |
5715 | } | |
5716 | ||
ebafbe83 | 5717 | /* Floating point arguments passed in registers have to be |
6a3a010b MR |
5718 | treated specially. On 32-bit architectures, doubles are |
5719 | passed in register pairs; the even FP register gets the | |
5720 | low word, and the odd FP register gets the high word. | |
5721 | On O64, the first two floating point arguments are also | |
5722 | copied to general registers, because MIPS16 functions | |
5723 | don't use float registers for arguments. This duplication | |
5724 | of arguments in general registers can't hurt non-MIPS16 | |
5725 | functions because those registers are normally skipped. */ | |
ebafbe83 | 5726 | |
74ed0bb4 MD |
5727 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
5728 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 5729 | { |
e17a4113 | 5730 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
2afd3f0a MR |
5731 | if (mips_debug) |
5732 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5733 | float_argreg, phex (regval, len)); | |
9c9acae0 | 5734 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
5735 | if (mips_debug) |
5736 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5737 | argreg, phex (regval, len)); | |
9c9acae0 | 5738 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 5739 | argreg++; |
ebafbe83 | 5740 | /* Reserve space for the FP register. */ |
1a69e1e4 | 5741 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
5742 | } |
5743 | else | |
5744 | { | |
5745 | /* Copy the argument to general registers or the stack in | |
5746 | register-sized pieces. Large arguments are split between | |
5747 | registers and stack. */ | |
1a69e1e4 | 5748 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
5749 | are treated specially: Irix cc passes them in registers |
5750 | where gcc sometimes puts them on the stack. For maximum | |
5751 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
5752 | int odd_sized_struct = (len > MIPS64_REGSIZE |
5753 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
5754 | while (len > 0) |
5755 | { | |
5756 | /* Remember if the argument was written to the stack. */ | |
5757 | int stack_used_p = 0; | |
1a69e1e4 | 5758 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
5759 | |
5760 | if (mips_debug) | |
5761 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
5762 | partial_len); | |
5763 | ||
5764 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 5765 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 5766 | || odd_sized_struct) |
ebafbe83 MS |
5767 | { |
5768 | /* Should shorter than int integer values be | |
025bb325 | 5769 | promoted to int before being stored? */ |
ebafbe83 MS |
5770 | int longword_offset = 0; |
5771 | CORE_ADDR addr; | |
5772 | stack_used_p = 1; | |
72a155b4 | 5773 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 5774 | { |
1a69e1e4 DJ |
5775 | if ((typecode == TYPE_CODE_INT |
5776 | || typecode == TYPE_CODE_PTR | |
5777 | || typecode == TYPE_CODE_FLT) | |
5778 | && len <= 4) | |
5779 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
5780 | } |
5781 | ||
5782 | if (mips_debug) | |
5783 | { | |
5af949e3 UW |
5784 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
5785 | paddress (gdbarch, stack_offset)); | |
5786 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
5787 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
5788 | } |
5789 | ||
5790 | addr = sp + stack_offset + longword_offset; | |
5791 | ||
5792 | if (mips_debug) | |
5793 | { | |
5794 | int i; | |
5af949e3 UW |
5795 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
5796 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
5797 | for (i = 0; i < partial_len; i++) |
5798 | { | |
6d82d43b | 5799 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
5800 | val[i] & 0xff); |
5801 | } | |
5802 | } | |
5803 | write_memory (addr, val, partial_len); | |
5804 | } | |
5805 | ||
5806 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 5807 | structs may go thru BOTH paths. */ |
ebafbe83 | 5808 | /* Write this portion of the argument to a general |
6d82d43b | 5809 | purpose register. */ |
74ed0bb4 | 5810 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 | 5811 | { |
e17a4113 UW |
5812 | LONGEST regval = extract_signed_integer (val, partial_len, |
5813 | byte_order); | |
4246e332 | 5814 | /* Value may need to be sign extended, because |
1b13c4f6 | 5815 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
5816 | |
5817 | /* A non-floating-point argument being passed in a | |
5818 | general register. If a struct or union, and if | |
5819 | the remaining length is smaller than the register | |
5820 | size, we have to adjust the register value on | |
5821 | big endian targets. | |
5822 | ||
5823 | It does not seem to be necessary to do the | |
025bb325 | 5824 | same for integral types. */ |
480d3dd2 | 5825 | |
72a155b4 | 5826 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5827 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
5828 | && (typecode == TYPE_CODE_STRUCT |
5829 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5830 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 5831 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
5832 | |
5833 | if (mips_debug) | |
5834 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
5835 | argreg, | |
1a69e1e4 | 5836 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 5837 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
5838 | argreg++; |
5839 | ||
5840 | /* Prevent subsequent floating point arguments from | |
5841 | being passed in floating point registers. */ | |
74ed0bb4 | 5842 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
5843 | } |
5844 | ||
5845 | len -= partial_len; | |
5846 | val += partial_len; | |
5847 | ||
b021a221 MS |
5848 | /* Compute the offset into the stack at which we will |
5849 | copy the next parameter. | |
ebafbe83 | 5850 | |
6d82d43b AC |
5851 | In older ABIs, the caller reserved space for |
5852 | registers that contained arguments. This was loosely | |
5853 | refered to as their "home". Consequently, space is | |
5854 | always allocated. */ | |
ebafbe83 | 5855 | |
1a69e1e4 | 5856 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
5857 | } |
5858 | } | |
5859 | if (mips_debug) | |
5860 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
5861 | } | |
5862 | ||
f10683bb | 5863 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5864 | |
ebafbe83 MS |
5865 | /* Return adjusted stack pointer. */ |
5866 | return sp; | |
5867 | } | |
5868 | ||
9c8fdbfa | 5869 | static enum return_value_convention |
6a3a010b | 5870 | mips_o64_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 5871 | struct type *type, struct regcache *regcache, |
47a35522 | 5872 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 5873 | { |
6a3a010b | 5874 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 5875 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
72a155b4 | 5876 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6a3a010b | 5877 | enum mips_fval_reg fval_reg; |
7a076fd2 | 5878 | |
6a3a010b | 5879 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
7a076fd2 FF |
5880 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
5881 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
5882 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
5883 | return RETURN_VALUE_STRUCT_CONVENTION; | |
74ed0bb4 | 5884 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
7a076fd2 | 5885 | { |
6a3a010b MR |
5886 | /* A floating-point value. If reading in or copying, then we get it |
5887 | from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code. | |
5888 | If writing out only, then we put it to both FP0 and GPR2. We do | |
5889 | not support reading in with no function known, if this safety | |
5890 | check ever triggers, then we'll have to try harder. */ | |
5891 | gdb_assert (function || !readbuf); | |
7a076fd2 | 5892 | if (mips_debug) |
6a3a010b MR |
5893 | switch (fval_reg) |
5894 | { | |
5895 | case mips_fval_fpr: | |
5896 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
5897 | break; | |
5898 | case mips_fval_gpr: | |
5899 | fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); | |
5900 | break; | |
5901 | case mips_fval_both: | |
5902 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); | |
5903 | break; | |
5904 | } | |
5905 | if (fval_reg != mips_fval_gpr) | |
5906 | mips_xfer_register (gdbarch, regcache, | |
5907 | (gdbarch_num_regs (gdbarch) | |
5908 | + mips_regnum (gdbarch)->fp0), | |
5909 | TYPE_LENGTH (type), | |
5910 | gdbarch_byte_order (gdbarch), | |
5911 | readbuf, writebuf, 0); | |
5912 | if (fval_reg != mips_fval_fpr) | |
5913 | mips_xfer_register (gdbarch, regcache, | |
5914 | gdbarch_num_regs (gdbarch) + 2, | |
5915 | TYPE_LENGTH (type), | |
5916 | gdbarch_byte_order (gdbarch), | |
5917 | readbuf, writebuf, 0); | |
7a076fd2 FF |
5918 | return RETURN_VALUE_REGISTER_CONVENTION; |
5919 | } | |
5920 | else | |
5921 | { | |
5922 | /* A scalar extract each part but least-significant-byte | |
025bb325 | 5923 | justified. */ |
7a076fd2 FF |
5924 | int offset; |
5925 | int regnum; | |
5926 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
5927 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 5928 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 5929 | { |
1a69e1e4 | 5930 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
5931 | if (offset + xfer > TYPE_LENGTH (type)) |
5932 | xfer = TYPE_LENGTH (type) - offset; | |
5933 | if (mips_debug) | |
5934 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
5935 | offset, xfer, regnum); | |
ba32f989 DJ |
5936 | mips_xfer_register (gdbarch, regcache, |
5937 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 5938 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5939 | readbuf, writebuf, offset); |
7a076fd2 FF |
5940 | } |
5941 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5942 | } | |
6d82d43b AC |
5943 | } |
5944 | ||
dd824b04 DJ |
5945 | /* Floating point register management. |
5946 | ||
5947 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
5948 | 64bit operations, these early MIPS cpus treat fp register pairs | |
5949 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
5950 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
5951 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
5952 | double precision floats into two 32-bit chunks and store them in | |
5953 | consecutive fp regs. To display 64-bit floats stored in this | |
5954 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
5955 | Throw in user-configurable endianness and you have a real mess. | |
5956 | ||
5957 | The way this works is: | |
5958 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
5959 | double-precision value will be split across two logical registers. | |
5960 | The lower-numbered logical register will hold the low-order bits, | |
5961 | regardless of the processor's endianness. | |
5962 | - If we are on a 64-bit processor, and we are looking for a | |
5963 | single-precision value, it will be in the low ordered bits | |
5964 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
5965 | save slot in memory. | |
5966 | - If we are in 64-bit mode, everything is straightforward. | |
5967 | ||
5968 | Note that this code only deals with "live" registers at the top of the | |
5969 | stack. We will attempt to deal with saved registers later, when | |
025bb325 | 5970 | the raw/cooked register interface is in place. (We need a general |
dd824b04 DJ |
5971 | interface that can deal with dynamic saved register sizes -- fp |
5972 | regs could be 32 bits wide in one frame and 64 on the frame above | |
5973 | and below). */ | |
5974 | ||
5975 | /* Copy a 32-bit single-precision value from the current frame | |
5976 | into rare_buffer. */ | |
5977 | ||
5978 | static void | |
e11c53d2 | 5979 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 5980 | gdb_byte *rare_buffer) |
dd824b04 | 5981 | { |
72a155b4 UW |
5982 | struct gdbarch *gdbarch = get_frame_arch (frame); |
5983 | int raw_size = register_size (gdbarch, regno); | |
47a35522 | 5984 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 5985 | |
e11c53d2 | 5986 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 5987 | error (_("can't read register %d (%s)"), |
72a155b4 | 5988 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
5989 | if (raw_size == 8) |
5990 | { | |
5991 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 5992 | 32 bits. */ |
dd824b04 DJ |
5993 | int offset; |
5994 | ||
72a155b4 | 5995 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
5996 | offset = 4; |
5997 | else | |
5998 | offset = 0; | |
5999 | ||
6000 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
6001 | } | |
6002 | else | |
6003 | { | |
6004 | memcpy (rare_buffer, raw_buffer, 4); | |
6005 | } | |
6006 | } | |
6007 | ||
6008 | /* Copy a 64-bit double-precision value from the current frame into | |
6009 | rare_buffer. This may include getting half of it from the next | |
6010 | register. */ | |
6011 | ||
6012 | static void | |
e11c53d2 | 6013 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 6014 | gdb_byte *rare_buffer) |
dd824b04 | 6015 | { |
72a155b4 UW |
6016 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6017 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 6018 | |
9c9acae0 | 6019 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
6020 | { |
6021 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 6022 | all 64 bits. */ |
e11c53d2 | 6023 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 6024 | error (_("can't read register %d (%s)"), |
72a155b4 | 6025 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
6026 | } |
6027 | else | |
6028 | { | |
72a155b4 | 6029 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 6030 | |
72a155b4 | 6031 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 6032 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
6033 | _("mips_read_fp_register_double: bad access to " |
6034 | "odd-numbered FP register")); | |
dd824b04 DJ |
6035 | |
6036 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 6037 | each register. */ |
72a155b4 | 6038 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 6039 | { |
e11c53d2 AC |
6040 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
6041 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 6042 | } |
361d1df0 | 6043 | else |
dd824b04 | 6044 | { |
e11c53d2 AC |
6045 | mips_read_fp_register_single (frame, regno, rare_buffer); |
6046 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
6047 | } |
6048 | } | |
6049 | } | |
6050 | ||
c906108c | 6051 | static void |
e11c53d2 AC |
6052 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
6053 | int regnum) | |
025bb325 | 6054 | { /* Do values for FP (float) regs. */ |
72a155b4 | 6055 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 6056 | gdb_byte *raw_buffer; |
025bb325 | 6057 | double doub, flt1; /* Doubles extracted from raw hex data. */ |
3903d437 | 6058 | int inv1, inv2; |
c5aa993b | 6059 | |
025bb325 MS |
6060 | raw_buffer = alloca (2 * register_size (gdbarch, |
6061 | mips_regnum (gdbarch)->fp0)); | |
c906108c | 6062 | |
72a155b4 | 6063 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 6064 | fprintf_filtered (file, "%*s", |
72a155b4 | 6065 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 6066 | ""); |
f0ef6b29 | 6067 | |
72a155b4 | 6068 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 6069 | { |
79a45b7d TT |
6070 | struct value_print_options opts; |
6071 | ||
f0ef6b29 KB |
6072 | /* 4-byte registers: Print hex and floating. Also print even |
6073 | numbered registers as doubles. */ | |
e11c53d2 | 6074 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
025bb325 MS |
6075 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
6076 | raw_buffer, &inv1); | |
c5aa993b | 6077 | |
79a45b7d | 6078 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6079 | print_scalar_formatted (raw_buffer, |
6080 | builtin_type (gdbarch)->builtin_uint32, | |
6081 | &opts, 'w', file); | |
dd824b04 | 6082 | |
e11c53d2 | 6083 | fprintf_filtered (file, " flt: "); |
1adad886 | 6084 | if (inv1) |
e11c53d2 | 6085 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 6086 | else |
e11c53d2 | 6087 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 6088 | |
72a155b4 | 6089 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 6090 | { |
e11c53d2 | 6091 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
6092 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
6093 | raw_buffer, &inv2); | |
1adad886 | 6094 | |
e11c53d2 | 6095 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 6096 | if (inv2) |
e11c53d2 | 6097 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 6098 | else |
e11c53d2 | 6099 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 6100 | } |
c906108c SS |
6101 | } |
6102 | else | |
dd824b04 | 6103 | { |
79a45b7d TT |
6104 | struct value_print_options opts; |
6105 | ||
f0ef6b29 | 6106 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 6107 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 UW |
6108 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
6109 | raw_buffer, &inv1); | |
c906108c | 6110 | |
e11c53d2 | 6111 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
6112 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
6113 | raw_buffer, &inv2); | |
f0ef6b29 | 6114 | |
79a45b7d | 6115 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6116 | print_scalar_formatted (raw_buffer, |
6117 | builtin_type (gdbarch)->builtin_uint64, | |
6118 | &opts, 'g', file); | |
f0ef6b29 | 6119 | |
e11c53d2 | 6120 | fprintf_filtered (file, " flt: "); |
1adad886 | 6121 | if (inv1) |
e11c53d2 | 6122 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 6123 | else |
e11c53d2 | 6124 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 6125 | |
e11c53d2 | 6126 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 6127 | if (inv2) |
e11c53d2 | 6128 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 6129 | else |
e11c53d2 | 6130 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
6131 | } |
6132 | } | |
6133 | ||
6134 | static void | |
e11c53d2 | 6135 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 6136 | int regnum) |
f0ef6b29 | 6137 | { |
a4b8ebc8 | 6138 | struct gdbarch *gdbarch = get_frame_arch (frame); |
79a45b7d | 6139 | struct value_print_options opts; |
de15c4ab | 6140 | struct value *val; |
1adad886 | 6141 | |
004159a2 | 6142 | if (mips_float_register_p (gdbarch, regnum)) |
f0ef6b29 | 6143 | { |
e11c53d2 | 6144 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
6145 | return; |
6146 | } | |
6147 | ||
de15c4ab PA |
6148 | val = get_frame_register_value (frame, regnum); |
6149 | if (value_optimized_out (val)) | |
f0ef6b29 | 6150 | { |
c9f4d572 | 6151 | fprintf_filtered (file, "%s: [Invalid]", |
72a155b4 | 6152 | gdbarch_register_name (gdbarch, regnum)); |
f0ef6b29 | 6153 | return; |
c906108c | 6154 | } |
f0ef6b29 | 6155 | |
72a155b4 | 6156 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
6157 | |
6158 | /* The problem with printing numeric register names (r26, etc.) is that | |
6159 | the user can't use them on input. Probably the best solution is to | |
6160 | fix it so that either the numeric or the funky (a2, etc.) names | |
6161 | are accepted on input. */ | |
6162 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 6163 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 6164 | else |
e11c53d2 | 6165 | fprintf_filtered (file, ": "); |
f0ef6b29 | 6166 | |
79a45b7d | 6167 | get_formatted_print_options (&opts, 'x'); |
de15c4ab PA |
6168 | val_print_scalar_formatted (value_type (val), |
6169 | value_contents_for_printing (val), | |
6170 | value_embedded_offset (val), | |
6171 | val, | |
6172 | &opts, 0, file); | |
c906108c SS |
6173 | } |
6174 | ||
f0ef6b29 KB |
6175 | /* Replacement for generic do_registers_info. |
6176 | Print regs in pretty columns. */ | |
6177 | ||
6178 | static int | |
e11c53d2 AC |
6179 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
6180 | int regnum) | |
f0ef6b29 | 6181 | { |
e11c53d2 AC |
6182 | fprintf_filtered (file, " "); |
6183 | mips_print_fp_register (file, frame, regnum); | |
6184 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
6185 | return regnum + 1; |
6186 | } | |
6187 | ||
6188 | ||
025bb325 | 6189 | /* Print a row's worth of GP (int) registers, with name labels above. */ |
c906108c SS |
6190 | |
6191 | static int | |
e11c53d2 | 6192 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 6193 | int start_regnum) |
c906108c | 6194 | { |
a4b8ebc8 | 6195 | struct gdbarch *gdbarch = get_frame_arch (frame); |
025bb325 | 6196 | /* Do values for GP (int) regs. */ |
47a35522 | 6197 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
025bb325 MS |
6198 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols |
6199 | per row. */ | |
c906108c | 6200 | int col, byte; |
a4b8ebc8 | 6201 | int regnum; |
c906108c | 6202 | |
025bb325 | 6203 | /* For GP registers, we print a separate row of names above the vals. */ |
a4b8ebc8 | 6204 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
6205 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
6206 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 6207 | regnum++) |
c906108c | 6208 | { |
72a155b4 | 6209 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6210 | continue; /* unused register */ |
004159a2 | 6211 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6212 | break; /* End the row: reached FP register. */ |
0cc93a06 | 6213 | /* Large registers are handled separately. */ |
72a155b4 | 6214 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6215 | { |
6216 | if (col > 0) | |
6217 | break; /* End the row before this register. */ | |
6218 | ||
6219 | /* Print this register on a row by itself. */ | |
6220 | mips_print_register (file, frame, regnum); | |
6221 | fprintf_filtered (file, "\n"); | |
6222 | return regnum + 1; | |
6223 | } | |
d05f6826 DJ |
6224 | if (col == 0) |
6225 | fprintf_filtered (file, " "); | |
6d82d43b | 6226 | fprintf_filtered (file, |
72a155b4 UW |
6227 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
6228 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
6229 | col++; |
6230 | } | |
d05f6826 DJ |
6231 | |
6232 | if (col == 0) | |
6233 | return regnum; | |
6234 | ||
025bb325 | 6235 | /* Print the R0 to R31 names. */ |
72a155b4 | 6236 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 6237 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 6238 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
6239 | else |
6240 | fprintf_filtered (file, "\n "); | |
c906108c | 6241 | |
025bb325 | 6242 | /* Now print the values in hex, 4 or 8 to the row. */ |
a4b8ebc8 | 6243 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
6244 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
6245 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 6246 | regnum++) |
c906108c | 6247 | { |
72a155b4 | 6248 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6249 | continue; /* unused register */ |
004159a2 | 6250 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6251 | break; /* End row: reached FP register. */ |
72a155b4 | 6252 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6253 | break; /* End row: large register. */ |
6254 | ||
c906108c | 6255 | /* OK: get the data in raw format. */ |
e11c53d2 | 6256 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 | 6257 | error (_("can't read register %d (%s)"), |
72a155b4 | 6258 | regnum, gdbarch_register_name (gdbarch, regnum)); |
c906108c | 6259 | /* pad small registers */ |
4246e332 | 6260 | for (byte = 0; |
72a155b4 UW |
6261 | byte < (mips_abi_regsize (gdbarch) |
6262 | - register_size (gdbarch, regnum)); byte++) | |
c906108c | 6263 | printf_filtered (" "); |
025bb325 | 6264 | /* Now print the register value in hex, endian order. */ |
72a155b4 | 6265 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 6266 | for (byte = |
72a155b4 UW |
6267 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
6268 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 6269 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 6270 | else |
72a155b4 | 6271 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 6272 | byte >= 0; byte--) |
47a35522 | 6273 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 6274 | fprintf_filtered (file, " "); |
c906108c SS |
6275 | col++; |
6276 | } | |
025bb325 | 6277 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 6278 | fprintf_filtered (file, "\n"); |
c906108c SS |
6279 | |
6280 | return regnum; | |
6281 | } | |
6282 | ||
025bb325 | 6283 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ |
c906108c | 6284 | |
bf1f5b4c | 6285 | static void |
e11c53d2 AC |
6286 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
6287 | struct frame_info *frame, int regnum, int all) | |
c906108c | 6288 | { |
025bb325 | 6289 | if (regnum != -1) /* Do one specified register. */ |
c906108c | 6290 | { |
72a155b4 UW |
6291 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
6292 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 6293 | error (_("Not a valid register for the current processor type")); |
c906108c | 6294 | |
0cc93a06 | 6295 | mips_print_register (file, frame, regnum); |
e11c53d2 | 6296 | fprintf_filtered (file, "\n"); |
c906108c | 6297 | } |
c5aa993b | 6298 | else |
025bb325 | 6299 | /* Do all (or most) registers. */ |
c906108c | 6300 | { |
72a155b4 UW |
6301 | regnum = gdbarch_num_regs (gdbarch); |
6302 | while (regnum < gdbarch_num_regs (gdbarch) | |
6303 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 6304 | { |
004159a2 | 6305 | if (mips_float_register_p (gdbarch, regnum)) |
e11c53d2 | 6306 | { |
025bb325 | 6307 | if (all) /* True for "INFO ALL-REGISTERS" command. */ |
e11c53d2 AC |
6308 | regnum = print_fp_register_row (file, frame, regnum); |
6309 | else | |
025bb325 | 6310 | regnum += MIPS_NUMREGS; /* Skip floating point regs. */ |
e11c53d2 | 6311 | } |
c906108c | 6312 | else |
e11c53d2 | 6313 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
6314 | } |
6315 | } | |
6316 | } | |
6317 | ||
63807e1d | 6318 | static int |
3352ef37 AC |
6319 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
6320 | struct frame_info *frame) | |
c906108c | 6321 | { |
e17a4113 | 6322 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3352ef37 | 6323 | CORE_ADDR pc = get_frame_pc (frame); |
4cc0665f MR |
6324 | struct address_space *aspace; |
6325 | enum mips_isa isa; | |
6326 | ULONGEST insn; | |
6327 | int status; | |
6328 | int size; | |
6329 | ||
6330 | if ((mips_pc_is_mips (pc) | |
6331 | && !mips32_instruction_has_delay_slot (gdbarch, pc)) | |
6332 | || (mips_pc_is_micromips (gdbarch, pc) | |
6333 | && !micromips_instruction_has_delay_slot (gdbarch, pc, 0)) | |
6334 | || (mips_pc_is_mips16 (gdbarch, pc) | |
6335 | && !mips16_instruction_has_delay_slot (gdbarch, pc, 0))) | |
06648491 MK |
6336 | return 0; |
6337 | ||
4cc0665f MR |
6338 | isa = mips_pc_isa (gdbarch, pc); |
6339 | /* _has_delay_slot above will have validated the read. */ | |
6340 | insn = mips_fetch_instruction (gdbarch, isa, pc, NULL); | |
6341 | size = mips_insn_size (isa, insn); | |
6342 | aspace = get_frame_address_space (frame); | |
6343 | return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here; | |
c906108c SS |
6344 | } |
6345 | ||
6d82d43b AC |
6346 | /* To skip prologues, I use this predicate. Returns either PC itself |
6347 | if the code at PC does not look like a function prologue; otherwise | |
6348 | returns an address that (if we're lucky) follows the prologue. If | |
6349 | LENIENT, then we must skip everything which is involved in setting | |
6350 | up the frame (it's OK to skip more, just so long as we don't skip | |
6351 | anything which might clobber the registers which are being saved. | |
6352 | We must skip more in the case where part of the prologue is in the | |
6353 | delay slot of a non-prologue instruction). */ | |
6354 | ||
6355 | static CORE_ADDR | |
6093d2eb | 6356 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 6357 | { |
8b622e6a AC |
6358 | CORE_ADDR limit_pc; |
6359 | CORE_ADDR func_addr; | |
6360 | ||
6d82d43b AC |
6361 | /* See if we can determine the end of the prologue via the symbol table. |
6362 | If so, then return either PC, or the PC after the prologue, whichever | |
6363 | is greater. */ | |
8b622e6a AC |
6364 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
6365 | { | |
d80b854b UW |
6366 | CORE_ADDR post_prologue_pc |
6367 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a AC |
6368 | if (post_prologue_pc != 0) |
6369 | return max (pc, post_prologue_pc); | |
6370 | } | |
6d82d43b AC |
6371 | |
6372 | /* Can't determine prologue from the symbol table, need to examine | |
6373 | instructions. */ | |
6374 | ||
98b4dd94 JB |
6375 | /* Find an upper limit on the function prologue using the debug |
6376 | information. If the debug information could not be used to provide | |
6377 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 6378 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
6379 | if (limit_pc == 0) |
6380 | limit_pc = pc + 100; /* Magic. */ | |
6381 | ||
4cc0665f | 6382 | if (mips_pc_is_mips16 (gdbarch, pc)) |
e17a4113 | 6383 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
4cc0665f MR |
6384 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6385 | return micromips_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); | |
6d82d43b | 6386 | else |
e17a4113 | 6387 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
88658117 AC |
6388 | } |
6389 | ||
97ab0fdd MR |
6390 | /* Check whether the PC is in a function epilogue (32-bit version). |
6391 | This is a helper function for mips_in_function_epilogue_p. */ | |
6392 | static int | |
e17a4113 | 6393 | mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6394 | { |
6395 | CORE_ADDR func_addr = 0, func_end = 0; | |
6396 | ||
6397 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6398 | { | |
6399 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6400 | CORE_ADDR addr = func_end - 12; | |
6401 | ||
6402 | if (addr < func_addr + 4) | |
6403 | addr = func_addr + 4; | |
6404 | if (pc < addr) | |
6405 | return 0; | |
6406 | ||
6407 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
6408 | { | |
6409 | unsigned long high_word; | |
6410 | unsigned long inst; | |
6411 | ||
4cc0665f | 6412 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
97ab0fdd MR |
6413 | high_word = (inst >> 16) & 0xffff; |
6414 | ||
6415 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
6416 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
6417 | && inst != 0x03e00008 /* jr $ra */ | |
6418 | && inst != 0x00000000) /* nop */ | |
6419 | return 0; | |
6420 | } | |
6421 | ||
6422 | return 1; | |
6423 | } | |
6424 | ||
6425 | return 0; | |
6426 | } | |
6427 | ||
4cc0665f MR |
6428 | /* Check whether the PC is in a function epilogue (microMIPS version). |
6429 | This is a helper function for mips_in_function_epilogue_p. */ | |
6430 | ||
6431 | static int | |
6432 | micromips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
6433 | { | |
6434 | CORE_ADDR func_addr = 0; | |
6435 | CORE_ADDR func_end = 0; | |
6436 | CORE_ADDR addr; | |
6437 | ULONGEST insn; | |
6438 | long offset; | |
6439 | int dreg; | |
6440 | int sreg; | |
6441 | int loc; | |
6442 | ||
6443 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6444 | return 0; | |
6445 | ||
6446 | /* The microMIPS epilogue is max. 12 bytes long. */ | |
6447 | addr = func_end - 12; | |
6448 | ||
6449 | if (addr < func_addr + 2) | |
6450 | addr = func_addr + 2; | |
6451 | if (pc < addr) | |
6452 | return 0; | |
6453 | ||
6454 | for (; pc < func_end; pc += loc) | |
6455 | { | |
6456 | loc = 0; | |
6457 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
6458 | loc += MIPS_INSN16_SIZE; | |
6459 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
6460 | { | |
6461 | /* 48-bit instructions. */ | |
6462 | case 3 * MIPS_INSN16_SIZE: | |
6463 | /* No epilogue instructions in this category. */ | |
6464 | return 0; | |
6465 | ||
6466 | /* 32-bit instructions. */ | |
6467 | case 2 * MIPS_INSN16_SIZE: | |
6468 | insn <<= 16; | |
6469 | insn |= mips_fetch_instruction (gdbarch, | |
6470 | ISA_MICROMIPS, pc + loc, NULL); | |
6471 | loc += MIPS_INSN16_SIZE; | |
6472 | switch (micromips_op (insn >> 16)) | |
6473 | { | |
6474 | case 0xc: /* ADDIU: bits 001100 */ | |
6475 | case 0x17: /* DADDIU: bits 010111 */ | |
6476 | sreg = b0s5_reg (insn >> 16); | |
6477 | dreg = b5s5_reg (insn >> 16); | |
6478 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
6479 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
6480 | /* (D)ADDIU $sp, imm */ | |
6481 | && offset >= 0) | |
6482 | break; | |
6483 | return 0; | |
6484 | ||
6485 | default: | |
6486 | return 0; | |
6487 | } | |
6488 | break; | |
6489 | ||
6490 | /* 16-bit instructions. */ | |
6491 | case MIPS_INSN16_SIZE: | |
6492 | switch (micromips_op (insn)) | |
6493 | { | |
6494 | case 0x3: /* MOVE: bits 000011 */ | |
6495 | sreg = b0s5_reg (insn); | |
6496 | dreg = b5s5_reg (insn); | |
6497 | if (sreg == 0 && dreg == 0) | |
6498 | /* MOVE $zero, $zero aka NOP */ | |
6499 | break; | |
6500 | return 0; | |
6501 | ||
6502 | case 0x11: /* POOL16C: bits 010001 */ | |
6503 | if (b5s5_op (insn) == 0x18 | |
6504 | /* JRADDIUSP: bits 010011 11000 */ | |
6505 | || (b5s5_op (insn) == 0xd | |
6506 | /* JRC: bits 010011 01101 */ | |
6507 | && b0s5_reg (insn) == MIPS_RA_REGNUM)) | |
6508 | /* JRC $ra */ | |
6509 | break; | |
6510 | return 0; | |
6511 | ||
6512 | case 0x13: /* POOL16D: bits 010011 */ | |
6513 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
6514 | if ((insn & 0x1) == 0x1 | |
6515 | /* ADDIUSP: bits 010011 1 */ | |
6516 | && offset > 0) | |
6517 | break; | |
6518 | return 0; | |
6519 | ||
6520 | default: | |
6521 | return 0; | |
6522 | } | |
6523 | } | |
6524 | } | |
6525 | ||
6526 | return 1; | |
6527 | } | |
6528 | ||
97ab0fdd MR |
6529 | /* Check whether the PC is in a function epilogue (16-bit version). |
6530 | This is a helper function for mips_in_function_epilogue_p. */ | |
6531 | static int | |
e17a4113 | 6532 | mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6533 | { |
6534 | CORE_ADDR func_addr = 0, func_end = 0; | |
6535 | ||
6536 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6537 | { | |
6538 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6539 | CORE_ADDR addr = func_end - 12; | |
6540 | ||
6541 | if (addr < func_addr + 4) | |
6542 | addr = func_addr + 4; | |
6543 | if (pc < addr) | |
6544 | return 0; | |
6545 | ||
6546 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
6547 | { | |
6548 | unsigned short inst; | |
6549 | ||
4cc0665f | 6550 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL); |
97ab0fdd MR |
6551 | |
6552 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
6553 | continue; | |
6554 | ||
6555 | if (inst != 0x6300 /* addiu $sp,offset */ | |
6556 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
6557 | && inst != 0xe820 /* jr $ra */ | |
6558 | && inst != 0xe8a0 /* jrc $ra */ | |
6559 | && inst != 0x6500) /* nop */ | |
6560 | return 0; | |
6561 | } | |
6562 | ||
6563 | return 1; | |
6564 | } | |
6565 | ||
6566 | return 0; | |
6567 | } | |
6568 | ||
6569 | /* The epilogue is defined here as the area at the end of a function, | |
6570 | after an instruction which destroys the function's stack frame. */ | |
6571 | static int | |
6572 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
6573 | { | |
4cc0665f | 6574 | if (mips_pc_is_mips16 (gdbarch, pc)) |
e17a4113 | 6575 | return mips16_in_function_epilogue_p (gdbarch, pc); |
4cc0665f MR |
6576 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6577 | return micromips_in_function_epilogue_p (gdbarch, pc); | |
97ab0fdd | 6578 | else |
e17a4113 | 6579 | return mips32_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd MR |
6580 | } |
6581 | ||
025bb325 | 6582 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
a5ea2558 AC |
6583 | used for all MIPS-specific commands. */ |
6584 | ||
a5ea2558 | 6585 | static void |
acdb74a0 | 6586 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
6587 | { |
6588 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
6589 | } | |
6590 | ||
a5ea2558 | 6591 | static void |
acdb74a0 | 6592 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 6593 | { |
6d82d43b AC |
6594 | printf_unfiltered |
6595 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
6596 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
6597 | } | |
6598 | ||
c906108c SS |
6599 | /* Commands to show/set the MIPS FPU type. */ |
6600 | ||
c906108c | 6601 | static void |
acdb74a0 | 6602 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 6603 | { |
c906108c | 6604 | char *fpu; |
6ca0852e | 6605 | |
1cf3db46 | 6606 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
6ca0852e UW |
6607 | { |
6608 | printf_unfiltered | |
6609 | ("The MIPS floating-point coprocessor is unknown " | |
6610 | "because the current architecture is not MIPS.\n"); | |
6611 | return; | |
6612 | } | |
6613 | ||
1cf3db46 | 6614 | switch (MIPS_FPU_TYPE (target_gdbarch)) |
c906108c SS |
6615 | { |
6616 | case MIPS_FPU_SINGLE: | |
6617 | fpu = "single-precision"; | |
6618 | break; | |
6619 | case MIPS_FPU_DOUBLE: | |
6620 | fpu = "double-precision"; | |
6621 | break; | |
6622 | case MIPS_FPU_NONE: | |
6623 | fpu = "absent (none)"; | |
6624 | break; | |
93d56215 | 6625 | default: |
e2e0b3e5 | 6626 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
6627 | } |
6628 | if (mips_fpu_type_auto) | |
025bb325 MS |
6629 | printf_unfiltered ("The MIPS floating-point coprocessor " |
6630 | "is set automatically (currently %s)\n", | |
6631 | fpu); | |
c906108c | 6632 | else |
6d82d43b AC |
6633 | printf_unfiltered |
6634 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
6635 | } |
6636 | ||
6637 | ||
c906108c | 6638 | static void |
acdb74a0 | 6639 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 6640 | { |
025bb325 MS |
6641 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", " |
6642 | "\"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
6643 | show_mipsfpu_command (args, from_tty); |
6644 | } | |
6645 | ||
c906108c | 6646 | static void |
acdb74a0 | 6647 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 6648 | { |
8d5838b5 AC |
6649 | struct gdbarch_info info; |
6650 | gdbarch_info_init (&info); | |
c906108c SS |
6651 | mips_fpu_type = MIPS_FPU_SINGLE; |
6652 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6653 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6654 | instead of relying on globals. Doing that would let generic code | |
6655 | handle the search for this specific architecture. */ | |
6656 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6657 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6658 | } |
6659 | ||
c906108c | 6660 | static void |
acdb74a0 | 6661 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 6662 | { |
8d5838b5 AC |
6663 | struct gdbarch_info info; |
6664 | gdbarch_info_init (&info); | |
c906108c SS |
6665 | mips_fpu_type = MIPS_FPU_DOUBLE; |
6666 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6667 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6668 | instead of relying on globals. Doing that would let generic code | |
6669 | handle the search for this specific architecture. */ | |
6670 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6671 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6672 | } |
6673 | ||
c906108c | 6674 | static void |
acdb74a0 | 6675 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 6676 | { |
8d5838b5 AC |
6677 | struct gdbarch_info info; |
6678 | gdbarch_info_init (&info); | |
c906108c SS |
6679 | mips_fpu_type = MIPS_FPU_NONE; |
6680 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6681 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6682 | instead of relying on globals. Doing that would let generic code | |
6683 | handle the search for this specific architecture. */ | |
6684 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 6685 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
6686 | } |
6687 | ||
c906108c | 6688 | static void |
acdb74a0 | 6689 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
6690 | { |
6691 | mips_fpu_type_auto = 1; | |
6692 | } | |
6693 | ||
c906108c | 6694 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
6695 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
6696 | the relevant processor still exists (it dates back to '94) and | |
6697 | secondly this is not the way to do this. The processor type should | |
6698 | be set by forcing an architecture change. */ | |
c906108c | 6699 | |
691c0433 AC |
6700 | void |
6701 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 6702 | { |
bb486190 UW |
6703 | struct regcache *regcache = get_current_regcache (); |
6704 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
6705 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
a9614958 | 6706 | ULONGEST prid; |
c906108c | 6707 | |
bb486190 | 6708 | regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid); |
c906108c | 6709 | if ((prid & ~0xf) == 0x700) |
691c0433 | 6710 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
6711 | } |
6712 | ||
6713 | /* Just like reinit_frame_cache, but with the right arguments to be | |
6714 | callable as an sfunc. */ | |
6715 | ||
6716 | static void | |
acdb74a0 AC |
6717 | reinit_frame_cache_sfunc (char *args, int from_tty, |
6718 | struct cmd_list_element *c) | |
c906108c SS |
6719 | { |
6720 | reinit_frame_cache (); | |
6721 | } | |
6722 | ||
a89aa300 AC |
6723 | static int |
6724 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 6725 | { |
4cc0665f MR |
6726 | struct gdbarch *gdbarch = info->application_data; |
6727 | ||
d31431ed AC |
6728 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
6729 | disassembler needs to be able to locally determine the ISA, and | |
6730 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
6731 | work. */ | |
4cc0665f | 6732 | if (mips_pc_is_mips16 (gdbarch, memaddr)) |
ec4045ea | 6733 | info->mach = bfd_mach_mips16; |
4cc0665f MR |
6734 | else if (mips_pc_is_micromips (gdbarch, memaddr)) |
6735 | info->mach = bfd_mach_mips_micromips; | |
c906108c SS |
6736 | |
6737 | /* Round down the instruction address to the appropriate boundary. */ | |
4cc0665f MR |
6738 | memaddr &= (info->mach == bfd_mach_mips16 |
6739 | || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3; | |
c5aa993b | 6740 | |
e5ab0dce | 6741 | /* Set the disassembler options. */ |
9dae60cc | 6742 | if (!info->disassembler_options) |
e5ab0dce AC |
6743 | /* This string is not recognized explicitly by the disassembler, |
6744 | but it tells the disassembler to not try to guess the ABI from | |
6745 | the bfd elf headers, such that, if the user overrides the ABI | |
6746 | of a program linked as NewABI, the disassembly will follow the | |
6747 | register naming conventions specified by the user. */ | |
6748 | info->disassembler_options = "gpr-names=32"; | |
6749 | ||
c906108c | 6750 | /* Call the appropriate disassembler based on the target endian-ness. */ |
40887e1a | 6751 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
6752 | return print_insn_big_mips (memaddr, info); |
6753 | else | |
6754 | return print_insn_little_mips (memaddr, info); | |
6755 | } | |
6756 | ||
9dae60cc UW |
6757 | static int |
6758 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) | |
6759 | { | |
6760 | /* Set up the disassembler info, so that we get the right | |
6761 | register names from libopcodes. */ | |
6762 | info->disassembler_options = "gpr-names=n32"; | |
6763 | info->flavour = bfd_target_elf_flavour; | |
6764 | ||
6765 | return gdb_print_insn_mips (memaddr, info); | |
6766 | } | |
6767 | ||
6768 | static int | |
6769 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) | |
6770 | { | |
6771 | /* Set up the disassembler info, so that we get the right | |
6772 | register names from libopcodes. */ | |
6773 | info->disassembler_options = "gpr-names=64"; | |
6774 | info->flavour = bfd_target_elf_flavour; | |
6775 | ||
6776 | return gdb_print_insn_mips (memaddr, info); | |
6777 | } | |
6778 | ||
025bb325 MS |
6779 | /* This function implements gdbarch_breakpoint_from_pc. It uses the |
6780 | program counter value to determine whether a 16- or 32-bit breakpoint | |
6781 | should be used. It returns a pointer to a string of bytes that encode a | |
6782 | breakpoint instruction, stores the length of the string to *lenptr, and | |
6783 | adjusts pc (if necessary) to point to the actual memory location where | |
6784 | the breakpoint should be inserted. */ | |
c906108c | 6785 | |
47a35522 | 6786 | static const gdb_byte * |
025bb325 MS |
6787 | mips_breakpoint_from_pc (struct gdbarch *gdbarch, |
6788 | CORE_ADDR *pcptr, int *lenptr) | |
c906108c | 6789 | { |
4cc0665f MR |
6790 | CORE_ADDR pc = *pcptr; |
6791 | ||
67d57894 | 6792 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 6793 | { |
4cc0665f | 6794 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c906108c | 6795 | { |
47a35522 | 6796 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
4cc0665f | 6797 | *pcptr = unmake_compact_addr (pc); |
c5aa993b | 6798 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
6799 | return mips16_big_breakpoint; |
6800 | } | |
4cc0665f MR |
6801 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6802 | { | |
6803 | static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 }; | |
6804 | static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 }; | |
6805 | ULONGEST insn; | |
6806 | int status; | |
6807 | int size; | |
6808 | ||
6809 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); | |
6810 | size = status ? 2 | |
6811 | : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4; | |
6812 | *pcptr = unmake_compact_addr (pc); | |
6813 | *lenptr = size; | |
6814 | return (size == 2) ? micromips16_big_breakpoint | |
6815 | : micromips32_big_breakpoint; | |
6816 | } | |
c906108c SS |
6817 | else |
6818 | { | |
aaab4dba AC |
6819 | /* The IDT board uses an unusual breakpoint value, and |
6820 | sometimes gets confused when it sees the usual MIPS | |
6821 | breakpoint instruction. */ | |
47a35522 MK |
6822 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
6823 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
6824 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
f2ec0ecf | 6825 | /* Likewise, IRIX appears to expect a different breakpoint, |
025bb325 | 6826 | although this is not apparent until you try to use pthreads. */ |
f2ec0ecf | 6827 | static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd }; |
c906108c | 6828 | |
c5aa993b | 6829 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
6830 | |
6831 | if (strcmp (target_shortname, "mips") == 0) | |
6832 | return idt_big_breakpoint; | |
6833 | else if (strcmp (target_shortname, "ddb") == 0 | |
6834 | || strcmp (target_shortname, "pmon") == 0 | |
6835 | || strcmp (target_shortname, "lsi") == 0) | |
6836 | return pmon_big_breakpoint; | |
f2ec0ecf JB |
6837 | else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX) |
6838 | return irix_big_breakpoint; | |
c906108c SS |
6839 | else |
6840 | return big_breakpoint; | |
6841 | } | |
6842 | } | |
6843 | else | |
6844 | { | |
4cc0665f | 6845 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c906108c | 6846 | { |
47a35522 | 6847 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
4cc0665f | 6848 | *pcptr = unmake_compact_addr (pc); |
c5aa993b | 6849 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
6850 | return mips16_little_breakpoint; |
6851 | } | |
4cc0665f MR |
6852 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6853 | { | |
6854 | static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 }; | |
6855 | static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 }; | |
6856 | ULONGEST insn; | |
6857 | int status; | |
6858 | int size; | |
6859 | ||
6860 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); | |
6861 | size = status ? 2 | |
6862 | : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4; | |
6863 | *pcptr = unmake_compact_addr (pc); | |
6864 | *lenptr = size; | |
6865 | return (size == 2) ? micromips16_little_breakpoint | |
6866 | : micromips32_little_breakpoint; | |
6867 | } | |
c906108c SS |
6868 | else |
6869 | { | |
47a35522 MK |
6870 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
6871 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
6872 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 6873 | |
c5aa993b | 6874 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
6875 | |
6876 | if (strcmp (target_shortname, "mips") == 0) | |
6877 | return idt_little_breakpoint; | |
6878 | else if (strcmp (target_shortname, "ddb") == 0 | |
6879 | || strcmp (target_shortname, "pmon") == 0 | |
6880 | || strcmp (target_shortname, "lsi") == 0) | |
6881 | return pmon_little_breakpoint; | |
6882 | else | |
6883 | return little_breakpoint; | |
6884 | } | |
6885 | } | |
6886 | } | |
6887 | ||
4cc0665f MR |
6888 | /* Determine the remote breakpoint kind suitable for the PC. The following |
6889 | kinds are used: | |
6890 | ||
6891 | * 2 -- 16-bit MIPS16 mode breakpoint, | |
6892 | ||
6893 | * 3 -- 16-bit microMIPS mode breakpoint, | |
6894 | ||
6895 | * 4 -- 32-bit standard MIPS mode breakpoint, | |
6896 | ||
6897 | * 5 -- 32-bit microMIPS mode breakpoint. */ | |
6898 | ||
6899 | static void | |
6900 | mips_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, | |
6901 | int *kindptr) | |
6902 | { | |
6903 | CORE_ADDR pc = *pcptr; | |
6904 | ||
6905 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
6906 | { | |
6907 | *pcptr = unmake_compact_addr (pc); | |
6908 | *kindptr = 2; | |
6909 | } | |
6910 | else if (mips_pc_is_micromips (gdbarch, pc)) | |
6911 | { | |
6912 | ULONGEST insn; | |
6913 | int status; | |
6914 | int size; | |
6915 | ||
6916 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); | |
6917 | size = status ? 2 : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4; | |
6918 | *pcptr = unmake_compact_addr (pc); | |
6919 | *kindptr = size | 1; | |
6920 | } | |
6921 | else | |
6922 | *kindptr = 4; | |
6923 | } | |
6924 | ||
c8cef75f MR |
6925 | /* Return non-zero if the ADDR instruction has a branch delay slot |
6926 | (i.e. it is a jump or branch instruction). This function is based | |
6927 | on mips32_next_pc. */ | |
6928 | ||
6929 | static int | |
6930 | mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr) | |
6931 | { | |
c8cef75f MR |
6932 | unsigned long inst; |
6933 | int status; | |
6934 | int op; | |
a385295e MR |
6935 | int rs; |
6936 | int rt; | |
c8cef75f | 6937 | |
4cc0665f | 6938 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status); |
c8cef75f MR |
6939 | if (status) |
6940 | return 0; | |
6941 | ||
c8cef75f MR |
6942 | op = itype_op (inst); |
6943 | if ((inst & 0xe0000000) != 0) | |
a385295e MR |
6944 | { |
6945 | rs = itype_rs (inst); | |
6946 | rt = itype_rt (inst); | |
6947 | return (op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
6948 | || op == 29 /* JALX: bits 011101 */ | |
6949 | || (op == 17 | |
6950 | && (rs == 8 | |
c8cef75f | 6951 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e MR |
6952 | || (rs == 9 && (rt & 0x2) == 0) |
6953 | /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ | |
6954 | || (rs == 10 && (rt & 0x2) == 0)))); | |
6955 | /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ | |
6956 | } | |
c8cef75f MR |
6957 | else |
6958 | switch (op & 0x07) /* extract bits 28,27,26 */ | |
6959 | { | |
6960 | case 0: /* SPECIAL */ | |
6961 | op = rtype_funct (inst); | |
6962 | return (op == 8 /* JR */ | |
6963 | || op == 9); /* JALR */ | |
6964 | break; /* end SPECIAL */ | |
6965 | case 1: /* REGIMM */ | |
a385295e MR |
6966 | rs = itype_rs (inst); |
6967 | rt = itype_rt (inst); /* branch condition */ | |
6968 | return ((rt & 0xc) == 0 | |
c8cef75f MR |
6969 | /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */ |
6970 | /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */ | |
a385295e MR |
6971 | || ((rt & 0x1e) == 0x1c && rs == 0)); |
6972 | /* BPOSGE32, BPOSGE64: bits 1110x */ | |
c8cef75f MR |
6973 | break; /* end REGIMM */ |
6974 | default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ | |
6975 | return 1; | |
6976 | break; | |
6977 | } | |
6978 | } | |
6979 | ||
6980 | /* Return non-zero if the ADDR instruction, which must be a 32-bit | |
6981 | instruction if MUSTBE32 is set or can be any instruction otherwise, | |
6982 | has a branch delay slot (i.e. it is a non-compact jump instruction). */ | |
6983 | ||
4cc0665f MR |
6984 | static int |
6985 | micromips_instruction_has_delay_slot (struct gdbarch *gdbarch, | |
6986 | CORE_ADDR addr, int mustbe32) | |
6987 | { | |
6988 | ULONGEST insn; | |
6989 | int status; | |
6990 | ||
6991 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); | |
6992 | if (status) | |
6993 | return 0; | |
6994 | ||
6995 | if (!mustbe32) /* 16-bit instructions. */ | |
6996 | return (micromips_op (insn) == 0x11 | |
6997 | /* POOL16C: bits 010001 */ | |
6998 | && (b5s5_op (insn) == 0xc | |
6999 | /* JR16: bits 010001 01100 */ | |
7000 | || (b5s5_op (insn) & 0x1e) == 0xe)) | |
7001 | /* JALR16, JALRS16: bits 010001 0111x */ | |
7002 | || (micromips_op (insn) & 0x37) == 0x23 | |
7003 | /* BEQZ16, BNEZ16: bits 10x011 */ | |
7004 | || micromips_op (insn) == 0x33; | |
7005 | /* B16: bits 110011 */ | |
7006 | ||
7007 | /* 32-bit instructions. */ | |
7008 | if (micromips_op (insn) == 0x0) | |
7009 | /* POOL32A: bits 000000 */ | |
7010 | { | |
7011 | insn <<= 16; | |
7012 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); | |
7013 | if (status) | |
7014 | return 0; | |
7015 | return b0s6_op (insn) == 0x3c | |
7016 | /* POOL32Axf: bits 000000 ... 111100 */ | |
7017 | && (b6s10_ext (insn) & 0x2bf) == 0x3c; | |
7018 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
7019 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
7020 | } | |
7021 | ||
7022 | return (micromips_op (insn) == 0x10 | |
7023 | /* POOL32I: bits 010000 */ | |
7024 | && ((b5s5_op (insn) & 0x1c) == 0x0 | |
7025 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ | |
7026 | || (b5s5_op (insn) & 0x1d) == 0x4 | |
7027 | /* BLEZ, BGTZ: bits 010000 001x0 */ | |
7028 | || (b5s5_op (insn) & 0x1d) == 0x11 | |
7029 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ | |
7030 | || ((b5s5_op (insn) & 0x1e) == 0x14 | |
7031 | && (insn & 0x3) == 0x0) | |
7032 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ | |
7033 | || (b5s5_op (insn) & 0x1e) == 0x1a | |
7034 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ | |
7035 | || ((b5s5_op (insn) & 0x1e) == 0x1c | |
7036 | && (insn & 0x3) == 0x0) | |
7037 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ | |
7038 | || ((b5s5_op (insn) & 0x1c) == 0x1c | |
7039 | && (insn & 0x3) == 0x1))) | |
7040 | /* BC1ANY*: bits 010000 111xx xxx01 */ | |
7041 | || (micromips_op (insn) & 0x1f) == 0x1d | |
7042 | /* JALS, JAL: bits x11101 */ | |
7043 | || (micromips_op (insn) & 0x37) == 0x25 | |
7044 | /* BEQ, BNE: bits 10x101 */ | |
7045 | || micromips_op (insn) == 0x35 | |
7046 | /* J: bits 110101 */ | |
7047 | || micromips_op (insn) == 0x3c; | |
7048 | /* JALX: bits 111100 */ | |
7049 | } | |
7050 | ||
c8cef75f MR |
7051 | static int |
7052 | mips16_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr, | |
7053 | int mustbe32) | |
7054 | { | |
c8cef75f MR |
7055 | unsigned short inst; |
7056 | int status; | |
7057 | ||
4cc0665f | 7058 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, addr, &status); |
c8cef75f MR |
7059 | if (status) |
7060 | return 0; | |
7061 | ||
c8cef75f MR |
7062 | if (!mustbe32) |
7063 | return (inst & 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */ | |
7064 | return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */ | |
7065 | } | |
7066 | ||
7067 | /* Calculate the starting address of the MIPS memory segment BPADDR is in. | |
7068 | This assumes KSSEG exists. */ | |
7069 | ||
7070 | static CORE_ADDR | |
7071 | mips_segment_boundary (CORE_ADDR bpaddr) | |
7072 | { | |
7073 | CORE_ADDR mask = CORE_ADDR_MAX; | |
7074 | int segsize; | |
7075 | ||
7076 | if (sizeof (CORE_ADDR) == 8) | |
7077 | /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid | |
7078 | a compiler warning produced where CORE_ADDR is a 32-bit type even | |
7079 | though in that case this is dead code). */ | |
7080 | switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3) | |
7081 | { | |
7082 | case 3: | |
7083 | if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr) | |
7084 | segsize = 29; /* 32-bit compatibility segment */ | |
7085 | else | |
7086 | segsize = 62; /* xkseg */ | |
7087 | break; | |
7088 | case 2: /* xkphys */ | |
7089 | segsize = 59; | |
7090 | break; | |
7091 | default: /* xksseg (1), xkuseg/kuseg (0) */ | |
7092 | segsize = 62; | |
7093 | break; | |
7094 | } | |
7095 | else if (bpaddr & 0x80000000) /* kernel segment */ | |
7096 | segsize = 29; | |
7097 | else | |
7098 | segsize = 31; /* user segment */ | |
7099 | mask <<= segsize; | |
7100 | return bpaddr & mask; | |
7101 | } | |
7102 | ||
7103 | /* Move the breakpoint at BPADDR out of any branch delay slot by shifting | |
7104 | it backwards if necessary. Return the address of the new location. */ | |
7105 | ||
7106 | static CORE_ADDR | |
7107 | mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
7108 | { | |
22e048c9 | 7109 | CORE_ADDR prev_addr; |
c8cef75f MR |
7110 | CORE_ADDR boundary; |
7111 | CORE_ADDR func_addr; | |
7112 | ||
7113 | /* If a breakpoint is set on the instruction in a branch delay slot, | |
7114 | GDB gets confused. When the breakpoint is hit, the PC isn't on | |
7115 | the instruction in the branch delay slot, the PC will point to | |
7116 | the branch instruction. Since the PC doesn't match any known | |
7117 | breakpoints, GDB reports a trap exception. | |
7118 | ||
7119 | There are two possible fixes for this problem. | |
7120 | ||
7121 | 1) When the breakpoint gets hit, see if the BD bit is set in the | |
7122 | Cause register (which indicates the last exception occurred in a | |
7123 | branch delay slot). If the BD bit is set, fix the PC to point to | |
7124 | the instruction in the branch delay slot. | |
7125 | ||
7126 | 2) When the user sets the breakpoint, don't allow him to set the | |
7127 | breakpoint on the instruction in the branch delay slot. Instead | |
7128 | move the breakpoint to the branch instruction (which will have | |
7129 | the same result). | |
7130 | ||
7131 | The problem with the first solution is that if the user then | |
7132 | single-steps the processor, the branch instruction will get | |
7133 | skipped (since GDB thinks the PC is on the instruction in the | |
7134 | branch delay slot). | |
7135 | ||
7136 | So, we'll use the second solution. To do this we need to know if | |
7137 | the instruction we're trying to set the breakpoint on is in the | |
7138 | branch delay slot. */ | |
7139 | ||
7140 | boundary = mips_segment_boundary (bpaddr); | |
7141 | ||
7142 | /* Make sure we don't scan back before the beginning of the current | |
7143 | function, since we may fetch constant data or insns that look like | |
7144 | a jump. Of course we might do that anyway if the compiler has | |
7145 | moved constants inline. :-( */ | |
7146 | if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL) | |
7147 | && func_addr > boundary && func_addr <= bpaddr) | |
7148 | boundary = func_addr; | |
7149 | ||
4cc0665f | 7150 | if (mips_pc_is_mips (bpaddr)) |
c8cef75f MR |
7151 | { |
7152 | if (bpaddr == boundary) | |
7153 | return bpaddr; | |
7154 | ||
7155 | /* If the previous instruction has a branch delay slot, we have | |
7156 | to move the breakpoint to the branch instruction. */ | |
7157 | prev_addr = bpaddr - 4; | |
7158 | if (mips32_instruction_has_delay_slot (gdbarch, prev_addr)) | |
7159 | bpaddr = prev_addr; | |
7160 | } | |
7161 | else | |
7162 | { | |
4cc0665f | 7163 | int (*instruction_has_delay_slot) (struct gdbarch *, CORE_ADDR, int); |
c8cef75f MR |
7164 | CORE_ADDR addr, jmpaddr; |
7165 | int i; | |
7166 | ||
4cc0665f | 7167 | boundary = unmake_compact_addr (boundary); |
c8cef75f MR |
7168 | |
7169 | /* The only MIPS16 instructions with delay slots are JAL, JALX, | |
7170 | JALR and JR. An absolute JAL/JALX is always 4 bytes long, | |
7171 | so try for that first, then try the 2 byte JALR/JR. | |
4cc0665f MR |
7172 | The microMIPS ASE has a whole range of jumps and branches |
7173 | with delay slots, some of which take 4 bytes and some take | |
7174 | 2 bytes, so the idea is the same. | |
c8cef75f MR |
7175 | FIXME: We have to assume that bpaddr is not the second half |
7176 | of an extended instruction. */ | |
4cc0665f MR |
7177 | instruction_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr) |
7178 | ? micromips_instruction_has_delay_slot | |
7179 | : mips16_instruction_has_delay_slot); | |
c8cef75f MR |
7180 | |
7181 | jmpaddr = 0; | |
7182 | addr = bpaddr; | |
7183 | for (i = 1; i < 4; i++) | |
7184 | { | |
4cc0665f | 7185 | if (unmake_compact_addr (addr) == boundary) |
c8cef75f | 7186 | break; |
4cc0665f MR |
7187 | addr -= MIPS_INSN16_SIZE; |
7188 | if (i == 1 && instruction_has_delay_slot (gdbarch, addr, 0)) | |
c8cef75f MR |
7189 | /* Looks like a JR/JALR at [target-1], but it could be |
7190 | the second word of a previous JAL/JALX, so record it | |
7191 | and check back one more. */ | |
7192 | jmpaddr = addr; | |
4cc0665f | 7193 | else if (i > 1 && instruction_has_delay_slot (gdbarch, addr, 1)) |
c8cef75f MR |
7194 | { |
7195 | if (i == 2) | |
7196 | /* Looks like a JAL/JALX at [target-2], but it could also | |
7197 | be the second word of a previous JAL/JALX, record it, | |
7198 | and check back one more. */ | |
7199 | jmpaddr = addr; | |
7200 | else | |
7201 | /* Looks like a JAL/JALX at [target-3], so any previously | |
7202 | recorded JAL/JALX or JR/JALR must be wrong, because: | |
7203 | ||
7204 | >-3: JAL | |
7205 | -2: JAL-ext (can't be JAL/JALX) | |
7206 | -1: bdslot (can't be JR/JALR) | |
7207 | 0: target insn | |
7208 | ||
7209 | Of course it could be another JAL-ext which looks | |
7210 | like a JAL, but in that case we'd have broken out | |
7211 | of this loop at [target-2]: | |
7212 | ||
7213 | -4: JAL | |
7214 | >-3: JAL-ext | |
7215 | -2: bdslot (can't be jmp) | |
7216 | -1: JR/JALR | |
7217 | 0: target insn */ | |
7218 | jmpaddr = 0; | |
7219 | } | |
7220 | else | |
7221 | { | |
7222 | /* Not a jump instruction: if we're at [target-1] this | |
7223 | could be the second word of a JAL/JALX, so continue; | |
7224 | otherwise we're done. */ | |
7225 | if (i > 1) | |
7226 | break; | |
7227 | } | |
7228 | } | |
7229 | ||
7230 | if (jmpaddr) | |
7231 | bpaddr = jmpaddr; | |
7232 | } | |
7233 | ||
7234 | return bpaddr; | |
7235 | } | |
7236 | ||
14132e89 MR |
7237 | /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16 |
7238 | call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */ | |
7239 | ||
7240 | static int | |
7241 | mips_is_stub_suffix (const char *suffix, int zero) | |
7242 | { | |
7243 | switch (suffix[0]) | |
7244 | { | |
7245 | case '0': | |
7246 | return zero && suffix[1] == '\0'; | |
7247 | case '1': | |
7248 | return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0'); | |
7249 | case '2': | |
7250 | case '5': | |
7251 | case '6': | |
7252 | case '9': | |
7253 | return suffix[1] == '\0'; | |
7254 | default: | |
7255 | return 0; | |
7256 | } | |
7257 | } | |
7258 | ||
7259 | /* Return non-zero if MODE is one of the mode infixes used for MIPS16 | |
7260 | call stubs, one of sf, df, sc, or dc. */ | |
7261 | ||
7262 | static int | |
7263 | mips_is_stub_mode (const char *mode) | |
7264 | { | |
7265 | return ((mode[0] == 's' || mode[0] == 'd') | |
7266 | && (mode[1] == 'f' || mode[1] == 'c')); | |
7267 | } | |
7268 | ||
7269 | /* Code at PC is a compiler-generated stub. Such a stub for a function | |
7270 | bar might have a name like __fn_stub_bar, and might look like this: | |
7271 | ||
7272 | mfc1 $4, $f13 | |
7273 | mfc1 $5, $f12 | |
7274 | mfc1 $6, $f15 | |
7275 | mfc1 $7, $f14 | |
7276 | ||
7277 | followed by (or interspersed with): | |
7278 | ||
7279 | j bar | |
7280 | ||
7281 | or: | |
7282 | ||
7283 | lui $25, %hi(bar) | |
7284 | addiu $25, $25, %lo(bar) | |
7285 | jr $25 | |
7286 | ||
7287 | ($1 may be used in old code; for robustness we accept any register) | |
7288 | or, in PIC code: | |
7289 | ||
7290 | lui $28, %hi(_gp_disp) | |
7291 | addiu $28, $28, %lo(_gp_disp) | |
7292 | addu $28, $28, $25 | |
7293 | lw $25, %got(bar) | |
7294 | addiu $25, $25, %lo(bar) | |
7295 | jr $25 | |
7296 | ||
7297 | In the case of a __call_stub_bar stub, the sequence to set up | |
7298 | arguments might look like this: | |
7299 | ||
7300 | mtc1 $4, $f13 | |
7301 | mtc1 $5, $f12 | |
7302 | mtc1 $6, $f15 | |
7303 | mtc1 $7, $f14 | |
7304 | ||
7305 | followed by (or interspersed with) one of the jump sequences above. | |
7306 | ||
7307 | In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead | |
7308 | of J or JR, respectively, followed by: | |
7309 | ||
7310 | mfc1 $2, $f0 | |
7311 | mfc1 $3, $f1 | |
7312 | jr $18 | |
7313 | ||
7314 | We are at the beginning of the stub here, and scan down and extract | |
7315 | the target address from the jump immediate instruction or, if a jump | |
7316 | register instruction is used, from the register referred. Return | |
7317 | the value of PC calculated or 0 if inconclusive. | |
7318 | ||
7319 | The limit on the search is arbitrarily set to 20 instructions. FIXME. */ | |
7320 | ||
7321 | static CORE_ADDR | |
7322 | mips_get_mips16_fn_stub_pc (struct frame_info *frame, CORE_ADDR pc) | |
7323 | { | |
7324 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
7325 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7326 | int addrreg = MIPS_ZERO_REGNUM; | |
7327 | CORE_ADDR start_pc = pc; | |
7328 | CORE_ADDR target_pc = 0; | |
7329 | CORE_ADDR addr = 0; | |
7330 | CORE_ADDR gp = 0; | |
7331 | int status = 0; | |
7332 | int i; | |
7333 | ||
7334 | for (i = 0; | |
7335 | status == 0 && target_pc == 0 && i < 20; | |
7336 | i++, pc += MIPS_INSN32_SIZE) | |
7337 | { | |
4cc0665f | 7338 | ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
14132e89 MR |
7339 | CORE_ADDR imm; |
7340 | int rt; | |
7341 | int rs; | |
7342 | int rd; | |
7343 | ||
7344 | switch (itype_op (inst)) | |
7345 | { | |
7346 | case 0: /* SPECIAL */ | |
7347 | switch (rtype_funct (inst)) | |
7348 | { | |
7349 | case 8: /* JR */ | |
7350 | case 9: /* JALR */ | |
7351 | rs = rtype_rs (inst); | |
7352 | if (rs == MIPS_GP_REGNUM) | |
7353 | target_pc = gp; /* Hmm... */ | |
7354 | else if (rs == addrreg) | |
7355 | target_pc = addr; | |
7356 | break; | |
7357 | ||
7358 | case 0x21: /* ADDU */ | |
7359 | rt = rtype_rt (inst); | |
7360 | rs = rtype_rs (inst); | |
7361 | rd = rtype_rd (inst); | |
7362 | if (rd == MIPS_GP_REGNUM | |
7363 | && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM) | |
7364 | || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM))) | |
7365 | gp += start_pc; | |
7366 | break; | |
7367 | } | |
7368 | break; | |
7369 | ||
7370 | case 2: /* J */ | |
7371 | case 3: /* JAL */ | |
7372 | target_pc = jtype_target (inst) << 2; | |
7373 | target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); | |
7374 | break; | |
7375 | ||
7376 | case 9: /* ADDIU */ | |
7377 | rt = itype_rt (inst); | |
7378 | rs = itype_rs (inst); | |
7379 | if (rt == rs) | |
7380 | { | |
7381 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7382 | if (rt == MIPS_GP_REGNUM) | |
7383 | gp += imm; | |
7384 | else if (rt == addrreg) | |
7385 | addr += imm; | |
7386 | } | |
7387 | break; | |
7388 | ||
7389 | case 0xf: /* LUI */ | |
7390 | rt = itype_rt (inst); | |
7391 | imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16; | |
7392 | if (rt == MIPS_GP_REGNUM) | |
7393 | gp = imm; | |
7394 | else if (rt != MIPS_ZERO_REGNUM) | |
7395 | { | |
7396 | addrreg = rt; | |
7397 | addr = imm; | |
7398 | } | |
7399 | break; | |
7400 | ||
7401 | case 0x23: /* LW */ | |
7402 | rt = itype_rt (inst); | |
7403 | rs = itype_rs (inst); | |
7404 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7405 | if (gp != 0 && rs == MIPS_GP_REGNUM) | |
7406 | { | |
7407 | gdb_byte buf[4]; | |
7408 | ||
7409 | memset (buf, 0, sizeof (buf)); | |
7410 | status = target_read_memory (gp + imm, buf, sizeof (buf)); | |
7411 | addrreg = rt; | |
7412 | addr = extract_signed_integer (buf, sizeof (buf), byte_order); | |
7413 | } | |
7414 | break; | |
7415 | } | |
7416 | } | |
7417 | ||
7418 | return target_pc; | |
7419 | } | |
7420 | ||
7421 | /* If PC is in a MIPS16 call or return stub, return the address of the | |
7422 | target PC, which is either the callee or the caller. There are several | |
c906108c SS |
7423 | cases which must be handled: |
7424 | ||
14132e89 MR |
7425 | * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7426 | and the target PC is in $31 ($ra). | |
c906108c | 7427 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
14132e89 MR |
7428 | and the target PC is in $2. |
7429 | * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, | |
7430 | i.e. before the JALR instruction, this is effectively a call stub | |
7431 | and the target PC is in $2. Otherwise this is effectively | |
7432 | a return stub and the target PC is in $18. | |
7433 | * If the PC is at the start of __call_stub_fp_*, i.e. before the | |
7434 | JAL or JALR instruction, this is effectively a call stub and the | |
7435 | target PC is buried in the instruction stream. Otherwise this | |
7436 | is effectively a return stub and the target PC is in $18. | |
7437 | * If the PC is in __call_stub_* or in __fn_stub_*, this is a call | |
7438 | stub and the target PC is buried in the instruction stream. | |
7439 | ||
7440 | See the source code for the stubs in gcc/config/mips/mips16.S, or the | |
7441 | stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the | |
e7d6a6d2 | 7442 | gory details. */ |
c906108c | 7443 | |
757a7cc6 | 7444 | static CORE_ADDR |
db5f024e | 7445 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 7446 | { |
e17a4113 | 7447 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 7448 | CORE_ADDR start_addr; |
14132e89 MR |
7449 | const char *name; |
7450 | size_t prefixlen; | |
c906108c SS |
7451 | |
7452 | /* Find the starting address and name of the function containing the PC. */ | |
7453 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
7454 | return 0; | |
7455 | ||
14132e89 MR |
7456 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7457 | and the target PC is in $31 ($ra). */ | |
7458 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7459 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7460 | && mips_is_stub_mode (name + prefixlen) | |
7461 | && name[prefixlen + 2] == '\0') | |
7462 | return get_frame_register_signed | |
7463 | (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
7464 | ||
7465 | /* If the PC is in __mips16_call_stub_*, this is one of the call | |
7466 | call/return stubs. */ | |
7467 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7468 | if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0) | |
c906108c SS |
7469 | { |
7470 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
7471 | and the target PC is in $2. */ | |
14132e89 MR |
7472 | if (mips_is_stub_suffix (name + prefixlen, 0)) |
7473 | return get_frame_register_signed | |
7474 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c | 7475 | |
14132e89 MR |
7476 | /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, |
7477 | i.e. before the JALR instruction, this is effectively a call stub | |
b021a221 | 7478 | and the target PC is in $2. Otherwise this is effectively |
c5aa993b | 7479 | a return stub and the target PC is in $18. */ |
14132e89 MR |
7480 | else if (mips_is_stub_mode (name + prefixlen) |
7481 | && name[prefixlen + 2] == '_' | |
7482 | && mips_is_stub_suffix (name + prefixlen + 3, 0)) | |
c906108c SS |
7483 | { |
7484 | if (pc == start_addr) | |
14132e89 MR |
7485 | /* This is the 'call' part of a call stub. The return |
7486 | address is in $2. */ | |
7487 | return get_frame_register_signed | |
7488 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c SS |
7489 | else |
7490 | /* This is the 'return' part of a call stub. The return | |
14132e89 MR |
7491 | address is in $18. */ |
7492 | return get_frame_register_signed | |
7493 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7494 | } |
14132e89 MR |
7495 | else |
7496 | return 0; /* Not a stub. */ | |
7497 | } | |
7498 | ||
7499 | /* If the PC is in __call_stub_* or __fn_stub*, this is one of the | |
7500 | compiler-generated call or call/return stubs. */ | |
7501 | if (strncmp (name, mips_str_fn_stub, strlen (mips_str_fn_stub)) == 0 | |
7502 | || strncmp (name, mips_str_call_stub, strlen (mips_str_call_stub)) == 0) | |
7503 | { | |
7504 | if (pc == start_addr) | |
7505 | /* This is the 'call' part of a call stub. Call this helper | |
7506 | to scan through this code for interesting instructions | |
7507 | and determine the final PC. */ | |
7508 | return mips_get_mips16_fn_stub_pc (frame, pc); | |
7509 | else | |
7510 | /* This is the 'return' part of a call stub. The return address | |
7511 | is in $18. */ | |
7512 | return get_frame_register_signed | |
7513 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7514 | } |
14132e89 MR |
7515 | |
7516 | return 0; /* Not a stub. */ | |
7517 | } | |
7518 | ||
7519 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
7520 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
7521 | ||
7522 | static int | |
7523 | mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name) | |
7524 | { | |
7525 | CORE_ADDR start_addr; | |
7526 | size_t prefixlen; | |
7527 | ||
7528 | /* Find the starting address of the function containing the PC. */ | |
7529 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
7530 | return 0; | |
7531 | ||
7532 | /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at | |
7533 | the start, i.e. after the JALR instruction, this is effectively | |
7534 | a return stub. */ | |
7535 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7536 | if (pc != start_addr | |
7537 | && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0 | |
7538 | && mips_is_stub_mode (name + prefixlen) | |
7539 | && name[prefixlen + 2] == '_' | |
7540 | && mips_is_stub_suffix (name + prefixlen + 3, 1)) | |
7541 | return 1; | |
7542 | ||
7543 | /* If the PC is in __call_stub_fp_* but not at the start, i.e. after | |
7544 | the JAL or JALR instruction, this is effectively a return stub. */ | |
7545 | prefixlen = strlen (mips_str_call_fp_stub); | |
7546 | if (pc != start_addr | |
7547 | && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0) | |
7548 | return 1; | |
7549 | ||
7550 | /* Consume the .pic. prefix of any PIC stub, this function must return | |
7551 | true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub | |
7552 | or the call stub path will trigger in handle_inferior_event causing | |
7553 | it to go astray. */ | |
7554 | prefixlen = strlen (mips_str_pic); | |
7555 | if (strncmp (name, mips_str_pic, prefixlen) == 0) | |
7556 | name += prefixlen; | |
7557 | ||
7558 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */ | |
7559 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7560 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7561 | && mips_is_stub_mode (name + prefixlen) | |
7562 | && name[prefixlen + 2] == '\0') | |
7563 | return 1; | |
7564 | ||
7565 | return 0; /* Not a stub. */ | |
c906108c SS |
7566 | } |
7567 | ||
db5f024e DJ |
7568 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
7569 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
7570 | so that $t9 has the correct value at function entry. */ | |
7571 | ||
7572 | static CORE_ADDR | |
7573 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
7574 | { | |
e17a4113 UW |
7575 | struct gdbarch *gdbarch = get_frame_arch (frame); |
7576 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
db5f024e DJ |
7577 | struct minimal_symbol *msym; |
7578 | int i; | |
7579 | gdb_byte stub_code[16]; | |
7580 | int32_t stub_words[4]; | |
7581 | ||
7582 | /* The stub for foo is named ".pic.foo", and is either two | |
7583 | instructions inserted before foo or a three instruction sequence | |
7584 | which jumps to foo. */ | |
7585 | msym = lookup_minimal_symbol_by_pc (pc); | |
7586 | if (msym == NULL | |
7587 | || SYMBOL_VALUE_ADDRESS (msym) != pc | |
7588 | || SYMBOL_LINKAGE_NAME (msym) == NULL | |
7589 | || strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) != 0) | |
7590 | return 0; | |
7591 | ||
7592 | /* A two-instruction header. */ | |
7593 | if (MSYMBOL_SIZE (msym) == 8) | |
7594 | return pc + 8; | |
7595 | ||
7596 | /* A three-instruction (plus delay slot) trampoline. */ | |
7597 | if (MSYMBOL_SIZE (msym) == 16) | |
7598 | { | |
7599 | if (target_read_memory (pc, stub_code, 16) != 0) | |
7600 | return 0; | |
7601 | for (i = 0; i < 4; i++) | |
e17a4113 UW |
7602 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
7603 | 4, byte_order); | |
db5f024e DJ |
7604 | |
7605 | /* A stub contains these instructions: | |
7606 | lui t9, %hi(target) | |
7607 | j target | |
7608 | addiu t9, t9, %lo(target) | |
7609 | nop | |
7610 | ||
7611 | This works even for N64, since stubs are only generated with | |
7612 | -msym32. */ | |
7613 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
7614 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
7615 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
7616 | && stub_words[3] == 0x00000000) | |
34b192ce MR |
7617 | return ((((stub_words[0] & 0x0000ffff) << 16) |
7618 | + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000; | |
db5f024e DJ |
7619 | } |
7620 | ||
7621 | /* Not a recognized stub. */ | |
7622 | return 0; | |
7623 | } | |
7624 | ||
7625 | static CORE_ADDR | |
7626 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
7627 | { | |
14132e89 | 7628 | CORE_ADDR requested_pc = pc; |
db5f024e | 7629 | CORE_ADDR target_pc; |
14132e89 MR |
7630 | CORE_ADDR new_pc; |
7631 | ||
7632 | do | |
7633 | { | |
7634 | target_pc = pc; | |
db5f024e | 7635 | |
14132e89 MR |
7636 | new_pc = mips_skip_mips16_trampoline_code (frame, pc); |
7637 | if (new_pc) | |
7638 | { | |
7639 | pc = new_pc; | |
4cc0665f MR |
7640 | if (is_compact_addr (pc)) |
7641 | pc = unmake_compact_addr (pc); | |
14132e89 | 7642 | } |
db5f024e | 7643 | |
14132e89 MR |
7644 | new_pc = find_solib_trampoline_target (frame, pc); |
7645 | if (new_pc) | |
7646 | { | |
7647 | pc = new_pc; | |
4cc0665f MR |
7648 | if (is_compact_addr (pc)) |
7649 | pc = unmake_compact_addr (pc); | |
14132e89 | 7650 | } |
db5f024e | 7651 | |
14132e89 MR |
7652 | new_pc = mips_skip_pic_trampoline_code (frame, pc); |
7653 | if (new_pc) | |
7654 | { | |
7655 | pc = new_pc; | |
4cc0665f MR |
7656 | if (is_compact_addr (pc)) |
7657 | pc = unmake_compact_addr (pc); | |
14132e89 MR |
7658 | } |
7659 | } | |
7660 | while (pc != target_pc); | |
db5f024e | 7661 | |
14132e89 | 7662 | return pc != requested_pc ? pc : 0; |
db5f024e DJ |
7663 | } |
7664 | ||
a4b8ebc8 | 7665 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 7666 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7667 | |
7668 | static int | |
d3f73121 | 7669 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7670 | { |
a4b8ebc8 | 7671 | int regnum; |
2f38ef89 | 7672 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7673 | regnum = num; |
2f38ef89 | 7674 | else if (num >= 38 && num < 70) |
d3f73121 | 7675 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 7676 | else if (num == 70) |
d3f73121 | 7677 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7678 | else if (num == 71) |
d3f73121 | 7679 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7680 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78) |
7681 | regnum = num + mips_regnum (gdbarch)->dspacc - 72; | |
2f38ef89 | 7682 | else |
a4b8ebc8 AC |
7683 | /* This will hopefully (eventually) provoke a warning. Should |
7684 | we be calling complaint() here? */ | |
d3f73121 MD |
7685 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
7686 | return gdbarch_num_regs (gdbarch) + regnum; | |
88c72b7d AC |
7687 | } |
7688 | ||
2f38ef89 | 7689 | |
a4b8ebc8 | 7690 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 7691 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7692 | |
7693 | static int | |
d3f73121 | 7694 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7695 | { |
a4b8ebc8 | 7696 | int regnum; |
2f38ef89 | 7697 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7698 | regnum = num; |
2f38ef89 | 7699 | else if (num >= 32 && num < 64) |
d3f73121 | 7700 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 7701 | else if (num == 64) |
d3f73121 | 7702 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7703 | else if (num == 65) |
d3f73121 | 7704 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7705 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72) |
7706 | regnum = num + mips_regnum (gdbarch)->dspacc - 66; | |
2f38ef89 | 7707 | else |
a4b8ebc8 AC |
7708 | /* This will hopefully (eventually) provoke a warning. Should we |
7709 | be calling complaint() here? */ | |
d3f73121 MD |
7710 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
7711 | return gdbarch_num_regs (gdbarch) + regnum; | |
a4b8ebc8 AC |
7712 | } |
7713 | ||
7714 | static int | |
e7faf938 | 7715 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
7716 | { |
7717 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 7718 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
7719 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
7720 | decide if it is valid. Should instead define a standard sim/gdb | |
7721 | register numbering scheme. */ | |
e7faf938 MD |
7722 | if (gdbarch_register_name (gdbarch, |
7723 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
7724 | && gdbarch_register_name (gdbarch, | |
025bb325 MS |
7725 | gdbarch_num_regs (gdbarch) |
7726 | + regnum)[0] != '\0') | |
a4b8ebc8 AC |
7727 | return regnum; |
7728 | else | |
6d82d43b | 7729 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
7730 | } |
7731 | ||
2f38ef89 | 7732 | |
4844f454 CV |
7733 | /* Convert an integer into an address. Extracting the value signed |
7734 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
7735 | |
7736 | static CORE_ADDR | |
79dd2d24 | 7737 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 7738 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 7739 | { |
e17a4113 UW |
7740 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7741 | return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); | |
fc0c74b1 AC |
7742 | } |
7743 | ||
82e91389 DJ |
7744 | /* Dummy virtual frame pointer method. This is no more or less accurate |
7745 | than most other architectures; we just need to be explicit about it, | |
7746 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
7747 | an assertion failure. */ | |
7748 | ||
7749 | static void | |
a54fba4c MD |
7750 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
7751 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
7752 | { |
7753 | *reg = MIPS_SP_REGNUM; | |
7754 | *offset = 0; | |
7755 | } | |
7756 | ||
caaa3122 DJ |
7757 | static void |
7758 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
7759 | { | |
7760 | enum mips_abi *abip = (enum mips_abi *) obj; | |
7761 | const char *name = bfd_get_section_name (abfd, sect); | |
7762 | ||
7763 | if (*abip != MIPS_ABI_UNKNOWN) | |
7764 | return; | |
7765 | ||
7766 | if (strncmp (name, ".mdebug.", 8) != 0) | |
7767 | return; | |
7768 | ||
7769 | if (strcmp (name, ".mdebug.abi32") == 0) | |
7770 | *abip = MIPS_ABI_O32; | |
7771 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
7772 | *abip = MIPS_ABI_N32; | |
62a49b2c | 7773 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 7774 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
7775 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
7776 | *abip = MIPS_ABI_O64; | |
7777 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
7778 | *abip = MIPS_ABI_EABI32; | |
7779 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
7780 | *abip = MIPS_ABI_EABI64; | |
7781 | else | |
8a3fe4f8 | 7782 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
7783 | } |
7784 | ||
22e47e37 FF |
7785 | static void |
7786 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
7787 | { | |
7788 | int *lbp = (int *) obj; | |
7789 | const char *name = bfd_get_section_name (abfd, sect); | |
7790 | ||
7791 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
7792 | *lbp = 32; | |
7793 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
7794 | *lbp = 64; | |
7795 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
7796 | warning (_("unrecognized .gcc_compiled_longXX")); | |
7797 | } | |
7798 | ||
2e4ebe70 DJ |
7799 | static enum mips_abi |
7800 | global_mips_abi (void) | |
7801 | { | |
7802 | int i; | |
7803 | ||
7804 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
7805 | if (mips_abi_strings[i] == mips_abi_string) | |
7806 | return (enum mips_abi) i; | |
7807 | ||
e2e0b3e5 | 7808 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
7809 | } |
7810 | ||
4cc0665f MR |
7811 | /* Return the default compressed instruction set, either of MIPS16 |
7812 | or microMIPS, selected when none could have been determined from | |
7813 | the ELF header of the binary being executed (or no binary has been | |
7814 | selected. */ | |
7815 | ||
7816 | static enum mips_isa | |
7817 | global_mips_compression (void) | |
7818 | { | |
7819 | int i; | |
7820 | ||
7821 | for (i = 0; mips_compression_strings[i] != NULL; i++) | |
7822 | if (mips_compression_strings[i] == mips_compression_string) | |
7823 | return (enum mips_isa) i; | |
7824 | ||
7825 | internal_error (__FILE__, __LINE__, _("unknown compressed ISA string")); | |
7826 | } | |
7827 | ||
29709017 DJ |
7828 | static void |
7829 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
7830 | { | |
29709017 DJ |
7831 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
7832 | assume that's what we've got. */ | |
4eb0ad19 DJ |
7833 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
7834 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
7835 | |
7836 | /* If the size matches the full set of registers GDB traditionally | |
7837 | knows about, including floating point, for either 32-bit or | |
7838 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
7839 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
7840 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
7841 | |
7842 | /* Otherwise we don't have a useful guess. */ | |
7843 | } | |
7844 | ||
f8b73d13 DJ |
7845 | static struct value * |
7846 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
7847 | { | |
7848 | const int *reg_p = baton; | |
7849 | return value_of_register (*reg_p, frame); | |
7850 | } | |
7851 | ||
c2d11a7d | 7852 | static struct gdbarch * |
6d82d43b | 7853 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 7854 | { |
c2d11a7d JM |
7855 | struct gdbarch *gdbarch; |
7856 | struct gdbarch_tdep *tdep; | |
7857 | int elf_flags; | |
2e4ebe70 | 7858 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 7859 | int i, num_regs; |
8d5838b5 | 7860 | enum mips_fpu_type fpu_type; |
f8b73d13 | 7861 | struct tdesc_arch_data *tdesc_data = NULL; |
609ca2b9 | 7862 | int elf_fpu_type = 0; |
1faeff08 MR |
7863 | const char **reg_names; |
7864 | struct mips_regnum mips_regnum, *regnum; | |
4cc0665f | 7865 | enum mips_isa mips_isa; |
1faeff08 MR |
7866 | int dspacc; |
7867 | int dspctl; | |
7868 | ||
7869 | /* Fill in the OS dependent register numbers and names. */ | |
7870 | if (info.osabi == GDB_OSABI_IRIX) | |
7871 | { | |
7872 | mips_regnum.fp0 = 32; | |
7873 | mips_regnum.pc = 64; | |
7874 | mips_regnum.cause = 65; | |
7875 | mips_regnum.badvaddr = 66; | |
7876 | mips_regnum.hi = 67; | |
7877 | mips_regnum.lo = 68; | |
7878 | mips_regnum.fp_control_status = 69; | |
7879 | mips_regnum.fp_implementation_revision = 70; | |
7880 | mips_regnum.dspacc = dspacc = -1; | |
7881 | mips_regnum.dspctl = dspctl = -1; | |
7882 | num_regs = 71; | |
7883 | reg_names = mips_irix_reg_names; | |
7884 | } | |
7885 | else if (info.osabi == GDB_OSABI_LINUX) | |
7886 | { | |
7887 | mips_regnum.fp0 = 38; | |
7888 | mips_regnum.pc = 37; | |
7889 | mips_regnum.cause = 36; | |
7890 | mips_regnum.badvaddr = 35; | |
7891 | mips_regnum.hi = 34; | |
7892 | mips_regnum.lo = 33; | |
7893 | mips_regnum.fp_control_status = 70; | |
7894 | mips_regnum.fp_implementation_revision = 71; | |
7895 | mips_regnum.dspacc = -1; | |
7896 | mips_regnum.dspctl = -1; | |
7897 | dspacc = 72; | |
7898 | dspctl = 78; | |
7899 | num_regs = 79; | |
7900 | reg_names = mips_linux_reg_names; | |
7901 | } | |
7902 | else | |
7903 | { | |
7904 | mips_regnum.lo = MIPS_EMBED_LO_REGNUM; | |
7905 | mips_regnum.hi = MIPS_EMBED_HI_REGNUM; | |
7906 | mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
7907 | mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM; | |
7908 | mips_regnum.pc = MIPS_EMBED_PC_REGNUM; | |
7909 | mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM; | |
7910 | mips_regnum.fp_control_status = 70; | |
7911 | mips_regnum.fp_implementation_revision = 71; | |
7912 | mips_regnum.dspacc = dspacc = -1; | |
7913 | mips_regnum.dspctl = dspctl = -1; | |
7914 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
7915 | if (info.bfd_arch_info != NULL | |
7916 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
7917 | reg_names = mips_tx39_reg_names; | |
7918 | else | |
7919 | reg_names = mips_generic_reg_names; | |
7920 | } | |
f8b73d13 DJ |
7921 | |
7922 | /* Check any target description for validity. */ | |
7923 | if (tdesc_has_registers (info.target_desc)) | |
7924 | { | |
7925 | static const char *const mips_gprs[] = { | |
7926 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
7927 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
7928 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
7929 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
7930 | }; | |
7931 | static const char *const mips_fprs[] = { | |
7932 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
7933 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
7934 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
7935 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
7936 | }; | |
7937 | ||
7938 | const struct tdesc_feature *feature; | |
7939 | int valid_p; | |
7940 | ||
7941 | feature = tdesc_find_feature (info.target_desc, | |
7942 | "org.gnu.gdb.mips.cpu"); | |
7943 | if (feature == NULL) | |
7944 | return NULL; | |
7945 | ||
7946 | tdesc_data = tdesc_data_alloc (); | |
7947 | ||
7948 | valid_p = 1; | |
7949 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
7950 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
7951 | mips_gprs[i]); | |
7952 | ||
7953 | ||
7954 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 7955 | mips_regnum.lo, "lo"); |
f8b73d13 | 7956 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
1faeff08 | 7957 | mips_regnum.hi, "hi"); |
f8b73d13 | 7958 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
1faeff08 | 7959 | mips_regnum.pc, "pc"); |
f8b73d13 DJ |
7960 | |
7961 | if (!valid_p) | |
7962 | { | |
7963 | tdesc_data_cleanup (tdesc_data); | |
7964 | return NULL; | |
7965 | } | |
7966 | ||
7967 | feature = tdesc_find_feature (info.target_desc, | |
7968 | "org.gnu.gdb.mips.cp0"); | |
7969 | if (feature == NULL) | |
7970 | { | |
7971 | tdesc_data_cleanup (tdesc_data); | |
7972 | return NULL; | |
7973 | } | |
7974 | ||
7975 | valid_p = 1; | |
7976 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 7977 | mips_regnum.badvaddr, "badvaddr"); |
f8b73d13 DJ |
7978 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
7979 | MIPS_PS_REGNUM, "status"); | |
7980 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 7981 | mips_regnum.cause, "cause"); |
f8b73d13 DJ |
7982 | |
7983 | if (!valid_p) | |
7984 | { | |
7985 | tdesc_data_cleanup (tdesc_data); | |
7986 | return NULL; | |
7987 | } | |
7988 | ||
7989 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
7990 | backend is not prepared for that, though. */ | |
7991 | feature = tdesc_find_feature (info.target_desc, | |
7992 | "org.gnu.gdb.mips.fpu"); | |
7993 | if (feature == NULL) | |
7994 | { | |
7995 | tdesc_data_cleanup (tdesc_data); | |
7996 | return NULL; | |
7997 | } | |
7998 | ||
7999 | valid_p = 1; | |
8000 | for (i = 0; i < 32; i++) | |
8001 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 8002 | i + mips_regnum.fp0, mips_fprs[i]); |
f8b73d13 DJ |
8003 | |
8004 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 MR |
8005 | mips_regnum.fp_control_status, |
8006 | "fcsr"); | |
8007 | valid_p | |
8008 | &= tdesc_numbered_register (feature, tdesc_data, | |
8009 | mips_regnum.fp_implementation_revision, | |
8010 | "fir"); | |
f8b73d13 DJ |
8011 | |
8012 | if (!valid_p) | |
8013 | { | |
8014 | tdesc_data_cleanup (tdesc_data); | |
8015 | return NULL; | |
8016 | } | |
8017 | ||
1faeff08 MR |
8018 | if (dspacc >= 0) |
8019 | { | |
8020 | feature = tdesc_find_feature (info.target_desc, | |
8021 | "org.gnu.gdb.mips.dsp"); | |
8022 | /* The DSP registers are optional; it's OK if they are absent. */ | |
8023 | if (feature != NULL) | |
8024 | { | |
8025 | i = 0; | |
8026 | valid_p = 1; | |
8027 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8028 | dspacc + i++, "hi1"); | |
8029 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8030 | dspacc + i++, "lo1"); | |
8031 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8032 | dspacc + i++, "hi2"); | |
8033 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8034 | dspacc + i++, "lo2"); | |
8035 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8036 | dspacc + i++, "hi3"); | |
8037 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8038 | dspacc + i++, "lo3"); | |
8039 | ||
8040 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
8041 | dspctl, "dspctl"); | |
8042 | ||
8043 | if (!valid_p) | |
8044 | { | |
8045 | tdesc_data_cleanup (tdesc_data); | |
8046 | return NULL; | |
8047 | } | |
8048 | ||
8049 | mips_regnum.dspacc = dspacc; | |
8050 | mips_regnum.dspctl = dspctl; | |
8051 | } | |
8052 | } | |
8053 | ||
f8b73d13 DJ |
8054 | /* It would be nice to detect an attempt to use a 64-bit ABI |
8055 | when only 32-bit registers are provided. */ | |
1faeff08 | 8056 | reg_names = NULL; |
f8b73d13 | 8057 | } |
c2d11a7d | 8058 | |
ec03c1ac AC |
8059 | /* First of all, extract the elf_flags, if available. */ |
8060 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8061 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
8062 | else if (arches != NULL) |
8063 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
8064 | else |
8065 | elf_flags = 0; | |
8066 | if (gdbarch_debug) | |
8067 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 8068 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 8069 | |
102182a9 | 8070 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
8071 | switch ((elf_flags & EF_MIPS_ABI)) |
8072 | { | |
8073 | case E_MIPS_ABI_O32: | |
ec03c1ac | 8074 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
8075 | break; |
8076 | case E_MIPS_ABI_O64: | |
ec03c1ac | 8077 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
8078 | break; |
8079 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 8080 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
8081 | break; |
8082 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 8083 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
8084 | break; |
8085 | default: | |
acdb74a0 | 8086 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 8087 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 8088 | else |
ec03c1ac | 8089 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
8090 | break; |
8091 | } | |
acdb74a0 | 8092 | |
caaa3122 | 8093 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
8094 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
8095 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 8096 | |
dc305454 | 8097 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
8098 | MIPS architecture (if there is one). */ |
8099 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
8100 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 8101 | |
32a6503c | 8102 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 8103 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
8104 | && info.bfd_arch_info != NULL |
8105 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8106 | { | |
8107 | switch (info.bfd_arch_info->mach) | |
8108 | { | |
8109 | case bfd_mach_mips3900: | |
ec03c1ac | 8110 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
8111 | break; |
8112 | case bfd_mach_mips4100: | |
8113 | case bfd_mach_mips5000: | |
ec03c1ac | 8114 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 8115 | break; |
1d06468c EZ |
8116 | case bfd_mach_mips8000: |
8117 | case bfd_mach_mips10000: | |
32a6503c KB |
8118 | /* On Irix, ELF64 executables use the N64 ABI. The |
8119 | pseudo-sections which describe the ABI aren't present | |
8120 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
8121 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
8122 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 8123 | found_abi = MIPS_ABI_N64; |
28d169de | 8124 | else |
ec03c1ac | 8125 | found_abi = MIPS_ABI_N32; |
1d06468c | 8126 | break; |
bf64bfd6 AC |
8127 | } |
8128 | } | |
2e4ebe70 | 8129 | |
26c53e50 DJ |
8130 | /* Default 64-bit objects to N64 instead of O32. */ |
8131 | if (found_abi == MIPS_ABI_UNKNOWN | |
8132 | && info.abfd != NULL | |
8133 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
8134 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
8135 | found_abi = MIPS_ABI_N64; | |
8136 | ||
ec03c1ac AC |
8137 | if (gdbarch_debug) |
8138 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
8139 | found_abi); | |
8140 | ||
8141 | /* What has the user specified from the command line? */ | |
8142 | wanted_abi = global_mips_abi (); | |
8143 | if (gdbarch_debug) | |
8144 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
8145 | wanted_abi); | |
2e4ebe70 DJ |
8146 | |
8147 | /* Now that we have found what the ABI for this binary would be, | |
8148 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
8149 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
8150 | mips_abi = wanted_abi; | |
ec03c1ac AC |
8151 | else if (found_abi != MIPS_ABI_UNKNOWN) |
8152 | mips_abi = found_abi; | |
8153 | else | |
8154 | mips_abi = MIPS_ABI_O32; | |
8155 | if (gdbarch_debug) | |
8156 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
8157 | mips_abi); | |
2e4ebe70 | 8158 | |
4cc0665f MR |
8159 | /* Determine the default compressed ISA. */ |
8160 | if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0 | |
8161 | && (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0) | |
8162 | mips_isa = ISA_MICROMIPS; | |
8163 | else if ((elf_flags & EF_MIPS_ARCH_ASE_M16) != 0 | |
8164 | && (elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) == 0) | |
8165 | mips_isa = ISA_MIPS16; | |
8166 | else | |
8167 | mips_isa = global_mips_compression (); | |
8168 | mips_compression_string = mips_compression_strings[mips_isa]; | |
8169 | ||
ec03c1ac | 8170 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 8171 | if (gdbarch_debug) |
ec03c1ac | 8172 | fprintf_unfiltered (gdb_stdlog, |
025bb325 MS |
8173 | "mips_gdbarch_init: " |
8174 | "mips64_transfers_32bit_regs_p = %d\n", | |
ec03c1ac | 8175 | mips64_transfers_32bit_regs_p); |
0dadbba0 | 8176 | |
8d5838b5 | 8177 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
8178 | #ifdef HAVE_ELF |
8179 | if (info.abfd | |
8180 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8181 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
8182 | Tag_GNU_MIPS_ABI_FP); | |
8183 | #endif /* HAVE_ELF */ | |
8184 | ||
8d5838b5 AC |
8185 | if (!mips_fpu_type_auto) |
8186 | fpu_type = mips_fpu_type; | |
609ca2b9 DJ |
8187 | else if (elf_fpu_type != 0) |
8188 | { | |
8189 | switch (elf_fpu_type) | |
8190 | { | |
8191 | case 1: | |
8192 | fpu_type = MIPS_FPU_DOUBLE; | |
8193 | break; | |
8194 | case 2: | |
8195 | fpu_type = MIPS_FPU_SINGLE; | |
8196 | break; | |
8197 | case 3: | |
8198 | default: | |
8199 | /* Soft float or unknown. */ | |
8200 | fpu_type = MIPS_FPU_NONE; | |
8201 | break; | |
8202 | } | |
8203 | } | |
8d5838b5 AC |
8204 | else if (info.bfd_arch_info != NULL |
8205 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8206 | switch (info.bfd_arch_info->mach) | |
8207 | { | |
8208 | case bfd_mach_mips3900: | |
8209 | case bfd_mach_mips4100: | |
8210 | case bfd_mach_mips4111: | |
a9d61c86 | 8211 | case bfd_mach_mips4120: |
8d5838b5 AC |
8212 | fpu_type = MIPS_FPU_NONE; |
8213 | break; | |
8214 | case bfd_mach_mips4650: | |
8215 | fpu_type = MIPS_FPU_SINGLE; | |
8216 | break; | |
8217 | default: | |
8218 | fpu_type = MIPS_FPU_DOUBLE; | |
8219 | break; | |
8220 | } | |
8221 | else if (arches != NULL) | |
8222 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
8223 | else | |
8224 | fpu_type = MIPS_FPU_DOUBLE; | |
8225 | if (gdbarch_debug) | |
8226 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 8227 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 8228 | |
29709017 DJ |
8229 | /* Check for blatant incompatibilities. */ |
8230 | ||
8231 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
8232 | ABI. */ | |
8233 | if (info.target_desc | |
8234 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
8235 | && mips_abi != MIPS_ABI_EABI32 | |
8236 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
8237 | { |
8238 | if (tdesc_data != NULL) | |
8239 | tdesc_data_cleanup (tdesc_data); | |
8240 | return NULL; | |
8241 | } | |
29709017 | 8242 | |
025bb325 | 8243 | /* Try to find a pre-existing architecture. */ |
c2d11a7d JM |
8244 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
8245 | arches != NULL; | |
8246 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
8247 | { | |
8248 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 8249 | using. */ |
9103eae0 | 8250 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 8251 | continue; |
9103eae0 | 8252 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 8253 | continue; |
719ec221 AC |
8254 | /* Need to be pedantic about which register virtual size is |
8255 | used. */ | |
8256 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
8257 | != mips64_transfers_32bit_regs_p) | |
8258 | continue; | |
8d5838b5 AC |
8259 | /* Be pedantic about which FPU is selected. */ |
8260 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
8261 | continue; | |
f8b73d13 DJ |
8262 | |
8263 | if (tdesc_data != NULL) | |
8264 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 8265 | return arches->gdbarch; |
c2d11a7d JM |
8266 | } |
8267 | ||
102182a9 | 8268 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
8269 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
8270 | gdbarch = gdbarch_alloc (&info, tdep); | |
8271 | tdep->elf_flags = elf_flags; | |
719ec221 | 8272 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
8273 | tdep->found_abi = found_abi; |
8274 | tdep->mips_abi = mips_abi; | |
4cc0665f | 8275 | tdep->mips_isa = mips_isa; |
8d5838b5 | 8276 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
8277 | tdep->register_size_valid_p = 0; |
8278 | tdep->register_size = 0; | |
50e8a0d5 HZ |
8279 | tdep->gregset = NULL; |
8280 | tdep->gregset64 = NULL; | |
8281 | tdep->fpregset = NULL; | |
8282 | tdep->fpregset64 = NULL; | |
29709017 DJ |
8283 | |
8284 | if (info.target_desc) | |
8285 | { | |
8286 | /* Some useful properties can be inferred from the target. */ | |
8287 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
8288 | { | |
8289 | tdep->register_size_valid_p = 1; | |
8290 | tdep->register_size = 4; | |
8291 | } | |
8292 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
8293 | { | |
8294 | tdep->register_size_valid_p = 1; | |
8295 | tdep->register_size = 8; | |
8296 | } | |
8297 | } | |
c2d11a7d | 8298 | |
102182a9 | 8299 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
8300 | set_gdbarch_short_bit (gdbarch, 16); |
8301 | set_gdbarch_int_bit (gdbarch, 32); | |
8302 | set_gdbarch_float_bit (gdbarch, 32); | |
8303 | set_gdbarch_double_bit (gdbarch, 64); | |
8304 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
8305 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
8306 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
8307 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 8308 | |
175ff332 HZ |
8309 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
8310 | mips_ax_pseudo_register_collect); | |
8311 | set_gdbarch_ax_pseudo_register_push_stack | |
8312 | (gdbarch, mips_ax_pseudo_register_push_stack); | |
8313 | ||
6d82d43b | 8314 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
8315 | mips_elf_make_msymbol_special); |
8316 | ||
1faeff08 MR |
8317 | regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum); |
8318 | *regnum = mips_regnum; | |
1faeff08 MR |
8319 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
8320 | set_gdbarch_num_regs (gdbarch, num_regs); | |
8321 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8322 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
8323 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); | |
8324 | tdep->mips_processor_reg_names = reg_names; | |
8325 | tdep->regnum = regnum; | |
fe29b929 | 8326 | |
0dadbba0 | 8327 | switch (mips_abi) |
c2d11a7d | 8328 | { |
0dadbba0 | 8329 | case MIPS_ABI_O32: |
25ab4790 | 8330 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 8331 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 8332 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8333 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 8334 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8335 | set_gdbarch_long_bit (gdbarch, 32); |
8336 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8337 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8338 | break; | |
0dadbba0 | 8339 | case MIPS_ABI_O64: |
25ab4790 | 8340 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 8341 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 8342 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8343 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 8344 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8345 | set_gdbarch_long_bit (gdbarch, 32); |
8346 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8347 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8348 | break; | |
0dadbba0 | 8349 | case MIPS_ABI_EABI32: |
25ab4790 | 8350 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8351 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8352 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8353 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8354 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8355 | set_gdbarch_long_bit (gdbarch, 32); |
8356 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8357 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8358 | break; | |
0dadbba0 | 8359 | case MIPS_ABI_EABI64: |
25ab4790 | 8360 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8361 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8362 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8363 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8364 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8365 | set_gdbarch_long_bit (gdbarch, 64); |
8366 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8367 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8368 | break; | |
0dadbba0 | 8369 | case MIPS_ABI_N32: |
25ab4790 | 8370 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8371 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8372 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8373 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8374 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
8375 | set_gdbarch_long_bit (gdbarch, 32); |
8376 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8377 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8378 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8379 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
8380 | break; |
8381 | case MIPS_ABI_N64: | |
25ab4790 | 8382 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8383 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8384 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8385 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
8386 | tdep->default_mask_address_p = 0; |
8387 | set_gdbarch_long_bit (gdbarch, 64); | |
8388 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8389 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8390 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8391 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 8392 | break; |
c2d11a7d | 8393 | default: |
e2e0b3e5 | 8394 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
8395 | } |
8396 | ||
22e47e37 FF |
8397 | /* GCC creates a pseudo-section whose name specifies the size of |
8398 | longs, since -mlong32 or -mlong64 may be used independent of | |
8399 | other options. How those options affect pointer sizes is ABI and | |
8400 | architecture dependent, so use them to override the default sizes | |
8401 | set by the ABI. This table shows the relationship between ABI, | |
8402 | -mlongXX, and size of pointers: | |
8403 | ||
8404 | ABI -mlongXX ptr bits | |
8405 | --- -------- -------- | |
8406 | o32 32 32 | |
8407 | o32 64 32 | |
8408 | n32 32 32 | |
8409 | n32 64 64 | |
8410 | o64 32 32 | |
8411 | o64 64 64 | |
8412 | n64 32 32 | |
8413 | n64 64 64 | |
8414 | eabi32 32 32 | |
8415 | eabi32 64 32 | |
8416 | eabi64 32 32 | |
8417 | eabi64 64 64 | |
8418 | ||
8419 | Note that for o32 and eabi32, pointers are always 32 bits | |
8420 | regardless of any -mlongXX option. For all others, pointers and | |
025bb325 | 8421 | longs are the same, as set by -mlongXX or set by defaults. */ |
22e47e37 FF |
8422 | |
8423 | if (info.abfd != NULL) | |
8424 | { | |
8425 | int long_bit = 0; | |
8426 | ||
8427 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
8428 | if (long_bit) | |
8429 | { | |
8430 | set_gdbarch_long_bit (gdbarch, long_bit); | |
8431 | switch (mips_abi) | |
8432 | { | |
8433 | case MIPS_ABI_O32: | |
8434 | case MIPS_ABI_EABI32: | |
8435 | break; | |
8436 | case MIPS_ABI_N32: | |
8437 | case MIPS_ABI_O64: | |
8438 | case MIPS_ABI_N64: | |
8439 | case MIPS_ABI_EABI64: | |
8440 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
8441 | break; | |
8442 | default: | |
8443 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
8444 | } | |
8445 | } | |
8446 | } | |
8447 | ||
a5ea2558 AC |
8448 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
8449 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
8450 | comment: | |
8451 | ||
8452 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
8453 | flag in object files because to do so would make it impossible to | |
102182a9 | 8454 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 8455 | unnecessarily restrictive. |
361d1df0 | 8456 | |
a5ea2558 AC |
8457 | We could solve this problem by adding "-gp32" multilibs to gcc, |
8458 | but to set this flag before gcc is built with such multilibs will | |
8459 | break too many systems.'' | |
8460 | ||
8461 | But even more unhelpfully, the default linker output target for | |
8462 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
8463 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 8464 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
8465 | this flag to detect 32-bit mode would do the wrong thing given |
8466 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 8467 | as 32-bit programs by default. */ |
a5ea2558 | 8468 | |
6c997a34 | 8469 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 8470 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 8471 | |
102182a9 MS |
8472 | /* Add/remove bits from an address. The MIPS needs be careful to |
8473 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
8474 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
8475 | ||
58dfe9ff AC |
8476 | /* Unwind the frame. */ |
8477 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 8478 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 8479 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 8480 | |
102182a9 | 8481 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 8482 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
8483 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
8484 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
8485 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
8486 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 8487 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 8488 | |
025bb325 | 8489 | /* MIPS version of CALL_DUMMY. */ |
c2d11a7d | 8490 | |
2c76a0c7 JB |
8491 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
8492 | set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code); | |
dc604539 | 8493 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 8494 | |
87783b8b AC |
8495 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
8496 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
8497 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
8498 | ||
f7b9e9fc AC |
8499 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
8500 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
4cc0665f MR |
8501 | set_gdbarch_remote_breakpoint_from_pc (gdbarch, |
8502 | mips_remote_breakpoint_from_pc); | |
c8cef75f MR |
8503 | set_gdbarch_adjust_breakpoint_address (gdbarch, |
8504 | mips_adjust_breakpoint_address); | |
f7b9e9fc AC |
8505 | |
8506 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 8507 | |
97ab0fdd MR |
8508 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
8509 | ||
fc0c74b1 AC |
8510 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
8511 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
8512 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 8513 | |
a4b8ebc8 | 8514 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 8515 | |
e11c53d2 | 8516 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 8517 | |
9dae60cc UW |
8518 | if (mips_abi == MIPS_ABI_N32) |
8519 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); | |
8520 | else if (mips_abi == MIPS_ABI_N64) | |
8521 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); | |
8522 | else | |
8523 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); | |
e5ab0dce | 8524 | |
d92524f1 PM |
8525 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
8526 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 8527 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
8528 | being used as guards for target_stopped_by_watchpoint, why not have |
8529 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
8530 | is sitting on? */ |
8531 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
8532 | ||
e7d6a6d2 | 8533 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 8534 | |
14132e89 MR |
8535 | /* NOTE drow/2012-04-25: We overload the core solib trampoline code |
8536 | to support MIPS16. This is a bad thing. Make sure not to do it | |
8537 | if we have an OS ABI that actually supports shared libraries, since | |
8538 | shared library support is more important. If we have an OS someday | |
8539 | that supports both shared libraries and MIPS16, we'll have to find | |
8540 | a better place for these. | |
8541 | macro/2012-04-25: But that applies to return trampolines only and | |
8542 | currently no MIPS OS ABI uses shared libraries that have them. */ | |
8543 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); | |
8544 | ||
025bb325 MS |
8545 | set_gdbarch_single_step_through_delay (gdbarch, |
8546 | mips_single_step_through_delay); | |
3352ef37 | 8547 | |
0d5de010 DJ |
8548 | /* Virtual tables. */ |
8549 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
8550 | ||
29709017 DJ |
8551 | mips_register_g_packet_guesses (gdbarch); |
8552 | ||
6de918a6 | 8553 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 8554 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 8555 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 8556 | |
9aac7884 MR |
8557 | /* The hook may have adjusted num_regs, fetch the final value and |
8558 | set pc_regnum and sp_regnum now that it has been fixed. */ | |
9aac7884 MR |
8559 | num_regs = gdbarch_num_regs (gdbarch); |
8560 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); | |
8561 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8562 | ||
5792a79b | 8563 | /* Unwind the frame. */ |
b8a22b94 DJ |
8564 | dwarf2_append_unwinders (gdbarch); |
8565 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
8566 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
4cc0665f | 8567 | frame_unwind_append_unwinder (gdbarch, &mips_micro_frame_unwind); |
b8a22b94 | 8568 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); |
2bd0c3d7 | 8569 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 8570 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 | 8571 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
4cc0665f | 8572 | frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer); |
45c9dd44 | 8573 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); |
5792a79b | 8574 | |
f8b73d13 DJ |
8575 | if (tdesc_data) |
8576 | { | |
8577 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 8578 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
8579 | |
8580 | /* Override the normal target description methods to handle our | |
8581 | dual real and pseudo registers. */ | |
8582 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
025bb325 MS |
8583 | set_gdbarch_register_reggroup_p (gdbarch, |
8584 | mips_tdesc_register_reggroup_p); | |
f8b73d13 DJ |
8585 | |
8586 | num_regs = gdbarch_num_regs (gdbarch); | |
8587 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8588 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
8589 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8590 | } | |
8591 | ||
8592 | /* Add ABI-specific aliases for the registers. */ | |
8593 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
8594 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
8595 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
8596 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
8597 | else | |
8598 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
8599 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
8600 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
8601 | ||
8602 | /* Add some other standard aliases. */ | |
8603 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
8604 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
8605 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
8606 | ||
865093a3 AR |
8607 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
8608 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
8609 | value_of_mips_user_reg, | |
8610 | &mips_numeric_register_aliases[i].regnum); | |
8611 | ||
4b9b3959 AC |
8612 | return gdbarch; |
8613 | } | |
8614 | ||
2e4ebe70 | 8615 | static void |
6d82d43b | 8616 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
8617 | { |
8618 | struct gdbarch_info info; | |
8619 | ||
8620 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
8621 | mips_gdbarch_init will take care of the rest. */ | |
8622 | gdbarch_info_init (&info); | |
8623 | gdbarch_update_p (info); | |
8624 | } | |
8625 | ||
ad188201 KB |
8626 | /* Print out which MIPS ABI is in use. */ |
8627 | ||
8628 | static void | |
1f8ca57c JB |
8629 | show_mips_abi (struct ui_file *file, |
8630 | int from_tty, | |
8631 | struct cmd_list_element *ignored_cmd, | |
8632 | const char *ignored_value) | |
ad188201 | 8633 | { |
1cf3db46 | 8634 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
1f8ca57c JB |
8635 | fprintf_filtered |
8636 | (file, | |
8637 | "The MIPS ABI is unknown because the current architecture " | |
8638 | "is not MIPS.\n"); | |
ad188201 KB |
8639 | else |
8640 | { | |
8641 | enum mips_abi global_abi = global_mips_abi (); | |
1cf3db46 | 8642 | enum mips_abi actual_abi = mips_abi (target_gdbarch); |
ad188201 KB |
8643 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
8644 | ||
8645 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
8646 | fprintf_filtered |
8647 | (file, | |
8648 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 8649 | actual_abi_str); |
ad188201 | 8650 | else if (global_abi == actual_abi) |
1f8ca57c JB |
8651 | fprintf_filtered |
8652 | (file, | |
8653 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 8654 | actual_abi_str); |
ad188201 KB |
8655 | else |
8656 | { | |
8657 | /* Probably shouldn't happen... */ | |
025bb325 MS |
8658 | fprintf_filtered (file, |
8659 | "The (auto detected) MIPS ABI \"%s\" is in use " | |
8660 | "even though the user setting was \"%s\".\n", | |
6d82d43b | 8661 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
8662 | } |
8663 | } | |
8664 | } | |
8665 | ||
4cc0665f MR |
8666 | /* Print out which MIPS compressed ISA encoding is used. */ |
8667 | ||
8668 | static void | |
8669 | show_mips_compression (struct ui_file *file, int from_tty, | |
8670 | struct cmd_list_element *c, const char *value) | |
8671 | { | |
8672 | fprintf_filtered (file, _("The compressed ISA encoding used is %s.\n"), | |
8673 | value); | |
8674 | } | |
8675 | ||
4b9b3959 | 8676 | static void |
72a155b4 | 8677 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 8678 | { |
72a155b4 | 8679 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 8680 | if (tdep != NULL) |
c2d11a7d | 8681 | { |
acdb74a0 AC |
8682 | int ef_mips_arch; |
8683 | int ef_mips_32bitmode; | |
f49e4e6d | 8684 | /* Determine the ISA. */ |
acdb74a0 AC |
8685 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
8686 | { | |
8687 | case E_MIPS_ARCH_1: | |
8688 | ef_mips_arch = 1; | |
8689 | break; | |
8690 | case E_MIPS_ARCH_2: | |
8691 | ef_mips_arch = 2; | |
8692 | break; | |
8693 | case E_MIPS_ARCH_3: | |
8694 | ef_mips_arch = 3; | |
8695 | break; | |
8696 | case E_MIPS_ARCH_4: | |
93d56215 | 8697 | ef_mips_arch = 4; |
acdb74a0 AC |
8698 | break; |
8699 | default: | |
93d56215 | 8700 | ef_mips_arch = 0; |
acdb74a0 AC |
8701 | break; |
8702 | } | |
f49e4e6d | 8703 | /* Determine the size of a pointer. */ |
acdb74a0 | 8704 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
8705 | fprintf_unfiltered (file, |
8706 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 8707 | tdep->elf_flags); |
4b9b3959 | 8708 | fprintf_unfiltered (file, |
acdb74a0 AC |
8709 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
8710 | ef_mips_32bitmode); | |
8711 | fprintf_unfiltered (file, | |
8712 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
8713 | ef_mips_arch); | |
8714 | fprintf_unfiltered (file, | |
8715 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 8716 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b | 8717 | fprintf_unfiltered (file, |
025bb325 MS |
8718 | "mips_dump_tdep: " |
8719 | "mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 8720 | mips_mask_address_p (tdep), |
4014092b | 8721 | tdep->default_mask_address_p); |
c2d11a7d | 8722 | } |
4b9b3959 AC |
8723 | fprintf_unfiltered (file, |
8724 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
8725 | MIPS_DEFAULT_FPU_TYPE, | |
8726 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
8727 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
8728 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
8729 | : "???")); | |
74ed0bb4 MD |
8730 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
8731 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
8732 | fprintf_unfiltered (file, |
8733 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 MD |
8734 | MIPS_FPU_TYPE (gdbarch), |
8735 | (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" | |
8736 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" | |
8737 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" | |
4b9b3959 | 8738 | : "???")); |
c2d11a7d JM |
8739 | } |
8740 | ||
025bb325 | 8741 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 8742 | |
c906108c | 8743 | void |
acdb74a0 | 8744 | _initialize_mips_tdep (void) |
c906108c SS |
8745 | { |
8746 | static struct cmd_list_element *mipsfpulist = NULL; | |
8747 | struct cmd_list_element *c; | |
8748 | ||
6d82d43b | 8749 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
8750 | if (MIPS_ABI_LAST + 1 |
8751 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 8752 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 8753 | |
4b9b3959 | 8754 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 8755 | |
8d5f9dcb DJ |
8756 | mips_pdr_data = register_objfile_data (); |
8757 | ||
4eb0ad19 DJ |
8758 | /* Create feature sets with the appropriate properties. The values |
8759 | are not important. */ | |
8760 | mips_tdesc_gp32 = allocate_target_description (); | |
8761 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
8762 | ||
8763 | mips_tdesc_gp64 = allocate_target_description (); | |
8764 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
8765 | ||
025bb325 | 8766 | /* Add root prefix command for all "set mips"/"show mips" commands. */ |
a5ea2558 | 8767 | add_prefix_cmd ("mips", no_class, set_mips_command, |
1bedd215 | 8768 | _("Various MIPS specific commands."), |
a5ea2558 AC |
8769 | &setmipscmdlist, "set mips ", 0, &setlist); |
8770 | ||
8771 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 8772 | _("Various MIPS specific commands."), |
a5ea2558 AC |
8773 | &showmipscmdlist, "show mips ", 0, &showlist); |
8774 | ||
025bb325 | 8775 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
8776 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
8777 | &mips_abi_string, _("\ | |
8778 | Set the MIPS ABI used by this program."), _("\ | |
8779 | Show the MIPS ABI used by this program."), _("\ | |
8780 | This option can be set to one of:\n\ | |
8781 | auto - the default ABI associated with the current binary\n\ | |
8782 | o32\n\ | |
8783 | o64\n\ | |
8784 | n32\n\ | |
8785 | n64\n\ | |
8786 | eabi32\n\ | |
8787 | eabi64"), | |
8788 | mips_abi_update, | |
8789 | show_mips_abi, | |
8790 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 8791 | |
4cc0665f MR |
8792 | /* Allow the user to set the ISA to assume for compressed code if ELF |
8793 | file flags don't tell or there is no program file selected. This | |
8794 | setting is updated whenever unambiguous ELF file flags are interpreted, | |
8795 | and carried over to subsequent sessions. */ | |
8796 | add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings, | |
8797 | &mips_compression_string, _("\ | |
8798 | Set the compressed ISA encoding used by MIPS code."), _("\ | |
8799 | Show the compressed ISA encoding used by MIPS code."), _("\ | |
8800 | Select the compressed ISA encoding used in functions that have no symbol\n\ | |
8801 | information available. The encoding can be set to either of:\n\ | |
8802 | mips16\n\ | |
8803 | micromips\n\ | |
8804 | and is updated automatically from ELF file flags if available."), | |
8805 | mips_abi_update, | |
8806 | show_mips_compression, | |
8807 | &setmipscmdlist, &showmipscmdlist); | |
8808 | ||
c906108c SS |
8809 | /* Let the user turn off floating point and set the fence post for |
8810 | heuristic_proc_start. */ | |
8811 | ||
8812 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 8813 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
8814 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
8815 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 8816 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
8817 | &mipsfpulist); |
8818 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 8819 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
8820 | &mipsfpulist); |
8821 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
8822 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
8823 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
8824 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 8825 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
8826 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
8827 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
8828 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
8829 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 8830 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
8831 | &mipsfpulist); |
8832 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 8833 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
8834 | &showlist); |
8835 | ||
c906108c SS |
8836 | /* We really would like to have both "0" and "unlimited" work, but |
8837 | command.c doesn't deal with that. So make it a var_zinteger | |
8838 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 8839 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
8840 | &heuristic_fence_post, _("\ |
8841 | Set the distance searched for the start of a function."), _("\ | |
8842 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
8843 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
8844 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 8845 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 8846 | reinit_frame_cache_sfunc, |
025bb325 MS |
8847 | NULL, /* FIXME: i18n: The distance searched for |
8848 | the start of a function is %s. */ | |
6bcadd06 | 8849 | &setlist, &showlist); |
c906108c SS |
8850 | |
8851 | /* Allow the user to control whether the upper bits of 64-bit | |
8852 | addresses should be zeroed. */ | |
7915a72c AC |
8853 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
8854 | &mask_address_var, _("\ | |
8855 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
8856 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
cce7e648 | 8857 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
7915a72c | 8858 | allow GDB to determine the correct value."), |
08546159 AC |
8859 | NULL, show_mask_address, |
8860 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
8861 | |
8862 | /* Allow the user to control the size of 32 bit registers within the | |
8863 | raw remote packet. */ | |
b3f42336 | 8864 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
8865 | &mips64_transfers_32bit_regs_p, _("\ |
8866 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
8867 | _("\ | |
8868 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
8869 | _("\ | |
719ec221 AC |
8870 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
8871 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 8872 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 8873 | set_mips64_transfers_32bit_regs, |
025bb325 MS |
8874 | NULL, /* FIXME: i18n: Compatibility with 64-bit |
8875 | MIPS target that transfers 32-bit | |
8876 | quantities is %s. */ | |
7915a72c | 8877 | &setlist, &showlist); |
9ace0497 | 8878 | |
025bb325 | 8879 | /* Debug this files internals. */ |
6bcadd06 | 8880 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
8881 | &mips_debug, _("\ |
8882 | Set mips debugging."), _("\ | |
8883 | Show mips debugging."), _("\ | |
8884 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 8885 | NULL, |
025bb325 MS |
8886 | NULL, /* FIXME: i18n: Mips debugging is |
8887 | currently %s. */ | |
6bcadd06 | 8888 | &setdebuglist, &showdebuglist); |
c906108c | 8889 | } |