Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a | 3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
16e109ca AC |
4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software |
5 | Foundation, Inc. | |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2 of the License, or | |
15 | (at your option) any later version. | |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b JM |
22 | You should have received a copy of the GNU General Public License |
23 | along with this program; if not, write to the Free Software | |
24 | Foundation, Inc., 59 Temple Place - Suite 330, | |
25 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
26 | |
27 | #include "defs.h" | |
28 | #include "gdb_string.h" | |
5e2e9765 | 29 | #include "gdb_assert.h" |
c906108c SS |
30 | #include "frame.h" |
31 | #include "inferior.h" | |
32 | #include "symtab.h" | |
33 | #include "value.h" | |
34 | #include "gdbcmd.h" | |
35 | #include "language.h" | |
36 | #include "gdbcore.h" | |
37 | #include "symfile.h" | |
38 | #include "objfiles.h" | |
39 | #include "gdbtypes.h" | |
40 | #include "target.h" | |
28d069e6 | 41 | #include "arch-utils.h" |
4e052eda | 42 | #include "regcache.h" |
70f80edf | 43 | #include "osabi.h" |
d1973055 | 44 | #include "mips-tdep.h" |
fe898f56 | 45 | #include "block.h" |
a4b8ebc8 | 46 | #include "reggroups.h" |
c906108c | 47 | #include "opcode/mips.h" |
c2d11a7d JM |
48 | #include "elf/mips.h" |
49 | #include "elf-bfd.h" | |
2475bac3 | 50 | #include "symcat.h" |
a4b8ebc8 | 51 | #include "sim-regno.h" |
a89aa300 | 52 | #include "dis-asm.h" |
edfae063 AC |
53 | #include "frame-unwind.h" |
54 | #include "frame-base.h" | |
55 | #include "trad-frame.h" | |
7d9b040b | 56 | #include "infcall.h" |
fed7ba43 | 57 | #include "floatformat.h" |
c906108c | 58 | |
8d5f9dcb DJ |
59 | static const struct objfile_data *mips_pdr_data; |
60 | ||
5bbcb741 | 61 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 62 | |
dd824b04 DJ |
63 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
64 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
65 | #define ST0_FR (1 << 26) | |
66 | ||
b0069a17 AC |
67 | /* The sizes of floating point registers. */ |
68 | ||
69 | enum | |
70 | { | |
71 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
72 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
73 | }; | |
74 | ||
0dadbba0 | 75 | |
2e4ebe70 DJ |
76 | static const char *mips_abi_string; |
77 | ||
78 | static const char *mips_abi_strings[] = { | |
79 | "auto", | |
80 | "n32", | |
81 | "o32", | |
28d169de | 82 | "n64", |
2e4ebe70 DJ |
83 | "o64", |
84 | "eabi32", | |
85 | "eabi64", | |
86 | NULL | |
87 | }; | |
88 | ||
cce74817 | 89 | struct frame_extra_info |
6d82d43b AC |
90 | { |
91 | mips_extra_func_info_t proc_desc; | |
92 | int num_args; | |
93 | }; | |
cce74817 | 94 | |
d929b26f AC |
95 | /* Various MIPS ISA options (related to stack analysis) can be |
96 | overridden dynamically. Establish an enum/array for managing | |
97 | them. */ | |
98 | ||
53904c9e AC |
99 | static const char size_auto[] = "auto"; |
100 | static const char size_32[] = "32"; | |
101 | static const char size_64[] = "64"; | |
d929b26f | 102 | |
53904c9e | 103 | static const char *size_enums[] = { |
d929b26f AC |
104 | size_auto, |
105 | size_32, | |
106 | size_64, | |
a5ea2558 AC |
107 | 0 |
108 | }; | |
109 | ||
7a292a7a | 110 | /* Some MIPS boards don't support floating point while others only |
ceae6e75 | 111 | support single-precision floating-point operations. */ |
c906108c SS |
112 | |
113 | enum mips_fpu_type | |
6d82d43b AC |
114 | { |
115 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
116 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
117 | MIPS_FPU_NONE /* No floating point. */ | |
118 | }; | |
c906108c SS |
119 | |
120 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
121 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
122 | #endif | |
123 | static int mips_fpu_type_auto = 1; | |
124 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 125 | |
9ace0497 | 126 | static int mips_debug = 0; |
7a292a7a | 127 | |
c2d11a7d JM |
128 | /* MIPS specific per-architecture information */ |
129 | struct gdbarch_tdep | |
6d82d43b AC |
130 | { |
131 | /* from the elf header */ | |
132 | int elf_flags; | |
133 | ||
134 | /* mips options */ | |
135 | enum mips_abi mips_abi; | |
136 | enum mips_abi found_abi; | |
137 | enum mips_fpu_type mips_fpu_type; | |
138 | int mips_last_arg_regnum; | |
139 | int mips_last_fp_arg_regnum; | |
6d82d43b AC |
140 | int default_mask_address_p; |
141 | /* Is the target using 64-bit raw integer registers but only | |
142 | storing a left-aligned 32-bit value in each? */ | |
143 | int mips64_transfers_32bit_regs_p; | |
144 | /* Indexes for various registers. IRIX and embedded have | |
145 | different values. This contains the "public" fields. Don't | |
146 | add any that do not need to be public. */ | |
147 | const struct mips_regnum *regnum; | |
148 | /* Register names table for the current register set. */ | |
149 | const char **mips_processor_reg_names; | |
150 | }; | |
c2d11a7d | 151 | |
fed7ba43 JB |
152 | static int |
153 | n32n64_floatformat_always_valid (const struct floatformat *fmt, | |
154 | const char *from) | |
155 | { | |
156 | return 1; | |
157 | } | |
158 | ||
159 | /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long. | |
160 | They are implemented as a pair of 64bit doubles where the high | |
161 | part holds the result of the operation rounded to double, and | |
162 | the low double holds the difference between the exact result and | |
163 | the rounded result. So "high" + "low" contains the result with | |
164 | added precision. Unfortunately, the floatformat structure used | |
165 | by GDB is not powerful enough to describe this format. As a temporary | |
166 | measure, we define a 128bit floatformat that only uses the high part. | |
167 | We lose a bit of precision but that's probably the best we can do | |
168 | for now with the current infrastructure. */ | |
169 | ||
170 | static const struct floatformat floatformat_n32n64_long_double_big = | |
171 | { | |
172 | floatformat_big, 128, 0, 1, 11, 1023, 2047, 12, 52, | |
173 | floatformat_intbit_no, | |
174 | "floatformat_ieee_double_big", | |
175 | n32n64_floatformat_always_valid | |
176 | }; | |
177 | ||
56cea623 AC |
178 | const struct mips_regnum * |
179 | mips_regnum (struct gdbarch *gdbarch) | |
180 | { | |
181 | return gdbarch_tdep (gdbarch)->regnum; | |
182 | } | |
183 | ||
184 | static int | |
185 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
186 | { | |
187 | return mips_regnum (gdbarch)->fp0 + 12; | |
188 | } | |
189 | ||
0dadbba0 | 190 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 191 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 192 | |
c2d11a7d | 193 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 194 | |
c2d11a7d | 195 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 196 | |
c2d11a7d | 197 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 198 | |
95404a3e AC |
199 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
200 | functions to test, set, or clear bit 0 of addresses. */ | |
201 | ||
202 | static CORE_ADDR | |
203 | is_mips16_addr (CORE_ADDR addr) | |
204 | { | |
205 | return ((addr) & 1); | |
206 | } | |
207 | ||
95404a3e AC |
208 | static CORE_ADDR |
209 | unmake_mips16_addr (CORE_ADDR addr) | |
210 | { | |
211 | return ((addr) & ~1); | |
212 | } | |
213 | ||
22540ece AC |
214 | /* Return the contents of register REGNUM as a signed integer. */ |
215 | ||
216 | static LONGEST | |
217 | read_signed_register (int regnum) | |
218 | { | |
1d93fe1a AC |
219 | LONGEST val; |
220 | regcache_cooked_read_signed (current_regcache, regnum, &val); | |
221 | return val; | |
22540ece AC |
222 | } |
223 | ||
224 | static LONGEST | |
225 | read_signed_register_pid (int regnum, ptid_t ptid) | |
226 | { | |
227 | ptid_t save_ptid; | |
228 | LONGEST retval; | |
229 | ||
230 | if (ptid_equal (ptid, inferior_ptid)) | |
231 | return read_signed_register (regnum); | |
232 | ||
233 | save_ptid = inferior_ptid; | |
234 | ||
235 | inferior_ptid = ptid; | |
236 | ||
237 | retval = read_signed_register (regnum); | |
238 | ||
239 | inferior_ptid = save_ptid; | |
240 | ||
241 | return retval; | |
242 | } | |
243 | ||
d1973055 KB |
244 | /* Return the MIPS ABI associated with GDBARCH. */ |
245 | enum mips_abi | |
246 | mips_abi (struct gdbarch *gdbarch) | |
247 | { | |
248 | return gdbarch_tdep (gdbarch)->mips_abi; | |
249 | } | |
250 | ||
4246e332 | 251 | int |
1b13c4f6 | 252 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 AC |
253 | { |
254 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word | |
255 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
256 | } | |
257 | ||
480d3dd2 AC |
258 | /* Return the currently configured (or set) saved register size. */ |
259 | ||
1b13c4f6 | 260 | static const char *mips_abi_regsize_string = size_auto; |
480d3dd2 | 261 | |
d929b26f | 262 | static unsigned int |
13326b4e | 263 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 264 | { |
1b13c4f6 | 265 | if (mips_abi_regsize_string == size_auto) |
13326b4e AC |
266 | switch (mips_abi (gdbarch)) |
267 | { | |
268 | case MIPS_ABI_EABI32: | |
269 | case MIPS_ABI_O32: | |
270 | return 4; | |
271 | case MIPS_ABI_N32: | |
272 | case MIPS_ABI_N64: | |
273 | case MIPS_ABI_O64: | |
274 | case MIPS_ABI_EABI64: | |
275 | return 8; | |
276 | case MIPS_ABI_UNKNOWN: | |
277 | case MIPS_ABI_LAST: | |
278 | default: | |
279 | internal_error (__FILE__, __LINE__, "bad switch"); | |
280 | } | |
1b13c4f6 | 281 | else if (mips_abi_regsize_string == size_64) |
d929b26f | 282 | return 8; |
1b13c4f6 | 283 | else /* if (mips_abi_regsize_string == size_32) */ |
d929b26f AC |
284 | return 4; |
285 | } | |
286 | ||
71b8ef93 | 287 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 288 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 289 | "info" field is used for this purpose. |
5a89d8aa MS |
290 | |
291 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
292 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
293 | minimal symbol to mark it as a 16-bit function | |
294 | ||
f594e5e9 | 295 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 296 | |
5a89d8aa | 297 | static void |
6d82d43b AC |
298 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
299 | { | |
300 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
301 | { | |
302 | MSYMBOL_INFO (msym) = (char *) | |
303 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
304 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
305 | } | |
5a89d8aa MS |
306 | } |
307 | ||
71b8ef93 MS |
308 | static int |
309 | msymbol_is_special (struct minimal_symbol *msym) | |
310 | { | |
311 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
312 | } | |
313 | ||
88658117 AC |
314 | /* XFER a value from the big/little/left end of the register. |
315 | Depending on the size of the value it might occupy the entire | |
316 | register or just part of it. Make an allowance for this, aligning | |
317 | things accordingly. */ | |
318 | ||
319 | static void | |
320 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
6d82d43b AC |
321 | enum bfd_endian endian, bfd_byte * in, |
322 | const bfd_byte * out, int buf_offset) | |
88658117 | 323 | { |
88658117 | 324 | int reg_offset = 0; |
a4b8ebc8 | 325 | gdb_assert (reg_num >= NUM_REGS); |
cb1d2653 AC |
326 | /* Need to transfer the left or right part of the register, based on |
327 | the targets byte order. */ | |
88658117 AC |
328 | switch (endian) |
329 | { | |
330 | case BFD_ENDIAN_BIG: | |
719ec221 | 331 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
332 | break; |
333 | case BFD_ENDIAN_LITTLE: | |
334 | reg_offset = 0; | |
335 | break; | |
6d82d43b | 336 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
337 | reg_offset = 0; |
338 | break; | |
339 | default: | |
340 | internal_error (__FILE__, __LINE__, "bad switch"); | |
341 | } | |
342 | if (mips_debug) | |
cb1d2653 AC |
343 | fprintf_unfiltered (gdb_stderr, |
344 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
345 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
346 | if (mips_debug && out != NULL) |
347 | { | |
348 | int i; | |
cb1d2653 | 349 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 350 | for (i = 0; i < length; i++) |
cb1d2653 | 351 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
352 | } |
353 | if (in != NULL) | |
6d82d43b AC |
354 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
355 | in + buf_offset); | |
88658117 | 356 | if (out != NULL) |
6d82d43b AC |
357 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
358 | out + buf_offset); | |
88658117 AC |
359 | if (mips_debug && in != NULL) |
360 | { | |
361 | int i; | |
cb1d2653 | 362 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 363 | for (i = 0; i < length; i++) |
cb1d2653 | 364 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
365 | } |
366 | if (mips_debug) | |
367 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
368 | } | |
369 | ||
dd824b04 DJ |
370 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
371 | compatiblity mode. A return value of 1 means that we have | |
372 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
373 | ||
374 | static int | |
375 | mips2_fp_compat (void) | |
376 | { | |
377 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
378 | meaningful. */ | |
6d82d43b AC |
379 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == |
380 | 4) | |
dd824b04 DJ |
381 | return 0; |
382 | ||
383 | #if 0 | |
384 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
385 | in all the places we deal with FP registers. PR gdb/413. */ | |
386 | /* Otherwise check the FR bit in the status register - it controls | |
387 | the FP compatiblity mode. If it is clear we are in compatibility | |
388 | mode. */ | |
389 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
390 | return 1; | |
391 | #endif | |
361d1df0 | 392 | |
dd824b04 DJ |
393 | return 0; |
394 | } | |
395 | ||
d929b26f | 396 | /* The amount of space reserved on the stack for registers. This is |
1b13c4f6 | 397 | different to MIPS_ABI_REGSIZE as it determines the alignment of |
d929b26f AC |
398 | data allocated after the registers have run out. */ |
399 | ||
53904c9e | 400 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
401 | |
402 | static unsigned int | |
13326b4e | 403 | mips_stack_argsize (struct gdbarch *gdbarch) |
d929b26f AC |
404 | { |
405 | if (mips_stack_argsize_string == size_auto) | |
13326b4e | 406 | return mips_abi_regsize (gdbarch); |
d929b26f AC |
407 | else if (mips_stack_argsize_string == size_64) |
408 | return 8; | |
6d82d43b | 409 | else /* if (mips_stack_argsize_string == size_32) */ |
d929b26f AC |
410 | return 4; |
411 | } | |
412 | ||
7a292a7a | 413 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 414 | |
c9343fd1 | 415 | struct mips_frame_cache; |
eec63939 AC |
416 | static mips_extra_func_info_t non_heuristic_proc_desc (CORE_ADDR pc, |
417 | CORE_ADDR *addrptr); | |
c906108c | 418 | |
a14ed312 | 419 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 420 | |
a14ed312 | 421 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 422 | |
a14ed312 | 423 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 424 | |
67b2c998 DJ |
425 | static struct type *mips_float_register_type (void); |
426 | static struct type *mips_double_register_type (void); | |
427 | ||
acdb74a0 AC |
428 | /* The list of available "set mips " and "show mips " commands */ |
429 | ||
430 | static struct cmd_list_element *setmipscmdlist = NULL; | |
431 | static struct cmd_list_element *showmipscmdlist = NULL; | |
432 | ||
5e2e9765 KB |
433 | /* Integer registers 0 thru 31 are handled explicitly by |
434 | mips_register_name(). Processor specific registers 32 and above | |
691c0433 AC |
435 | are listed in the followign tables. */ |
436 | ||
6d82d43b AC |
437 | enum |
438 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
439 | |
440 | /* Generic MIPS. */ | |
441 | ||
442 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
443 | "sr", "lo", "hi", "bad", "cause", "pc", |
444 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
445 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
446 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
447 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
448 | "fsr", "fir", "" /*"fp" */ , "", | |
449 | "", "", "", "", "", "", "", "", | |
450 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
451 | }; |
452 | ||
453 | /* Names of IDT R3041 registers. */ | |
454 | ||
455 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
456 | "sr", "lo", "hi", "bad", "cause", "pc", |
457 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
458 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
459 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
460 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
461 | "fsr", "fir", "", /*"fp" */ "", | |
462 | "", "", "bus", "ccfg", "", "", "", "", | |
463 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
464 | }; |
465 | ||
466 | /* Names of tx39 registers. */ | |
467 | ||
468 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
469 | "sr", "lo", "hi", "bad", "cause", "pc", |
470 | "", "", "", "", "", "", "", "", | |
471 | "", "", "", "", "", "", "", "", | |
472 | "", "", "", "", "", "", "", "", | |
473 | "", "", "", "", "", "", "", "", | |
474 | "", "", "", "", | |
475 | "", "", "", "", "", "", "", "", | |
476 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
477 | }; |
478 | ||
479 | /* Names of IRIX registers. */ | |
480 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
481 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
482 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
483 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
484 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
485 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
486 | }; |
487 | ||
cce74817 | 488 | |
5e2e9765 | 489 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 490 | static const char * |
5e2e9765 | 491 | mips_register_name (int regno) |
cce74817 | 492 | { |
691c0433 | 493 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
494 | /* GPR names for all ABIs other than n32/n64. */ |
495 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
496 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
497 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
498 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
499 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
500 | }; |
501 | ||
502 | /* GPR names for n32 and n64 ABIs. */ | |
503 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
504 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
505 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
506 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
507 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
508 | }; |
509 | ||
510 | enum mips_abi abi = mips_abi (current_gdbarch); | |
511 | ||
a4b8ebc8 AC |
512 | /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then |
513 | don't make the raw register names visible. */ | |
514 | int rawnum = regno % NUM_REGS; | |
515 | if (regno < NUM_REGS) | |
516 | return ""; | |
517 | ||
5e2e9765 KB |
518 | /* The MIPS integer registers are always mapped from 0 to 31. The |
519 | names of the registers (which reflects the conventions regarding | |
520 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 521 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
522 | { |
523 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 524 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 525 | else |
a4b8ebc8 | 526 | return mips_gpr_names[rawnum]; |
5e2e9765 | 527 | } |
a4b8ebc8 | 528 | else if (32 <= rawnum && rawnum < NUM_REGS) |
691c0433 AC |
529 | { |
530 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
531 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
532 | } | |
5e2e9765 KB |
533 | else |
534 | internal_error (__FILE__, __LINE__, | |
a4b8ebc8 | 535 | "mips_register_name: bad register number %d", rawnum); |
cce74817 | 536 | } |
5e2e9765 | 537 | |
a4b8ebc8 | 538 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 539 | |
a4b8ebc8 AC |
540 | static int |
541 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
542 | struct reggroup *reggroup) | |
543 | { | |
544 | int vector_p; | |
545 | int float_p; | |
546 | int raw_p; | |
547 | int rawnum = regnum % NUM_REGS; | |
548 | int pseudo = regnum / NUM_REGS; | |
549 | if (reggroup == all_reggroup) | |
550 | return pseudo; | |
551 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
552 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
553 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
554 | (gdbarch), as not all architectures are multi-arch. */ | |
555 | raw_p = rawnum < NUM_REGS; | |
6d82d43b | 556 | if (REGISTER_NAME (regnum) == NULL || REGISTER_NAME (regnum)[0] == '\0') |
a4b8ebc8 AC |
557 | return 0; |
558 | if (reggroup == float_reggroup) | |
559 | return float_p && pseudo; | |
560 | if (reggroup == vector_reggroup) | |
561 | return vector_p && pseudo; | |
562 | if (reggroup == general_reggroup) | |
563 | return (!vector_p && !float_p) && pseudo; | |
564 | /* Save the pseudo registers. Need to make certain that any code | |
565 | extracting register values from a saved register cache also uses | |
566 | pseudo registers. */ | |
567 | if (reggroup == save_reggroup) | |
568 | return raw_p && pseudo; | |
569 | /* Restore the same pseudo register. */ | |
570 | if (reggroup == restore_reggroup) | |
571 | return raw_p && pseudo; | |
6d82d43b | 572 | return 0; |
a4b8ebc8 AC |
573 | } |
574 | ||
575 | /* Map the symbol table registers which live in the range [1 * | |
576 | NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw | |
47ebcfbe | 577 | registers. Take care of alignment and size problems. */ |
c5aa993b | 578 | |
a4b8ebc8 AC |
579 | static void |
580 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
581 | int cookednum, void *buf) | |
582 | { | |
47ebcfbe | 583 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 584 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 585 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 586 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
587 | else if (register_size (gdbarch, rawnum) > |
588 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
589 | { |
590 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
591 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
592 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); | |
593 | else | |
594 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
595 | } | |
596 | else | |
597 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 AC |
598 | } |
599 | ||
600 | static void | |
6d82d43b AC |
601 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
602 | struct regcache *regcache, int cookednum, | |
603 | const void *buf) | |
a4b8ebc8 | 604 | { |
47ebcfbe | 605 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 606 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 607 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 608 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
609 | else if (register_size (gdbarch, rawnum) > |
610 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
611 | { |
612 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
613 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
614 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); | |
615 | else | |
616 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
617 | } | |
618 | else | |
619 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 | 620 | } |
c5aa993b | 621 | |
c906108c | 622 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 623 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
624 | |
625 | /* Heuristic_proc_start may hunt through the text section for a long | |
626 | time across a 2400 baud serial line. Allows the user to limit this | |
627 | search. */ | |
628 | ||
629 | static unsigned int heuristic_fence_post = 0; | |
630 | ||
c5aa993b JM |
631 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
632 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
633 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
634 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
635 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
636 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
637 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
638 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
639 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
640 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
6c0d6680 DJ |
641 | /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, |
642 | this will corrupt pdr.iline. Fortunately we don't use it. */ | |
c906108c SS |
643 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
644 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
c906108c | 645 | |
46cd78fb | 646 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
647 | register N. NOTE: This defines the pseudo register type so need to |
648 | rebuild the architecture vector. */ | |
43e526b9 JM |
649 | |
650 | static int mips64_transfers_32bit_regs_p = 0; | |
651 | ||
719ec221 AC |
652 | static void |
653 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
654 | struct cmd_list_element *c) | |
43e526b9 | 655 | { |
719ec221 AC |
656 | struct gdbarch_info info; |
657 | gdbarch_info_init (&info); | |
658 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
659 | instead of relying on globals. Doing that would let generic code | |
660 | handle the search for this specific architecture. */ | |
661 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 662 | { |
719ec221 AC |
663 | mips64_transfers_32bit_regs_p = 0; |
664 | error ("32-bit compatibility mode not supported"); | |
a4b8ebc8 | 665 | } |
a4b8ebc8 AC |
666 | } |
667 | ||
47ebcfbe | 668 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 669 | |
ff2e87ac AC |
670 | static int |
671 | mips_convert_register_p (int regnum, struct type *type) | |
672 | { | |
673 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
719ec221 | 674 | && register_size (current_gdbarch, regnum) == 4 |
87783b8b AC |
675 | && (regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
676 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32 | |
6d82d43b | 677 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
678 | } |
679 | ||
42c466d7 | 680 | static void |
ff2e87ac AC |
681 | mips_register_to_value (struct frame_info *frame, int regnum, |
682 | struct type *type, void *to) | |
102182a9 | 683 | { |
7f5f525d AC |
684 | get_frame_register (frame, regnum + 0, (char *) to + 4); |
685 | get_frame_register (frame, regnum + 1, (char *) to + 0); | |
102182a9 MS |
686 | } |
687 | ||
42c466d7 | 688 | static void |
ff2e87ac AC |
689 | mips_value_to_register (struct frame_info *frame, int regnum, |
690 | struct type *type, const void *from) | |
102182a9 | 691 | { |
ff2e87ac AC |
692 | put_frame_register (frame, regnum + 0, (const char *) from + 4); |
693 | put_frame_register (frame, regnum + 1, (const char *) from + 0); | |
102182a9 MS |
694 | } |
695 | ||
a4b8ebc8 AC |
696 | /* Return the GDB type object for the "standard" data type of data in |
697 | register REG. */ | |
78fde5f8 KB |
698 | |
699 | static struct type * | |
a4b8ebc8 AC |
700 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
701 | { | |
5ef80fb0 | 702 | gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS); |
56cea623 AC |
703 | if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
704 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 705 | { |
5ef80fb0 | 706 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 707 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
5ef80fb0 AC |
708 | switch (gdbarch_byte_order (gdbarch)) |
709 | { | |
710 | case BFD_ENDIAN_BIG: | |
1b13c4f6 | 711 | if (mips_isa_regsize (gdbarch) == 4) |
5ef80fb0 AC |
712 | return builtin_type_ieee_single_big; |
713 | else | |
714 | return builtin_type_ieee_double_big; | |
715 | case BFD_ENDIAN_LITTLE: | |
1b13c4f6 | 716 | if (mips_isa_regsize (gdbarch) == 4) |
5ef80fb0 AC |
717 | return builtin_type_ieee_single_little; |
718 | else | |
719 | return builtin_type_ieee_double_little; | |
720 | case BFD_ENDIAN_UNKNOWN: | |
721 | default: | |
722 | internal_error (__FILE__, __LINE__, "bad switch"); | |
723 | } | |
a6425924 | 724 | } |
d5ac5a39 AC |
725 | else if (regnum < NUM_REGS) |
726 | { | |
727 | /* The raw or ISA registers. These are all sized according to | |
728 | the ISA regsize. */ | |
729 | if (mips_isa_regsize (gdbarch) == 4) | |
730 | return builtin_type_int32; | |
731 | else | |
732 | return builtin_type_int64; | |
733 | } | |
78fde5f8 | 734 | else |
d5ac5a39 AC |
735 | { |
736 | /* The cooked or ABI registers. These are sized according to | |
737 | the ABI (with a few complications). */ | |
738 | if (regnum >= (NUM_REGS | |
739 | + mips_regnum (current_gdbarch)->fp_control_status) | |
740 | && regnum <= NUM_REGS + LAST_EMBED_REGNUM) | |
741 | /* The pseudo/cooked view of the embedded registers is always | |
742 | 32-bit. The raw view is handled below. */ | |
743 | return builtin_type_int32; | |
744 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
745 | /* The target, while possibly using a 64-bit register buffer, | |
746 | is only transfering 32-bits of each integer register. | |
747 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
748 | return builtin_type_int32; | |
749 | else if (mips_abi_regsize (gdbarch) == 4) | |
750 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
751 | 32- or 64-bit). */ | |
752 | return builtin_type_int32; | |
753 | else | |
754 | /* 64-bit ABI. */ | |
755 | return builtin_type_int64; | |
756 | } | |
78fde5f8 KB |
757 | } |
758 | ||
bcb0cc15 MS |
759 | /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ |
760 | ||
761 | static CORE_ADDR | |
762 | mips_read_sp (void) | |
763 | { | |
f10683bb | 764 | return read_signed_register (MIPS_SP_REGNUM); |
bcb0cc15 MS |
765 | } |
766 | ||
c906108c | 767 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 768 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
769 | |
770 | static int | |
480d3dd2 | 771 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
772 | { |
773 | switch (mask_address_var) | |
774 | { | |
7f19b9a2 | 775 | case AUTO_BOOLEAN_TRUE: |
4014092b | 776 | return 1; |
7f19b9a2 | 777 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
778 | return 0; |
779 | break; | |
7f19b9a2 | 780 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 781 | return tdep->default_mask_address_p; |
4014092b | 782 | default: |
6d82d43b | 783 | internal_error (__FILE__, __LINE__, "mips_mask_address_p: bad switch"); |
4014092b | 784 | return -1; |
361d1df0 | 785 | } |
4014092b AC |
786 | } |
787 | ||
788 | static void | |
e9e68a56 | 789 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b | 790 | { |
480d3dd2 | 791 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4014092b AC |
792 | switch (mask_address_var) |
793 | { | |
7f19b9a2 | 794 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
795 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
796 | break; | |
7f19b9a2 | 797 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
798 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
799 | break; | |
7f19b9a2 | 800 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
801 | printf_filtered |
802 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
803 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
804 | break; |
805 | default: | |
6d82d43b | 806 | internal_error (__FILE__, __LINE__, "show_mask_address: bad switch"); |
4014092b | 807 | break; |
361d1df0 | 808 | } |
4014092b | 809 | } |
c906108c | 810 | |
c906108c SS |
811 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
812 | ||
0fe7e7c8 AC |
813 | int |
814 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
815 | { |
816 | struct minimal_symbol *sym; | |
817 | ||
818 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 819 | if (is_mips16_addr (memaddr)) |
c906108c SS |
820 | return 1; |
821 | ||
822 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
823 | the high bit of the info field. Use this to decide if the function is | |
824 | MIPS16 or normal MIPS. */ | |
825 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
826 | if (sym) | |
71b8ef93 | 827 | return msymbol_is_special (sym); |
c906108c SS |
828 | else |
829 | return 0; | |
830 | } | |
831 | ||
b2fa5097 | 832 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
833 | all registers should be sign extended for simplicity? */ |
834 | ||
835 | static CORE_ADDR | |
39f77062 | 836 | mips_read_pc (ptid_t ptid) |
6c997a34 | 837 | { |
b6cb9035 AC |
838 | return read_signed_register_pid (mips_regnum (current_gdbarch)->pc, ptid); |
839 | } | |
840 | ||
58dfe9ff AC |
841 | static CORE_ADDR |
842 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
843 | { | |
edfae063 AC |
844 | return frame_unwind_register_signed (next_frame, |
845 | NUM_REGS + mips_regnum (gdbarch)->pc); | |
846 | } | |
847 | ||
848 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
849 | dummy frame. The frame ID's base needs to match the TOS value | |
850 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
851 | breakpoint. */ | |
852 | ||
853 | static struct frame_id | |
854 | mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
855 | { | |
f10683bb | 856 | return frame_id_build (frame_unwind_register_signed (next_frame, NUM_REGS + MIPS_SP_REGNUM), |
edfae063 | 857 | frame_pc_unwind (next_frame)); |
58dfe9ff AC |
858 | } |
859 | ||
b6cb9035 AC |
860 | static void |
861 | mips_write_pc (CORE_ADDR pc, ptid_t ptid) | |
862 | { | |
863 | write_register_pid (mips_regnum (current_gdbarch)->pc, pc, ptid); | |
6c997a34 | 864 | } |
c906108c | 865 | |
c906108c SS |
866 | /* Fetch and return instruction from the specified location. If the PC |
867 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
868 | ||
869 | static t_inst | |
acdb74a0 | 870 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c | 871 | { |
4c7d22cb | 872 | char buf[MIPS32_INSN_SIZE]; |
c906108c SS |
873 | int instlen; |
874 | int status; | |
875 | ||
0fe7e7c8 | 876 | if (mips_pc_is_mips16 (addr)) |
c906108c | 877 | { |
4c7d22cb | 878 | instlen = MIPS16_INSN_SIZE; |
95404a3e | 879 | addr = unmake_mips16_addr (addr); |
c906108c SS |
880 | } |
881 | else | |
4c7d22cb | 882 | instlen = MIPS32_INSN_SIZE; |
1f602b35 | 883 | status = deprecated_read_memory_nobpt (addr, buf, instlen); |
c906108c SS |
884 | if (status) |
885 | memory_error (status, addr); | |
886 | return extract_unsigned_integer (buf, instlen); | |
887 | } | |
888 | ||
edfae063 AC |
889 | static ULONGEST |
890 | mips16_fetch_instruction (CORE_ADDR addr) | |
891 | { | |
4c7d22cb | 892 | char buf[MIPS16_INSN_SIZE]; |
edfae063 AC |
893 | int status; |
894 | ||
edfae063 | 895 | addr = unmake_mips16_addr (addr); |
4c7d22cb | 896 | status = deprecated_read_memory_nobpt (addr, buf, sizeof (buf)); |
edfae063 AC |
897 | if (status) |
898 | memory_error (status, addr); | |
4c7d22cb | 899 | return extract_unsigned_integer (buf, sizeof (buf)); |
edfae063 AC |
900 | } |
901 | ||
c906108c | 902 | /* These the fields of 32 bit mips instructions */ |
e135b889 DJ |
903 | #define mips32_op(x) (x >> 26) |
904 | #define itype_op(x) (x >> 26) | |
905 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 906 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 907 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 908 | |
e135b889 DJ |
909 | #define jtype_op(x) (x >> 26) |
910 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 911 | |
e135b889 DJ |
912 | #define rtype_op(x) (x >> 26) |
913 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
914 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
915 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
916 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
917 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
918 | |
919 | static CORE_ADDR | |
c5aa993b JM |
920 | mips32_relative_offset (unsigned long inst) |
921 | { | |
922 | long x; | |
923 | x = itype_immediate (inst); | |
924 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 925 | { |
c5aa993b | 926 | x |= 0xffff0000; /* sign extension */ |
c906108c | 927 | } |
c5aa993b JM |
928 | x = x << 2; |
929 | return x; | |
c906108c SS |
930 | } |
931 | ||
932 | /* Determine whate to set a single step breakpoint while considering | |
933 | branch prediction */ | |
5a89d8aa | 934 | static CORE_ADDR |
c5aa993b JM |
935 | mips32_next_pc (CORE_ADDR pc) |
936 | { | |
937 | unsigned long inst; | |
938 | int op; | |
939 | inst = mips_fetch_instruction (pc); | |
e135b889 | 940 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 941 | { |
e135b889 | 942 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 943 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 944 | { |
e135b889 | 945 | op = (itype_op (inst) & 0x03); |
c906108c SS |
946 | switch (op) |
947 | { | |
e135b889 DJ |
948 | case 0: /* BEQL */ |
949 | goto equal_branch; | |
950 | case 1: /* BNEL */ | |
951 | goto neq_branch; | |
952 | case 2: /* BLEZL */ | |
953 | goto less_branch; | |
954 | case 3: /* BGTZ */ | |
955 | goto greater_branch; | |
c5aa993b JM |
956 | default: |
957 | pc += 4; | |
c906108c SS |
958 | } |
959 | } | |
e135b889 | 960 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 961 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
962 | { |
963 | int tf = itype_rt (inst) & 0x01; | |
964 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b AC |
965 | int fcrcs = |
966 | read_signed_register (mips_regnum (current_gdbarch)-> | |
967 | fp_control_status); | |
e135b889 DJ |
968 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
969 | ||
970 | if (((cond >> cnum) & 0x01) == tf) | |
971 | pc += mips32_relative_offset (inst) + 4; | |
972 | else | |
973 | pc += 8; | |
974 | } | |
c5aa993b JM |
975 | else |
976 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
977 | } |
978 | else | |
c5aa993b JM |
979 | { /* This gets way messy */ |
980 | ||
c906108c | 981 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 982 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 983 | { |
c5aa993b JM |
984 | case 0: /* SPECIAL */ |
985 | op = rtype_funct (inst); | |
986 | switch (op) | |
987 | { | |
988 | case 8: /* JR */ | |
989 | case 9: /* JALR */ | |
6c997a34 AC |
990 | /* Set PC to that address */ |
991 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
992 | break; |
993 | default: | |
994 | pc += 4; | |
995 | } | |
996 | ||
6d82d43b | 997 | break; /* end SPECIAL */ |
c5aa993b | 998 | case 1: /* REGIMM */ |
c906108c | 999 | { |
e135b889 DJ |
1000 | op = itype_rt (inst); /* branch condition */ |
1001 | switch (op) | |
c906108c | 1002 | { |
c5aa993b | 1003 | case 0: /* BLTZ */ |
e135b889 DJ |
1004 | case 2: /* BLTZL */ |
1005 | case 16: /* BLTZAL */ | |
c5aa993b | 1006 | case 18: /* BLTZALL */ |
c906108c | 1007 | less_branch: |
6c997a34 | 1008 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
1009 | pc += mips32_relative_offset (inst) + 4; |
1010 | else | |
1011 | pc += 8; /* after the delay slot */ | |
1012 | break; | |
e135b889 | 1013 | case 1: /* BGEZ */ |
c5aa993b JM |
1014 | case 3: /* BGEZL */ |
1015 | case 17: /* BGEZAL */ | |
1016 | case 19: /* BGEZALL */ | |
6c997a34 | 1017 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
1018 | pc += mips32_relative_offset (inst) + 4; |
1019 | else | |
1020 | pc += 8; /* after the delay slot */ | |
1021 | break; | |
e135b889 | 1022 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1023 | default: |
1024 | pc += 4; | |
c906108c SS |
1025 | } |
1026 | } | |
6d82d43b | 1027 | break; /* end REGIMM */ |
c5aa993b JM |
1028 | case 2: /* J */ |
1029 | case 3: /* JAL */ | |
1030 | { | |
1031 | unsigned long reg; | |
1032 | reg = jtype_target (inst) << 2; | |
e135b889 | 1033 | /* Upper four bits get never changed... */ |
c5aa993b | 1034 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 1035 | } |
c5aa993b JM |
1036 | break; |
1037 | /* FIXME case JALX : */ | |
1038 | { | |
1039 | unsigned long reg; | |
1040 | reg = jtype_target (inst) << 2; | |
1041 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
1042 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1043 | } | |
c5aa993b | 1044 | break; /* The new PC will be alternate mode */ |
e135b889 | 1045 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1046 | equal_branch: |
6c997a34 AC |
1047 | if (read_signed_register (itype_rs (inst)) == |
1048 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1049 | pc += mips32_relative_offset (inst) + 4; |
1050 | else | |
1051 | pc += 8; | |
1052 | break; | |
e135b889 | 1053 | case 5: /* BNE, BNEL */ |
c5aa993b | 1054 | neq_branch: |
6c997a34 | 1055 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1056 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1057 | pc += mips32_relative_offset (inst) + 4; |
1058 | else | |
1059 | pc += 8; | |
1060 | break; | |
e135b889 | 1061 | case 6: /* BLEZ, BLEZL */ |
1fd8cd20 | 1062 | if (read_signed_register (itype_rs (inst)) <= 0) |
c5aa993b JM |
1063 | pc += mips32_relative_offset (inst) + 4; |
1064 | else | |
1065 | pc += 8; | |
1066 | break; | |
1067 | case 7: | |
e135b889 DJ |
1068 | default: |
1069 | greater_branch: /* BGTZ, BGTZL */ | |
1fd8cd20 | 1070 | if (read_signed_register (itype_rs (inst)) > 0) |
c5aa993b JM |
1071 | pc += mips32_relative_offset (inst) + 4; |
1072 | else | |
1073 | pc += 8; | |
1074 | break; | |
c5aa993b JM |
1075 | } /* switch */ |
1076 | } /* else */ | |
1077 | return pc; | |
1078 | } /* mips32_next_pc */ | |
c906108c SS |
1079 | |
1080 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1081 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1082 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1083 | We dont want to set a single step instruction on the extend instruction | |
1084 | either. | |
c5aa993b | 1085 | */ |
c906108c SS |
1086 | |
1087 | /* Lots of mips16 instruction formats */ | |
1088 | /* Predicting jumps requires itype,ritype,i8type | |
1089 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1090 | */ |
c906108c SS |
1091 | enum mips16_inst_fmts |
1092 | { | |
c5aa993b JM |
1093 | itype, /* 0 immediate 5,10 */ |
1094 | ritype, /* 1 5,3,8 */ | |
1095 | rrtype, /* 2 5,3,3,5 */ | |
1096 | rritype, /* 3 5,3,3,5 */ | |
1097 | rrrtype, /* 4 5,3,3,3,2 */ | |
1098 | rriatype, /* 5 5,3,3,1,4 */ | |
1099 | shifttype, /* 6 5,3,3,3,2 */ | |
1100 | i8type, /* 7 5,3,8 */ | |
1101 | i8movtype, /* 8 5,3,3,5 */ | |
1102 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1103 | i64type, /* 10 5,3,8 */ | |
1104 | ri64type, /* 11 5,3,3,5 */ | |
1105 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1106 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1107 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1108 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1109 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1110 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1111 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1112 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1113 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1114 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1115 | }; | |
12f02c2a AC |
1116 | /* I am heaping all the fields of the formats into one structure and |
1117 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1118 | struct upk_mips16 |
6d82d43b AC |
1119 | { |
1120 | CORE_ADDR offset; | |
1121 | unsigned int regx; /* Function in i8 type */ | |
1122 | unsigned int regy; | |
1123 | }; | |
c906108c SS |
1124 | |
1125 | ||
12f02c2a AC |
1126 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1127 | for the bits which make up the immediatate extension. */ | |
c906108c | 1128 | |
12f02c2a AC |
1129 | static CORE_ADDR |
1130 | extended_offset (unsigned int extension) | |
c906108c | 1131 | { |
12f02c2a | 1132 | CORE_ADDR value; |
c5aa993b JM |
1133 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1134 | value = value << 6; | |
1135 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1136 | value = value << 5; | |
1137 | value |= extension & 0x01f; /* extract 4:0 */ | |
1138 | return value; | |
c906108c SS |
1139 | } |
1140 | ||
1141 | /* Only call this function if you know that this is an extendable | |
1142 | instruction, It wont malfunction, but why make excess remote memory references? | |
1143 | If the immediate operands get sign extended or somthing, do it after | |
1144 | the extension is performed. | |
c5aa993b | 1145 | */ |
c906108c SS |
1146 | /* FIXME: Every one of these cases needs to worry about sign extension |
1147 | when the offset is to be used in relative addressing */ | |
1148 | ||
1149 | ||
12f02c2a | 1150 | static unsigned int |
c5aa993b | 1151 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1152 | { |
c5aa993b JM |
1153 | char buf[8]; |
1154 | pc &= 0xfffffffe; /* clear the low order bit */ | |
1155 | target_read_memory (pc, buf, 2); | |
1156 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1157 | } |
1158 | ||
1159 | static void | |
c5aa993b | 1160 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1161 | unsigned int extension, |
1162 | unsigned int inst, | |
6d82d43b | 1163 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1164 | { |
12f02c2a AC |
1165 | CORE_ADDR offset; |
1166 | int regx; | |
1167 | int regy; | |
1168 | switch (insn_format) | |
c906108c | 1169 | { |
c5aa993b | 1170 | case itype: |
c906108c | 1171 | { |
12f02c2a AC |
1172 | CORE_ADDR value; |
1173 | if (extension) | |
c5aa993b JM |
1174 | { |
1175 | value = extended_offset (extension); | |
1176 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1177 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1178 | } |
1179 | else | |
c5aa993b | 1180 | { |
12f02c2a | 1181 | value = inst & 0x7ff; |
c5aa993b | 1182 | /* FIXME : Consider sign extension */ |
c906108c | 1183 | } |
12f02c2a AC |
1184 | offset = value; |
1185 | regx = -1; | |
1186 | regy = -1; | |
c906108c | 1187 | } |
c5aa993b JM |
1188 | break; |
1189 | case ritype: | |
1190 | case i8type: | |
1191 | { /* A register identifier and an offset */ | |
c906108c SS |
1192 | /* Most of the fields are the same as I type but the |
1193 | immediate value is of a different length */ | |
12f02c2a AC |
1194 | CORE_ADDR value; |
1195 | if (extension) | |
c906108c | 1196 | { |
c5aa993b JM |
1197 | value = extended_offset (extension); |
1198 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1199 | value |= inst & 0xff; /* eleven bits from instruction */ |
1200 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1201 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1202 | { | |
1203 | value &= ~0x3fff; /* remove the sign bit */ | |
1204 | value = -value; | |
c906108c SS |
1205 | } |
1206 | } | |
c5aa993b JM |
1207 | else |
1208 | { | |
12f02c2a AC |
1209 | value = inst & 0xff; /* 8 bits */ |
1210 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1211 | /* FIXME: Do sign extension , this format needs it */ |
1212 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1213 | { | |
1214 | value &= 0xef; /* remove the sign bit */ | |
1215 | value = -value; | |
1216 | } | |
c5aa993b | 1217 | } |
12f02c2a AC |
1218 | offset = value; |
1219 | regy = -1; | |
c5aa993b | 1220 | break; |
c906108c | 1221 | } |
c5aa993b | 1222 | case jalxtype: |
c906108c | 1223 | { |
c5aa993b | 1224 | unsigned long value; |
12f02c2a AC |
1225 | unsigned int nexthalf; |
1226 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1227 | value = value << 16; |
1228 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1229 | value |= nexthalf; | |
12f02c2a AC |
1230 | offset = value; |
1231 | regx = -1; | |
1232 | regy = -1; | |
c5aa993b | 1233 | break; |
c906108c SS |
1234 | } |
1235 | default: | |
6d82d43b | 1236 | internal_error (__FILE__, __LINE__, "bad switch"); |
c906108c | 1237 | } |
12f02c2a AC |
1238 | upk->offset = offset; |
1239 | upk->regx = regx; | |
1240 | upk->regy = regy; | |
c906108c SS |
1241 | } |
1242 | ||
1243 | ||
c5aa993b JM |
1244 | static CORE_ADDR |
1245 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1246 | { |
c5aa993b | 1247 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1248 | } |
1249 | ||
12f02c2a AC |
1250 | static CORE_ADDR |
1251 | extended_mips16_next_pc (CORE_ADDR pc, | |
6d82d43b | 1252 | unsigned int extension, unsigned int insn) |
c906108c | 1253 | { |
12f02c2a AC |
1254 | int op = (insn >> 11); |
1255 | switch (op) | |
c906108c | 1256 | { |
6d82d43b | 1257 | case 2: /* Branch */ |
12f02c2a AC |
1258 | { |
1259 | CORE_ADDR offset; | |
1260 | struct upk_mips16 upk; | |
1261 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1262 | offset = upk.offset; | |
1263 | if (offset & 0x800) | |
1264 | { | |
1265 | offset &= 0xeff; | |
1266 | offset = -offset; | |
1267 | } | |
1268 | pc += (offset << 1) + 2; | |
1269 | break; | |
1270 | } | |
6d82d43b | 1271 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1272 | { |
1273 | struct upk_mips16 upk; | |
1274 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1275 | pc = add_offset_16 (pc, upk.offset); | |
1276 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1277 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1278 | else | |
1279 | pc |= 0x01; | |
1280 | break; | |
1281 | } | |
6d82d43b | 1282 | case 4: /* beqz */ |
12f02c2a AC |
1283 | { |
1284 | struct upk_mips16 upk; | |
1285 | int reg; | |
1286 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1287 | reg = read_signed_register (upk.regx); | |
1288 | if (reg == 0) | |
1289 | pc += (upk.offset << 1) + 2; | |
1290 | else | |
1291 | pc += 2; | |
1292 | break; | |
1293 | } | |
6d82d43b | 1294 | case 5: /* bnez */ |
12f02c2a AC |
1295 | { |
1296 | struct upk_mips16 upk; | |
1297 | int reg; | |
1298 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1299 | reg = read_signed_register (upk.regx); | |
1300 | if (reg != 0) | |
1301 | pc += (upk.offset << 1) + 2; | |
1302 | else | |
1303 | pc += 2; | |
1304 | break; | |
1305 | } | |
6d82d43b | 1306 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1307 | { |
1308 | struct upk_mips16 upk; | |
1309 | int reg; | |
1310 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1311 | /* upk.regx contains the opcode */ | |
1312 | reg = read_signed_register (24); /* Test register is 24 */ | |
1313 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1314 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1315 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1316 | pc += (upk.offset << 1) + 2; | |
1317 | else | |
1318 | pc += 2; | |
1319 | break; | |
1320 | } | |
6d82d43b | 1321 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1322 | { |
1323 | struct upk_mips16 upk; | |
1324 | /* upk.fmt = rrtype; */ | |
1325 | op = insn & 0x1f; | |
1326 | if (op == 0) | |
c5aa993b | 1327 | { |
12f02c2a AC |
1328 | int reg; |
1329 | upk.regx = (insn >> 8) & 0x07; | |
1330 | upk.regy = (insn >> 5) & 0x07; | |
1331 | switch (upk.regy) | |
c5aa993b | 1332 | { |
12f02c2a AC |
1333 | case 0: |
1334 | reg = upk.regx; | |
1335 | break; | |
1336 | case 1: | |
1337 | reg = 31; | |
6d82d43b | 1338 | break; /* Function return instruction */ |
12f02c2a AC |
1339 | case 2: |
1340 | reg = upk.regx; | |
1341 | break; | |
1342 | default: | |
1343 | reg = 31; | |
6d82d43b | 1344 | break; /* BOGUS Guess */ |
c906108c | 1345 | } |
12f02c2a | 1346 | pc = read_signed_register (reg); |
c906108c | 1347 | } |
12f02c2a | 1348 | else |
c5aa993b | 1349 | pc += 2; |
12f02c2a AC |
1350 | break; |
1351 | } | |
1352 | case 30: | |
1353 | /* This is an instruction extension. Fetch the real instruction | |
1354 | (which follows the extension) and decode things based on | |
1355 | that. */ | |
1356 | { | |
1357 | pc += 2; | |
1358 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1359 | break; | |
1360 | } | |
1361 | default: | |
1362 | { | |
1363 | pc += 2; | |
1364 | break; | |
1365 | } | |
c906108c | 1366 | } |
c5aa993b | 1367 | return pc; |
12f02c2a | 1368 | } |
c906108c | 1369 | |
5a89d8aa | 1370 | static CORE_ADDR |
12f02c2a AC |
1371 | mips16_next_pc (CORE_ADDR pc) |
1372 | { | |
1373 | unsigned int insn = fetch_mips_16 (pc); | |
1374 | return extended_mips16_next_pc (pc, 0, insn); | |
1375 | } | |
1376 | ||
1377 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1378 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1379 | It works by decoding the current instruction and predicting where a |
1380 | branch will go. This isnt hard because all the data is available. | |
1381 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1382 | CORE_ADDR |
1383 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1384 | { |
c5aa993b JM |
1385 | if (pc & 0x01) |
1386 | return mips16_next_pc (pc); | |
1387 | else | |
1388 | return mips32_next_pc (pc); | |
12f02c2a | 1389 | } |
c906108c | 1390 | |
edfae063 AC |
1391 | struct mips_frame_cache |
1392 | { | |
1393 | CORE_ADDR base; | |
1394 | struct trad_frame_saved_reg *saved_regs; | |
1395 | }; | |
1396 | ||
1397 | ||
1398 | static struct mips_frame_cache * | |
1399 | mips_mdebug_frame_cache (struct frame_info *next_frame, void **this_cache) | |
1400 | { | |
0d5febcc | 1401 | CORE_ADDR startaddr = 0; |
edfae063 AC |
1402 | mips_extra_func_info_t proc_desc; |
1403 | struct mips_frame_cache *cache; | |
1404 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
1405 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1406 | /* r0 bit means kernel trap */ | |
1407 | int kernel_trap; | |
1408 | /* What registers have been saved? Bitmasks. */ | |
1409 | unsigned long gen_mask, float_mask; | |
1410 | ||
1411 | if ((*this_cache) != NULL) | |
1412 | return (*this_cache); | |
1413 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); | |
1414 | (*this_cache) = cache; | |
1415 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
1416 | ||
1417 | /* Get the mdebug proc descriptor. */ | |
0d5febcc AC |
1418 | proc_desc = non_heuristic_proc_desc (frame_pc_unwind (next_frame), |
1419 | &startaddr); | |
1420 | /* Must be true. This is only called when the sniffer detected a | |
1421 | proc descriptor. */ | |
1422 | gdb_assert (proc_desc != NULL); | |
edfae063 AC |
1423 | |
1424 | /* Extract the frame's base. */ | |
1425 | cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) | |
1426 | + PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); | |
1427 | ||
1428 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; | |
1429 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1430 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
1431 | ||
9733cfe1 AC |
1432 | /* Must be true. The in_prologue case is left for the heuristic |
1433 | unwinder. This is always used on kernel traps. */ | |
1434 | gdb_assert (!in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc)) | |
1435 | || kernel_trap); | |
edfae063 AC |
1436 | |
1437 | /* Fill in the offsets for the registers which gen_mask says were | |
1438 | saved. */ | |
1439 | { | |
4fbbbd07 | 1440 | CORE_ADDR reg_position = (cache->base + PROC_REG_OFFSET (proc_desc)); |
edfae063 | 1441 | int ireg; |
4fbbbd07 | 1442 | |
edfae063 AC |
1443 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) |
1444 | if (gen_mask & 0x80000000) | |
1445 | { | |
1446 | cache->saved_regs[NUM_REGS + ireg].addr = reg_position; | |
13326b4e | 1447 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1448 | } |
1449 | } | |
1450 | ||
1451 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse | |
1452 | order of that normally used by gcc. Therefore, we have to fetch | |
1453 | the first instruction of the function, and if it's an entry | |
1454 | instruction that saves $s0 or $s1, correct their saved addresses. */ | |
0fe7e7c8 | 1455 | if (mips_pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) |
edfae063 AC |
1456 | { |
1457 | ULONGEST inst = mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
1458 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) | |
1459 | /* entry */ | |
1460 | { | |
1461 | int reg; | |
1462 | int sreg_count = (inst >> 6) & 3; | |
1463 | ||
1464 | /* Check if the ra register was pushed on the stack. */ | |
1465 | CORE_ADDR reg_position = (cache->base | |
1466 | + PROC_REG_OFFSET (proc_desc)); | |
1467 | if (inst & 0x20) | |
13326b4e | 1468 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1469 | |
1470 | /* Check if the s0 and s1 registers were pushed on the | |
1471 | stack. */ | |
1472 | /* NOTE: cagney/2004-02-08: Huh? This is doing no such | |
1473 | check. */ | |
1474 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1475 | { | |
1476 | cache->saved_regs[NUM_REGS + reg].addr = reg_position; | |
13326b4e | 1477 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1478 | } |
1479 | } | |
1480 | } | |
1481 | ||
1482 | /* Fill in the offsets for the registers which float_mask says were | |
1483 | saved. */ | |
1484 | { | |
1485 | CORE_ADDR reg_position = (cache->base | |
1486 | + PROC_FREG_OFFSET (proc_desc)); | |
1487 | int ireg; | |
1488 | /* Fill in the offsets for the float registers which float_mask | |
1489 | says were saved. */ | |
1490 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
1491 | if (float_mask & 0x80000000) | |
1492 | { | |
13326b4e | 1493 | if (mips_abi_regsize (gdbarch) == 4 |
edfae063 AC |
1494 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
1495 | { | |
1496 | /* On a big endian 32 bit ABI, floating point registers | |
1497 | are paired to form doubles such that the most | |
1498 | significant part is in $f[N+1] and the least | |
1499 | significant in $f[N] vis: $f[N+1] ||| $f[N]. The | |
1500 | registers are also spilled as a pair and stored as a | |
1501 | double. | |
1502 | ||
1503 | When little-endian the least significant part is | |
1504 | stored first leading to the memory order $f[N] and | |
1505 | then $f[N+1]. | |
1506 | ||
1507 | Unfortunately, when big-endian the most significant | |
1508 | part of the double is stored first, and the least | |
1509 | significant is stored second. This leads to the | |
1510 | registers being ordered in memory as firt $f[N+1] and | |
1511 | then $f[N]. | |
1512 | ||
1513 | For the big-endian case make certain that the | |
1514 | addresses point at the correct (swapped) locations | |
1515 | $f[N] and $f[N+1] pair (keep in mind that | |
1516 | reg_position is decremented each time through the | |
1517 | loop). */ | |
1518 | if ((ireg & 1)) | |
1519 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
13326b4e | 1520 | .addr = reg_position - mips_abi_regsize (gdbarch); |
edfae063 AC |
1521 | else |
1522 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
13326b4e | 1523 | .addr = reg_position + mips_abi_regsize (gdbarch); |
edfae063 AC |
1524 | } |
1525 | else | |
1526 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
1527 | .addr = reg_position; | |
13326b4e | 1528 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1529 | } |
1530 | ||
1531 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
4c7d22cb | 1532 | = cache->saved_regs[NUM_REGS + MIPS_RA_REGNUM]; |
edfae063 AC |
1533 | } |
1534 | ||
1535 | /* SP_REGNUM, contains the value and not the address. */ | |
f10683bb | 1536 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); |
edfae063 AC |
1537 | |
1538 | return (*this_cache); | |
1539 | } | |
1540 | ||
1541 | static void | |
1542 | mips_mdebug_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
1543 | struct frame_id *this_id) | |
1544 | { | |
1545 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1546 | this_cache); | |
1547 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
1548 | } | |
1549 | ||
1550 | static void | |
1551 | mips_mdebug_frame_prev_register (struct frame_info *next_frame, | |
1552 | void **this_cache, | |
1553 | int regnum, int *optimizedp, | |
1554 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1555 | int *realnump, void *valuep) | |
1556 | { | |
1557 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1558 | this_cache); | |
1f67027d AC |
1559 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
1560 | optimizedp, lvalp, addrp, realnump, valuep); | |
edfae063 AC |
1561 | } |
1562 | ||
1563 | static const struct frame_unwind mips_mdebug_frame_unwind = | |
1564 | { | |
1565 | NORMAL_FRAME, | |
1566 | mips_mdebug_frame_this_id, | |
1567 | mips_mdebug_frame_prev_register | |
1568 | }; | |
1569 | ||
1570 | static const struct frame_unwind * | |
1571 | mips_mdebug_frame_sniffer (struct frame_info *next_frame) | |
1572 | { | |
eec63939 AC |
1573 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
1574 | CORE_ADDR startaddr = 0; | |
1575 | mips_extra_func_info_t proc_desc; | |
1576 | int kernel_trap; | |
1577 | ||
1578 | /* Only use the mdebug frame unwinder on mdebug frames where all the | |
1579 | registers have been saved. Leave hard cases such as no mdebug or | |
1580 | in prologue for the heuristic unwinders. */ | |
1581 | ||
1582 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
1583 | if (proc_desc == NULL) | |
1584 | return NULL; | |
1585 | ||
1586 | /* Not sure exactly what kernel_trap means, but if it means the | |
1587 | kernel saves the registers without a prologue doing it, we better | |
1588 | not examine the prologue to see whether registers have been saved | |
1589 | yet. */ | |
1590 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; | |
1591 | if (kernel_trap) | |
1592 | return &mips_mdebug_frame_unwind; | |
1593 | ||
1594 | /* In any frame other than the innermost or a frame interrupted by a | |
1595 | signal, we assume that all registers have been saved. This | |
1596 | assumes that all register saves in a function happen before the | |
1597 | first function call. */ | |
1598 | if (!in_prologue (pc, PROC_LOW_ADDR (proc_desc))) | |
1599 | return &mips_mdebug_frame_unwind; | |
1600 | ||
1601 | return NULL; | |
edfae063 AC |
1602 | } |
1603 | ||
1604 | static CORE_ADDR | |
1605 | mips_mdebug_frame_base_address (struct frame_info *next_frame, | |
1606 | void **this_cache) | |
1607 | { | |
1608 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1609 | this_cache); | |
1610 | return info->base; | |
1611 | } | |
1612 | ||
1613 | static const struct frame_base mips_mdebug_frame_base = { | |
1614 | &mips_mdebug_frame_unwind, | |
1615 | mips_mdebug_frame_base_address, | |
1616 | mips_mdebug_frame_base_address, | |
1617 | mips_mdebug_frame_base_address | |
1618 | }; | |
1619 | ||
1620 | static const struct frame_base * | |
1621 | mips_mdebug_frame_base_sniffer (struct frame_info *next_frame) | |
1622 | { | |
eec63939 AC |
1623 | if (mips_mdebug_frame_sniffer (next_frame) != NULL) |
1624 | return &mips_mdebug_frame_base; | |
1625 | else | |
1626 | return NULL; | |
1627 | } | |
1628 | ||
29639122 JB |
1629 | /* Set a register's saved stack address in temp_saved_regs. If an |
1630 | address has already been set for this register, do nothing; this | |
1631 | way we will only recognize the first save of a given register in a | |
1632 | function prologue. | |
eec63939 | 1633 | |
29639122 JB |
1634 | For simplicity, save the address in both [0 .. NUM_REGS) and |
1635 | [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range | |
1636 | is used as it is only second range (the ABI instead of ISA | |
1637 | registers) that comes into play when finding saved registers in a | |
1638 | frame. */ | |
eec63939 AC |
1639 | |
1640 | static void | |
29639122 JB |
1641 | set_reg_offset (struct mips_frame_cache *this_cache, int regnum, |
1642 | CORE_ADDR offset) | |
eec63939 | 1643 | { |
29639122 JB |
1644 | if (this_cache != NULL |
1645 | && this_cache->saved_regs[regnum].addr == -1) | |
1646 | { | |
1647 | this_cache->saved_regs[regnum + 0 * NUM_REGS].addr = offset; | |
1648 | this_cache->saved_regs[regnum + 1 * NUM_REGS].addr = offset; | |
1649 | } | |
eec63939 AC |
1650 | } |
1651 | ||
eec63939 | 1652 | |
29639122 JB |
1653 | /* Fetch the immediate value from a MIPS16 instruction. |
1654 | If the previous instruction was an EXTEND, use it to extend | |
1655 | the upper bits of the immediate value. This is a helper function | |
1656 | for mips16_scan_prologue. */ | |
eec63939 | 1657 | |
29639122 JB |
1658 | static int |
1659 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1660 | unsigned short inst, /* current instruction */ | |
1661 | int nbits, /* number of bits in imm field */ | |
1662 | int scale, /* scale factor to be applied to imm */ | |
1663 | int is_signed) /* is the imm field signed? */ | |
eec63939 | 1664 | { |
29639122 | 1665 | int offset; |
eec63939 | 1666 | |
29639122 JB |
1667 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1668 | { | |
1669 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1670 | if (offset & 0x8000) /* check for negative extend */ | |
1671 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1672 | return offset | (inst & 0x1f); | |
1673 | } | |
eec63939 | 1674 | else |
29639122 JB |
1675 | { |
1676 | int max_imm = 1 << nbits; | |
1677 | int mask = max_imm - 1; | |
1678 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1679 | |
29639122 JB |
1680 | offset = inst & mask; |
1681 | if (is_signed && (offset & sign_bit)) | |
1682 | offset = 0 - (max_imm - offset); | |
1683 | return offset * scale; | |
1684 | } | |
1685 | } | |
eec63939 | 1686 | |
65596487 | 1687 | |
29639122 JB |
1688 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1689 | the associated FRAME_CACHE if not null. | |
1690 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1691 | |
29639122 JB |
1692 | static CORE_ADDR |
1693 | mips16_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
1694 | struct frame_info *next_frame, | |
1695 | struct mips_frame_cache *this_cache) | |
1696 | { | |
1697 | CORE_ADDR cur_pc; | |
1698 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1699 | CORE_ADDR sp; | |
1700 | long frame_offset = 0; /* Size of stack frame. */ | |
1701 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1702 | int frame_reg = MIPS_SP_REGNUM; | |
1703 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1704 | unsigned inst = 0; /* current instruction */ | |
1705 | unsigned entry_inst = 0; /* the entry instruction */ | |
1706 | int reg, offset; | |
a343eb3c | 1707 | |
29639122 JB |
1708 | int extend_bytes = 0; |
1709 | int prev_extend_bytes; | |
1710 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 1711 | |
29639122 JB |
1712 | /* Can be called when there's no process, and hence when there's no |
1713 | NEXT_FRAME. */ | |
1714 | if (next_frame != NULL) | |
1715 | sp = read_next_frame_reg (next_frame, NUM_REGS + MIPS_SP_REGNUM); | |
1716 | else | |
1717 | sp = 0; | |
eec63939 | 1718 | |
29639122 JB |
1719 | if (limit_pc > start_pc + 200) |
1720 | limit_pc = start_pc + 200; | |
eec63939 | 1721 | |
4c7d22cb | 1722 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSN_SIZE) |
29639122 JB |
1723 | { |
1724 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1725 | the immediate offset extension from it in mips16_get_imm. */ | |
1726 | prev_inst = inst; | |
eec63939 | 1727 | |
29639122 JB |
1728 | /* Fetch and decode the instruction. */ |
1729 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
eec63939 | 1730 | |
29639122 JB |
1731 | /* Normally we ignore extend instructions. However, if it is |
1732 | not followed by a valid prologue instruction, then this | |
1733 | instruction is not part of the prologue either. We must | |
1734 | remember in this case to adjust the end_prologue_addr back | |
1735 | over the extend. */ | |
1736 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1737 | { | |
4c7d22cb | 1738 | extend_bytes = MIPS16_INSN_SIZE; |
29639122 JB |
1739 | continue; |
1740 | } | |
eec63939 | 1741 | |
29639122 JB |
1742 | prev_extend_bytes = extend_bytes; |
1743 | extend_bytes = 0; | |
eec63939 | 1744 | |
29639122 JB |
1745 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1746 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1747 | { | |
1748 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
1749 | if (offset < 0) /* negative stack adjustment? */ | |
1750 | frame_offset -= offset; | |
1751 | else | |
1752 | /* Exit loop if a positive stack adjustment is found, which | |
1753 | usually means that the stack cleanup code in the function | |
1754 | epilogue is reached. */ | |
1755 | break; | |
1756 | } | |
1757 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1758 | { | |
1759 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1760 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
1761 | set_reg_offset (this_cache, reg, sp + offset); | |
1762 | } | |
1763 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1764 | { | |
1765 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1766 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1767 | set_reg_offset (this_cache, reg, sp + offset); | |
1768 | } | |
1769 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1770 | { | |
1771 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4c7d22cb | 1772 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1773 | } |
1774 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1775 | { | |
1776 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
4c7d22cb | 1777 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1778 | } |
1779 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1780 | { | |
1781 | frame_addr = sp; | |
1782 | frame_reg = 17; | |
1783 | } | |
1784 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1785 | { | |
1786 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1787 | frame_addr = sp + offset; | |
1788 | frame_reg = 17; | |
1789 | frame_adjust = offset; | |
1790 | } | |
1791 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1792 | { | |
1793 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1794 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1795 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1796 | } | |
1797 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1798 | { | |
1799 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1800 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1801 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1802 | } | |
1803 | else if ((inst & 0xf81f) == 0xe809 | |
1804 | && (inst & 0x700) != 0x700) /* entry */ | |
1805 | entry_inst = inst; /* save for later processing */ | |
1806 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ | |
4c7d22cb | 1807 | cur_pc += MIPS16_INSN_SIZE; /* 32-bit instruction */ |
29639122 JB |
1808 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1809 | { | |
1810 | /* This instruction is part of the prologue, but we don't | |
1811 | need to do anything special to handle it. */ | |
1812 | } | |
1813 | else | |
1814 | { | |
1815 | /* This instruction is not an instruction typically found | |
1816 | in a prologue, so we must have reached the end of the | |
1817 | prologue. */ | |
1818 | if (end_prologue_addr == 0) | |
1819 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1820 | } | |
1821 | } | |
eec63939 | 1822 | |
29639122 JB |
1823 | /* The entry instruction is typically the first instruction in a function, |
1824 | and it stores registers at offsets relative to the value of the old SP | |
1825 | (before the prologue). But the value of the sp parameter to this | |
1826 | function is the new SP (after the prologue has been executed). So we | |
1827 | can't calculate those offsets until we've seen the entire prologue, | |
1828 | and can calculate what the old SP must have been. */ | |
1829 | if (entry_inst != 0) | |
1830 | { | |
1831 | int areg_count = (entry_inst >> 8) & 7; | |
1832 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1833 | |
29639122 JB |
1834 | /* The entry instruction always subtracts 32 from the SP. */ |
1835 | frame_offset += 32; | |
1836 | ||
1837 | /* Now we can calculate what the SP must have been at the | |
1838 | start of the function prologue. */ | |
1839 | sp += frame_offset; | |
1840 | ||
1841 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1842 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1843 | { | |
1844 | set_reg_offset (this_cache, reg, sp + offset); | |
1845 | offset += mips_abi_regsize (current_gdbarch); | |
1846 | } | |
1847 | ||
1848 | /* Check if the ra register was pushed on the stack. */ | |
1849 | offset = -4; | |
1850 | if (entry_inst & 0x20) | |
1851 | { | |
4c7d22cb | 1852 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1853 | offset -= mips_abi_regsize (current_gdbarch); |
1854 | } | |
1855 | ||
1856 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1857 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1858 | { | |
1859 | set_reg_offset (this_cache, reg, sp + offset); | |
1860 | offset -= mips_abi_regsize (current_gdbarch); | |
1861 | } | |
1862 | } | |
1863 | ||
1864 | if (this_cache != NULL) | |
1865 | { | |
1866 | this_cache->base = | |
1867 | (frame_unwind_register_signed (next_frame, NUM_REGS + frame_reg) | |
1868 | + frame_offset - frame_adjust); | |
1869 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
1870 | be able to get rid of the assignment below, evetually. But it's | |
1871 | still needed for now. */ | |
1872 | this_cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
4c7d22cb | 1873 | = this_cache->saved_regs[NUM_REGS + MIPS_RA_REGNUM]; |
29639122 JB |
1874 | } |
1875 | ||
1876 | /* If we didn't reach the end of the prologue when scanning the function | |
1877 | instructions, then set end_prologue_addr to the address of the | |
1878 | instruction immediately after the last one we scanned. */ | |
1879 | if (end_prologue_addr == 0) | |
1880 | end_prologue_addr = cur_pc; | |
1881 | ||
1882 | return end_prologue_addr; | |
eec63939 AC |
1883 | } |
1884 | ||
29639122 JB |
1885 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1886 | Procedures that use the 32-bit instruction set are handled by the | |
1887 | mips_insn32 unwinder. */ | |
1888 | ||
1889 | static struct mips_frame_cache * | |
1890 | mips_insn16_frame_cache (struct frame_info *next_frame, void **this_cache) | |
eec63939 | 1891 | { |
29639122 | 1892 | struct mips_frame_cache *cache; |
eec63939 AC |
1893 | |
1894 | if ((*this_cache) != NULL) | |
1895 | return (*this_cache); | |
29639122 JB |
1896 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1897 | (*this_cache) = cache; | |
1898 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
eec63939 | 1899 | |
29639122 JB |
1900 | /* Analyze the function prologue. */ |
1901 | { | |
1902 | const CORE_ADDR pc = frame_pc_unwind (next_frame); | |
1903 | CORE_ADDR start_addr; | |
eec63939 | 1904 | |
29639122 JB |
1905 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1906 | if (start_addr == 0) | |
1907 | start_addr = heuristic_proc_start (pc); | |
1908 | /* We can't analyze the prologue if we couldn't find the begining | |
1909 | of the function. */ | |
1910 | if (start_addr == 0) | |
1911 | return cache; | |
eec63939 | 1912 | |
29639122 JB |
1913 | mips16_scan_prologue (start_addr, pc, next_frame, *this_cache); |
1914 | } | |
1915 | ||
1916 | /* SP_REGNUM, contains the value and not the address. */ | |
1917 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); | |
eec63939 | 1918 | |
29639122 | 1919 | return (*this_cache); |
eec63939 AC |
1920 | } |
1921 | ||
1922 | static void | |
29639122 JB |
1923 | mips_insn16_frame_this_id (struct frame_info *next_frame, void **this_cache, |
1924 | struct frame_id *this_id) | |
eec63939 | 1925 | { |
29639122 JB |
1926 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1927 | this_cache); | |
1928 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
eec63939 AC |
1929 | } |
1930 | ||
1931 | static void | |
29639122 | 1932 | mips_insn16_frame_prev_register (struct frame_info *next_frame, |
eec63939 AC |
1933 | void **this_cache, |
1934 | int regnum, int *optimizedp, | |
1935 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1936 | int *realnump, void *valuep) | |
1937 | { | |
29639122 JB |
1938 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1939 | this_cache); | |
1940 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
1941 | optimizedp, lvalp, addrp, realnump, valuep); | |
eec63939 AC |
1942 | } |
1943 | ||
29639122 | 1944 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
1945 | { |
1946 | NORMAL_FRAME, | |
29639122 JB |
1947 | mips_insn16_frame_this_id, |
1948 | mips_insn16_frame_prev_register | |
eec63939 AC |
1949 | }; |
1950 | ||
1951 | static const struct frame_unwind * | |
29639122 | 1952 | mips_insn16_frame_sniffer (struct frame_info *next_frame) |
eec63939 AC |
1953 | { |
1954 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
0fe7e7c8 | 1955 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
1956 | return &mips_insn16_frame_unwind; |
1957 | return NULL; | |
eec63939 AC |
1958 | } |
1959 | ||
1960 | static CORE_ADDR | |
29639122 JB |
1961 | mips_insn16_frame_base_address (struct frame_info *next_frame, |
1962 | void **this_cache) | |
eec63939 | 1963 | { |
29639122 JB |
1964 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1965 | this_cache); | |
1966 | return info->base; | |
eec63939 AC |
1967 | } |
1968 | ||
29639122 | 1969 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 1970 | { |
29639122 JB |
1971 | &mips_insn16_frame_unwind, |
1972 | mips_insn16_frame_base_address, | |
1973 | mips_insn16_frame_base_address, | |
1974 | mips_insn16_frame_base_address | |
eec63939 AC |
1975 | }; |
1976 | ||
1977 | static const struct frame_base * | |
29639122 | 1978 | mips_insn16_frame_base_sniffer (struct frame_info *next_frame) |
eec63939 | 1979 | { |
29639122 JB |
1980 | if (mips_insn16_frame_sniffer (next_frame) != NULL) |
1981 | return &mips_insn16_frame_base; | |
eec63939 AC |
1982 | else |
1983 | return NULL; | |
edfae063 AC |
1984 | } |
1985 | ||
29639122 JB |
1986 | /* Mark all the registers as unset in the saved_regs array |
1987 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
1988 | ||
1989 | void | |
1990 | reset_saved_regs (struct mips_frame_cache *this_cache) | |
c906108c | 1991 | { |
29639122 JB |
1992 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
1993 | return; | |
1994 | ||
1995 | { | |
1996 | const int num_regs = NUM_REGS; | |
1997 | int i; | |
64159455 | 1998 | |
29639122 JB |
1999 | for (i = 0; i < num_regs; i++) |
2000 | { | |
2001 | this_cache->saved_regs[i].addr = -1; | |
2002 | } | |
2003 | } | |
c906108c SS |
2004 | } |
2005 | ||
29639122 JB |
2006 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
2007 | the associated FRAME_CACHE if not null. | |
2008 | Return the address of the first instruction past the prologue. */ | |
c906108c | 2009 | |
875e1767 | 2010 | static CORE_ADDR |
29639122 JB |
2011 | mips32_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2012 | struct frame_info *next_frame, | |
2013 | struct mips_frame_cache *this_cache) | |
c906108c | 2014 | { |
29639122 JB |
2015 | CORE_ADDR cur_pc; |
2016 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
2017 | CORE_ADDR sp; | |
2018 | long frame_offset; | |
2019 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 2020 | |
29639122 JB |
2021 | CORE_ADDR end_prologue_addr = 0; |
2022 | int seen_sp_adjust = 0; | |
2023 | int load_immediate_bytes = 0; | |
8fa9cfa1 | 2024 | |
29639122 JB |
2025 | /* Can be called when there's no process, and hence when there's no |
2026 | NEXT_FRAME. */ | |
2027 | if (next_frame != NULL) | |
2028 | sp = read_next_frame_reg (next_frame, NUM_REGS + MIPS_SP_REGNUM); | |
8fa9cfa1 | 2029 | else |
29639122 | 2030 | sp = 0; |
9022177c | 2031 | |
29639122 JB |
2032 | if (limit_pc > start_pc + 200) |
2033 | limit_pc = start_pc + 200; | |
9022177c | 2034 | |
29639122 | 2035 | restart: |
9022177c | 2036 | |
29639122 | 2037 | frame_offset = 0; |
4c7d22cb | 2038 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS32_INSN_SIZE) |
9022177c | 2039 | { |
29639122 JB |
2040 | unsigned long inst, high_word, low_word; |
2041 | int reg; | |
9022177c | 2042 | |
29639122 JB |
2043 | /* Fetch the instruction. */ |
2044 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
9022177c | 2045 | |
29639122 JB |
2046 | /* Save some code by pre-extracting some useful fields. */ |
2047 | high_word = (inst >> 16) & 0xffff; | |
2048 | low_word = inst & 0xffff; | |
2049 | reg = high_word & 0x1f; | |
fe29b929 | 2050 | |
29639122 JB |
2051 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
2052 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
2053 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2054 | { | |
2055 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
2056 | frame_offset += 0x10000 - low_word; | |
2057 | else | |
2058 | /* Exit loop if a positive stack adjustment is found, which | |
2059 | usually means that the stack cleanup code in the function | |
2060 | epilogue is reached. */ | |
2061 | break; | |
2062 | seen_sp_adjust = 1; | |
2063 | } | |
2064 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
2065 | { | |
2066 | set_reg_offset (this_cache, reg, sp + low_word); | |
2067 | } | |
2068 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
2069 | { | |
2070 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
2071 | set_reg_offset (this_cache, reg, sp + low_word); | |
2072 | } | |
2073 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
2074 | { | |
2075 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
2076 | if ((long) low_word != frame_offset) | |
2077 | frame_addr = sp + low_word; | |
2078 | else if (frame_reg == MIPS_SP_REGNUM) | |
2079 | { | |
2080 | unsigned alloca_adjust; | |
a4b8ebc8 | 2081 | |
29639122 JB |
2082 | frame_reg = 30; |
2083 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); | |
2084 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); | |
2085 | if (alloca_adjust > 0) | |
2086 | { | |
2087 | /* FP > SP + frame_size. This may be because of | |
2088 | an alloca or somethings similar. Fix sp to | |
2089 | "pre-alloca" value, and try again. */ | |
2090 | sp += alloca_adjust; | |
2091 | /* Need to reset the status of all registers. Otherwise, | |
2092 | we will hit a guard that prevents the new address | |
2093 | for each register to be recomputed during the second | |
2094 | pass. */ | |
2095 | reset_saved_regs (this_cache); | |
2096 | goto restart; | |
2097 | } | |
2098 | } | |
2099 | } | |
2100 | /* move $30,$sp. With different versions of gas this will be either | |
2101 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2102 | Accept any one of these. */ | |
2103 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
2104 | { | |
2105 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
2106 | if (frame_reg == MIPS_SP_REGNUM) | |
2107 | { | |
2108 | unsigned alloca_adjust; | |
c906108c | 2109 | |
29639122 JB |
2110 | frame_reg = 30; |
2111 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); | |
2112 | alloca_adjust = (unsigned) (frame_addr - sp); | |
2113 | if (alloca_adjust > 0) | |
2114 | { | |
2115 | /* FP > SP + frame_size. This may be because of | |
2116 | an alloca or somethings similar. Fix sp to | |
2117 | "pre-alloca" value, and try again. */ | |
2118 | sp = frame_addr; | |
2119 | /* Need to reset the status of all registers. Otherwise, | |
2120 | we will hit a guard that prevents the new address | |
2121 | for each register to be recomputed during the second | |
2122 | pass. */ | |
2123 | reset_saved_regs (this_cache); | |
2124 | goto restart; | |
2125 | } | |
2126 | } | |
2127 | } | |
2128 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ | |
2129 | { | |
2130 | set_reg_offset (this_cache, reg, frame_addr + low_word); | |
2131 | } | |
2132 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
2133 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
2134 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
2135 | || high_word == 0x3c1c /* lui $gp,n */ | |
2136 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
2137 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
2138 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
2139 | ) | |
2140 | { | |
2141 | /* These instructions are part of the prologue, but we don't | |
2142 | need to do anything special to handle them. */ | |
2143 | } | |
2144 | /* The instructions below load $at or $t0 with an immediate | |
2145 | value in preparation for a stack adjustment via | |
2146 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
2147 | initialize a local variable, so we accept them only before | |
2148 | a stack adjustment instruction was seen. */ | |
2149 | else if (!seen_sp_adjust | |
2150 | && (high_word == 0x3c01 /* lui $at,n */ | |
2151 | || high_word == 0x3c08 /* lui $t0,n */ | |
2152 | || high_word == 0x3421 /* ori $at,$at,n */ | |
2153 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
2154 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
2155 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
2156 | )) | |
2157 | { | |
4c7d22cb | 2158 | load_immediate_bytes += MIPS32_INSN_SIZE; /* FIXME! */ |
29639122 JB |
2159 | } |
2160 | else | |
2161 | { | |
2162 | /* This instruction is not an instruction typically found | |
2163 | in a prologue, so we must have reached the end of the | |
2164 | prologue. */ | |
2165 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
2166 | loop now? Why would we need to continue scanning the function | |
2167 | instructions? */ | |
2168 | if (end_prologue_addr == 0) | |
2169 | end_prologue_addr = cur_pc; | |
2170 | } | |
a4b8ebc8 | 2171 | } |
c906108c | 2172 | |
29639122 JB |
2173 | if (this_cache != NULL) |
2174 | { | |
2175 | this_cache->base = | |
2176 | (frame_unwind_register_signed (next_frame, NUM_REGS + frame_reg) | |
2177 | + frame_offset); | |
2178 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2179 | this assignment below, eventually. But it's still needed | |
2180 | for now. */ | |
2181 | this_cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
4c7d22cb | 2182 | = this_cache->saved_regs[NUM_REGS + MIPS_RA_REGNUM]; |
29639122 | 2183 | } |
c906108c | 2184 | |
29639122 JB |
2185 | /* If we didn't reach the end of the prologue when scanning the function |
2186 | instructions, then set end_prologue_addr to the address of the | |
2187 | instruction immediately after the last one we scanned. */ | |
2188 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2189 | we may as well be careful and do our best if we have a null | |
2190 | end_prologue_addr. */ | |
2191 | if (end_prologue_addr == 0) | |
2192 | end_prologue_addr = cur_pc; | |
2193 | ||
2194 | /* In a frameless function, we might have incorrectly | |
2195 | skipped some load immediate instructions. Undo the skipping | |
2196 | if the load immediate was not followed by a stack adjustment. */ | |
2197 | if (load_immediate_bytes && !seen_sp_adjust) | |
2198 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2199 | |
29639122 | 2200 | return end_prologue_addr; |
c906108c SS |
2201 | } |
2202 | ||
29639122 JB |
2203 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2204 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2205 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2206 | unwinder. */ | |
c906108c | 2207 | |
29639122 JB |
2208 | static struct mips_frame_cache * |
2209 | mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache) | |
c906108c | 2210 | { |
29639122 | 2211 | struct mips_frame_cache *cache; |
c906108c | 2212 | |
29639122 JB |
2213 | if ((*this_cache) != NULL) |
2214 | return (*this_cache); | |
c5aa993b | 2215 | |
29639122 JB |
2216 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2217 | (*this_cache) = cache; | |
2218 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
c5aa993b | 2219 | |
29639122 JB |
2220 | /* Analyze the function prologue. */ |
2221 | { | |
2222 | const CORE_ADDR pc = frame_pc_unwind (next_frame); | |
2223 | CORE_ADDR start_addr; | |
c906108c | 2224 | |
29639122 JB |
2225 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2226 | if (start_addr == 0) | |
2227 | start_addr = heuristic_proc_start (pc); | |
2228 | /* We can't analyze the prologue if we couldn't find the begining | |
2229 | of the function. */ | |
2230 | if (start_addr == 0) | |
2231 | return cache; | |
c5aa993b | 2232 | |
29639122 JB |
2233 | mips32_scan_prologue (start_addr, pc, next_frame, *this_cache); |
2234 | } | |
2235 | ||
2236 | /* SP_REGNUM, contains the value and not the address. */ | |
2237 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); | |
c5aa993b | 2238 | |
29639122 | 2239 | return (*this_cache); |
c906108c SS |
2240 | } |
2241 | ||
29639122 JB |
2242 | static void |
2243 | mips_insn32_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2244 | struct frame_id *this_id) | |
c906108c | 2245 | { |
29639122 JB |
2246 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
2247 | this_cache); | |
2248 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
2249 | } | |
c906108c | 2250 | |
29639122 JB |
2251 | static void |
2252 | mips_insn32_frame_prev_register (struct frame_info *next_frame, | |
2253 | void **this_cache, | |
2254 | int regnum, int *optimizedp, | |
2255 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
2256 | int *realnump, void *valuep) | |
2257 | { | |
2258 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, | |
2259 | this_cache); | |
2260 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
2261 | optimizedp, lvalp, addrp, realnump, valuep); | |
c906108c SS |
2262 | } |
2263 | ||
29639122 JB |
2264 | static const struct frame_unwind mips_insn32_frame_unwind = |
2265 | { | |
2266 | NORMAL_FRAME, | |
2267 | mips_insn32_frame_this_id, | |
2268 | mips_insn32_frame_prev_register | |
2269 | }; | |
c906108c | 2270 | |
29639122 JB |
2271 | static const struct frame_unwind * |
2272 | mips_insn32_frame_sniffer (struct frame_info *next_frame) | |
2273 | { | |
2274 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
0fe7e7c8 | 2275 | if (! mips_pc_is_mips16 (pc)) |
29639122 JB |
2276 | return &mips_insn32_frame_unwind; |
2277 | return NULL; | |
2278 | } | |
c906108c | 2279 | |
1c645fec | 2280 | static CORE_ADDR |
29639122 JB |
2281 | mips_insn32_frame_base_address (struct frame_info *next_frame, |
2282 | void **this_cache) | |
c906108c | 2283 | { |
29639122 JB |
2284 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
2285 | this_cache); | |
2286 | return info->base; | |
2287 | } | |
c906108c | 2288 | |
29639122 JB |
2289 | static const struct frame_base mips_insn32_frame_base = |
2290 | { | |
2291 | &mips_insn32_frame_unwind, | |
2292 | mips_insn32_frame_base_address, | |
2293 | mips_insn32_frame_base_address, | |
2294 | mips_insn32_frame_base_address | |
2295 | }; | |
1c645fec | 2296 | |
29639122 JB |
2297 | static const struct frame_base * |
2298 | mips_insn32_frame_base_sniffer (struct frame_info *next_frame) | |
2299 | { | |
2300 | if (mips_insn32_frame_sniffer (next_frame) != NULL) | |
2301 | return &mips_insn32_frame_base; | |
a65bbe44 | 2302 | else |
29639122 JB |
2303 | return NULL; |
2304 | } | |
a65bbe44 | 2305 | |
29639122 JB |
2306 | static struct trad_frame_cache * |
2307 | mips_stub_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2308 | { | |
2309 | CORE_ADDR pc; | |
2310 | CORE_ADDR start_addr; | |
2311 | CORE_ADDR stack_addr; | |
2312 | struct trad_frame_cache *this_trad_cache; | |
c906108c | 2313 | |
29639122 JB |
2314 | if ((*this_cache) != NULL) |
2315 | return (*this_cache); | |
2316 | this_trad_cache = trad_frame_cache_zalloc (next_frame); | |
2317 | (*this_cache) = this_trad_cache; | |
1c645fec | 2318 | |
29639122 | 2319 | /* The return address is in the link register. */ |
4c7d22cb | 2320 | trad_frame_set_reg_realreg (this_trad_cache, PC_REGNUM, MIPS_RA_REGNUM); |
1c645fec | 2321 | |
29639122 JB |
2322 | /* Frame ID, since it's a frameless / stackless function, no stack |
2323 | space is allocated and SP on entry is the current SP. */ | |
2324 | pc = frame_pc_unwind (next_frame); | |
2325 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
4c7d22cb | 2326 | stack_addr = frame_unwind_register_signed (next_frame, MIPS_SP_REGNUM); |
29639122 | 2327 | trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr)); |
1c645fec | 2328 | |
29639122 JB |
2329 | /* Assume that the frame's base is the same as the |
2330 | stack-pointer. */ | |
2331 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2332 | |
29639122 JB |
2333 | return this_trad_cache; |
2334 | } | |
c906108c | 2335 | |
29639122 JB |
2336 | static void |
2337 | mips_stub_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2338 | struct frame_id *this_id) | |
2339 | { | |
2340 | struct trad_frame_cache *this_trad_cache | |
2341 | = mips_stub_frame_cache (next_frame, this_cache); | |
2342 | trad_frame_get_id (this_trad_cache, this_id); | |
2343 | } | |
c906108c | 2344 | |
29639122 JB |
2345 | static void |
2346 | mips_stub_frame_prev_register (struct frame_info *next_frame, | |
2347 | void **this_cache, | |
2348 | int regnum, int *optimizedp, | |
2349 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
2350 | int *realnump, void *valuep) | |
2351 | { | |
2352 | struct trad_frame_cache *this_trad_cache | |
2353 | = mips_stub_frame_cache (next_frame, this_cache); | |
2354 | trad_frame_get_register (this_trad_cache, next_frame, regnum, optimizedp, | |
2355 | lvalp, addrp, realnump, valuep); | |
2356 | } | |
c906108c | 2357 | |
29639122 JB |
2358 | static const struct frame_unwind mips_stub_frame_unwind = |
2359 | { | |
2360 | NORMAL_FRAME, | |
2361 | mips_stub_frame_this_id, | |
2362 | mips_stub_frame_prev_register | |
2363 | }; | |
c906108c | 2364 | |
29639122 JB |
2365 | static const struct frame_unwind * |
2366 | mips_stub_frame_sniffer (struct frame_info *next_frame) | |
2367 | { | |
2368 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
2369 | if (in_plt_section (pc, NULL)) | |
2370 | return &mips_stub_frame_unwind; | |
2371 | else | |
2372 | return NULL; | |
2373 | } | |
c906108c | 2374 | |
29639122 JB |
2375 | static CORE_ADDR |
2376 | mips_stub_frame_base_address (struct frame_info *next_frame, | |
2377 | void **this_cache) | |
2378 | { | |
2379 | struct trad_frame_cache *this_trad_cache | |
2380 | = mips_stub_frame_cache (next_frame, this_cache); | |
2381 | return trad_frame_get_this_base (this_trad_cache); | |
2382 | } | |
0fce0821 | 2383 | |
29639122 JB |
2384 | static const struct frame_base mips_stub_frame_base = |
2385 | { | |
2386 | &mips_stub_frame_unwind, | |
2387 | mips_stub_frame_base_address, | |
2388 | mips_stub_frame_base_address, | |
2389 | mips_stub_frame_base_address | |
2390 | }; | |
2391 | ||
2392 | static const struct frame_base * | |
2393 | mips_stub_frame_base_sniffer (struct frame_info *next_frame) | |
2394 | { | |
2395 | if (mips_stub_frame_sniffer (next_frame) != NULL) | |
2396 | return &mips_stub_frame_base; | |
2397 | else | |
2398 | return NULL; | |
2399 | } | |
2400 | ||
2401 | static CORE_ADDR | |
2402 | read_next_frame_reg (struct frame_info *fi, int regno) | |
2403 | { | |
2404 | /* Always a pseudo. */ | |
2405 | gdb_assert (regno >= NUM_REGS); | |
2406 | if (fi == NULL) | |
0fce0821 | 2407 | { |
29639122 JB |
2408 | LONGEST val; |
2409 | regcache_cooked_read_signed (current_regcache, regno, &val); | |
2410 | return val; | |
0fce0821 | 2411 | } |
29639122 JB |
2412 | else |
2413 | return frame_unwind_register_signed (fi, regno); | |
1c645fec | 2414 | |
c906108c SS |
2415 | } |
2416 | ||
29639122 | 2417 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2418 | |
29639122 JB |
2419 | static CORE_ADDR |
2420 | mips_addr_bits_remove (CORE_ADDR addr) | |
65596487 | 2421 | { |
29639122 JB |
2422 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2423 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) | |
2424 | /* This hack is a work-around for existing boards using PMON, the | |
2425 | simulator, and any other 64-bit targets that doesn't have true | |
2426 | 64-bit addressing. On these targets, the upper 32 bits of | |
2427 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2428 | likely to have been sign extended to all 1s by instruction | |
2429 | sequences that load 32-bit addresses. For example, a typical | |
2430 | piece of code that loads an address is this: | |
65596487 | 2431 | |
29639122 JB |
2432 | lui $r2, <upper 16 bits> |
2433 | ori $r2, <lower 16 bits> | |
65596487 | 2434 | |
29639122 JB |
2435 | But the lui sign-extends the value such that the upper 32 bits |
2436 | may be all 1s. The workaround is simply to mask off these | |
2437 | bits. In the future, gcc may be changed to support true 64-bit | |
2438 | addressing, and this masking will have to be disabled. */ | |
2439 | return addr &= 0xffffffffUL; | |
2440 | else | |
2441 | return addr; | |
65596487 JB |
2442 | } |
2443 | ||
29639122 JB |
2444 | /* mips_software_single_step() is called just before we want to resume |
2445 | the inferior, if we want to single-step it but there is no hardware | |
2446 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
2447 | the target of the coming instruction and breakpoint it. | |
1e05a7bf | 2448 | |
29639122 JB |
2449 | single_step is also called just after the inferior stops. If we had |
2450 | set up a simulated single-step, we undo our damage. */ | |
2451 | ||
2452 | void | |
2453 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
c906108c | 2454 | { |
29639122 JB |
2455 | static CORE_ADDR next_pc; |
2456 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
2457 | static binsn_quantum break_mem; | |
2458 | CORE_ADDR pc; | |
65596487 | 2459 | |
29639122 JB |
2460 | if (insert_breakpoints_p) |
2461 | { | |
2462 | pc = read_register (mips_regnum (current_gdbarch)->pc); | |
2463 | next_pc = mips_next_pc (pc); | |
98b4dd94 | 2464 | |
29639122 JB |
2465 | target_insert_breakpoint (next_pc, break_mem); |
2466 | } | |
a65bbe44 | 2467 | else |
29639122 JB |
2468 | target_remove_breakpoint (next_pc, break_mem); |
2469 | } | |
a65bbe44 | 2470 | |
29639122 | 2471 | static struct mips_extra_func_info temp_proc_desc; |
a65bbe44 | 2472 | |
29639122 JB |
2473 | /* Test whether the PC points to the return instruction at the |
2474 | end of a function. */ | |
65596487 | 2475 | |
29639122 JB |
2476 | static int |
2477 | mips_about_to_return (CORE_ADDR pc) | |
2478 | { | |
0fe7e7c8 | 2479 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2480 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2481 | generates a "jr $ra"; other times it generates code to load | |
2482 | the return address from the stack to an accessible register (such | |
2483 | as $a3), then a "jr" using that register. This second case | |
2484 | is almost impossible to distinguish from an indirect jump | |
2485 | used for switch statements, so we don't even try. */ | |
2486 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
2487 | else | |
2488 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
2489 | } | |
c906108c | 2490 | |
c906108c | 2491 | |
29639122 JB |
2492 | /* This fencepost looks highly suspicious to me. Removing it also |
2493 | seems suspicious as it could affect remote debugging across serial | |
2494 | lines. */ | |
c906108c | 2495 | |
29639122 JB |
2496 | static CORE_ADDR |
2497 | heuristic_proc_start (CORE_ADDR pc) | |
2498 | { | |
2499 | CORE_ADDR start_pc; | |
2500 | CORE_ADDR fence; | |
2501 | int instlen; | |
2502 | int seen_adjsp = 0; | |
65596487 | 2503 | |
29639122 JB |
2504 | pc = ADDR_BITS_REMOVE (pc); |
2505 | start_pc = pc; | |
2506 | fence = start_pc - heuristic_fence_post; | |
2507 | if (start_pc == 0) | |
2508 | return 0; | |
65596487 | 2509 | |
29639122 JB |
2510 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2511 | fence = VM_MIN_ADDRESS; | |
65596487 | 2512 | |
0fe7e7c8 | 2513 | instlen = mips_pc_is_mips16 (pc) ? MIPS16_INSN_SIZE : MIPS32_INSN_SIZE; |
98b4dd94 | 2514 | |
29639122 JB |
2515 | /* search back for previous return */ |
2516 | for (start_pc -= instlen;; start_pc -= instlen) | |
2517 | if (start_pc < fence) | |
2518 | { | |
2519 | /* It's not clear to me why we reach this point when | |
2520 | stop_soon, but with this test, at least we | |
2521 | don't print out warnings for every child forked (eg, on | |
2522 | decstation). 22apr93 rich@cygnus.com. */ | |
2523 | if (stop_soon == NO_STOP_QUIETLY) | |
2524 | { | |
2525 | static int blurb_printed = 0; | |
98b4dd94 | 2526 | |
29639122 JB |
2527 | warning ("GDB can't find the start of the function at 0x%s.", |
2528 | paddr_nz (pc)); | |
2529 | ||
2530 | if (!blurb_printed) | |
2531 | { | |
2532 | /* This actually happens frequently in embedded | |
2533 | development, when you first connect to a board | |
2534 | and your stack pointer and pc are nowhere in | |
2535 | particular. This message needs to give people | |
2536 | in that situation enough information to | |
2537 | determine that it's no big deal. */ | |
2538 | printf_filtered ("\n\ | |
2539 | GDB is unable to find the start of the function at 0x%s\n\ | |
2540 | and thus can't determine the size of that function's stack frame.\n\ | |
2541 | This means that GDB may be unable to access that stack frame, or\n\ | |
2542 | the frames below it.\n\ | |
2543 | This problem is most likely caused by an invalid program counter or\n\ | |
2544 | stack pointer.\n\ | |
2545 | However, if you think GDB should simply search farther back\n\ | |
2546 | from 0x%s for code which looks like the beginning of a\n\ | |
2547 | function, you can increase the range of the search using the `set\n\ | |
2548 | heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); | |
2549 | blurb_printed = 1; | |
2550 | } | |
2551 | } | |
2552 | ||
2553 | return 0; | |
2554 | } | |
0fe7e7c8 | 2555 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2556 | { |
2557 | unsigned short inst; | |
2558 | ||
2559 | /* On MIPS16, any one of the following is likely to be the | |
2560 | start of a function: | |
2561 | entry | |
2562 | addiu sp,-n | |
2563 | daddiu sp,-n | |
2564 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
2565 | inst = mips_fetch_instruction (start_pc); | |
2566 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
2567 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2568 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2569 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
2570 | break; | |
2571 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2572 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2573 | seen_adjsp = 1; | |
2574 | else | |
2575 | seen_adjsp = 0; | |
2576 | } | |
2577 | else if (mips_about_to_return (start_pc)) | |
2578 | { | |
4c7d22cb MK |
2579 | /* Skip return and its delay slot. */ |
2580 | start_pc += 2 * MIPS32_INSN_SIZE; | |
29639122 JB |
2581 | break; |
2582 | } | |
2583 | ||
2584 | return start_pc; | |
c906108c SS |
2585 | } |
2586 | ||
6c0d6680 DJ |
2587 | struct mips_objfile_private |
2588 | { | |
2589 | bfd_size_type size; | |
2590 | char *contents; | |
2591 | }; | |
2592 | ||
2593 | /* Global used to communicate between non_heuristic_proc_desc and | |
2594 | compare_pdr_entries within qsort (). */ | |
2595 | static bfd *the_bfd; | |
2596 | ||
2597 | static int | |
2598 | compare_pdr_entries (const void *a, const void *b) | |
2599 | { | |
2600 | CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); | |
2601 | CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); | |
2602 | ||
2603 | if (lhs < rhs) | |
2604 | return -1; | |
2605 | else if (lhs == rhs) | |
2606 | return 0; | |
2607 | else | |
2608 | return 1; | |
2609 | } | |
2610 | ||
c906108c | 2611 | static mips_extra_func_info_t |
acdb74a0 | 2612 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
2613 | { |
2614 | CORE_ADDR startaddr; | |
2615 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 2616 | struct block *b = block_for_pc (pc); |
c906108c | 2617 | struct symbol *sym; |
6c0d6680 DJ |
2618 | struct obj_section *sec; |
2619 | struct mips_objfile_private *priv; | |
2620 | ||
c906108c SS |
2621 | find_pc_partial_function (pc, NULL, &startaddr, NULL); |
2622 | if (addrptr) | |
2623 | *addrptr = startaddr; | |
6c0d6680 DJ |
2624 | |
2625 | priv = NULL; | |
2626 | ||
2627 | sec = find_pc_section (pc); | |
2628 | if (sec != NULL) | |
c906108c | 2629 | { |
8d5f9dcb | 2630 | priv = (struct mips_objfile_private *) objfile_data (sec->objfile, mips_pdr_data); |
6c0d6680 DJ |
2631 | |
2632 | /* Search the ".pdr" section generated by GAS. This includes most of | |
6d82d43b | 2633 | the information normally found in ECOFF PDRs. */ |
6c0d6680 DJ |
2634 | |
2635 | the_bfd = sec->objfile->obfd; | |
2636 | if (priv == NULL | |
2637 | && (the_bfd->format == bfd_object | |
2638 | && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour | |
2639 | && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) | |
2640 | { | |
2641 | /* Right now GAS only outputs the address as a four-byte sequence. | |
2642 | This means that we should not bother with this method on 64-bit | |
2643 | targets (until that is fixed). */ | |
2644 | ||
8b92e4d5 | 2645 | priv = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2646 | sizeof (struct mips_objfile_private)); |
2647 | priv->size = 0; | |
8d5f9dcb | 2648 | set_objfile_data (sec->objfile, mips_pdr_data, priv); |
6c0d6680 DJ |
2649 | } |
2650 | else if (priv == NULL) | |
2651 | { | |
2652 | asection *bfdsec; | |
2653 | ||
8b92e4d5 | 2654 | priv = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2655 | sizeof (struct mips_objfile_private)); |
2656 | ||
2657 | bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); | |
2658 | if (bfdsec != NULL) | |
2659 | { | |
2660 | priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); | |
8b92e4d5 | 2661 | priv->contents = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2662 | priv->size); |
2663 | bfd_get_section_contents (sec->objfile->obfd, bfdsec, | |
2664 | priv->contents, 0, priv->size); | |
2665 | ||
2666 | /* In general, the .pdr section is sorted. However, in the | |
6d82d43b AC |
2667 | presence of multiple code sections (and other corner cases) |
2668 | it can become unsorted. Sort it so that we can use a faster | |
2669 | binary search. */ | |
2670 | qsort (priv->contents, priv->size / 32, 32, | |
2671 | compare_pdr_entries); | |
6c0d6680 DJ |
2672 | } |
2673 | else | |
2674 | priv->size = 0; | |
2675 | ||
8d5f9dcb | 2676 | set_objfile_data (sec->objfile, mips_pdr_data, priv); |
6c0d6680 DJ |
2677 | } |
2678 | the_bfd = NULL; | |
2679 | ||
2680 | if (priv->size != 0) | |
2681 | { | |
2682 | int low, mid, high; | |
2683 | char *ptr; | |
34fcf120 | 2684 | CORE_ADDR pdr_pc; |
6c0d6680 DJ |
2685 | |
2686 | low = 0; | |
2687 | high = priv->size / 32; | |
2688 | ||
34fcf120 DJ |
2689 | /* We've found a .pdr section describing this objfile. We want to |
2690 | find the entry which describes this code address. The .pdr | |
2691 | information is not very descriptive; we have only a function | |
2692 | start address. We have to look for the closest entry, because | |
2693 | the local symbol at the beginning of this function may have | |
2694 | been stripped - so if we ask the symbol table for the start | |
2695 | address we may get a preceding global function. */ | |
2696 | ||
2697 | /* First, find the last .pdr entry starting at or before PC. */ | |
6c0d6680 DJ |
2698 | do |
2699 | { | |
6c0d6680 DJ |
2700 | mid = (low + high) / 2; |
2701 | ||
2702 | ptr = priv->contents + mid * 32; | |
2703 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2704 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2705 | SECT_OFF_TEXT (sec->objfile)); | |
34fcf120 DJ |
2706 | |
2707 | if (pdr_pc > pc) | |
6c0d6680 DJ |
2708 | high = mid; |
2709 | else | |
2710 | low = mid + 1; | |
2711 | } | |
2712 | while (low != high); | |
2713 | ||
34fcf120 DJ |
2714 | /* Both low and high point one past the PDR of interest. If |
2715 | both are zero, that means this PC is before any region | |
2716 | covered by a PDR, i.e. pdr_pc for the first PDR entry is | |
2717 | greater than PC. */ | |
2718 | if (low > 0) | |
2719 | { | |
2720 | ptr = priv->contents + (low - 1) * 32; | |
2721 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2722 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2723 | SECT_OFF_TEXT (sec->objfile)); | |
2724 | } | |
2725 | ||
2726 | /* We don't have a range, so we have no way to know for sure | |
2727 | whether we're in the correct PDR or a PDR for a preceding | |
2728 | function and the current function was a stripped local | |
2729 | symbol. But if the PDR's PC is at least as great as the | |
2730 | best guess from the symbol table, assume that it does cover | |
2731 | the right area; if a .pdr section is present at all then | |
2732 | nearly every function will have an entry. The biggest exception | |
2733 | will be the dynamic linker stubs; conveniently these are | |
2734 | placed before .text instead of after. */ | |
2735 | ||
2736 | if (pc >= pdr_pc && pdr_pc >= startaddr) | |
6c0d6680 DJ |
2737 | { |
2738 | struct symbol *sym = find_pc_function (pc); | |
2739 | ||
34fcf120 DJ |
2740 | if (addrptr) |
2741 | *addrptr = pdr_pc; | |
2742 | ||
6c0d6680 DJ |
2743 | /* Fill in what we need of the proc_desc. */ |
2744 | proc_desc = (mips_extra_func_info_t) | |
8b92e4d5 | 2745 | obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 | 2746 | sizeof (struct mips_extra_func_info)); |
34fcf120 | 2747 | PROC_LOW_ADDR (proc_desc) = pdr_pc; |
6c0d6680 DJ |
2748 | |
2749 | /* Only used for dummy frames. */ | |
2750 | PROC_HIGH_ADDR (proc_desc) = 0; | |
2751 | ||
2752 | PROC_FRAME_OFFSET (proc_desc) | |
2753 | = bfd_get_32 (sec->objfile->obfd, ptr + 20); | |
2754 | PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2755 | ptr + 24); | |
2756 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
2757 | PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2758 | ptr + 4); | |
2759 | PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2760 | ptr + 12); | |
2761 | PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2762 | ptr + 8); | |
2763 | PROC_FREG_OFFSET (proc_desc) | |
2764 | = bfd_get_32 (sec->objfile->obfd, ptr + 16); | |
2765 | PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2766 | ptr + 28); | |
2767 | proc_desc->pdr.isym = (long) sym; | |
2768 | ||
2769 | return proc_desc; | |
2770 | } | |
2771 | } | |
c906108c SS |
2772 | } |
2773 | ||
6c0d6680 DJ |
2774 | if (b == NULL) |
2775 | return NULL; | |
2776 | ||
2777 | if (startaddr > BLOCK_START (b)) | |
2778 | { | |
2779 | /* This is the "pathological" case referred to in a comment in | |
6d82d43b AC |
2780 | print_frame_info. It might be better to move this check into |
2781 | symbol reading. */ | |
6c0d6680 DJ |
2782 | return NULL; |
2783 | } | |
2784 | ||
176620f1 | 2785 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL); |
6c0d6680 | 2786 | |
c906108c SS |
2787 | /* If we never found a PDR for this function in symbol reading, then |
2788 | examine prologues to find the information. */ | |
2789 | if (sym) | |
2790 | { | |
2791 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
2792 | if (PROC_FRAME_REG (proc_desc) == -1) | |
2793 | return NULL; | |
2794 | else | |
2795 | return proc_desc; | |
2796 | } | |
2797 | else | |
2798 | return NULL; | |
2799 | } | |
2800 | ||
c906108c SS |
2801 | /* MIPS stack frames are almost impenetrable. When execution stops, |
2802 | we basically have to look at symbol information for the function | |
2803 | that we stopped in, which tells us *which* register (if any) is | |
2804 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 2805 | the frame itself is at. |
c906108c SS |
2806 | |
2807 | This presents a problem when trying to examine a stack in memory | |
2808 | (that isn't executing at the moment), using the "frame" command. We | |
2809 | don't have a PC, nor do we have any registers except SP. | |
2810 | ||
2811 | This routine takes two arguments, SP and PC, and tries to make the | |
2812 | cached frames look as if these two arguments defined a frame on the | |
2813 | cache. This allows the rest of info frame to extract the important | |
2814 | arguments without difficulty. */ | |
2815 | ||
2816 | struct frame_info * | |
acdb74a0 | 2817 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
2818 | { |
2819 | if (argc != 2) | |
2820 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2821 | ||
2822 | return create_new_frame (argv[0], argv[1]); | |
2823 | } | |
2824 | ||
f09ded24 AC |
2825 | /* According to the current ABI, should the type be passed in a |
2826 | floating-point register (assuming that there is space)? When there | |
2827 | is no FPU, FP are not even considered as possibile candidates for | |
2828 | FP registers and, consequently this returns false - forces FP | |
2829 | arguments into integer registers. */ | |
2830 | ||
2831 | static int | |
2832 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2833 | { | |
2834 | return ((typecode == TYPE_CODE_FLT | |
2835 | || (MIPS_EABI | |
6d82d43b AC |
2836 | && (typecode == TYPE_CODE_STRUCT |
2837 | || typecode == TYPE_CODE_UNION) | |
f09ded24 AC |
2838 | && TYPE_NFIELDS (arg_type) == 1 |
2839 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 2840 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2841 | } |
2842 | ||
49e790b0 DJ |
2843 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2844 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2845 | ||
2846 | static int | |
2847 | mips_type_needs_double_align (struct type *type) | |
2848 | { | |
2849 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2850 | |
49e790b0 DJ |
2851 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2852 | return 1; | |
2853 | else if (typecode == TYPE_CODE_STRUCT) | |
2854 | { | |
2855 | if (TYPE_NFIELDS (type) < 1) | |
2856 | return 0; | |
2857 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2858 | } | |
2859 | else if (typecode == TYPE_CODE_UNION) | |
2860 | { | |
361d1df0 | 2861 | int i, n; |
49e790b0 DJ |
2862 | |
2863 | n = TYPE_NFIELDS (type); | |
2864 | for (i = 0; i < n; i++) | |
2865 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2866 | return 1; | |
2867 | return 0; | |
2868 | } | |
2869 | return 0; | |
2870 | } | |
2871 | ||
dc604539 AC |
2872 | /* Adjust the address downward (direction of stack growth) so that it |
2873 | is correctly aligned for a new stack frame. */ | |
2874 | static CORE_ADDR | |
2875 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2876 | { | |
5b03f266 | 2877 | return align_down (addr, 16); |
dc604539 AC |
2878 | } |
2879 | ||
f7ab6ec6 | 2880 | static CORE_ADDR |
7d9b040b | 2881 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2882 | struct regcache *regcache, CORE_ADDR bp_addr, |
2883 | int nargs, struct value **args, CORE_ADDR sp, | |
2884 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2885 | { |
2886 | int argreg; | |
2887 | int float_argreg; | |
2888 | int argnum; | |
2889 | int len = 0; | |
2890 | int stack_offset = 0; | |
480d3dd2 | 2891 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2892 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
c906108c | 2893 | |
25ab4790 AC |
2894 | /* For shared libraries, "t9" needs to point at the function |
2895 | address. */ | |
4c7d22cb | 2896 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2897 | |
2898 | /* Set the return address register to point to the entry point of | |
2899 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2900 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2901 | |
c906108c | 2902 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2903 | are properly aligned. The stack has to be at least 64-bit |
2904 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2905 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2906 | aligned, so we round to this widest known alignment. */ | |
2907 | ||
5b03f266 AC |
2908 | sp = align_down (sp, 16); |
2909 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2910 | |
46e0f506 | 2911 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2912 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2913 | passed in registers, but that's OK. */ |
c906108c | 2914 | for (argnum = 0; argnum < nargs; argnum++) |
6d82d43b | 2915 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 2916 | mips_stack_argsize (gdbarch)); |
5b03f266 | 2917 | sp -= align_up (len, 16); |
c906108c | 2918 | |
9ace0497 | 2919 | if (mips_debug) |
6d82d43b | 2920 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2921 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2922 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2923 | |
c906108c | 2924 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2925 | argreg = MIPS_A0_REGNUM; |
56cea623 | 2926 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 2927 | |
46e0f506 | 2928 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2929 | if (struct_return) |
9ace0497 AC |
2930 | { |
2931 | if (mips_debug) | |
2932 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2933 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2934 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
2935 | write_register (argreg++, struct_addr); |
2936 | } | |
c906108c SS |
2937 | |
2938 | /* Now load as many as possible of the first arguments into | |
2939 | registers, and push the rest onto the stack. Loop thru args | |
2940 | from first to last. */ | |
2941 | for (argnum = 0; argnum < nargs; argnum++) | |
2942 | { | |
2943 | char *val; | |
d9d9c31f | 2944 | char valbuf[MAX_REGISTER_SIZE]; |
ea7c478f | 2945 | struct value *arg = args[argnum]; |
c906108c SS |
2946 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
2947 | int len = TYPE_LENGTH (arg_type); | |
2948 | enum type_code typecode = TYPE_CODE (arg_type); | |
2949 | ||
9ace0497 AC |
2950 | if (mips_debug) |
2951 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2952 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2953 | argnum + 1, len, (int) typecode); |
9ace0497 | 2954 | |
c906108c | 2955 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2956 | reference. */ |
13326b4e | 2957 | if (len > mips_abi_regsize (gdbarch) |
9ace0497 | 2958 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2959 | { |
13326b4e | 2960 | store_unsigned_integer (valbuf, mips_abi_regsize (gdbarch), |
480d3dd2 | 2961 | VALUE_ADDRESS (arg)); |
c906108c | 2962 | typecode = TYPE_CODE_PTR; |
13326b4e | 2963 | len = mips_abi_regsize (gdbarch); |
c906108c | 2964 | val = valbuf; |
9ace0497 AC |
2965 | if (mips_debug) |
2966 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2967 | } |
2968 | else | |
c5aa993b | 2969 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
2970 | |
2971 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2972 | even-numbered floating point register. Round the FP register |
2973 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2974 | left. Non MIPS_EABI targets also pass the FP in the integer |
2975 | registers so also round up normal registers. */ | |
ceae6e75 AC |
2976 | if (mips_abi_regsize (gdbarch) < 8 |
2977 | && fp_register_arg_p (typecode, arg_type)) | |
acdb74a0 AC |
2978 | { |
2979 | if ((float_argreg & 1)) | |
2980 | float_argreg++; | |
2981 | } | |
c906108c SS |
2982 | |
2983 | /* Floating point arguments passed in registers have to be | |
2984 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2985 | are passed in register pairs; the even register gets |
2986 | the low word, and the odd register gets the high word. | |
2987 | On non-EABI processors, the first two floating point arguments are | |
2988 | also copied to general registers, because MIPS16 functions | |
2989 | don't use float registers for arguments. This duplication of | |
2990 | arguments in general registers can't hurt non-MIPS16 functions | |
2991 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2992 | /* MIPS_EABI squeezes a struct that contains a single floating |
2993 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2994 | stack. */ |
f09ded24 AC |
2995 | if (fp_register_arg_p (typecode, arg_type) |
2996 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c | 2997 | { |
ceae6e75 | 2998 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
c906108c | 2999 | { |
d7449b42 | 3000 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
3001 | unsigned long regval; |
3002 | ||
3003 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 3004 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 3005 | if (mips_debug) |
acdb74a0 | 3006 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3007 | float_argreg, phex (regval, 4)); |
c906108c | 3008 | write_register (float_argreg++, regval); |
c906108c SS |
3009 | |
3010 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 3011 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 3012 | if (mips_debug) |
acdb74a0 | 3013 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3014 | float_argreg, phex (regval, 4)); |
c906108c | 3015 | write_register (float_argreg++, regval); |
c906108c SS |
3016 | } |
3017 | else | |
3018 | { | |
3019 | /* This is a floating point value that fits entirely | |
3020 | in a single register. */ | |
53a5351d | 3021 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 3022 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
3023 | LONGEST regval = extract_unsigned_integer (val, len); |
3024 | if (mips_debug) | |
acdb74a0 | 3025 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3026 | float_argreg, phex (regval, len)); |
c906108c | 3027 | write_register (float_argreg++, regval); |
c906108c SS |
3028 | } |
3029 | } | |
3030 | else | |
3031 | { | |
3032 | /* Copy the argument to general registers or the stack in | |
3033 | register-sized pieces. Large arguments are split between | |
3034 | registers and stack. */ | |
4246e332 | 3035 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
3036 | mips_abi_regsize() are treated specially: Irix cc passes |
3037 | them in registers where gcc sometimes puts them on the | |
3038 | stack. For maximum compatibility, we will put them in | |
3039 | both places. */ | |
13326b4e AC |
3040 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
3041 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
46e0f506 | 3042 | |
f09ded24 | 3043 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3044 | register are only written to memory. */ |
c906108c SS |
3045 | while (len > 0) |
3046 | { | |
ebafbe83 | 3047 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 3048 | int stack_used_p = 0; |
13326b4e AC |
3049 | int partial_len = (len < mips_abi_regsize (gdbarch) |
3050 | ? len : mips_abi_regsize (gdbarch)); | |
c906108c | 3051 | |
acdb74a0 AC |
3052 | if (mips_debug) |
3053 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3054 | partial_len); | |
3055 | ||
566f0f7a | 3056 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
3057 | if (argreg > MIPS_LAST_ARG_REGNUM |
3058 | || odd_sized_struct | |
3059 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 3060 | { |
c906108c SS |
3061 | /* Should shorter than int integer values be |
3062 | promoted to int before being stored? */ | |
c906108c | 3063 | int longword_offset = 0; |
9ace0497 | 3064 | CORE_ADDR addr; |
566f0f7a | 3065 | stack_used_p = 1; |
d7449b42 | 3066 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 3067 | { |
13326b4e | 3068 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
3069 | && (typecode == TYPE_CODE_INT |
3070 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3071 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 3072 | longword_offset = mips_stack_argsize (gdbarch) - len; |
480d3dd2 AC |
3073 | else if ((typecode == TYPE_CODE_STRUCT |
3074 | || typecode == TYPE_CODE_UNION) | |
3075 | && (TYPE_LENGTH (arg_type) | |
13326b4e AC |
3076 | < mips_stack_argsize (gdbarch))) |
3077 | longword_offset = mips_stack_argsize (gdbarch) - len; | |
7a292a7a | 3078 | } |
c5aa993b | 3079 | |
9ace0497 AC |
3080 | if (mips_debug) |
3081 | { | |
cb3d25d1 MS |
3082 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
3083 | paddr_nz (stack_offset)); | |
3084 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3085 | paddr_nz (longword_offset)); | |
9ace0497 | 3086 | } |
361d1df0 | 3087 | |
9ace0497 AC |
3088 | addr = sp + stack_offset + longword_offset; |
3089 | ||
3090 | if (mips_debug) | |
3091 | { | |
3092 | int i; | |
6d82d43b | 3093 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 | 3094 | paddr_nz (addr)); |
9ace0497 AC |
3095 | for (i = 0; i < partial_len; i++) |
3096 | { | |
6d82d43b | 3097 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 3098 | val[i] & 0xff); |
9ace0497 AC |
3099 | } |
3100 | } | |
3101 | write_memory (addr, val, partial_len); | |
c906108c SS |
3102 | } |
3103 | ||
f09ded24 AC |
3104 | /* Note!!! This is NOT an else clause. Odd sized |
3105 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 3106 | arguments will not. */ |
566f0f7a | 3107 | /* Write this portion of the argument to a general |
6d82d43b | 3108 | purpose register. */ |
f09ded24 AC |
3109 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3110 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 3111 | { |
6d82d43b AC |
3112 | LONGEST regval = |
3113 | extract_unsigned_integer (val, partial_len); | |
c906108c | 3114 | |
9ace0497 | 3115 | if (mips_debug) |
acdb74a0 | 3116 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 3117 | argreg, |
6d82d43b | 3118 | phex (regval, |
13326b4e | 3119 | mips_abi_regsize (gdbarch))); |
c906108c SS |
3120 | write_register (argreg, regval); |
3121 | argreg++; | |
c906108c | 3122 | } |
c5aa993b | 3123 | |
c906108c SS |
3124 | len -= partial_len; |
3125 | val += partial_len; | |
3126 | ||
566f0f7a | 3127 | /* Compute the the offset into the stack at which we |
6d82d43b | 3128 | will copy the next parameter. |
566f0f7a | 3129 | |
566f0f7a | 3130 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 3131 | only needs to be adjusted when it has been used. */ |
c906108c | 3132 | |
46e0f506 | 3133 | if (stack_used_p) |
480d3dd2 | 3134 | stack_offset += align_up (partial_len, |
13326b4e | 3135 | mips_stack_argsize (gdbarch)); |
c906108c SS |
3136 | } |
3137 | } | |
9ace0497 AC |
3138 | if (mips_debug) |
3139 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
3140 | } |
3141 | ||
f10683bb | 3142 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3143 | |
0f71a2f6 JM |
3144 | /* Return adjusted stack pointer. */ |
3145 | return sp; | |
3146 | } | |
3147 | ||
9c8fdbfa | 3148 | /* Determin the return value convention being used. */ |
6d82d43b | 3149 | |
9c8fdbfa AC |
3150 | static enum return_value_convention |
3151 | mips_eabi_return_value (struct gdbarch *gdbarch, | |
3152 | struct type *type, struct regcache *regcache, | |
3153 | void *readbuf, const void *writebuf) | |
6d82d43b | 3154 | { |
9c8fdbfa AC |
3155 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
3156 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3157 | if (readbuf) | |
3158 | memset (readbuf, 0, TYPE_LENGTH (type)); | |
3159 | return RETURN_VALUE_REGISTER_CONVENTION; | |
6d82d43b AC |
3160 | } |
3161 | ||
6d82d43b AC |
3162 | |
3163 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 3164 | |
f7ab6ec6 | 3165 | static CORE_ADDR |
7d9b040b | 3166 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3167 | struct regcache *regcache, CORE_ADDR bp_addr, |
3168 | int nargs, struct value **args, CORE_ADDR sp, | |
3169 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3170 | { |
3171 | int argreg; | |
3172 | int float_argreg; | |
3173 | int argnum; | |
3174 | int len = 0; | |
3175 | int stack_offset = 0; | |
480d3dd2 | 3176 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3177 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 3178 | |
25ab4790 AC |
3179 | /* For shared libraries, "t9" needs to point at the function |
3180 | address. */ | |
4c7d22cb | 3181 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3182 | |
3183 | /* Set the return address register to point to the entry point of | |
3184 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3185 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3186 | |
cb3d25d1 MS |
3187 | /* First ensure that the stack and structure return address (if any) |
3188 | are properly aligned. The stack has to be at least 64-bit | |
3189 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3190 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3191 | aligned, so we round to this widest known alignment. */ | |
3192 | ||
5b03f266 AC |
3193 | sp = align_down (sp, 16); |
3194 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3195 | |
3196 | /* Now make space on the stack for the args. */ | |
3197 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 3198 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 3199 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3200 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3201 | |
3202 | if (mips_debug) | |
6d82d43b | 3203 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3204 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
3205 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3206 | |
3207 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3208 | argreg = MIPS_A0_REGNUM; |
56cea623 | 3209 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 3210 | |
46e0f506 | 3211 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3212 | if (struct_return) |
3213 | { | |
3214 | if (mips_debug) | |
3215 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3216 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
3217 | argreg, paddr_nz (struct_addr)); |
3218 | write_register (argreg++, struct_addr); | |
3219 | } | |
3220 | ||
3221 | /* Now load as many as possible of the first arguments into | |
3222 | registers, and push the rest onto the stack. Loop thru args | |
3223 | from first to last. */ | |
3224 | for (argnum = 0; argnum < nargs; argnum++) | |
3225 | { | |
3226 | char *val; | |
cb3d25d1 MS |
3227 | struct value *arg = args[argnum]; |
3228 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3229 | int len = TYPE_LENGTH (arg_type); | |
3230 | enum type_code typecode = TYPE_CODE (arg_type); | |
3231 | ||
3232 | if (mips_debug) | |
3233 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3234 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3235 | argnum + 1, len, (int) typecode); |
3236 | ||
3237 | val = (char *) VALUE_CONTENTS (arg); | |
3238 | ||
3239 | if (fp_register_arg_p (typecode, arg_type) | |
3240 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3241 | { | |
3242 | /* This is a floating point value that fits entirely | |
3243 | in a single register. */ | |
3244 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3245 | above to ensure that it is even register aligned. */ | |
3246 | LONGEST regval = extract_unsigned_integer (val, len); | |
3247 | if (mips_debug) | |
3248 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3249 | float_argreg, phex (regval, len)); | |
3250 | write_register (float_argreg++, regval); | |
3251 | ||
3252 | if (mips_debug) | |
3253 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3254 | argreg, phex (regval, len)); | |
3255 | write_register (argreg, regval); | |
3256 | argreg += 1; | |
3257 | } | |
3258 | else | |
3259 | { | |
3260 | /* Copy the argument to general registers or the stack in | |
3261 | register-sized pieces. Large arguments are split between | |
3262 | registers and stack. */ | |
4246e332 | 3263 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
3264 | mips_abi_regsize() are treated specially: Irix cc passes |
3265 | them in registers where gcc sometimes puts them on the | |
3266 | stack. For maximum compatibility, we will put them in | |
3267 | both places. */ | |
13326b4e AC |
3268 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
3269 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
cb3d25d1 | 3270 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3271 | register are only written to memory. */ |
cb3d25d1 MS |
3272 | while (len > 0) |
3273 | { | |
3274 | /* Rememer if the argument was written to the stack. */ | |
3275 | int stack_used_p = 0; | |
13326b4e AC |
3276 | int partial_len = (len < mips_abi_regsize (gdbarch) |
3277 | ? len : mips_abi_regsize (gdbarch)); | |
cb3d25d1 MS |
3278 | |
3279 | if (mips_debug) | |
3280 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3281 | partial_len); | |
3282 | ||
3283 | /* Write this portion of the argument to the stack. */ | |
3284 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3285 | || odd_sized_struct | |
3286 | || fp_register_arg_p (typecode, arg_type)) | |
3287 | { | |
3288 | /* Should shorter than int integer values be | |
3289 | promoted to int before being stored? */ | |
3290 | int longword_offset = 0; | |
3291 | CORE_ADDR addr; | |
3292 | stack_used_p = 1; | |
3293 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3294 | { | |
13326b4e | 3295 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
3296 | && (typecode == TYPE_CODE_INT |
3297 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3298 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 3299 | longword_offset = mips_stack_argsize (gdbarch) - len; |
cb3d25d1 MS |
3300 | } |
3301 | ||
3302 | if (mips_debug) | |
3303 | { | |
3304 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3305 | paddr_nz (stack_offset)); | |
3306 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3307 | paddr_nz (longword_offset)); | |
3308 | } | |
3309 | ||
3310 | addr = sp + stack_offset + longword_offset; | |
3311 | ||
3312 | if (mips_debug) | |
3313 | { | |
3314 | int i; | |
6d82d43b | 3315 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 MS |
3316 | paddr_nz (addr)); |
3317 | for (i = 0; i < partial_len; i++) | |
3318 | { | |
6d82d43b | 3319 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3320 | val[i] & 0xff); |
3321 | } | |
3322 | } | |
3323 | write_memory (addr, val, partial_len); | |
3324 | } | |
3325 | ||
3326 | /* Note!!! This is NOT an else clause. Odd sized | |
3327 | structs may go thru BOTH paths. Floating point | |
3328 | arguments will not. */ | |
3329 | /* Write this portion of the argument to a general | |
6d82d43b | 3330 | purpose register. */ |
cb3d25d1 MS |
3331 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3332 | && !fp_register_arg_p (typecode, arg_type)) | |
3333 | { | |
6d82d43b AC |
3334 | LONGEST regval = |
3335 | extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
3336 | |
3337 | /* A non-floating-point argument being passed in a | |
3338 | general register. If a struct or union, and if | |
3339 | the remaining length is smaller than the register | |
3340 | size, we have to adjust the register value on | |
3341 | big endian targets. | |
3342 | ||
3343 | It does not seem to be necessary to do the | |
3344 | same for integral types. | |
3345 | ||
3346 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3347 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 3348 | mips_abi_regsize(), generates a left shift as |
cb3d25d1 MS |
3349 | part of storing the argument in a register a |
3350 | register (the left shift isn't generated when | |
1b13c4f6 | 3351 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3352 | it is quite possible that this is GCC |
3353 | contradicting the LE/O32 ABI, GDB has not been | |
3354 | adjusted to accommodate this. Either someone | |
3355 | needs to demonstrate that the LE/O32 ABI | |
3356 | specifies such a left shift OR this new ABI gets | |
3357 | identified as such and GDB gets tweaked | |
3358 | accordingly. */ | |
cb3d25d1 MS |
3359 | |
3360 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
13326b4e | 3361 | && partial_len < mips_abi_regsize (gdbarch) |
cb3d25d1 MS |
3362 | && (typecode == TYPE_CODE_STRUCT || |
3363 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 3364 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
cb3d25d1 MS |
3365 | TARGET_CHAR_BIT); |
3366 | ||
3367 | if (mips_debug) | |
3368 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3369 | argreg, | |
6d82d43b | 3370 | phex (regval, |
13326b4e | 3371 | mips_abi_regsize (gdbarch))); |
cb3d25d1 MS |
3372 | write_register (argreg, regval); |
3373 | argreg++; | |
3374 | } | |
3375 | ||
3376 | len -= partial_len; | |
3377 | val += partial_len; | |
3378 | ||
3379 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3380 | will copy the next parameter. |
cb3d25d1 MS |
3381 | |
3382 | In N32 (N64?), the stack_offset only needs to be | |
3383 | adjusted when it has been used. */ | |
3384 | ||
3385 | if (stack_used_p) | |
480d3dd2 | 3386 | stack_offset += align_up (partial_len, |
13326b4e | 3387 | mips_stack_argsize (gdbarch)); |
cb3d25d1 MS |
3388 | } |
3389 | } | |
3390 | if (mips_debug) | |
3391 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3392 | } | |
3393 | ||
f10683bb | 3394 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3395 | |
cb3d25d1 MS |
3396 | /* Return adjusted stack pointer. */ |
3397 | return sp; | |
3398 | } | |
3399 | ||
6d82d43b AC |
3400 | static enum return_value_convention |
3401 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
3402 | struct type *type, struct regcache *regcache, | |
3403 | void *readbuf, const void *writebuf) | |
ebafbe83 | 3404 | { |
6d82d43b AC |
3405 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3406 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3407 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3408 | || TYPE_CODE (type) == TYPE_CODE_ARRAY | |
13326b4e | 3409 | || TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
6d82d43b AC |
3410 | return RETURN_VALUE_STRUCT_CONVENTION; |
3411 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3412 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3413 | { | |
3414 | /* A floating-point value belongs in the least significant part | |
3415 | of FP0. */ | |
3416 | if (mips_debug) | |
3417 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3418 | mips_xfer_register (regcache, | |
3419 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
3420 | TYPE_LENGTH (type), | |
3421 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3422 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3423 | } | |
3424 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3425 | && TYPE_NFIELDS (type) <= 2 | |
3426 | && TYPE_NFIELDS (type) >= 1 | |
3427 | && ((TYPE_NFIELDS (type) == 1 | |
3428 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3429 | == TYPE_CODE_FLT)) | |
3430 | || (TYPE_NFIELDS (type) == 2 | |
3431 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3432 | == TYPE_CODE_FLT) | |
3433 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3434 | == TYPE_CODE_FLT))) | |
3435 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3436 | { | |
3437 | /* A struct that contains one or two floats. Each value is part | |
3438 | in the least significant part of their floating point | |
3439 | register.. */ | |
6d82d43b AC |
3440 | int regnum; |
3441 | int field; | |
3442 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3443 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3444 | { | |
3445 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3446 | / TARGET_CHAR_BIT); | |
3447 | if (mips_debug) | |
3448 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3449 | offset); | |
3450 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
3451 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3452 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3453 | } | |
3454 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3455 | } | |
3456 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3457 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3458 | { | |
3459 | /* A structure or union. Extract the left justified value, | |
3460 | regardless of the byte order. I.e. DO NOT USE | |
3461 | mips_xfer_lower. */ | |
3462 | int offset; | |
3463 | int regnum; | |
4c7d22cb | 3464 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3465 | offset < TYPE_LENGTH (type); |
3466 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3467 | { | |
3468 | int xfer = register_size (current_gdbarch, regnum); | |
3469 | if (offset + xfer > TYPE_LENGTH (type)) | |
3470 | xfer = TYPE_LENGTH (type) - offset; | |
3471 | if (mips_debug) | |
3472 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3473 | offset, xfer, regnum); | |
3474 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3475 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
3476 | } | |
3477 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3478 | } | |
3479 | else | |
3480 | { | |
3481 | /* A scalar extract each part but least-significant-byte | |
3482 | justified. */ | |
3483 | int offset; | |
3484 | int regnum; | |
4c7d22cb | 3485 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3486 | offset < TYPE_LENGTH (type); |
3487 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3488 | { | |
3489 | int xfer = register_size (current_gdbarch, regnum); | |
6d82d43b AC |
3490 | if (offset + xfer > TYPE_LENGTH (type)) |
3491 | xfer = TYPE_LENGTH (type) - offset; | |
3492 | if (mips_debug) | |
3493 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3494 | offset, xfer, regnum); | |
3495 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3496 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3497 | } | |
3498 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3499 | } | |
3500 | } | |
3501 | ||
3502 | /* O32 ABI stuff. */ | |
3503 | ||
3504 | static CORE_ADDR | |
7d9b040b | 3505 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3506 | struct regcache *regcache, CORE_ADDR bp_addr, |
3507 | int nargs, struct value **args, CORE_ADDR sp, | |
3508 | int struct_return, CORE_ADDR struct_addr) | |
3509 | { | |
3510 | int argreg; | |
3511 | int float_argreg; | |
3512 | int argnum; | |
3513 | int len = 0; | |
3514 | int stack_offset = 0; | |
3515 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7d9b040b | 3516 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3517 | |
3518 | /* For shared libraries, "t9" needs to point at the function | |
3519 | address. */ | |
4c7d22cb | 3520 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3521 | |
3522 | /* Set the return address register to point to the entry point of | |
3523 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3524 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3525 | |
3526 | /* First ensure that the stack and structure return address (if any) | |
3527 | are properly aligned. The stack has to be at least 64-bit | |
3528 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3529 | aligned. For n32 and n64, stack frames need to be 128-bit |
3530 | aligned, so we round to this widest known alignment. */ | |
3531 | ||
5b03f266 AC |
3532 | sp = align_down (sp, 16); |
3533 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3534 | |
3535 | /* Now make space on the stack for the args. */ | |
3536 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 3537 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 3538 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3539 | sp -= align_up (len, 16); |
ebafbe83 MS |
3540 | |
3541 | if (mips_debug) | |
6d82d43b | 3542 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3543 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3544 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3545 | |
3546 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3547 | argreg = MIPS_A0_REGNUM; |
56cea623 | 3548 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 3549 | |
bcb0cc15 | 3550 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3551 | if (struct_return) |
3552 | { | |
3553 | if (mips_debug) | |
3554 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3555 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
3556 | argreg, paddr_nz (struct_addr)); |
3557 | write_register (argreg++, struct_addr); | |
13326b4e | 3558 | stack_offset += mips_stack_argsize (gdbarch); |
ebafbe83 MS |
3559 | } |
3560 | ||
3561 | /* Now load as many as possible of the first arguments into | |
3562 | registers, and push the rest onto the stack. Loop thru args | |
3563 | from first to last. */ | |
3564 | for (argnum = 0; argnum < nargs; argnum++) | |
3565 | { | |
3566 | char *val; | |
ebafbe83 MS |
3567 | struct value *arg = args[argnum]; |
3568 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3569 | int len = TYPE_LENGTH (arg_type); | |
3570 | enum type_code typecode = TYPE_CODE (arg_type); | |
3571 | ||
3572 | if (mips_debug) | |
3573 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3574 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3575 | argnum + 1, len, (int) typecode); |
3576 | ||
3577 | val = (char *) VALUE_CONTENTS (arg); | |
3578 | ||
3579 | /* 32-bit ABIs always start floating point arguments in an | |
3580 | even-numbered floating point register. Round the FP register | |
3581 | up before the check to see if there are any FP registers | |
3582 | left. O32/O64 targets also pass the FP in the integer | |
3583 | registers so also round up normal registers. */ | |
ceae6e75 AC |
3584 | if (mips_abi_regsize (gdbarch) < 8 |
3585 | && fp_register_arg_p (typecode, arg_type)) | |
46cac009 AC |
3586 | { |
3587 | if ((float_argreg & 1)) | |
3588 | float_argreg++; | |
3589 | } | |
3590 | ||
3591 | /* Floating point arguments passed in registers have to be | |
3592 | treated specially. On 32-bit architectures, doubles | |
3593 | are passed in register pairs; the even register gets | |
3594 | the low word, and the odd register gets the high word. | |
3595 | On O32/O64, the first two floating point arguments are | |
3596 | also copied to general registers, because MIPS16 functions | |
3597 | don't use float registers for arguments. This duplication of | |
3598 | arguments in general registers can't hurt non-MIPS16 functions | |
3599 | because those registers are normally skipped. */ | |
3600 | ||
3601 | if (fp_register_arg_p (typecode, arg_type) | |
3602 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3603 | { | |
ceae6e75 | 3604 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
46cac009 AC |
3605 | { |
3606 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3607 | unsigned long regval; | |
3608 | ||
3609 | /* Write the low word of the double to the even register(s). */ | |
3610 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3611 | if (mips_debug) | |
3612 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3613 | float_argreg, phex (regval, 4)); | |
3614 | write_register (float_argreg++, regval); | |
3615 | if (mips_debug) | |
3616 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3617 | argreg, phex (regval, 4)); | |
3618 | write_register (argreg++, regval); | |
3619 | ||
3620 | /* Write the high word of the double to the odd register(s). */ | |
3621 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3622 | if (mips_debug) | |
3623 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3624 | float_argreg, phex (regval, 4)); | |
3625 | write_register (float_argreg++, regval); | |
3626 | ||
3627 | if (mips_debug) | |
3628 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3629 | argreg, phex (regval, 4)); | |
3630 | write_register (argreg++, regval); | |
3631 | } | |
3632 | else | |
3633 | { | |
3634 | /* This is a floating point value that fits entirely | |
3635 | in a single register. */ | |
3636 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3637 | above to ensure that it is even register aligned. */ |
46cac009 AC |
3638 | LONGEST regval = extract_unsigned_integer (val, len); |
3639 | if (mips_debug) | |
3640 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3641 | float_argreg, phex (regval, len)); | |
3642 | write_register (float_argreg++, regval); | |
3643 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
3644 | registers for each argument. The below is (my |
3645 | guess) to ensure that the corresponding integer | |
3646 | register has reserved the same space. */ | |
46cac009 AC |
3647 | if (mips_debug) |
3648 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3649 | argreg, phex (regval, len)); | |
3650 | write_register (argreg, regval); | |
ceae6e75 | 3651 | argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2; |
46cac009 AC |
3652 | } |
3653 | /* Reserve space for the FP register. */ | |
13326b4e | 3654 | stack_offset += align_up (len, mips_stack_argsize (gdbarch)); |
46cac009 AC |
3655 | } |
3656 | else | |
3657 | { | |
3658 | /* Copy the argument to general registers or the stack in | |
3659 | register-sized pieces. Large arguments are split between | |
3660 | registers and stack. */ | |
4246e332 | 3661 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
3662 | mips_abi_regsize() are treated specially: Irix cc passes |
3663 | them in registers where gcc sometimes puts them on the | |
3664 | stack. For maximum compatibility, we will put them in | |
3665 | both places. */ | |
13326b4e AC |
3666 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
3667 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
46cac009 AC |
3668 | /* Structures should be aligned to eight bytes (even arg registers) |
3669 | on MIPS_ABI_O32, if their first member has double precision. */ | |
13326b4e | 3670 | if (mips_abi_regsize (gdbarch) < 8 |
46cac009 AC |
3671 | && mips_type_needs_double_align (arg_type)) |
3672 | { | |
3673 | if ((argreg & 1)) | |
6d82d43b | 3674 | argreg++; |
46cac009 AC |
3675 | } |
3676 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 3677 | register are only written to memory. */ |
46cac009 AC |
3678 | while (len > 0) |
3679 | { | |
3680 | /* Remember if the argument was written to the stack. */ | |
3681 | int stack_used_p = 0; | |
13326b4e AC |
3682 | int partial_len = (len < mips_abi_regsize (gdbarch) |
3683 | ? len : mips_abi_regsize (gdbarch)); | |
46cac009 AC |
3684 | |
3685 | if (mips_debug) | |
3686 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3687 | partial_len); | |
3688 | ||
3689 | /* Write this portion of the argument to the stack. */ | |
3690 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3691 | || odd_sized_struct | |
3692 | || fp_register_arg_p (typecode, arg_type)) | |
3693 | { | |
3694 | /* Should shorter than int integer values be | |
3695 | promoted to int before being stored? */ | |
3696 | int longword_offset = 0; | |
3697 | CORE_ADDR addr; | |
3698 | stack_used_p = 1; | |
3699 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3700 | { | |
13326b4e | 3701 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
3702 | && (typecode == TYPE_CODE_INT |
3703 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3704 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 3705 | longword_offset = mips_stack_argsize (gdbarch) - len; |
46cac009 AC |
3706 | } |
3707 | ||
3708 | if (mips_debug) | |
3709 | { | |
3710 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3711 | paddr_nz (stack_offset)); | |
3712 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3713 | paddr_nz (longword_offset)); | |
3714 | } | |
3715 | ||
3716 | addr = sp + stack_offset + longword_offset; | |
3717 | ||
3718 | if (mips_debug) | |
3719 | { | |
3720 | int i; | |
6d82d43b | 3721 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
46cac009 AC |
3722 | paddr_nz (addr)); |
3723 | for (i = 0; i < partial_len; i++) | |
3724 | { | |
6d82d43b | 3725 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3726 | val[i] & 0xff); |
3727 | } | |
3728 | } | |
3729 | write_memory (addr, val, partial_len); | |
3730 | } | |
3731 | ||
3732 | /* Note!!! This is NOT an else clause. Odd sized | |
3733 | structs may go thru BOTH paths. Floating point | |
3734 | arguments will not. */ | |
3735 | /* Write this portion of the argument to a general | |
6d82d43b | 3736 | purpose register. */ |
46cac009 AC |
3737 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3738 | && !fp_register_arg_p (typecode, arg_type)) | |
3739 | { | |
3740 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3741 | /* Value may need to be sign extended, because |
1b13c4f6 | 3742 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3743 | |
3744 | /* A non-floating-point argument being passed in a | |
3745 | general register. If a struct or union, and if | |
3746 | the remaining length is smaller than the register | |
3747 | size, we have to adjust the register value on | |
3748 | big endian targets. | |
3749 | ||
3750 | It does not seem to be necessary to do the | |
3751 | same for integral types. | |
3752 | ||
3753 | Also don't do this adjustment on O64 binaries. | |
3754 | ||
3755 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3756 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 3757 | mips_abi_regsize(), generates a left shift as |
46cac009 AC |
3758 | part of storing the argument in a register a |
3759 | register (the left shift isn't generated when | |
1b13c4f6 | 3760 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3761 | it is quite possible that this is GCC |
3762 | contradicting the LE/O32 ABI, GDB has not been | |
3763 | adjusted to accommodate this. Either someone | |
3764 | needs to demonstrate that the LE/O32 ABI | |
3765 | specifies such a left shift OR this new ABI gets | |
3766 | identified as such and GDB gets tweaked | |
3767 | accordingly. */ | |
3768 | ||
13326b4e | 3769 | if (mips_abi_regsize (gdbarch) < 8 |
46cac009 | 3770 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
13326b4e | 3771 | && partial_len < mips_abi_regsize (gdbarch) |
46cac009 AC |
3772 | && (typecode == TYPE_CODE_STRUCT || |
3773 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 3774 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
46cac009 AC |
3775 | TARGET_CHAR_BIT); |
3776 | ||
3777 | if (mips_debug) | |
3778 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3779 | argreg, | |
6d82d43b | 3780 | phex (regval, |
13326b4e | 3781 | mips_abi_regsize (gdbarch))); |
46cac009 AC |
3782 | write_register (argreg, regval); |
3783 | argreg++; | |
3784 | ||
3785 | /* Prevent subsequent floating point arguments from | |
3786 | being passed in floating point registers. */ | |
3787 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3788 | } | |
3789 | ||
3790 | len -= partial_len; | |
3791 | val += partial_len; | |
3792 | ||
3793 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3794 | will copy the next parameter. |
46cac009 | 3795 | |
6d82d43b AC |
3796 | In older ABIs, the caller reserved space for |
3797 | registers that contained arguments. This was loosely | |
3798 | refered to as their "home". Consequently, space is | |
3799 | always allocated. */ | |
46cac009 | 3800 | |
480d3dd2 | 3801 | stack_offset += align_up (partial_len, |
13326b4e | 3802 | mips_stack_argsize (gdbarch)); |
46cac009 AC |
3803 | } |
3804 | } | |
3805 | if (mips_debug) | |
3806 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3807 | } | |
3808 | ||
f10683bb | 3809 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3810 | |
46cac009 AC |
3811 | /* Return adjusted stack pointer. */ |
3812 | return sp; | |
3813 | } | |
3814 | ||
6d82d43b AC |
3815 | static enum return_value_convention |
3816 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
3817 | struct regcache *regcache, | |
3818 | void *readbuf, const void *writebuf) | |
3819 | { | |
3820 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3821 | ||
3822 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3823 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3824 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3825 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3826 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3827 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3828 | { | |
3829 | /* A single-precision floating-point value. It fits in the | |
3830 | least significant part of FP0. */ | |
3831 | if (mips_debug) | |
3832 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3833 | mips_xfer_register (regcache, | |
3834 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
3835 | TYPE_LENGTH (type), | |
3836 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3837 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3838 | } | |
3839 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3840 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3841 | { | |
3842 | /* A double-precision floating-point value. The most | |
3843 | significant part goes in FP1, and the least significant in | |
3844 | FP0. */ | |
3845 | if (mips_debug) | |
3846 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
3847 | switch (TARGET_BYTE_ORDER) | |
3848 | { | |
3849 | case BFD_ENDIAN_LITTLE: | |
3850 | mips_xfer_register (regcache, | |
3851 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3852 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3853 | mips_xfer_register (regcache, | |
3854 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3855 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
3856 | break; | |
3857 | case BFD_ENDIAN_BIG: | |
3858 | mips_xfer_register (regcache, | |
3859 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3860 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3861 | mips_xfer_register (regcache, | |
3862 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3863 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
3864 | break; | |
3865 | default: | |
3866 | internal_error (__FILE__, __LINE__, "bad switch"); | |
3867 | } | |
3868 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3869 | } | |
3870 | #if 0 | |
3871 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3872 | && TYPE_NFIELDS (type) <= 2 | |
3873 | && TYPE_NFIELDS (type) >= 1 | |
3874 | && ((TYPE_NFIELDS (type) == 1 | |
3875 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3876 | == TYPE_CODE_FLT)) | |
3877 | || (TYPE_NFIELDS (type) == 2 | |
3878 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3879 | == TYPE_CODE_FLT) | |
3880 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3881 | == TYPE_CODE_FLT))) | |
3882 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3883 | { | |
3884 | /* A struct that contains one or two floats. Each value is part | |
3885 | in the least significant part of their floating point | |
3886 | register.. */ | |
3887 | bfd_byte reg[MAX_REGISTER_SIZE]; | |
3888 | int regnum; | |
3889 | int field; | |
3890 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3891 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3892 | { | |
3893 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3894 | / TARGET_CHAR_BIT); | |
3895 | if (mips_debug) | |
3896 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3897 | offset); | |
3898 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
3899 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3900 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3901 | } | |
3902 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3903 | } | |
3904 | #endif | |
3905 | #if 0 | |
3906 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3907 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3908 | { | |
3909 | /* A structure or union. Extract the left justified value, | |
3910 | regardless of the byte order. I.e. DO NOT USE | |
3911 | mips_xfer_lower. */ | |
3912 | int offset; | |
3913 | int regnum; | |
4c7d22cb | 3914 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3915 | offset < TYPE_LENGTH (type); |
3916 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3917 | { | |
3918 | int xfer = register_size (current_gdbarch, regnum); | |
3919 | if (offset + xfer > TYPE_LENGTH (type)) | |
3920 | xfer = TYPE_LENGTH (type) - offset; | |
3921 | if (mips_debug) | |
3922 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3923 | offset, xfer, regnum); | |
3924 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3925 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
3926 | } | |
3927 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3928 | } | |
3929 | #endif | |
3930 | else | |
3931 | { | |
3932 | /* A scalar extract each part but least-significant-byte | |
3933 | justified. o32 thinks registers are 4 byte, regardless of | |
3934 | the ISA. mips_stack_argsize controls this. */ | |
3935 | int offset; | |
3936 | int regnum; | |
4c7d22cb | 3937 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3938 | offset < TYPE_LENGTH (type); |
13326b4e | 3939 | offset += mips_stack_argsize (gdbarch), regnum++) |
6d82d43b | 3940 | { |
13326b4e | 3941 | int xfer = mips_stack_argsize (gdbarch); |
6d82d43b AC |
3942 | if (offset + xfer > TYPE_LENGTH (type)) |
3943 | xfer = TYPE_LENGTH (type) - offset; | |
3944 | if (mips_debug) | |
3945 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3946 | offset, xfer, regnum); | |
3947 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3948 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3949 | } | |
3950 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3951 | } | |
3952 | } | |
3953 | ||
3954 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
3955 | ABI. */ | |
46cac009 AC |
3956 | |
3957 | static CORE_ADDR | |
7d9b040b | 3958 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3959 | struct regcache *regcache, CORE_ADDR bp_addr, |
3960 | int nargs, | |
3961 | struct value **args, CORE_ADDR sp, | |
3962 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
3963 | { |
3964 | int argreg; | |
3965 | int float_argreg; | |
3966 | int argnum; | |
3967 | int len = 0; | |
3968 | int stack_offset = 0; | |
480d3dd2 | 3969 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3970 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 3971 | |
25ab4790 AC |
3972 | /* For shared libraries, "t9" needs to point at the function |
3973 | address. */ | |
4c7d22cb | 3974 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3975 | |
3976 | /* Set the return address register to point to the entry point of | |
3977 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3978 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3979 | |
46cac009 AC |
3980 | /* First ensure that the stack and structure return address (if any) |
3981 | are properly aligned. The stack has to be at least 64-bit | |
3982 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3983 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3984 | aligned, so we round to this widest known alignment. */ | |
3985 | ||
5b03f266 AC |
3986 | sp = align_down (sp, 16); |
3987 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3988 | |
3989 | /* Now make space on the stack for the args. */ | |
3990 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 3991 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 3992 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3993 | sp -= align_up (len, 16); |
46cac009 AC |
3994 | |
3995 | if (mips_debug) | |
6d82d43b | 3996 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3997 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
3998 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
3999 | |
4000 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4001 | argreg = MIPS_A0_REGNUM; |
56cea623 | 4002 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
4003 | |
4004 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
4005 | if (struct_return) | |
4006 | { | |
4007 | if (mips_debug) | |
4008 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4009 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
4010 | argreg, paddr_nz (struct_addr)); |
4011 | write_register (argreg++, struct_addr); | |
13326b4e | 4012 | stack_offset += mips_stack_argsize (gdbarch); |
46cac009 AC |
4013 | } |
4014 | ||
4015 | /* Now load as many as possible of the first arguments into | |
4016 | registers, and push the rest onto the stack. Loop thru args | |
4017 | from first to last. */ | |
4018 | for (argnum = 0; argnum < nargs; argnum++) | |
4019 | { | |
4020 | char *val; | |
46cac009 AC |
4021 | struct value *arg = args[argnum]; |
4022 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
4023 | int len = TYPE_LENGTH (arg_type); | |
4024 | enum type_code typecode = TYPE_CODE (arg_type); | |
4025 | ||
4026 | if (mips_debug) | |
4027 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4028 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
4029 | argnum + 1, len, (int) typecode); |
4030 | ||
4031 | val = (char *) VALUE_CONTENTS (arg); | |
4032 | ||
4033 | /* 32-bit ABIs always start floating point arguments in an | |
4034 | even-numbered floating point register. Round the FP register | |
4035 | up before the check to see if there are any FP registers | |
4036 | left. O32/O64 targets also pass the FP in the integer | |
4037 | registers so also round up normal registers. */ | |
ceae6e75 AC |
4038 | if (mips_abi_regsize (gdbarch) < 8 |
4039 | && fp_register_arg_p (typecode, arg_type)) | |
ebafbe83 MS |
4040 | { |
4041 | if ((float_argreg & 1)) | |
4042 | float_argreg++; | |
4043 | } | |
4044 | ||
4045 | /* Floating point arguments passed in registers have to be | |
4046 | treated specially. On 32-bit architectures, doubles | |
4047 | are passed in register pairs; the even register gets | |
4048 | the low word, and the odd register gets the high word. | |
4049 | On O32/O64, the first two floating point arguments are | |
4050 | also copied to general registers, because MIPS16 functions | |
4051 | don't use float registers for arguments. This duplication of | |
4052 | arguments in general registers can't hurt non-MIPS16 functions | |
4053 | because those registers are normally skipped. */ | |
4054 | ||
4055 | if (fp_register_arg_p (typecode, arg_type) | |
4056 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
4057 | { | |
ceae6e75 | 4058 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
ebafbe83 MS |
4059 | { |
4060 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
4061 | unsigned long regval; | |
4062 | ||
4063 | /* Write the low word of the double to the even register(s). */ | |
4064 | regval = extract_unsigned_integer (val + low_offset, 4); | |
4065 | if (mips_debug) | |
4066 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4067 | float_argreg, phex (regval, 4)); | |
4068 | write_register (float_argreg++, regval); | |
4069 | if (mips_debug) | |
4070 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4071 | argreg, phex (regval, 4)); | |
4072 | write_register (argreg++, regval); | |
4073 | ||
4074 | /* Write the high word of the double to the odd register(s). */ | |
4075 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
4076 | if (mips_debug) | |
4077 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4078 | float_argreg, phex (regval, 4)); | |
4079 | write_register (float_argreg++, regval); | |
4080 | ||
4081 | if (mips_debug) | |
4082 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4083 | argreg, phex (regval, 4)); | |
4084 | write_register (argreg++, regval); | |
4085 | } | |
4086 | else | |
4087 | { | |
4088 | /* This is a floating point value that fits entirely | |
4089 | in a single register. */ | |
4090 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 4091 | above to ensure that it is even register aligned. */ |
ebafbe83 MS |
4092 | LONGEST regval = extract_unsigned_integer (val, len); |
4093 | if (mips_debug) | |
4094 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4095 | float_argreg, phex (regval, len)); | |
4096 | write_register (float_argreg++, regval); | |
4097 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
4098 | registers for each argument. The below is (my |
4099 | guess) to ensure that the corresponding integer | |
4100 | register has reserved the same space. */ | |
ebafbe83 MS |
4101 | if (mips_debug) |
4102 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4103 | argreg, phex (regval, len)); | |
4104 | write_register (argreg, regval); | |
ceae6e75 | 4105 | argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2; |
ebafbe83 MS |
4106 | } |
4107 | /* Reserve space for the FP register. */ | |
13326b4e | 4108 | stack_offset += align_up (len, mips_stack_argsize (gdbarch)); |
ebafbe83 MS |
4109 | } |
4110 | else | |
4111 | { | |
4112 | /* Copy the argument to general registers or the stack in | |
4113 | register-sized pieces. Large arguments are split between | |
4114 | registers and stack. */ | |
4246e332 | 4115 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
4116 | mips_abi_regsize() are treated specially: Irix cc passes |
4117 | them in registers where gcc sometimes puts them on the | |
4118 | stack. For maximum compatibility, we will put them in | |
4119 | both places. */ | |
13326b4e AC |
4120 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
4121 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
ebafbe83 MS |
4122 | /* Structures should be aligned to eight bytes (even arg registers) |
4123 | on MIPS_ABI_O32, if their first member has double precision. */ | |
13326b4e | 4124 | if (mips_abi_regsize (gdbarch) < 8 |
ebafbe83 MS |
4125 | && mips_type_needs_double_align (arg_type)) |
4126 | { | |
4127 | if ((argreg & 1)) | |
6d82d43b | 4128 | argreg++; |
ebafbe83 MS |
4129 | } |
4130 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 4131 | register are only written to memory. */ |
ebafbe83 MS |
4132 | while (len > 0) |
4133 | { | |
4134 | /* Remember if the argument was written to the stack. */ | |
4135 | int stack_used_p = 0; | |
13326b4e AC |
4136 | int partial_len = (len < mips_abi_regsize (gdbarch) |
4137 | ? len : mips_abi_regsize (gdbarch)); | |
ebafbe83 MS |
4138 | |
4139 | if (mips_debug) | |
4140 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4141 | partial_len); | |
4142 | ||
4143 | /* Write this portion of the argument to the stack. */ | |
4144 | if (argreg > MIPS_LAST_ARG_REGNUM | |
4145 | || odd_sized_struct | |
4146 | || fp_register_arg_p (typecode, arg_type)) | |
4147 | { | |
4148 | /* Should shorter than int integer values be | |
4149 | promoted to int before being stored? */ | |
4150 | int longword_offset = 0; | |
4151 | CORE_ADDR addr; | |
4152 | stack_used_p = 1; | |
4153 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4154 | { | |
13326b4e | 4155 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
4156 | && (typecode == TYPE_CODE_INT |
4157 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4158 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 4159 | longword_offset = mips_stack_argsize (gdbarch) - len; |
ebafbe83 MS |
4160 | } |
4161 | ||
4162 | if (mips_debug) | |
4163 | { | |
4164 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
4165 | paddr_nz (stack_offset)); | |
4166 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
4167 | paddr_nz (longword_offset)); | |
4168 | } | |
4169 | ||
4170 | addr = sp + stack_offset + longword_offset; | |
4171 | ||
4172 | if (mips_debug) | |
4173 | { | |
4174 | int i; | |
6d82d43b | 4175 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
ebafbe83 MS |
4176 | paddr_nz (addr)); |
4177 | for (i = 0; i < partial_len; i++) | |
4178 | { | |
6d82d43b | 4179 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4180 | val[i] & 0xff); |
4181 | } | |
4182 | } | |
4183 | write_memory (addr, val, partial_len); | |
4184 | } | |
4185 | ||
4186 | /* Note!!! This is NOT an else clause. Odd sized | |
4187 | structs may go thru BOTH paths. Floating point | |
4188 | arguments will not. */ | |
4189 | /* Write this portion of the argument to a general | |
6d82d43b | 4190 | purpose register. */ |
ebafbe83 MS |
4191 | if (argreg <= MIPS_LAST_ARG_REGNUM |
4192 | && !fp_register_arg_p (typecode, arg_type)) | |
4193 | { | |
4194 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 4195 | /* Value may need to be sign extended, because |
1b13c4f6 | 4196 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
4197 | |
4198 | /* A non-floating-point argument being passed in a | |
4199 | general register. If a struct or union, and if | |
4200 | the remaining length is smaller than the register | |
4201 | size, we have to adjust the register value on | |
4202 | big endian targets. | |
4203 | ||
4204 | It does not seem to be necessary to do the | |
4205 | same for integral types. | |
4206 | ||
4207 | Also don't do this adjustment on O64 binaries. | |
4208 | ||
4209 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
4210 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 4211 | mips_abi_regsize(), generates a left shift as |
ebafbe83 MS |
4212 | part of storing the argument in a register a |
4213 | register (the left shift isn't generated when | |
1b13c4f6 | 4214 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
4215 | it is quite possible that this is GCC |
4216 | contradicting the LE/O32 ABI, GDB has not been | |
4217 | adjusted to accommodate this. Either someone | |
4218 | needs to demonstrate that the LE/O32 ABI | |
4219 | specifies such a left shift OR this new ABI gets | |
4220 | identified as such and GDB gets tweaked | |
4221 | accordingly. */ | |
4222 | ||
13326b4e | 4223 | if (mips_abi_regsize (gdbarch) < 8 |
ebafbe83 | 4224 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
13326b4e | 4225 | && partial_len < mips_abi_regsize (gdbarch) |
ebafbe83 MS |
4226 | && (typecode == TYPE_CODE_STRUCT || |
4227 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 4228 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
ebafbe83 MS |
4229 | TARGET_CHAR_BIT); |
4230 | ||
4231 | if (mips_debug) | |
4232 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4233 | argreg, | |
6d82d43b | 4234 | phex (regval, |
13326b4e | 4235 | mips_abi_regsize (gdbarch))); |
ebafbe83 MS |
4236 | write_register (argreg, regval); |
4237 | argreg++; | |
4238 | ||
4239 | /* Prevent subsequent floating point arguments from | |
4240 | being passed in floating point registers. */ | |
4241 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
4242 | } | |
4243 | ||
4244 | len -= partial_len; | |
4245 | val += partial_len; | |
4246 | ||
4247 | /* Compute the the offset into the stack at which we | |
6d82d43b | 4248 | will copy the next parameter. |
ebafbe83 | 4249 | |
6d82d43b AC |
4250 | In older ABIs, the caller reserved space for |
4251 | registers that contained arguments. This was loosely | |
4252 | refered to as their "home". Consequently, space is | |
4253 | always allocated. */ | |
ebafbe83 | 4254 | |
480d3dd2 | 4255 | stack_offset += align_up (partial_len, |
13326b4e | 4256 | mips_stack_argsize (gdbarch)); |
ebafbe83 MS |
4257 | } |
4258 | } | |
4259 | if (mips_debug) | |
4260 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4261 | } | |
4262 | ||
f10683bb | 4263 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4264 | |
ebafbe83 MS |
4265 | /* Return adjusted stack pointer. */ |
4266 | return sp; | |
4267 | } | |
4268 | ||
9c8fdbfa AC |
4269 | static enum return_value_convention |
4270 | mips_o64_return_value (struct gdbarch *gdbarch, | |
4271 | struct type *type, struct regcache *regcache, | |
4272 | void *readbuf, const void *writebuf) | |
6d82d43b | 4273 | { |
9c8fdbfa | 4274 | return RETURN_VALUE_STRUCT_CONVENTION; |
6d82d43b AC |
4275 | } |
4276 | ||
dd824b04 DJ |
4277 | /* Floating point register management. |
4278 | ||
4279 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4280 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4281 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4282 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4283 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4284 | double precision floats into two 32-bit chunks and store them in | |
4285 | consecutive fp regs. To display 64-bit floats stored in this | |
4286 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4287 | Throw in user-configurable endianness and you have a real mess. | |
4288 | ||
4289 | The way this works is: | |
4290 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4291 | double-precision value will be split across two logical registers. | |
4292 | The lower-numbered logical register will hold the low-order bits, | |
4293 | regardless of the processor's endianness. | |
4294 | - If we are on a 64-bit processor, and we are looking for a | |
4295 | single-precision value, it will be in the low ordered bits | |
4296 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4297 | save slot in memory. | |
4298 | - If we are in 64-bit mode, everything is straightforward. | |
4299 | ||
4300 | Note that this code only deals with "live" registers at the top of the | |
4301 | stack. We will attempt to deal with saved registers later, when | |
4302 | the raw/cooked register interface is in place. (We need a general | |
4303 | interface that can deal with dynamic saved register sizes -- fp | |
4304 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4305 | and below). */ | |
4306 | ||
67b2c998 DJ |
4307 | static struct type * |
4308 | mips_float_register_type (void) | |
4309 | { | |
361d1df0 | 4310 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
4311 | return builtin_type_ieee_single_big; |
4312 | else | |
4313 | return builtin_type_ieee_single_little; | |
4314 | } | |
4315 | ||
4316 | static struct type * | |
4317 | mips_double_register_type (void) | |
4318 | { | |
361d1df0 | 4319 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
4320 | return builtin_type_ieee_double_big; |
4321 | else | |
4322 | return builtin_type_ieee_double_little; | |
4323 | } | |
4324 | ||
dd824b04 DJ |
4325 | /* Copy a 32-bit single-precision value from the current frame |
4326 | into rare_buffer. */ | |
4327 | ||
4328 | static void | |
e11c53d2 AC |
4329 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
4330 | char *rare_buffer) | |
dd824b04 | 4331 | { |
719ec221 | 4332 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
4333 | char *raw_buffer = alloca (raw_size); |
4334 | ||
e11c53d2 | 4335 | if (!frame_register_read (frame, regno, raw_buffer)) |
dd824b04 DJ |
4336 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4337 | if (raw_size == 8) | |
4338 | { | |
4339 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4340 | 32 bits. */ |
dd824b04 DJ |
4341 | int offset; |
4342 | ||
4343 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4344 | offset = 4; | |
4345 | else | |
4346 | offset = 0; | |
4347 | ||
4348 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4349 | } | |
4350 | else | |
4351 | { | |
4352 | memcpy (rare_buffer, raw_buffer, 4); | |
4353 | } | |
4354 | } | |
4355 | ||
4356 | /* Copy a 64-bit double-precision value from the current frame into | |
4357 | rare_buffer. This may include getting half of it from the next | |
4358 | register. */ | |
4359 | ||
4360 | static void | |
e11c53d2 AC |
4361 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
4362 | char *rare_buffer) | |
dd824b04 | 4363 | { |
719ec221 | 4364 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
4365 | |
4366 | if (raw_size == 8 && !mips2_fp_compat ()) | |
4367 | { | |
4368 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4369 | all 64 bits. */ |
e11c53d2 | 4370 | if (!frame_register_read (frame, regno, rare_buffer)) |
dd824b04 DJ |
4371 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4372 | } | |
4373 | else | |
4374 | { | |
56cea623 | 4375 | if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) |
dd824b04 DJ |
4376 | internal_error (__FILE__, __LINE__, |
4377 | "mips_read_fp_register_double: bad access to " | |
4378 | "odd-numbered FP register"); | |
4379 | ||
4380 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4381 | each register. */ |
dd824b04 DJ |
4382 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
4383 | { | |
e11c53d2 AC |
4384 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4385 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4386 | } |
361d1df0 | 4387 | else |
dd824b04 | 4388 | { |
e11c53d2 AC |
4389 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4390 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4391 | } |
4392 | } | |
4393 | } | |
4394 | ||
c906108c | 4395 | static void |
e11c53d2 AC |
4396 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4397 | int regnum) | |
c5aa993b | 4398 | { /* do values for FP (float) regs */ |
dd824b04 | 4399 | char *raw_buffer; |
3903d437 AC |
4400 | double doub, flt1; /* doubles extracted from raw hex data */ |
4401 | int inv1, inv2; | |
c5aa993b | 4402 | |
6d82d43b AC |
4403 | raw_buffer = |
4404 | (char *) alloca (2 * | |
4405 | register_size (current_gdbarch, | |
4406 | mips_regnum (current_gdbarch)->fp0)); | |
c906108c | 4407 | |
e11c53d2 AC |
4408 | fprintf_filtered (file, "%s:", REGISTER_NAME (regnum)); |
4409 | fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), | |
4410 | ""); | |
f0ef6b29 | 4411 | |
719ec221 | 4412 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ()) |
c906108c | 4413 | { |
f0ef6b29 KB |
4414 | /* 4-byte registers: Print hex and floating. Also print even |
4415 | numbered registers as doubles. */ | |
e11c53d2 | 4416 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4417 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4418 | |
6d82d43b AC |
4419 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', |
4420 | file); | |
dd824b04 | 4421 | |
e11c53d2 | 4422 | fprintf_filtered (file, " flt: "); |
1adad886 | 4423 | if (inv1) |
e11c53d2 | 4424 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4425 | else |
e11c53d2 | 4426 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4427 | |
f0ef6b29 KB |
4428 | if (regnum % 2 == 0) |
4429 | { | |
e11c53d2 | 4430 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 | 4431 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
6d82d43b | 4432 | &inv2); |
1adad886 | 4433 | |
e11c53d2 | 4434 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4435 | if (inv2) |
e11c53d2 | 4436 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4437 | else |
e11c53d2 | 4438 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4439 | } |
c906108c SS |
4440 | } |
4441 | else | |
dd824b04 | 4442 | { |
f0ef6b29 | 4443 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4444 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4445 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4446 | |
e11c53d2 | 4447 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4448 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4449 | ||
361d1df0 | 4450 | |
6d82d43b AC |
4451 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', |
4452 | file); | |
f0ef6b29 | 4453 | |
e11c53d2 | 4454 | fprintf_filtered (file, " flt: "); |
1adad886 | 4455 | if (inv1) |
e11c53d2 | 4456 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4457 | else |
e11c53d2 | 4458 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4459 | |
e11c53d2 | 4460 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4461 | if (inv2) |
e11c53d2 | 4462 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4463 | else |
e11c53d2 | 4464 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4465 | } |
4466 | } | |
4467 | ||
4468 | static void | |
e11c53d2 AC |
4469 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
4470 | int regnum, int all) | |
f0ef6b29 | 4471 | { |
a4b8ebc8 | 4472 | struct gdbarch *gdbarch = get_frame_arch (frame); |
d9d9c31f | 4473 | char raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4474 | int offset; |
1adad886 | 4475 | |
a4b8ebc8 | 4476 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4477 | { |
e11c53d2 | 4478 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4479 | return; |
4480 | } | |
4481 | ||
4482 | /* Get the data in raw format. */ | |
e11c53d2 | 4483 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4484 | { |
e11c53d2 | 4485 | fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum)); |
f0ef6b29 | 4486 | return; |
c906108c | 4487 | } |
f0ef6b29 | 4488 | |
e11c53d2 | 4489 | fputs_filtered (REGISTER_NAME (regnum), file); |
f0ef6b29 KB |
4490 | |
4491 | /* The problem with printing numeric register names (r26, etc.) is that | |
4492 | the user can't use them on input. Probably the best solution is to | |
4493 | fix it so that either the numeric or the funky (a2, etc.) names | |
4494 | are accepted on input. */ | |
4495 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4496 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4497 | else |
e11c53d2 | 4498 | fprintf_filtered (file, ": "); |
f0ef6b29 KB |
4499 | |
4500 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
6d82d43b AC |
4501 | offset = |
4502 | register_size (current_gdbarch, | |
4503 | regnum) - register_size (current_gdbarch, regnum); | |
f0ef6b29 KB |
4504 | else |
4505 | offset = 0; | |
4506 | ||
6d82d43b AC |
4507 | print_scalar_formatted (raw_buffer + offset, |
4508 | gdbarch_register_type (gdbarch, regnum), 'x', 0, | |
4509 | file); | |
c906108c SS |
4510 | } |
4511 | ||
f0ef6b29 KB |
4512 | /* Replacement for generic do_registers_info. |
4513 | Print regs in pretty columns. */ | |
4514 | ||
4515 | static int | |
e11c53d2 AC |
4516 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4517 | int regnum) | |
f0ef6b29 | 4518 | { |
e11c53d2 AC |
4519 | fprintf_filtered (file, " "); |
4520 | mips_print_fp_register (file, frame, regnum); | |
4521 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4522 | return regnum + 1; |
4523 | } | |
4524 | ||
4525 | ||
c906108c SS |
4526 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4527 | ||
4528 | static int | |
e11c53d2 | 4529 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4530 | int start_regnum) |
c906108c | 4531 | { |
a4b8ebc8 | 4532 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4533 | /* do values for GP (int) regs */ |
d9d9c31f | 4534 | char raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 4535 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4536 | int col, byte; |
a4b8ebc8 | 4537 | int regnum; |
c906108c SS |
4538 | |
4539 | /* For GP registers, we print a separate row of names above the vals */ | |
e11c53d2 | 4540 | fprintf_filtered (file, " "); |
a4b8ebc8 | 4541 | for (col = 0, regnum = start_regnum; |
6d82d43b | 4542 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
4543 | { |
4544 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4545 | continue; /* unused register */ |
6d82d43b AC |
4546 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4547 | TYPE_CODE_FLT) | |
c5aa993b | 4548 | break; /* end the row: reached FP register */ |
6d82d43b | 4549 | fprintf_filtered (file, |
d5ac5a39 | 4550 | mips_abi_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", |
e11c53d2 | 4551 | REGISTER_NAME (regnum)); |
c906108c SS |
4552 | col++; |
4553 | } | |
a4b8ebc8 | 4554 | /* print the R0 to R31 names */ |
20e6603c AC |
4555 | if ((start_regnum % NUM_REGS) < MIPS_NUMREGS) |
4556 | fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS); | |
4557 | else | |
4558 | fprintf_filtered (file, "\n "); | |
c906108c | 4559 | |
c906108c | 4560 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4561 | for (col = 0, regnum = start_regnum; |
6d82d43b | 4562 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
4563 | { |
4564 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4565 | continue; /* unused register */ |
6d82d43b AC |
4566 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4567 | TYPE_CODE_FLT) | |
c5aa993b | 4568 | break; /* end row: reached FP register */ |
c906108c | 4569 | /* OK: get the data in raw format. */ |
e11c53d2 | 4570 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c906108c SS |
4571 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
4572 | /* pad small registers */ | |
4246e332 | 4573 | for (byte = 0; |
d5ac5a39 | 4574 | byte < (mips_abi_regsize (current_gdbarch) |
6d82d43b | 4575 | - register_size (current_gdbarch, regnum)); byte++) |
c906108c SS |
4576 | printf_filtered (" "); |
4577 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 4578 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
6d82d43b AC |
4579 | for (byte = |
4580 | register_size (current_gdbarch, | |
4581 | regnum) - register_size (current_gdbarch, regnum); | |
4582 | byte < register_size (current_gdbarch, regnum); byte++) | |
e11c53d2 | 4583 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
c906108c | 4584 | else |
c73e8f27 | 4585 | for (byte = register_size (current_gdbarch, regnum) - 1; |
6d82d43b | 4586 | byte >= 0; byte--) |
e11c53d2 AC |
4587 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
4588 | fprintf_filtered (file, " "); | |
c906108c SS |
4589 | col++; |
4590 | } | |
c5aa993b | 4591 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4592 | fprintf_filtered (file, "\n"); |
c906108c SS |
4593 | |
4594 | return regnum; | |
4595 | } | |
4596 | ||
4597 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4598 | ||
bf1f5b4c | 4599 | static void |
e11c53d2 AC |
4600 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4601 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4602 | { |
c5aa993b | 4603 | if (regnum != -1) /* do one specified register */ |
c906108c | 4604 | { |
a4b8ebc8 | 4605 | gdb_assert (regnum >= NUM_REGS); |
c906108c SS |
4606 | if (*(REGISTER_NAME (regnum)) == '\0') |
4607 | error ("Not a valid register for the current processor type"); | |
4608 | ||
e11c53d2 AC |
4609 | mips_print_register (file, frame, regnum, 0); |
4610 | fprintf_filtered (file, "\n"); | |
c906108c | 4611 | } |
c5aa993b JM |
4612 | else |
4613 | /* do all (or most) registers */ | |
c906108c | 4614 | { |
a4b8ebc8 AC |
4615 | regnum = NUM_REGS; |
4616 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
c906108c | 4617 | { |
6d82d43b AC |
4618 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4619 | TYPE_CODE_FLT) | |
e11c53d2 AC |
4620 | { |
4621 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4622 | regnum = print_fp_register_row (file, frame, regnum); | |
4623 | else | |
4624 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4625 | } | |
c906108c | 4626 | else |
e11c53d2 | 4627 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4628 | } |
4629 | } | |
4630 | } | |
4631 | ||
c906108c SS |
4632 | /* Is this a branch with a delay slot? */ |
4633 | ||
c906108c | 4634 | static int |
acdb74a0 | 4635 | is_delayed (unsigned long insn) |
c906108c SS |
4636 | { |
4637 | int i; | |
4638 | for (i = 0; i < NUMOPCODES; ++i) | |
4639 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4640 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4641 | break; | |
4642 | return (i < NUMOPCODES | |
4643 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4644 | | INSN_COND_BRANCH_DELAY | |
4645 | | INSN_COND_BRANCH_LIKELY))); | |
4646 | } | |
4647 | ||
4648 | int | |
acdb74a0 | 4649 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c | 4650 | { |
4c7d22cb | 4651 | char buf[MIPS32_INSN_SIZE]; |
c906108c SS |
4652 | |
4653 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4654 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4655 | return 0; |
4656 | ||
4c7d22cb | 4657 | if (target_read_memory (pc, buf, sizeof buf) != 0) |
c906108c SS |
4658 | /* If error reading memory, guess that it is not a delayed branch. */ |
4659 | return 0; | |
4c7d22cb | 4660 | return is_delayed (extract_unsigned_integer (buf, sizeof buf)); |
c906108c SS |
4661 | } |
4662 | ||
6d82d43b AC |
4663 | /* To skip prologues, I use this predicate. Returns either PC itself |
4664 | if the code at PC does not look like a function prologue; otherwise | |
4665 | returns an address that (if we're lucky) follows the prologue. If | |
4666 | LENIENT, then we must skip everything which is involved in setting | |
4667 | up the frame (it's OK to skip more, just so long as we don't skip | |
4668 | anything which might clobber the registers which are being saved. | |
4669 | We must skip more in the case where part of the prologue is in the | |
4670 | delay slot of a non-prologue instruction). */ | |
4671 | ||
4672 | static CORE_ADDR | |
4673 | mips_skip_prologue (CORE_ADDR pc) | |
4674 | { | |
8b622e6a AC |
4675 | CORE_ADDR limit_pc; |
4676 | CORE_ADDR func_addr; | |
4677 | ||
6d82d43b AC |
4678 | /* See if we can determine the end of the prologue via the symbol table. |
4679 | If so, then return either PC, or the PC after the prologue, whichever | |
4680 | is greater. */ | |
8b622e6a AC |
4681 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4682 | { | |
4683 | CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr); | |
4684 | if (post_prologue_pc != 0) | |
4685 | return max (pc, post_prologue_pc); | |
4686 | } | |
6d82d43b AC |
4687 | |
4688 | /* Can't determine prologue from the symbol table, need to examine | |
4689 | instructions. */ | |
4690 | ||
98b4dd94 JB |
4691 | /* Find an upper limit on the function prologue using the debug |
4692 | information. If the debug information could not be used to provide | |
4693 | that bound, then use an arbitrary large number as the upper bound. */ | |
4694 | limit_pc = skip_prologue_using_sal (pc); | |
4695 | if (limit_pc == 0) | |
4696 | limit_pc = pc + 100; /* Magic. */ | |
4697 | ||
0fe7e7c8 | 4698 | if (mips_pc_is_mips16 (pc)) |
a65bbe44 | 4699 | return mips16_scan_prologue (pc, limit_pc, NULL, NULL); |
6d82d43b | 4700 | else |
a65bbe44 | 4701 | return mips32_scan_prologue (pc, limit_pc, NULL, NULL); |
88658117 AC |
4702 | } |
4703 | ||
a5ea2558 AC |
4704 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4705 | used for all MIPS-specific commands. */ | |
4706 | ||
a5ea2558 | 4707 | static void |
acdb74a0 | 4708 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4709 | { |
4710 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4711 | } | |
4712 | ||
a5ea2558 | 4713 | static void |
acdb74a0 | 4714 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 4715 | { |
6d82d43b AC |
4716 | printf_unfiltered |
4717 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
4718 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
4719 | } | |
4720 | ||
c906108c SS |
4721 | /* Commands to show/set the MIPS FPU type. */ |
4722 | ||
c906108c | 4723 | static void |
acdb74a0 | 4724 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4725 | { |
c906108c SS |
4726 | char *fpu; |
4727 | switch (MIPS_FPU_TYPE) | |
4728 | { | |
4729 | case MIPS_FPU_SINGLE: | |
4730 | fpu = "single-precision"; | |
4731 | break; | |
4732 | case MIPS_FPU_DOUBLE: | |
4733 | fpu = "double-precision"; | |
4734 | break; | |
4735 | case MIPS_FPU_NONE: | |
4736 | fpu = "absent (none)"; | |
4737 | break; | |
93d56215 AC |
4738 | default: |
4739 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
4740 | } |
4741 | if (mips_fpu_type_auto) | |
6d82d43b AC |
4742 | printf_unfiltered |
4743 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4744 | fpu); | |
c906108c | 4745 | else |
6d82d43b AC |
4746 | printf_unfiltered |
4747 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
4748 | } |
4749 | ||
4750 | ||
c906108c | 4751 | static void |
acdb74a0 | 4752 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 4753 | { |
6d82d43b AC |
4754 | printf_unfiltered |
4755 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
4756 | show_mipsfpu_command (args, from_tty); |
4757 | } | |
4758 | ||
c906108c | 4759 | static void |
acdb74a0 | 4760 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 4761 | { |
8d5838b5 AC |
4762 | struct gdbarch_info info; |
4763 | gdbarch_info_init (&info); | |
c906108c SS |
4764 | mips_fpu_type = MIPS_FPU_SINGLE; |
4765 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4766 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4767 | instead of relying on globals. Doing that would let generic code | |
4768 | handle the search for this specific architecture. */ | |
4769 | if (!gdbarch_update_p (info)) | |
4770 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
4771 | } |
4772 | ||
c906108c | 4773 | static void |
acdb74a0 | 4774 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 4775 | { |
8d5838b5 AC |
4776 | struct gdbarch_info info; |
4777 | gdbarch_info_init (&info); | |
c906108c SS |
4778 | mips_fpu_type = MIPS_FPU_DOUBLE; |
4779 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4780 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4781 | instead of relying on globals. Doing that would let generic code | |
4782 | handle the search for this specific architecture. */ | |
4783 | if (!gdbarch_update_p (info)) | |
4784 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
4785 | } |
4786 | ||
c906108c | 4787 | static void |
acdb74a0 | 4788 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 4789 | { |
8d5838b5 AC |
4790 | struct gdbarch_info info; |
4791 | gdbarch_info_init (&info); | |
c906108c SS |
4792 | mips_fpu_type = MIPS_FPU_NONE; |
4793 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4794 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4795 | instead of relying on globals. Doing that would let generic code | |
4796 | handle the search for this specific architecture. */ | |
4797 | if (!gdbarch_update_p (info)) | |
4798 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
4799 | } |
4800 | ||
c906108c | 4801 | static void |
acdb74a0 | 4802 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
4803 | { |
4804 | mips_fpu_type_auto = 1; | |
4805 | } | |
4806 | ||
c906108c | 4807 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
4808 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
4809 | the relevant processor still exists (it dates back to '94) and | |
4810 | secondly this is not the way to do this. The processor type should | |
4811 | be set by forcing an architecture change. */ | |
c906108c | 4812 | |
691c0433 AC |
4813 | void |
4814 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 4815 | { |
691c0433 | 4816 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
4817 | CORE_ADDR prid; |
4818 | ||
4819 | prid = read_register (PRID_REGNUM); | |
4820 | ||
4821 | if ((prid & ~0xf) == 0x700) | |
691c0433 | 4822 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
4823 | } |
4824 | ||
4825 | /* Just like reinit_frame_cache, but with the right arguments to be | |
4826 | callable as an sfunc. */ | |
4827 | ||
4828 | static void | |
acdb74a0 AC |
4829 | reinit_frame_cache_sfunc (char *args, int from_tty, |
4830 | struct cmd_list_element *c) | |
c906108c SS |
4831 | { |
4832 | reinit_frame_cache (); | |
4833 | } | |
4834 | ||
a89aa300 AC |
4835 | static int |
4836 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 4837 | { |
e5ab0dce | 4838 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 4839 | |
d31431ed AC |
4840 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
4841 | disassembler needs to be able to locally determine the ISA, and | |
4842 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
4843 | work. */ | |
ec4045ea AC |
4844 | if (mips_pc_is_mips16 (memaddr)) |
4845 | info->mach = bfd_mach_mips16; | |
c906108c SS |
4846 | |
4847 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 4848 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 4849 | |
e5ab0dce | 4850 | /* Set the disassembler options. */ |
6d82d43b | 4851 | if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64) |
e5ab0dce AC |
4852 | { |
4853 | /* Set up the disassembler info, so that we get the right | |
6d82d43b | 4854 | register names from libopcodes. */ |
e5ab0dce AC |
4855 | if (tdep->mips_abi == MIPS_ABI_N32) |
4856 | info->disassembler_options = "gpr-names=n32"; | |
4857 | else | |
4858 | info->disassembler_options = "gpr-names=64"; | |
4859 | info->flavour = bfd_target_elf_flavour; | |
4860 | } | |
4861 | else | |
4862 | /* This string is not recognized explicitly by the disassembler, | |
4863 | but it tells the disassembler to not try to guess the ABI from | |
4864 | the bfd elf headers, such that, if the user overrides the ABI | |
4865 | of a program linked as NewABI, the disassembly will follow the | |
4866 | register naming conventions specified by the user. */ | |
4867 | info->disassembler_options = "gpr-names=32"; | |
4868 | ||
c906108c | 4869 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 4870 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
4871 | return print_insn_big_mips (memaddr, info); |
4872 | else | |
4873 | return print_insn_little_mips (memaddr, info); | |
4874 | } | |
4875 | ||
c906108c SS |
4876 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
4877 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
4878 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
4879 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
4880 | (if necessary) to point to the actual memory location where the | |
4881 | breakpoint should be inserted. */ | |
4882 | ||
f7ab6ec6 | 4883 | static const unsigned char * |
6d82d43b | 4884 | mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 4885 | { |
d7449b42 | 4886 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c | 4887 | { |
0fe7e7c8 | 4888 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4889 | { |
6d82d43b | 4890 | static unsigned char mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 4891 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4892 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
4893 | return mips16_big_breakpoint; |
4894 | } | |
4895 | else | |
4896 | { | |
aaab4dba AC |
4897 | /* The IDT board uses an unusual breakpoint value, and |
4898 | sometimes gets confused when it sees the usual MIPS | |
4899 | breakpoint instruction. */ | |
6d82d43b AC |
4900 | static unsigned char big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
4901 | static unsigned char pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
4902 | static unsigned char idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 4903 | |
c5aa993b | 4904 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
4905 | |
4906 | if (strcmp (target_shortname, "mips") == 0) | |
4907 | return idt_big_breakpoint; | |
4908 | else if (strcmp (target_shortname, "ddb") == 0 | |
4909 | || strcmp (target_shortname, "pmon") == 0 | |
4910 | || strcmp (target_shortname, "lsi") == 0) | |
4911 | return pmon_big_breakpoint; | |
4912 | else | |
4913 | return big_breakpoint; | |
4914 | } | |
4915 | } | |
4916 | else | |
4917 | { | |
0fe7e7c8 | 4918 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4919 | { |
6d82d43b | 4920 | static unsigned char mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 4921 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4922 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
4923 | return mips16_little_breakpoint; |
4924 | } | |
4925 | else | |
4926 | { | |
6d82d43b AC |
4927 | static unsigned char little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
4928 | static unsigned char pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
4929 | static unsigned char idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 4930 | |
c5aa993b | 4931 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
4932 | |
4933 | if (strcmp (target_shortname, "mips") == 0) | |
4934 | return idt_little_breakpoint; | |
4935 | else if (strcmp (target_shortname, "ddb") == 0 | |
4936 | || strcmp (target_shortname, "pmon") == 0 | |
4937 | || strcmp (target_shortname, "lsi") == 0) | |
4938 | return pmon_little_breakpoint; | |
4939 | else | |
4940 | return little_breakpoint; | |
4941 | } | |
4942 | } | |
4943 | } | |
4944 | ||
4945 | /* If PC is in a mips16 call or return stub, return the address of the target | |
4946 | PC, which is either the callee or the caller. There are several | |
4947 | cases which must be handled: | |
4948 | ||
4949 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 4950 | target PC is in $31 ($ra). |
c906108c | 4951 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 4952 | and the target PC is in $2. |
c906108c | 4953 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
4954 | before the jal instruction, this is effectively a call stub |
4955 | and the the target PC is in $2. Otherwise this is effectively | |
4956 | a return stub and the target PC is in $18. | |
c906108c SS |
4957 | |
4958 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 4959 | gory details. */ |
c906108c | 4960 | |
757a7cc6 | 4961 | static CORE_ADDR |
e7d6a6d2 | 4962 | mips_skip_trampoline_code (CORE_ADDR pc) |
c906108c SS |
4963 | { |
4964 | char *name; | |
4965 | CORE_ADDR start_addr; | |
4966 | ||
4967 | /* Find the starting address and name of the function containing the PC. */ | |
4968 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
4969 | return 0; | |
4970 | ||
4971 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
4972 | target PC is in $31 ($ra). */ | |
4973 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
4974 | || strcmp (name, "__mips16_ret_df") == 0) | |
4c7d22cb | 4975 | return read_signed_register (MIPS_RA_REGNUM); |
c906108c SS |
4976 | |
4977 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
4978 | { | |
4979 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
4980 | and the target PC is in $2. */ | |
4981 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 4982 | return read_signed_register (2); |
c906108c SS |
4983 | |
4984 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
4985 | before the jal instruction, this is effectively a call stub |
4986 | and the the target PC is in $2. Otherwise this is effectively | |
4987 | a return stub and the target PC is in $18. */ | |
c906108c SS |
4988 | else if (name[19] == 's' || name[19] == 'd') |
4989 | { | |
4990 | if (pc == start_addr) | |
4991 | { | |
4992 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
4993 | stub. Such a stub for a function bar might have a name |
4994 | like __fn_stub_bar, and might look like this: | |
4995 | mfc1 $4,$f13 | |
4996 | mfc1 $5,$f12 | |
4997 | mfc1 $6,$f15 | |
4998 | mfc1 $7,$f14 | |
4999 | la $1,bar (becomes a lui/addiu pair) | |
5000 | jr $1 | |
5001 | So scan down to the lui/addi and extract the target | |
5002 | address from those two instructions. */ | |
c906108c | 5003 | |
6c997a34 | 5004 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
5005 | t_inst inst; |
5006 | int i; | |
5007 | ||
5008 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
5009 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
5010 | 0) | |
c906108c SS |
5011 | return target_pc; |
5012 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5013 | && strcmp (name, "etext") != 0 | |
5014 | && strcmp (name, "_etext") != 0) | |
5015 | return target_pc; | |
5016 | ||
5017 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5018 | The limit on the search is arbitrarily set to 20 |
5019 | instructions. FIXME. */ | |
4c7d22cb | 5020 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS32_INSN_SIZE) |
c906108c | 5021 | { |
c5aa993b JM |
5022 | inst = mips_fetch_instruction (target_pc); |
5023 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5024 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5025 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5026 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5027 | } |
5028 | ||
5029 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5030 | return target_pc; | |
5031 | } | |
5032 | else | |
5033 | /* This is the 'return' part of a call stub. The return | |
5034 | address is in $r18. */ | |
6c997a34 | 5035 | return read_signed_register (18); |
c906108c SS |
5036 | } |
5037 | } | |
c5aa993b | 5038 | return 0; /* not a stub */ |
c906108c SS |
5039 | } |
5040 | ||
5041 | ||
5042 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
5043 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
5044 | ||
757a7cc6 | 5045 | static int |
acdb74a0 | 5046 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5047 | { |
5048 | CORE_ADDR start_addr; | |
5049 | ||
5050 | /* Find the starting address of the function containing the PC. If the | |
5051 | caller didn't give us a name, look it up at the same time. */ | |
6d82d43b AC |
5052 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == |
5053 | 0) | |
c906108c SS |
5054 | return 0; |
5055 | ||
5056 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5057 | { | |
5058 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
5059 | if (name[19] >= '0' && name[19] <= '9') | |
5060 | return 1; | |
5061 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5062 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
5063 | else if (name[19] == 's' || name[19] == 'd') |
5064 | return pc == start_addr; | |
5065 | } | |
5066 | ||
c5aa993b | 5067 | return 0; /* not a stub */ |
c906108c SS |
5068 | } |
5069 | ||
5070 | ||
c5115f39 AC |
5071 | /* Return non-zero if the PC is inside a return thunk (aka stub or |
5072 | trampoline). */ | |
c906108c | 5073 | |
e41b17f0 | 5074 | static int |
c5115f39 | 5075 | mips_in_solib_return_trampoline (CORE_ADDR pc, char *name) |
c906108c SS |
5076 | { |
5077 | CORE_ADDR start_addr; | |
5078 | ||
5079 | /* Find the starting address of the function containing the PC. */ | |
5080 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
5081 | return 0; | |
5082 | ||
5083 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
5084 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5085 | || strcmp (name, "__mips16_ret_df") == 0) | |
5086 | return 1; | |
5087 | ||
5088 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 5089 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c | 5090 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
6d82d43b | 5091 | && (name[19] == 's' || name[19] == 'd') && pc != start_addr) |
c906108c SS |
5092 | return 1; |
5093 | ||
c5aa993b | 5094 | return 0; /* not a stub */ |
c906108c SS |
5095 | } |
5096 | ||
5097 | ||
a53c66de AC |
5098 | /* Return non-zero if the PC is in a library helper function that |
5099 | should be ignored. This implements the | |
5100 | DEPRECATED_IGNORE_HELPER_CALL macro. */ | |
c906108c SS |
5101 | |
5102 | int | |
acdb74a0 | 5103 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
5104 | { |
5105 | char *name; | |
5106 | ||
5107 | /* Find the starting address and name of the function containing the PC. */ | |
5108 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
5109 | return 0; | |
5110 | ||
5111 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
5112 | that we want to ignore. */ | |
5113 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
5114 | || strcmp (name, "__mips16_ret_df") == 0); | |
5115 | } | |
5116 | ||
5117 | ||
a4b8ebc8 AC |
5118 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
5119 | [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5120 | |
5121 | static int | |
5122 | mips_stab_reg_to_regnum (int num) | |
5123 | { | |
a4b8ebc8 | 5124 | int regnum; |
2f38ef89 | 5125 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5126 | regnum = num; |
2f38ef89 | 5127 | else if (num >= 38 && num < 70) |
56cea623 | 5128 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 5129 | else if (num == 70) |
56cea623 | 5130 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5131 | else if (num == 71) |
56cea623 | 5132 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5133 | else |
a4b8ebc8 AC |
5134 | /* This will hopefully (eventually) provoke a warning. Should |
5135 | we be calling complaint() here? */ | |
5136 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5137 | return NUM_REGS + regnum; | |
88c72b7d AC |
5138 | } |
5139 | ||
2f38ef89 | 5140 | |
a4b8ebc8 AC |
5141 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
5142 | NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5143 | |
5144 | static int | |
2f38ef89 | 5145 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 5146 | { |
a4b8ebc8 | 5147 | int regnum; |
2f38ef89 | 5148 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5149 | regnum = num; |
2f38ef89 | 5150 | else if (num >= 32 && num < 64) |
56cea623 | 5151 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 5152 | else if (num == 64) |
56cea623 | 5153 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5154 | else if (num == 65) |
56cea623 | 5155 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5156 | else |
a4b8ebc8 AC |
5157 | /* This will hopefully (eventually) provoke a warning. Should we |
5158 | be calling complaint() here? */ | |
5159 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5160 | return NUM_REGS + regnum; | |
5161 | } | |
5162 | ||
5163 | static int | |
5164 | mips_register_sim_regno (int regnum) | |
5165 | { | |
5166 | /* Only makes sense to supply raw registers. */ | |
5167 | gdb_assert (regnum >= 0 && regnum < NUM_REGS); | |
5168 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to | |
5169 | decide if it is valid. Should instead define a standard sim/gdb | |
5170 | register numbering scheme. */ | |
5171 | if (REGISTER_NAME (NUM_REGS + regnum) != NULL | |
5172 | && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0') | |
5173 | return regnum; | |
5174 | else | |
6d82d43b | 5175 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
5176 | } |
5177 | ||
2f38ef89 | 5178 | |
fc0c74b1 AC |
5179 | /* Convert an integer into an address. By first converting the value |
5180 | into a pointer and then extracting it signed, the address is | |
5181 | guarenteed to be correctly sign extended. */ | |
5182 | ||
5183 | static CORE_ADDR | |
5184 | mips_integer_to_address (struct type *type, void *buf) | |
5185 | { | |
5186 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5187 | LONGEST val = unpack_long (type, buf); | |
5188 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
5189 | return extract_signed_integer (tmp, | |
5190 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5191 | } | |
5192 | ||
caaa3122 DJ |
5193 | static void |
5194 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5195 | { | |
5196 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5197 | const char *name = bfd_get_section_name (abfd, sect); | |
5198 | ||
5199 | if (*abip != MIPS_ABI_UNKNOWN) | |
5200 | return; | |
5201 | ||
5202 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5203 | return; | |
5204 | ||
5205 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5206 | *abip = MIPS_ABI_O32; | |
5207 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5208 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5209 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5210 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5211 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5212 | *abip = MIPS_ABI_O64; | |
5213 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5214 | *abip = MIPS_ABI_EABI32; | |
5215 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5216 | *abip = MIPS_ABI_EABI64; | |
5217 | else | |
5218 | warning ("unsupported ABI %s.", name + 8); | |
5219 | } | |
5220 | ||
2e4ebe70 DJ |
5221 | static enum mips_abi |
5222 | global_mips_abi (void) | |
5223 | { | |
5224 | int i; | |
5225 | ||
5226 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5227 | if (mips_abi_strings[i] == mips_abi_string) | |
5228 | return (enum mips_abi) i; | |
5229 | ||
6d82d43b | 5230 | internal_error (__FILE__, __LINE__, "unknown ABI string"); |
2e4ebe70 DJ |
5231 | } |
5232 | ||
c2d11a7d | 5233 | static struct gdbarch * |
6d82d43b | 5234 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5235 | { |
c2d11a7d JM |
5236 | struct gdbarch *gdbarch; |
5237 | struct gdbarch_tdep *tdep; | |
5238 | int elf_flags; | |
2e4ebe70 | 5239 | enum mips_abi mips_abi, found_abi, wanted_abi; |
a4b8ebc8 | 5240 | int num_regs; |
8d5838b5 | 5241 | enum mips_fpu_type fpu_type; |
c2d11a7d | 5242 | |
ec03c1ac AC |
5243 | /* First of all, extract the elf_flags, if available. */ |
5244 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5245 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5246 | else if (arches != NULL) |
5247 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5248 | else |
5249 | elf_flags = 0; | |
5250 | if (gdbarch_debug) | |
5251 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5252 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5253 | |
102182a9 | 5254 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5255 | switch ((elf_flags & EF_MIPS_ABI)) |
5256 | { | |
5257 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5258 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5259 | break; |
5260 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5261 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5262 | break; |
5263 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5264 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5265 | break; |
5266 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5267 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5268 | break; |
5269 | default: | |
acdb74a0 | 5270 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5271 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5272 | else |
ec03c1ac | 5273 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5274 | break; |
5275 | } | |
acdb74a0 | 5276 | |
caaa3122 | 5277 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5278 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5279 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5280 | |
dc305454 | 5281 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
5282 | MIPS architecture (if there is one). */ |
5283 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5284 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5285 | |
32a6503c | 5286 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5287 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5288 | && info.bfd_arch_info != NULL |
5289 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5290 | { | |
5291 | switch (info.bfd_arch_info->mach) | |
5292 | { | |
5293 | case bfd_mach_mips3900: | |
ec03c1ac | 5294 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5295 | break; |
5296 | case bfd_mach_mips4100: | |
5297 | case bfd_mach_mips5000: | |
ec03c1ac | 5298 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5299 | break; |
1d06468c EZ |
5300 | case bfd_mach_mips8000: |
5301 | case bfd_mach_mips10000: | |
32a6503c KB |
5302 | /* On Irix, ELF64 executables use the N64 ABI. The |
5303 | pseudo-sections which describe the ABI aren't present | |
5304 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5305 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5306 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5307 | found_abi = MIPS_ABI_N64; |
28d169de | 5308 | else |
ec03c1ac | 5309 | found_abi = MIPS_ABI_N32; |
1d06468c | 5310 | break; |
bf64bfd6 AC |
5311 | } |
5312 | } | |
2e4ebe70 | 5313 | |
ec03c1ac AC |
5314 | if (gdbarch_debug) |
5315 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5316 | found_abi); | |
5317 | ||
5318 | /* What has the user specified from the command line? */ | |
5319 | wanted_abi = global_mips_abi (); | |
5320 | if (gdbarch_debug) | |
5321 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5322 | wanted_abi); | |
2e4ebe70 DJ |
5323 | |
5324 | /* Now that we have found what the ABI for this binary would be, | |
5325 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5326 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5327 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5328 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5329 | mips_abi = found_abi; | |
5330 | else | |
5331 | mips_abi = MIPS_ABI_O32; | |
5332 | if (gdbarch_debug) | |
5333 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5334 | mips_abi); | |
2e4ebe70 | 5335 | |
ec03c1ac | 5336 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5337 | if (gdbarch_debug) |
ec03c1ac AC |
5338 | fprintf_unfiltered (gdb_stdlog, |
5339 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
5340 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 5341 | |
8d5838b5 AC |
5342 | /* Determine the MIPS FPU type. */ |
5343 | if (!mips_fpu_type_auto) | |
5344 | fpu_type = mips_fpu_type; | |
5345 | else if (info.bfd_arch_info != NULL | |
5346 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5347 | switch (info.bfd_arch_info->mach) | |
5348 | { | |
5349 | case bfd_mach_mips3900: | |
5350 | case bfd_mach_mips4100: | |
5351 | case bfd_mach_mips4111: | |
a9d61c86 | 5352 | case bfd_mach_mips4120: |
8d5838b5 AC |
5353 | fpu_type = MIPS_FPU_NONE; |
5354 | break; | |
5355 | case bfd_mach_mips4650: | |
5356 | fpu_type = MIPS_FPU_SINGLE; | |
5357 | break; | |
5358 | default: | |
5359 | fpu_type = MIPS_FPU_DOUBLE; | |
5360 | break; | |
5361 | } | |
5362 | else if (arches != NULL) | |
5363 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5364 | else | |
5365 | fpu_type = MIPS_FPU_DOUBLE; | |
5366 | if (gdbarch_debug) | |
5367 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5368 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5369 | |
c2d11a7d JM |
5370 | /* try to find a pre-existing architecture */ |
5371 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5372 | arches != NULL; | |
5373 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5374 | { | |
5375 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5376 | using. */ |
9103eae0 | 5377 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5378 | continue; |
9103eae0 | 5379 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5380 | continue; |
719ec221 AC |
5381 | /* Need to be pedantic about which register virtual size is |
5382 | used. */ | |
5383 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5384 | != mips64_transfers_32bit_regs_p) | |
5385 | continue; | |
8d5838b5 AC |
5386 | /* Be pedantic about which FPU is selected. */ |
5387 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5388 | continue; | |
4be87837 | 5389 | return arches->gdbarch; |
c2d11a7d JM |
5390 | } |
5391 | ||
102182a9 | 5392 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5393 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5394 | gdbarch = gdbarch_alloc (&info, tdep); | |
5395 | tdep->elf_flags = elf_flags; | |
719ec221 | 5396 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5397 | tdep->found_abi = found_abi; |
5398 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5399 | tdep->mips_fpu_type = fpu_type; |
c2d11a7d | 5400 | |
102182a9 | 5401 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5402 | set_gdbarch_short_bit (gdbarch, 16); |
5403 | set_gdbarch_int_bit (gdbarch, 32); | |
5404 | set_gdbarch_float_bit (gdbarch, 32); | |
5405 | set_gdbarch_double_bit (gdbarch, 64); | |
5406 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5407 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5408 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5409 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5410 | |
6d82d43b | 5411 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
5412 | mips_elf_make_msymbol_special); |
5413 | ||
16e109ca | 5414 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5415 | { |
16e109ca | 5416 | const char **reg_names; |
56cea623 AC |
5417 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5418 | struct mips_regnum); | |
56cea623 AC |
5419 | if (info.osabi == GDB_OSABI_IRIX) |
5420 | { | |
5421 | regnum->fp0 = 32; | |
5422 | regnum->pc = 64; | |
5423 | regnum->cause = 65; | |
5424 | regnum->badvaddr = 66; | |
5425 | regnum->hi = 67; | |
5426 | regnum->lo = 68; | |
5427 | regnum->fp_control_status = 69; | |
5428 | regnum->fp_implementation_revision = 70; | |
5429 | num_regs = 71; | |
16e109ca | 5430 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5431 | } |
5432 | else | |
5433 | { | |
5434 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5435 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5436 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5437 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5438 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5439 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5440 | regnum->fp_control_status = 70; | |
5441 | regnum->fp_implementation_revision = 71; | |
5442 | num_regs = 90; | |
16e109ca AC |
5443 | if (info.bfd_arch_info != NULL |
5444 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5445 | reg_names = mips_tx39_reg_names; | |
5446 | else | |
5447 | reg_names = mips_generic_reg_names; | |
56cea623 AC |
5448 | } |
5449 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been | |
5450 | replaced by read_pc? */ | |
f10683bb MH |
5451 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
5452 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
5453 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
5454 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5455 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca AC |
5456 | set_gdbarch_register_name (gdbarch, mips_register_name); |
5457 | tdep->mips_processor_reg_names = reg_names; | |
5458 | tdep->regnum = regnum; | |
56cea623 | 5459 | } |
fe29b929 | 5460 | |
0dadbba0 | 5461 | switch (mips_abi) |
c2d11a7d | 5462 | { |
0dadbba0 | 5463 | case MIPS_ABI_O32: |
25ab4790 | 5464 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5465 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 5466 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5467 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5468 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5469 | set_gdbarch_long_bit (gdbarch, 32); |
5470 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5471 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5472 | break; | |
0dadbba0 | 5473 | case MIPS_ABI_O64: |
25ab4790 | 5474 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 5475 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 5476 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5477 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5478 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5479 | set_gdbarch_long_bit (gdbarch, 32); |
5480 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5481 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5482 | break; | |
0dadbba0 | 5483 | case MIPS_ABI_EABI32: |
25ab4790 | 5484 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5485 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5486 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5487 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5488 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5489 | set_gdbarch_long_bit (gdbarch, 32); |
5490 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5491 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5492 | break; | |
0dadbba0 | 5493 | case MIPS_ABI_EABI64: |
25ab4790 | 5494 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5495 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5496 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5497 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5498 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5499 | set_gdbarch_long_bit (gdbarch, 64); |
5500 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5501 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5502 | break; | |
0dadbba0 | 5503 | case MIPS_ABI_N32: |
25ab4790 | 5504 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5505 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5506 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5507 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5508 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5509 | set_gdbarch_long_bit (gdbarch, 32); |
5510 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5511 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 JB |
5512 | set_gdbarch_long_double_bit (gdbarch, 128); |
5513 | set_gdbarch_long_double_format (gdbarch, | |
5514 | &floatformat_n32n64_long_double_big); | |
28d169de KB |
5515 | break; |
5516 | case MIPS_ABI_N64: | |
25ab4790 | 5517 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5518 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5519 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5520 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5521 | tdep->default_mask_address_p = 0; |
5522 | set_gdbarch_long_bit (gdbarch, 64); | |
5523 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5524 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 JB |
5525 | set_gdbarch_long_double_bit (gdbarch, 128); |
5526 | set_gdbarch_long_double_format (gdbarch, | |
5527 | &floatformat_n32n64_long_double_big); | |
0dadbba0 | 5528 | break; |
c2d11a7d | 5529 | default: |
6d82d43b | 5530 | internal_error (__FILE__, __LINE__, "unknown ABI in switch"); |
c2d11a7d JM |
5531 | } |
5532 | ||
a5ea2558 AC |
5533 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5534 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5535 | comment: | |
5536 | ||
5537 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5538 | flag in object files because to do so would make it impossible to | |
102182a9 | 5539 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5540 | unnecessarily restrictive. |
361d1df0 | 5541 | |
a5ea2558 AC |
5542 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5543 | but to set this flag before gcc is built with such multilibs will | |
5544 | break too many systems.'' | |
5545 | ||
5546 | But even more unhelpfully, the default linker output target for | |
5547 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5548 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5549 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5550 | this flag to detect 32-bit mode would do the wrong thing given |
5551 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5552 | as 32-bit programs by default. */ |
a5ea2558 | 5553 | |
6c997a34 | 5554 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 5555 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
bcb0cc15 | 5556 | set_gdbarch_read_sp (gdbarch, mips_read_sp); |
c2d11a7d | 5557 | |
102182a9 MS |
5558 | /* Add/remove bits from an address. The MIPS needs be careful to |
5559 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5560 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5561 | ||
58dfe9ff AC |
5562 | /* Unwind the frame. */ |
5563 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
edfae063 | 5564 | set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id); |
10312cc4 | 5565 | |
102182a9 | 5566 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5567 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
5568 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
5569 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5570 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, | |
5571 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5572 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, | |
5573 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5574 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5575 | |
c2d11a7d JM |
5576 | /* MIPS version of CALL_DUMMY */ |
5577 | ||
9710e734 AC |
5578 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
5579 | replaced by a command, and all targets will default to on stack | |
5580 | (regardless of the stack's execute status). */ | |
5581 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 5582 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 5583 | |
87783b8b AC |
5584 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
5585 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
5586 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
5587 | ||
f7b9e9fc AC |
5588 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5589 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
5590 | |
5591 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 5592 | |
fc0c74b1 AC |
5593 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5594 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5595 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5596 | |
a4b8ebc8 | 5597 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 5598 | |
e11c53d2 | 5599 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 5600 | |
e5ab0dce AC |
5601 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
5602 | ||
3a3bc038 AC |
5603 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
5604 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
5605 | need to all be folded into the target vector. Since they are | |
5606 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
5607 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
5608 | is sitting on? */ | |
5609 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
5610 | ||
e7d6a6d2 | 5611 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 5612 | |
6de918a6 DJ |
5613 | /* NOTE drow/2004-02-11: We overload the core solib trampoline code |
5614 | to support MIPS16. This is a bad thing. Make sure not to do it | |
5615 | if we have an OS ABI that actually supports shared libraries, since | |
5616 | shared library support is more important. If we have an OS someday | |
5617 | that supports both shared libraries and MIPS16, we'll have to find | |
5618 | a better place for these. */ | |
5619 | if (info.osabi == GDB_OSABI_UNKNOWN) | |
5620 | { | |
5621 | set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); | |
c5115f39 | 5622 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_solib_return_trampoline); |
6de918a6 DJ |
5623 | } |
5624 | ||
5625 | /* Hook in OS ABI-specific overrides, if they have been registered. */ | |
5626 | gdbarch_init_osabi (info, gdbarch); | |
757a7cc6 | 5627 | |
5792a79b | 5628 | /* Unwind the frame. */ |
eec63939 | 5629 | frame_unwind_append_sniffer (gdbarch, mips_stub_frame_sniffer); |
5792a79b | 5630 | frame_unwind_append_sniffer (gdbarch, mips_mdebug_frame_sniffer); |
45c9dd44 AC |
5631 | frame_unwind_append_sniffer (gdbarch, mips_insn16_frame_sniffer); |
5632 | frame_unwind_append_sniffer (gdbarch, mips_insn32_frame_sniffer); | |
eec63939 | 5633 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
5792a79b | 5634 | frame_base_append_sniffer (gdbarch, mips_mdebug_frame_base_sniffer); |
45c9dd44 AC |
5635 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
5636 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 5637 | |
4b9b3959 AC |
5638 | return gdbarch; |
5639 | } | |
5640 | ||
2e4ebe70 | 5641 | static void |
6d82d43b | 5642 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
5643 | { |
5644 | struct gdbarch_info info; | |
5645 | ||
5646 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
5647 | mips_gdbarch_init will take care of the rest. */ | |
5648 | gdbarch_info_init (&info); | |
5649 | gdbarch_update_p (info); | |
5650 | } | |
5651 | ||
ad188201 KB |
5652 | /* Print out which MIPS ABI is in use. */ |
5653 | ||
5654 | static void | |
5655 | show_mips_abi (char *ignore_args, int from_tty) | |
5656 | { | |
5657 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
6d82d43b AC |
5658 | printf_filtered |
5659 | ("The MIPS ABI is unknown because the current architecture is not MIPS.\n"); | |
ad188201 KB |
5660 | else |
5661 | { | |
5662 | enum mips_abi global_abi = global_mips_abi (); | |
5663 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
5664 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
5665 | ||
5666 | if (global_abi == MIPS_ABI_UNKNOWN) | |
6d82d43b AC |
5667 | printf_filtered |
5668 | ("The MIPS ABI is set automatically (currently \"%s\").\n", | |
5669 | actual_abi_str); | |
ad188201 | 5670 | else if (global_abi == actual_abi) |
6d82d43b AC |
5671 | printf_filtered |
5672 | ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
5673 | actual_abi_str); | |
ad188201 KB |
5674 | else |
5675 | { | |
5676 | /* Probably shouldn't happen... */ | |
6d82d43b AC |
5677 | printf_filtered |
5678 | ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
5679 | actual_abi_str, mips_abi_strings[global_abi]); | |
ad188201 KB |
5680 | } |
5681 | } | |
5682 | } | |
5683 | ||
4b9b3959 AC |
5684 | static void |
5685 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
5686 | { | |
5687 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
5688 | if (tdep != NULL) | |
c2d11a7d | 5689 | { |
acdb74a0 AC |
5690 | int ef_mips_arch; |
5691 | int ef_mips_32bitmode; | |
5692 | /* determine the ISA */ | |
5693 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
5694 | { | |
5695 | case E_MIPS_ARCH_1: | |
5696 | ef_mips_arch = 1; | |
5697 | break; | |
5698 | case E_MIPS_ARCH_2: | |
5699 | ef_mips_arch = 2; | |
5700 | break; | |
5701 | case E_MIPS_ARCH_3: | |
5702 | ef_mips_arch = 3; | |
5703 | break; | |
5704 | case E_MIPS_ARCH_4: | |
93d56215 | 5705 | ef_mips_arch = 4; |
acdb74a0 AC |
5706 | break; |
5707 | default: | |
93d56215 | 5708 | ef_mips_arch = 0; |
acdb74a0 AC |
5709 | break; |
5710 | } | |
5711 | /* determine the size of a pointer */ | |
5712 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
5713 | fprintf_unfiltered (file, |
5714 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 5715 | tdep->elf_flags); |
4b9b3959 | 5716 | fprintf_unfiltered (file, |
acdb74a0 AC |
5717 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
5718 | ef_mips_32bitmode); | |
5719 | fprintf_unfiltered (file, | |
5720 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
5721 | ef_mips_arch); | |
5722 | fprintf_unfiltered (file, | |
5723 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 5724 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
5725 | fprintf_unfiltered (file, |
5726 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 5727 | mips_mask_address_p (tdep), |
4014092b | 5728 | tdep->default_mask_address_p); |
c2d11a7d | 5729 | } |
4b9b3959 AC |
5730 | fprintf_unfiltered (file, |
5731 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
5732 | MIPS_DEFAULT_FPU_TYPE, | |
5733 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5734 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5735 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5736 | : "???")); | |
6d82d43b | 5737 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI); |
4b9b3959 AC |
5738 | fprintf_unfiltered (file, |
5739 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
5740 | MIPS_FPU_TYPE, | |
5741 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5742 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5743 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5744 | : "???")); | |
4b9b3959 | 5745 | fprintf_unfiltered (file, |
480d3dd2 | 5746 | "mips_dump_tdep: mips_stack_argsize() = %d\n", |
13326b4e | 5747 | mips_stack_argsize (current_gdbarch)); |
2475bac3 AC |
5748 | fprintf_unfiltered (file, |
5749 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
6d82d43b | 5750 | XSTRING (ADDR_BITS_REMOVE (ADDR))); |
2475bac3 AC |
5751 | fprintf_unfiltered (file, |
5752 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
5753 | XSTRING (ATTACH_DETACH)); | |
2475bac3 AC |
5754 | fprintf_unfiltered (file, |
5755 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
5756 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
5757 | fprintf_unfiltered (file, | |
5758 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
5759 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
2475bac3 AC |
5760 | fprintf_unfiltered (file, |
5761 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
5762 | FIRST_EMBED_REGNUM); | |
2475bac3 | 5763 | fprintf_unfiltered (file, |
a53c66de AC |
5764 | "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n", |
5765 | XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
5766 | fprintf_unfiltered (file, |
5767 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
5768 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
2475bac3 AC |
5769 | fprintf_unfiltered (file, |
5770 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
5771 | LAST_EMBED_REGNUM); | |
2475bac3 AC |
5772 | #ifdef MACHINE_CPROC_FP_OFFSET |
5773 | fprintf_unfiltered (file, | |
5774 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
5775 | MACHINE_CPROC_FP_OFFSET); | |
5776 | #endif | |
5777 | #ifdef MACHINE_CPROC_PC_OFFSET | |
5778 | fprintf_unfiltered (file, | |
5779 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
5780 | MACHINE_CPROC_PC_OFFSET); | |
5781 | #endif | |
5782 | #ifdef MACHINE_CPROC_SP_OFFSET | |
5783 | fprintf_unfiltered (file, | |
5784 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
5785 | MACHINE_CPROC_SP_OFFSET); | |
5786 | #endif | |
6d82d43b | 5787 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); |
2475bac3 AC |
5788 | fprintf_unfiltered (file, |
5789 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
2475bac3 | 5790 | fprintf_unfiltered (file, |
acdb74a0 AC |
5791 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
5792 | MIPS_LAST_ARG_REGNUM, | |
4c7d22cb | 5793 | MIPS_LAST_ARG_REGNUM - MIPS_A0_REGNUM + 1); |
2475bac3 | 5794 | fprintf_unfiltered (file, |
6d82d43b | 5795 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS); |
2475bac3 | 5796 | fprintf_unfiltered (file, |
1b13c4f6 | 5797 | "mips_dump_tdep: mips_abi_regsize() = %d\n", |
13326b4e | 5798 | mips_abi_regsize (current_gdbarch)); |
2475bac3 | 5799 | fprintf_unfiltered (file, |
6d82d43b | 5800 | "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM); |
2475bac3 AC |
5801 | fprintf_unfiltered (file, |
5802 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
5803 | fprintf_unfiltered (file, | |
5804 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
6d82d43b AC |
5805 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FRAME_REG = function?\n"); |
5806 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
5807 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
5808 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
5809 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
5810 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
5811 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
5812 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
5813 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
5814 | fprintf_unfiltered (file, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM); | |
2475bac3 AC |
5815 | #ifdef SAVED_BYTES |
5816 | fprintf_unfiltered (file, | |
6d82d43b | 5817 | "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES); |
2475bac3 AC |
5818 | #endif |
5819 | #ifdef SAVED_FP | |
6d82d43b | 5820 | fprintf_unfiltered (file, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP); |
2475bac3 AC |
5821 | #endif |
5822 | #ifdef SAVED_PC | |
6d82d43b | 5823 | fprintf_unfiltered (file, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC); |
2475bac3 AC |
5824 | #endif |
5825 | fprintf_unfiltered (file, | |
5826 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
5827 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
2475bac3 AC |
5828 | fprintf_unfiltered (file, |
5829 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
5830 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
5831 | fprintf_unfiltered (file, | |
b0ed3589 AC |
5832 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
5833 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
5834 | fprintf_unfiltered (file, |
5835 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
5836 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
5837 | #ifdef STACK_END_ADDR | |
5838 | fprintf_unfiltered (file, | |
5839 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
5840 | STACK_END_ADDR); | |
5841 | #endif | |
5842 | fprintf_unfiltered (file, | |
5843 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
5844 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
5845 | fprintf_unfiltered (file, | |
5846 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
5847 | STEP_SKIPS_DELAY_P); | |
5848 | fprintf_unfiltered (file, | |
5849 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
5850 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
2475bac3 AC |
5851 | fprintf_unfiltered (file, |
5852 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
5853 | fprintf_unfiltered (file, | |
5854 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
6d82d43b AC |
5855 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT |
5856 | (TYPE, CNT, OTHERTYPE))); | |
2475bac3 AC |
5857 | #ifdef TRACE_CLEAR |
5858 | fprintf_unfiltered (file, | |
5859 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
5860 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
5861 | #endif | |
5862 | #ifdef TRACE_FLAVOR | |
5863 | fprintf_unfiltered (file, | |
6d82d43b | 5864 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR); |
2475bac3 AC |
5865 | #endif |
5866 | #ifdef TRACE_FLAVOR_SIZE | |
5867 | fprintf_unfiltered (file, | |
5868 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
5869 | TRACE_FLAVOR_SIZE); | |
5870 | #endif | |
5871 | #ifdef TRACE_SET | |
5872 | fprintf_unfiltered (file, | |
5873 | "mips_dump_tdep: TRACE_SET # %s\n", | |
6d82d43b | 5874 | XSTRING (TRACE_SET (X, STATE))); |
2475bac3 | 5875 | #endif |
2475bac3 AC |
5876 | #ifdef UNUSED_REGNUM |
5877 | fprintf_unfiltered (file, | |
6d82d43b | 5878 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM); |
2475bac3 | 5879 | #endif |
2475bac3 AC |
5880 | fprintf_unfiltered (file, |
5881 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
5882 | (long) VM_MIN_ADDRESS); | |
c2d11a7d JM |
5883 | } |
5884 | ||
6d82d43b | 5885 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 5886 | |
c906108c | 5887 | void |
acdb74a0 | 5888 | _initialize_mips_tdep (void) |
c906108c SS |
5889 | { |
5890 | static struct cmd_list_element *mipsfpulist = NULL; | |
5891 | struct cmd_list_element *c; | |
5892 | ||
6d82d43b | 5893 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
5894 | if (MIPS_ABI_LAST + 1 |
5895 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
5896 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
5897 | ||
4b9b3959 | 5898 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 5899 | |
8d5f9dcb DJ |
5900 | mips_pdr_data = register_objfile_data (); |
5901 | ||
a5ea2558 AC |
5902 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
5903 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
5904 | "Various MIPS specific commands.", | |
5905 | &setmipscmdlist, "set mips ", 0, &setlist); | |
5906 | ||
5907 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
5908 | "Various MIPS specific commands.", | |
5909 | &showmipscmdlist, "show mips ", 0, &showlist); | |
5910 | ||
5911 | /* Allow the user to override the saved register size. */ | |
1b295c3d AC |
5912 | add_setshow_enum_cmd ("saved-gpreg-size", class_obscure, |
5913 | size_enums, &mips_abi_regsize_string, "\ | |
5914 | Set size of general purpose registers saved on the stack.\n", "\ | |
5915 | Show size of general purpose registers saved on the stack.\n", "\ | |
a5ea2558 AC |
5916 | This option can be set to one of:\n\ |
5917 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
5918 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
5919 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
5920 | saved GP register size from information contained in the executable.\n\ | |
1b295c3d AC |
5921 | (default: auto)", "\ |
5922 | Size of general purpose registers saved on the stack is %s.\n", | |
5923 | NULL, NULL, &setmipscmdlist, &showmipscmdlist); | |
a5ea2558 | 5924 | |
d929b26f | 5925 | /* Allow the user to override the argument stack size. */ |
1b295c3d AC |
5926 | add_setshow_enum_cmd ("stack-arg-size", class_obscure, |
5927 | size_enums, &mips_stack_argsize_string, "\ | |
5928 | Set the amount of stack space reserved for each argument.\n", "\ | |
5929 | Show the amount of stack space reserved for each argument.\n", "\ | |
d929b26f AC |
5930 | This option can be set to one of:\n\ |
5931 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
5932 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
5933 | auto - Allow GDB to determine the correct setting from the current\n\ | |
1b295c3d AC |
5934 | target and executable (default)", "\ |
5935 | The amount of stack space reserved for each argument is %s.\n", | |
5936 | NULL, NULL, &setmipscmdlist, &showmipscmdlist); | |
d929b26f | 5937 | |
2e4ebe70 DJ |
5938 | /* Allow the user to override the ABI. */ |
5939 | c = add_set_enum_cmd | |
5940 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
5941 | "Set the ABI used by this program.\n" | |
5942 | "This option can be set to one of:\n" | |
5943 | " auto - the default ABI associated with the current binary\n" | |
5944 | " o32\n" | |
6d82d43b | 5945 | " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist); |
2e4ebe70 | 5946 | set_cmd_sfunc (c, mips_abi_update); |
ad188201 | 5947 | add_cmd ("abi", class_obscure, show_mips_abi, |
6d82d43b | 5948 | "Show ABI in use by MIPS target", &showmipscmdlist); |
2e4ebe70 | 5949 | |
c906108c SS |
5950 | /* Let the user turn off floating point and set the fence post for |
5951 | heuristic_proc_start. */ | |
5952 | ||
5953 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
5954 | "Set use of MIPS floating-point coprocessor.", | |
5955 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
5956 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
5957 | "Select single-precision MIPS floating-point coprocessor.", | |
5958 | &mipsfpulist); | |
5959 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 5960 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
5961 | &mipsfpulist); |
5962 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
5963 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
5964 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
5965 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
6d82d43b | 5966 | "Select no MIPS floating-point coprocessor.", &mipsfpulist); |
c906108c SS |
5967 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
5968 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
5969 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
5970 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
5971 | "Select MIPS floating-point coprocessor automatically.", | |
5972 | &mipsfpulist); | |
5973 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
5974 | "Show current use of MIPS floating-point coprocessor target.", | |
5975 | &showlist); | |
5976 | ||
c906108c SS |
5977 | /* We really would like to have both "0" and "unlimited" work, but |
5978 | command.c doesn't deal with that. So make it a var_zinteger | |
5979 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 AC |
5980 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
5981 | &heuristic_fence_post, "\ | |
5982 | Set the distance searched for the start of a function.\n", "\ | |
5983 | Show the distance searched for the start of a function.\n", "\ | |
c906108c SS |
5984 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
5985 | program for the start of a function. This command sets the distance of the\n\ | |
6bcadd06 AC |
5986 | search. The only need to set it is when debugging a stripped executable.", "\ |
5987 | The distance searched for the start of a function is %s.\n", | |
5988 | reinit_frame_cache_sfunc, NULL, | |
5989 | &setlist, &showlist); | |
c906108c SS |
5990 | |
5991 | /* Allow the user to control whether the upper bits of 64-bit | |
5992 | addresses should be zeroed. */ | |
e9e68a56 | 5993 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
3b64bf98 AC |
5994 | Set zeroing of upper 32 bits of 64-bit addresses.", "\ |
5995 | Show zeroing of upper 32 bits of 64-bit addresses.", "\ | |
e9e68a56 AC |
5996 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ |
5997 | allow GDB to determine the correct value.\n", "\ | |
3b64bf98 | 5998 | Zerroing of upper 32 bits of 64-bit address is %s.", |
6d82d43b | 5999 | NULL, show_mask_address, &setmipscmdlist, &showmipscmdlist); |
43e526b9 JM |
6000 | |
6001 | /* Allow the user to control the size of 32 bit registers within the | |
6002 | raw remote packet. */ | |
b3f42336 AC |
6003 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
6004 | &mips64_transfers_32bit_regs_p, "\ | |
3b64bf98 AC |
6005 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\ |
6006 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\ | |
719ec221 AC |
6007 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6008 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6d82d43b | 6009 | 64 bits for others. Use \"off\" to disable compatibility mode", "\ |
3b64bf98 AC |
6010 | Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.", |
6011 | set_mips64_transfers_32bit_regs, NULL, &setlist, &showlist); | |
9ace0497 AC |
6012 | |
6013 | /* Debug this files internals. */ | |
6bcadd06 AC |
6014 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
6015 | &mips_debug, "\ | |
6016 | Set mips debugging.\n", "\ | |
6017 | Show mips debugging.\n", "\ | |
6018 | When non-zero, mips specific debugging is enabled.\n", "\ | |
6019 | Mips debugging is currently %s.\n", | |
6020 | NULL, NULL, | |
6021 | &setdebuglist, &showdebuglist); | |
c906108c | 6022 | } |