Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a AC |
3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
4 | 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. | |
bf64bfd6 | 5 | |
c906108c SS |
6 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
7 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
8 | ||
c5aa993b | 9 | This file is part of GDB. |
c906108c | 10 | |
c5aa993b JM |
11 | This program is free software; you can redistribute it and/or modify |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2 of the License, or | |
14 | (at your option) any later version. | |
c906108c | 15 | |
c5aa993b JM |
16 | This program is distributed in the hope that it will be useful, |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
c906108c | 20 | |
c5aa993b JM |
21 | You should have received a copy of the GNU General Public License |
22 | along with this program; if not, write to the Free Software | |
23 | Foundation, Inc., 59 Temple Place - Suite 330, | |
24 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
25 | |
26 | #include "defs.h" | |
27 | #include "gdb_string.h" | |
28 | #include "frame.h" | |
29 | #include "inferior.h" | |
30 | #include "symtab.h" | |
31 | #include "value.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "language.h" | |
34 | #include "gdbcore.h" | |
35 | #include "symfile.h" | |
36 | #include "objfiles.h" | |
37 | #include "gdbtypes.h" | |
38 | #include "target.h" | |
28d069e6 | 39 | #include "arch-utils.h" |
4e052eda | 40 | #include "regcache.h" |
70f80edf | 41 | #include "osabi.h" |
c906108c SS |
42 | |
43 | #include "opcode/mips.h" | |
c2d11a7d JM |
44 | #include "elf/mips.h" |
45 | #include "elf-bfd.h" | |
2475bac3 | 46 | #include "symcat.h" |
c906108c | 47 | |
dd824b04 DJ |
48 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
49 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
50 | #define ST0_FR (1 << 26) | |
51 | ||
b0069a17 AC |
52 | /* The sizes of floating point registers. */ |
53 | ||
54 | enum | |
55 | { | |
56 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
57 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
58 | }; | |
59 | ||
0dadbba0 AC |
60 | /* All the possible MIPS ABIs. */ |
61 | ||
62 | enum mips_abi | |
63 | { | |
2e4ebe70 | 64 | MIPS_ABI_UNKNOWN = 0, |
0dadbba0 AC |
65 | MIPS_ABI_N32, |
66 | MIPS_ABI_O32, | |
28d169de | 67 | MIPS_ABI_N64, |
0dadbba0 AC |
68 | MIPS_ABI_O64, |
69 | MIPS_ABI_EABI32, | |
2e4ebe70 DJ |
70 | MIPS_ABI_EABI64, |
71 | MIPS_ABI_LAST | |
0dadbba0 AC |
72 | }; |
73 | ||
2e4ebe70 DJ |
74 | static const char *mips_abi_string; |
75 | ||
76 | static const char *mips_abi_strings[] = { | |
77 | "auto", | |
78 | "n32", | |
79 | "o32", | |
28d169de | 80 | "n64", |
2e4ebe70 DJ |
81 | "o64", |
82 | "eabi32", | |
83 | "eabi64", | |
84 | NULL | |
85 | }; | |
86 | ||
cce74817 | 87 | struct frame_extra_info |
c5aa993b JM |
88 | { |
89 | mips_extra_func_info_t proc_desc; | |
90 | int num_args; | |
91 | }; | |
cce74817 | 92 | |
d929b26f AC |
93 | /* Various MIPS ISA options (related to stack analysis) can be |
94 | overridden dynamically. Establish an enum/array for managing | |
95 | them. */ | |
96 | ||
53904c9e AC |
97 | static const char size_auto[] = "auto"; |
98 | static const char size_32[] = "32"; | |
99 | static const char size_64[] = "64"; | |
d929b26f | 100 | |
53904c9e | 101 | static const char *size_enums[] = { |
d929b26f AC |
102 | size_auto, |
103 | size_32, | |
104 | size_64, | |
a5ea2558 AC |
105 | 0 |
106 | }; | |
107 | ||
7a292a7a SS |
108 | /* Some MIPS boards don't support floating point while others only |
109 | support single-precision floating-point operations. See also | |
110 | FP_REGISTER_DOUBLE. */ | |
c906108c SS |
111 | |
112 | enum mips_fpu_type | |
c5aa993b JM |
113 | { |
114 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
115 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
116 | MIPS_FPU_NONE /* No floating point. */ | |
117 | }; | |
c906108c SS |
118 | |
119 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
120 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
121 | #endif | |
122 | static int mips_fpu_type_auto = 1; | |
123 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 124 | |
9ace0497 | 125 | static int mips_debug = 0; |
7a292a7a | 126 | |
c2d11a7d JM |
127 | /* MIPS specific per-architecture information */ |
128 | struct gdbarch_tdep | |
129 | { | |
130 | /* from the elf header */ | |
131 | int elf_flags; | |
70f80edf | 132 | |
c2d11a7d | 133 | /* mips options */ |
0dadbba0 | 134 | enum mips_abi mips_abi; |
2e4ebe70 | 135 | enum mips_abi found_abi; |
c2d11a7d JM |
136 | enum mips_fpu_type mips_fpu_type; |
137 | int mips_last_arg_regnum; | |
138 | int mips_last_fp_arg_regnum; | |
a5ea2558 | 139 | int mips_default_saved_regsize; |
c2d11a7d | 140 | int mips_fp_register_double; |
d929b26f | 141 | int mips_default_stack_argsize; |
5213ab06 | 142 | int gdb_target_is_mips64; |
4014092b | 143 | int default_mask_address_p; |
70f80edf JT |
144 | |
145 | enum gdb_osabi osabi; | |
c2d11a7d JM |
146 | }; |
147 | ||
0dadbba0 | 148 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 149 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 150 | |
c2d11a7d | 151 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 152 | |
c2d11a7d | 153 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 154 | |
c2d11a7d | 155 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 156 | |
d929b26f AC |
157 | /* Return the currently configured (or set) saved register size. */ |
158 | ||
a5ea2558 | 159 | #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize) |
c2d11a7d | 160 | |
53904c9e | 161 | static const char *mips_saved_regsize_string = size_auto; |
d929b26f AC |
162 | |
163 | #define MIPS_SAVED_REGSIZE (mips_saved_regsize()) | |
164 | ||
165 | static unsigned int | |
acdb74a0 | 166 | mips_saved_regsize (void) |
d929b26f AC |
167 | { |
168 | if (mips_saved_regsize_string == size_auto) | |
169 | return MIPS_DEFAULT_SAVED_REGSIZE; | |
170 | else if (mips_saved_regsize_string == size_64) | |
171 | return 8; | |
172 | else /* if (mips_saved_regsize_string == size_32) */ | |
173 | return 4; | |
174 | } | |
175 | ||
dd824b04 DJ |
176 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
177 | compatiblity mode. A return value of 1 means that we have | |
178 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
179 | ||
180 | static int | |
181 | mips2_fp_compat (void) | |
182 | { | |
183 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
184 | meaningful. */ | |
185 | if (REGISTER_RAW_SIZE (FP0_REGNUM) == 4) | |
186 | return 0; | |
187 | ||
188 | #if 0 | |
189 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
190 | in all the places we deal with FP registers. PR gdb/413. */ | |
191 | /* Otherwise check the FR bit in the status register - it controls | |
192 | the FP compatiblity mode. If it is clear we are in compatibility | |
193 | mode. */ | |
194 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
195 | return 1; | |
196 | #endif | |
361d1df0 | 197 | |
dd824b04 DJ |
198 | return 0; |
199 | } | |
200 | ||
c2d11a7d JM |
201 | /* Indicate that the ABI makes use of double-precision registers |
202 | provided by the FPU (rather than combining pairs of registers to | |
203 | form double-precision values). Do not use "TARGET_IS_MIPS64" to | |
204 | determine if the ABI is using double-precision registers. See also | |
205 | MIPS_FPU_TYPE. */ | |
c2d11a7d | 206 | #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double) |
c2d11a7d | 207 | |
d929b26f AC |
208 | /* The amount of space reserved on the stack for registers. This is |
209 | different to MIPS_SAVED_REGSIZE as it determines the alignment of | |
210 | data allocated after the registers have run out. */ | |
211 | ||
0dadbba0 | 212 | #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize) |
d929b26f AC |
213 | |
214 | #define MIPS_STACK_ARGSIZE (mips_stack_argsize ()) | |
215 | ||
53904c9e | 216 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
217 | |
218 | static unsigned int | |
219 | mips_stack_argsize (void) | |
220 | { | |
221 | if (mips_stack_argsize_string == size_auto) | |
222 | return MIPS_DEFAULT_STACK_ARGSIZE; | |
223 | else if (mips_stack_argsize_string == size_64) | |
224 | return 8; | |
225 | else /* if (mips_stack_argsize_string == size_32) */ | |
226 | return 4; | |
227 | } | |
228 | ||
5213ab06 | 229 | #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0) |
c2d11a7d | 230 | |
92e1c15c | 231 | #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p) |
92e1c15c | 232 | |
7a292a7a | 233 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 234 | |
a14ed312 | 235 | int gdb_print_insn_mips (bfd_vma, disassemble_info *); |
c906108c | 236 | |
a14ed312 | 237 | static void mips_print_register (int, int); |
c906108c SS |
238 | |
239 | static mips_extra_func_info_t | |
479412cd | 240 | heuristic_proc_desc (CORE_ADDR, CORE_ADDR, struct frame_info *, int); |
c906108c | 241 | |
a14ed312 | 242 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 243 | |
a14ed312 | 244 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 245 | |
a14ed312 | 246 | int mips_set_processor_type (char *); |
c906108c | 247 | |
a14ed312 | 248 | static void mips_show_processor_type_command (char *, int); |
c906108c | 249 | |
a14ed312 | 250 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c SS |
251 | |
252 | static mips_extra_func_info_t | |
479412cd | 253 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame); |
c906108c | 254 | |
a14ed312 KB |
255 | static CORE_ADDR after_prologue (CORE_ADDR pc, |
256 | mips_extra_func_info_t proc_desc); | |
c906108c | 257 | |
dd824b04 DJ |
258 | static void mips_read_fp_register_single (int regno, char *rare_buffer); |
259 | static void mips_read_fp_register_double (int regno, char *rare_buffer); | |
260 | ||
67b2c998 DJ |
261 | static struct type *mips_float_register_type (void); |
262 | static struct type *mips_double_register_type (void); | |
263 | ||
c906108c SS |
264 | /* This value is the model of MIPS in use. It is derived from the value |
265 | of the PrID register. */ | |
266 | ||
267 | char *mips_processor_type; | |
268 | ||
269 | char *tmp_mips_processor_type; | |
270 | ||
acdb74a0 AC |
271 | /* The list of available "set mips " and "show mips " commands */ |
272 | ||
273 | static struct cmd_list_element *setmipscmdlist = NULL; | |
274 | static struct cmd_list_element *showmipscmdlist = NULL; | |
275 | ||
c906108c SS |
276 | /* A set of original names, to be used when restoring back to generic |
277 | registers from a specific set. */ | |
278 | ||
cce74817 JM |
279 | char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES; |
280 | char **mips_processor_reg_names = mips_generic_reg_names; | |
281 | ||
fa88f677 | 282 | const char * |
fba45db2 | 283 | mips_register_name (int i) |
cce74817 JM |
284 | { |
285 | return mips_processor_reg_names[i]; | |
286 | } | |
9846de1b | 287 | /* *INDENT-OFF* */ |
c906108c SS |
288 | /* Names of IDT R3041 registers. */ |
289 | ||
290 | char *mips_r3041_reg_names[] = { | |
291 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
292 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
293 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
294 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
295 | "sr", "lo", "hi", "bad", "cause","pc", | |
296 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
297 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
298 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
299 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
300 | "fsr", "fir", "fp", "", | |
301 | "", "", "bus", "ccfg", "", "", "", "", | |
302 | "", "", "port", "cmp", "", "", "epc", "prid", | |
303 | }; | |
304 | ||
305 | /* Names of IDT R3051 registers. */ | |
306 | ||
307 | char *mips_r3051_reg_names[] = { | |
308 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
309 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
310 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
311 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
312 | "sr", "lo", "hi", "bad", "cause","pc", | |
313 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
314 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
315 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
316 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
317 | "fsr", "fir", "fp", "", | |
318 | "inx", "rand", "elo", "", "ctxt", "", "", "", | |
319 | "", "", "ehi", "", "", "", "epc", "prid", | |
320 | }; | |
321 | ||
322 | /* Names of IDT R3081 registers. */ | |
323 | ||
324 | char *mips_r3081_reg_names[] = { | |
325 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
326 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
327 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
328 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
329 | "sr", "lo", "hi", "bad", "cause","pc", | |
330 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
331 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
332 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
333 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
334 | "fsr", "fir", "fp", "", | |
335 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", | |
336 | "", "", "ehi", "", "", "", "epc", "prid", | |
337 | }; | |
338 | ||
339 | /* Names of LSI 33k registers. */ | |
340 | ||
341 | char *mips_lsi33k_reg_names[] = { | |
342 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
343 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
344 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
345 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
346 | "epc", "hi", "lo", "sr", "cause","badvaddr", | |
347 | "dcic", "bpc", "bda", "", "", "", "", "", | |
348 | "", "", "", "", "", "", "", "", | |
349 | "", "", "", "", "", "", "", "", | |
350 | "", "", "", "", "", "", "", "", | |
351 | "", "", "", "", | |
352 | "", "", "", "", "", "", "", "", | |
353 | "", "", "", "", "", "", "", "", | |
354 | }; | |
355 | ||
356 | struct { | |
357 | char *name; | |
358 | char **regnames; | |
359 | } mips_processor_type_table[] = { | |
360 | { "generic", mips_generic_reg_names }, | |
361 | { "r3041", mips_r3041_reg_names }, | |
362 | { "r3051", mips_r3051_reg_names }, | |
363 | { "r3071", mips_r3081_reg_names }, | |
364 | { "r3081", mips_r3081_reg_names }, | |
365 | { "lsi33k", mips_lsi33k_reg_names }, | |
366 | { NULL, NULL } | |
367 | }; | |
9846de1b | 368 | /* *INDENT-ON* */ |
c906108c | 369 | |
c5aa993b JM |
370 | |
371 | ||
372 | ||
c906108c | 373 | /* Table to translate MIPS16 register field to actual register number. */ |
c5aa993b JM |
374 | static int mips16_to_32_reg[8] = |
375 | {16, 17, 2, 3, 4, 5, 6, 7}; | |
c906108c SS |
376 | |
377 | /* Heuristic_proc_start may hunt through the text section for a long | |
378 | time across a 2400 baud serial line. Allows the user to limit this | |
379 | search. */ | |
380 | ||
381 | static unsigned int heuristic_fence_post = 0; | |
382 | ||
c5aa993b JM |
383 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
384 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
385 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
386 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
387 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
388 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
389 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
390 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
391 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
392 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
6c0d6680 DJ |
393 | /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, |
394 | this will corrupt pdr.iline. Fortunately we don't use it. */ | |
c906108c SS |
395 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
396 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
397 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) | |
398 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) | |
399 | ||
400 | struct linked_proc_info | |
c5aa993b JM |
401 | { |
402 | struct mips_extra_func_info info; | |
403 | struct linked_proc_info *next; | |
404 | } | |
405 | *linked_proc_desc_table = NULL; | |
c906108c | 406 | |
cce74817 | 407 | void |
acdb74a0 | 408 | mips_print_extra_frame_info (struct frame_info *fi) |
cce74817 JM |
409 | { |
410 | if (fi | |
411 | && fi->extra_info | |
412 | && fi->extra_info->proc_desc | |
413 | && fi->extra_info->proc_desc->pdr.framereg < NUM_REGS) | |
d4f3574e | 414 | printf_filtered (" frame pointer is at %s+%s\n", |
cce74817 | 415 | REGISTER_NAME (fi->extra_info->proc_desc->pdr.framereg), |
d4f3574e | 416 | paddr_d (fi->extra_info->proc_desc->pdr.frameoffset)); |
cce74817 | 417 | } |
c906108c | 418 | |
46cd78fb AC |
419 | /* Number of bytes of storage in the actual machine representation for |
420 | register N. NOTE: This indirectly defines the register size | |
421 | transfered by the GDB protocol. */ | |
43e526b9 JM |
422 | |
423 | static int mips64_transfers_32bit_regs_p = 0; | |
424 | ||
425 | int | |
acdb74a0 | 426 | mips_register_raw_size (int reg_nr) |
43e526b9 JM |
427 | { |
428 | if (mips64_transfers_32bit_regs_p) | |
429 | return REGISTER_VIRTUAL_SIZE (reg_nr); | |
d02ee681 AC |
430 | else if (reg_nr >= FP0_REGNUM && reg_nr < FP0_REGNUM + 32 |
431 | && FP_REGISTER_DOUBLE) | |
432 | /* For MIPS_ABI_N32 (for example) we need 8 byte floating point | |
433 | registers. */ | |
434 | return 8; | |
43e526b9 JM |
435 | else |
436 | return MIPS_REGSIZE; | |
437 | } | |
438 | ||
46cd78fb AC |
439 | /* Convert between RAW and VIRTUAL registers. The RAW register size |
440 | defines the remote-gdb packet. */ | |
441 | ||
43e526b9 | 442 | int |
acdb74a0 | 443 | mips_register_convertible (int reg_nr) |
43e526b9 JM |
444 | { |
445 | if (mips64_transfers_32bit_regs_p) | |
446 | return 0; | |
447 | else | |
448 | return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr)); | |
449 | } | |
450 | ||
451 | void | |
acdb74a0 AC |
452 | mips_register_convert_to_virtual (int n, struct type *virtual_type, |
453 | char *raw_buf, char *virt_buf) | |
43e526b9 | 454 | { |
d7449b42 | 455 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
43e526b9 JM |
456 | memcpy (virt_buf, |
457 | raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), | |
458 | TYPE_LENGTH (virtual_type)); | |
459 | else | |
460 | memcpy (virt_buf, | |
461 | raw_buf, | |
462 | TYPE_LENGTH (virtual_type)); | |
463 | } | |
464 | ||
465 | void | |
acdb74a0 AC |
466 | mips_register_convert_to_raw (struct type *virtual_type, int n, |
467 | char *virt_buf, char *raw_buf) | |
43e526b9 JM |
468 | { |
469 | memset (raw_buf, 0, REGISTER_RAW_SIZE (n)); | |
d7449b42 | 470 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
43e526b9 JM |
471 | memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), |
472 | virt_buf, | |
473 | TYPE_LENGTH (virtual_type)); | |
474 | else | |
475 | memcpy (raw_buf, | |
476 | virt_buf, | |
477 | TYPE_LENGTH (virtual_type)); | |
478 | } | |
479 | ||
78fde5f8 KB |
480 | /* Return the GDB type object for the "standard" data type |
481 | of data in register REG. | |
482 | ||
483 | Note: kevinb/2002-08-01: The definition below should faithfully | |
484 | reproduce the behavior of each of the REGISTER_VIRTUAL_TYPE | |
485 | definitions found in config/mips/tm-*.h. I'm concerned about | |
486 | the ``FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM'' clause | |
487 | though. In some cases FP_REGNUM is in this range, and I doubt | |
488 | that this code is correct for the 64-bit case. */ | |
489 | ||
490 | static struct type * | |
491 | mips_register_virtual_type (int reg) | |
492 | { | |
493 | if (FP0_REGNUM <= reg && reg < FP0_REGNUM + 32) | |
a6425924 KB |
494 | { |
495 | /* Floating point registers... */ | |
496 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
497 | return builtin_type_ieee_double_big; | |
498 | else | |
499 | return builtin_type_ieee_double_little; | |
500 | } | |
78fde5f8 KB |
501 | else if (reg == PS_REGNUM /* CR */) |
502 | return builtin_type_uint32; | |
503 | else if (FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM) | |
504 | return builtin_type_uint32; | |
505 | else | |
506 | { | |
a6425924 KB |
507 | /* Everything else... |
508 | Return type appropriate for width of register. */ | |
509 | if (MIPS_REGSIZE == TYPE_LENGTH (builtin_type_uint64)) | |
510 | return builtin_type_uint64; | |
78fde5f8 | 511 | else |
a6425924 | 512 | return builtin_type_uint32; |
78fde5f8 KB |
513 | } |
514 | } | |
515 | ||
c906108c | 516 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 517 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
518 | |
519 | static int | |
520 | mips_mask_address_p (void) | |
521 | { | |
522 | switch (mask_address_var) | |
523 | { | |
7f19b9a2 | 524 | case AUTO_BOOLEAN_TRUE: |
4014092b | 525 | return 1; |
7f19b9a2 | 526 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
527 | return 0; |
528 | break; | |
7f19b9a2 | 529 | case AUTO_BOOLEAN_AUTO: |
92e1c15c | 530 | return MIPS_DEFAULT_MASK_ADDRESS_P; |
4014092b | 531 | default: |
8e65ff28 AC |
532 | internal_error (__FILE__, __LINE__, |
533 | "mips_mask_address_p: bad switch"); | |
4014092b | 534 | return -1; |
361d1df0 | 535 | } |
4014092b AC |
536 | } |
537 | ||
538 | static void | |
e9e68a56 | 539 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b AC |
540 | { |
541 | switch (mask_address_var) | |
542 | { | |
7f19b9a2 | 543 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
544 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
545 | break; | |
7f19b9a2 | 546 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
547 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
548 | break; | |
7f19b9a2 | 549 | case AUTO_BOOLEAN_AUTO: |
4014092b AC |
550 | printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n", |
551 | mips_mask_address_p () ? "enabled" : "disabled"); | |
552 | break; | |
553 | default: | |
8e65ff28 AC |
554 | internal_error (__FILE__, __LINE__, |
555 | "show_mask_address: bad switch"); | |
4014092b | 556 | break; |
361d1df0 | 557 | } |
4014092b | 558 | } |
c906108c SS |
559 | |
560 | /* Should call_function allocate stack space for a struct return? */ | |
cb811fe7 | 561 | |
c906108c | 562 | int |
cb811fe7 | 563 | mips_eabi_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 564 | { |
cb811fe7 MS |
565 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
566 | } | |
567 | ||
568 | int | |
569 | mips_n32n64_use_struct_convention (int gcc_p, struct type *type) | |
570 | { | |
b78bcb18 | 571 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
cb811fe7 MS |
572 | } |
573 | ||
574 | int | |
575 | mips_o32_use_struct_convention (int gcc_p, struct type *type) | |
576 | { | |
577 | return 1; /* Structures are returned by ref in extra arg0. */ | |
c906108c SS |
578 | } |
579 | ||
8b389c40 MS |
580 | /* Should call_function pass struct by reference? |
581 | For each architecture, structs are passed either by | |
582 | value or by reference, depending on their size. */ | |
583 | ||
584 | static int | |
585 | mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type) | |
586 | { | |
587 | enum type_code typecode = TYPE_CODE (check_typedef (type)); | |
588 | int len = TYPE_LENGTH (check_typedef (type)); | |
589 | ||
590 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
591 | return (len > MIPS_SAVED_REGSIZE); | |
592 | ||
593 | return 0; | |
594 | } | |
595 | ||
596 | static int | |
597 | mips_n32n64_reg_struct_has_addr (int gcc_p, struct type *type) | |
598 | { | |
599 | return 0; /* Assumption: N32/N64 never passes struct by ref. */ | |
600 | } | |
601 | ||
602 | int | |
603 | mips_o32_reg_struct_has_addr (int gcc_p, struct type *type) | |
604 | { | |
605 | return 0; /* Assumption: O32/O64 never passes struct by ref. */ | |
606 | } | |
607 | ||
c906108c SS |
608 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
609 | ||
610 | static int | |
611 | pc_is_mips16 (bfd_vma memaddr) | |
612 | { | |
613 | struct minimal_symbol *sym; | |
614 | ||
615 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
616 | if (IS_MIPS16_ADDR (memaddr)) | |
617 | return 1; | |
618 | ||
619 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
620 | the high bit of the info field. Use this to decide if the function is | |
621 | MIPS16 or normal MIPS. */ | |
622 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
623 | if (sym) | |
624 | return MSYMBOL_IS_SPECIAL (sym); | |
625 | else | |
626 | return 0; | |
627 | } | |
628 | ||
6c997a34 AC |
629 | /* MIPS believes that the PC has a sign extended value. Perhaphs the |
630 | all registers should be sign extended for simplicity? */ | |
631 | ||
632 | static CORE_ADDR | |
39f77062 | 633 | mips_read_pc (ptid_t ptid) |
6c997a34 | 634 | { |
39f77062 | 635 | return read_signed_register_pid (PC_REGNUM, ptid); |
6c997a34 | 636 | } |
c906108c SS |
637 | |
638 | /* This returns the PC of the first inst after the prologue. If we can't | |
639 | find the prologue, then return 0. */ | |
640 | ||
641 | static CORE_ADDR | |
acdb74a0 AC |
642 | after_prologue (CORE_ADDR pc, |
643 | mips_extra_func_info_t proc_desc) | |
c906108c SS |
644 | { |
645 | struct symtab_and_line sal; | |
646 | CORE_ADDR func_addr, func_end; | |
647 | ||
479412cd DJ |
648 | /* Pass cur_frame == 0 to find_proc_desc. We should not attempt |
649 | to read the stack pointer from the current machine state, because | |
650 | the current machine state has nothing to do with the information | |
651 | we need from the proc_desc; and the process may or may not exist | |
652 | right now. */ | |
c906108c | 653 | if (!proc_desc) |
479412cd | 654 | proc_desc = find_proc_desc (pc, NULL, 0); |
c906108c SS |
655 | |
656 | if (proc_desc) | |
657 | { | |
658 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 659 | strongly suspect that frameless always means prologueless... */ |
c906108c SS |
660 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
661 | && PROC_FRAME_OFFSET (proc_desc) == 0) | |
662 | return 0; | |
663 | } | |
664 | ||
665 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
666 | return 0; /* Unknown */ | |
667 | ||
668 | sal = find_pc_line (func_addr, 0); | |
669 | ||
670 | if (sal.end < func_end) | |
671 | return sal.end; | |
672 | ||
673 | /* The line after the prologue is after the end of the function. In this | |
674 | case, tell the caller to find the prologue the hard way. */ | |
675 | ||
676 | return 0; | |
677 | } | |
678 | ||
679 | /* Decode a MIPS32 instruction that saves a register in the stack, and | |
680 | set the appropriate bit in the general register mask or float register mask | |
681 | to indicate which register is saved. This is a helper function | |
682 | for mips_find_saved_regs. */ | |
683 | ||
684 | static void | |
acdb74a0 AC |
685 | mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask, |
686 | unsigned long *float_mask) | |
c906108c SS |
687 | { |
688 | int reg; | |
689 | ||
690 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ | |
691 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ | |
692 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ | |
693 | { | |
694 | /* It might be possible to use the instruction to | |
c5aa993b JM |
695 | find the offset, rather than the code below which |
696 | is based on things being in a certain order in the | |
697 | frame, but figuring out what the instruction's offset | |
698 | is relative to might be a little tricky. */ | |
c906108c SS |
699 | reg = (inst & 0x001f0000) >> 16; |
700 | *gen_mask |= (1 << reg); | |
701 | } | |
702 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ | |
c5aa993b JM |
703 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
704 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ | |
c906108c SS |
705 | |
706 | { | |
707 | reg = ((inst & 0x001f0000) >> 16); | |
708 | *float_mask |= (1 << reg); | |
709 | } | |
710 | } | |
711 | ||
712 | /* Decode a MIPS16 instruction that saves a register in the stack, and | |
713 | set the appropriate bit in the general register or float register mask | |
714 | to indicate which register is saved. This is a helper function | |
715 | for mips_find_saved_regs. */ | |
716 | ||
717 | static void | |
acdb74a0 | 718 | mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask) |
c906108c | 719 | { |
c5aa993b | 720 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
c906108c SS |
721 | { |
722 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
723 | *gen_mask |= (1 << reg); | |
724 | } | |
c5aa993b | 725 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
c906108c SS |
726 | { |
727 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
728 | *gen_mask |= (1 << reg); | |
729 | } | |
c5aa993b | 730 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
c906108c SS |
731 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
732 | *gen_mask |= (1 << RA_REGNUM); | |
733 | } | |
734 | ||
735 | ||
736 | /* Fetch and return instruction from the specified location. If the PC | |
737 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
738 | ||
739 | static t_inst | |
acdb74a0 | 740 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c SS |
741 | { |
742 | char buf[MIPS_INSTLEN]; | |
743 | int instlen; | |
744 | int status; | |
745 | ||
746 | if (pc_is_mips16 (addr)) | |
747 | { | |
748 | instlen = MIPS16_INSTLEN; | |
749 | addr = UNMAKE_MIPS16_ADDR (addr); | |
750 | } | |
751 | else | |
c5aa993b | 752 | instlen = MIPS_INSTLEN; |
c906108c SS |
753 | status = read_memory_nobpt (addr, buf, instlen); |
754 | if (status) | |
755 | memory_error (status, addr); | |
756 | return extract_unsigned_integer (buf, instlen); | |
757 | } | |
758 | ||
759 | ||
760 | /* These the fields of 32 bit mips instructions */ | |
e135b889 DJ |
761 | #define mips32_op(x) (x >> 26) |
762 | #define itype_op(x) (x >> 26) | |
763 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 764 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 765 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 766 | |
e135b889 DJ |
767 | #define jtype_op(x) (x >> 26) |
768 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 769 | |
e135b889 DJ |
770 | #define rtype_op(x) (x >> 26) |
771 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
772 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
773 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
774 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
775 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
776 | |
777 | static CORE_ADDR | |
c5aa993b JM |
778 | mips32_relative_offset (unsigned long inst) |
779 | { | |
780 | long x; | |
781 | x = itype_immediate (inst); | |
782 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 783 | { |
c5aa993b | 784 | x |= 0xffff0000; /* sign extension */ |
c906108c | 785 | } |
c5aa993b JM |
786 | x = x << 2; |
787 | return x; | |
c906108c SS |
788 | } |
789 | ||
790 | /* Determine whate to set a single step breakpoint while considering | |
791 | branch prediction */ | |
792 | CORE_ADDR | |
c5aa993b JM |
793 | mips32_next_pc (CORE_ADDR pc) |
794 | { | |
795 | unsigned long inst; | |
796 | int op; | |
797 | inst = mips_fetch_instruction (pc); | |
e135b889 | 798 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 799 | { |
e135b889 DJ |
800 | if (itype_op (inst) >> 2 == 5) |
801 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
c5aa993b | 802 | { |
e135b889 | 803 | op = (itype_op (inst) & 0x03); |
c906108c SS |
804 | switch (op) |
805 | { | |
e135b889 DJ |
806 | case 0: /* BEQL */ |
807 | goto equal_branch; | |
808 | case 1: /* BNEL */ | |
809 | goto neq_branch; | |
810 | case 2: /* BLEZL */ | |
811 | goto less_branch; | |
812 | case 3: /* BGTZ */ | |
813 | goto greater_branch; | |
c5aa993b JM |
814 | default: |
815 | pc += 4; | |
c906108c SS |
816 | } |
817 | } | |
e135b889 DJ |
818 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
819 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ | |
820 | { | |
821 | int tf = itype_rt (inst) & 0x01; | |
822 | int cnum = itype_rt (inst) >> 2; | |
823 | int fcrcs = read_signed_register (FCRCS_REGNUM); | |
824 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); | |
825 | ||
826 | if (((cond >> cnum) & 0x01) == tf) | |
827 | pc += mips32_relative_offset (inst) + 4; | |
828 | else | |
829 | pc += 8; | |
830 | } | |
c5aa993b JM |
831 | else |
832 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
833 | } |
834 | else | |
c5aa993b JM |
835 | { /* This gets way messy */ |
836 | ||
c906108c | 837 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 838 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 839 | { |
c5aa993b JM |
840 | case 0: /* SPECIAL */ |
841 | op = rtype_funct (inst); | |
842 | switch (op) | |
843 | { | |
844 | case 8: /* JR */ | |
845 | case 9: /* JALR */ | |
6c997a34 AC |
846 | /* Set PC to that address */ |
847 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
848 | break; |
849 | default: | |
850 | pc += 4; | |
851 | } | |
852 | ||
e135b889 | 853 | break; /* end SPECIAL */ |
c5aa993b | 854 | case 1: /* REGIMM */ |
c906108c | 855 | { |
e135b889 DJ |
856 | op = itype_rt (inst); /* branch condition */ |
857 | switch (op) | |
c906108c | 858 | { |
c5aa993b | 859 | case 0: /* BLTZ */ |
e135b889 DJ |
860 | case 2: /* BLTZL */ |
861 | case 16: /* BLTZAL */ | |
c5aa993b | 862 | case 18: /* BLTZALL */ |
c906108c | 863 | less_branch: |
6c997a34 | 864 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
865 | pc += mips32_relative_offset (inst) + 4; |
866 | else | |
867 | pc += 8; /* after the delay slot */ | |
868 | break; | |
e135b889 | 869 | case 1: /* BGEZ */ |
c5aa993b JM |
870 | case 3: /* BGEZL */ |
871 | case 17: /* BGEZAL */ | |
872 | case 19: /* BGEZALL */ | |
c906108c | 873 | greater_equal_branch: |
6c997a34 | 874 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
875 | pc += mips32_relative_offset (inst) + 4; |
876 | else | |
877 | pc += 8; /* after the delay slot */ | |
878 | break; | |
e135b889 | 879 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
880 | default: |
881 | pc += 4; | |
c906108c SS |
882 | } |
883 | } | |
e135b889 | 884 | break; /* end REGIMM */ |
c5aa993b JM |
885 | case 2: /* J */ |
886 | case 3: /* JAL */ | |
887 | { | |
888 | unsigned long reg; | |
889 | reg = jtype_target (inst) << 2; | |
e135b889 | 890 | /* Upper four bits get never changed... */ |
c5aa993b | 891 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 892 | } |
c5aa993b JM |
893 | break; |
894 | /* FIXME case JALX : */ | |
895 | { | |
896 | unsigned long reg; | |
897 | reg = jtype_target (inst) << 2; | |
898 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
899 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
900 | } | |
c5aa993b | 901 | break; /* The new PC will be alternate mode */ |
e135b889 | 902 | case 4: /* BEQ, BEQL */ |
c5aa993b | 903 | equal_branch: |
6c997a34 AC |
904 | if (read_signed_register (itype_rs (inst)) == |
905 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
906 | pc += mips32_relative_offset (inst) + 4; |
907 | else | |
908 | pc += 8; | |
909 | break; | |
e135b889 | 910 | case 5: /* BNE, BNEL */ |
c5aa993b | 911 | neq_branch: |
6c997a34 | 912 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 913 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
914 | pc += mips32_relative_offset (inst) + 4; |
915 | else | |
916 | pc += 8; | |
917 | break; | |
e135b889 | 918 | case 6: /* BLEZ, BLEZL */ |
c906108c | 919 | less_zero_branch: |
6c997a34 | 920 | if (read_signed_register (itype_rs (inst) <= 0)) |
c5aa993b JM |
921 | pc += mips32_relative_offset (inst) + 4; |
922 | else | |
923 | pc += 8; | |
924 | break; | |
925 | case 7: | |
e135b889 DJ |
926 | default: |
927 | greater_branch: /* BGTZ, BGTZL */ | |
6c997a34 | 928 | if (read_signed_register (itype_rs (inst) > 0)) |
c5aa993b JM |
929 | pc += mips32_relative_offset (inst) + 4; |
930 | else | |
931 | pc += 8; | |
932 | break; | |
c5aa993b JM |
933 | } /* switch */ |
934 | } /* else */ | |
935 | return pc; | |
936 | } /* mips32_next_pc */ | |
c906108c SS |
937 | |
938 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 939 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
940 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
941 | We dont want to set a single step instruction on the extend instruction | |
942 | either. | |
c5aa993b | 943 | */ |
c906108c SS |
944 | |
945 | /* Lots of mips16 instruction formats */ | |
946 | /* Predicting jumps requires itype,ritype,i8type | |
947 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 948 | */ |
c906108c SS |
949 | enum mips16_inst_fmts |
950 | { | |
c5aa993b JM |
951 | itype, /* 0 immediate 5,10 */ |
952 | ritype, /* 1 5,3,8 */ | |
953 | rrtype, /* 2 5,3,3,5 */ | |
954 | rritype, /* 3 5,3,3,5 */ | |
955 | rrrtype, /* 4 5,3,3,3,2 */ | |
956 | rriatype, /* 5 5,3,3,1,4 */ | |
957 | shifttype, /* 6 5,3,3,3,2 */ | |
958 | i8type, /* 7 5,3,8 */ | |
959 | i8movtype, /* 8 5,3,3,5 */ | |
960 | i8mov32rtype, /* 9 5,3,5,3 */ | |
961 | i64type, /* 10 5,3,8 */ | |
962 | ri64type, /* 11 5,3,3,5 */ | |
963 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
964 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
965 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
966 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
967 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
968 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
969 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
970 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
971 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
972 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
973 | }; | |
12f02c2a AC |
974 | /* I am heaping all the fields of the formats into one structure and |
975 | then, only the fields which are involved in instruction extension */ | |
c906108c | 976 | struct upk_mips16 |
c5aa993b | 977 | { |
12f02c2a | 978 | CORE_ADDR offset; |
c5aa993b JM |
979 | unsigned int regx; /* Function in i8 type */ |
980 | unsigned int regy; | |
981 | }; | |
c906108c SS |
982 | |
983 | ||
12f02c2a AC |
984 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
985 | for the bits which make up the immediatate extension. */ | |
c906108c | 986 | |
12f02c2a AC |
987 | static CORE_ADDR |
988 | extended_offset (unsigned int extension) | |
c906108c | 989 | { |
12f02c2a | 990 | CORE_ADDR value; |
c5aa993b JM |
991 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
992 | value = value << 6; | |
993 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
994 | value = value << 5; | |
995 | value |= extension & 0x01f; /* extract 4:0 */ | |
996 | return value; | |
c906108c SS |
997 | } |
998 | ||
999 | /* Only call this function if you know that this is an extendable | |
1000 | instruction, It wont malfunction, but why make excess remote memory references? | |
1001 | If the immediate operands get sign extended or somthing, do it after | |
1002 | the extension is performed. | |
c5aa993b | 1003 | */ |
c906108c SS |
1004 | /* FIXME: Every one of these cases needs to worry about sign extension |
1005 | when the offset is to be used in relative addressing */ | |
1006 | ||
1007 | ||
12f02c2a | 1008 | static unsigned int |
c5aa993b | 1009 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1010 | { |
c5aa993b JM |
1011 | char buf[8]; |
1012 | pc &= 0xfffffffe; /* clear the low order bit */ | |
1013 | target_read_memory (pc, buf, 2); | |
1014 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1015 | } |
1016 | ||
1017 | static void | |
c5aa993b | 1018 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1019 | unsigned int extension, |
1020 | unsigned int inst, | |
1021 | enum mips16_inst_fmts insn_format, | |
c5aa993b | 1022 | struct upk_mips16 *upk) |
c906108c | 1023 | { |
12f02c2a AC |
1024 | CORE_ADDR offset; |
1025 | int regx; | |
1026 | int regy; | |
1027 | switch (insn_format) | |
c906108c | 1028 | { |
c5aa993b | 1029 | case itype: |
c906108c | 1030 | { |
12f02c2a AC |
1031 | CORE_ADDR value; |
1032 | if (extension) | |
c5aa993b JM |
1033 | { |
1034 | value = extended_offset (extension); | |
1035 | value = value << 11; /* rom for the original value */ | |
12f02c2a | 1036 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1037 | } |
1038 | else | |
c5aa993b | 1039 | { |
12f02c2a | 1040 | value = inst & 0x7ff; |
c5aa993b | 1041 | /* FIXME : Consider sign extension */ |
c906108c | 1042 | } |
12f02c2a AC |
1043 | offset = value; |
1044 | regx = -1; | |
1045 | regy = -1; | |
c906108c | 1046 | } |
c5aa993b JM |
1047 | break; |
1048 | case ritype: | |
1049 | case i8type: | |
1050 | { /* A register identifier and an offset */ | |
c906108c SS |
1051 | /* Most of the fields are the same as I type but the |
1052 | immediate value is of a different length */ | |
12f02c2a AC |
1053 | CORE_ADDR value; |
1054 | if (extension) | |
c906108c | 1055 | { |
c5aa993b JM |
1056 | value = extended_offset (extension); |
1057 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1058 | value |= inst & 0xff; /* eleven bits from instruction */ |
1059 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1060 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1061 | { | |
1062 | value &= ~0x3fff; /* remove the sign bit */ | |
1063 | value = -value; | |
c906108c SS |
1064 | } |
1065 | } | |
c5aa993b JM |
1066 | else |
1067 | { | |
12f02c2a AC |
1068 | value = inst & 0xff; /* 8 bits */ |
1069 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1070 | /* FIXME: Do sign extension , this format needs it */ |
1071 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1072 | { | |
1073 | value &= 0xef; /* remove the sign bit */ | |
1074 | value = -value; | |
1075 | } | |
c5aa993b | 1076 | } |
12f02c2a AC |
1077 | offset = value; |
1078 | regy = -1; | |
c5aa993b | 1079 | break; |
c906108c | 1080 | } |
c5aa993b | 1081 | case jalxtype: |
c906108c | 1082 | { |
c5aa993b | 1083 | unsigned long value; |
12f02c2a AC |
1084 | unsigned int nexthalf; |
1085 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1086 | value = value << 16; |
1087 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1088 | value |= nexthalf; | |
12f02c2a AC |
1089 | offset = value; |
1090 | regx = -1; | |
1091 | regy = -1; | |
c5aa993b | 1092 | break; |
c906108c SS |
1093 | } |
1094 | default: | |
8e65ff28 AC |
1095 | internal_error (__FILE__, __LINE__, |
1096 | "bad switch"); | |
c906108c | 1097 | } |
12f02c2a AC |
1098 | upk->offset = offset; |
1099 | upk->regx = regx; | |
1100 | upk->regy = regy; | |
c906108c SS |
1101 | } |
1102 | ||
1103 | ||
c5aa993b JM |
1104 | static CORE_ADDR |
1105 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1106 | { |
c5aa993b | 1107 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1108 | } |
1109 | ||
12f02c2a AC |
1110 | static CORE_ADDR |
1111 | extended_mips16_next_pc (CORE_ADDR pc, | |
1112 | unsigned int extension, | |
1113 | unsigned int insn) | |
c906108c | 1114 | { |
12f02c2a AC |
1115 | int op = (insn >> 11); |
1116 | switch (op) | |
c906108c | 1117 | { |
12f02c2a AC |
1118 | case 2: /* Branch */ |
1119 | { | |
1120 | CORE_ADDR offset; | |
1121 | struct upk_mips16 upk; | |
1122 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1123 | offset = upk.offset; | |
1124 | if (offset & 0x800) | |
1125 | { | |
1126 | offset &= 0xeff; | |
1127 | offset = -offset; | |
1128 | } | |
1129 | pc += (offset << 1) + 2; | |
1130 | break; | |
1131 | } | |
1132 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ | |
1133 | { | |
1134 | struct upk_mips16 upk; | |
1135 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1136 | pc = add_offset_16 (pc, upk.offset); | |
1137 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1138 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1139 | else | |
1140 | pc |= 0x01; | |
1141 | break; | |
1142 | } | |
1143 | case 4: /* beqz */ | |
1144 | { | |
1145 | struct upk_mips16 upk; | |
1146 | int reg; | |
1147 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1148 | reg = read_signed_register (upk.regx); | |
1149 | if (reg == 0) | |
1150 | pc += (upk.offset << 1) + 2; | |
1151 | else | |
1152 | pc += 2; | |
1153 | break; | |
1154 | } | |
1155 | case 5: /* bnez */ | |
1156 | { | |
1157 | struct upk_mips16 upk; | |
1158 | int reg; | |
1159 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1160 | reg = read_signed_register (upk.regx); | |
1161 | if (reg != 0) | |
1162 | pc += (upk.offset << 1) + 2; | |
1163 | else | |
1164 | pc += 2; | |
1165 | break; | |
1166 | } | |
1167 | case 12: /* I8 Formats btez btnez */ | |
1168 | { | |
1169 | struct upk_mips16 upk; | |
1170 | int reg; | |
1171 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1172 | /* upk.regx contains the opcode */ | |
1173 | reg = read_signed_register (24); /* Test register is 24 */ | |
1174 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1175 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1176 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1177 | pc += (upk.offset << 1) + 2; | |
1178 | else | |
1179 | pc += 2; | |
1180 | break; | |
1181 | } | |
1182 | case 29: /* RR Formats JR, JALR, JALR-RA */ | |
1183 | { | |
1184 | struct upk_mips16 upk; | |
1185 | /* upk.fmt = rrtype; */ | |
1186 | op = insn & 0x1f; | |
1187 | if (op == 0) | |
c5aa993b | 1188 | { |
12f02c2a AC |
1189 | int reg; |
1190 | upk.regx = (insn >> 8) & 0x07; | |
1191 | upk.regy = (insn >> 5) & 0x07; | |
1192 | switch (upk.regy) | |
c5aa993b | 1193 | { |
12f02c2a AC |
1194 | case 0: |
1195 | reg = upk.regx; | |
1196 | break; | |
1197 | case 1: | |
1198 | reg = 31; | |
1199 | break; /* Function return instruction */ | |
1200 | case 2: | |
1201 | reg = upk.regx; | |
1202 | break; | |
1203 | default: | |
1204 | reg = 31; | |
1205 | break; /* BOGUS Guess */ | |
c906108c | 1206 | } |
12f02c2a | 1207 | pc = read_signed_register (reg); |
c906108c | 1208 | } |
12f02c2a | 1209 | else |
c5aa993b | 1210 | pc += 2; |
12f02c2a AC |
1211 | break; |
1212 | } | |
1213 | case 30: | |
1214 | /* This is an instruction extension. Fetch the real instruction | |
1215 | (which follows the extension) and decode things based on | |
1216 | that. */ | |
1217 | { | |
1218 | pc += 2; | |
1219 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1220 | break; | |
1221 | } | |
1222 | default: | |
1223 | { | |
1224 | pc += 2; | |
1225 | break; | |
1226 | } | |
c906108c | 1227 | } |
c5aa993b | 1228 | return pc; |
12f02c2a | 1229 | } |
c906108c | 1230 | |
12f02c2a AC |
1231 | CORE_ADDR |
1232 | mips16_next_pc (CORE_ADDR pc) | |
1233 | { | |
1234 | unsigned int insn = fetch_mips_16 (pc); | |
1235 | return extended_mips16_next_pc (pc, 0, insn); | |
1236 | } | |
1237 | ||
1238 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1239 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1240 | It works by decoding the current instruction and predicting where a |
1241 | branch will go. This isnt hard because all the data is available. | |
1242 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1243 | CORE_ADDR |
1244 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1245 | { |
c5aa993b JM |
1246 | if (pc & 0x01) |
1247 | return mips16_next_pc (pc); | |
1248 | else | |
1249 | return mips32_next_pc (pc); | |
12f02c2a | 1250 | } |
c906108c SS |
1251 | |
1252 | /* Guaranteed to set fci->saved_regs to some values (it never leaves it | |
ffabd70d KB |
1253 | NULL). |
1254 | ||
1255 | Note: kevinb/2002-08-09: The only caller of this function is (and | |
1256 | should remain) mips_frame_init_saved_regs(). In fact, | |
1257 | aside from calling mips_find_saved_regs(), mips_frame_init_saved_regs() | |
1258 | does nothing more than set frame->saved_regs[SP_REGNUM]. These two | |
1259 | functions should really be combined and now that there is only one | |
1260 | caller, it should be straightforward. (Watch out for multiple returns | |
c4ac3e63 | 1261 | though.) */ |
c906108c | 1262 | |
d28e01f4 | 1263 | static void |
acdb74a0 | 1264 | mips_find_saved_regs (struct frame_info *fci) |
c906108c SS |
1265 | { |
1266 | int ireg; | |
1267 | CORE_ADDR reg_position; | |
1268 | /* r0 bit means kernel trap */ | |
1269 | int kernel_trap; | |
1270 | /* What registers have been saved? Bitmasks. */ | |
1271 | unsigned long gen_mask, float_mask; | |
1272 | mips_extra_func_info_t proc_desc; | |
1273 | t_inst inst; | |
1274 | ||
1275 | frame_saved_regs_zalloc (fci); | |
1276 | ||
1277 | /* If it is the frame for sigtramp, the saved registers are located | |
1278 | in a sigcontext structure somewhere on the stack. | |
1279 | If the stack layout for sigtramp changes we might have to change these | |
1280 | constants and the companion fixup_sigtramp in mdebugread.c */ | |
1281 | #ifndef SIGFRAME_BASE | |
1282 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes | |
1283 | above the sigtramp frame. */ | |
1284 | #define SIGFRAME_BASE MIPS_REGSIZE | |
1285 | /* FIXME! Are these correct?? */ | |
1286 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE) | |
1287 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE) | |
1288 | #define SIGFRAME_FPREGSAVE_OFF \ | |
1289 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE) | |
1290 | #endif | |
1291 | #ifndef SIGFRAME_REG_SIZE | |
1292 | /* FIXME! Is this correct?? */ | |
1293 | #define SIGFRAME_REG_SIZE MIPS_REGSIZE | |
1294 | #endif | |
1295 | if (fci->signal_handler_caller) | |
1296 | { | |
1297 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1298 | { | |
c5aa993b JM |
1299 | reg_position = fci->frame + SIGFRAME_REGSAVE_OFF |
1300 | + ireg * SIGFRAME_REG_SIZE; | |
1301 | fci->saved_regs[ireg] = reg_position; | |
c906108c SS |
1302 | } |
1303 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) | |
1304 | { | |
c5aa993b JM |
1305 | reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF |
1306 | + ireg * SIGFRAME_REG_SIZE; | |
1307 | fci->saved_regs[FP0_REGNUM + ireg] = reg_position; | |
c906108c SS |
1308 | } |
1309 | fci->saved_regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF; | |
1310 | return; | |
1311 | } | |
1312 | ||
cce74817 | 1313 | proc_desc = fci->extra_info->proc_desc; |
c906108c SS |
1314 | if (proc_desc == NULL) |
1315 | /* I'm not sure how/whether this can happen. Normally when we can't | |
1316 | find a proc_desc, we "synthesize" one using heuristic_proc_desc | |
1317 | and set the saved_regs right away. */ | |
1318 | return; | |
1319 | ||
c5aa993b JM |
1320 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; |
1321 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1322 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
c906108c | 1323 | |
c5aa993b JM |
1324 | if ( /* In any frame other than the innermost or a frame interrupted by |
1325 | a signal, we assume that all registers have been saved. | |
1326 | This assumes that all register saves in a function happen before | |
1327 | the first function call. */ | |
1328 | (fci->next == NULL || fci->next->signal_handler_caller) | |
c906108c | 1329 | |
c5aa993b JM |
1330 | /* In a dummy frame we know exactly where things are saved. */ |
1331 | && !PROC_DESC_IS_DUMMY (proc_desc) | |
c906108c | 1332 | |
c5aa993b JM |
1333 | /* Don't bother unless we are inside a function prologue. Outside the |
1334 | prologue, we know where everything is. */ | |
c906108c | 1335 | |
c5aa993b | 1336 | && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc)) |
c906108c | 1337 | |
c5aa993b JM |
1338 | /* Not sure exactly what kernel_trap means, but if it means |
1339 | the kernel saves the registers without a prologue doing it, | |
1340 | we better not examine the prologue to see whether registers | |
1341 | have been saved yet. */ | |
1342 | && !kernel_trap) | |
c906108c SS |
1343 | { |
1344 | /* We need to figure out whether the registers that the proc_desc | |
c5aa993b | 1345 | claims are saved have been saved yet. */ |
c906108c SS |
1346 | |
1347 | CORE_ADDR addr; | |
1348 | ||
1349 | /* Bitmasks; set if we have found a save for the register. */ | |
1350 | unsigned long gen_save_found = 0; | |
1351 | unsigned long float_save_found = 0; | |
1352 | int instlen; | |
1353 | ||
1354 | /* If the address is odd, assume this is MIPS16 code. */ | |
1355 | addr = PROC_LOW_ADDR (proc_desc); | |
1356 | instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; | |
1357 | ||
1358 | /* Scan through this function's instructions preceding the current | |
1359 | PC, and look for those that save registers. */ | |
1360 | while (addr < fci->pc) | |
1361 | { | |
1362 | inst = mips_fetch_instruction (addr); | |
1363 | if (pc_is_mips16 (addr)) | |
1364 | mips16_decode_reg_save (inst, &gen_save_found); | |
1365 | else | |
1366 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); | |
1367 | addr += instlen; | |
1368 | } | |
1369 | gen_mask = gen_save_found; | |
1370 | float_mask = float_save_found; | |
1371 | } | |
1372 | ||
1373 | /* Fill in the offsets for the registers which gen_mask says | |
1374 | were saved. */ | |
1375 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
c5aa993b | 1376 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) |
c906108c SS |
1377 | if (gen_mask & 0x80000000) |
1378 | { | |
1379 | fci->saved_regs[ireg] = reg_position; | |
7a292a7a | 1380 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1381 | } |
1382 | ||
1383 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order | |
1384 | of that normally used by gcc. Therefore, we have to fetch the first | |
1385 | instruction of the function, and if it's an entry instruction that | |
1386 | saves $s0 or $s1, correct their saved addresses. */ | |
1387 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) | |
1388 | { | |
1389 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
c5aa993b | 1390 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
c906108c SS |
1391 | { |
1392 | int reg; | |
1393 | int sreg_count = (inst >> 6) & 3; | |
c5aa993b | 1394 | |
c906108c SS |
1395 | /* Check if the ra register was pushed on the stack. */ |
1396 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); | |
1397 | if (inst & 0x20) | |
7a292a7a | 1398 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1399 | |
1400 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
c5aa993b | 1401 | for (reg = 16; reg < sreg_count + 16; reg++) |
c906108c SS |
1402 | { |
1403 | fci->saved_regs[reg] = reg_position; | |
7a292a7a | 1404 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1405 | } |
1406 | } | |
1407 | } | |
1408 | ||
1409 | /* Fill in the offsets for the registers which float_mask says | |
1410 | were saved. */ | |
1411 | reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc); | |
1412 | ||
6acdf5c7 MS |
1413 | /* Apparently, the freg_offset gives the offset to the first 64 bit |
1414 | saved. | |
1415 | ||
1416 | When the ABI specifies 64 bit saved registers, the FREG_OFFSET | |
1417 | designates the first saved 64 bit register. | |
1418 | ||
1419 | When the ABI specifies 32 bit saved registers, the ``64 bit saved | |
1420 | DOUBLE'' consists of two adjacent 32 bit registers, Hence | |
1421 | FREG_OFFSET, designates the address of the lower register of the | |
1422 | register pair. Adjust the offset so that it designates the upper | |
1423 | register of the pair -- i.e., the address of the first saved 32 | |
1424 | bit register. */ | |
1425 | ||
1426 | if (MIPS_SAVED_REGSIZE == 4) | |
7a292a7a | 1427 | reg_position += MIPS_SAVED_REGSIZE; |
c906108c SS |
1428 | |
1429 | /* Fill in the offsets for the float registers which float_mask says | |
1430 | were saved. */ | |
c5aa993b | 1431 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) |
c906108c SS |
1432 | if (float_mask & 0x80000000) |
1433 | { | |
c5aa993b | 1434 | fci->saved_regs[FP0_REGNUM + ireg] = reg_position; |
7a292a7a | 1435 | reg_position -= MIPS_SAVED_REGSIZE; |
c906108c SS |
1436 | } |
1437 | ||
1438 | fci->saved_regs[PC_REGNUM] = fci->saved_regs[RA_REGNUM]; | |
1439 | } | |
1440 | ||
d28e01f4 KB |
1441 | /* Set up the 'saved_regs' array. This is a data structure containing |
1442 | the addresses on the stack where each register has been saved, for | |
1443 | each stack frame. Registers that have not been saved will have | |
1444 | zero here. The stack pointer register is special: rather than the | |
1445 | address where the stack register has been saved, saved_regs[SP_REGNUM] | |
1446 | will have the actual value of the previous frame's stack register. */ | |
1447 | ||
1448 | static void | |
1449 | mips_frame_init_saved_regs (struct frame_info *frame) | |
1450 | { | |
1451 | if (frame->saved_regs == NULL) | |
1452 | { | |
1453 | mips_find_saved_regs (frame); | |
1454 | } | |
1455 | frame->saved_regs[SP_REGNUM] = frame->frame; | |
1456 | } | |
1457 | ||
c906108c | 1458 | static CORE_ADDR |
acdb74a0 | 1459 | read_next_frame_reg (struct frame_info *fi, int regno) |
c906108c SS |
1460 | { |
1461 | for (; fi; fi = fi->next) | |
1462 | { | |
1463 | /* We have to get the saved sp from the sigcontext | |
c5aa993b | 1464 | if it is a signal handler frame. */ |
c906108c SS |
1465 | if (regno == SP_REGNUM && !fi->signal_handler_caller) |
1466 | return fi->frame; | |
1467 | else | |
1468 | { | |
1469 | if (fi->saved_regs == NULL) | |
ffabd70d | 1470 | FRAME_INIT_SAVED_REGS (fi); |
c906108c | 1471 | if (fi->saved_regs[regno]) |
2acceee2 | 1472 | return read_memory_integer (ADDR_BITS_REMOVE (fi->saved_regs[regno]), MIPS_SAVED_REGSIZE); |
c906108c SS |
1473 | } |
1474 | } | |
6c997a34 | 1475 | return read_signed_register (regno); |
c906108c SS |
1476 | } |
1477 | ||
1478 | /* mips_addr_bits_remove - remove useless address bits */ | |
1479 | ||
875e1767 | 1480 | static CORE_ADDR |
acdb74a0 | 1481 | mips_addr_bits_remove (CORE_ADDR addr) |
c906108c | 1482 | { |
5213ab06 AC |
1483 | if (GDB_TARGET_IS_MIPS64) |
1484 | { | |
4014092b | 1485 | if (mips_mask_address_p () && (addr >> 32 == (CORE_ADDR) 0xffffffff)) |
5213ab06 AC |
1486 | { |
1487 | /* This hack is a work-around for existing boards using | |
1488 | PMON, the simulator, and any other 64-bit targets that | |
1489 | doesn't have true 64-bit addressing. On these targets, | |
1490 | the upper 32 bits of addresses are ignored by the | |
1491 | hardware. Thus, the PC or SP are likely to have been | |
1492 | sign extended to all 1s by instruction sequences that | |
1493 | load 32-bit addresses. For example, a typical piece of | |
4014092b AC |
1494 | code that loads an address is this: |
1495 | lui $r2, <upper 16 bits> | |
1496 | ori $r2, <lower 16 bits> | |
1497 | But the lui sign-extends the value such that the upper 32 | |
1498 | bits may be all 1s. The workaround is simply to mask off | |
1499 | these bits. In the future, gcc may be changed to support | |
1500 | true 64-bit addressing, and this masking will have to be | |
1501 | disabled. */ | |
5213ab06 AC |
1502 | addr &= (CORE_ADDR) 0xffffffff; |
1503 | } | |
1504 | } | |
4014092b | 1505 | else if (mips_mask_address_p ()) |
5213ab06 | 1506 | { |
4014092b AC |
1507 | /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be |
1508 | masking off bits, instead, the actual target should be asking | |
1509 | for the address to be converted to a valid pointer. */ | |
5213ab06 AC |
1510 | /* Even when GDB is configured for some 32-bit targets |
1511 | (e.g. mips-elf), BFD is configured to handle 64-bit targets, | |
1512 | so CORE_ADDR is 64 bits. So we still have to mask off | |
1513 | useless bits from addresses. */ | |
c5aa993b | 1514 | addr &= (CORE_ADDR) 0xffffffff; |
c906108c | 1515 | } |
c906108c SS |
1516 | return addr; |
1517 | } | |
1518 | ||
9022177c DJ |
1519 | /* mips_software_single_step() is called just before we want to resume |
1520 | the inferior, if we want to single-step it but there is no hardware | |
75c9abc6 | 1521 | or kernel single-step support (MIPS on GNU/Linux for example). We find |
9022177c DJ |
1522 | the target of the coming instruction and breakpoint it. |
1523 | ||
1524 | single_step is also called just after the inferior stops. If we had | |
1525 | set up a simulated single-step, we undo our damage. */ | |
1526 | ||
1527 | void | |
1528 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
1529 | { | |
1530 | static CORE_ADDR next_pc; | |
1531 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
1532 | static binsn_quantum break_mem; | |
1533 | CORE_ADDR pc; | |
1534 | ||
1535 | if (insert_breakpoints_p) | |
1536 | { | |
1537 | pc = read_register (PC_REGNUM); | |
1538 | next_pc = mips_next_pc (pc); | |
1539 | ||
1540 | target_insert_breakpoint (next_pc, break_mem); | |
1541 | } | |
1542 | else | |
1543 | target_remove_breakpoint (next_pc, break_mem); | |
1544 | } | |
1545 | ||
10312cc4 | 1546 | static void |
acdb74a0 | 1547 | mips_init_frame_pc_first (int fromleaf, struct frame_info *prev) |
c906108c SS |
1548 | { |
1549 | CORE_ADDR pc, tmp; | |
1550 | ||
1551 | pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) : | |
c5aa993b | 1552 | prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ()); |
c906108c | 1553 | tmp = mips_skip_stub (pc); |
c5aa993b | 1554 | prev->pc = tmp ? tmp : pc; |
c906108c SS |
1555 | } |
1556 | ||
1557 | ||
1558 | CORE_ADDR | |
acdb74a0 | 1559 | mips_frame_saved_pc (struct frame_info *frame) |
c906108c SS |
1560 | { |
1561 | CORE_ADDR saved_pc; | |
cce74817 | 1562 | mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc; |
c906108c SS |
1563 | /* We have to get the saved pc from the sigcontext |
1564 | if it is a signal handler frame. */ | |
1565 | int pcreg = frame->signal_handler_caller ? PC_REGNUM | |
c5aa993b | 1566 | : (proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM); |
c906108c | 1567 | |
c5aa993b | 1568 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
7a292a7a | 1569 | saved_pc = read_memory_integer (frame->frame - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE); |
c906108c | 1570 | else |
7a292a7a | 1571 | saved_pc = read_next_frame_reg (frame, pcreg); |
c906108c SS |
1572 | |
1573 | return ADDR_BITS_REMOVE (saved_pc); | |
1574 | } | |
1575 | ||
1576 | static struct mips_extra_func_info temp_proc_desc; | |
cce74817 | 1577 | static CORE_ADDR temp_saved_regs[NUM_REGS]; |
c906108c SS |
1578 | |
1579 | /* Set a register's saved stack address in temp_saved_regs. If an address | |
1580 | has already been set for this register, do nothing; this way we will | |
1581 | only recognize the first save of a given register in a function prologue. | |
1582 | This is a helper function for mips{16,32}_heuristic_proc_desc. */ | |
1583 | ||
1584 | static void | |
acdb74a0 | 1585 | set_reg_offset (int regno, CORE_ADDR offset) |
c906108c | 1586 | { |
cce74817 JM |
1587 | if (temp_saved_regs[regno] == 0) |
1588 | temp_saved_regs[regno] = offset; | |
c906108c SS |
1589 | } |
1590 | ||
1591 | ||
1592 | /* Test whether the PC points to the return instruction at the | |
1593 | end of a function. */ | |
1594 | ||
c5aa993b | 1595 | static int |
acdb74a0 | 1596 | mips_about_to_return (CORE_ADDR pc) |
c906108c SS |
1597 | { |
1598 | if (pc_is_mips16 (pc)) | |
1599 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler | |
1600 | generates a "jr $ra"; other times it generates code to load | |
1601 | the return address from the stack to an accessible register (such | |
1602 | as $a3), then a "jr" using that register. This second case | |
1603 | is almost impossible to distinguish from an indirect jump | |
1604 | used for switch statements, so we don't even try. */ | |
1605 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
1606 | else | |
1607 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
1608 | } | |
1609 | ||
1610 | ||
1611 | /* This fencepost looks highly suspicious to me. Removing it also | |
1612 | seems suspicious as it could affect remote debugging across serial | |
1613 | lines. */ | |
1614 | ||
1615 | static CORE_ADDR | |
acdb74a0 | 1616 | heuristic_proc_start (CORE_ADDR pc) |
c906108c | 1617 | { |
c5aa993b JM |
1618 | CORE_ADDR start_pc; |
1619 | CORE_ADDR fence; | |
1620 | int instlen; | |
1621 | int seen_adjsp = 0; | |
c906108c | 1622 | |
c5aa993b JM |
1623 | pc = ADDR_BITS_REMOVE (pc); |
1624 | start_pc = pc; | |
1625 | fence = start_pc - heuristic_fence_post; | |
1626 | if (start_pc == 0) | |
1627 | return 0; | |
c906108c | 1628 | |
c5aa993b JM |
1629 | if (heuristic_fence_post == UINT_MAX |
1630 | || fence < VM_MIN_ADDRESS) | |
1631 | fence = VM_MIN_ADDRESS; | |
c906108c | 1632 | |
c5aa993b | 1633 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
c906108c | 1634 | |
c5aa993b JM |
1635 | /* search back for previous return */ |
1636 | for (start_pc -= instlen;; start_pc -= instlen) | |
1637 | if (start_pc < fence) | |
1638 | { | |
1639 | /* It's not clear to me why we reach this point when | |
1640 | stop_soon_quietly, but with this test, at least we | |
1641 | don't print out warnings for every child forked (eg, on | |
1642 | decstation). 22apr93 rich@cygnus.com. */ | |
1643 | if (!stop_soon_quietly) | |
c906108c | 1644 | { |
c5aa993b JM |
1645 | static int blurb_printed = 0; |
1646 | ||
1647 | warning ("Warning: GDB can't find the start of the function at 0x%s.", | |
1648 | paddr_nz (pc)); | |
1649 | ||
1650 | if (!blurb_printed) | |
c906108c | 1651 | { |
c5aa993b JM |
1652 | /* This actually happens frequently in embedded |
1653 | development, when you first connect to a board | |
1654 | and your stack pointer and pc are nowhere in | |
1655 | particular. This message needs to give people | |
1656 | in that situation enough information to | |
1657 | determine that it's no big deal. */ | |
1658 | printf_filtered ("\n\ | |
cd0fc7c3 SS |
1659 | GDB is unable to find the start of the function at 0x%s\n\ |
1660 | and thus can't determine the size of that function's stack frame.\n\ | |
1661 | This means that GDB may be unable to access that stack frame, or\n\ | |
1662 | the frames below it.\n\ | |
1663 | This problem is most likely caused by an invalid program counter or\n\ | |
1664 | stack pointer.\n\ | |
1665 | However, if you think GDB should simply search farther back\n\ | |
1666 | from 0x%s for code which looks like the beginning of a\n\ | |
1667 | function, you can increase the range of the search using the `set\n\ | |
1668 | heuristic-fence-post' command.\n", | |
c5aa993b JM |
1669 | paddr_nz (pc), paddr_nz (pc)); |
1670 | blurb_printed = 1; | |
c906108c | 1671 | } |
c906108c SS |
1672 | } |
1673 | ||
c5aa993b JM |
1674 | return 0; |
1675 | } | |
1676 | else if (pc_is_mips16 (start_pc)) | |
1677 | { | |
1678 | unsigned short inst; | |
1679 | ||
1680 | /* On MIPS16, any one of the following is likely to be the | |
1681 | start of a function: | |
1682 | entry | |
1683 | addiu sp,-n | |
1684 | daddiu sp,-n | |
1685 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
1686 | inst = mips_fetch_instruction (start_pc); | |
1687 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
1688 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
1689 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
1690 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
1691 | break; | |
1692 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
1693 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1694 | seen_adjsp = 1; | |
1695 | else | |
1696 | seen_adjsp = 0; | |
1697 | } | |
1698 | else if (mips_about_to_return (start_pc)) | |
1699 | { | |
1700 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ | |
1701 | break; | |
1702 | } | |
1703 | ||
c5aa993b | 1704 | return start_pc; |
c906108c SS |
1705 | } |
1706 | ||
1707 | /* Fetch the immediate value from a MIPS16 instruction. | |
1708 | If the previous instruction was an EXTEND, use it to extend | |
1709 | the upper bits of the immediate value. This is a helper function | |
1710 | for mips16_heuristic_proc_desc. */ | |
1711 | ||
1712 | static int | |
acdb74a0 AC |
1713 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ |
1714 | unsigned short inst, /* current instruction */ | |
1715 | int nbits, /* number of bits in imm field */ | |
1716 | int scale, /* scale factor to be applied to imm */ | |
1717 | int is_signed) /* is the imm field signed? */ | |
c906108c SS |
1718 | { |
1719 | int offset; | |
1720 | ||
1721 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ | |
1722 | { | |
1723 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
c5aa993b | 1724 | if (offset & 0x8000) /* check for negative extend */ |
c906108c SS |
1725 | offset = 0 - (0x10000 - (offset & 0xffff)); |
1726 | return offset | (inst & 0x1f); | |
1727 | } | |
1728 | else | |
1729 | { | |
1730 | int max_imm = 1 << nbits; | |
1731 | int mask = max_imm - 1; | |
1732 | int sign_bit = max_imm >> 1; | |
1733 | ||
1734 | offset = inst & mask; | |
1735 | if (is_signed && (offset & sign_bit)) | |
1736 | offset = 0 - (max_imm - offset); | |
1737 | return offset * scale; | |
1738 | } | |
1739 | } | |
1740 | ||
1741 | ||
1742 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction | |
1743 | stream from start_pc to limit_pc. */ | |
1744 | ||
1745 | static void | |
acdb74a0 AC |
1746 | mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1747 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
1748 | { |
1749 | CORE_ADDR cur_pc; | |
1750 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1751 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1752 | unsigned inst = 0; /* current instruction */ | |
1753 | unsigned entry_inst = 0; /* the entry instruction */ | |
1754 | int reg, offset; | |
1755 | ||
c5aa993b JM |
1756 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
1757 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ | |
c906108c SS |
1758 | |
1759 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) | |
1760 | { | |
1761 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1762 | the immediate offset extension from it in mips16_get_imm. */ | |
1763 | prev_inst = inst; | |
1764 | ||
1765 | /* Fetch and decode the instruction. */ | |
1766 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
c5aa993b | 1767 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
c906108c SS |
1768 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
1769 | { | |
1770 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
c5aa993b JM |
1771 | if (offset < 0) /* negative stack adjustment? */ |
1772 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; | |
c906108c SS |
1773 | else |
1774 | /* Exit loop if a positive stack adjustment is found, which | |
1775 | usually means that the stack cleanup code in the function | |
1776 | epilogue is reached. */ | |
1777 | break; | |
1778 | } | |
1779 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1780 | { | |
1781 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1782 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
c5aa993b | 1783 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
c906108c SS |
1784 | set_reg_offset (reg, sp + offset); |
1785 | } | |
1786 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1787 | { | |
1788 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1789 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1790 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
c906108c SS |
1791 | set_reg_offset (reg, sp + offset); |
1792 | } | |
1793 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1794 | { | |
1795 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
c5aa993b | 1796 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
c906108c SS |
1797 | set_reg_offset (RA_REGNUM, sp + offset); |
1798 | } | |
1799 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1800 | { | |
1801 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
c5aa993b | 1802 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
c906108c SS |
1803 | set_reg_offset (RA_REGNUM, sp + offset); |
1804 | } | |
c5aa993b | 1805 | else if (inst == 0x673d) /* move $s1, $sp */ |
c906108c SS |
1806 | { |
1807 | frame_addr = sp; | |
1808 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
1809 | } | |
1810 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1811 | { | |
1812 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1813 | frame_addr = sp + offset; | |
1814 | PROC_FRAME_REG (&temp_proc_desc) = 17; | |
1815 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; | |
1816 | } | |
1817 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1818 | { | |
1819 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1820 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1821 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1822 | set_reg_offset (reg, frame_addr + offset); |
1823 | } | |
1824 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1825 | { | |
1826 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1827 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
c5aa993b | 1828 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1829 | set_reg_offset (reg, frame_addr + offset); |
1830 | } | |
c5aa993b JM |
1831 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
1832 | entry_inst = inst; /* save for later processing */ | |
c906108c | 1833 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
c5aa993b | 1834 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
c906108c SS |
1835 | } |
1836 | ||
c5aa993b JM |
1837 | /* The entry instruction is typically the first instruction in a function, |
1838 | and it stores registers at offsets relative to the value of the old SP | |
1839 | (before the prologue). But the value of the sp parameter to this | |
1840 | function is the new SP (after the prologue has been executed). So we | |
1841 | can't calculate those offsets until we've seen the entire prologue, | |
1842 | and can calculate what the old SP must have been. */ | |
1843 | if (entry_inst != 0) | |
1844 | { | |
1845 | int areg_count = (entry_inst >> 8) & 7; | |
1846 | int sreg_count = (entry_inst >> 6) & 3; | |
c906108c | 1847 | |
c5aa993b JM |
1848 | /* The entry instruction always subtracts 32 from the SP. */ |
1849 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; | |
c906108c | 1850 | |
c5aa993b JM |
1851 | /* Now we can calculate what the SP must have been at the |
1852 | start of the function prologue. */ | |
1853 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); | |
c906108c | 1854 | |
c5aa993b JM |
1855 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
1856 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1857 | { | |
1858 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
1859 | set_reg_offset (reg, sp + offset); | |
1860 | offset += MIPS_SAVED_REGSIZE; | |
1861 | } | |
c906108c | 1862 | |
c5aa993b JM |
1863 | /* Check if the ra register was pushed on the stack. */ |
1864 | offset = -4; | |
1865 | if (entry_inst & 0x20) | |
1866 | { | |
1867 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; | |
1868 | set_reg_offset (RA_REGNUM, sp + offset); | |
1869 | offset -= MIPS_SAVED_REGSIZE; | |
1870 | } | |
c906108c | 1871 | |
c5aa993b JM |
1872 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
1873 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1874 | { | |
1875 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; | |
1876 | set_reg_offset (reg, sp + offset); | |
1877 | offset -= MIPS_SAVED_REGSIZE; | |
1878 | } | |
1879 | } | |
c906108c SS |
1880 | } |
1881 | ||
1882 | static void | |
fba45db2 KB |
1883 | mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1884 | struct frame_info *next_frame, CORE_ADDR sp) | |
c906108c SS |
1885 | { |
1886 | CORE_ADDR cur_pc; | |
c5aa993b | 1887 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
c906108c | 1888 | restart: |
cce74817 | 1889 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c5aa993b | 1890 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
c906108c SS |
1891 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
1892 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) | |
1893 | { | |
1894 | unsigned long inst, high_word, low_word; | |
1895 | int reg; | |
1896 | ||
1897 | /* Fetch the instruction. */ | |
1898 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
1899 | ||
1900 | /* Save some code by pre-extracting some useful fields. */ | |
1901 | high_word = (inst >> 16) & 0xffff; | |
1902 | low_word = inst & 0xffff; | |
1903 | reg = high_word & 0x1f; | |
1904 | ||
c5aa993b | 1905 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
c906108c SS |
1906 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
1907 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1908 | { | |
1909 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
c5aa993b | 1910 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
c906108c SS |
1911 | else |
1912 | /* Exit loop if a positive stack adjustment is found, which | |
1913 | usually means that the stack cleanup code in the function | |
1914 | epilogue is reached. */ | |
1915 | break; | |
1916 | } | |
1917 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
1918 | { | |
c5aa993b | 1919 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1920 | set_reg_offset (reg, sp + low_word); |
1921 | } | |
1922 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
1923 | { | |
1924 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, | |
1925 | but the register size used is only 32 bits. Make the address | |
1926 | for the saved register point to the lower 32 bits. */ | |
c5aa993b | 1927 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1928 | set_reg_offset (reg, sp + low_word + 8 - MIPS_REGSIZE); |
1929 | } | |
c5aa993b | 1930 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
c906108c SS |
1931 | { |
1932 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
c5aa993b JM |
1933 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
1934 | frame_addr = sp + low_word; | |
c906108c SS |
1935 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) |
1936 | { | |
1937 | unsigned alloca_adjust; | |
1938 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
c5aa993b JM |
1939 | frame_addr = read_next_frame_reg (next_frame, 30); |
1940 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); | |
c906108c SS |
1941 | if (alloca_adjust > 0) |
1942 | { | |
1943 | /* FP > SP + frame_size. This may be because | |
1944 | * of an alloca or somethings similar. | |
1945 | * Fix sp to "pre-alloca" value, and try again. | |
1946 | */ | |
1947 | sp += alloca_adjust; | |
1948 | goto restart; | |
1949 | } | |
1950 | } | |
1951 | } | |
c5aa993b JM |
1952 | /* move $30,$sp. With different versions of gas this will be either |
1953 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
1954 | Accept any one of these. */ | |
c906108c SS |
1955 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
1956 | { | |
1957 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
1958 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) | |
1959 | { | |
1960 | unsigned alloca_adjust; | |
1961 | PROC_FRAME_REG (&temp_proc_desc) = 30; | |
c5aa993b JM |
1962 | frame_addr = read_next_frame_reg (next_frame, 30); |
1963 | alloca_adjust = (unsigned) (frame_addr - sp); | |
c906108c SS |
1964 | if (alloca_adjust > 0) |
1965 | { | |
1966 | /* FP > SP + frame_size. This may be because | |
1967 | * of an alloca or somethings similar. | |
1968 | * Fix sp to "pre-alloca" value, and try again. | |
1969 | */ | |
1970 | sp += alloca_adjust; | |
1971 | goto restart; | |
1972 | } | |
1973 | } | |
1974 | } | |
c5aa993b | 1975 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
c906108c | 1976 | { |
c5aa993b | 1977 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
c906108c SS |
1978 | set_reg_offset (reg, frame_addr + low_word); |
1979 | } | |
1980 | } | |
1981 | } | |
1982 | ||
1983 | static mips_extra_func_info_t | |
acdb74a0 | 1984 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
479412cd | 1985 | struct frame_info *next_frame, int cur_frame) |
c906108c | 1986 | { |
479412cd DJ |
1987 | CORE_ADDR sp; |
1988 | ||
1989 | if (cur_frame) | |
1990 | sp = read_next_frame_reg (next_frame, SP_REGNUM); | |
1991 | else | |
1992 | sp = 0; | |
c906108c | 1993 | |
c5aa993b JM |
1994 | if (start_pc == 0) |
1995 | return NULL; | |
1996 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); | |
cce74817 | 1997 | memset (&temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
1998 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
1999 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; | |
2000 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; | |
2001 | ||
2002 | if (start_pc + 200 < limit_pc) | |
2003 | limit_pc = start_pc + 200; | |
2004 | if (pc_is_mips16 (start_pc)) | |
2005 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2006 | else | |
2007 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); | |
2008 | return &temp_proc_desc; | |
2009 | } | |
2010 | ||
6c0d6680 DJ |
2011 | struct mips_objfile_private |
2012 | { | |
2013 | bfd_size_type size; | |
2014 | char *contents; | |
2015 | }; | |
2016 | ||
2017 | /* Global used to communicate between non_heuristic_proc_desc and | |
2018 | compare_pdr_entries within qsort (). */ | |
2019 | static bfd *the_bfd; | |
2020 | ||
2021 | static int | |
2022 | compare_pdr_entries (const void *a, const void *b) | |
2023 | { | |
2024 | CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); | |
2025 | CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); | |
2026 | ||
2027 | if (lhs < rhs) | |
2028 | return -1; | |
2029 | else if (lhs == rhs) | |
2030 | return 0; | |
2031 | else | |
2032 | return 1; | |
2033 | } | |
2034 | ||
c906108c | 2035 | static mips_extra_func_info_t |
acdb74a0 | 2036 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
2037 | { |
2038 | CORE_ADDR startaddr; | |
2039 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 2040 | struct block *b = block_for_pc (pc); |
c906108c | 2041 | struct symbol *sym; |
6c0d6680 DJ |
2042 | struct obj_section *sec; |
2043 | struct mips_objfile_private *priv; | |
2044 | ||
2045 | if (PC_IN_CALL_DUMMY (pc, 0, 0)) | |
2046 | return NULL; | |
c906108c SS |
2047 | |
2048 | find_pc_partial_function (pc, NULL, &startaddr, NULL); | |
2049 | if (addrptr) | |
2050 | *addrptr = startaddr; | |
6c0d6680 DJ |
2051 | |
2052 | priv = NULL; | |
2053 | ||
2054 | sec = find_pc_section (pc); | |
2055 | if (sec != NULL) | |
c906108c | 2056 | { |
6c0d6680 DJ |
2057 | priv = (struct mips_objfile_private *) sec->objfile->obj_private; |
2058 | ||
2059 | /* Search the ".pdr" section generated by GAS. This includes most of | |
2060 | the information normally found in ECOFF PDRs. */ | |
2061 | ||
2062 | the_bfd = sec->objfile->obfd; | |
2063 | if (priv == NULL | |
2064 | && (the_bfd->format == bfd_object | |
2065 | && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour | |
2066 | && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) | |
2067 | { | |
2068 | /* Right now GAS only outputs the address as a four-byte sequence. | |
2069 | This means that we should not bother with this method on 64-bit | |
2070 | targets (until that is fixed). */ | |
2071 | ||
2072 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2073 | sizeof (struct mips_objfile_private)); | |
2074 | priv->size = 0; | |
2075 | sec->objfile->obj_private = priv; | |
2076 | } | |
2077 | else if (priv == NULL) | |
2078 | { | |
2079 | asection *bfdsec; | |
2080 | ||
2081 | priv = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2082 | sizeof (struct mips_objfile_private)); | |
2083 | ||
2084 | bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); | |
2085 | if (bfdsec != NULL) | |
2086 | { | |
2087 | priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); | |
2088 | priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack, | |
2089 | priv->size); | |
2090 | bfd_get_section_contents (sec->objfile->obfd, bfdsec, | |
2091 | priv->contents, 0, priv->size); | |
2092 | ||
2093 | /* In general, the .pdr section is sorted. However, in the | |
2094 | presence of multiple code sections (and other corner cases) | |
2095 | it can become unsorted. Sort it so that we can use a faster | |
2096 | binary search. */ | |
2097 | qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries); | |
2098 | } | |
2099 | else | |
2100 | priv->size = 0; | |
2101 | ||
2102 | sec->objfile->obj_private = priv; | |
2103 | } | |
2104 | the_bfd = NULL; | |
2105 | ||
2106 | if (priv->size != 0) | |
2107 | { | |
2108 | int low, mid, high; | |
2109 | char *ptr; | |
2110 | ||
2111 | low = 0; | |
2112 | high = priv->size / 32; | |
2113 | ||
2114 | do | |
2115 | { | |
2116 | CORE_ADDR pdr_pc; | |
2117 | ||
2118 | mid = (low + high) / 2; | |
2119 | ||
2120 | ptr = priv->contents + mid * 32; | |
2121 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2122 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2123 | SECT_OFF_TEXT (sec->objfile)); | |
2124 | if (pdr_pc == startaddr) | |
2125 | break; | |
2126 | if (pdr_pc > startaddr) | |
2127 | high = mid; | |
2128 | else | |
2129 | low = mid + 1; | |
2130 | } | |
2131 | while (low != high); | |
2132 | ||
2133 | if (low != high) | |
2134 | { | |
2135 | struct symbol *sym = find_pc_function (pc); | |
2136 | ||
2137 | /* Fill in what we need of the proc_desc. */ | |
2138 | proc_desc = (mips_extra_func_info_t) | |
2139 | obstack_alloc (&sec->objfile->psymbol_obstack, | |
2140 | sizeof (struct mips_extra_func_info)); | |
2141 | PROC_LOW_ADDR (proc_desc) = startaddr; | |
2142 | ||
2143 | /* Only used for dummy frames. */ | |
2144 | PROC_HIGH_ADDR (proc_desc) = 0; | |
2145 | ||
2146 | PROC_FRAME_OFFSET (proc_desc) | |
2147 | = bfd_get_32 (sec->objfile->obfd, ptr + 20); | |
2148 | PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2149 | ptr + 24); | |
2150 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
2151 | PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2152 | ptr + 4); | |
2153 | PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2154 | ptr + 12); | |
2155 | PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2156 | ptr + 8); | |
2157 | PROC_FREG_OFFSET (proc_desc) | |
2158 | = bfd_get_32 (sec->objfile->obfd, ptr + 16); | |
2159 | PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2160 | ptr + 28); | |
2161 | proc_desc->pdr.isym = (long) sym; | |
2162 | ||
2163 | return proc_desc; | |
2164 | } | |
2165 | } | |
c906108c SS |
2166 | } |
2167 | ||
6c0d6680 DJ |
2168 | if (b == NULL) |
2169 | return NULL; | |
2170 | ||
2171 | if (startaddr > BLOCK_START (b)) | |
2172 | { | |
2173 | /* This is the "pathological" case referred to in a comment in | |
2174 | print_frame_info. It might be better to move this check into | |
2175 | symbol reading. */ | |
2176 | return NULL; | |
2177 | } | |
2178 | ||
2179 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL); | |
2180 | ||
c906108c SS |
2181 | /* If we never found a PDR for this function in symbol reading, then |
2182 | examine prologues to find the information. */ | |
2183 | if (sym) | |
2184 | { | |
2185 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
2186 | if (PROC_FRAME_REG (proc_desc) == -1) | |
2187 | return NULL; | |
2188 | else | |
2189 | return proc_desc; | |
2190 | } | |
2191 | else | |
2192 | return NULL; | |
2193 | } | |
2194 | ||
2195 | ||
2196 | static mips_extra_func_info_t | |
479412cd | 2197 | find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame) |
c906108c SS |
2198 | { |
2199 | mips_extra_func_info_t proc_desc; | |
2200 | CORE_ADDR startaddr; | |
2201 | ||
2202 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
2203 | ||
2204 | if (proc_desc) | |
2205 | { | |
2206 | /* IF this is the topmost frame AND | |
2207 | * (this proc does not have debugging information OR | |
2208 | * the PC is in the procedure prologue) | |
2209 | * THEN create a "heuristic" proc_desc (by analyzing | |
2210 | * the actual code) to replace the "official" proc_desc. | |
2211 | */ | |
2212 | if (next_frame == NULL) | |
2213 | { | |
2214 | struct symtab_and_line val; | |
2215 | struct symbol *proc_symbol = | |
c86b5b38 | 2216 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); |
c906108c SS |
2217 | |
2218 | if (proc_symbol) | |
2219 | { | |
2220 | val = find_pc_line (BLOCK_START | |
c5aa993b | 2221 | (SYMBOL_BLOCK_VALUE (proc_symbol)), |
c906108c SS |
2222 | 0); |
2223 | val.pc = val.end ? val.end : pc; | |
2224 | } | |
2225 | if (!proc_symbol || pc < val.pc) | |
2226 | { | |
2227 | mips_extra_func_info_t found_heuristic = | |
c86b5b38 MS |
2228 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
2229 | pc, next_frame, cur_frame); | |
c906108c SS |
2230 | if (found_heuristic) |
2231 | proc_desc = found_heuristic; | |
2232 | } | |
2233 | } | |
2234 | } | |
2235 | else | |
2236 | { | |
2237 | /* Is linked_proc_desc_table really necessary? It only seems to be used | |
c5aa993b JM |
2238 | by procedure call dummys. However, the procedures being called ought |
2239 | to have their own proc_descs, and even if they don't, | |
2240 | heuristic_proc_desc knows how to create them! */ | |
c906108c SS |
2241 | |
2242 | register struct linked_proc_info *link; | |
2243 | ||
2244 | for (link = linked_proc_desc_table; link; link = link->next) | |
c5aa993b JM |
2245 | if (PROC_LOW_ADDR (&link->info) <= pc |
2246 | && PROC_HIGH_ADDR (&link->info) > pc) | |
c906108c SS |
2247 | return &link->info; |
2248 | ||
2249 | if (startaddr == 0) | |
2250 | startaddr = heuristic_proc_start (pc); | |
2251 | ||
2252 | proc_desc = | |
479412cd | 2253 | heuristic_proc_desc (startaddr, pc, next_frame, cur_frame); |
c906108c SS |
2254 | } |
2255 | return proc_desc; | |
2256 | } | |
2257 | ||
2258 | static CORE_ADDR | |
acdb74a0 AC |
2259 | get_frame_pointer (struct frame_info *frame, |
2260 | mips_extra_func_info_t proc_desc) | |
c906108c | 2261 | { |
c86b5b38 MS |
2262 | return ADDR_BITS_REMOVE (read_next_frame_reg (frame, |
2263 | PROC_FRAME_REG (proc_desc)) + | |
2264 | PROC_FRAME_OFFSET (proc_desc) - | |
2265 | PROC_FRAME_ADJUST (proc_desc)); | |
c906108c SS |
2266 | } |
2267 | ||
2268 | mips_extra_func_info_t cached_proc_desc; | |
2269 | ||
2270 | CORE_ADDR | |
acdb74a0 | 2271 | mips_frame_chain (struct frame_info *frame) |
c906108c SS |
2272 | { |
2273 | mips_extra_func_info_t proc_desc; | |
2274 | CORE_ADDR tmp; | |
c5aa993b | 2275 | CORE_ADDR saved_pc = FRAME_SAVED_PC (frame); |
c906108c SS |
2276 | |
2277 | if (saved_pc == 0 || inside_entry_file (saved_pc)) | |
2278 | return 0; | |
2279 | ||
2280 | /* Check if the PC is inside a call stub. If it is, fetch the | |
2281 | PC of the caller of that stub. */ | |
2282 | if ((tmp = mips_skip_stub (saved_pc)) != 0) | |
2283 | saved_pc = tmp; | |
2284 | ||
2285 | /* Look up the procedure descriptor for this PC. */ | |
479412cd | 2286 | proc_desc = find_proc_desc (saved_pc, frame, 1); |
c906108c SS |
2287 | if (!proc_desc) |
2288 | return 0; | |
2289 | ||
2290 | cached_proc_desc = proc_desc; | |
2291 | ||
2292 | /* If no frame pointer and frame size is zero, we must be at end | |
2293 | of stack (or otherwise hosed). If we don't check frame size, | |
2294 | we loop forever if we see a zero size frame. */ | |
2295 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM | |
2296 | && PROC_FRAME_OFFSET (proc_desc) == 0 | |
c5aa993b JM |
2297 | /* The previous frame from a sigtramp frame might be frameless |
2298 | and have frame size zero. */ | |
c906108c SS |
2299 | && !frame->signal_handler_caller) |
2300 | return 0; | |
2301 | else | |
2302 | return get_frame_pointer (frame, proc_desc); | |
2303 | } | |
2304 | ||
2305 | void | |
acdb74a0 | 2306 | mips_init_extra_frame_info (int fromleaf, struct frame_info *fci) |
c906108c SS |
2307 | { |
2308 | int regnum; | |
2309 | ||
2310 | /* Use proc_desc calculated in frame_chain */ | |
2311 | mips_extra_func_info_t proc_desc = | |
c86b5b38 | 2312 | fci->next ? cached_proc_desc : find_proc_desc (fci->pc, fci->next, 1); |
c906108c | 2313 | |
cce74817 JM |
2314 | fci->extra_info = (struct frame_extra_info *) |
2315 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
2316 | ||
c906108c | 2317 | fci->saved_regs = NULL; |
cce74817 | 2318 | fci->extra_info->proc_desc = |
c906108c SS |
2319 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
2320 | if (proc_desc) | |
2321 | { | |
2322 | /* Fixup frame-pointer - only needed for top frame */ | |
2323 | /* This may not be quite right, if proc has a real frame register. | |
c5aa993b JM |
2324 | Get the value of the frame relative sp, procedure might have been |
2325 | interrupted by a signal at it's very start. */ | |
c906108c SS |
2326 | if (fci->pc == PROC_LOW_ADDR (proc_desc) |
2327 | && !PROC_DESC_IS_DUMMY (proc_desc)) | |
2328 | fci->frame = read_next_frame_reg (fci->next, SP_REGNUM); | |
2329 | else | |
2330 | fci->frame = get_frame_pointer (fci->next, proc_desc); | |
2331 | ||
2332 | if (proc_desc == &temp_proc_desc) | |
2333 | { | |
2334 | char *name; | |
2335 | ||
2336 | /* Do not set the saved registers for a sigtramp frame, | |
2337 | mips_find_saved_registers will do that for us. | |
2338 | We can't use fci->signal_handler_caller, it is not yet set. */ | |
2339 | find_pc_partial_function (fci->pc, &name, | |
c5aa993b | 2340 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
d7bd68ca | 2341 | if (!PC_IN_SIGTRAMP (fci->pc, name)) |
c906108c | 2342 | { |
c5aa993b | 2343 | frame_saved_regs_zalloc (fci); |
cce74817 | 2344 | memcpy (fci->saved_regs, temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
2345 | fci->saved_regs[PC_REGNUM] |
2346 | = fci->saved_regs[RA_REGNUM]; | |
ffabd70d KB |
2347 | /* Set value of previous frame's stack pointer. Remember that |
2348 | saved_regs[SP_REGNUM] is special in that it contains the | |
2349 | value of the stack pointer register. The other saved_regs | |
2350 | values are addresses (in the inferior) at which a given | |
2351 | register's value may be found. */ | |
2352 | fci->saved_regs[SP_REGNUM] = fci->frame; | |
c906108c SS |
2353 | } |
2354 | } | |
2355 | ||
2356 | /* hack: if argument regs are saved, guess these contain args */ | |
cce74817 JM |
2357 | /* assume we can't tell how many args for now */ |
2358 | fci->extra_info->num_args = -1; | |
c906108c SS |
2359 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) |
2360 | { | |
c5aa993b | 2361 | if (PROC_REG_MASK (proc_desc) & (1 << regnum)) |
c906108c | 2362 | { |
cce74817 | 2363 | fci->extra_info->num_args = regnum - A0_REGNUM + 1; |
c906108c SS |
2364 | break; |
2365 | } | |
c5aa993b | 2366 | } |
c906108c SS |
2367 | } |
2368 | } | |
2369 | ||
2370 | /* MIPS stack frames are almost impenetrable. When execution stops, | |
2371 | we basically have to look at symbol information for the function | |
2372 | that we stopped in, which tells us *which* register (if any) is | |
2373 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 2374 | the frame itself is at. |
c906108c SS |
2375 | |
2376 | This presents a problem when trying to examine a stack in memory | |
2377 | (that isn't executing at the moment), using the "frame" command. We | |
2378 | don't have a PC, nor do we have any registers except SP. | |
2379 | ||
2380 | This routine takes two arguments, SP and PC, and tries to make the | |
2381 | cached frames look as if these two arguments defined a frame on the | |
2382 | cache. This allows the rest of info frame to extract the important | |
2383 | arguments without difficulty. */ | |
2384 | ||
2385 | struct frame_info * | |
acdb74a0 | 2386 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
2387 | { |
2388 | if (argc != 2) | |
2389 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2390 | ||
2391 | return create_new_frame (argv[0], argv[1]); | |
2392 | } | |
2393 | ||
f09ded24 AC |
2394 | /* According to the current ABI, should the type be passed in a |
2395 | floating-point register (assuming that there is space)? When there | |
2396 | is no FPU, FP are not even considered as possibile candidates for | |
2397 | FP registers and, consequently this returns false - forces FP | |
2398 | arguments into integer registers. */ | |
2399 | ||
2400 | static int | |
2401 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2402 | { | |
2403 | return ((typecode == TYPE_CODE_FLT | |
2404 | || (MIPS_EABI | |
2405 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
2406 | && TYPE_NFIELDS (arg_type) == 1 | |
2407 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 2408 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2409 | } |
2410 | ||
49e790b0 DJ |
2411 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2412 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2413 | ||
2414 | static int | |
2415 | mips_type_needs_double_align (struct type *type) | |
2416 | { | |
2417 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2418 | |
49e790b0 DJ |
2419 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2420 | return 1; | |
2421 | else if (typecode == TYPE_CODE_STRUCT) | |
2422 | { | |
2423 | if (TYPE_NFIELDS (type) < 1) | |
2424 | return 0; | |
2425 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2426 | } | |
2427 | else if (typecode == TYPE_CODE_UNION) | |
2428 | { | |
361d1df0 | 2429 | int i, n; |
49e790b0 DJ |
2430 | |
2431 | n = TYPE_NFIELDS (type); | |
2432 | for (i = 0; i < n; i++) | |
2433 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2434 | return 1; | |
2435 | return 0; | |
2436 | } | |
2437 | return 0; | |
2438 | } | |
2439 | ||
cb3d25d1 MS |
2440 | /* Macros to round N up or down to the next A boundary; |
2441 | A must be a power of two. */ | |
2442 | ||
2443 | #define ROUND_DOWN(n,a) ((n) & ~((a)-1)) | |
2444 | #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1)) | |
2445 | ||
c906108c | 2446 | CORE_ADDR |
46e0f506 MS |
2447 | mips_eabi_push_arguments (int nargs, |
2448 | struct value **args, | |
2449 | CORE_ADDR sp, | |
2450 | int struct_return, | |
2451 | CORE_ADDR struct_addr) | |
c906108c SS |
2452 | { |
2453 | int argreg; | |
2454 | int float_argreg; | |
2455 | int argnum; | |
2456 | int len = 0; | |
2457 | int stack_offset = 0; | |
2458 | ||
c906108c | 2459 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2460 | are properly aligned. The stack has to be at least 64-bit |
2461 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2462 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2463 | aligned, so we round to this widest known alignment. */ | |
2464 | ||
c906108c | 2465 | sp = ROUND_DOWN (sp, 16); |
cce41527 | 2466 | struct_addr = ROUND_DOWN (struct_addr, 16); |
c5aa993b | 2467 | |
46e0f506 | 2468 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2469 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2470 | passed in registers, but that's OK. */ |
c906108c | 2471 | for (argnum = 0; argnum < nargs; argnum++) |
46e0f506 MS |
2472 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
2473 | MIPS_STACK_ARGSIZE); | |
c906108c SS |
2474 | sp -= ROUND_UP (len, 16); |
2475 | ||
9ace0497 | 2476 | if (mips_debug) |
46e0f506 MS |
2477 | fprintf_unfiltered (gdb_stdlog, |
2478 | "mips_eabi_push_arguments: sp=0x%s allocated %d\n", | |
cb3d25d1 | 2479 | paddr_nz (sp), ROUND_UP (len, 16)); |
9ace0497 | 2480 | |
c906108c SS |
2481 | /* Initialize the integer and float register pointers. */ |
2482 | argreg = A0_REGNUM; | |
2483 | float_argreg = FPA0_REGNUM; | |
2484 | ||
46e0f506 | 2485 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2486 | if (struct_return) |
9ace0497 AC |
2487 | { |
2488 | if (mips_debug) | |
2489 | fprintf_unfiltered (gdb_stdlog, | |
46e0f506 | 2490 | "mips_eabi_push_arguments: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2491 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
2492 | write_register (argreg++, struct_addr); |
2493 | } | |
c906108c SS |
2494 | |
2495 | /* Now load as many as possible of the first arguments into | |
2496 | registers, and push the rest onto the stack. Loop thru args | |
2497 | from first to last. */ | |
2498 | for (argnum = 0; argnum < nargs; argnum++) | |
2499 | { | |
2500 | char *val; | |
cb3d25d1 | 2501 | char *valbuf = alloca (MAX_REGISTER_RAW_SIZE); |
ea7c478f | 2502 | struct value *arg = args[argnum]; |
c906108c SS |
2503 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
2504 | int len = TYPE_LENGTH (arg_type); | |
2505 | enum type_code typecode = TYPE_CODE (arg_type); | |
2506 | ||
9ace0497 AC |
2507 | if (mips_debug) |
2508 | fprintf_unfiltered (gdb_stdlog, | |
46e0f506 | 2509 | "mips_eabi_push_arguments: %d len=%d type=%d", |
acdb74a0 | 2510 | argnum + 1, len, (int) typecode); |
9ace0497 | 2511 | |
c906108c | 2512 | /* The EABI passes structures that do not fit in a register by |
46e0f506 MS |
2513 | reference. */ |
2514 | if (len > MIPS_SAVED_REGSIZE | |
9ace0497 | 2515 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2516 | { |
7a292a7a | 2517 | store_address (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg)); |
c906108c | 2518 | typecode = TYPE_CODE_PTR; |
7a292a7a | 2519 | len = MIPS_SAVED_REGSIZE; |
c906108c | 2520 | val = valbuf; |
9ace0497 AC |
2521 | if (mips_debug) |
2522 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2523 | } |
2524 | else | |
c5aa993b | 2525 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
2526 | |
2527 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2528 | even-numbered floating point register. Round the FP register |
2529 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2530 | left. Non MIPS_EABI targets also pass the FP in the integer |
2531 | registers so also round up normal registers. */ | |
acdb74a0 AC |
2532 | if (!FP_REGISTER_DOUBLE |
2533 | && fp_register_arg_p (typecode, arg_type)) | |
2534 | { | |
2535 | if ((float_argreg & 1)) | |
2536 | float_argreg++; | |
2537 | } | |
c906108c SS |
2538 | |
2539 | /* Floating point arguments passed in registers have to be | |
2540 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2541 | are passed in register pairs; the even register gets |
2542 | the low word, and the odd register gets the high word. | |
2543 | On non-EABI processors, the first two floating point arguments are | |
2544 | also copied to general registers, because MIPS16 functions | |
2545 | don't use float registers for arguments. This duplication of | |
2546 | arguments in general registers can't hurt non-MIPS16 functions | |
2547 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2548 | /* MIPS_EABI squeezes a struct that contains a single floating |
2549 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2550 | stack. */ |
f09ded24 AC |
2551 | if (fp_register_arg_p (typecode, arg_type) |
2552 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c SS |
2553 | { |
2554 | if (!FP_REGISTER_DOUBLE && len == 8) | |
2555 | { | |
d7449b42 | 2556 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2557 | unsigned long regval; |
2558 | ||
2559 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2560 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2561 | if (mips_debug) |
acdb74a0 | 2562 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2563 | float_argreg, phex (regval, 4)); |
c906108c | 2564 | write_register (float_argreg++, regval); |
c906108c SS |
2565 | |
2566 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2567 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2568 | if (mips_debug) |
acdb74a0 | 2569 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2570 | float_argreg, phex (regval, 4)); |
c906108c | 2571 | write_register (float_argreg++, regval); |
c906108c SS |
2572 | } |
2573 | else | |
2574 | { | |
2575 | /* This is a floating point value that fits entirely | |
2576 | in a single register. */ | |
53a5351d | 2577 | /* On 32 bit ABI's the float_argreg is further adjusted |
46e0f506 | 2578 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2579 | LONGEST regval = extract_unsigned_integer (val, len); |
2580 | if (mips_debug) | |
acdb74a0 | 2581 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2582 | float_argreg, phex (regval, len)); |
c906108c | 2583 | write_register (float_argreg++, regval); |
c906108c SS |
2584 | } |
2585 | } | |
2586 | else | |
2587 | { | |
2588 | /* Copy the argument to general registers or the stack in | |
2589 | register-sized pieces. Large arguments are split between | |
2590 | registers and stack. */ | |
2591 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
2592 | are treated specially: Irix cc passes them in registers | |
2593 | where gcc sometimes puts them on the stack. For maximum | |
2594 | compatibility, we will put them in both places. */ | |
c5aa993b | 2595 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
7a292a7a | 2596 | (len % MIPS_SAVED_REGSIZE != 0)); |
46e0f506 | 2597 | |
f09ded24 | 2598 | /* Note: Floating-point values that didn't fit into an FP |
46e0f506 | 2599 | register are only written to memory. */ |
c906108c SS |
2600 | while (len > 0) |
2601 | { | |
ebafbe83 | 2602 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2603 | int stack_used_p = 0; |
46e0f506 MS |
2604 | int partial_len = |
2605 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
c906108c | 2606 | |
acdb74a0 AC |
2607 | if (mips_debug) |
2608 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2609 | partial_len); | |
2610 | ||
566f0f7a | 2611 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2612 | if (argreg > MIPS_LAST_ARG_REGNUM |
2613 | || odd_sized_struct | |
2614 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2615 | { |
c906108c SS |
2616 | /* Should shorter than int integer values be |
2617 | promoted to int before being stored? */ | |
c906108c | 2618 | int longword_offset = 0; |
9ace0497 | 2619 | CORE_ADDR addr; |
566f0f7a | 2620 | stack_used_p = 1; |
d7449b42 | 2621 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 2622 | { |
d929b26f | 2623 | if (MIPS_STACK_ARGSIZE == 8 && |
7a292a7a SS |
2624 | (typecode == TYPE_CODE_INT || |
2625 | typecode == TYPE_CODE_PTR || | |
2626 | typecode == TYPE_CODE_FLT) && len <= 4) | |
d929b26f | 2627 | longword_offset = MIPS_STACK_ARGSIZE - len; |
7a292a7a SS |
2628 | else if ((typecode == TYPE_CODE_STRUCT || |
2629 | typecode == TYPE_CODE_UNION) && | |
d929b26f AC |
2630 | TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE) |
2631 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
7a292a7a | 2632 | } |
c5aa993b | 2633 | |
9ace0497 AC |
2634 | if (mips_debug) |
2635 | { | |
cb3d25d1 MS |
2636 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2637 | paddr_nz (stack_offset)); | |
2638 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2639 | paddr_nz (longword_offset)); | |
9ace0497 | 2640 | } |
361d1df0 | 2641 | |
9ace0497 AC |
2642 | addr = sp + stack_offset + longword_offset; |
2643 | ||
2644 | if (mips_debug) | |
2645 | { | |
2646 | int i; | |
cb3d25d1 MS |
2647 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
2648 | paddr_nz (addr)); | |
9ace0497 AC |
2649 | for (i = 0; i < partial_len; i++) |
2650 | { | |
cb3d25d1 MS |
2651 | fprintf_unfiltered (gdb_stdlog, "%02x", |
2652 | val[i] & 0xff); | |
9ace0497 AC |
2653 | } |
2654 | } | |
2655 | write_memory (addr, val, partial_len); | |
c906108c SS |
2656 | } |
2657 | ||
f09ded24 AC |
2658 | /* Note!!! This is NOT an else clause. Odd sized |
2659 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2660 | arguments will not. */ |
566f0f7a | 2661 | /* Write this portion of the argument to a general |
46e0f506 | 2662 | purpose register. */ |
f09ded24 AC |
2663 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2664 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2665 | { |
9ace0497 | 2666 | LONGEST regval = extract_unsigned_integer (val, partial_len); |
c906108c | 2667 | |
9ace0497 | 2668 | if (mips_debug) |
acdb74a0 | 2669 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 AC |
2670 | argreg, |
2671 | phex (regval, MIPS_SAVED_REGSIZE)); | |
c906108c SS |
2672 | write_register (argreg, regval); |
2673 | argreg++; | |
c906108c | 2674 | } |
c5aa993b | 2675 | |
c906108c SS |
2676 | len -= partial_len; |
2677 | val += partial_len; | |
2678 | ||
566f0f7a AC |
2679 | /* Compute the the offset into the stack at which we |
2680 | will copy the next parameter. | |
2681 | ||
566f0f7a | 2682 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2683 | only needs to be adjusted when it has been used. */ |
c906108c | 2684 | |
46e0f506 | 2685 | if (stack_used_p) |
d929b26f | 2686 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); |
c906108c SS |
2687 | } |
2688 | } | |
9ace0497 AC |
2689 | if (mips_debug) |
2690 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2691 | } |
2692 | ||
0f71a2f6 JM |
2693 | /* Return adjusted stack pointer. */ |
2694 | return sp; | |
2695 | } | |
2696 | ||
ebafbe83 MS |
2697 | /* N32/N64 version of push_arguments. */ |
2698 | ||
cb3d25d1 MS |
2699 | CORE_ADDR |
2700 | mips_n32n64_push_arguments (int nargs, | |
2701 | struct value **args, | |
2702 | CORE_ADDR sp, | |
2703 | int struct_return, | |
2704 | CORE_ADDR struct_addr) | |
2705 | { | |
2706 | int argreg; | |
2707 | int float_argreg; | |
2708 | int argnum; | |
2709 | int len = 0; | |
2710 | int stack_offset = 0; | |
2711 | ||
2712 | /* First ensure that the stack and structure return address (if any) | |
2713 | are properly aligned. The stack has to be at least 64-bit | |
2714 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2715 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2716 | aligned, so we round to this widest known alignment. */ | |
2717 | ||
2718 | sp = ROUND_DOWN (sp, 16); | |
2719 | struct_addr = ROUND_DOWN (struct_addr, 16); | |
2720 | ||
2721 | /* Now make space on the stack for the args. */ | |
2722 | for (argnum = 0; argnum < nargs; argnum++) | |
2723 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), | |
2724 | MIPS_STACK_ARGSIZE); | |
2725 | sp -= ROUND_UP (len, 16); | |
2726 | ||
2727 | if (mips_debug) | |
2728 | fprintf_unfiltered (gdb_stdlog, | |
2729 | "mips_n32n64_push_arguments: sp=0x%s allocated %d\n", | |
2730 | paddr_nz (sp), ROUND_UP (len, 16)); | |
2731 | ||
2732 | /* Initialize the integer and float register pointers. */ | |
2733 | argreg = A0_REGNUM; | |
2734 | float_argreg = FPA0_REGNUM; | |
2735 | ||
46e0f506 | 2736 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
2737 | if (struct_return) |
2738 | { | |
2739 | if (mips_debug) | |
2740 | fprintf_unfiltered (gdb_stdlog, | |
2741 | "mips_n32n64_push_arguments: struct_return reg=%d 0x%s\n", | |
2742 | argreg, paddr_nz (struct_addr)); | |
2743 | write_register (argreg++, struct_addr); | |
2744 | } | |
2745 | ||
2746 | /* Now load as many as possible of the first arguments into | |
2747 | registers, and push the rest onto the stack. Loop thru args | |
2748 | from first to last. */ | |
2749 | for (argnum = 0; argnum < nargs; argnum++) | |
2750 | { | |
2751 | char *val; | |
2752 | char *valbuf = alloca (MAX_REGISTER_RAW_SIZE); | |
2753 | struct value *arg = args[argnum]; | |
2754 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
2755 | int len = TYPE_LENGTH (arg_type); | |
2756 | enum type_code typecode = TYPE_CODE (arg_type); | |
2757 | ||
2758 | if (mips_debug) | |
2759 | fprintf_unfiltered (gdb_stdlog, | |
2760 | "mips_n32n64_push_arguments: %d len=%d type=%d", | |
2761 | argnum + 1, len, (int) typecode); | |
2762 | ||
2763 | val = (char *) VALUE_CONTENTS (arg); | |
2764 | ||
2765 | if (fp_register_arg_p (typecode, arg_type) | |
2766 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
2767 | { | |
2768 | /* This is a floating point value that fits entirely | |
2769 | in a single register. */ | |
2770 | /* On 32 bit ABI's the float_argreg is further adjusted | |
2771 | above to ensure that it is even register aligned. */ | |
2772 | LONGEST regval = extract_unsigned_integer (val, len); | |
2773 | if (mips_debug) | |
2774 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
2775 | float_argreg, phex (regval, len)); | |
2776 | write_register (float_argreg++, regval); | |
2777 | ||
2778 | if (mips_debug) | |
2779 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
2780 | argreg, phex (regval, len)); | |
2781 | write_register (argreg, regval); | |
2782 | argreg += 1; | |
2783 | } | |
2784 | else | |
2785 | { | |
2786 | /* Copy the argument to general registers or the stack in | |
2787 | register-sized pieces. Large arguments are split between | |
2788 | registers and stack. */ | |
2789 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
2790 | are treated specially: Irix cc passes them in registers | |
2791 | where gcc sometimes puts them on the stack. For maximum | |
2792 | compatibility, we will put them in both places. */ | |
2793 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && | |
2794 | (len % MIPS_SAVED_REGSIZE != 0)); | |
2795 | /* Note: Floating-point values that didn't fit into an FP | |
2796 | register are only written to memory. */ | |
2797 | while (len > 0) | |
2798 | { | |
2799 | /* Rememer if the argument was written to the stack. */ | |
2800 | int stack_used_p = 0; | |
2801 | int partial_len = len < MIPS_SAVED_REGSIZE ? | |
2802 | len : MIPS_SAVED_REGSIZE; | |
2803 | ||
2804 | if (mips_debug) | |
2805 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2806 | partial_len); | |
2807 | ||
2808 | /* Write this portion of the argument to the stack. */ | |
2809 | if (argreg > MIPS_LAST_ARG_REGNUM | |
2810 | || odd_sized_struct | |
2811 | || fp_register_arg_p (typecode, arg_type)) | |
2812 | { | |
2813 | /* Should shorter than int integer values be | |
2814 | promoted to int before being stored? */ | |
2815 | int longword_offset = 0; | |
2816 | CORE_ADDR addr; | |
2817 | stack_used_p = 1; | |
2818 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2819 | { | |
2820 | if (MIPS_STACK_ARGSIZE == 8 && | |
2821 | (typecode == TYPE_CODE_INT || | |
2822 | typecode == TYPE_CODE_PTR || | |
2823 | typecode == TYPE_CODE_FLT) && len <= 4) | |
2824 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
2825 | else if ((typecode == TYPE_CODE_STRUCT || | |
2826 | typecode == TYPE_CODE_UNION) && | |
2827 | TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE) | |
2828 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
2829 | } | |
2830 | ||
2831 | if (mips_debug) | |
2832 | { | |
2833 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
2834 | paddr_nz (stack_offset)); | |
2835 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2836 | paddr_nz (longword_offset)); | |
2837 | } | |
2838 | ||
2839 | addr = sp + stack_offset + longword_offset; | |
2840 | ||
2841 | if (mips_debug) | |
2842 | { | |
2843 | int i; | |
2844 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
2845 | paddr_nz (addr)); | |
2846 | for (i = 0; i < partial_len; i++) | |
2847 | { | |
2848 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
2849 | val[i] & 0xff); | |
2850 | } | |
2851 | } | |
2852 | write_memory (addr, val, partial_len); | |
2853 | } | |
2854 | ||
2855 | /* Note!!! This is NOT an else clause. Odd sized | |
2856 | structs may go thru BOTH paths. Floating point | |
2857 | arguments will not. */ | |
2858 | /* Write this portion of the argument to a general | |
2859 | purpose register. */ | |
2860 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
2861 | && !fp_register_arg_p (typecode, arg_type)) | |
2862 | { | |
2863 | LONGEST regval = extract_unsigned_integer (val, partial_len); | |
2864 | ||
2865 | /* A non-floating-point argument being passed in a | |
2866 | general register. If a struct or union, and if | |
2867 | the remaining length is smaller than the register | |
2868 | size, we have to adjust the register value on | |
2869 | big endian targets. | |
2870 | ||
2871 | It does not seem to be necessary to do the | |
2872 | same for integral types. | |
2873 | ||
2874 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
2875 | outputting LE O32 with sizeof (struct) < | |
2876 | MIPS_SAVED_REGSIZE, generates a left shift as | |
2877 | part of storing the argument in a register a | |
2878 | register (the left shift isn't generated when | |
2879 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
2880 | is quite possible that this is GCC contradicting | |
2881 | the LE/O32 ABI, GDB has not been adjusted to | |
2882 | accommodate this. Either someone needs to | |
2883 | demonstrate that the LE/O32 ABI specifies such a | |
2884 | left shift OR this new ABI gets identified as | |
2885 | such and GDB gets tweaked accordingly. */ | |
2886 | ||
2887 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
2888 | && partial_len < MIPS_SAVED_REGSIZE | |
2889 | && (typecode == TYPE_CODE_STRUCT || | |
2890 | typecode == TYPE_CODE_UNION)) | |
2891 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
2892 | TARGET_CHAR_BIT); | |
2893 | ||
2894 | if (mips_debug) | |
2895 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
2896 | argreg, | |
2897 | phex (regval, MIPS_SAVED_REGSIZE)); | |
2898 | write_register (argreg, regval); | |
2899 | argreg++; | |
2900 | } | |
2901 | ||
2902 | len -= partial_len; | |
2903 | val += partial_len; | |
2904 | ||
2905 | /* Compute the the offset into the stack at which we | |
2906 | will copy the next parameter. | |
2907 | ||
2908 | In N32 (N64?), the stack_offset only needs to be | |
2909 | adjusted when it has been used. */ | |
2910 | ||
2911 | if (stack_used_p) | |
2912 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); | |
2913 | } | |
2914 | } | |
2915 | if (mips_debug) | |
2916 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
2917 | } | |
2918 | ||
2919 | /* Return adjusted stack pointer. */ | |
2920 | return sp; | |
2921 | } | |
2922 | ||
ebafbe83 MS |
2923 | /* O32/O64 version of push_arguments. */ |
2924 | ||
2925 | CORE_ADDR | |
2926 | mips_o32o64_push_arguments (int nargs, | |
2927 | struct value **args, | |
2928 | CORE_ADDR sp, | |
2929 | int struct_return, | |
2930 | CORE_ADDR struct_addr) | |
2931 | { | |
2932 | int argreg; | |
2933 | int float_argreg; | |
2934 | int argnum; | |
2935 | int len = 0; | |
2936 | int stack_offset = 0; | |
ebafbe83 MS |
2937 | |
2938 | /* First ensure that the stack and structure return address (if any) | |
2939 | are properly aligned. The stack has to be at least 64-bit | |
2940 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2941 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2942 | aligned, so we round to this widest known alignment. */ | |
2943 | ||
2944 | sp = ROUND_DOWN (sp, 16); | |
2945 | struct_addr = ROUND_DOWN (struct_addr, 16); | |
2946 | ||
2947 | /* Now make space on the stack for the args. */ | |
2948 | for (argnum = 0; argnum < nargs; argnum++) | |
2949 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), | |
2950 | MIPS_STACK_ARGSIZE); | |
2951 | sp -= ROUND_UP (len, 16); | |
2952 | ||
2953 | if (mips_debug) | |
2954 | fprintf_unfiltered (gdb_stdlog, | |
2955 | "mips_o32o64_push_arguments: sp=0x%s allocated %d\n", | |
2956 | paddr_nz (sp), ROUND_UP (len, 16)); | |
2957 | ||
2958 | /* Initialize the integer and float register pointers. */ | |
2959 | argreg = A0_REGNUM; | |
2960 | float_argreg = FPA0_REGNUM; | |
2961 | ||
2962 | /* the struct_return pointer occupies the first parameter-passing reg */ | |
2963 | if (struct_return) | |
2964 | { | |
2965 | if (mips_debug) | |
2966 | fprintf_unfiltered (gdb_stdlog, | |
2967 | "mips_o32o64_push_arguments: struct_return reg=%d 0x%s\n", | |
2968 | argreg, paddr_nz (struct_addr)); | |
2969 | write_register (argreg++, struct_addr); | |
2970 | stack_offset += MIPS_STACK_ARGSIZE; | |
2971 | } | |
2972 | ||
2973 | /* Now load as many as possible of the first arguments into | |
2974 | registers, and push the rest onto the stack. Loop thru args | |
2975 | from first to last. */ | |
2976 | for (argnum = 0; argnum < nargs; argnum++) | |
2977 | { | |
2978 | char *val; | |
2979 | char *valbuf = alloca (MAX_REGISTER_RAW_SIZE); | |
2980 | struct value *arg = args[argnum]; | |
2981 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
2982 | int len = TYPE_LENGTH (arg_type); | |
2983 | enum type_code typecode = TYPE_CODE (arg_type); | |
2984 | ||
2985 | if (mips_debug) | |
2986 | fprintf_unfiltered (gdb_stdlog, | |
2987 | "mips_o32o64_push_arguments: %d len=%d type=%d", | |
2988 | argnum + 1, len, (int) typecode); | |
2989 | ||
2990 | val = (char *) VALUE_CONTENTS (arg); | |
2991 | ||
2992 | /* 32-bit ABIs always start floating point arguments in an | |
2993 | even-numbered floating point register. Round the FP register | |
2994 | up before the check to see if there are any FP registers | |
2995 | left. O32/O64 targets also pass the FP in the integer | |
2996 | registers so also round up normal registers. */ | |
2997 | if (!FP_REGISTER_DOUBLE | |
2998 | && fp_register_arg_p (typecode, arg_type)) | |
2999 | { | |
3000 | if ((float_argreg & 1)) | |
3001 | float_argreg++; | |
3002 | } | |
3003 | ||
3004 | /* Floating point arguments passed in registers have to be | |
3005 | treated specially. On 32-bit architectures, doubles | |
3006 | are passed in register pairs; the even register gets | |
3007 | the low word, and the odd register gets the high word. | |
3008 | On O32/O64, the first two floating point arguments are | |
3009 | also copied to general registers, because MIPS16 functions | |
3010 | don't use float registers for arguments. This duplication of | |
3011 | arguments in general registers can't hurt non-MIPS16 functions | |
3012 | because those registers are normally skipped. */ | |
3013 | ||
3014 | if (fp_register_arg_p (typecode, arg_type) | |
3015 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3016 | { | |
3017 | if (!FP_REGISTER_DOUBLE && len == 8) | |
3018 | { | |
3019 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3020 | unsigned long regval; | |
3021 | ||
3022 | /* Write the low word of the double to the even register(s). */ | |
3023 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3024 | if (mips_debug) | |
3025 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3026 | float_argreg, phex (regval, 4)); | |
3027 | write_register (float_argreg++, regval); | |
3028 | if (mips_debug) | |
3029 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3030 | argreg, phex (regval, 4)); | |
3031 | write_register (argreg++, regval); | |
3032 | ||
3033 | /* Write the high word of the double to the odd register(s). */ | |
3034 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3035 | if (mips_debug) | |
3036 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3037 | float_argreg, phex (regval, 4)); | |
3038 | write_register (float_argreg++, regval); | |
3039 | ||
3040 | if (mips_debug) | |
3041 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3042 | argreg, phex (regval, 4)); | |
3043 | write_register (argreg++, regval); | |
3044 | } | |
3045 | else | |
3046 | { | |
3047 | /* This is a floating point value that fits entirely | |
3048 | in a single register. */ | |
3049 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3050 | above to ensure that it is even register aligned. */ | |
3051 | LONGEST regval = extract_unsigned_integer (val, len); | |
3052 | if (mips_debug) | |
3053 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3054 | float_argreg, phex (regval, len)); | |
3055 | write_register (float_argreg++, regval); | |
3056 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
3057 | registers for each argument. The below is (my | |
3058 | guess) to ensure that the corresponding integer | |
3059 | register has reserved the same space. */ | |
3060 | if (mips_debug) | |
3061 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3062 | argreg, phex (regval, len)); | |
3063 | write_register (argreg, regval); | |
3064 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; | |
3065 | } | |
3066 | /* Reserve space for the FP register. */ | |
3067 | stack_offset += ROUND_UP (len, MIPS_STACK_ARGSIZE); | |
3068 | } | |
3069 | else | |
3070 | { | |
3071 | /* Copy the argument to general registers or the stack in | |
3072 | register-sized pieces. Large arguments are split between | |
3073 | registers and stack. */ | |
3074 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE | |
3075 | are treated specially: Irix cc passes them in registers | |
3076 | where gcc sometimes puts them on the stack. For maximum | |
3077 | compatibility, we will put them in both places. */ | |
3078 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && | |
3079 | (len % MIPS_SAVED_REGSIZE != 0)); | |
3080 | /* Structures should be aligned to eight bytes (even arg registers) | |
3081 | on MIPS_ABI_O32, if their first member has double precision. */ | |
3082 | if (MIPS_SAVED_REGSIZE < 8 | |
3083 | && mips_type_needs_double_align (arg_type)) | |
3084 | { | |
3085 | if ((argreg & 1)) | |
3086 | argreg++; | |
3087 | } | |
3088 | /* Note: Floating-point values that didn't fit into an FP | |
3089 | register are only written to memory. */ | |
3090 | while (len > 0) | |
3091 | { | |
3092 | /* Remember if the argument was written to the stack. */ | |
3093 | int stack_used_p = 0; | |
3094 | int partial_len = | |
3095 | len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; | |
3096 | ||
3097 | if (mips_debug) | |
3098 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3099 | partial_len); | |
3100 | ||
3101 | /* Write this portion of the argument to the stack. */ | |
3102 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3103 | || odd_sized_struct | |
3104 | || fp_register_arg_p (typecode, arg_type)) | |
3105 | { | |
3106 | /* Should shorter than int integer values be | |
3107 | promoted to int before being stored? */ | |
3108 | int longword_offset = 0; | |
3109 | CORE_ADDR addr; | |
3110 | stack_used_p = 1; | |
3111 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3112 | { | |
3113 | if (MIPS_STACK_ARGSIZE == 8 && | |
3114 | (typecode == TYPE_CODE_INT || | |
3115 | typecode == TYPE_CODE_PTR || | |
3116 | typecode == TYPE_CODE_FLT) && len <= 4) | |
3117 | longword_offset = MIPS_STACK_ARGSIZE - len; | |
3118 | } | |
3119 | ||
3120 | if (mips_debug) | |
3121 | { | |
3122 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3123 | paddr_nz (stack_offset)); | |
3124 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3125 | paddr_nz (longword_offset)); | |
3126 | } | |
3127 | ||
3128 | addr = sp + stack_offset + longword_offset; | |
3129 | ||
3130 | if (mips_debug) | |
3131 | { | |
3132 | int i; | |
3133 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", | |
3134 | paddr_nz (addr)); | |
3135 | for (i = 0; i < partial_len; i++) | |
3136 | { | |
3137 | fprintf_unfiltered (gdb_stdlog, "%02x", | |
3138 | val[i] & 0xff); | |
3139 | } | |
3140 | } | |
3141 | write_memory (addr, val, partial_len); | |
3142 | } | |
3143 | ||
3144 | /* Note!!! This is NOT an else clause. Odd sized | |
3145 | structs may go thru BOTH paths. Floating point | |
3146 | arguments will not. */ | |
3147 | /* Write this portion of the argument to a general | |
3148 | purpose register. */ | |
3149 | if (argreg <= MIPS_LAST_ARG_REGNUM | |
3150 | && !fp_register_arg_p (typecode, arg_type)) | |
3151 | { | |
3152 | LONGEST regval = extract_signed_integer (val, partial_len); | |
3153 | /* Value may need to be sign extended, because | |
3154 | MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */ | |
3155 | ||
3156 | /* A non-floating-point argument being passed in a | |
3157 | general register. If a struct or union, and if | |
3158 | the remaining length is smaller than the register | |
3159 | size, we have to adjust the register value on | |
3160 | big endian targets. | |
3161 | ||
3162 | It does not seem to be necessary to do the | |
3163 | same for integral types. | |
3164 | ||
3165 | Also don't do this adjustment on O64 binaries. | |
3166 | ||
3167 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3168 | outputting LE O32 with sizeof (struct) < | |
3169 | MIPS_SAVED_REGSIZE, generates a left shift as | |
3170 | part of storing the argument in a register a | |
3171 | register (the left shift isn't generated when | |
3172 | sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it | |
3173 | is quite possible that this is GCC contradicting | |
3174 | the LE/O32 ABI, GDB has not been adjusted to | |
3175 | accommodate this. Either someone needs to | |
3176 | demonstrate that the LE/O32 ABI specifies such a | |
3177 | left shift OR this new ABI gets identified as | |
3178 | such and GDB gets tweaked accordingly. */ | |
3179 | ||
3180 | if (MIPS_SAVED_REGSIZE < 8 | |
3181 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3182 | && partial_len < MIPS_SAVED_REGSIZE | |
3183 | && (typecode == TYPE_CODE_STRUCT || | |
3184 | typecode == TYPE_CODE_UNION)) | |
3185 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * | |
3186 | TARGET_CHAR_BIT); | |
3187 | ||
3188 | if (mips_debug) | |
3189 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3190 | argreg, | |
3191 | phex (regval, MIPS_SAVED_REGSIZE)); | |
3192 | write_register (argreg, regval); | |
3193 | argreg++; | |
3194 | ||
3195 | /* Prevent subsequent floating point arguments from | |
3196 | being passed in floating point registers. */ | |
3197 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3198 | } | |
3199 | ||
3200 | len -= partial_len; | |
3201 | val += partial_len; | |
3202 | ||
3203 | /* Compute the the offset into the stack at which we | |
3204 | will copy the next parameter. | |
3205 | ||
3206 | In older ABIs, the caller reserved space for | |
3207 | registers that contained arguments. This was loosely | |
3208 | refered to as their "home". Consequently, space is | |
3209 | always allocated. */ | |
3210 | ||
3211 | stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE); | |
3212 | } | |
3213 | } | |
3214 | if (mips_debug) | |
3215 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3216 | } | |
3217 | ||
3218 | /* Return adjusted stack pointer. */ | |
3219 | return sp; | |
3220 | } | |
3221 | ||
0f71a2f6 | 3222 | CORE_ADDR |
acdb74a0 | 3223 | mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
0f71a2f6 | 3224 | { |
c906108c SS |
3225 | /* Set the return address register to point to the entry |
3226 | point of the program, where a breakpoint lies in wait. */ | |
c5aa993b | 3227 | write_register (RA_REGNUM, CALL_DUMMY_ADDRESS ()); |
c906108c SS |
3228 | return sp; |
3229 | } | |
3230 | ||
3231 | static void | |
c5aa993b | 3232 | mips_push_register (CORE_ADDR * sp, int regno) |
c906108c | 3233 | { |
cb3d25d1 | 3234 | char *buffer = alloca (MAX_REGISTER_RAW_SIZE); |
7a292a7a SS |
3235 | int regsize; |
3236 | int offset; | |
3237 | if (MIPS_SAVED_REGSIZE < REGISTER_RAW_SIZE (regno)) | |
3238 | { | |
3239 | regsize = MIPS_SAVED_REGSIZE; | |
d7449b42 | 3240 | offset = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
3241 | ? REGISTER_RAW_SIZE (regno) - MIPS_SAVED_REGSIZE |
3242 | : 0); | |
3243 | } | |
3244 | else | |
3245 | { | |
3246 | regsize = REGISTER_RAW_SIZE (regno); | |
3247 | offset = 0; | |
3248 | } | |
c906108c SS |
3249 | *sp -= regsize; |
3250 | read_register_gen (regno, buffer); | |
7a292a7a | 3251 | write_memory (*sp, buffer + offset, regsize); |
c906108c SS |
3252 | } |
3253 | ||
3254 | /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */ | |
3255 | #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1)) | |
3256 | ||
3257 | void | |
acdb74a0 | 3258 | mips_push_dummy_frame (void) |
c906108c SS |
3259 | { |
3260 | int ireg; | |
c5aa993b JM |
3261 | struct linked_proc_info *link = (struct linked_proc_info *) |
3262 | xmalloc (sizeof (struct linked_proc_info)); | |
c906108c | 3263 | mips_extra_func_info_t proc_desc = &link->info; |
6c997a34 | 3264 | CORE_ADDR sp = ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM)); |
c906108c SS |
3265 | CORE_ADDR old_sp = sp; |
3266 | link->next = linked_proc_desc_table; | |
3267 | linked_proc_desc_table = link; | |
3268 | ||
3269 | /* FIXME! are these correct ? */ | |
c5aa993b | 3270 | #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */ |
c906108c SS |
3271 | #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1)) |
3272 | #define FLOAT_REG_SAVE_MASK MASK(0,19) | |
3273 | #define FLOAT_SINGLE_REG_SAVE_MASK \ | |
3274 | ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0)) | |
3275 | /* | |
3276 | * The registers we must save are all those not preserved across | |
3277 | * procedure calls. Dest_Reg (see tm-mips.h) must also be saved. | |
3278 | * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI | |
3279 | * and FP Control/Status registers. | |
361d1df0 | 3280 | * |
c906108c SS |
3281 | * |
3282 | * Dummy frame layout: | |
3283 | * (high memory) | |
c5aa993b JM |
3284 | * Saved PC |
3285 | * Saved MMHI, MMLO, FPC_CSR | |
3286 | * Saved R31 | |
3287 | * Saved R28 | |
3288 | * ... | |
3289 | * Saved R1 | |
c906108c SS |
3290 | * Saved D18 (i.e. F19, F18) |
3291 | * ... | |
3292 | * Saved D0 (i.e. F1, F0) | |
c5aa993b | 3293 | * Argument build area and stack arguments written via mips_push_arguments |
c906108c SS |
3294 | * (low memory) |
3295 | */ | |
3296 | ||
3297 | /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */ | |
c5aa993b JM |
3298 | PROC_FRAME_REG (proc_desc) = PUSH_FP_REGNUM; |
3299 | PROC_FRAME_OFFSET (proc_desc) = 0; | |
3300 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
c906108c SS |
3301 | mips_push_register (&sp, PC_REGNUM); |
3302 | mips_push_register (&sp, HI_REGNUM); | |
3303 | mips_push_register (&sp, LO_REGNUM); | |
3304 | mips_push_register (&sp, MIPS_FPU_TYPE == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM); | |
3305 | ||
3306 | /* Save general CPU registers */ | |
c5aa993b | 3307 | PROC_REG_MASK (proc_desc) = GEN_REG_SAVE_MASK; |
c906108c | 3308 | /* PROC_REG_OFFSET is the offset of the first saved register from FP. */ |
c5aa993b JM |
3309 | PROC_REG_OFFSET (proc_desc) = sp - old_sp - MIPS_SAVED_REGSIZE; |
3310 | for (ireg = 32; --ireg >= 0;) | |
3311 | if (PROC_REG_MASK (proc_desc) & (1 << ireg)) | |
c906108c SS |
3312 | mips_push_register (&sp, ireg); |
3313 | ||
3314 | /* Save floating point registers starting with high order word */ | |
c5aa993b | 3315 | PROC_FREG_MASK (proc_desc) = |
c906108c SS |
3316 | MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK |
3317 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0; | |
3318 | /* PROC_FREG_OFFSET is the offset of the first saved *double* register | |
3319 | from FP. */ | |
c5aa993b JM |
3320 | PROC_FREG_OFFSET (proc_desc) = sp - old_sp - 8; |
3321 | for (ireg = 32; --ireg >= 0;) | |
3322 | if (PROC_FREG_MASK (proc_desc) & (1 << ireg)) | |
c906108c SS |
3323 | mips_push_register (&sp, ireg + FP0_REGNUM); |
3324 | ||
3325 | /* Update the frame pointer for the call dummy and the stack pointer. | |
3326 | Set the procedure's starting and ending addresses to point to the | |
3327 | call dummy address at the entry point. */ | |
3328 | write_register (PUSH_FP_REGNUM, old_sp); | |
3329 | write_register (SP_REGNUM, sp); | |
c5aa993b JM |
3330 | PROC_LOW_ADDR (proc_desc) = CALL_DUMMY_ADDRESS (); |
3331 | PROC_HIGH_ADDR (proc_desc) = CALL_DUMMY_ADDRESS () + 4; | |
3332 | SET_PROC_DESC_IS_DUMMY (proc_desc); | |
3333 | PROC_PC_REG (proc_desc) = RA_REGNUM; | |
c906108c SS |
3334 | } |
3335 | ||
3336 | void | |
acdb74a0 | 3337 | mips_pop_frame (void) |
c906108c SS |
3338 | { |
3339 | register int regnum; | |
3340 | struct frame_info *frame = get_current_frame (); | |
3341 | CORE_ADDR new_sp = FRAME_FP (frame); | |
3342 | ||
cce74817 | 3343 | mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc; |
c906108c | 3344 | |
c5aa993b | 3345 | write_register (PC_REGNUM, FRAME_SAVED_PC (frame)); |
c906108c | 3346 | if (frame->saved_regs == NULL) |
ffabd70d | 3347 | FRAME_INIT_SAVED_REGS (frame); |
c906108c SS |
3348 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
3349 | { | |
3350 | if (regnum != SP_REGNUM && regnum != PC_REGNUM | |
3351 | && frame->saved_regs[regnum]) | |
3352 | write_register (regnum, | |
3353 | read_memory_integer (frame->saved_regs[regnum], | |
c5aa993b | 3354 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
3355 | } |
3356 | write_register (SP_REGNUM, new_sp); | |
3357 | flush_cached_frames (); | |
3358 | ||
c5aa993b | 3359 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
c906108c SS |
3360 | { |
3361 | struct linked_proc_info *pi_ptr, *prev_ptr; | |
3362 | ||
3363 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; | |
3364 | pi_ptr != NULL; | |
3365 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) | |
3366 | { | |
3367 | if (&pi_ptr->info == proc_desc) | |
3368 | break; | |
3369 | } | |
3370 | ||
3371 | if (pi_ptr == NULL) | |
3372 | error ("Can't locate dummy extra frame info\n"); | |
3373 | ||
3374 | if (prev_ptr != NULL) | |
3375 | prev_ptr->next = pi_ptr->next; | |
3376 | else | |
3377 | linked_proc_desc_table = pi_ptr->next; | |
3378 | ||
b8c9b27d | 3379 | xfree (pi_ptr); |
c906108c SS |
3380 | |
3381 | write_register (HI_REGNUM, | |
c5aa993b | 3382 | read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3383 | MIPS_SAVED_REGSIZE)); |
c906108c | 3384 | write_register (LO_REGNUM, |
c5aa993b | 3385 | read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3386 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
3387 | if (MIPS_FPU_TYPE != MIPS_FPU_NONE) |
3388 | write_register (FCRCS_REGNUM, | |
c5aa993b | 3389 | read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE, |
7a292a7a | 3390 | MIPS_SAVED_REGSIZE)); |
c906108c SS |
3391 | } |
3392 | } | |
3393 | ||
dd824b04 DJ |
3394 | /* Floating point register management. |
3395 | ||
3396 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
3397 | 64bit operations, these early MIPS cpus treat fp register pairs | |
3398 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
3399 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
3400 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
3401 | double precision floats into two 32-bit chunks and store them in | |
3402 | consecutive fp regs. To display 64-bit floats stored in this | |
3403 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
3404 | Throw in user-configurable endianness and you have a real mess. | |
3405 | ||
3406 | The way this works is: | |
3407 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
3408 | double-precision value will be split across two logical registers. | |
3409 | The lower-numbered logical register will hold the low-order bits, | |
3410 | regardless of the processor's endianness. | |
3411 | - If we are on a 64-bit processor, and we are looking for a | |
3412 | single-precision value, it will be in the low ordered bits | |
3413 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
3414 | save slot in memory. | |
3415 | - If we are in 64-bit mode, everything is straightforward. | |
3416 | ||
3417 | Note that this code only deals with "live" registers at the top of the | |
3418 | stack. We will attempt to deal with saved registers later, when | |
3419 | the raw/cooked register interface is in place. (We need a general | |
3420 | interface that can deal with dynamic saved register sizes -- fp | |
3421 | regs could be 32 bits wide in one frame and 64 on the frame above | |
3422 | and below). */ | |
3423 | ||
67b2c998 DJ |
3424 | static struct type * |
3425 | mips_float_register_type (void) | |
3426 | { | |
361d1df0 | 3427 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3428 | return builtin_type_ieee_single_big; |
3429 | else | |
3430 | return builtin_type_ieee_single_little; | |
3431 | } | |
3432 | ||
3433 | static struct type * | |
3434 | mips_double_register_type (void) | |
3435 | { | |
361d1df0 | 3436 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3437 | return builtin_type_ieee_double_big; |
3438 | else | |
3439 | return builtin_type_ieee_double_little; | |
3440 | } | |
3441 | ||
dd824b04 DJ |
3442 | /* Copy a 32-bit single-precision value from the current frame |
3443 | into rare_buffer. */ | |
3444 | ||
3445 | static void | |
3446 | mips_read_fp_register_single (int regno, char *rare_buffer) | |
3447 | { | |
3448 | int raw_size = REGISTER_RAW_SIZE (regno); | |
3449 | char *raw_buffer = alloca (raw_size); | |
3450 | ||
cda5a58a | 3451 | if (!frame_register_read (selected_frame, regno, raw_buffer)) |
dd824b04 DJ |
3452 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
3453 | if (raw_size == 8) | |
3454 | { | |
3455 | /* We have a 64-bit value for this register. Find the low-order | |
3456 | 32 bits. */ | |
3457 | int offset; | |
3458 | ||
3459 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3460 | offset = 4; | |
3461 | else | |
3462 | offset = 0; | |
3463 | ||
3464 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
3465 | } | |
3466 | else | |
3467 | { | |
3468 | memcpy (rare_buffer, raw_buffer, 4); | |
3469 | } | |
3470 | } | |
3471 | ||
3472 | /* Copy a 64-bit double-precision value from the current frame into | |
3473 | rare_buffer. This may include getting half of it from the next | |
3474 | register. */ | |
3475 | ||
3476 | static void | |
3477 | mips_read_fp_register_double (int regno, char *rare_buffer) | |
3478 | { | |
3479 | int raw_size = REGISTER_RAW_SIZE (regno); | |
3480 | ||
3481 | if (raw_size == 8 && !mips2_fp_compat ()) | |
3482 | { | |
3483 | /* We have a 64-bit value for this register, and we should use | |
3484 | all 64 bits. */ | |
cda5a58a | 3485 | if (!frame_register_read (selected_frame, regno, rare_buffer)) |
dd824b04 DJ |
3486 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
3487 | } | |
3488 | else | |
3489 | { | |
3490 | if ((regno - FP0_REGNUM) & 1) | |
3491 | internal_error (__FILE__, __LINE__, | |
3492 | "mips_read_fp_register_double: bad access to " | |
3493 | "odd-numbered FP register"); | |
3494 | ||
3495 | /* mips_read_fp_register_single will find the correct 32 bits from | |
3496 | each register. */ | |
3497 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3498 | { | |
3499 | mips_read_fp_register_single (regno, rare_buffer + 4); | |
3500 | mips_read_fp_register_single (regno + 1, rare_buffer); | |
3501 | } | |
361d1df0 | 3502 | else |
dd824b04 DJ |
3503 | { |
3504 | mips_read_fp_register_single (regno, rare_buffer); | |
3505 | mips_read_fp_register_single (regno + 1, rare_buffer + 4); | |
3506 | } | |
3507 | } | |
3508 | } | |
3509 | ||
c906108c | 3510 | static void |
acdb74a0 | 3511 | mips_print_register (int regnum, int all) |
c906108c | 3512 | { |
119d55d8 | 3513 | char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE); |
c906108c SS |
3514 | |
3515 | /* Get the data in raw format. */ | |
cda5a58a | 3516 | if (!frame_register_read (selected_frame, regnum, raw_buffer)) |
c906108c SS |
3517 | { |
3518 | printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum)); | |
3519 | return; | |
3520 | } | |
3521 | ||
dd824b04 DJ |
3522 | /* If we have a actual 32-bit floating point register (or we are in |
3523 | 32-bit compatibility mode), and the register is even-numbered, | |
3524 | also print it as a double (spanning two registers). */ | |
c906108c | 3525 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT |
dd824b04 DJ |
3526 | && (REGISTER_RAW_SIZE (regnum) == 4 |
3527 | || mips2_fp_compat ()) | |
c5aa993b | 3528 | && !((regnum - FP0_REGNUM) & 1)) |
dd824b04 | 3529 | { |
cb3d25d1 | 3530 | char *dbuffer = alloca (2 * MAX_REGISTER_RAW_SIZE); |
c906108c | 3531 | |
dd824b04 | 3532 | mips_read_fp_register_double (regnum, dbuffer); |
c906108c | 3533 | |
dd824b04 | 3534 | printf_filtered ("(d%d: ", regnum - FP0_REGNUM); |
67b2c998 | 3535 | val_print (mips_double_register_type (), dbuffer, 0, 0, |
dd824b04 DJ |
3536 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
3537 | printf_filtered ("); "); | |
3538 | } | |
c906108c SS |
3539 | fputs_filtered (REGISTER_NAME (regnum), gdb_stdout); |
3540 | ||
3541 | /* The problem with printing numeric register names (r26, etc.) is that | |
3542 | the user can't use them on input. Probably the best solution is to | |
3543 | fix it so that either the numeric or the funky (a2, etc.) names | |
3544 | are accepted on input. */ | |
3545 | if (regnum < MIPS_NUMREGS) | |
3546 | printf_filtered ("(r%d): ", regnum); | |
3547 | else | |
3548 | printf_filtered (": "); | |
3549 | ||
3550 | /* If virtual format is floating, print it that way. */ | |
3551 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) | |
dd824b04 DJ |
3552 | if (REGISTER_RAW_SIZE (regnum) == 8 && !mips2_fp_compat ()) |
3553 | { | |
3554 | /* We have a meaningful 64-bit value in this register. Show | |
3555 | it as a 32-bit float and a 64-bit double. */ | |
d7449b42 | 3556 | int offset = 4 * (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG); |
c906108c SS |
3557 | |
3558 | printf_filtered (" (float) "); | |
67b2c998 | 3559 | val_print (mips_float_register_type (), raw_buffer + offset, 0, 0, |
c906108c SS |
3560 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
3561 | printf_filtered (", (double) "); | |
67b2c998 | 3562 | val_print (mips_double_register_type (), raw_buffer, 0, 0, |
c906108c SS |
3563 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
3564 | } | |
3565 | else | |
3566 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0, | |
3567 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
3568 | /* Else print as integer in hex. */ | |
3569 | else | |
ed9a39eb JM |
3570 | { |
3571 | int offset; | |
3572 | ||
d7449b42 | 3573 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
ed9a39eb JM |
3574 | offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); |
3575 | else | |
3576 | offset = 0; | |
361d1df0 | 3577 | |
ed9a39eb JM |
3578 | print_scalar_formatted (raw_buffer + offset, |
3579 | REGISTER_VIRTUAL_TYPE (regnum), | |
3580 | 'x', 0, gdb_stdout); | |
3581 | } | |
c906108c SS |
3582 | } |
3583 | ||
361d1df0 | 3584 | /* Replacement for generic do_registers_info. |
c906108c SS |
3585 | Print regs in pretty columns. */ |
3586 | ||
3587 | static int | |
acdb74a0 | 3588 | do_fp_register_row (int regnum) |
c5aa993b | 3589 | { /* do values for FP (float) regs */ |
dd824b04 | 3590 | char *raw_buffer; |
c906108c SS |
3591 | double doub, flt1, flt2; /* doubles extracted from raw hex data */ |
3592 | int inv1, inv2, inv3; | |
c5aa993b | 3593 | |
dd824b04 | 3594 | raw_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM)); |
c906108c | 3595 | |
dd824b04 | 3596 | if (REGISTER_RAW_SIZE (regnum) == 4 || mips2_fp_compat ()) |
c906108c | 3597 | { |
dd824b04 DJ |
3598 | /* 4-byte registers: we can fit two registers per row. */ |
3599 | /* Also print every pair of 4-byte regs as an 8-byte double. */ | |
3600 | mips_read_fp_register_single (regnum, raw_buffer); | |
67b2c998 | 3601 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 3602 | |
dd824b04 | 3603 | mips_read_fp_register_single (regnum + 1, raw_buffer); |
67b2c998 | 3604 | flt2 = unpack_double (mips_float_register_type (), raw_buffer, &inv2); |
dd824b04 DJ |
3605 | |
3606 | mips_read_fp_register_double (regnum, raw_buffer); | |
67b2c998 | 3607 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3); |
361d1df0 | 3608 | |
1adad886 AC |
3609 | printf_filtered (" %-5s", REGISTER_NAME (regnum)); |
3610 | if (inv1) | |
3611 | printf_filtered (": <invalid float>"); | |
3612 | else | |
3613 | printf_filtered ("%-17.9g", flt1); | |
3614 | ||
3615 | printf_filtered (" %-5s", REGISTER_NAME (regnum + 1)); | |
3616 | if (inv2) | |
3617 | printf_filtered (": <invalid float>"); | |
3618 | else | |
3619 | printf_filtered ("%-17.9g", flt2); | |
3620 | ||
3621 | printf_filtered (" dbl: "); | |
3622 | if (inv3) | |
3623 | printf_filtered ("<invalid double>"); | |
3624 | else | |
3625 | printf_filtered ("%-24.17g", doub); | |
3626 | printf_filtered ("\n"); | |
3627 | ||
c906108c | 3628 | /* may want to do hex display here (future enhancement) */ |
c5aa993b | 3629 | regnum += 2; |
c906108c SS |
3630 | } |
3631 | else | |
dd824b04 DJ |
3632 | { |
3633 | /* Eight byte registers: print each one as float AND as double. */ | |
3634 | mips_read_fp_register_single (regnum, raw_buffer); | |
67b2c998 | 3635 | flt1 = unpack_double (mips_double_register_type (), raw_buffer, &inv1); |
c906108c | 3636 | |
dd824b04 | 3637 | mips_read_fp_register_double (regnum, raw_buffer); |
67b2c998 | 3638 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3); |
361d1df0 | 3639 | |
1adad886 AC |
3640 | printf_filtered (" %-5s: ", REGISTER_NAME (regnum)); |
3641 | if (inv1) | |
3642 | printf_filtered ("<invalid float>"); | |
3643 | else | |
3644 | printf_filtered ("flt: %-17.9g", flt1); | |
3645 | ||
3646 | printf_filtered (" dbl: "); | |
3647 | if (inv3) | |
3648 | printf_filtered ("<invalid double>"); | |
3649 | else | |
3650 | printf_filtered ("%-24.17g", doub); | |
3651 | ||
3652 | printf_filtered ("\n"); | |
c906108c SS |
3653 | /* may want to do hex display here (future enhancement) */ |
3654 | regnum++; | |
3655 | } | |
3656 | return regnum; | |
3657 | } | |
3658 | ||
3659 | /* Print a row's worth of GP (int) registers, with name labels above */ | |
3660 | ||
3661 | static int | |
acdb74a0 | 3662 | do_gp_register_row (int regnum) |
c906108c SS |
3663 | { |
3664 | /* do values for GP (int) regs */ | |
cb3d25d1 | 3665 | char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE); |
c906108c SS |
3666 | int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */ |
3667 | int col, byte; | |
3668 | int start_regnum = regnum; | |
3669 | int numregs = NUM_REGS; | |
3670 | ||
3671 | ||
3672 | /* For GP registers, we print a separate row of names above the vals */ | |
3673 | printf_filtered (" "); | |
3674 | for (col = 0; col < ncols && regnum < numregs; regnum++) | |
3675 | { | |
3676 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 3677 | continue; /* unused register */ |
c906108c | 3678 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
c5aa993b JM |
3679 | break; /* end the row: reached FP register */ |
3680 | printf_filtered (MIPS_REGSIZE == 8 ? "%17s" : "%9s", | |
c906108c SS |
3681 | REGISTER_NAME (regnum)); |
3682 | col++; | |
3683 | } | |
c5aa993b | 3684 | printf_filtered (start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ", |
c906108c SS |
3685 | start_regnum); /* print the R0 to R31 names */ |
3686 | ||
3687 | regnum = start_regnum; /* go back to start of row */ | |
3688 | /* now print the values in hex, 4 or 8 to the row */ | |
3689 | for (col = 0; col < ncols && regnum < numregs; regnum++) | |
3690 | { | |
3691 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 3692 | continue; /* unused register */ |
c906108c | 3693 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
c5aa993b | 3694 | break; /* end row: reached FP register */ |
c906108c | 3695 | /* OK: get the data in raw format. */ |
cda5a58a | 3696 | if (!frame_register_read (selected_frame, regnum, raw_buffer)) |
c906108c SS |
3697 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
3698 | /* pad small registers */ | |
43e526b9 | 3699 | for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++) |
c906108c SS |
3700 | printf_filtered (" "); |
3701 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 3702 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
43e526b9 JM |
3703 | for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); |
3704 | byte < REGISTER_RAW_SIZE (regnum); | |
3705 | byte++) | |
c906108c SS |
3706 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); |
3707 | else | |
43e526b9 JM |
3708 | for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1; |
3709 | byte >= 0; | |
3710 | byte--) | |
c906108c SS |
3711 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); |
3712 | printf_filtered (" "); | |
3713 | col++; | |
3714 | } | |
c5aa993b | 3715 | if (col > 0) /* ie. if we actually printed anything... */ |
c906108c SS |
3716 | printf_filtered ("\n"); |
3717 | ||
3718 | return regnum; | |
3719 | } | |
3720 | ||
3721 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
3722 | ||
3723 | void | |
acdb74a0 | 3724 | mips_do_registers_info (int regnum, int fpregs) |
c906108c | 3725 | { |
c5aa993b | 3726 | if (regnum != -1) /* do one specified register */ |
c906108c SS |
3727 | { |
3728 | if (*(REGISTER_NAME (regnum)) == '\0') | |
3729 | error ("Not a valid register for the current processor type"); | |
3730 | ||
3731 | mips_print_register (regnum, 0); | |
3732 | printf_filtered ("\n"); | |
3733 | } | |
c5aa993b JM |
3734 | else |
3735 | /* do all (or most) registers */ | |
c906108c SS |
3736 | { |
3737 | regnum = 0; | |
3738 | while (regnum < NUM_REGS) | |
3739 | { | |
c5aa993b JM |
3740 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
3741 | if (fpregs) /* true for "INFO ALL-REGISTERS" command */ | |
c906108c SS |
3742 | regnum = do_fp_register_row (regnum); /* FP regs */ |
3743 | else | |
3744 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
3745 | else | |
3746 | regnum = do_gp_register_row (regnum); /* GP (int) regs */ | |
3747 | } | |
3748 | } | |
3749 | } | |
3750 | ||
3751 | /* Return number of args passed to a frame. described by FIP. | |
3752 | Can return -1, meaning no way to tell. */ | |
3753 | ||
3754 | int | |
acdb74a0 | 3755 | mips_frame_num_args (struct frame_info *frame) |
c906108c | 3756 | { |
c906108c SS |
3757 | return -1; |
3758 | } | |
3759 | ||
3760 | /* Is this a branch with a delay slot? */ | |
3761 | ||
a14ed312 | 3762 | static int is_delayed (unsigned long); |
c906108c SS |
3763 | |
3764 | static int | |
acdb74a0 | 3765 | is_delayed (unsigned long insn) |
c906108c SS |
3766 | { |
3767 | int i; | |
3768 | for (i = 0; i < NUMOPCODES; ++i) | |
3769 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
3770 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
3771 | break; | |
3772 | return (i < NUMOPCODES | |
3773 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
3774 | | INSN_COND_BRANCH_DELAY | |
3775 | | INSN_COND_BRANCH_LIKELY))); | |
3776 | } | |
3777 | ||
3778 | int | |
acdb74a0 | 3779 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c SS |
3780 | { |
3781 | char buf[MIPS_INSTLEN]; | |
3782 | ||
3783 | /* There is no branch delay slot on MIPS16. */ | |
3784 | if (pc_is_mips16 (pc)) | |
3785 | return 0; | |
3786 | ||
3787 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) | |
3788 | /* If error reading memory, guess that it is not a delayed branch. */ | |
3789 | return 0; | |
c5aa993b | 3790 | return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN)); |
c906108c SS |
3791 | } |
3792 | ||
3793 | ||
3794 | /* Skip the PC past function prologue instructions (32-bit version). | |
3795 | This is a helper function for mips_skip_prologue. */ | |
3796 | ||
3797 | static CORE_ADDR | |
f7b9e9fc | 3798 | mips32_skip_prologue (CORE_ADDR pc) |
c906108c | 3799 | { |
c5aa993b JM |
3800 | t_inst inst; |
3801 | CORE_ADDR end_pc; | |
3802 | int seen_sp_adjust = 0; | |
3803 | int load_immediate_bytes = 0; | |
3804 | ||
3805 | /* Skip the typical prologue instructions. These are the stack adjustment | |
3806 | instruction and the instructions that save registers on the stack | |
3807 | or in the gcc frame. */ | |
3808 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN) | |
3809 | { | |
3810 | unsigned long high_word; | |
c906108c | 3811 | |
c5aa993b JM |
3812 | inst = mips_fetch_instruction (pc); |
3813 | high_word = (inst >> 16) & 0xffff; | |
c906108c | 3814 | |
c5aa993b JM |
3815 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
3816 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ | |
3817 | seen_sp_adjust = 1; | |
3818 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ | |
3819 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ | |
3820 | seen_sp_adjust = 1; | |
3821 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ | |
3822 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ | |
3823 | && (inst & 0x001F0000)) /* reg != $zero */ | |
3824 | continue; | |
3825 | ||
3826 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ | |
3827 | continue; | |
3828 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) | |
3829 | /* sx reg,n($s8) */ | |
3830 | continue; /* reg != $zero */ | |
3831 | ||
3832 | /* move $s8,$sp. With different versions of gas this will be either | |
3833 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. | |
3834 | Accept any one of these. */ | |
3835 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
3836 | continue; | |
3837 | ||
3838 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ | |
3839 | continue; | |
3840 | else if (high_word == 0x3c1c) /* lui $gp,n */ | |
3841 | continue; | |
3842 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ | |
3843 | continue; | |
3844 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
3845 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ | |
3846 | continue; | |
3847 | /* The following instructions load $at or $t0 with an immediate | |
3848 | value in preparation for a stack adjustment via | |
3849 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize | |
3850 | a local variable, so we accept them only before a stack adjustment | |
3851 | instruction was seen. */ | |
3852 | else if (!seen_sp_adjust) | |
3853 | { | |
3854 | if (high_word == 0x3c01 || /* lui $at,n */ | |
3855 | high_word == 0x3c08) /* lui $t0,n */ | |
3856 | { | |
3857 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
3858 | continue; | |
3859 | } | |
3860 | else if (high_word == 0x3421 || /* ori $at,$at,n */ | |
3861 | high_word == 0x3508 || /* ori $t0,$t0,n */ | |
3862 | high_word == 0x3401 || /* ori $at,$zero,n */ | |
3863 | high_word == 0x3408) /* ori $t0,$zero,n */ | |
3864 | { | |
3865 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ | |
3866 | continue; | |
3867 | } | |
3868 | else | |
3869 | break; | |
3870 | } | |
3871 | else | |
3872 | break; | |
c906108c SS |
3873 | } |
3874 | ||
c5aa993b JM |
3875 | /* In a frameless function, we might have incorrectly |
3876 | skipped some load immediate instructions. Undo the skipping | |
3877 | if the load immediate was not followed by a stack adjustment. */ | |
3878 | if (load_immediate_bytes && !seen_sp_adjust) | |
3879 | pc -= load_immediate_bytes; | |
3880 | return pc; | |
c906108c SS |
3881 | } |
3882 | ||
3883 | /* Skip the PC past function prologue instructions (16-bit version). | |
3884 | This is a helper function for mips_skip_prologue. */ | |
3885 | ||
3886 | static CORE_ADDR | |
f7b9e9fc | 3887 | mips16_skip_prologue (CORE_ADDR pc) |
c906108c | 3888 | { |
c5aa993b JM |
3889 | CORE_ADDR end_pc; |
3890 | int extend_bytes = 0; | |
3891 | int prev_extend_bytes; | |
c906108c | 3892 | |
c5aa993b JM |
3893 | /* Table of instructions likely to be found in a function prologue. */ |
3894 | static struct | |
c906108c SS |
3895 | { |
3896 | unsigned short inst; | |
3897 | unsigned short mask; | |
c5aa993b JM |
3898 | } |
3899 | table[] = | |
3900 | { | |
c906108c | 3901 | { |
c5aa993b JM |
3902 | 0x6300, 0xff00 |
3903 | } | |
3904 | , /* addiu $sp,offset */ | |
3905 | { | |
3906 | 0xfb00, 0xff00 | |
3907 | } | |
3908 | , /* daddiu $sp,offset */ | |
3909 | { | |
3910 | 0xd000, 0xf800 | |
3911 | } | |
3912 | , /* sw reg,n($sp) */ | |
3913 | { | |
3914 | 0xf900, 0xff00 | |
3915 | } | |
3916 | , /* sd reg,n($sp) */ | |
3917 | { | |
3918 | 0x6200, 0xff00 | |
3919 | } | |
3920 | , /* sw $ra,n($sp) */ | |
3921 | { | |
3922 | 0xfa00, 0xff00 | |
3923 | } | |
3924 | , /* sd $ra,n($sp) */ | |
3925 | { | |
3926 | 0x673d, 0xffff | |
3927 | } | |
3928 | , /* move $s1,sp */ | |
3929 | { | |
3930 | 0xd980, 0xff80 | |
3931 | } | |
3932 | , /* sw $a0-$a3,n($s1) */ | |
3933 | { | |
3934 | 0x6704, 0xff1c | |
3935 | } | |
3936 | , /* move reg,$a0-$a3 */ | |
3937 | { | |
3938 | 0xe809, 0xf81f | |
3939 | } | |
3940 | , /* entry pseudo-op */ | |
3941 | { | |
3942 | 0x0100, 0xff00 | |
3943 | } | |
3944 | , /* addiu $s1,$sp,n */ | |
3945 | { | |
3946 | 0, 0 | |
3947 | } /* end of table marker */ | |
3948 | }; | |
3949 | ||
3950 | /* Skip the typical prologue instructions. These are the stack adjustment | |
3951 | instruction and the instructions that save registers on the stack | |
3952 | or in the gcc frame. */ | |
3953 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN) | |
3954 | { | |
3955 | unsigned short inst; | |
3956 | int i; | |
c906108c | 3957 | |
c5aa993b | 3958 | inst = mips_fetch_instruction (pc); |
c906108c | 3959 | |
c5aa993b JM |
3960 | /* Normally we ignore an extend instruction. However, if it is |
3961 | not followed by a valid prologue instruction, we must adjust | |
3962 | the pc back over the extend so that it won't be considered | |
3963 | part of the prologue. */ | |
3964 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
3965 | { | |
3966 | extend_bytes = MIPS16_INSTLEN; | |
3967 | continue; | |
3968 | } | |
3969 | prev_extend_bytes = extend_bytes; | |
3970 | extend_bytes = 0; | |
c906108c | 3971 | |
c5aa993b JM |
3972 | /* Check for other valid prologue instructions besides extend. */ |
3973 | for (i = 0; table[i].mask != 0; i++) | |
3974 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ | |
3975 | break; | |
3976 | if (table[i].mask != 0) /* it was in table? */ | |
3977 | continue; /* ignore it */ | |
3978 | else | |
3979 | /* non-prologue */ | |
3980 | { | |
3981 | /* Return the current pc, adjusted backwards by 2 if | |
3982 | the previous instruction was an extend. */ | |
3983 | return pc - prev_extend_bytes; | |
3984 | } | |
c906108c SS |
3985 | } |
3986 | return pc; | |
3987 | } | |
3988 | ||
3989 | /* To skip prologues, I use this predicate. Returns either PC itself | |
3990 | if the code at PC does not look like a function prologue; otherwise | |
3991 | returns an address that (if we're lucky) follows the prologue. If | |
3992 | LENIENT, then we must skip everything which is involved in setting | |
3993 | up the frame (it's OK to skip more, just so long as we don't skip | |
3994 | anything which might clobber the registers which are being saved. | |
3995 | We must skip more in the case where part of the prologue is in the | |
3996 | delay slot of a non-prologue instruction). */ | |
3997 | ||
3998 | CORE_ADDR | |
f7b9e9fc | 3999 | mips_skip_prologue (CORE_ADDR pc) |
c906108c SS |
4000 | { |
4001 | /* See if we can determine the end of the prologue via the symbol table. | |
4002 | If so, then return either PC, or the PC after the prologue, whichever | |
4003 | is greater. */ | |
4004 | ||
4005 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); | |
4006 | ||
4007 | if (post_prologue_pc != 0) | |
4008 | return max (pc, post_prologue_pc); | |
4009 | ||
4010 | /* Can't determine prologue from the symbol table, need to examine | |
4011 | instructions. */ | |
4012 | ||
4013 | if (pc_is_mips16 (pc)) | |
f7b9e9fc | 4014 | return mips16_skip_prologue (pc); |
c906108c | 4015 | else |
f7b9e9fc | 4016 | return mips32_skip_prologue (pc); |
c906108c | 4017 | } |
c906108c | 4018 | |
7a292a7a SS |
4019 | /* Determine how a return value is stored within the MIPS register |
4020 | file, given the return type `valtype'. */ | |
4021 | ||
4022 | struct return_value_word | |
4023 | { | |
4024 | int len; | |
4025 | int reg; | |
4026 | int reg_offset; | |
4027 | int buf_offset; | |
4028 | }; | |
4029 | ||
7a292a7a | 4030 | static void |
acdb74a0 AC |
4031 | return_value_location (struct type *valtype, |
4032 | struct return_value_word *hi, | |
4033 | struct return_value_word *lo) | |
7a292a7a SS |
4034 | { |
4035 | int len = TYPE_LENGTH (valtype); | |
c5aa993b | 4036 | |
7a292a7a SS |
4037 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT |
4038 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) | |
4039 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) | |
4040 | { | |
4041 | if (!FP_REGISTER_DOUBLE && len == 8) | |
4042 | { | |
4043 | /* We need to break a 64bit float in two 32 bit halves and | |
c5aa993b | 4044 | spread them across a floating-point register pair. */ |
d7449b42 AC |
4045 | lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
4046 | hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4; | |
4047 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
7a292a7a SS |
4048 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8) |
4049 | ? 4 : 0); | |
4050 | hi->reg_offset = lo->reg_offset; | |
4051 | lo->reg = FP0_REGNUM + 0; | |
4052 | hi->reg = FP0_REGNUM + 1; | |
4053 | lo->len = 4; | |
4054 | hi->len = 4; | |
4055 | } | |
4056 | else | |
4057 | { | |
4058 | /* The floating point value fits in a single floating-point | |
c5aa993b | 4059 | register. */ |
d7449b42 | 4060 | lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4061 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8 |
4062 | && len == 4) | |
4063 | ? 4 : 0); | |
4064 | lo->reg = FP0_REGNUM; | |
4065 | lo->len = len; | |
4066 | lo->buf_offset = 0; | |
4067 | hi->len = 0; | |
4068 | hi->reg_offset = 0; | |
4069 | hi->buf_offset = 0; | |
4070 | hi->reg = 0; | |
4071 | } | |
4072 | } | |
4073 | else | |
4074 | { | |
4075 | /* Locate a result possibly spread across two registers. */ | |
4076 | int regnum = 2; | |
4077 | lo->reg = regnum + 0; | |
4078 | hi->reg = regnum + 1; | |
d7449b42 | 4079 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4080 | && len < MIPS_SAVED_REGSIZE) |
4081 | { | |
4082 | /* "un-left-justify" the value in the low register */ | |
4083 | lo->reg_offset = MIPS_SAVED_REGSIZE - len; | |
4084 | lo->len = len; | |
4085 | hi->reg_offset = 0; | |
4086 | hi->len = 0; | |
4087 | } | |
d7449b42 | 4088 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4089 | && len > MIPS_SAVED_REGSIZE /* odd-size structs */ |
4090 | && len < MIPS_SAVED_REGSIZE * 2 | |
4091 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || | |
4092 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) | |
4093 | { | |
4094 | /* "un-left-justify" the value spread across two registers. */ | |
4095 | lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len; | |
4096 | lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset; | |
4097 | hi->reg_offset = 0; | |
4098 | hi->len = len - lo->len; | |
4099 | } | |
4100 | else | |
4101 | { | |
4102 | /* Only perform a partial copy of the second register. */ | |
4103 | lo->reg_offset = 0; | |
4104 | hi->reg_offset = 0; | |
4105 | if (len > MIPS_SAVED_REGSIZE) | |
4106 | { | |
4107 | lo->len = MIPS_SAVED_REGSIZE; | |
4108 | hi->len = len - MIPS_SAVED_REGSIZE; | |
4109 | } | |
4110 | else | |
4111 | { | |
4112 | lo->len = len; | |
4113 | hi->len = 0; | |
4114 | } | |
4115 | } | |
d7449b42 | 4116 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
7a292a7a SS |
4117 | && REGISTER_RAW_SIZE (regnum) == 8 |
4118 | && MIPS_SAVED_REGSIZE == 4) | |
4119 | { | |
4120 | /* Account for the fact that only the least-signficant part | |
c5aa993b | 4121 | of the register is being used */ |
7a292a7a SS |
4122 | lo->reg_offset += 4; |
4123 | hi->reg_offset += 4; | |
4124 | } | |
4125 | lo->buf_offset = 0; | |
4126 | hi->buf_offset = lo->len; | |
4127 | } | |
4128 | } | |
4129 | ||
4130 | /* Given a return value in `regbuf' with a type `valtype', extract and | |
4131 | copy its value into `valbuf'. */ | |
4132 | ||
c906108c | 4133 | void |
acdb74a0 AC |
4134 | mips_extract_return_value (struct type *valtype, |
4135 | char regbuf[REGISTER_BYTES], | |
4136 | char *valbuf) | |
c906108c | 4137 | { |
7a292a7a SS |
4138 | struct return_value_word lo; |
4139 | struct return_value_word hi; | |
99567b1b | 4140 | return_value_location (valtype, &hi, &lo); |
7a292a7a SS |
4141 | |
4142 | memcpy (valbuf + lo.buf_offset, | |
4143 | regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset, | |
4144 | lo.len); | |
4145 | ||
4146 | if (hi.len > 0) | |
4147 | memcpy (valbuf + hi.buf_offset, | |
4148 | regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset, | |
4149 | hi.len); | |
c906108c SS |
4150 | } |
4151 | ||
7a292a7a SS |
4152 | /* Given a return value in `valbuf' with a type `valtype', write it's |
4153 | value into the appropriate register. */ | |
4154 | ||
c906108c | 4155 | void |
acdb74a0 | 4156 | mips_store_return_value (struct type *valtype, char *valbuf) |
c906108c | 4157 | { |
cb3d25d1 | 4158 | char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE); |
7a292a7a SS |
4159 | struct return_value_word lo; |
4160 | struct return_value_word hi; | |
99567b1b | 4161 | return_value_location (valtype, &hi, &lo); |
7a292a7a SS |
4162 | |
4163 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4164 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); | |
4165 | write_register_bytes (REGISTER_BYTE (lo.reg), | |
4166 | raw_buffer, | |
4167 | REGISTER_RAW_SIZE (lo.reg)); | |
c5aa993b | 4168 | |
7a292a7a SS |
4169 | if (hi.len > 0) |
4170 | { | |
4171 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
4172 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); | |
4173 | write_register_bytes (REGISTER_BYTE (hi.reg), | |
4174 | raw_buffer, | |
4175 | REGISTER_RAW_SIZE (hi.reg)); | |
4176 | } | |
c906108c SS |
4177 | } |
4178 | ||
4179 | /* Exported procedure: Is PC in the signal trampoline code */ | |
4180 | ||
4181 | int | |
acdb74a0 | 4182 | in_sigtramp (CORE_ADDR pc, char *ignore) |
c906108c SS |
4183 | { |
4184 | if (sigtramp_address == 0) | |
4185 | fixup_sigtramp (); | |
4186 | return (pc >= sigtramp_address && pc < sigtramp_end); | |
4187 | } | |
4188 | ||
a5ea2558 AC |
4189 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4190 | used for all MIPS-specific commands. */ | |
4191 | ||
a5ea2558 | 4192 | static void |
acdb74a0 | 4193 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4194 | { |
4195 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4196 | } | |
4197 | ||
a5ea2558 | 4198 | static void |
acdb74a0 | 4199 | set_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4200 | { |
4201 | printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
4202 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); | |
4203 | } | |
4204 | ||
c906108c SS |
4205 | /* Commands to show/set the MIPS FPU type. */ |
4206 | ||
c906108c | 4207 | static void |
acdb74a0 | 4208 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4209 | { |
c906108c SS |
4210 | char *fpu; |
4211 | switch (MIPS_FPU_TYPE) | |
4212 | { | |
4213 | case MIPS_FPU_SINGLE: | |
4214 | fpu = "single-precision"; | |
4215 | break; | |
4216 | case MIPS_FPU_DOUBLE: | |
4217 | fpu = "double-precision"; | |
4218 | break; | |
4219 | case MIPS_FPU_NONE: | |
4220 | fpu = "absent (none)"; | |
4221 | break; | |
93d56215 AC |
4222 | default: |
4223 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
4224 | } |
4225 | if (mips_fpu_type_auto) | |
4226 | printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4227 | fpu); | |
4228 | else | |
4229 | printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n", | |
4230 | fpu); | |
4231 | } | |
4232 | ||
4233 | ||
c906108c | 4234 | static void |
acdb74a0 | 4235 | set_mipsfpu_command (char *args, int from_tty) |
c906108c SS |
4236 | { |
4237 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
4238 | show_mipsfpu_command (args, from_tty); | |
4239 | } | |
4240 | ||
c906108c | 4241 | static void |
acdb74a0 | 4242 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c SS |
4243 | { |
4244 | mips_fpu_type = MIPS_FPU_SINGLE; | |
4245 | mips_fpu_type_auto = 0; | |
9e364162 | 4246 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE; |
c906108c SS |
4247 | } |
4248 | ||
c906108c | 4249 | static void |
acdb74a0 | 4250 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c SS |
4251 | { |
4252 | mips_fpu_type = MIPS_FPU_DOUBLE; | |
4253 | mips_fpu_type_auto = 0; | |
9e364162 | 4254 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE; |
c906108c SS |
4255 | } |
4256 | ||
c906108c | 4257 | static void |
acdb74a0 | 4258 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c SS |
4259 | { |
4260 | mips_fpu_type = MIPS_FPU_NONE; | |
4261 | mips_fpu_type_auto = 0; | |
9e364162 | 4262 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE; |
c906108c SS |
4263 | } |
4264 | ||
c906108c | 4265 | static void |
acdb74a0 | 4266 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
4267 | { |
4268 | mips_fpu_type_auto = 1; | |
4269 | } | |
4270 | ||
4271 | /* Command to set the processor type. */ | |
4272 | ||
4273 | void | |
acdb74a0 | 4274 | mips_set_processor_type_command (char *args, int from_tty) |
c906108c SS |
4275 | { |
4276 | int i; | |
4277 | ||
4278 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') | |
4279 | { | |
4280 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); | |
4281 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
4282 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); | |
4283 | ||
4284 | /* Restore the value. */ | |
4fcf66da | 4285 | tmp_mips_processor_type = xstrdup (mips_processor_type); |
c906108c SS |
4286 | |
4287 | return; | |
4288 | } | |
c5aa993b | 4289 | |
c906108c SS |
4290 | if (!mips_set_processor_type (tmp_mips_processor_type)) |
4291 | { | |
4292 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); | |
4293 | /* Restore its value. */ | |
4fcf66da | 4294 | tmp_mips_processor_type = xstrdup (mips_processor_type); |
c906108c SS |
4295 | } |
4296 | } | |
4297 | ||
4298 | static void | |
acdb74a0 | 4299 | mips_show_processor_type_command (char *args, int from_tty) |
c906108c SS |
4300 | { |
4301 | } | |
4302 | ||
4303 | /* Modify the actual processor type. */ | |
4304 | ||
4305 | int | |
acdb74a0 | 4306 | mips_set_processor_type (char *str) |
c906108c | 4307 | { |
1012bd0e | 4308 | int i; |
c906108c SS |
4309 | |
4310 | if (str == NULL) | |
4311 | return 0; | |
4312 | ||
4313 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) | |
4314 | { | |
4315 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) | |
4316 | { | |
4317 | mips_processor_type = str; | |
cce74817 | 4318 | mips_processor_reg_names = mips_processor_type_table[i].regnames; |
c906108c | 4319 | return 1; |
c906108c SS |
4320 | /* FIXME tweak fpu flag too */ |
4321 | } | |
4322 | } | |
4323 | ||
4324 | return 0; | |
4325 | } | |
4326 | ||
4327 | /* Attempt to identify the particular processor model by reading the | |
4328 | processor id. */ | |
4329 | ||
4330 | char * | |
acdb74a0 | 4331 | mips_read_processor_type (void) |
c906108c SS |
4332 | { |
4333 | CORE_ADDR prid; | |
4334 | ||
4335 | prid = read_register (PRID_REGNUM); | |
4336 | ||
4337 | if ((prid & ~0xf) == 0x700) | |
c5aa993b | 4338 | return savestring ("r3041", strlen ("r3041")); |
c906108c SS |
4339 | |
4340 | return NULL; | |
4341 | } | |
4342 | ||
4343 | /* Just like reinit_frame_cache, but with the right arguments to be | |
4344 | callable as an sfunc. */ | |
4345 | ||
4346 | static void | |
acdb74a0 AC |
4347 | reinit_frame_cache_sfunc (char *args, int from_tty, |
4348 | struct cmd_list_element *c) | |
c906108c SS |
4349 | { |
4350 | reinit_frame_cache (); | |
4351 | } | |
4352 | ||
4353 | int | |
acdb74a0 | 4354 | gdb_print_insn_mips (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
4355 | { |
4356 | mips_extra_func_info_t proc_desc; | |
4357 | ||
4358 | /* Search for the function containing this address. Set the low bit | |
4359 | of the address when searching, in case we were given an even address | |
4360 | that is the start of a 16-bit function. If we didn't do this, | |
4361 | the search would fail because the symbol table says the function | |
4362 | starts at an odd address, i.e. 1 byte past the given address. */ | |
4363 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
4364 | proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL); | |
4365 | ||
4366 | /* Make an attempt to determine if this is a 16-bit function. If | |
4367 | the procedure descriptor exists and the address therein is odd, | |
4368 | it's definitely a 16-bit function. Otherwise, we have to just | |
4369 | guess that if the address passed in is odd, it's 16-bits. */ | |
4370 | if (proc_desc) | |
361d1df0 | 4371 | info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ? |
65c11066 | 4372 | bfd_mach_mips16 : TM_PRINT_INSN_MACH; |
c906108c | 4373 | else |
361d1df0 | 4374 | info->mach = pc_is_mips16 (memaddr) ? |
65c11066 | 4375 | bfd_mach_mips16 : TM_PRINT_INSN_MACH; |
c906108c SS |
4376 | |
4377 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 4378 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 4379 | |
c906108c | 4380 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 4381 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
4382 | return print_insn_big_mips (memaddr, info); |
4383 | else | |
4384 | return print_insn_little_mips (memaddr, info); | |
4385 | } | |
4386 | ||
4387 | /* Old-style breakpoint macros. | |
4388 | The IDT board uses an unusual breakpoint value, and sometimes gets | |
4389 | confused when it sees the usual MIPS breakpoint instruction. */ | |
4390 | ||
4391 | #define BIG_BREAKPOINT {0, 0x5, 0, 0xd} | |
4392 | #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0} | |
4393 | #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd} | |
4394 | #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0} | |
4395 | #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd} | |
4396 | #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0} | |
4397 | #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5} | |
4398 | #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8} | |
4399 | ||
4400 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program | |
4401 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
4402 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
4403 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
4404 | (if necessary) to point to the actual memory location where the | |
4405 | breakpoint should be inserted. */ | |
4406 | ||
f4f9705a | 4407 | const unsigned char * |
acdb74a0 | 4408 | mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) |
c906108c | 4409 | { |
d7449b42 | 4410 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
4411 | { |
4412 | if (pc_is_mips16 (*pcptr)) | |
4413 | { | |
1012bd0e EZ |
4414 | static unsigned char mips16_big_breakpoint[] = |
4415 | MIPS16_BIG_BREAKPOINT; | |
c906108c | 4416 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
c5aa993b | 4417 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
4418 | return mips16_big_breakpoint; |
4419 | } | |
4420 | else | |
4421 | { | |
1012bd0e EZ |
4422 | static unsigned char big_breakpoint[] = BIG_BREAKPOINT; |
4423 | static unsigned char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT; | |
4424 | static unsigned char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT; | |
c906108c | 4425 | |
c5aa993b | 4426 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
4427 | |
4428 | if (strcmp (target_shortname, "mips") == 0) | |
4429 | return idt_big_breakpoint; | |
4430 | else if (strcmp (target_shortname, "ddb") == 0 | |
4431 | || strcmp (target_shortname, "pmon") == 0 | |
4432 | || strcmp (target_shortname, "lsi") == 0) | |
4433 | return pmon_big_breakpoint; | |
4434 | else | |
4435 | return big_breakpoint; | |
4436 | } | |
4437 | } | |
4438 | else | |
4439 | { | |
4440 | if (pc_is_mips16 (*pcptr)) | |
4441 | { | |
1012bd0e EZ |
4442 | static unsigned char mips16_little_breakpoint[] = |
4443 | MIPS16_LITTLE_BREAKPOINT; | |
c906108c | 4444 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
c5aa993b | 4445 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
4446 | return mips16_little_breakpoint; |
4447 | } | |
4448 | else | |
4449 | { | |
1012bd0e EZ |
4450 | static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT; |
4451 | static unsigned char pmon_little_breakpoint[] = | |
4452 | PMON_LITTLE_BREAKPOINT; | |
4453 | static unsigned char idt_little_breakpoint[] = | |
4454 | IDT_LITTLE_BREAKPOINT; | |
c906108c | 4455 | |
c5aa993b | 4456 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
4457 | |
4458 | if (strcmp (target_shortname, "mips") == 0) | |
4459 | return idt_little_breakpoint; | |
4460 | else if (strcmp (target_shortname, "ddb") == 0 | |
4461 | || strcmp (target_shortname, "pmon") == 0 | |
4462 | || strcmp (target_shortname, "lsi") == 0) | |
4463 | return pmon_little_breakpoint; | |
4464 | else | |
4465 | return little_breakpoint; | |
4466 | } | |
4467 | } | |
4468 | } | |
4469 | ||
4470 | /* If PC is in a mips16 call or return stub, return the address of the target | |
4471 | PC, which is either the callee or the caller. There are several | |
4472 | cases which must be handled: | |
4473 | ||
4474 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 4475 | target PC is in $31 ($ra). |
c906108c | 4476 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 4477 | and the target PC is in $2. |
c906108c | 4478 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
4479 | before the jal instruction, this is effectively a call stub |
4480 | and the the target PC is in $2. Otherwise this is effectively | |
4481 | a return stub and the target PC is in $18. | |
c906108c SS |
4482 | |
4483 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
4484 | gory details. | |
4485 | ||
4486 | This function implements the SKIP_TRAMPOLINE_CODE macro. | |
c5aa993b | 4487 | */ |
c906108c SS |
4488 | |
4489 | CORE_ADDR | |
acdb74a0 | 4490 | mips_skip_stub (CORE_ADDR pc) |
c906108c SS |
4491 | { |
4492 | char *name; | |
4493 | CORE_ADDR start_addr; | |
4494 | ||
4495 | /* Find the starting address and name of the function containing the PC. */ | |
4496 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
4497 | return 0; | |
4498 | ||
4499 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
4500 | target PC is in $31 ($ra). */ | |
4501 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
4502 | || strcmp (name, "__mips16_ret_df") == 0) | |
6c997a34 | 4503 | return read_signed_register (RA_REGNUM); |
c906108c SS |
4504 | |
4505 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
4506 | { | |
4507 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
4508 | and the target PC is in $2. */ | |
4509 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 4510 | return read_signed_register (2); |
c906108c SS |
4511 | |
4512 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
4513 | before the jal instruction, this is effectively a call stub |
4514 | and the the target PC is in $2. Otherwise this is effectively | |
4515 | a return stub and the target PC is in $18. */ | |
c906108c SS |
4516 | else if (name[19] == 's' || name[19] == 'd') |
4517 | { | |
4518 | if (pc == start_addr) | |
4519 | { | |
4520 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
4521 | stub. Such a stub for a function bar might have a name |
4522 | like __fn_stub_bar, and might look like this: | |
4523 | mfc1 $4,$f13 | |
4524 | mfc1 $5,$f12 | |
4525 | mfc1 $6,$f15 | |
4526 | mfc1 $7,$f14 | |
4527 | la $1,bar (becomes a lui/addiu pair) | |
4528 | jr $1 | |
4529 | So scan down to the lui/addi and extract the target | |
4530 | address from those two instructions. */ | |
c906108c | 4531 | |
6c997a34 | 4532 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
4533 | t_inst inst; |
4534 | int i; | |
4535 | ||
4536 | /* See if the name of the target function is __fn_stub_*. */ | |
4537 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0) | |
4538 | return target_pc; | |
4539 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
4540 | && strcmp (name, "etext") != 0 | |
4541 | && strcmp (name, "_etext") != 0) | |
4542 | return target_pc; | |
4543 | ||
4544 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
4545 | The limit on the search is arbitrarily set to 20 |
4546 | instructions. FIXME. */ | |
c906108c SS |
4547 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
4548 | { | |
c5aa993b JM |
4549 | inst = mips_fetch_instruction (target_pc); |
4550 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
4551 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
4552 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
4553 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
4554 | } |
4555 | ||
4556 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
4557 | return target_pc; | |
4558 | } | |
4559 | else | |
4560 | /* This is the 'return' part of a call stub. The return | |
4561 | address is in $r18. */ | |
6c997a34 | 4562 | return read_signed_register (18); |
c906108c SS |
4563 | } |
4564 | } | |
c5aa993b | 4565 | return 0; /* not a stub */ |
c906108c SS |
4566 | } |
4567 | ||
4568 | ||
4569 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
4570 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
4571 | ||
4572 | int | |
acdb74a0 | 4573 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
4574 | { |
4575 | CORE_ADDR start_addr; | |
4576 | ||
4577 | /* Find the starting address of the function containing the PC. If the | |
4578 | caller didn't give us a name, look it up at the same time. */ | |
4579 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) | |
4580 | return 0; | |
4581 | ||
4582 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
4583 | { | |
4584 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
4585 | if (name[19] >= '0' && name[19] <= '9') | |
4586 | return 1; | |
4587 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 4588 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
4589 | else if (name[19] == 's' || name[19] == 'd') |
4590 | return pc == start_addr; | |
4591 | } | |
4592 | ||
c5aa993b | 4593 | return 0; /* not a stub */ |
c906108c SS |
4594 | } |
4595 | ||
4596 | ||
4597 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
4598 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
4599 | ||
4600 | int | |
acdb74a0 | 4601 | mips_in_return_stub (CORE_ADDR pc, char *name) |
c906108c SS |
4602 | { |
4603 | CORE_ADDR start_addr; | |
4604 | ||
4605 | /* Find the starting address of the function containing the PC. */ | |
4606 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
4607 | return 0; | |
4608 | ||
4609 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
4610 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
4611 | || strcmp (name, "__mips16_ret_df") == 0) | |
4612 | return 1; | |
4613 | ||
4614 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 4615 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c SS |
4616 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
4617 | && (name[19] == 's' || name[19] == 'd') | |
4618 | && pc != start_addr) | |
4619 | return 1; | |
4620 | ||
c5aa993b | 4621 | return 0; /* not a stub */ |
c906108c SS |
4622 | } |
4623 | ||
4624 | ||
4625 | /* Return non-zero if the PC is in a library helper function that should | |
4626 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ | |
4627 | ||
4628 | int | |
acdb74a0 | 4629 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
4630 | { |
4631 | char *name; | |
4632 | ||
4633 | /* Find the starting address and name of the function containing the PC. */ | |
4634 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
4635 | return 0; | |
4636 | ||
4637 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
4638 | that we want to ignore. */ | |
4639 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
4640 | || strcmp (name, "__mips16_ret_df") == 0); | |
4641 | } | |
4642 | ||
4643 | ||
4644 | /* Return a location where we can set a breakpoint that will be hit | |
4645 | when an inferior function call returns. This is normally the | |
4646 | program's entry point. Executables that don't have an entry | |
4647 | point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS | |
4648 | whose address is the location where the breakpoint should be placed. */ | |
4649 | ||
4650 | CORE_ADDR | |
acdb74a0 | 4651 | mips_call_dummy_address (void) |
c906108c SS |
4652 | { |
4653 | struct minimal_symbol *sym; | |
4654 | ||
4655 | sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL); | |
4656 | if (sym) | |
4657 | return SYMBOL_VALUE_ADDRESS (sym); | |
4658 | else | |
4659 | return entry_point_address (); | |
4660 | } | |
4661 | ||
4662 | ||
9dcb560c | 4663 | /* If the current gcc for this target does not produce correct debugging |
b9a8e3bf JB |
4664 | information for float parameters, both prototyped and unprototyped, then |
4665 | define this macro. This forces gdb to always assume that floats are | |
4666 | passed as doubles and then converted in the callee. | |
4667 | ||
4668 | For the mips chip, it appears that the debug info marks the parameters as | |
4669 | floats regardless of whether the function is prototyped, but the actual | |
4670 | values are passed as doubles for the non-prototyped case and floats for | |
4671 | the prototyped case. Thus we choose to make the non-prototyped case work | |
4672 | for C and break the prototyped case, since the non-prototyped case is | |
4673 | probably much more common. (FIXME). */ | |
4674 | ||
4675 | static int | |
4676 | mips_coerce_float_to_double (struct type *formal, struct type *actual) | |
4677 | { | |
4678 | return current_language->la_language == language_c; | |
4679 | } | |
4680 | ||
47a8d4ba AC |
4681 | /* When debugging a 64 MIPS target running a 32 bit ABI, the size of |
4682 | the register stored on the stack (32) is different to its real raw | |
4683 | size (64). The below ensures that registers are fetched from the | |
4684 | stack using their ABI size and then stored into the RAW_BUFFER | |
4685 | using their raw size. | |
4686 | ||
4687 | The alternative to adding this function would be to add an ABI | |
4688 | macro - REGISTER_STACK_SIZE(). */ | |
4689 | ||
4690 | static void | |
acdb74a0 AC |
4691 | mips_get_saved_register (char *raw_buffer, |
4692 | int *optimized, | |
4693 | CORE_ADDR *addrp, | |
4694 | struct frame_info *frame, | |
4695 | int regnum, | |
4696 | enum lval_type *lval) | |
47a8d4ba AC |
4697 | { |
4698 | CORE_ADDR addr; | |
4699 | ||
4700 | if (!target_has_registers) | |
4701 | error ("No registers."); | |
4702 | ||
4703 | /* Normal systems don't optimize out things with register numbers. */ | |
4704 | if (optimized != NULL) | |
4705 | *optimized = 0; | |
4706 | addr = find_saved_register (frame, regnum); | |
4707 | if (addr != 0) | |
4708 | { | |
4709 | if (lval != NULL) | |
4710 | *lval = lval_memory; | |
4711 | if (regnum == SP_REGNUM) | |
4712 | { | |
4713 | if (raw_buffer != NULL) | |
4714 | { | |
4715 | /* Put it back in target format. */ | |
4716 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), | |
4717 | (LONGEST) addr); | |
4718 | } | |
4719 | if (addrp != NULL) | |
4720 | *addrp = 0; | |
4721 | return; | |
4722 | } | |
4723 | if (raw_buffer != NULL) | |
4724 | { | |
4725 | LONGEST val; | |
4726 | if (regnum < 32) | |
4727 | /* Only MIPS_SAVED_REGSIZE bytes of GP registers are | |
4728 | saved. */ | |
4729 | val = read_memory_integer (addr, MIPS_SAVED_REGSIZE); | |
4730 | else | |
4731 | val = read_memory_integer (addr, REGISTER_RAW_SIZE (regnum)); | |
4732 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), val); | |
4733 | } | |
4734 | } | |
4735 | else | |
4736 | { | |
4737 | if (lval != NULL) | |
4738 | *lval = lval_register; | |
4739 | addr = REGISTER_BYTE (regnum); | |
4740 | if (raw_buffer != NULL) | |
4741 | read_register_gen (regnum, raw_buffer); | |
4742 | } | |
4743 | if (addrp != NULL) | |
4744 | *addrp = addr; | |
4745 | } | |
2acceee2 | 4746 | |
f7b9e9fc AC |
4747 | /* Immediately after a function call, return the saved pc. |
4748 | Can't always go through the frames for this because on some machines | |
4749 | the new frame is not set up until the new function executes | |
4750 | some instructions. */ | |
4751 | ||
4752 | static CORE_ADDR | |
4753 | mips_saved_pc_after_call (struct frame_info *frame) | |
4754 | { | |
6c997a34 | 4755 | return read_signed_register (RA_REGNUM); |
f7b9e9fc AC |
4756 | } |
4757 | ||
4758 | ||
88c72b7d AC |
4759 | /* Convert a dbx stab register number (from `r' declaration) to a gdb |
4760 | REGNUM */ | |
4761 | ||
4762 | static int | |
4763 | mips_stab_reg_to_regnum (int num) | |
4764 | { | |
4765 | if (num < 32) | |
4766 | return num; | |
361d1df0 | 4767 | else |
88c72b7d AC |
4768 | return num + FP0_REGNUM - 38; |
4769 | } | |
4770 | ||
4771 | /* Convert a ecoff register number to a gdb REGNUM */ | |
4772 | ||
4773 | static int | |
4774 | mips_ecoff_reg_to_regnum (int num) | |
4775 | { | |
4776 | if (num < 32) | |
4777 | return num; | |
4778 | else | |
4779 | return num + FP0_REGNUM - 32; | |
4780 | } | |
4781 | ||
fc0c74b1 AC |
4782 | /* Convert an integer into an address. By first converting the value |
4783 | into a pointer and then extracting it signed, the address is | |
4784 | guarenteed to be correctly sign extended. */ | |
4785 | ||
4786 | static CORE_ADDR | |
4787 | mips_integer_to_address (struct type *type, void *buf) | |
4788 | { | |
4789 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
4790 | LONGEST val = unpack_long (type, buf); | |
4791 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
4792 | return extract_signed_integer (tmp, | |
4793 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
4794 | } | |
4795 | ||
caaa3122 DJ |
4796 | static void |
4797 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
4798 | { | |
4799 | enum mips_abi *abip = (enum mips_abi *) obj; | |
4800 | const char *name = bfd_get_section_name (abfd, sect); | |
4801 | ||
4802 | if (*abip != MIPS_ABI_UNKNOWN) | |
4803 | return; | |
4804 | ||
4805 | if (strncmp (name, ".mdebug.", 8) != 0) | |
4806 | return; | |
4807 | ||
4808 | if (strcmp (name, ".mdebug.abi32") == 0) | |
4809 | *abip = MIPS_ABI_O32; | |
4810 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
4811 | *abip = MIPS_ABI_N32; | |
e3bddbfa KB |
4812 | else if (strcmp (name, ".mdebug.abiN64") == 0) |
4813 | *abip = MIPS_ABI_N64; | |
caaa3122 DJ |
4814 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
4815 | *abip = MIPS_ABI_O64; | |
4816 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
4817 | *abip = MIPS_ABI_EABI32; | |
4818 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
4819 | *abip = MIPS_ABI_EABI64; | |
4820 | else | |
4821 | warning ("unsupported ABI %s.", name + 8); | |
4822 | } | |
4823 | ||
2e4ebe70 DJ |
4824 | static enum mips_abi |
4825 | global_mips_abi (void) | |
4826 | { | |
4827 | int i; | |
4828 | ||
4829 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
4830 | if (mips_abi_strings[i] == mips_abi_string) | |
4831 | return (enum mips_abi) i; | |
4832 | ||
4833 | internal_error (__FILE__, __LINE__, | |
4834 | "unknown ABI string"); | |
4835 | } | |
4836 | ||
c2d11a7d | 4837 | static struct gdbarch * |
acdb74a0 AC |
4838 | mips_gdbarch_init (struct gdbarch_info info, |
4839 | struct gdbarch_list *arches) | |
c2d11a7d JM |
4840 | { |
4841 | static LONGEST mips_call_dummy_words[] = | |
4842 | {0}; | |
4843 | struct gdbarch *gdbarch; | |
4844 | struct gdbarch_tdep *tdep; | |
4845 | int elf_flags; | |
2e4ebe70 | 4846 | enum mips_abi mips_abi, found_abi, wanted_abi; |
70f80edf | 4847 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
c2d11a7d | 4848 | |
1d06468c EZ |
4849 | /* Reset the disassembly info, in case it was set to something |
4850 | non-default. */ | |
4851 | tm_print_insn_info.flavour = bfd_target_unknown_flavour; | |
4852 | tm_print_insn_info.arch = bfd_arch_unknown; | |
4853 | tm_print_insn_info.mach = 0; | |
4854 | ||
70f80edf JT |
4855 | elf_flags = 0; |
4856 | ||
4857 | if (info.abfd) | |
4858 | { | |
4859 | /* First of all, extract the elf_flags, if available. */ | |
4860 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
4861 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
4862 | ||
4863 | /* Try to determine the OS ABI of the object we are loading. If | |
4864 | we end up with `unknown', just leave it that way. */ | |
4865 | osabi = gdbarch_lookup_osabi (info.abfd); | |
4866 | } | |
c2d11a7d | 4867 | |
0dadbba0 AC |
4868 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
4869 | switch ((elf_flags & EF_MIPS_ABI)) | |
4870 | { | |
4871 | case E_MIPS_ABI_O32: | |
4872 | mips_abi = MIPS_ABI_O32; | |
4873 | break; | |
4874 | case E_MIPS_ABI_O64: | |
4875 | mips_abi = MIPS_ABI_O64; | |
4876 | break; | |
4877 | case E_MIPS_ABI_EABI32: | |
4878 | mips_abi = MIPS_ABI_EABI32; | |
4879 | break; | |
4880 | case E_MIPS_ABI_EABI64: | |
4a7f7ba8 | 4881 | mips_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
4882 | break; |
4883 | default: | |
acdb74a0 AC |
4884 | if ((elf_flags & EF_MIPS_ABI2)) |
4885 | mips_abi = MIPS_ABI_N32; | |
4886 | else | |
4887 | mips_abi = MIPS_ABI_UNKNOWN; | |
0dadbba0 AC |
4888 | break; |
4889 | } | |
acdb74a0 | 4890 | |
caaa3122 DJ |
4891 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
4892 | if (mips_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) | |
4893 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &mips_abi); | |
4894 | ||
2e4ebe70 DJ |
4895 | /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN. |
4896 | Use the ABI from the last architecture if there is one. */ | |
4897 | if (info.abfd == NULL && arches != NULL) | |
4898 | mips_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
4899 | ||
32a6503c | 4900 | /* Try the architecture for any hint of the correct ABI. */ |
bf64bfd6 AC |
4901 | if (mips_abi == MIPS_ABI_UNKNOWN |
4902 | && info.bfd_arch_info != NULL | |
4903 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
4904 | { | |
4905 | switch (info.bfd_arch_info->mach) | |
4906 | { | |
4907 | case bfd_mach_mips3900: | |
4908 | mips_abi = MIPS_ABI_EABI32; | |
4909 | break; | |
4910 | case bfd_mach_mips4100: | |
4911 | case bfd_mach_mips5000: | |
4912 | mips_abi = MIPS_ABI_EABI64; | |
4913 | break; | |
1d06468c EZ |
4914 | case bfd_mach_mips8000: |
4915 | case bfd_mach_mips10000: | |
32a6503c KB |
4916 | /* On Irix, ELF64 executables use the N64 ABI. The |
4917 | pseudo-sections which describe the ABI aren't present | |
4918 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
4919 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
4920 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
4921 | mips_abi = MIPS_ABI_N64; | |
4922 | else | |
4923 | mips_abi = MIPS_ABI_N32; | |
1d06468c | 4924 | break; |
bf64bfd6 AC |
4925 | } |
4926 | } | |
2e4ebe70 | 4927 | |
0dadbba0 AC |
4928 | #ifdef MIPS_DEFAULT_ABI |
4929 | if (mips_abi == MIPS_ABI_UNKNOWN) | |
4930 | mips_abi = MIPS_DEFAULT_ABI; | |
4931 | #endif | |
4b9b3959 | 4932 | |
2e4ebe70 DJ |
4933 | if (mips_abi == MIPS_ABI_UNKNOWN) |
4934 | mips_abi = MIPS_ABI_O32; | |
4935 | ||
4936 | /* Now that we have found what the ABI for this binary would be, | |
4937 | check whether the user is overriding it. */ | |
4938 | found_abi = mips_abi; | |
4939 | wanted_abi = global_mips_abi (); | |
4940 | if (wanted_abi != MIPS_ABI_UNKNOWN) | |
4941 | mips_abi = wanted_abi; | |
4942 | ||
4b9b3959 AC |
4943 | if (gdbarch_debug) |
4944 | { | |
4945 | fprintf_unfiltered (gdb_stdlog, | |
9ace0497 | 4946 | "mips_gdbarch_init: elf_flags = 0x%08x\n", |
4b9b3959 | 4947 | elf_flags); |
4b9b3959 AC |
4948 | fprintf_unfiltered (gdb_stdlog, |
4949 | "mips_gdbarch_init: mips_abi = %d\n", | |
4950 | mips_abi); | |
2e4ebe70 DJ |
4951 | fprintf_unfiltered (gdb_stdlog, |
4952 | "mips_gdbarch_init: found_mips_abi = %d\n", | |
4953 | found_abi); | |
4b9b3959 | 4954 | } |
0dadbba0 | 4955 | |
c2d11a7d JM |
4956 | /* try to find a pre-existing architecture */ |
4957 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
4958 | arches != NULL; | |
4959 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
4960 | { | |
4961 | /* MIPS needs to be pedantic about which ABI the object is | |
4962 | using. */ | |
9103eae0 | 4963 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 4964 | continue; |
9103eae0 | 4965 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 4966 | continue; |
70f80edf JT |
4967 | if (gdbarch_tdep (arches->gdbarch)->osabi == osabi) |
4968 | return arches->gdbarch; | |
c2d11a7d JM |
4969 | } |
4970 | ||
4971 | /* Need a new architecture. Fill in a target specific vector. */ | |
4972 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
4973 | gdbarch = gdbarch_alloc (&info, tdep); | |
4974 | tdep->elf_flags = elf_flags; | |
70f80edf | 4975 | tdep->osabi = osabi; |
c2d11a7d | 4976 | |
46cd78fb | 4977 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
4978 | set_gdbarch_short_bit (gdbarch, 16); |
4979 | set_gdbarch_int_bit (gdbarch, 32); | |
4980 | set_gdbarch_float_bit (gdbarch, 32); | |
4981 | set_gdbarch_double_bit (gdbarch, 64); | |
4982 | set_gdbarch_long_double_bit (gdbarch, 64); | |
46cd78fb | 4983 | set_gdbarch_register_raw_size (gdbarch, mips_register_raw_size); |
2e4ebe70 | 4984 | tdep->found_abi = found_abi; |
0dadbba0 | 4985 | tdep->mips_abi = mips_abi; |
1d06468c | 4986 | |
0dadbba0 | 4987 | switch (mips_abi) |
c2d11a7d | 4988 | { |
0dadbba0 | 4989 | case MIPS_ABI_O32: |
ebafbe83 | 4990 | set_gdbarch_push_arguments (gdbarch, mips_o32o64_push_arguments); |
a5ea2558 | 4991 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 4992 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 4993 | tdep->mips_fp_register_double = 0; |
acdb74a0 AC |
4994 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
4995 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1; | |
5213ab06 | 4996 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 4997 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
4998 | set_gdbarch_long_bit (gdbarch, 32); |
4999 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5000 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8b389c40 MS |
5001 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5002 | mips_o32_reg_struct_has_addr); | |
cb811fe7 MS |
5003 | set_gdbarch_use_struct_convention (gdbarch, |
5004 | mips_o32_use_struct_convention); | |
c2d11a7d | 5005 | break; |
0dadbba0 | 5006 | case MIPS_ABI_O64: |
ebafbe83 | 5007 | set_gdbarch_push_arguments (gdbarch, mips_o32o64_push_arguments); |
a5ea2558 | 5008 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5009 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5010 | tdep->mips_fp_register_double = 1; |
acdb74a0 AC |
5011 | tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; |
5012 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1; | |
5213ab06 | 5013 | tdep->gdb_target_is_mips64 = 1; |
361d1df0 | 5014 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5015 | set_gdbarch_long_bit (gdbarch, 32); |
5016 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5017 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8b389c40 MS |
5018 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5019 | mips_o32_reg_struct_has_addr); | |
cb811fe7 MS |
5020 | set_gdbarch_use_struct_convention (gdbarch, |
5021 | mips_o32_use_struct_convention); | |
c2d11a7d | 5022 | break; |
0dadbba0 | 5023 | case MIPS_ABI_EABI32: |
46e0f506 | 5024 | set_gdbarch_push_arguments (gdbarch, mips_eabi_push_arguments); |
a5ea2558 | 5025 | tdep->mips_default_saved_regsize = 4; |
0dadbba0 | 5026 | tdep->mips_default_stack_argsize = 4; |
c2d11a7d | 5027 | tdep->mips_fp_register_double = 0; |
acdb74a0 AC |
5028 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
5029 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
5213ab06 | 5030 | tdep->gdb_target_is_mips64 = 0; |
4014092b | 5031 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5032 | set_gdbarch_long_bit (gdbarch, 32); |
5033 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5034 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8b389c40 MS |
5035 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5036 | mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5037 | set_gdbarch_use_struct_convention (gdbarch, |
5038 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5039 | break; |
0dadbba0 | 5040 | case MIPS_ABI_EABI64: |
46e0f506 | 5041 | set_gdbarch_push_arguments (gdbarch, mips_eabi_push_arguments); |
a5ea2558 | 5042 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 | 5043 | tdep->mips_default_stack_argsize = 8; |
c2d11a7d | 5044 | tdep->mips_fp_register_double = 1; |
acdb74a0 AC |
5045 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
5046 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
5213ab06 | 5047 | tdep->gdb_target_is_mips64 = 1; |
4014092b | 5048 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5049 | set_gdbarch_long_bit (gdbarch, 64); |
5050 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5051 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8b389c40 MS |
5052 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5053 | mips_eabi_reg_struct_has_addr); | |
cb811fe7 MS |
5054 | set_gdbarch_use_struct_convention (gdbarch, |
5055 | mips_eabi_use_struct_convention); | |
c2d11a7d | 5056 | break; |
0dadbba0 | 5057 | case MIPS_ABI_N32: |
cb3d25d1 | 5058 | set_gdbarch_push_arguments (gdbarch, mips_n32n64_push_arguments); |
63db5580 | 5059 | tdep->mips_default_saved_regsize = 8; |
0dadbba0 AC |
5060 | tdep->mips_default_stack_argsize = 8; |
5061 | tdep->mips_fp_register_double = 1; | |
acdb74a0 AC |
5062 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; |
5063 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
6acdf5c7 | 5064 | tdep->gdb_target_is_mips64 = 1; |
4014092b | 5065 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5066 | set_gdbarch_long_bit (gdbarch, 32); |
5067 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5068 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1d06468c EZ |
5069 | |
5070 | /* Set up the disassembler info, so that we get the right | |
28d169de KB |
5071 | register names from libopcodes. */ |
5072 | tm_print_insn_info.flavour = bfd_target_elf_flavour; | |
5073 | tm_print_insn_info.arch = bfd_arch_mips; | |
5074 | if (info.bfd_arch_info != NULL | |
5075 | && info.bfd_arch_info->arch == bfd_arch_mips | |
5076 | && info.bfd_arch_info->mach) | |
5077 | tm_print_insn_info.mach = info.bfd_arch_info->mach; | |
5078 | else | |
5079 | tm_print_insn_info.mach = bfd_mach_mips8000; | |
cb811fe7 MS |
5080 | |
5081 | set_gdbarch_use_struct_convention (gdbarch, | |
5082 | mips_n32n64_use_struct_convention); | |
8b389c40 MS |
5083 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5084 | mips_n32n64_reg_struct_has_addr); | |
28d169de KB |
5085 | break; |
5086 | case MIPS_ABI_N64: | |
cb3d25d1 | 5087 | set_gdbarch_push_arguments (gdbarch, mips_n32n64_push_arguments); |
28d169de KB |
5088 | tdep->mips_default_saved_regsize = 8; |
5089 | tdep->mips_default_stack_argsize = 8; | |
5090 | tdep->mips_fp_register_double = 1; | |
5091 | tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; | |
5092 | tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; | |
28d169de KB |
5093 | tdep->gdb_target_is_mips64 = 1; |
5094 | tdep->default_mask_address_p = 0; | |
5095 | set_gdbarch_long_bit (gdbarch, 64); | |
5096 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5097 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5098 | ||
5099 | /* Set up the disassembler info, so that we get the right | |
1d06468c EZ |
5100 | register names from libopcodes. */ |
5101 | tm_print_insn_info.flavour = bfd_target_elf_flavour; | |
5102 | tm_print_insn_info.arch = bfd_arch_mips; | |
5103 | if (info.bfd_arch_info != NULL | |
5104 | && info.bfd_arch_info->arch == bfd_arch_mips | |
5105 | && info.bfd_arch_info->mach) | |
5106 | tm_print_insn_info.mach = info.bfd_arch_info->mach; | |
5107 | else | |
5108 | tm_print_insn_info.mach = bfd_mach_mips8000; | |
cb811fe7 MS |
5109 | |
5110 | set_gdbarch_use_struct_convention (gdbarch, | |
5111 | mips_n32n64_use_struct_convention); | |
8b389c40 MS |
5112 | set_gdbarch_reg_struct_has_addr (gdbarch, |
5113 | mips_n32n64_reg_struct_has_addr); | |
0dadbba0 | 5114 | break; |
c2d11a7d | 5115 | default: |
2e4ebe70 DJ |
5116 | internal_error (__FILE__, __LINE__, |
5117 | "unknown ABI in switch"); | |
c2d11a7d JM |
5118 | } |
5119 | ||
a5ea2558 AC |
5120 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5121 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5122 | comment: | |
5123 | ||
5124 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5125 | flag in object files because to do so would make it impossible to | |
5126 | link with libraries compiled without "-gp32". This is | |
5127 | unnecessarily restrictive. | |
361d1df0 | 5128 | |
a5ea2558 AC |
5129 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5130 | but to set this flag before gcc is built with such multilibs will | |
5131 | break too many systems.'' | |
5132 | ||
5133 | But even more unhelpfully, the default linker output target for | |
5134 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5135 | for 64-bit programs - you need to change the ABI to change this, | |
5136 | and not all gcc targets support that currently. Therefore using | |
5137 | this flag to detect 32-bit mode would do the wrong thing given | |
5138 | the current gcc - it would make GDB treat these 64-bit programs | |
5139 | as 32-bit programs by default. */ | |
5140 | ||
c2d11a7d JM |
5141 | /* enable/disable the MIPS FPU */ |
5142 | if (!mips_fpu_type_auto) | |
5143 | tdep->mips_fpu_type = mips_fpu_type; | |
5144 | else if (info.bfd_arch_info != NULL | |
5145 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5146 | switch (info.bfd_arch_info->mach) | |
5147 | { | |
b0069a17 | 5148 | case bfd_mach_mips3900: |
c2d11a7d | 5149 | case bfd_mach_mips4100: |
ed9a39eb | 5150 | case bfd_mach_mips4111: |
c2d11a7d JM |
5151 | tdep->mips_fpu_type = MIPS_FPU_NONE; |
5152 | break; | |
bf64bfd6 AC |
5153 | case bfd_mach_mips4650: |
5154 | tdep->mips_fpu_type = MIPS_FPU_SINGLE; | |
5155 | break; | |
c2d11a7d JM |
5156 | default: |
5157 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
5158 | break; | |
5159 | } | |
5160 | else | |
5161 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; | |
5162 | ||
5163 | /* MIPS version of register names. NOTE: At present the MIPS | |
5164 | register name management is part way between the old - | |
5165 | #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr). | |
5166 | Further work on it is required. */ | |
5167 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
6c997a34 | 5168 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
c2d11a7d JM |
5169 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
5170 | set_gdbarch_read_fp (gdbarch, generic_target_read_fp); | |
c2d11a7d JM |
5171 | set_gdbarch_read_sp (gdbarch, generic_target_read_sp); |
5172 | set_gdbarch_write_sp (gdbarch, generic_target_write_sp); | |
5173 | ||
875e1767 AC |
5174 | /* Add/remove bits from an address. The MIPS needs be careful to |
5175 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
5176 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); | |
5177 | ||
10312cc4 AC |
5178 | /* There's a mess in stack frame creation. See comments in |
5179 | blockframe.c near reference to INIT_FRAME_PC_FIRST. */ | |
5180 | set_gdbarch_init_frame_pc_first (gdbarch, mips_init_frame_pc_first); | |
7824d2f2 | 5181 | set_gdbarch_init_frame_pc (gdbarch, init_frame_pc_noop); |
10312cc4 | 5182 | |
88c72b7d AC |
5183 | /* Map debug register numbers onto internal register numbers. */ |
5184 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); | |
5185 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_ecoff_reg_to_regnum); | |
5186 | ||
c2d11a7d JM |
5187 | /* Initialize a frame */ |
5188 | set_gdbarch_init_extra_frame_info (gdbarch, mips_init_extra_frame_info); | |
d28e01f4 | 5189 | set_gdbarch_frame_init_saved_regs (gdbarch, mips_frame_init_saved_regs); |
c2d11a7d JM |
5190 | |
5191 | /* MIPS version of CALL_DUMMY */ | |
5192 | ||
5193 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
5194 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
5195 | set_gdbarch_use_generic_dummy_frames (gdbarch, 0); | |
5196 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); | |
5197 | set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address); | |
5198 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
5199 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
5200 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
5201 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
5202 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point); | |
5203 | set_gdbarch_call_dummy_words (gdbarch, mips_call_dummy_words); | |
5204 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (mips_call_dummy_words)); | |
5205 | set_gdbarch_push_return_address (gdbarch, mips_push_return_address); | |
c2d11a7d | 5206 | set_gdbarch_register_convertible (gdbarch, generic_register_convertible_not); |
b9a8e3bf | 5207 | set_gdbarch_coerce_float_to_double (gdbarch, mips_coerce_float_to_double); |
c2d11a7d | 5208 | |
c4093a6a | 5209 | set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid); |
47a8d4ba | 5210 | set_gdbarch_get_saved_register (gdbarch, mips_get_saved_register); |
c2d11a7d | 5211 | |
f7b9e9fc AC |
5212 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5213 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
5214 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
f7b9e9fc AC |
5215 | |
5216 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
5217 | set_gdbarch_saved_pc_after_call (gdbarch, mips_saved_pc_after_call); | |
5218 | ||
fc0c74b1 AC |
5219 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5220 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5221 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5222 | |
32a6503c KB |
5223 | /* There are MIPS targets which do not yet use this since they still |
5224 | define REGISTER_VIRTUAL_TYPE. */ | |
78fde5f8 KB |
5225 | set_gdbarch_register_virtual_type (gdbarch, mips_register_virtual_type); |
5226 | ||
70f80edf JT |
5227 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
5228 | gdbarch_init_osabi (info, gdbarch, osabi); | |
5229 | ||
4b9b3959 AC |
5230 | return gdbarch; |
5231 | } | |
5232 | ||
2e4ebe70 DJ |
5233 | static void |
5234 | mips_abi_update (char *ignore_args, int from_tty, | |
5235 | struct cmd_list_element *c) | |
5236 | { | |
5237 | struct gdbarch_info info; | |
5238 | ||
5239 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
5240 | mips_gdbarch_init will take care of the rest. */ | |
5241 | gdbarch_info_init (&info); | |
5242 | gdbarch_update_p (info); | |
5243 | } | |
5244 | ||
4b9b3959 AC |
5245 | static void |
5246 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
5247 | { | |
5248 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
5249 | if (tdep != NULL) | |
c2d11a7d | 5250 | { |
acdb74a0 AC |
5251 | int ef_mips_arch; |
5252 | int ef_mips_32bitmode; | |
5253 | /* determine the ISA */ | |
5254 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
5255 | { | |
5256 | case E_MIPS_ARCH_1: | |
5257 | ef_mips_arch = 1; | |
5258 | break; | |
5259 | case E_MIPS_ARCH_2: | |
5260 | ef_mips_arch = 2; | |
5261 | break; | |
5262 | case E_MIPS_ARCH_3: | |
5263 | ef_mips_arch = 3; | |
5264 | break; | |
5265 | case E_MIPS_ARCH_4: | |
93d56215 | 5266 | ef_mips_arch = 4; |
acdb74a0 AC |
5267 | break; |
5268 | default: | |
93d56215 | 5269 | ef_mips_arch = 0; |
acdb74a0 AC |
5270 | break; |
5271 | } | |
5272 | /* determine the size of a pointer */ | |
5273 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
5274 | fprintf_unfiltered (file, |
5275 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 5276 | tdep->elf_flags); |
4b9b3959 | 5277 | fprintf_unfiltered (file, |
acdb74a0 AC |
5278 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
5279 | ef_mips_32bitmode); | |
5280 | fprintf_unfiltered (file, | |
5281 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
5282 | ef_mips_arch); | |
5283 | fprintf_unfiltered (file, | |
5284 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
5285 | tdep->mips_abi, | |
2e4ebe70 | 5286 | mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
5287 | fprintf_unfiltered (file, |
5288 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
5289 | mips_mask_address_p (), | |
5290 | tdep->default_mask_address_p); | |
c2d11a7d | 5291 | } |
4b9b3959 AC |
5292 | fprintf_unfiltered (file, |
5293 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
5294 | FP_REGISTER_DOUBLE); | |
5295 | fprintf_unfiltered (file, | |
5296 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
5297 | MIPS_DEFAULT_FPU_TYPE, | |
5298 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5299 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5300 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5301 | : "???")); | |
5302 | fprintf_unfiltered (file, | |
5303 | "mips_dump_tdep: MIPS_EABI = %d\n", | |
5304 | MIPS_EABI); | |
5305 | fprintf_unfiltered (file, | |
acdb74a0 AC |
5306 | "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n", |
5307 | MIPS_LAST_FP_ARG_REGNUM, | |
5308 | MIPS_LAST_FP_ARG_REGNUM - FPA0_REGNUM + 1); | |
4b9b3959 AC |
5309 | fprintf_unfiltered (file, |
5310 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
5311 | MIPS_FPU_TYPE, | |
5312 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5313 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5314 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5315 | : "???")); | |
5316 | fprintf_unfiltered (file, | |
5317 | "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n", | |
5318 | MIPS_DEFAULT_SAVED_REGSIZE); | |
4b9b3959 AC |
5319 | fprintf_unfiltered (file, |
5320 | "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", | |
5321 | FP_REGISTER_DOUBLE); | |
4b9b3959 AC |
5322 | fprintf_unfiltered (file, |
5323 | "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n", | |
5324 | MIPS_DEFAULT_STACK_ARGSIZE); | |
5325 | fprintf_unfiltered (file, | |
5326 | "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n", | |
5327 | MIPS_STACK_ARGSIZE); | |
5328 | fprintf_unfiltered (file, | |
5329 | "mips_dump_tdep: MIPS_REGSIZE = %d\n", | |
5330 | MIPS_REGSIZE); | |
2475bac3 AC |
5331 | fprintf_unfiltered (file, |
5332 | "mips_dump_tdep: A0_REGNUM = %d\n", | |
5333 | A0_REGNUM); | |
5334 | fprintf_unfiltered (file, | |
5335 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
5336 | XSTRING (ADDR_BITS_REMOVE(ADDR))); | |
5337 | fprintf_unfiltered (file, | |
5338 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
5339 | XSTRING (ATTACH_DETACH)); | |
5340 | fprintf_unfiltered (file, | |
5341 | "mips_dump_tdep: BADVADDR_REGNUM = %d\n", | |
5342 | BADVADDR_REGNUM); | |
5343 | fprintf_unfiltered (file, | |
5344 | "mips_dump_tdep: BIG_BREAKPOINT = delete?\n"); | |
5345 | fprintf_unfiltered (file, | |
5346 | "mips_dump_tdep: CAUSE_REGNUM = %d\n", | |
5347 | CAUSE_REGNUM); | |
5348 | fprintf_unfiltered (file, | |
5349 | "mips_dump_tdep: CPLUS_MARKER = %c\n", | |
5350 | CPLUS_MARKER); | |
5351 | fprintf_unfiltered (file, | |
5352 | "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n", | |
5353 | DEFAULT_MIPS_TYPE); | |
5354 | fprintf_unfiltered (file, | |
5355 | "mips_dump_tdep: DO_REGISTERS_INFO # %s\n", | |
5356 | XSTRING (DO_REGISTERS_INFO)); | |
5357 | fprintf_unfiltered (file, | |
5358 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
5359 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
5360 | fprintf_unfiltered (file, | |
5361 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
5362 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
5363 | fprintf_unfiltered (file, | |
5364 | "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n", | |
5365 | XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM, MSYM))); | |
5366 | fprintf_unfiltered (file, | |
5367 | "mips_dump_tdep: FCRCS_REGNUM = %d\n", | |
5368 | FCRCS_REGNUM); | |
5369 | fprintf_unfiltered (file, | |
5370 | "mips_dump_tdep: FCRIR_REGNUM = %d\n", | |
5371 | FCRIR_REGNUM); | |
5372 | fprintf_unfiltered (file, | |
5373 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
5374 | FIRST_EMBED_REGNUM); | |
5375 | fprintf_unfiltered (file, | |
5376 | "mips_dump_tdep: FPA0_REGNUM = %d\n", | |
5377 | FPA0_REGNUM); | |
5378 | fprintf_unfiltered (file, | |
5379 | "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n", | |
5380 | GDB_TARGET_IS_MIPS64); | |
5381 | fprintf_unfiltered (file, | |
5382 | "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n", | |
5383 | XSTRING (GDB_TARGET_MASK_DISAS_PC (PC))); | |
5384 | fprintf_unfiltered (file, | |
5385 | "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n", | |
5386 | XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC))); | |
5387 | fprintf_unfiltered (file, | |
5388 | "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n", | |
5389 | GEN_REG_SAVE_MASK); | |
5390 | fprintf_unfiltered (file, | |
5391 | "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n", | |
5392 | XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT)); | |
5393 | fprintf_unfiltered (file, | |
5394 | "mips_dump_tdep: HI_REGNUM = %d\n", | |
5395 | HI_REGNUM); | |
5396 | fprintf_unfiltered (file, | |
5397 | "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n"); | |
5398 | fprintf_unfiltered (file, | |
5399 | "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n"); | |
5400 | fprintf_unfiltered (file, | |
5401 | "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n", | |
5402 | XSTRING (IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
5403 | fprintf_unfiltered (file, |
5404 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
5405 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
5406 | fprintf_unfiltered (file, | |
5407 | "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", | |
5408 | XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); | |
5409 | fprintf_unfiltered (file, | |
5410 | "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n"); | |
5411 | fprintf_unfiltered (file, | |
5412 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
5413 | LAST_EMBED_REGNUM); | |
5414 | fprintf_unfiltered (file, | |
5415 | "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n"); | |
5416 | fprintf_unfiltered (file, | |
5417 | "mips_dump_tdep: LO_REGNUM = %d\n", | |
5418 | LO_REGNUM); | |
5419 | #ifdef MACHINE_CPROC_FP_OFFSET | |
5420 | fprintf_unfiltered (file, | |
5421 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
5422 | MACHINE_CPROC_FP_OFFSET); | |
5423 | #endif | |
5424 | #ifdef MACHINE_CPROC_PC_OFFSET | |
5425 | fprintf_unfiltered (file, | |
5426 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
5427 | MACHINE_CPROC_PC_OFFSET); | |
5428 | #endif | |
5429 | #ifdef MACHINE_CPROC_SP_OFFSET | |
5430 | fprintf_unfiltered (file, | |
5431 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
5432 | MACHINE_CPROC_SP_OFFSET); | |
5433 | #endif | |
5434 | fprintf_unfiltered (file, | |
5435 | "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n"); | |
5436 | fprintf_unfiltered (file, | |
5437 | "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n"); | |
5438 | fprintf_unfiltered (file, | |
5439 | "mips_dump_tdep: MIPS16_INSTLEN = %d\n", | |
5440 | MIPS16_INSTLEN); | |
5441 | fprintf_unfiltered (file, | |
5442 | "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n"); | |
5443 | fprintf_unfiltered (file, | |
5444 | "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); | |
5445 | fprintf_unfiltered (file, | |
5446 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
5447 | fprintf_unfiltered (file, | |
5448 | "mips_dump_tdep: MIPS_INSTLEN = %d\n", | |
5449 | MIPS_INSTLEN); | |
5450 | fprintf_unfiltered (file, | |
acdb74a0 AC |
5451 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
5452 | MIPS_LAST_ARG_REGNUM, | |
5453 | MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); | |
2475bac3 AC |
5454 | fprintf_unfiltered (file, |
5455 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", | |
5456 | MIPS_NUMREGS); | |
5457 | fprintf_unfiltered (file, | |
5458 | "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n"); | |
5459 | fprintf_unfiltered (file, | |
5460 | "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n", | |
5461 | MIPS_SAVED_REGSIZE); | |
5462 | fprintf_unfiltered (file, | |
5463 | "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n"); | |
5464 | fprintf_unfiltered (file, | |
5465 | "mips_dump_tdep: MSYMBOL_SIZE # %s\n", | |
5466 | XSTRING (MSYMBOL_SIZE (MSYM))); | |
5467 | fprintf_unfiltered (file, | |
5468 | "mips_dump_tdep: OP_LDFPR = used?\n"); | |
5469 | fprintf_unfiltered (file, | |
5470 | "mips_dump_tdep: OP_LDGPR = used?\n"); | |
5471 | fprintf_unfiltered (file, | |
5472 | "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n"); | |
5473 | fprintf_unfiltered (file, | |
5474 | "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n"); | |
5475 | fprintf_unfiltered (file, | |
5476 | "mips_dump_tdep: PRID_REGNUM = %d\n", | |
5477 | PRID_REGNUM); | |
5478 | fprintf_unfiltered (file, | |
5479 | "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n", | |
5480 | XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME))); | |
5481 | fprintf_unfiltered (file, | |
5482 | "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); | |
5483 | fprintf_unfiltered (file, | |
5484 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
5485 | fprintf_unfiltered (file, | |
5486 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
5487 | fprintf_unfiltered (file, | |
5488 | "mips_dump_tdep: PROC_FRAME_REG = function?\n"); | |
5489 | fprintf_unfiltered (file, | |
5490 | "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
5491 | fprintf_unfiltered (file, | |
5492 | "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
5493 | fprintf_unfiltered (file, | |
5494 | "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
5495 | fprintf_unfiltered (file, | |
5496 | "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
5497 | fprintf_unfiltered (file, | |
5498 | "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
5499 | fprintf_unfiltered (file, | |
5500 | "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
5501 | fprintf_unfiltered (file, | |
5502 | "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
5503 | fprintf_unfiltered (file, | |
5504 | "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
5505 | fprintf_unfiltered (file, | |
5506 | "mips_dump_tdep: PS_REGNUM = %d\n", | |
5507 | PS_REGNUM); | |
5508 | fprintf_unfiltered (file, | |
5509 | "mips_dump_tdep: PUSH_FP_REGNUM = %d\n", | |
5510 | PUSH_FP_REGNUM); | |
5511 | fprintf_unfiltered (file, | |
5512 | "mips_dump_tdep: RA_REGNUM = %d\n", | |
5513 | RA_REGNUM); | |
5514 | fprintf_unfiltered (file, | |
5515 | "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n", | |
5516 | XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM, VALTYPE, RAW_BUFFER))); | |
5517 | fprintf_unfiltered (file, | |
5518 | "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n", | |
5519 | XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM, VALTYPE, RAW_BUFFER))); | |
5520 | fprintf_unfiltered (file, | |
5521 | "mips_dump_tdep: REGISTER_NAMES = delete?\n"); | |
5522 | fprintf_unfiltered (file, | |
5523 | "mips_dump_tdep: ROUND_DOWN = function?\n"); | |
5524 | fprintf_unfiltered (file, | |
5525 | "mips_dump_tdep: ROUND_UP = function?\n"); | |
5526 | #ifdef SAVED_BYTES | |
5527 | fprintf_unfiltered (file, | |
5528 | "mips_dump_tdep: SAVED_BYTES = %d\n", | |
5529 | SAVED_BYTES); | |
5530 | #endif | |
5531 | #ifdef SAVED_FP | |
5532 | fprintf_unfiltered (file, | |
5533 | "mips_dump_tdep: SAVED_FP = %d\n", | |
5534 | SAVED_FP); | |
5535 | #endif | |
5536 | #ifdef SAVED_PC | |
5537 | fprintf_unfiltered (file, | |
5538 | "mips_dump_tdep: SAVED_PC = %d\n", | |
5539 | SAVED_PC); | |
5540 | #endif | |
5541 | fprintf_unfiltered (file, | |
5542 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
5543 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
5544 | fprintf_unfiltered (file, | |
5545 | "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); | |
5546 | fprintf_unfiltered (file, | |
5547 | "mips_dump_tdep: SIGFRAME_BASE = %d\n", | |
5548 | SIGFRAME_BASE); | |
5549 | fprintf_unfiltered (file, | |
5550 | "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n", | |
5551 | SIGFRAME_FPREGSAVE_OFF); | |
5552 | fprintf_unfiltered (file, | |
5553 | "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n", | |
5554 | SIGFRAME_PC_OFF); | |
5555 | fprintf_unfiltered (file, | |
5556 | "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n", | |
5557 | SIGFRAME_REGSAVE_OFF); | |
5558 | fprintf_unfiltered (file, | |
5559 | "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n", | |
5560 | SIGFRAME_REG_SIZE); | |
5561 | fprintf_unfiltered (file, | |
5562 | "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", | |
5563 | XSTRING (SKIP_TRAMPOLINE_CODE (PC))); | |
5564 | fprintf_unfiltered (file, | |
5565 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
5566 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
5567 | fprintf_unfiltered (file, | |
b0ed3589 AC |
5568 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
5569 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
5570 | fprintf_unfiltered (file, |
5571 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
5572 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
5573 | #ifdef STACK_END_ADDR | |
5574 | fprintf_unfiltered (file, | |
5575 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
5576 | STACK_END_ADDR); | |
5577 | #endif | |
5578 | fprintf_unfiltered (file, | |
5579 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
5580 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
5581 | fprintf_unfiltered (file, | |
5582 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
5583 | STEP_SKIPS_DELAY_P); | |
5584 | fprintf_unfiltered (file, | |
5585 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
5586 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
5587 | fprintf_unfiltered (file, | |
5588 | "mips_dump_tdep: T9_REGNUM = %d\n", | |
5589 | T9_REGNUM); | |
5590 | fprintf_unfiltered (file, | |
5591 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
5592 | fprintf_unfiltered (file, | |
5593 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
5594 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE))); | |
5595 | fprintf_unfiltered (file, | |
5596 | "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", | |
5597 | XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); | |
5598 | fprintf_unfiltered (file, | |
5599 | "mips_dump_tdep: TARGET_MIPS = used?\n"); | |
5600 | fprintf_unfiltered (file, | |
5601 | "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n", | |
5602 | XSTRING (TM_PRINT_INSN_MACH)); | |
5603 | #ifdef TRACE_CLEAR | |
5604 | fprintf_unfiltered (file, | |
5605 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
5606 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
5607 | #endif | |
5608 | #ifdef TRACE_FLAVOR | |
5609 | fprintf_unfiltered (file, | |
5610 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", | |
5611 | TRACE_FLAVOR); | |
5612 | #endif | |
5613 | #ifdef TRACE_FLAVOR_SIZE | |
5614 | fprintf_unfiltered (file, | |
5615 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
5616 | TRACE_FLAVOR_SIZE); | |
5617 | #endif | |
5618 | #ifdef TRACE_SET | |
5619 | fprintf_unfiltered (file, | |
5620 | "mips_dump_tdep: TRACE_SET # %s\n", | |
5621 | XSTRING (TRACE_SET (X,STATE))); | |
5622 | #endif | |
5623 | fprintf_unfiltered (file, | |
5624 | "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n"); | |
5625 | #ifdef UNUSED_REGNUM | |
5626 | fprintf_unfiltered (file, | |
5627 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", | |
5628 | UNUSED_REGNUM); | |
5629 | #endif | |
5630 | fprintf_unfiltered (file, | |
5631 | "mips_dump_tdep: V0_REGNUM = %d\n", | |
5632 | V0_REGNUM); | |
5633 | fprintf_unfiltered (file, | |
5634 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
5635 | (long) VM_MIN_ADDRESS); | |
5636 | #ifdef VX_NUM_REGS | |
5637 | fprintf_unfiltered (file, | |
5638 | "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n", | |
5639 | VX_NUM_REGS); | |
5640 | #endif | |
5641 | fprintf_unfiltered (file, | |
5642 | "mips_dump_tdep: ZERO_REGNUM = %d\n", | |
5643 | ZERO_REGNUM); | |
5644 | fprintf_unfiltered (file, | |
5645 | "mips_dump_tdep: _PROC_MAGIC_ = %d\n", | |
5646 | _PROC_MAGIC_); | |
70f80edf JT |
5647 | |
5648 | fprintf_unfiltered (file, | |
5649 | "mips_dump_tdep: OS ABI = %s\n", | |
5650 | gdbarch_osabi_name (tdep->osabi)); | |
c2d11a7d JM |
5651 | } |
5652 | ||
c906108c | 5653 | void |
acdb74a0 | 5654 | _initialize_mips_tdep (void) |
c906108c SS |
5655 | { |
5656 | static struct cmd_list_element *mipsfpulist = NULL; | |
5657 | struct cmd_list_element *c; | |
5658 | ||
2e4ebe70 DJ |
5659 | mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN]; |
5660 | if (MIPS_ABI_LAST + 1 | |
5661 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
5662 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
5663 | ||
4b9b3959 | 5664 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c5aa993b | 5665 | if (!tm_print_insn) /* Someone may have already set it */ |
c906108c SS |
5666 | tm_print_insn = gdb_print_insn_mips; |
5667 | ||
a5ea2558 AC |
5668 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
5669 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
5670 | "Various MIPS specific commands.", | |
5671 | &setmipscmdlist, "set mips ", 0, &setlist); | |
5672 | ||
5673 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
5674 | "Various MIPS specific commands.", | |
5675 | &showmipscmdlist, "show mips ", 0, &showlist); | |
5676 | ||
5677 | /* Allow the user to override the saved register size. */ | |
5678 | add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", | |
1ed2a135 AC |
5679 | class_obscure, |
5680 | size_enums, | |
5681 | &mips_saved_regsize_string, "\ | |
a5ea2558 AC |
5682 | Set size of general purpose registers saved on the stack.\n\ |
5683 | This option can be set to one of:\n\ | |
5684 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
5685 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
5686 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
5687 | saved GP register size from information contained in the executable.\n\ | |
5688 | (default: auto)", | |
1ed2a135 | 5689 | &setmipscmdlist), |
a5ea2558 AC |
5690 | &showmipscmdlist); |
5691 | ||
d929b26f AC |
5692 | /* Allow the user to override the argument stack size. */ |
5693 | add_show_from_set (add_set_enum_cmd ("stack-arg-size", | |
5694 | class_obscure, | |
5695 | size_enums, | |
1ed2a135 | 5696 | &mips_stack_argsize_string, "\ |
d929b26f AC |
5697 | Set the amount of stack space reserved for each argument.\n\ |
5698 | This option can be set to one of:\n\ | |
5699 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
5700 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
5701 | auto - Allow GDB to determine the correct setting from the current\n\ | |
5702 | target and executable (default)", | |
5703 | &setmipscmdlist), | |
5704 | &showmipscmdlist); | |
5705 | ||
2e4ebe70 DJ |
5706 | /* Allow the user to override the ABI. */ |
5707 | c = add_set_enum_cmd | |
5708 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
5709 | "Set the ABI used by this program.\n" | |
5710 | "This option can be set to one of:\n" | |
5711 | " auto - the default ABI associated with the current binary\n" | |
5712 | " o32\n" | |
5713 | " o64\n" | |
5714 | " n32\n" | |
f3a7b3a5 | 5715 | " n64\n" |
2e4ebe70 DJ |
5716 | " eabi32\n" |
5717 | " eabi64", | |
5718 | &setmipscmdlist); | |
5719 | add_show_from_set (c, &showmipscmdlist); | |
5720 | set_cmd_sfunc (c, mips_abi_update); | |
5721 | ||
c906108c SS |
5722 | /* Let the user turn off floating point and set the fence post for |
5723 | heuristic_proc_start. */ | |
5724 | ||
5725 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
5726 | "Set use of MIPS floating-point coprocessor.", | |
5727 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
5728 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
5729 | "Select single-precision MIPS floating-point coprocessor.", | |
5730 | &mipsfpulist); | |
5731 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 5732 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
5733 | &mipsfpulist); |
5734 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
5735 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
5736 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
5737 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
5738 | "Select no MIPS floating-point coprocessor.", | |
5739 | &mipsfpulist); | |
5740 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); | |
5741 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
5742 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
5743 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
5744 | "Select MIPS floating-point coprocessor automatically.", | |
5745 | &mipsfpulist); | |
5746 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
5747 | "Show current use of MIPS floating-point coprocessor target.", | |
5748 | &showlist); | |
5749 | ||
c906108c SS |
5750 | /* We really would like to have both "0" and "unlimited" work, but |
5751 | command.c doesn't deal with that. So make it a var_zinteger | |
5752 | because the user can always use "999999" or some such for unlimited. */ | |
5753 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, | |
5754 | (char *) &heuristic_fence_post, | |
5755 | "\ | |
5756 | Set the distance searched for the start of a function.\n\ | |
5757 | If you are debugging a stripped executable, GDB needs to search through the\n\ | |
5758 | program for the start of a function. This command sets the distance of the\n\ | |
5759 | search. The only need to set it is when debugging a stripped executable.", | |
5760 | &setlist); | |
5761 | /* We need to throw away the frame cache when we set this, since it | |
5762 | might change our ability to get backtraces. */ | |
9f60d481 | 5763 | set_cmd_sfunc (c, reinit_frame_cache_sfunc); |
c906108c SS |
5764 | add_show_from_set (c, &showlist); |
5765 | ||
5766 | /* Allow the user to control whether the upper bits of 64-bit | |
5767 | addresses should be zeroed. */ | |
e9e68a56 AC |
5768 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
5769 | Set zeroing of upper 32 bits of 64-bit addresses.\n\ | |
5770 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ | |
5771 | allow GDB to determine the correct value.\n", "\ | |
5772 | Show zeroing of upper 32 bits of 64-bit addresses.", | |
5773 | NULL, show_mask_address, | |
5774 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
5775 | |
5776 | /* Allow the user to control the size of 32 bit registers within the | |
5777 | raw remote packet. */ | |
5778 | add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs", | |
5779 | class_obscure, | |
5780 | var_boolean, | |
5781 | (char *)&mips64_transfers_32bit_regs_p, "\ | |
5782 | Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\ | |
5783 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ | |
5784 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
5785 | 64 bits for others. Use \"off\" to disable compatibility mode", | |
5786 | &setlist), | |
5787 | &showlist); | |
9ace0497 AC |
5788 | |
5789 | /* Debug this files internals. */ | |
5790 | add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger, | |
5791 | &mips_debug, "Set mips debugging.\n\ | |
5792 | When non-zero, mips specific debugging is enabled.", &setdebuglist), | |
5793 | &showdebuglist); | |
c906108c | 5794 | } |