Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4c38e0a4 JB |
4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, |
5 | 2010 Free Software Foundation, Inc. | |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 14 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 15 | (at your option) any later version. |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b | 22 | You should have received a copy of the GNU General Public License |
a9762ec7 | 23 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
24 | |
25 | #include "defs.h" | |
26 | #include "gdb_string.h" | |
5e2e9765 | 27 | #include "gdb_assert.h" |
c906108c SS |
28 | #include "frame.h" |
29 | #include "inferior.h" | |
30 | #include "symtab.h" | |
31 | #include "value.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "language.h" | |
34 | #include "gdbcore.h" | |
35 | #include "symfile.h" | |
36 | #include "objfiles.h" | |
37 | #include "gdbtypes.h" | |
38 | #include "target.h" | |
28d069e6 | 39 | #include "arch-utils.h" |
4e052eda | 40 | #include "regcache.h" |
70f80edf | 41 | #include "osabi.h" |
d1973055 | 42 | #include "mips-tdep.h" |
fe898f56 | 43 | #include "block.h" |
a4b8ebc8 | 44 | #include "reggroups.h" |
c906108c | 45 | #include "opcode/mips.h" |
c2d11a7d JM |
46 | #include "elf/mips.h" |
47 | #include "elf-bfd.h" | |
2475bac3 | 48 | #include "symcat.h" |
a4b8ebc8 | 49 | #include "sim-regno.h" |
a89aa300 | 50 | #include "dis-asm.h" |
edfae063 AC |
51 | #include "frame-unwind.h" |
52 | #include "frame-base.h" | |
53 | #include "trad-frame.h" | |
7d9b040b | 54 | #include "infcall.h" |
fed7ba43 | 55 | #include "floatformat.h" |
29709017 DJ |
56 | #include "remote.h" |
57 | #include "target-descriptions.h" | |
2bd0c3d7 | 58 | #include "dwarf2-frame.h" |
f8b73d13 | 59 | #include "user-regs.h" |
79a45b7d | 60 | #include "valprint.h" |
c906108c | 61 | |
8d5f9dcb DJ |
62 | static const struct objfile_data *mips_pdr_data; |
63 | ||
5bbcb741 | 64 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 65 | |
24e05951 | 66 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
67 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
68 | #define ST0_FR (1 << 26) | |
69 | ||
b0069a17 AC |
70 | /* The sizes of floating point registers. */ |
71 | ||
72 | enum | |
73 | { | |
74 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
75 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
76 | }; | |
77 | ||
1a69e1e4 DJ |
78 | enum |
79 | { | |
80 | MIPS32_REGSIZE = 4, | |
81 | MIPS64_REGSIZE = 8 | |
82 | }; | |
0dadbba0 | 83 | |
2e4ebe70 DJ |
84 | static const char *mips_abi_string; |
85 | ||
86 | static const char *mips_abi_strings[] = { | |
87 | "auto", | |
88 | "n32", | |
89 | "o32", | |
28d169de | 90 | "n64", |
2e4ebe70 DJ |
91 | "o64", |
92 | "eabi32", | |
93 | "eabi64", | |
94 | NULL | |
95 | }; | |
96 | ||
f8b73d13 DJ |
97 | /* The standard register names, and all the valid aliases for them. */ |
98 | struct register_alias | |
99 | { | |
100 | const char *name; | |
101 | int regnum; | |
102 | }; | |
103 | ||
104 | /* Aliases for o32 and most other ABIs. */ | |
105 | const struct register_alias mips_o32_aliases[] = { | |
106 | { "ta0", 12 }, | |
107 | { "ta1", 13 }, | |
108 | { "ta2", 14 }, | |
109 | { "ta3", 15 } | |
110 | }; | |
111 | ||
112 | /* Aliases for n32 and n64. */ | |
113 | const struct register_alias mips_n32_n64_aliases[] = { | |
114 | { "ta0", 8 }, | |
115 | { "ta1", 9 }, | |
116 | { "ta2", 10 }, | |
117 | { "ta3", 11 } | |
118 | }; | |
119 | ||
120 | /* Aliases for ABI-independent registers. */ | |
121 | const struct register_alias mips_register_aliases[] = { | |
122 | /* The architecture manuals specify these ABI-independent names for | |
123 | the GPRs. */ | |
124 | #define R(n) { "r" #n, n } | |
125 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
126 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
127 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
128 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
129 | #undef R | |
130 | ||
131 | /* k0 and k1 are sometimes called these instead (for "kernel | |
132 | temp"). */ | |
133 | { "kt0", 26 }, | |
134 | { "kt1", 27 }, | |
135 | ||
136 | /* This is the traditional GDB name for the CP0 status register. */ | |
137 | { "sr", MIPS_PS_REGNUM }, | |
138 | ||
139 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
140 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
141 | ||
142 | /* This is the traditional GDB name for the FCSR. */ | |
143 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
144 | }; | |
145 | ||
865093a3 AR |
146 | const struct register_alias mips_numeric_register_aliases[] = { |
147 | #define R(n) { #n, n } | |
148 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
149 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
150 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
151 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
152 | #undef R | |
153 | }; | |
154 | ||
c906108c SS |
155 | #ifndef MIPS_DEFAULT_FPU_TYPE |
156 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
157 | #endif | |
158 | static int mips_fpu_type_auto = 1; | |
159 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 160 | |
9ace0497 | 161 | static int mips_debug = 0; |
7a292a7a | 162 | |
29709017 DJ |
163 | /* Properties (for struct target_desc) describing the g/G packet |
164 | layout. */ | |
165 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
166 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
167 | ||
4eb0ad19 DJ |
168 | struct target_desc *mips_tdesc_gp32; |
169 | struct target_desc *mips_tdesc_gp64; | |
170 | ||
56cea623 AC |
171 | const struct mips_regnum * |
172 | mips_regnum (struct gdbarch *gdbarch) | |
173 | { | |
174 | return gdbarch_tdep (gdbarch)->regnum; | |
175 | } | |
176 | ||
177 | static int | |
178 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
179 | { | |
180 | return mips_regnum (gdbarch)->fp0 + 12; | |
181 | } | |
182 | ||
74ed0bb4 MD |
183 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
184 | == MIPS_ABI_EABI32 \ | |
185 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 186 | |
74ed0bb4 | 187 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 188 | |
74ed0bb4 | 189 | #define MIPS_LAST_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 190 | |
74ed0bb4 | 191 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 192 | |
95404a3e AC |
193 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
194 | functions to test, set, or clear bit 0 of addresses. */ | |
195 | ||
196 | static CORE_ADDR | |
197 | is_mips16_addr (CORE_ADDR addr) | |
198 | { | |
199 | return ((addr) & 1); | |
200 | } | |
201 | ||
95404a3e AC |
202 | static CORE_ADDR |
203 | unmake_mips16_addr (CORE_ADDR addr) | |
204 | { | |
5b652102 | 205 | return ((addr) & ~(CORE_ADDR) 1); |
95404a3e AC |
206 | } |
207 | ||
930bd0e0 KB |
208 | static CORE_ADDR |
209 | make_mips16_addr (CORE_ADDR addr) | |
210 | { | |
211 | return ((addr) | (CORE_ADDR) 1); | |
212 | } | |
213 | ||
d1973055 KB |
214 | /* Return the MIPS ABI associated with GDBARCH. */ |
215 | enum mips_abi | |
216 | mips_abi (struct gdbarch *gdbarch) | |
217 | { | |
218 | return gdbarch_tdep (gdbarch)->mips_abi; | |
219 | } | |
220 | ||
4246e332 | 221 | int |
1b13c4f6 | 222 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 223 | { |
29709017 DJ |
224 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
225 | ||
226 | /* If we know how big the registers are, use that size. */ | |
227 | if (tdep->register_size_valid_p) | |
228 | return tdep->register_size; | |
229 | ||
230 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
231 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
232 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
233 | } | |
234 | ||
480d3dd2 AC |
235 | /* Return the currently configured (or set) saved register size. */ |
236 | ||
e6bc2e8a | 237 | unsigned int |
13326b4e | 238 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 239 | { |
1a69e1e4 DJ |
240 | switch (mips_abi (gdbarch)) |
241 | { | |
242 | case MIPS_ABI_EABI32: | |
243 | case MIPS_ABI_O32: | |
244 | return 4; | |
245 | case MIPS_ABI_N32: | |
246 | case MIPS_ABI_N64: | |
247 | case MIPS_ABI_O64: | |
248 | case MIPS_ABI_EABI64: | |
249 | return 8; | |
250 | case MIPS_ABI_UNKNOWN: | |
251 | case MIPS_ABI_LAST: | |
252 | default: | |
253 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
254 | } | |
d929b26f AC |
255 | } |
256 | ||
71b8ef93 | 257 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 258 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 259 | "info" field is used for this purpose. |
5a89d8aa | 260 | |
95f1da47 | 261 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
5a89d8aa MS |
262 | i.e. refers to a 16-bit function, and sets a "special" bit in a |
263 | minimal symbol to mark it as a 16-bit function | |
264 | ||
f594e5e9 | 265 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 266 | |
5a89d8aa | 267 | static void |
6d82d43b AC |
268 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
269 | { | |
270 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
271 | { | |
b887350f | 272 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; |
6d82d43b | 273 | } |
5a89d8aa MS |
274 | } |
275 | ||
71b8ef93 MS |
276 | static int |
277 | msymbol_is_special (struct minimal_symbol *msym) | |
278 | { | |
b887350f | 279 | return MSYMBOL_TARGET_FLAG_1 (msym); |
71b8ef93 MS |
280 | } |
281 | ||
88658117 AC |
282 | /* XFER a value from the big/little/left end of the register. |
283 | Depending on the size of the value it might occupy the entire | |
284 | register or just part of it. Make an allowance for this, aligning | |
285 | things accordingly. */ | |
286 | ||
287 | static void | |
ba32f989 DJ |
288 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
289 | int reg_num, int length, | |
870cd05e MK |
290 | enum bfd_endian endian, gdb_byte *in, |
291 | const gdb_byte *out, int buf_offset) | |
88658117 | 292 | { |
88658117 | 293 | int reg_offset = 0; |
72a155b4 UW |
294 | |
295 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
296 | /* Need to transfer the left or right part of the register, based on |
297 | the targets byte order. */ | |
88658117 AC |
298 | switch (endian) |
299 | { | |
300 | case BFD_ENDIAN_BIG: | |
72a155b4 | 301 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
302 | break; |
303 | case BFD_ENDIAN_LITTLE: | |
304 | reg_offset = 0; | |
305 | break; | |
6d82d43b | 306 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
307 | reg_offset = 0; |
308 | break; | |
309 | default: | |
e2e0b3e5 | 310 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
311 | } |
312 | if (mips_debug) | |
cb1d2653 AC |
313 | fprintf_unfiltered (gdb_stderr, |
314 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
315 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
316 | if (mips_debug && out != NULL) |
317 | { | |
318 | int i; | |
cb1d2653 | 319 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 320 | for (i = 0; i < length; i++) |
cb1d2653 | 321 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
322 | } |
323 | if (in != NULL) | |
6d82d43b AC |
324 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
325 | in + buf_offset); | |
88658117 | 326 | if (out != NULL) |
6d82d43b AC |
327 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
328 | out + buf_offset); | |
88658117 AC |
329 | if (mips_debug && in != NULL) |
330 | { | |
331 | int i; | |
cb1d2653 | 332 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 333 | for (i = 0; i < length; i++) |
cb1d2653 | 334 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
335 | } |
336 | if (mips_debug) | |
337 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
338 | } | |
339 | ||
dd824b04 DJ |
340 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
341 | compatiblity mode. A return value of 1 means that we have | |
342 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
343 | ||
344 | static int | |
9c9acae0 | 345 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 346 | { |
72a155b4 | 347 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
348 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
349 | meaningful. */ | |
72a155b4 | 350 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
351 | return 0; |
352 | ||
353 | #if 0 | |
354 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
355 | in all the places we deal with FP registers. PR gdb/413. */ | |
356 | /* Otherwise check the FR bit in the status register - it controls | |
357 | the FP compatiblity mode. If it is clear we are in compatibility | |
358 | mode. */ | |
9c9acae0 | 359 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
360 | return 1; |
361 | #endif | |
361d1df0 | 362 | |
dd824b04 DJ |
363 | return 0; |
364 | } | |
365 | ||
7a292a7a | 366 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 367 | |
74ed0bb4 | 368 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 369 | |
a14ed312 | 370 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 371 | |
acdb74a0 AC |
372 | /* The list of available "set mips " and "show mips " commands */ |
373 | ||
374 | static struct cmd_list_element *setmipscmdlist = NULL; | |
375 | static struct cmd_list_element *showmipscmdlist = NULL; | |
376 | ||
5e2e9765 KB |
377 | /* Integer registers 0 thru 31 are handled explicitly by |
378 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 379 | are listed in the following tables. */ |
691c0433 | 380 | |
6d82d43b AC |
381 | enum |
382 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
383 | |
384 | /* Generic MIPS. */ | |
385 | ||
386 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
387 | "sr", "lo", "hi", "bad", "cause", "pc", |
388 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
389 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
390 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
391 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
392 | "fsr", "fir", "" /*"fp" */ , "", | |
393 | "", "", "", "", "", "", "", "", | |
394 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
395 | }; |
396 | ||
397 | /* Names of IDT R3041 registers. */ | |
398 | ||
399 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
400 | "sr", "lo", "hi", "bad", "cause", "pc", |
401 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
402 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
403 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
404 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
405 | "fsr", "fir", "", /*"fp" */ "", | |
406 | "", "", "bus", "ccfg", "", "", "", "", | |
407 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
408 | }; |
409 | ||
410 | /* Names of tx39 registers. */ | |
411 | ||
412 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
413 | "sr", "lo", "hi", "bad", "cause", "pc", |
414 | "", "", "", "", "", "", "", "", | |
415 | "", "", "", "", "", "", "", "", | |
416 | "", "", "", "", "", "", "", "", | |
417 | "", "", "", "", "", "", "", "", | |
418 | "", "", "", "", | |
419 | "", "", "", "", "", "", "", "", | |
420 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
421 | }; |
422 | ||
423 | /* Names of IRIX registers. */ | |
424 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
425 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
426 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
427 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
428 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
429 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
430 | }; |
431 | ||
cce74817 | 432 | |
5e2e9765 | 433 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 434 | static const char * |
d93859e2 | 435 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 436 | { |
d93859e2 | 437 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 KB |
438 | /* GPR names for all ABIs other than n32/n64. */ |
439 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
440 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
441 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
442 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
443 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
444 | }; |
445 | ||
446 | /* GPR names for n32 and n64 ABIs. */ | |
447 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
448 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
449 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
450 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
451 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
452 | }; |
453 | ||
d93859e2 | 454 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 455 | |
f57d151a | 456 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
6229fbea HZ |
457 | but then don't make the raw register names visible. This (upper) |
458 | range of user visible register numbers are the pseudo-registers. | |
459 | ||
460 | This approach was adopted accommodate the following scenario: | |
461 | It is possible to debug a 64-bit device using a 32-bit | |
462 | programming model. In such instances, the raw registers are | |
463 | configured to be 64-bits wide, while the pseudo registers are | |
464 | configured to be 32-bits wide. The registers that the user | |
465 | sees - the pseudo registers - match the users expectations | |
466 | given the programming model being used. */ | |
d93859e2 UW |
467 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
468 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
469 | return ""; |
470 | ||
5e2e9765 KB |
471 | /* The MIPS integer registers are always mapped from 0 to 31. The |
472 | names of the registers (which reflects the conventions regarding | |
473 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 474 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
475 | { |
476 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 477 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 478 | else |
a4b8ebc8 | 479 | return mips_gpr_names[rawnum]; |
5e2e9765 | 480 | } |
d93859e2 UW |
481 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
482 | return tdesc_register_name (gdbarch, rawnum); | |
483 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
484 | { |
485 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
486 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
487 | } | |
5e2e9765 KB |
488 | else |
489 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 490 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 491 | } |
5e2e9765 | 492 | |
a4b8ebc8 | 493 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 494 | |
a4b8ebc8 AC |
495 | static int |
496 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
497 | struct reggroup *reggroup) | |
498 | { | |
499 | int vector_p; | |
500 | int float_p; | |
501 | int raw_p; | |
72a155b4 UW |
502 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
503 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
504 | if (reggroup == all_reggroup) |
505 | return pseudo; | |
506 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
507 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
508 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
509 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
510 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
511 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
512 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
513 | return 0; |
514 | if (reggroup == float_reggroup) | |
515 | return float_p && pseudo; | |
516 | if (reggroup == vector_reggroup) | |
517 | return vector_p && pseudo; | |
518 | if (reggroup == general_reggroup) | |
519 | return (!vector_p && !float_p) && pseudo; | |
520 | /* Save the pseudo registers. Need to make certain that any code | |
521 | extracting register values from a saved register cache also uses | |
522 | pseudo registers. */ | |
523 | if (reggroup == save_reggroup) | |
524 | return raw_p && pseudo; | |
525 | /* Restore the same pseudo register. */ | |
526 | if (reggroup == restore_reggroup) | |
527 | return raw_p && pseudo; | |
6d82d43b | 528 | return 0; |
a4b8ebc8 AC |
529 | } |
530 | ||
f8b73d13 DJ |
531 | /* Return the groups that a MIPS register can be categorised into. |
532 | This version is only used if we have a target description which | |
533 | describes real registers (and their groups). */ | |
534 | ||
535 | static int | |
536 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
537 | struct reggroup *reggroup) | |
538 | { | |
539 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
540 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
541 | int ret; | |
542 | ||
543 | /* Only save, restore, and display the pseudo registers. Need to | |
544 | make certain that any code extracting register values from a | |
545 | saved register cache also uses pseudo registers. | |
546 | ||
547 | Note: saving and restoring the pseudo registers is slightly | |
548 | strange; if we have 64 bits, we should save and restore all | |
549 | 64 bits. But this is hard and has little benefit. */ | |
550 | if (!pseudo) | |
551 | return 0; | |
552 | ||
553 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
554 | if (ret != -1) | |
555 | return ret; | |
556 | ||
557 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
558 | } | |
559 | ||
a4b8ebc8 | 560 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 561 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 562 | registers. Take care of alignment and size problems. */ |
c5aa993b | 563 | |
a4b8ebc8 AC |
564 | static void |
565 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
47a35522 | 566 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 567 | { |
72a155b4 UW |
568 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
569 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
570 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 571 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 572 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
573 | else if (register_size (gdbarch, rawnum) > |
574 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 575 | { |
8bdf35dc | 576 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
47ebcfbe AC |
577 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
578 | else | |
8bdf35dc KB |
579 | { |
580 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
581 | LONGEST regval; | |
582 | regcache_raw_read_signed (regcache, rawnum, ®val); | |
583 | store_signed_integer (buf, 4, byte_order, regval); | |
584 | } | |
47ebcfbe AC |
585 | } |
586 | else | |
e2e0b3e5 | 587 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
588 | } |
589 | ||
590 | static void | |
6d82d43b AC |
591 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
592 | struct regcache *regcache, int cookednum, | |
47a35522 | 593 | const gdb_byte *buf) |
a4b8ebc8 | 594 | { |
72a155b4 UW |
595 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
596 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
597 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 598 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 599 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
600 | else if (register_size (gdbarch, rawnum) > |
601 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 602 | { |
8bdf35dc | 603 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
47ebcfbe AC |
604 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
605 | else | |
8bdf35dc KB |
606 | { |
607 | /* Sign extend the shortened version of the register prior | |
608 | to placing it in the raw register. This is required for | |
609 | some mips64 parts in order to avoid unpredictable behavior. */ | |
610 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
611 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); | |
612 | regcache_raw_write_signed (regcache, rawnum, regval); | |
613 | } | |
47ebcfbe AC |
614 | } |
615 | else | |
e2e0b3e5 | 616 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 617 | } |
c5aa993b | 618 | |
c906108c | 619 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 620 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
621 | |
622 | /* Heuristic_proc_start may hunt through the text section for a long | |
623 | time across a 2400 baud serial line. Allows the user to limit this | |
624 | search. */ | |
625 | ||
626 | static unsigned int heuristic_fence_post = 0; | |
627 | ||
46cd78fb | 628 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
629 | register N. NOTE: This defines the pseudo register type so need to |
630 | rebuild the architecture vector. */ | |
43e526b9 JM |
631 | |
632 | static int mips64_transfers_32bit_regs_p = 0; | |
633 | ||
719ec221 AC |
634 | static void |
635 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
636 | struct cmd_list_element *c) | |
43e526b9 | 637 | { |
719ec221 AC |
638 | struct gdbarch_info info; |
639 | gdbarch_info_init (&info); | |
640 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
641 | instead of relying on globals. Doing that would let generic code | |
642 | handle the search for this specific architecture. */ | |
643 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 644 | { |
719ec221 | 645 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 646 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 647 | } |
a4b8ebc8 AC |
648 | } |
649 | ||
47ebcfbe | 650 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 651 | |
ee51a8c7 KB |
652 | /* This predicate tests for the case of an 8 byte floating point |
653 | value that is being transferred to or from a pair of floating point | |
654 | registers each of which are (or are considered to be) only 4 bytes | |
655 | wide. */ | |
ff2e87ac | 656 | static int |
ee51a8c7 KB |
657 | mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
658 | struct type *type) | |
ff2e87ac | 659 | { |
0abe36f5 MD |
660 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
661 | && register_size (gdbarch, regnum) == 4 | |
662 | && (regnum % gdbarch_num_regs (gdbarch)) | |
663 | >= mips_regnum (gdbarch)->fp0 | |
664 | && (regnum % gdbarch_num_regs (gdbarch)) | |
665 | < mips_regnum (gdbarch)->fp0 + 32 | |
6d82d43b | 666 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
667 | } |
668 | ||
ee51a8c7 KB |
669 | /* This predicate tests for the case of a value of less than 8 |
670 | bytes in width that is being transfered to or from an 8 byte | |
671 | general purpose register. */ | |
672 | static int | |
673 | mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, | |
674 | struct type *type) | |
675 | { | |
676 | int num_regs = gdbarch_num_regs (gdbarch); | |
677 | ||
678 | return (register_size (gdbarch, regnum) == 8 | |
679 | && regnum % num_regs > 0 && regnum % num_regs < 32 | |
680 | && TYPE_LENGTH (type) < 8); | |
681 | } | |
682 | ||
683 | static int | |
684 | mips_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type) | |
685 | { | |
686 | return mips_convert_register_float_case_p (gdbarch, regnum, type) | |
687 | || mips_convert_register_gpreg_case_p (gdbarch, regnum, type); | |
688 | } | |
689 | ||
42c466d7 | 690 | static void |
ff2e87ac | 691 | mips_register_to_value (struct frame_info *frame, int regnum, |
47a35522 | 692 | struct type *type, gdb_byte *to) |
102182a9 | 693 | { |
ee51a8c7 KB |
694 | struct gdbarch *gdbarch = get_frame_arch (frame); |
695 | ||
696 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
697 | { | |
698 | get_frame_register (frame, regnum + 0, to + 4); | |
699 | get_frame_register (frame, regnum + 1, to + 0); | |
700 | } | |
701 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
702 | { | |
703 | int len = TYPE_LENGTH (type); | |
704 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
705 | get_frame_register_bytes (frame, regnum, 8 - len, len, to); | |
706 | else | |
707 | get_frame_register_bytes (frame, regnum, 0, len, to); | |
708 | } | |
709 | else | |
710 | { | |
711 | internal_error (__FILE__, __LINE__, | |
712 | _("mips_register_to_value: unrecognized case")); | |
713 | } | |
102182a9 MS |
714 | } |
715 | ||
42c466d7 | 716 | static void |
ff2e87ac | 717 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 718 | struct type *type, const gdb_byte *from) |
102182a9 | 719 | { |
ee51a8c7 KB |
720 | struct gdbarch *gdbarch = get_frame_arch (frame); |
721 | ||
722 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
723 | { | |
724 | put_frame_register (frame, regnum + 0, from + 4); | |
725 | put_frame_register (frame, regnum + 1, from + 0); | |
726 | } | |
727 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
728 | { | |
729 | gdb_byte fill[8]; | |
730 | int len = TYPE_LENGTH (type); | |
731 | ||
732 | /* Sign extend values, irrespective of type, that are stored to | |
733 | a 64-bit general purpose register. (32-bit unsigned values | |
734 | are stored as signed quantities within a 64-bit register. | |
735 | When performing an operation, in compiled code, that combines | |
736 | a 32-bit unsigned value with a signed 64-bit value, a type | |
737 | conversion is first performed that zeroes out the high 32 bits.) */ | |
738 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
739 | { | |
740 | if (from[0] & 0x80) | |
741 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); | |
742 | else | |
743 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); | |
744 | put_frame_register_bytes (frame, regnum, 0, 8 - len, fill); | |
745 | put_frame_register_bytes (frame, regnum, 8 - len, len, from); | |
746 | } | |
747 | else | |
748 | { | |
749 | if (from[len-1] & 0x80) | |
750 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); | |
751 | else | |
752 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); | |
753 | put_frame_register_bytes (frame, regnum, 0, len, from); | |
754 | put_frame_register_bytes (frame, regnum, len, 8 - len, fill); | |
755 | } | |
756 | } | |
757 | else | |
758 | { | |
759 | internal_error (__FILE__, __LINE__, | |
760 | _("mips_value_to_register: unrecognized case")); | |
761 | } | |
102182a9 MS |
762 | } |
763 | ||
a4b8ebc8 AC |
764 | /* Return the GDB type object for the "standard" data type of data in |
765 | register REG. */ | |
78fde5f8 KB |
766 | |
767 | static struct type * | |
a4b8ebc8 AC |
768 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
769 | { | |
72a155b4 UW |
770 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
771 | if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0 | |
772 | && (regnum % gdbarch_num_regs (gdbarch)) | |
773 | < mips_regnum (gdbarch)->fp0 + 32) | |
a6425924 | 774 | { |
5ef80fb0 | 775 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 776 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 777 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 778 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 779 | else |
27067745 | 780 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 781 | } |
72a155b4 | 782 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
783 | { |
784 | /* The raw or ISA registers. These are all sized according to | |
785 | the ISA regsize. */ | |
786 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 787 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 788 | else |
df4df182 | 789 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 790 | } |
78fde5f8 | 791 | else |
d5ac5a39 AC |
792 | { |
793 | /* The cooked or ABI registers. These are sized according to | |
794 | the ABI (with a few complications). */ | |
72a155b4 UW |
795 | if (regnum >= (gdbarch_num_regs (gdbarch) |
796 | + mips_regnum (gdbarch)->fp_control_status) | |
797 | && regnum <= gdbarch_num_regs (gdbarch) + MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
798 | /* The pseudo/cooked view of the embedded registers is always |
799 | 32-bit. The raw view is handled below. */ | |
df4df182 | 800 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
801 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
802 | /* The target, while possibly using a 64-bit register buffer, | |
803 | is only transfering 32-bits of each integer register. | |
804 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 805 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
806 | else if (mips_abi_regsize (gdbarch) == 4) |
807 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
808 | 32- or 64-bit). */ | |
df4df182 | 809 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
810 | else |
811 | /* 64-bit ABI. */ | |
df4df182 | 812 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 813 | } |
78fde5f8 KB |
814 | } |
815 | ||
f8b73d13 DJ |
816 | /* Return the GDB type for the pseudo register REGNUM, which is the |
817 | ABI-level view. This function is only called if there is a target | |
818 | description which includes registers, so we know precisely the | |
819 | types of hardware registers. */ | |
820 | ||
821 | static struct type * | |
822 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
823 | { | |
824 | const int num_regs = gdbarch_num_regs (gdbarch); | |
825 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
826 | int rawnum = regnum % num_regs; | |
827 | struct type *rawtype; | |
828 | ||
829 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
830 | ||
831 | /* Absent registers are still absent. */ | |
832 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
833 | if (TYPE_LENGTH (rawtype) == 0) | |
834 | return rawtype; | |
835 | ||
836 | if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32) | |
837 | /* Present the floating point registers however the hardware did; | |
838 | do not try to convert between FPU layouts. */ | |
839 | return rawtype; | |
840 | ||
841 | if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
842 | { | |
843 | /* The pseudo/cooked view of embedded registers is always | |
844 | 32-bit, even if the target transfers 64-bit values for them. | |
845 | New targets relying on XML descriptions should only transfer | |
846 | the necessary 32 bits, but older versions of GDB expected 64, | |
847 | so allow the target to provide 64 bits without interfering | |
848 | with the displayed type. */ | |
df4df182 | 849 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 DJ |
850 | } |
851 | ||
852 | /* Use pointer types for registers if we can. For n32 we can not, | |
853 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
854 | if (mips_abi_regsize (gdbarch) |
855 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 DJ |
856 | { |
857 | if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM) | |
0dfff4cb | 858 | return builtin_type (gdbarch)->builtin_data_ptr; |
f8b73d13 | 859 | else if (rawnum == MIPS_EMBED_PC_REGNUM) |
0dfff4cb | 860 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
861 | } |
862 | ||
863 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
864 | && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM) | |
df4df182 | 865 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 DJ |
866 | |
867 | /* For all other registers, pass through the hardware type. */ | |
868 | return rawtype; | |
869 | } | |
bcb0cc15 | 870 | |
c906108c | 871 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 872 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
873 | |
874 | static int | |
480d3dd2 | 875 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
876 | { |
877 | switch (mask_address_var) | |
878 | { | |
7f19b9a2 | 879 | case AUTO_BOOLEAN_TRUE: |
4014092b | 880 | return 1; |
7f19b9a2 | 881 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
882 | return 0; |
883 | break; | |
7f19b9a2 | 884 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 885 | return tdep->default_mask_address_p; |
4014092b | 886 | default: |
e2e0b3e5 | 887 | internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch")); |
4014092b | 888 | return -1; |
361d1df0 | 889 | } |
4014092b AC |
890 | } |
891 | ||
892 | static void | |
08546159 AC |
893 | show_mask_address (struct ui_file *file, int from_tty, |
894 | struct cmd_list_element *c, const char *value) | |
4014092b | 895 | { |
1cf3db46 | 896 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
08546159 AC |
897 | |
898 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
899 | switch (mask_address_var) |
900 | { | |
7f19b9a2 | 901 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
902 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
903 | break; | |
7f19b9a2 | 904 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
905 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
906 | break; | |
7f19b9a2 | 907 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
908 | printf_filtered |
909 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
910 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
911 | break; |
912 | default: | |
e2e0b3e5 | 913 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 914 | break; |
361d1df0 | 915 | } |
4014092b | 916 | } |
c906108c | 917 | |
c906108c SS |
918 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
919 | ||
0fe7e7c8 AC |
920 | int |
921 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
922 | { |
923 | struct minimal_symbol *sym; | |
924 | ||
925 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 926 | if (is_mips16_addr (memaddr)) |
c906108c SS |
927 | return 1; |
928 | ||
929 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
930 | the high bit of the info field. Use this to decide if the function is | |
931 | MIPS16 or normal MIPS. */ | |
932 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
933 | if (sym) | |
71b8ef93 | 934 | return msymbol_is_special (sym); |
c906108c SS |
935 | else |
936 | return 0; | |
937 | } | |
938 | ||
b2fa5097 | 939 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
940 | all registers should be sign extended for simplicity? */ |
941 | ||
942 | static CORE_ADDR | |
61a1198a | 943 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 944 | { |
61a1198a UW |
945 | ULONGEST pc; |
946 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; | |
947 | regcache_cooked_read_signed (regcache, regnum, &pc); | |
930bd0e0 KB |
948 | if (is_mips16_addr (pc)) |
949 | pc = unmake_mips16_addr (pc); | |
61a1198a | 950 | return pc; |
b6cb9035 AC |
951 | } |
952 | ||
58dfe9ff AC |
953 | static CORE_ADDR |
954 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
955 | { | |
930bd0e0 KB |
956 | ULONGEST pc; |
957 | ||
958 | pc = frame_unwind_register_signed | |
959 | (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc); | |
960 | if (is_mips16_addr (pc)) | |
961 | pc = unmake_mips16_addr (pc); | |
962 | return pc; | |
edfae063 AC |
963 | } |
964 | ||
30244cd8 UW |
965 | static CORE_ADDR |
966 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
967 | { | |
72a155b4 UW |
968 | return frame_unwind_register_signed |
969 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
970 | } |
971 | ||
b8a22b94 | 972 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
973 | dummy frame. The frame ID's base needs to match the TOS value |
974 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
975 | breakpoint. */ | |
976 | ||
977 | static struct frame_id | |
b8a22b94 | 978 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 979 | { |
f57d151a | 980 | return frame_id_build |
b8a22b94 DJ |
981 | (get_frame_register_signed (this_frame, |
982 | gdbarch_num_regs (gdbarch) | |
983 | + MIPS_SP_REGNUM), | |
984 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
985 | } |
986 | ||
b6cb9035 | 987 | static void |
61a1198a | 988 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 989 | { |
61a1198a | 990 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; |
930bd0e0 KB |
991 | if (mips_pc_is_mips16 (pc)) |
992 | regcache_cooked_write_unsigned (regcache, regnum, make_mips16_addr (pc)); | |
993 | else | |
994 | regcache_cooked_write_unsigned (regcache, regnum, pc); | |
6c997a34 | 995 | } |
c906108c | 996 | |
c906108c SS |
997 | /* Fetch and return instruction from the specified location. If the PC |
998 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
999 | ||
d37cca3d | 1000 | static ULONGEST |
e17a4113 | 1001 | mips_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr) |
c906108c | 1002 | { |
e17a4113 | 1003 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1004 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
1005 | int instlen; |
1006 | int status; | |
1007 | ||
0fe7e7c8 | 1008 | if (mips_pc_is_mips16 (addr)) |
c906108c | 1009 | { |
95ac2dcf | 1010 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 1011 | addr = unmake_mips16_addr (addr); |
c906108c SS |
1012 | } |
1013 | else | |
95ac2dcf | 1014 | instlen = MIPS_INSN32_SIZE; |
8defab1a | 1015 | status = target_read_memory (addr, buf, instlen); |
c906108c SS |
1016 | if (status) |
1017 | memory_error (status, addr); | |
e17a4113 | 1018 | return extract_unsigned_integer (buf, instlen, byte_order); |
c906108c SS |
1019 | } |
1020 | ||
c906108c | 1021 | /* These the fields of 32 bit mips instructions */ |
e135b889 DJ |
1022 | #define mips32_op(x) (x >> 26) |
1023 | #define itype_op(x) (x >> 26) | |
1024 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1025 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1026 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1027 | |
e135b889 DJ |
1028 | #define jtype_op(x) (x >> 26) |
1029 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1030 | |
e135b889 DJ |
1031 | #define rtype_op(x) (x >> 26) |
1032 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1033 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1034 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1035 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1036 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 1037 | |
06987e64 MK |
1038 | static LONGEST |
1039 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 1040 | { |
06987e64 | 1041 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
1042 | } |
1043 | ||
f49e4e6d MS |
1044 | /* Determine where to set a single step breakpoint while considering |
1045 | branch prediction. */ | |
5a89d8aa | 1046 | static CORE_ADDR |
0b1b3e42 | 1047 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b | 1048 | { |
e17a4113 | 1049 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c5aa993b JM |
1050 | unsigned long inst; |
1051 | int op; | |
e17a4113 | 1052 | inst = mips_fetch_instruction (gdbarch, pc); |
e135b889 | 1053 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 1054 | { |
e135b889 | 1055 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1056 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1057 | { |
e135b889 | 1058 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1059 | switch (op) |
1060 | { | |
e135b889 DJ |
1061 | case 0: /* BEQL */ |
1062 | goto equal_branch; | |
1063 | case 1: /* BNEL */ | |
1064 | goto neq_branch; | |
1065 | case 2: /* BLEZL */ | |
1066 | goto less_branch; | |
313628cc | 1067 | case 3: /* BGTZL */ |
e135b889 | 1068 | goto greater_branch; |
c5aa993b JM |
1069 | default: |
1070 | pc += 4; | |
c906108c SS |
1071 | } |
1072 | } | |
e135b889 | 1073 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1074 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
1075 | { |
1076 | int tf = itype_rt (inst) & 0x01; | |
1077 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b | 1078 | int fcrcs = |
72a155b4 UW |
1079 | get_frame_register_signed (frame, |
1080 | mips_regnum (get_frame_arch (frame))-> | |
0b1b3e42 | 1081 | fp_control_status); |
e135b889 DJ |
1082 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1083 | ||
1084 | if (((cond >> cnum) & 0x01) == tf) | |
1085 | pc += mips32_relative_offset (inst) + 4; | |
1086 | else | |
1087 | pc += 8; | |
1088 | } | |
c5aa993b JM |
1089 | else |
1090 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1091 | } |
1092 | else | |
c5aa993b JM |
1093 | { /* This gets way messy */ |
1094 | ||
c906108c | 1095 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1096 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1097 | { |
c5aa993b JM |
1098 | case 0: /* SPECIAL */ |
1099 | op = rtype_funct (inst); | |
1100 | switch (op) | |
1101 | { | |
1102 | case 8: /* JR */ | |
1103 | case 9: /* JALR */ | |
6c997a34 | 1104 | /* Set PC to that address */ |
0b1b3e42 | 1105 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b | 1106 | break; |
e38d4e1a DJ |
1107 | case 12: /* SYSCALL */ |
1108 | { | |
1109 | struct gdbarch_tdep *tdep; | |
1110 | ||
1111 | tdep = gdbarch_tdep (get_frame_arch (frame)); | |
1112 | if (tdep->syscall_next_pc != NULL) | |
1113 | pc = tdep->syscall_next_pc (frame); | |
1114 | else | |
1115 | pc += 4; | |
1116 | } | |
1117 | break; | |
c5aa993b JM |
1118 | default: |
1119 | pc += 4; | |
1120 | } | |
1121 | ||
6d82d43b | 1122 | break; /* end SPECIAL */ |
c5aa993b | 1123 | case 1: /* REGIMM */ |
c906108c | 1124 | { |
e135b889 DJ |
1125 | op = itype_rt (inst); /* branch condition */ |
1126 | switch (op) | |
c906108c | 1127 | { |
c5aa993b | 1128 | case 0: /* BLTZ */ |
e135b889 DJ |
1129 | case 2: /* BLTZL */ |
1130 | case 16: /* BLTZAL */ | |
c5aa993b | 1131 | case 18: /* BLTZALL */ |
c906108c | 1132 | less_branch: |
0b1b3e42 | 1133 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1134 | pc += mips32_relative_offset (inst) + 4; |
1135 | else | |
1136 | pc += 8; /* after the delay slot */ | |
1137 | break; | |
e135b889 | 1138 | case 1: /* BGEZ */ |
c5aa993b JM |
1139 | case 3: /* BGEZL */ |
1140 | case 17: /* BGEZAL */ | |
1141 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1142 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1143 | pc += mips32_relative_offset (inst) + 4; |
1144 | else | |
1145 | pc += 8; /* after the delay slot */ | |
1146 | break; | |
e135b889 | 1147 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1148 | default: |
1149 | pc += 4; | |
c906108c SS |
1150 | } |
1151 | } | |
6d82d43b | 1152 | break; /* end REGIMM */ |
c5aa993b JM |
1153 | case 2: /* J */ |
1154 | case 3: /* JAL */ | |
1155 | { | |
1156 | unsigned long reg; | |
1157 | reg = jtype_target (inst) << 2; | |
e135b889 | 1158 | /* Upper four bits get never changed... */ |
5b652102 | 1159 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1160 | } |
c5aa993b JM |
1161 | break; |
1162 | /* FIXME case JALX : */ | |
1163 | { | |
1164 | unsigned long reg; | |
1165 | reg = jtype_target (inst) << 2; | |
5b652102 | 1166 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ |
c906108c SS |
1167 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1168 | } | |
c5aa993b | 1169 | break; /* The new PC will be alternate mode */ |
e135b889 | 1170 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1171 | equal_branch: |
0b1b3e42 UW |
1172 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1173 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1174 | pc += mips32_relative_offset (inst) + 4; |
1175 | else | |
1176 | pc += 8; | |
1177 | break; | |
e135b889 | 1178 | case 5: /* BNE, BNEL */ |
c5aa993b | 1179 | neq_branch: |
0b1b3e42 UW |
1180 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1181 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1182 | pc += mips32_relative_offset (inst) + 4; |
1183 | else | |
1184 | pc += 8; | |
1185 | break; | |
e135b889 | 1186 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1187 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1188 | pc += mips32_relative_offset (inst) + 4; |
1189 | else | |
1190 | pc += 8; | |
1191 | break; | |
1192 | case 7: | |
e135b889 DJ |
1193 | default: |
1194 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1195 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1196 | pc += mips32_relative_offset (inst) + 4; |
1197 | else | |
1198 | pc += 8; | |
1199 | break; | |
c5aa993b JM |
1200 | } /* switch */ |
1201 | } /* else */ | |
1202 | return pc; | |
1203 | } /* mips32_next_pc */ | |
c906108c SS |
1204 | |
1205 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1206 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1207 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1208 | We dont want to set a single step instruction on the extend instruction | |
1209 | either. | |
c5aa993b | 1210 | */ |
c906108c SS |
1211 | |
1212 | /* Lots of mips16 instruction formats */ | |
1213 | /* Predicting jumps requires itype,ritype,i8type | |
1214 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1215 | */ |
c906108c SS |
1216 | enum mips16_inst_fmts |
1217 | { | |
c5aa993b JM |
1218 | itype, /* 0 immediate 5,10 */ |
1219 | ritype, /* 1 5,3,8 */ | |
1220 | rrtype, /* 2 5,3,3,5 */ | |
1221 | rritype, /* 3 5,3,3,5 */ | |
1222 | rrrtype, /* 4 5,3,3,3,2 */ | |
1223 | rriatype, /* 5 5,3,3,1,4 */ | |
1224 | shifttype, /* 6 5,3,3,3,2 */ | |
1225 | i8type, /* 7 5,3,8 */ | |
1226 | i8movtype, /* 8 5,3,3,5 */ | |
1227 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1228 | i64type, /* 10 5,3,8 */ | |
1229 | ri64type, /* 11 5,3,3,5 */ | |
1230 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1231 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1232 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1233 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1234 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1235 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1236 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1237 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1238 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1239 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1240 | }; | |
12f02c2a AC |
1241 | /* I am heaping all the fields of the formats into one structure and |
1242 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1243 | struct upk_mips16 |
6d82d43b AC |
1244 | { |
1245 | CORE_ADDR offset; | |
1246 | unsigned int regx; /* Function in i8 type */ | |
1247 | unsigned int regy; | |
1248 | }; | |
c906108c SS |
1249 | |
1250 | ||
12f02c2a | 1251 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 1252 | for the bits which make up the immediate extension. */ |
c906108c | 1253 | |
12f02c2a AC |
1254 | static CORE_ADDR |
1255 | extended_offset (unsigned int extension) | |
c906108c | 1256 | { |
12f02c2a | 1257 | CORE_ADDR value; |
c5aa993b JM |
1258 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1259 | value = value << 6; | |
1260 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1261 | value = value << 5; | |
1262 | value |= extension & 0x01f; /* extract 4:0 */ | |
1263 | return value; | |
c906108c SS |
1264 | } |
1265 | ||
1266 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
1267 | instruction. It won't malfunction, but why make excess remote memory |
1268 | references? If the immediate operands get sign extended or something, | |
1269 | do it after the extension is performed. */ | |
c906108c | 1270 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 1271 | when the offset is to be used in relative addressing. */ |
c906108c | 1272 | |
12f02c2a | 1273 | static unsigned int |
e17a4113 | 1274 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 1275 | { |
e17a4113 | 1276 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1277 | gdb_byte buf[8]; |
c5aa993b JM |
1278 | pc &= 0xfffffffe; /* clear the low order bit */ |
1279 | target_read_memory (pc, buf, 2); | |
e17a4113 | 1280 | return extract_unsigned_integer (buf, 2, byte_order); |
c906108c SS |
1281 | } |
1282 | ||
1283 | static void | |
e17a4113 | 1284 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
12f02c2a AC |
1285 | unsigned int extension, |
1286 | unsigned int inst, | |
6d82d43b | 1287 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1288 | { |
12f02c2a AC |
1289 | CORE_ADDR offset; |
1290 | int regx; | |
1291 | int regy; | |
1292 | switch (insn_format) | |
c906108c | 1293 | { |
c5aa993b | 1294 | case itype: |
c906108c | 1295 | { |
12f02c2a AC |
1296 | CORE_ADDR value; |
1297 | if (extension) | |
c5aa993b JM |
1298 | { |
1299 | value = extended_offset (extension); | |
1300 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1301 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1302 | } |
1303 | else | |
c5aa993b | 1304 | { |
12f02c2a | 1305 | value = inst & 0x7ff; |
c5aa993b | 1306 | /* FIXME : Consider sign extension */ |
c906108c | 1307 | } |
12f02c2a AC |
1308 | offset = value; |
1309 | regx = -1; | |
1310 | regy = -1; | |
c906108c | 1311 | } |
c5aa993b JM |
1312 | break; |
1313 | case ritype: | |
1314 | case i8type: | |
1315 | { /* A register identifier and an offset */ | |
c906108c SS |
1316 | /* Most of the fields are the same as I type but the |
1317 | immediate value is of a different length */ | |
12f02c2a AC |
1318 | CORE_ADDR value; |
1319 | if (extension) | |
c906108c | 1320 | { |
c5aa993b JM |
1321 | value = extended_offset (extension); |
1322 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1323 | value |= inst & 0xff; /* eleven bits from instruction */ |
1324 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1325 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1326 | { | |
1327 | value &= ~0x3fff; /* remove the sign bit */ | |
1328 | value = -value; | |
c906108c SS |
1329 | } |
1330 | } | |
c5aa993b JM |
1331 | else |
1332 | { | |
12f02c2a AC |
1333 | value = inst & 0xff; /* 8 bits */ |
1334 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1335 | /* FIXME: Do sign extension , this format needs it */ |
1336 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1337 | { | |
1338 | value &= 0xef; /* remove the sign bit */ | |
1339 | value = -value; | |
1340 | } | |
c5aa993b | 1341 | } |
12f02c2a AC |
1342 | offset = value; |
1343 | regy = -1; | |
c5aa993b | 1344 | break; |
c906108c | 1345 | } |
c5aa993b | 1346 | case jalxtype: |
c906108c | 1347 | { |
c5aa993b | 1348 | unsigned long value; |
12f02c2a AC |
1349 | unsigned int nexthalf; |
1350 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b | 1351 | value = value << 16; |
e17a4113 | 1352 | nexthalf = mips_fetch_instruction (gdbarch, pc + 2); /* low bit still set */ |
c5aa993b | 1353 | value |= nexthalf; |
12f02c2a AC |
1354 | offset = value; |
1355 | regx = -1; | |
1356 | regy = -1; | |
c5aa993b | 1357 | break; |
c906108c SS |
1358 | } |
1359 | default: | |
e2e0b3e5 | 1360 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1361 | } |
12f02c2a AC |
1362 | upk->offset = offset; |
1363 | upk->regx = regx; | |
1364 | upk->regy = regy; | |
c906108c SS |
1365 | } |
1366 | ||
1367 | ||
c5aa993b JM |
1368 | static CORE_ADDR |
1369 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1370 | { |
5b652102 | 1371 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
1372 | } |
1373 | ||
12f02c2a | 1374 | static CORE_ADDR |
0b1b3e42 | 1375 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 1376 | unsigned int extension, unsigned int insn) |
c906108c | 1377 | { |
e17a4113 | 1378 | struct gdbarch *gdbarch = get_frame_arch (frame); |
12f02c2a AC |
1379 | int op = (insn >> 11); |
1380 | switch (op) | |
c906108c | 1381 | { |
6d82d43b | 1382 | case 2: /* Branch */ |
12f02c2a AC |
1383 | { |
1384 | CORE_ADDR offset; | |
1385 | struct upk_mips16 upk; | |
e17a4113 | 1386 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
12f02c2a AC |
1387 | offset = upk.offset; |
1388 | if (offset & 0x800) | |
1389 | { | |
1390 | offset &= 0xeff; | |
1391 | offset = -offset; | |
1392 | } | |
1393 | pc += (offset << 1) + 2; | |
1394 | break; | |
1395 | } | |
6d82d43b | 1396 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1397 | { |
1398 | struct upk_mips16 upk; | |
e17a4113 | 1399 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
12f02c2a AC |
1400 | pc = add_offset_16 (pc, upk.offset); |
1401 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1402 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1403 | else | |
1404 | pc |= 0x01; | |
1405 | break; | |
1406 | } | |
6d82d43b | 1407 | case 4: /* beqz */ |
12f02c2a AC |
1408 | { |
1409 | struct upk_mips16 upk; | |
1410 | int reg; | |
e17a4113 | 1411 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
0b1b3e42 | 1412 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1413 | if (reg == 0) |
1414 | pc += (upk.offset << 1) + 2; | |
1415 | else | |
1416 | pc += 2; | |
1417 | break; | |
1418 | } | |
6d82d43b | 1419 | case 5: /* bnez */ |
12f02c2a AC |
1420 | { |
1421 | struct upk_mips16 upk; | |
1422 | int reg; | |
e17a4113 | 1423 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
0b1b3e42 | 1424 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1425 | if (reg != 0) |
1426 | pc += (upk.offset << 1) + 2; | |
1427 | else | |
1428 | pc += 2; | |
1429 | break; | |
1430 | } | |
6d82d43b | 1431 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1432 | { |
1433 | struct upk_mips16 upk; | |
1434 | int reg; | |
e17a4113 | 1435 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
12f02c2a | 1436 | /* upk.regx contains the opcode */ |
0b1b3e42 | 1437 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
1438 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
1439 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1440 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1441 | pc += (upk.offset << 1) + 2; | |
1442 | else | |
1443 | pc += 2; | |
1444 | break; | |
1445 | } | |
6d82d43b | 1446 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1447 | { |
1448 | struct upk_mips16 upk; | |
1449 | /* upk.fmt = rrtype; */ | |
1450 | op = insn & 0x1f; | |
1451 | if (op == 0) | |
c5aa993b | 1452 | { |
12f02c2a AC |
1453 | int reg; |
1454 | upk.regx = (insn >> 8) & 0x07; | |
1455 | upk.regy = (insn >> 5) & 0x07; | |
1456 | switch (upk.regy) | |
c5aa993b | 1457 | { |
12f02c2a AC |
1458 | case 0: |
1459 | reg = upk.regx; | |
1460 | break; | |
1461 | case 1: | |
1462 | reg = 31; | |
6d82d43b | 1463 | break; /* Function return instruction */ |
12f02c2a AC |
1464 | case 2: |
1465 | reg = upk.regx; | |
1466 | break; | |
1467 | default: | |
1468 | reg = 31; | |
6d82d43b | 1469 | break; /* BOGUS Guess */ |
c906108c | 1470 | } |
0b1b3e42 | 1471 | pc = get_frame_register_signed (frame, reg); |
c906108c | 1472 | } |
12f02c2a | 1473 | else |
c5aa993b | 1474 | pc += 2; |
12f02c2a AC |
1475 | break; |
1476 | } | |
1477 | case 30: | |
1478 | /* This is an instruction extension. Fetch the real instruction | |
1479 | (which follows the extension) and decode things based on | |
1480 | that. */ | |
1481 | { | |
1482 | pc += 2; | |
e17a4113 UW |
1483 | pc = extended_mips16_next_pc (frame, pc, insn, |
1484 | fetch_mips_16 (gdbarch, pc)); | |
12f02c2a AC |
1485 | break; |
1486 | } | |
1487 | default: | |
1488 | { | |
1489 | pc += 2; | |
1490 | break; | |
1491 | } | |
c906108c | 1492 | } |
c5aa993b | 1493 | return pc; |
12f02c2a | 1494 | } |
c906108c | 1495 | |
5a89d8aa | 1496 | static CORE_ADDR |
0b1b3e42 | 1497 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a | 1498 | { |
e17a4113 UW |
1499 | struct gdbarch *gdbarch = get_frame_arch (frame); |
1500 | unsigned int insn = fetch_mips_16 (gdbarch, pc); | |
0b1b3e42 | 1501 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
1502 | } |
1503 | ||
1504 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1505 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1506 | It works by decoding the current instruction and predicting where a |
1507 | branch will go. This isnt hard because all the data is available. | |
ce1f96de | 1508 | The MIPS32 and MIPS16 variants are quite different. */ |
ad527d2e | 1509 | static CORE_ADDR |
0b1b3e42 | 1510 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1511 | { |
ce1f96de | 1512 | if (is_mips16_addr (pc)) |
0b1b3e42 | 1513 | return mips16_next_pc (frame, pc); |
c5aa993b | 1514 | else |
0b1b3e42 | 1515 | return mips32_next_pc (frame, pc); |
12f02c2a | 1516 | } |
c906108c | 1517 | |
edfae063 AC |
1518 | struct mips_frame_cache |
1519 | { | |
1520 | CORE_ADDR base; | |
1521 | struct trad_frame_saved_reg *saved_regs; | |
1522 | }; | |
1523 | ||
29639122 JB |
1524 | /* Set a register's saved stack address in temp_saved_regs. If an |
1525 | address has already been set for this register, do nothing; this | |
1526 | way we will only recognize the first save of a given register in a | |
1527 | function prologue. | |
eec63939 | 1528 | |
f57d151a UW |
1529 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
1530 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
1531 | Strictly speaking, only the second range is used as it is only second | |
1532 | range (the ABI instead of ISA registers) that comes into play when finding | |
1533 | saved registers in a frame. */ | |
eec63939 AC |
1534 | |
1535 | static void | |
74ed0bb4 MD |
1536 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
1537 | int regnum, CORE_ADDR offset) | |
eec63939 | 1538 | { |
29639122 JB |
1539 | if (this_cache != NULL |
1540 | && this_cache->saved_regs[regnum].addr == -1) | |
1541 | { | |
74ed0bb4 MD |
1542 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
1543 | = offset; | |
1544 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr | |
1545 | = offset; | |
29639122 | 1546 | } |
eec63939 AC |
1547 | } |
1548 | ||
eec63939 | 1549 | |
29639122 JB |
1550 | /* Fetch the immediate value from a MIPS16 instruction. |
1551 | If the previous instruction was an EXTEND, use it to extend | |
1552 | the upper bits of the immediate value. This is a helper function | |
1553 | for mips16_scan_prologue. */ | |
eec63939 | 1554 | |
29639122 JB |
1555 | static int |
1556 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1557 | unsigned short inst, /* current instruction */ | |
1558 | int nbits, /* number of bits in imm field */ | |
1559 | int scale, /* scale factor to be applied to imm */ | |
1560 | int is_signed) /* is the imm field signed? */ | |
eec63939 | 1561 | { |
29639122 | 1562 | int offset; |
eec63939 | 1563 | |
29639122 JB |
1564 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1565 | { | |
1566 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1567 | if (offset & 0x8000) /* check for negative extend */ | |
1568 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1569 | return offset | (inst & 0x1f); | |
1570 | } | |
eec63939 | 1571 | else |
29639122 JB |
1572 | { |
1573 | int max_imm = 1 << nbits; | |
1574 | int mask = max_imm - 1; | |
1575 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1576 | |
29639122 JB |
1577 | offset = inst & mask; |
1578 | if (is_signed && (offset & sign_bit)) | |
1579 | offset = 0 - (max_imm - offset); | |
1580 | return offset * scale; | |
1581 | } | |
1582 | } | |
eec63939 | 1583 | |
65596487 | 1584 | |
29639122 JB |
1585 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1586 | the associated FRAME_CACHE if not null. | |
1587 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1588 | |
29639122 | 1589 | static CORE_ADDR |
e17a4113 UW |
1590 | mips16_scan_prologue (struct gdbarch *gdbarch, |
1591 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 1592 | struct frame_info *this_frame, |
29639122 JB |
1593 | struct mips_frame_cache *this_cache) |
1594 | { | |
1595 | CORE_ADDR cur_pc; | |
1596 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1597 | CORE_ADDR sp; | |
1598 | long frame_offset = 0; /* Size of stack frame. */ | |
1599 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1600 | int frame_reg = MIPS_SP_REGNUM; | |
1601 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1602 | unsigned inst = 0; /* current instruction */ | |
1603 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 1604 | unsigned save_inst = 0; /* the save instruction */ |
29639122 | 1605 | int reg, offset; |
a343eb3c | 1606 | |
29639122 JB |
1607 | int extend_bytes = 0; |
1608 | int prev_extend_bytes; | |
1609 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 1610 | |
29639122 | 1611 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
1612 | THIS_FRAME. */ |
1613 | if (this_frame != NULL) | |
1614 | sp = get_frame_register_signed (this_frame, | |
1615 | gdbarch_num_regs (gdbarch) | |
1616 | + MIPS_SP_REGNUM); | |
29639122 JB |
1617 | else |
1618 | sp = 0; | |
eec63939 | 1619 | |
29639122 JB |
1620 | if (limit_pc > start_pc + 200) |
1621 | limit_pc = start_pc + 200; | |
eec63939 | 1622 | |
95ac2dcf | 1623 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1624 | { |
1625 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1626 | the immediate offset extension from it in mips16_get_imm. */ | |
1627 | prev_inst = inst; | |
eec63939 | 1628 | |
29639122 | 1629 | /* Fetch and decode the instruction. */ |
e17a4113 | 1630 | inst = (unsigned short) mips_fetch_instruction (gdbarch, cur_pc); |
eec63939 | 1631 | |
29639122 JB |
1632 | /* Normally we ignore extend instructions. However, if it is |
1633 | not followed by a valid prologue instruction, then this | |
1634 | instruction is not part of the prologue either. We must | |
1635 | remember in this case to adjust the end_prologue_addr back | |
1636 | over the extend. */ | |
1637 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1638 | { | |
95ac2dcf | 1639 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1640 | continue; |
1641 | } | |
eec63939 | 1642 | |
29639122 JB |
1643 | prev_extend_bytes = extend_bytes; |
1644 | extend_bytes = 0; | |
eec63939 | 1645 | |
29639122 JB |
1646 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1647 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1648 | { | |
1649 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
1650 | if (offset < 0) /* negative stack adjustment? */ | |
1651 | frame_offset -= offset; | |
1652 | else | |
1653 | /* Exit loop if a positive stack adjustment is found, which | |
1654 | usually means that the stack cleanup code in the function | |
1655 | epilogue is reached. */ | |
1656 | break; | |
1657 | } | |
1658 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1659 | { | |
1660 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1661 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
74ed0bb4 | 1662 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1663 | } |
1664 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1665 | { | |
1666 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1667 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1668 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1669 | } |
1670 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1671 | { | |
1672 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 1673 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1674 | } |
1675 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1676 | { | |
1677 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 1678 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1679 | } |
1680 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1681 | { | |
1682 | frame_addr = sp; | |
1683 | frame_reg = 17; | |
1684 | } | |
1685 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1686 | { | |
1687 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1688 | frame_addr = sp + offset; | |
1689 | frame_reg = 17; | |
1690 | frame_adjust = offset; | |
1691 | } | |
1692 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1693 | { | |
1694 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1695 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1696 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1697 | } |
1698 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1699 | { | |
1700 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1701 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1702 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1703 | } |
1704 | else if ((inst & 0xf81f) == 0xe809 | |
1705 | && (inst & 0x700) != 0x700) /* entry */ | |
1706 | entry_inst = inst; /* save for later processing */ | |
2207132d MR |
1707 | else if ((inst & 0xff80) == 0x6480) /* save */ |
1708 | { | |
1709 | save_inst = inst; /* save for later processing */ | |
1710 | if (prev_extend_bytes) /* extend */ | |
1711 | save_inst |= prev_inst << 16; | |
1712 | } | |
29639122 | 1713 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
95ac2dcf | 1714 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1715 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1716 | { | |
1717 | /* This instruction is part of the prologue, but we don't | |
1718 | need to do anything special to handle it. */ | |
1719 | } | |
1720 | else | |
1721 | { | |
1722 | /* This instruction is not an instruction typically found | |
1723 | in a prologue, so we must have reached the end of the | |
1724 | prologue. */ | |
1725 | if (end_prologue_addr == 0) | |
1726 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1727 | } | |
1728 | } | |
eec63939 | 1729 | |
29639122 JB |
1730 | /* The entry instruction is typically the first instruction in a function, |
1731 | and it stores registers at offsets relative to the value of the old SP | |
1732 | (before the prologue). But the value of the sp parameter to this | |
1733 | function is the new SP (after the prologue has been executed). So we | |
1734 | can't calculate those offsets until we've seen the entire prologue, | |
1735 | and can calculate what the old SP must have been. */ | |
1736 | if (entry_inst != 0) | |
1737 | { | |
1738 | int areg_count = (entry_inst >> 8) & 7; | |
1739 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1740 | |
29639122 JB |
1741 | /* The entry instruction always subtracts 32 from the SP. */ |
1742 | frame_offset += 32; | |
1743 | ||
1744 | /* Now we can calculate what the SP must have been at the | |
1745 | start of the function prologue. */ | |
1746 | sp += frame_offset; | |
1747 | ||
1748 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1749 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1750 | { | |
74ed0bb4 | 1751 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1752 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
1753 | } |
1754 | ||
1755 | /* Check if the ra register was pushed on the stack. */ | |
1756 | offset = -4; | |
1757 | if (entry_inst & 0x20) | |
1758 | { | |
74ed0bb4 | 1759 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 1760 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1761 | } |
1762 | ||
1763 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1764 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1765 | { | |
74ed0bb4 | 1766 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1767 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1768 | } |
1769 | } | |
1770 | ||
2207132d MR |
1771 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
1772 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
1773 | size of the frame is specified as an immediate field of instruction | |
1774 | and an extended variation exists which lets additional registers and | |
1775 | frame space to be specified. The instruction always treats registers | |
1776 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
1777 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
1778 | { | |
1779 | static int args_table[16] = { | |
1780 | 0, 0, 0, 0, 1, 1, 1, 1, | |
1781 | 2, 2, 2, 0, 3, 3, 4, -1, | |
1782 | }; | |
1783 | static int astatic_table[16] = { | |
1784 | 0, 1, 2, 3, 0, 1, 2, 3, | |
1785 | 0, 1, 2, 4, 0, 1, 0, -1, | |
1786 | }; | |
1787 | int aregs = (save_inst >> 16) & 0xf; | |
1788 | int xsregs = (save_inst >> 24) & 0x7; | |
1789 | int args = args_table[aregs]; | |
1790 | int astatic = astatic_table[aregs]; | |
1791 | long frame_size; | |
1792 | ||
1793 | if (args < 0) | |
1794 | { | |
1795 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
1796 | args = 0; | |
1797 | } | |
1798 | if (astatic < 0) | |
1799 | { | |
1800 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
1801 | astatic = 0; | |
1802 | } | |
1803 | ||
1804 | /* For standard SAVE the frame size of 0 means 128. */ | |
1805 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
1806 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
1807 | frame_size = 16; | |
1808 | frame_size *= 8; | |
1809 | frame_offset += frame_size; | |
1810 | ||
1811 | /* Now we can calculate what the SP must have been at the | |
1812 | start of the function prologue. */ | |
1813 | sp += frame_offset; | |
1814 | ||
1815 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
1816 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
1817 | { | |
74ed0bb4 | 1818 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1819 | offset += mips_abi_regsize (gdbarch); |
1820 | } | |
1821 | ||
1822 | offset = -4; | |
1823 | ||
1824 | /* Check if the RA register was pushed on the stack. */ | |
1825 | if (save_inst & 0x40) | |
1826 | { | |
74ed0bb4 | 1827 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
1828 | offset -= mips_abi_regsize (gdbarch); |
1829 | } | |
1830 | ||
1831 | /* Check if the S8 register was pushed on the stack. */ | |
1832 | if (xsregs > 6) | |
1833 | { | |
74ed0bb4 | 1834 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
1835 | offset -= mips_abi_regsize (gdbarch); |
1836 | xsregs--; | |
1837 | } | |
1838 | /* Check if S2-S7 were pushed on the stack. */ | |
1839 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
1840 | { | |
74ed0bb4 | 1841 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1842 | offset -= mips_abi_regsize (gdbarch); |
1843 | } | |
1844 | ||
1845 | /* Check if the S1 register was pushed on the stack. */ | |
1846 | if (save_inst & 0x10) | |
1847 | { | |
74ed0bb4 | 1848 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
1849 | offset -= mips_abi_regsize (gdbarch); |
1850 | } | |
1851 | /* Check if the S0 register was pushed on the stack. */ | |
1852 | if (save_inst & 0x20) | |
1853 | { | |
74ed0bb4 | 1854 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
1855 | offset -= mips_abi_regsize (gdbarch); |
1856 | } | |
1857 | ||
1858 | /* Check if A0-A3 were pushed on the stack. */ | |
1859 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
1860 | { | |
74ed0bb4 | 1861 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1862 | offset -= mips_abi_regsize (gdbarch); |
1863 | } | |
1864 | } | |
1865 | ||
29639122 JB |
1866 | if (this_cache != NULL) |
1867 | { | |
1868 | this_cache->base = | |
b8a22b94 DJ |
1869 | (get_frame_register_signed (this_frame, |
1870 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
1871 | + frame_offset - frame_adjust); |
1872 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
1873 | be able to get rid of the assignment below, evetually. But it's | |
1874 | still needed for now. */ | |
72a155b4 UW |
1875 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
1876 | + mips_regnum (gdbarch)->pc] | |
1877 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
29639122 JB |
1878 | } |
1879 | ||
1880 | /* If we didn't reach the end of the prologue when scanning the function | |
1881 | instructions, then set end_prologue_addr to the address of the | |
1882 | instruction immediately after the last one we scanned. */ | |
1883 | if (end_prologue_addr == 0) | |
1884 | end_prologue_addr = cur_pc; | |
1885 | ||
1886 | return end_prologue_addr; | |
eec63939 AC |
1887 | } |
1888 | ||
29639122 JB |
1889 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1890 | Procedures that use the 32-bit instruction set are handled by the | |
1891 | mips_insn32 unwinder. */ | |
1892 | ||
1893 | static struct mips_frame_cache * | |
b8a22b94 | 1894 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 1895 | { |
e17a4113 | 1896 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 1897 | struct mips_frame_cache *cache; |
eec63939 AC |
1898 | |
1899 | if ((*this_cache) != NULL) | |
1900 | return (*this_cache); | |
29639122 JB |
1901 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1902 | (*this_cache) = cache; | |
b8a22b94 | 1903 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 1904 | |
29639122 JB |
1905 | /* Analyze the function prologue. */ |
1906 | { | |
b8a22b94 | 1907 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 1908 | CORE_ADDR start_addr; |
eec63939 | 1909 | |
29639122 JB |
1910 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1911 | if (start_addr == 0) | |
e17a4113 | 1912 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
1913 | /* We can't analyze the prologue if we couldn't find the begining |
1914 | of the function. */ | |
1915 | if (start_addr == 0) | |
1916 | return cache; | |
eec63939 | 1917 | |
e17a4113 | 1918 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
1919 | } |
1920 | ||
3e8c568d | 1921 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 | 1922 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 1923 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
72a155b4 | 1924 | cache->base); |
eec63939 | 1925 | |
29639122 | 1926 | return (*this_cache); |
eec63939 AC |
1927 | } |
1928 | ||
1929 | static void | |
b8a22b94 | 1930 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 1931 | struct frame_id *this_id) |
eec63939 | 1932 | { |
b8a22b94 | 1933 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 1934 | this_cache); |
21327321 DJ |
1935 | /* This marks the outermost frame. */ |
1936 | if (info->base == 0) | |
1937 | return; | |
b8a22b94 | 1938 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
1939 | } |
1940 | ||
b8a22b94 DJ |
1941 | static struct value * |
1942 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
1943 | void **this_cache, int regnum) | |
eec63939 | 1944 | { |
b8a22b94 | 1945 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 1946 | this_cache); |
b8a22b94 DJ |
1947 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
1948 | } | |
1949 | ||
1950 | static int | |
1951 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
1952 | struct frame_info *this_frame, void **this_cache) | |
1953 | { | |
1954 | CORE_ADDR pc = get_frame_pc (this_frame); | |
1955 | if (mips_pc_is_mips16 (pc)) | |
1956 | return 1; | |
1957 | return 0; | |
eec63939 AC |
1958 | } |
1959 | ||
29639122 | 1960 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
1961 | { |
1962 | NORMAL_FRAME, | |
29639122 | 1963 | mips_insn16_frame_this_id, |
b8a22b94 DJ |
1964 | mips_insn16_frame_prev_register, |
1965 | NULL, | |
1966 | mips_insn16_frame_sniffer | |
eec63939 AC |
1967 | }; |
1968 | ||
eec63939 | 1969 | static CORE_ADDR |
b8a22b94 | 1970 | mips_insn16_frame_base_address (struct frame_info *this_frame, |
29639122 | 1971 | void **this_cache) |
eec63939 | 1972 | { |
b8a22b94 | 1973 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 JB |
1974 | this_cache); |
1975 | return info->base; | |
eec63939 AC |
1976 | } |
1977 | ||
29639122 | 1978 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 1979 | { |
29639122 JB |
1980 | &mips_insn16_frame_unwind, |
1981 | mips_insn16_frame_base_address, | |
1982 | mips_insn16_frame_base_address, | |
1983 | mips_insn16_frame_base_address | |
eec63939 AC |
1984 | }; |
1985 | ||
1986 | static const struct frame_base * | |
b8a22b94 | 1987 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 1988 | { |
b8a22b94 DJ |
1989 | CORE_ADDR pc = get_frame_pc (this_frame); |
1990 | if (mips_pc_is_mips16 (pc)) | |
29639122 | 1991 | return &mips_insn16_frame_base; |
eec63939 AC |
1992 | else |
1993 | return NULL; | |
edfae063 AC |
1994 | } |
1995 | ||
29639122 JB |
1996 | /* Mark all the registers as unset in the saved_regs array |
1997 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
1998 | ||
74ed0bb4 MD |
1999 | static void |
2000 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 2001 | { |
29639122 JB |
2002 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
2003 | return; | |
2004 | ||
2005 | { | |
74ed0bb4 | 2006 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 2007 | int i; |
64159455 | 2008 | |
29639122 JB |
2009 | for (i = 0; i < num_regs; i++) |
2010 | { | |
2011 | this_cache->saved_regs[i].addr = -1; | |
2012 | } | |
2013 | } | |
c906108c SS |
2014 | } |
2015 | ||
29639122 JB |
2016 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
2017 | the associated FRAME_CACHE if not null. | |
2018 | Return the address of the first instruction past the prologue. */ | |
c906108c | 2019 | |
875e1767 | 2020 | static CORE_ADDR |
e17a4113 UW |
2021 | mips32_scan_prologue (struct gdbarch *gdbarch, |
2022 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 2023 | struct frame_info *this_frame, |
29639122 | 2024 | struct mips_frame_cache *this_cache) |
c906108c | 2025 | { |
29639122 JB |
2026 | CORE_ADDR cur_pc; |
2027 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
2028 | CORE_ADDR sp; | |
2029 | long frame_offset; | |
2030 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 2031 | |
29639122 JB |
2032 | CORE_ADDR end_prologue_addr = 0; |
2033 | int seen_sp_adjust = 0; | |
2034 | int load_immediate_bytes = 0; | |
db5f024e | 2035 | int in_delay_slot = 0; |
7d1e6fb8 | 2036 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 2037 | |
29639122 | 2038 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
2039 | THIS_FRAME. */ |
2040 | if (this_frame != NULL) | |
2041 | sp = get_frame_register_signed (this_frame, | |
2042 | gdbarch_num_regs (gdbarch) | |
2043 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 2044 | else |
29639122 | 2045 | sp = 0; |
9022177c | 2046 | |
29639122 JB |
2047 | if (limit_pc > start_pc + 200) |
2048 | limit_pc = start_pc + 200; | |
9022177c | 2049 | |
29639122 | 2050 | restart: |
9022177c | 2051 | |
29639122 | 2052 | frame_offset = 0; |
95ac2dcf | 2053 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 2054 | { |
29639122 JB |
2055 | unsigned long inst, high_word, low_word; |
2056 | int reg; | |
9022177c | 2057 | |
29639122 | 2058 | /* Fetch the instruction. */ |
e17a4113 | 2059 | inst = (unsigned long) mips_fetch_instruction (gdbarch, cur_pc); |
9022177c | 2060 | |
29639122 JB |
2061 | /* Save some code by pre-extracting some useful fields. */ |
2062 | high_word = (inst >> 16) & 0xffff; | |
2063 | low_word = inst & 0xffff; | |
2064 | reg = high_word & 0x1f; | |
fe29b929 | 2065 | |
29639122 JB |
2066 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
2067 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
2068 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2069 | { | |
2070 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
2071 | frame_offset += 0x10000 - low_word; | |
2072 | else | |
2073 | /* Exit loop if a positive stack adjustment is found, which | |
2074 | usually means that the stack cleanup code in the function | |
2075 | epilogue is reached. */ | |
2076 | break; | |
2077 | seen_sp_adjust = 1; | |
2078 | } | |
7d1e6fb8 KB |
2079 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
2080 | && !regsize_is_64_bits) | |
29639122 | 2081 | { |
74ed0bb4 | 2082 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 | 2083 | } |
7d1e6fb8 KB |
2084 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
2085 | && regsize_is_64_bits) | |
29639122 JB |
2086 | { |
2087 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
74ed0bb4 | 2088 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 JB |
2089 | } |
2090 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
2091 | { | |
2092 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
2093 | if ((long) low_word != frame_offset) | |
2094 | frame_addr = sp + low_word; | |
b8a22b94 | 2095 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
2096 | { |
2097 | unsigned alloca_adjust; | |
a4b8ebc8 | 2098 | |
29639122 | 2099 | frame_reg = 30; |
b8a22b94 DJ |
2100 | frame_addr = get_frame_register_signed |
2101 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 2102 | |
29639122 JB |
2103 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
2104 | if (alloca_adjust > 0) | |
2105 | { | |
2106 | /* FP > SP + frame_size. This may be because of | |
2107 | an alloca or somethings similar. Fix sp to | |
2108 | "pre-alloca" value, and try again. */ | |
2109 | sp += alloca_adjust; | |
2110 | /* Need to reset the status of all registers. Otherwise, | |
2111 | we will hit a guard that prevents the new address | |
2112 | for each register to be recomputed during the second | |
2113 | pass. */ | |
74ed0bb4 | 2114 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2115 | goto restart; |
2116 | } | |
2117 | } | |
2118 | } | |
2119 | /* move $30,$sp. With different versions of gas this will be either | |
2120 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2121 | Accept any one of these. */ | |
2122 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
2123 | { | |
2124 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 2125 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
2126 | { |
2127 | unsigned alloca_adjust; | |
c906108c | 2128 | |
29639122 | 2129 | frame_reg = 30; |
b8a22b94 DJ |
2130 | frame_addr = get_frame_register_signed |
2131 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 2132 | |
29639122 JB |
2133 | alloca_adjust = (unsigned) (frame_addr - sp); |
2134 | if (alloca_adjust > 0) | |
2135 | { | |
2136 | /* FP > SP + frame_size. This may be because of | |
2137 | an alloca or somethings similar. Fix sp to | |
2138 | "pre-alloca" value, and try again. */ | |
2139 | sp = frame_addr; | |
2140 | /* Need to reset the status of all registers. Otherwise, | |
2141 | we will hit a guard that prevents the new address | |
2142 | for each register to be recomputed during the second | |
2143 | pass. */ | |
74ed0bb4 | 2144 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2145 | goto restart; |
2146 | } | |
2147 | } | |
2148 | } | |
7d1e6fb8 KB |
2149 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
2150 | && !regsize_is_64_bits) | |
29639122 | 2151 | { |
74ed0bb4 | 2152 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word); |
29639122 JB |
2153 | } |
2154 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
2155 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
2156 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
2157 | || high_word == 0x3c1c /* lui $gp,n */ | |
2158 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
2159 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
2160 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
2161 | ) | |
2162 | { | |
2163 | /* These instructions are part of the prologue, but we don't | |
2164 | need to do anything special to handle them. */ | |
2165 | } | |
2166 | /* The instructions below load $at or $t0 with an immediate | |
2167 | value in preparation for a stack adjustment via | |
2168 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
2169 | initialize a local variable, so we accept them only before | |
2170 | a stack adjustment instruction was seen. */ | |
2171 | else if (!seen_sp_adjust | |
2172 | && (high_word == 0x3c01 /* lui $at,n */ | |
2173 | || high_word == 0x3c08 /* lui $t0,n */ | |
2174 | || high_word == 0x3421 /* ori $at,$at,n */ | |
2175 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
2176 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
2177 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
2178 | )) | |
2179 | { | |
95ac2dcf | 2180 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
29639122 JB |
2181 | } |
2182 | else | |
2183 | { | |
2184 | /* This instruction is not an instruction typically found | |
2185 | in a prologue, so we must have reached the end of the | |
2186 | prologue. */ | |
2187 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
2188 | loop now? Why would we need to continue scanning the function | |
2189 | instructions? */ | |
2190 | if (end_prologue_addr == 0) | |
2191 | end_prologue_addr = cur_pc; | |
db5f024e DJ |
2192 | |
2193 | /* Check for branches and jumps. For now, only jump to | |
2194 | register are caught (i.e. returns). */ | |
2195 | if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8) | |
2196 | in_delay_slot = 1; | |
29639122 | 2197 | } |
db5f024e DJ |
2198 | |
2199 | /* If the previous instruction was a jump, we must have reached | |
2200 | the end of the prologue by now. Stop scanning so that we do | |
2201 | not go past the function return. */ | |
2202 | if (in_delay_slot) | |
2203 | break; | |
a4b8ebc8 | 2204 | } |
c906108c | 2205 | |
29639122 JB |
2206 | if (this_cache != NULL) |
2207 | { | |
2208 | this_cache->base = | |
b8a22b94 DJ |
2209 | (get_frame_register_signed (this_frame, |
2210 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
2211 | + frame_offset); |
2212 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2213 | this assignment below, eventually. But it's still needed | |
2214 | for now. */ | |
72a155b4 UW |
2215 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
2216 | + mips_regnum (gdbarch)->pc] | |
2217 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 2218 | + MIPS_RA_REGNUM]; |
29639122 | 2219 | } |
c906108c | 2220 | |
29639122 JB |
2221 | /* If we didn't reach the end of the prologue when scanning the function |
2222 | instructions, then set end_prologue_addr to the address of the | |
2223 | instruction immediately after the last one we scanned. */ | |
2224 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2225 | we may as well be careful and do our best if we have a null | |
2226 | end_prologue_addr. */ | |
2227 | if (end_prologue_addr == 0) | |
2228 | end_prologue_addr = cur_pc; | |
2229 | ||
2230 | /* In a frameless function, we might have incorrectly | |
2231 | skipped some load immediate instructions. Undo the skipping | |
2232 | if the load immediate was not followed by a stack adjustment. */ | |
2233 | if (load_immediate_bytes && !seen_sp_adjust) | |
2234 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2235 | |
29639122 | 2236 | return end_prologue_addr; |
c906108c SS |
2237 | } |
2238 | ||
29639122 JB |
2239 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2240 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2241 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2242 | unwinder. */ | |
c906108c | 2243 | |
29639122 | 2244 | static struct mips_frame_cache * |
b8a22b94 | 2245 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 2246 | { |
e17a4113 | 2247 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 2248 | struct mips_frame_cache *cache; |
c906108c | 2249 | |
29639122 JB |
2250 | if ((*this_cache) != NULL) |
2251 | return (*this_cache); | |
c5aa993b | 2252 | |
29639122 JB |
2253 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2254 | (*this_cache) = cache; | |
b8a22b94 | 2255 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 2256 | |
29639122 JB |
2257 | /* Analyze the function prologue. */ |
2258 | { | |
b8a22b94 | 2259 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 2260 | CORE_ADDR start_addr; |
c906108c | 2261 | |
29639122 JB |
2262 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2263 | if (start_addr == 0) | |
e17a4113 | 2264 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
2265 | /* We can't analyze the prologue if we couldn't find the begining |
2266 | of the function. */ | |
2267 | if (start_addr == 0) | |
2268 | return cache; | |
c5aa993b | 2269 | |
e17a4113 | 2270 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
2271 | } |
2272 | ||
3e8c568d | 2273 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 2274 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 2275 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
f57d151a | 2276 | cache->base); |
c5aa993b | 2277 | |
29639122 | 2278 | return (*this_cache); |
c906108c SS |
2279 | } |
2280 | ||
29639122 | 2281 | static void |
b8a22b94 | 2282 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 2283 | struct frame_id *this_id) |
c906108c | 2284 | { |
b8a22b94 | 2285 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2286 | this_cache); |
21327321 DJ |
2287 | /* This marks the outermost frame. */ |
2288 | if (info->base == 0) | |
2289 | return; | |
b8a22b94 | 2290 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 2291 | } |
c906108c | 2292 | |
b8a22b94 DJ |
2293 | static struct value * |
2294 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
2295 | void **this_cache, int regnum) | |
29639122 | 2296 | { |
b8a22b94 | 2297 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2298 | this_cache); |
b8a22b94 DJ |
2299 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
2300 | } | |
2301 | ||
2302 | static int | |
2303 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
2304 | struct frame_info *this_frame, void **this_cache) | |
2305 | { | |
2306 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2307 | if (! mips_pc_is_mips16 (pc)) | |
2308 | return 1; | |
2309 | return 0; | |
c906108c SS |
2310 | } |
2311 | ||
29639122 JB |
2312 | static const struct frame_unwind mips_insn32_frame_unwind = |
2313 | { | |
2314 | NORMAL_FRAME, | |
2315 | mips_insn32_frame_this_id, | |
b8a22b94 DJ |
2316 | mips_insn32_frame_prev_register, |
2317 | NULL, | |
2318 | mips_insn32_frame_sniffer | |
29639122 | 2319 | }; |
c906108c | 2320 | |
1c645fec | 2321 | static CORE_ADDR |
b8a22b94 | 2322 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 2323 | void **this_cache) |
c906108c | 2324 | { |
b8a22b94 | 2325 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
2326 | this_cache); |
2327 | return info->base; | |
2328 | } | |
c906108c | 2329 | |
29639122 JB |
2330 | static const struct frame_base mips_insn32_frame_base = |
2331 | { | |
2332 | &mips_insn32_frame_unwind, | |
2333 | mips_insn32_frame_base_address, | |
2334 | mips_insn32_frame_base_address, | |
2335 | mips_insn32_frame_base_address | |
2336 | }; | |
1c645fec | 2337 | |
29639122 | 2338 | static const struct frame_base * |
b8a22b94 | 2339 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2340 | { |
b8a22b94 DJ |
2341 | CORE_ADDR pc = get_frame_pc (this_frame); |
2342 | if (! mips_pc_is_mips16 (pc)) | |
29639122 | 2343 | return &mips_insn32_frame_base; |
a65bbe44 | 2344 | else |
29639122 JB |
2345 | return NULL; |
2346 | } | |
a65bbe44 | 2347 | |
29639122 | 2348 | static struct trad_frame_cache * |
b8a22b94 | 2349 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
2350 | { |
2351 | CORE_ADDR pc; | |
2352 | CORE_ADDR start_addr; | |
2353 | CORE_ADDR stack_addr; | |
2354 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
2355 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2356 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 2357 | |
29639122 JB |
2358 | if ((*this_cache) != NULL) |
2359 | return (*this_cache); | |
b8a22b94 | 2360 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 2361 | (*this_cache) = this_trad_cache; |
1c645fec | 2362 | |
29639122 | 2363 | /* The return address is in the link register. */ |
3e8c568d | 2364 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 2365 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 2366 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 2367 | |
29639122 JB |
2368 | /* Frame ID, since it's a frameless / stackless function, no stack |
2369 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 2370 | pc = get_frame_pc (this_frame); |
29639122 | 2371 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
2372 | stack_addr = get_frame_register_signed (this_frame, |
2373 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 2374 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 2375 | |
29639122 JB |
2376 | /* Assume that the frame's base is the same as the |
2377 | stack-pointer. */ | |
2378 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2379 | |
29639122 JB |
2380 | return this_trad_cache; |
2381 | } | |
c906108c | 2382 | |
29639122 | 2383 | static void |
b8a22b94 | 2384 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
2385 | struct frame_id *this_id) |
2386 | { | |
2387 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2388 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2389 | trad_frame_get_id (this_trad_cache, this_id); |
2390 | } | |
c906108c | 2391 | |
b8a22b94 DJ |
2392 | static struct value * |
2393 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
2394 | void **this_cache, int regnum) | |
29639122 JB |
2395 | { |
2396 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
2397 | = mips_stub_frame_cache (this_frame, this_cache); |
2398 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 2399 | } |
c906108c | 2400 | |
b8a22b94 DJ |
2401 | static int |
2402 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
2403 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 2404 | { |
aa6c981f | 2405 | gdb_byte dummy[4]; |
979b38e0 | 2406 | struct obj_section *s; |
b8a22b94 | 2407 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
db5f024e | 2408 | struct minimal_symbol *msym; |
979b38e0 | 2409 | |
aa6c981f | 2410 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
2411 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
2412 | return 1; | |
aa6c981f | 2413 | |
29639122 | 2414 | if (in_plt_section (pc, NULL)) |
b8a22b94 | 2415 | return 1; |
979b38e0 DJ |
2416 | |
2417 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2418 | s = find_pc_section (pc); | |
2419 | ||
2420 | if (s != NULL | |
2421 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2422 | ".MIPS.stubs") == 0) | |
b8a22b94 | 2423 | return 1; |
979b38e0 | 2424 | |
db5f024e DJ |
2425 | /* Calling a PIC function from a non-PIC function passes through a |
2426 | stub. The stub for foo is named ".pic.foo". */ | |
2427 | msym = lookup_minimal_symbol_by_pc (pc); | |
2428 | if (msym != NULL | |
2429 | && SYMBOL_LINKAGE_NAME (msym) != NULL | |
2430 | && strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) == 0) | |
2431 | return 1; | |
2432 | ||
b8a22b94 | 2433 | return 0; |
29639122 | 2434 | } |
c906108c | 2435 | |
b8a22b94 DJ |
2436 | static const struct frame_unwind mips_stub_frame_unwind = |
2437 | { | |
2438 | NORMAL_FRAME, | |
2439 | mips_stub_frame_this_id, | |
2440 | mips_stub_frame_prev_register, | |
2441 | NULL, | |
2442 | mips_stub_frame_sniffer | |
2443 | }; | |
2444 | ||
29639122 | 2445 | static CORE_ADDR |
b8a22b94 | 2446 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
2447 | void **this_cache) |
2448 | { | |
2449 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2450 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2451 | return trad_frame_get_this_base (this_trad_cache); |
2452 | } | |
0fce0821 | 2453 | |
29639122 JB |
2454 | static const struct frame_base mips_stub_frame_base = |
2455 | { | |
2456 | &mips_stub_frame_unwind, | |
2457 | mips_stub_frame_base_address, | |
2458 | mips_stub_frame_base_address, | |
2459 | mips_stub_frame_base_address | |
2460 | }; | |
2461 | ||
2462 | static const struct frame_base * | |
b8a22b94 | 2463 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2464 | { |
b8a22b94 | 2465 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
2466 | return &mips_stub_frame_base; |
2467 | else | |
2468 | return NULL; | |
2469 | } | |
2470 | ||
29639122 | 2471 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2472 | |
29639122 | 2473 | static CORE_ADDR |
24568a2c | 2474 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 2475 | { |
24568a2c | 2476 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
930bd0e0 KB |
2477 | |
2478 | if (is_mips16_addr (addr)) | |
2479 | addr = unmake_mips16_addr (addr); | |
2480 | ||
29639122 JB |
2481 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
2482 | /* This hack is a work-around for existing boards using PMON, the | |
2483 | simulator, and any other 64-bit targets that doesn't have true | |
2484 | 64-bit addressing. On these targets, the upper 32 bits of | |
2485 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2486 | likely to have been sign extended to all 1s by instruction | |
2487 | sequences that load 32-bit addresses. For example, a typical | |
2488 | piece of code that loads an address is this: | |
65596487 | 2489 | |
29639122 JB |
2490 | lui $r2, <upper 16 bits> |
2491 | ori $r2, <lower 16 bits> | |
65596487 | 2492 | |
29639122 JB |
2493 | But the lui sign-extends the value such that the upper 32 bits |
2494 | may be all 1s. The workaround is simply to mask off these | |
2495 | bits. In the future, gcc may be changed to support true 64-bit | |
2496 | addressing, and this masking will have to be disabled. */ | |
2497 | return addr &= 0xffffffffUL; | |
2498 | else | |
2499 | return addr; | |
65596487 JB |
2500 | } |
2501 | ||
3d5f6d12 DJ |
2502 | /* Instructions used during single-stepping of atomic sequences. */ |
2503 | #define LL_OPCODE 0x30 | |
2504 | #define LLD_OPCODE 0x34 | |
2505 | #define SC_OPCODE 0x38 | |
2506 | #define SCD_OPCODE 0x3c | |
2507 | ||
2508 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
2509 | instruction and ending with a SC/SCD instruction. If such a sequence | |
2510 | is found, attempt to step through it. A breakpoint is placed at the end of | |
2511 | the sequence. */ | |
2512 | ||
2513 | static int | |
6c95b8df PA |
2514 | deal_with_atomic_sequence (struct gdbarch *gdbarch, |
2515 | struct address_space *aspace, CORE_ADDR pc) | |
3d5f6d12 DJ |
2516 | { |
2517 | CORE_ADDR breaks[2] = {-1, -1}; | |
2518 | CORE_ADDR loc = pc; | |
2519 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
2520 | unsigned long insn; | |
2521 | int insn_count; | |
2522 | int index; | |
2523 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
2524 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
2525 | ||
2526 | if (pc & 0x01) | |
2527 | return 0; | |
2528 | ||
e17a4113 | 2529 | insn = mips_fetch_instruction (gdbarch, loc); |
3d5f6d12 DJ |
2530 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
2531 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
2532 | return 0; | |
2533 | ||
2534 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
2535 | instructions. */ | |
2536 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
2537 | { | |
2538 | int is_branch = 0; | |
2539 | loc += MIPS_INSN32_SIZE; | |
e17a4113 | 2540 | insn = mips_fetch_instruction (gdbarch, loc); |
3d5f6d12 DJ |
2541 | |
2542 | /* Assume that there is at most one branch in the atomic | |
2543 | sequence. If a branch is found, put a breakpoint in its | |
2544 | destination address. */ | |
2545 | switch (itype_op (insn)) | |
2546 | { | |
2547 | case 0: /* SPECIAL */ | |
2548 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
2549 | return 0; /* fallback to the standard single-step code. */ | |
2550 | break; | |
2551 | case 1: /* REGIMM */ | |
2552 | is_branch = ((itype_rt (insn) & 0xc0) == 0); /* B{LT,GE}Z* */ | |
2553 | break; | |
2554 | case 2: /* J */ | |
2555 | case 3: /* JAL */ | |
2556 | return 0; /* fallback to the standard single-step code. */ | |
2557 | case 4: /* BEQ */ | |
2558 | case 5: /* BNE */ | |
2559 | case 6: /* BLEZ */ | |
2560 | case 7: /* BGTZ */ | |
2561 | case 20: /* BEQL */ | |
2562 | case 21: /* BNEL */ | |
2563 | case 22: /* BLEZL */ | |
2564 | case 23: /* BGTTL */ | |
2565 | is_branch = 1; | |
2566 | break; | |
2567 | case 17: /* COP1 */ | |
2568 | case 18: /* COP2 */ | |
2569 | case 19: /* COP3 */ | |
2570 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
2571 | break; | |
2572 | } | |
2573 | if (is_branch) | |
2574 | { | |
2575 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
2576 | if (last_breakpoint >= 1) | |
2577 | return 0; /* More than one branch found, fallback to the | |
2578 | standard single-step code. */ | |
2579 | breaks[1] = branch_bp; | |
2580 | last_breakpoint++; | |
2581 | } | |
2582 | ||
2583 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
2584 | break; | |
2585 | } | |
2586 | ||
2587 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
2588 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
2589 | return 0; | |
2590 | ||
2591 | loc += MIPS_INSN32_SIZE; | |
2592 | ||
2593 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
2594 | breaks[0] = loc; | |
2595 | ||
2596 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
2597 | placed (branch instruction's destination) in the atomic sequence */ | |
2598 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) | |
2599 | last_breakpoint = 0; | |
2600 | ||
2601 | /* Effectively inserts the breakpoints. */ | |
2602 | for (index = 0; index <= last_breakpoint; index++) | |
6c95b8df | 2603 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
3d5f6d12 DJ |
2604 | |
2605 | return 1; | |
2606 | } | |
2607 | ||
29639122 JB |
2608 | /* mips_software_single_step() is called just before we want to resume |
2609 | the inferior, if we want to single-step it but there is no hardware | |
2610 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 2611 | the target of the coming instruction and breakpoint it. */ |
29639122 | 2612 | |
e6590a1b | 2613 | int |
0b1b3e42 | 2614 | mips_software_single_step (struct frame_info *frame) |
c906108c | 2615 | { |
a6d9a66e | 2616 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6c95b8df | 2617 | struct address_space *aspace = get_frame_address_space (frame); |
8181d85f | 2618 | CORE_ADDR pc, next_pc; |
65596487 | 2619 | |
0b1b3e42 | 2620 | pc = get_frame_pc (frame); |
6c95b8df | 2621 | if (deal_with_atomic_sequence (gdbarch, aspace, pc)) |
3d5f6d12 DJ |
2622 | return 1; |
2623 | ||
0b1b3e42 | 2624 | next_pc = mips_next_pc (frame, pc); |
e6590a1b | 2625 | |
6c95b8df | 2626 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
e6590a1b | 2627 | return 1; |
29639122 | 2628 | } |
a65bbe44 | 2629 | |
29639122 JB |
2630 | /* Test whether the PC points to the return instruction at the |
2631 | end of a function. */ | |
65596487 | 2632 | |
29639122 | 2633 | static int |
e17a4113 | 2634 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 | 2635 | { |
0fe7e7c8 | 2636 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2637 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2638 | generates a "jr $ra"; other times it generates code to load | |
2639 | the return address from the stack to an accessible register (such | |
2640 | as $a3), then a "jr" using that register. This second case | |
2641 | is almost impossible to distinguish from an indirect jump | |
2642 | used for switch statements, so we don't even try. */ | |
e17a4113 | 2643 | return mips_fetch_instruction (gdbarch, pc) == 0xe820; /* jr $ra */ |
29639122 | 2644 | else |
e17a4113 | 2645 | return mips_fetch_instruction (gdbarch, pc) == 0x3e00008; /* jr $ra */ |
29639122 | 2646 | } |
c906108c | 2647 | |
c906108c | 2648 | |
29639122 JB |
2649 | /* This fencepost looks highly suspicious to me. Removing it also |
2650 | seems suspicious as it could affect remote debugging across serial | |
2651 | lines. */ | |
c906108c | 2652 | |
29639122 | 2653 | static CORE_ADDR |
74ed0bb4 | 2654 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
2655 | { |
2656 | CORE_ADDR start_pc; | |
2657 | CORE_ADDR fence; | |
2658 | int instlen; | |
2659 | int seen_adjsp = 0; | |
d6b48e9c | 2660 | struct inferior *inf; |
65596487 | 2661 | |
74ed0bb4 | 2662 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
2663 | start_pc = pc; |
2664 | fence = start_pc - heuristic_fence_post; | |
2665 | if (start_pc == 0) | |
2666 | return 0; | |
65596487 | 2667 | |
29639122 JB |
2668 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2669 | fence = VM_MIN_ADDRESS; | |
65596487 | 2670 | |
95ac2dcf | 2671 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2672 | |
d6b48e9c PA |
2673 | inf = current_inferior (); |
2674 | ||
29639122 JB |
2675 | /* search back for previous return */ |
2676 | for (start_pc -= instlen;; start_pc -= instlen) | |
2677 | if (start_pc < fence) | |
2678 | { | |
2679 | /* It's not clear to me why we reach this point when | |
2680 | stop_soon, but with this test, at least we | |
2681 | don't print out warnings for every child forked (eg, on | |
2682 | decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 2683 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
2684 | { |
2685 | static int blurb_printed = 0; | |
98b4dd94 | 2686 | |
5af949e3 UW |
2687 | warning (_("GDB can't find the start of the function at %s."), |
2688 | paddress (gdbarch, pc)); | |
29639122 JB |
2689 | |
2690 | if (!blurb_printed) | |
2691 | { | |
2692 | /* This actually happens frequently in embedded | |
2693 | development, when you first connect to a board | |
2694 | and your stack pointer and pc are nowhere in | |
2695 | particular. This message needs to give people | |
2696 | in that situation enough information to | |
2697 | determine that it's no big deal. */ | |
2698 | printf_filtered ("\n\ | |
5af949e3 | 2699 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
2700 | and thus can't determine the size of that function's stack frame.\n\ |
2701 | This means that GDB may be unable to access that stack frame, or\n\ | |
2702 | the frames below it.\n\ | |
2703 | This problem is most likely caused by an invalid program counter or\n\ | |
2704 | stack pointer.\n\ | |
2705 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 2706 | from %s for code which looks like the beginning of a\n\ |
29639122 | 2707 | function, you can increase the range of the search using the `set\n\ |
5af949e3 UW |
2708 | heuristic-fence-post' command.\n", |
2709 | paddress (gdbarch, pc), paddress (gdbarch, pc)); | |
29639122 JB |
2710 | blurb_printed = 1; |
2711 | } | |
2712 | } | |
2713 | ||
2714 | return 0; | |
2715 | } | |
0fe7e7c8 | 2716 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2717 | { |
2718 | unsigned short inst; | |
2719 | ||
2720 | /* On MIPS16, any one of the following is likely to be the | |
2721 | start of a function: | |
193774b3 MR |
2722 | extend save |
2723 | save | |
29639122 JB |
2724 | entry |
2725 | addiu sp,-n | |
2726 | daddiu sp,-n | |
2727 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
e17a4113 | 2728 | inst = mips_fetch_instruction (gdbarch, start_pc); |
193774b3 MR |
2729 | if ((inst & 0xff80) == 0x6480) /* save */ |
2730 | { | |
2731 | if (start_pc - instlen >= fence) | |
2732 | { | |
e17a4113 | 2733 | inst = mips_fetch_instruction (gdbarch, start_pc - instlen); |
193774b3 MR |
2734 | if ((inst & 0xf800) == 0xf000) /* extend */ |
2735 | start_pc -= instlen; | |
2736 | } | |
2737 | break; | |
2738 | } | |
2739 | else if (((inst & 0xf81f) == 0xe809 | |
2740 | && (inst & 0x700) != 0x700) /* entry */ | |
2741 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2742 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2743 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
2744 | break; |
2745 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2746 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2747 | seen_adjsp = 1; | |
2748 | else | |
2749 | seen_adjsp = 0; | |
2750 | } | |
e17a4113 | 2751 | else if (mips_about_to_return (gdbarch, start_pc)) |
29639122 | 2752 | { |
4c7d22cb | 2753 | /* Skip return and its delay slot. */ |
95ac2dcf | 2754 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2755 | break; |
2756 | } | |
2757 | ||
2758 | return start_pc; | |
c906108c SS |
2759 | } |
2760 | ||
6c0d6680 DJ |
2761 | struct mips_objfile_private |
2762 | { | |
2763 | bfd_size_type size; | |
2764 | char *contents; | |
2765 | }; | |
2766 | ||
f09ded24 AC |
2767 | /* According to the current ABI, should the type be passed in a |
2768 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 2769 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 AC |
2770 | FP registers and, consequently this returns false - forces FP |
2771 | arguments into integer registers. */ | |
2772 | ||
2773 | static int | |
74ed0bb4 MD |
2774 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
2775 | struct type *arg_type) | |
f09ded24 AC |
2776 | { |
2777 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 2778 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
2779 | && (typecode == TYPE_CODE_STRUCT |
2780 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 2781 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
2782 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
2783 | == TYPE_CODE_FLT)) | |
74ed0bb4 | 2784 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
2785 | } |
2786 | ||
49e790b0 DJ |
2787 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2788 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2789 | ||
2790 | static int | |
2791 | mips_type_needs_double_align (struct type *type) | |
2792 | { | |
2793 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2794 | |
49e790b0 DJ |
2795 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2796 | return 1; | |
2797 | else if (typecode == TYPE_CODE_STRUCT) | |
2798 | { | |
2799 | if (TYPE_NFIELDS (type) < 1) | |
2800 | return 0; | |
2801 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2802 | } | |
2803 | else if (typecode == TYPE_CODE_UNION) | |
2804 | { | |
361d1df0 | 2805 | int i, n; |
49e790b0 DJ |
2806 | |
2807 | n = TYPE_NFIELDS (type); | |
2808 | for (i = 0; i < n; i++) | |
2809 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2810 | return 1; | |
2811 | return 0; | |
2812 | } | |
2813 | return 0; | |
2814 | } | |
2815 | ||
dc604539 AC |
2816 | /* Adjust the address downward (direction of stack growth) so that it |
2817 | is correctly aligned for a new stack frame. */ | |
2818 | static CORE_ADDR | |
2819 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2820 | { | |
5b03f266 | 2821 | return align_down (addr, 16); |
dc604539 AC |
2822 | } |
2823 | ||
f7ab6ec6 | 2824 | static CORE_ADDR |
7d9b040b | 2825 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2826 | struct regcache *regcache, CORE_ADDR bp_addr, |
2827 | int nargs, struct value **args, CORE_ADDR sp, | |
2828 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2829 | { |
2830 | int argreg; | |
2831 | int float_argreg; | |
2832 | int argnum; | |
2833 | int len = 0; | |
2834 | int stack_offset = 0; | |
480d3dd2 | 2835 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 2836 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 2837 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 2838 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 2839 | |
25ab4790 AC |
2840 | /* For shared libraries, "t9" needs to point at the function |
2841 | address. */ | |
4c7d22cb | 2842 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2843 | |
2844 | /* Set the return address register to point to the entry point of | |
2845 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2846 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2847 | |
c906108c | 2848 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2849 | are properly aligned. The stack has to be at least 64-bit |
2850 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2851 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2852 | aligned, so we round to this widest known alignment. */ | |
2853 | ||
5b03f266 AC |
2854 | sp = align_down (sp, 16); |
2855 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2856 | |
46e0f506 | 2857 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2858 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2859 | passed in registers, but that's OK. */ |
c906108c | 2860 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 2861 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 2862 | sp -= align_up (len, 16); |
c906108c | 2863 | |
9ace0497 | 2864 | if (mips_debug) |
6d82d43b | 2865 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
2866 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
2867 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
9ace0497 | 2868 | |
c906108c | 2869 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2870 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 2871 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 2872 | |
46e0f506 | 2873 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2874 | if (struct_return) |
9ace0497 AC |
2875 | { |
2876 | if (mips_debug) | |
2877 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
2878 | "mips_eabi_push_dummy_call: struct_return reg=%d %s\n", |
2879 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 2880 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 2881 | } |
c906108c SS |
2882 | |
2883 | /* Now load as many as possible of the first arguments into | |
2884 | registers, and push the rest onto the stack. Loop thru args | |
2885 | from first to last. */ | |
2886 | for (argnum = 0; argnum < nargs; argnum++) | |
2887 | { | |
47a35522 MK |
2888 | const gdb_byte *val; |
2889 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 2890 | struct value *arg = args[argnum]; |
4991999e | 2891 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
2892 | int len = TYPE_LENGTH (arg_type); |
2893 | enum type_code typecode = TYPE_CODE (arg_type); | |
2894 | ||
9ace0497 AC |
2895 | if (mips_debug) |
2896 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2897 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2898 | argnum + 1, len, (int) typecode); |
9ace0497 | 2899 | |
930bd0e0 KB |
2900 | /* Function pointer arguments to mips16 code need to be made into |
2901 | mips16 pointers. */ | |
2902 | if (typecode == TYPE_CODE_PTR | |
2903 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
2904 | { | |
2905 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
2906 | len, byte_order); | |
2907 | if (mips_pc_is_mips16 (addr)) | |
2908 | { | |
2909 | store_signed_integer (valbuf, len, byte_order, | |
2910 | make_mips16_addr (addr)); | |
2911 | val = valbuf; | |
2912 | } | |
2913 | else | |
2914 | val = value_contents (arg); | |
2915 | } | |
c906108c | 2916 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2917 | reference. */ |
930bd0e0 | 2918 | else if (len > regsize |
9ace0497 | 2919 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2920 | { |
e17a4113 UW |
2921 | store_unsigned_integer (valbuf, regsize, byte_order, |
2922 | value_address (arg)); | |
c906108c | 2923 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 2924 | len = regsize; |
c906108c | 2925 | val = valbuf; |
9ace0497 AC |
2926 | if (mips_debug) |
2927 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2928 | } |
2929 | else | |
47a35522 | 2930 | val = value_contents (arg); |
c906108c SS |
2931 | |
2932 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2933 | even-numbered floating point register. Round the FP register |
2934 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2935 | left. Non MIPS_EABI targets also pass the FP in the integer |
2936 | registers so also round up normal registers. */ | |
74ed0bb4 | 2937 | if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
2938 | { |
2939 | if ((float_argreg & 1)) | |
2940 | float_argreg++; | |
2941 | } | |
c906108c SS |
2942 | |
2943 | /* Floating point arguments passed in registers have to be | |
2944 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2945 | are passed in register pairs; the even register gets |
2946 | the low word, and the odd register gets the high word. | |
2947 | On non-EABI processors, the first two floating point arguments are | |
2948 | also copied to general registers, because MIPS16 functions | |
2949 | don't use float registers for arguments. This duplication of | |
2950 | arguments in general registers can't hurt non-MIPS16 functions | |
2951 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2952 | /* MIPS_EABI squeezes a struct that contains a single floating |
2953 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2954 | stack. */ |
74ed0bb4 MD |
2955 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
2956 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 2957 | { |
6da397e0 KB |
2958 | /* EABI32 will pass doubles in consecutive registers, even on |
2959 | 64-bit cores. At one time, we used to check the size of | |
2960 | `float_argreg' to determine whether or not to pass doubles | |
2961 | in consecutive registers, but this is not sufficient for | |
2962 | making the ABI determination. */ | |
2963 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 2964 | { |
72a155b4 | 2965 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 2966 | == BFD_ENDIAN_BIG ? 4 : 0; |
a8852dc5 | 2967 | long regval; |
c906108c SS |
2968 | |
2969 | /* Write the low word of the double to the even register(s). */ | |
a8852dc5 KB |
2970 | regval = extract_signed_integer (val + low_offset, |
2971 | 4, byte_order); | |
9ace0497 | 2972 | if (mips_debug) |
acdb74a0 | 2973 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2974 | float_argreg, phex (regval, 4)); |
a8852dc5 | 2975 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
2976 | |
2977 | /* Write the high word of the double to the odd register(s). */ | |
a8852dc5 KB |
2978 | regval = extract_signed_integer (val + 4 - low_offset, |
2979 | 4, byte_order); | |
9ace0497 | 2980 | if (mips_debug) |
acdb74a0 | 2981 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2982 | float_argreg, phex (regval, 4)); |
a8852dc5 | 2983 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
2984 | } |
2985 | else | |
2986 | { | |
2987 | /* This is a floating point value that fits entirely | |
2988 | in a single register. */ | |
53a5351d | 2989 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 2990 | above to ensure that it is even register aligned. */ |
a8852dc5 | 2991 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
9ace0497 | 2992 | if (mips_debug) |
acdb74a0 | 2993 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2994 | float_argreg, phex (regval, len)); |
a8852dc5 | 2995 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
2996 | } |
2997 | } | |
2998 | else | |
2999 | { | |
3000 | /* Copy the argument to general registers or the stack in | |
3001 | register-sized pieces. Large arguments are split between | |
3002 | registers and stack. */ | |
1a69e1e4 DJ |
3003 | /* Note: structs whose size is not a multiple of regsize |
3004 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3005 | them in registers where gcc sometimes puts them on the |
3006 | stack. For maximum compatibility, we will put them in | |
3007 | both places. */ | |
1a69e1e4 | 3008 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 3009 | |
f09ded24 | 3010 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3011 | register are only written to memory. */ |
c906108c SS |
3012 | while (len > 0) |
3013 | { | |
ebafbe83 | 3014 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 3015 | int stack_used_p = 0; |
1a69e1e4 | 3016 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 3017 | |
acdb74a0 AC |
3018 | if (mips_debug) |
3019 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3020 | partial_len); | |
3021 | ||
566f0f7a | 3022 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 3023 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 3024 | || odd_sized_struct |
74ed0bb4 | 3025 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 3026 | { |
c906108c SS |
3027 | /* Should shorter than int integer values be |
3028 | promoted to int before being stored? */ | |
c906108c | 3029 | int longword_offset = 0; |
9ace0497 | 3030 | CORE_ADDR addr; |
566f0f7a | 3031 | stack_used_p = 1; |
72a155b4 | 3032 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 3033 | { |
1a69e1e4 | 3034 | if (regsize == 8 |
480d3dd2 AC |
3035 | && (typecode == TYPE_CODE_INT |
3036 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3037 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 3038 | longword_offset = regsize - len; |
480d3dd2 AC |
3039 | else if ((typecode == TYPE_CODE_STRUCT |
3040 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
3041 | && TYPE_LENGTH (arg_type) < regsize) |
3042 | longword_offset = regsize - len; | |
7a292a7a | 3043 | } |
c5aa993b | 3044 | |
9ace0497 AC |
3045 | if (mips_debug) |
3046 | { | |
5af949e3 UW |
3047 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3048 | paddress (gdbarch, stack_offset)); | |
3049 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3050 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 3051 | } |
361d1df0 | 3052 | |
9ace0497 AC |
3053 | addr = sp + stack_offset + longword_offset; |
3054 | ||
3055 | if (mips_debug) | |
3056 | { | |
3057 | int i; | |
5af949e3 UW |
3058 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3059 | paddress (gdbarch, addr)); | |
9ace0497 AC |
3060 | for (i = 0; i < partial_len; i++) |
3061 | { | |
6d82d43b | 3062 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 3063 | val[i] & 0xff); |
9ace0497 AC |
3064 | } |
3065 | } | |
3066 | write_memory (addr, val, partial_len); | |
c906108c SS |
3067 | } |
3068 | ||
f09ded24 AC |
3069 | /* Note!!! This is NOT an else clause. Odd sized |
3070 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 3071 | arguments will not. */ |
566f0f7a | 3072 | /* Write this portion of the argument to a general |
6d82d43b | 3073 | purpose register. */ |
74ed0bb4 MD |
3074 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
3075 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 3076 | { |
6d82d43b | 3077 | LONGEST regval = |
a8852dc5 | 3078 | extract_signed_integer (val, partial_len, byte_order); |
c906108c | 3079 | |
9ace0497 | 3080 | if (mips_debug) |
acdb74a0 | 3081 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 3082 | argreg, |
1a69e1e4 | 3083 | phex (regval, regsize)); |
a8852dc5 | 3084 | regcache_cooked_write_signed (regcache, argreg, regval); |
c906108c | 3085 | argreg++; |
c906108c | 3086 | } |
c5aa993b | 3087 | |
c906108c SS |
3088 | len -= partial_len; |
3089 | val += partial_len; | |
3090 | ||
566f0f7a | 3091 | /* Compute the the offset into the stack at which we |
6d82d43b | 3092 | will copy the next parameter. |
566f0f7a | 3093 | |
566f0f7a | 3094 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 3095 | only needs to be adjusted when it has been used. */ |
c906108c | 3096 | |
46e0f506 | 3097 | if (stack_used_p) |
1a69e1e4 | 3098 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
3099 | } |
3100 | } | |
9ace0497 AC |
3101 | if (mips_debug) |
3102 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
3103 | } |
3104 | ||
f10683bb | 3105 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3106 | |
0f71a2f6 JM |
3107 | /* Return adjusted stack pointer. */ |
3108 | return sp; | |
3109 | } | |
3110 | ||
a1f5b845 | 3111 | /* Determine the return value convention being used. */ |
6d82d43b | 3112 | |
9c8fdbfa | 3113 | static enum return_value_convention |
c055b101 | 3114 | mips_eabi_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 3115 | struct type *type, struct regcache *regcache, |
47a35522 | 3116 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3117 | { |
609ba780 JM |
3118 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3119 | int fp_return_type = 0; | |
3120 | int offset, regnum, xfer; | |
3121 | ||
9c8fdbfa AC |
3122 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
3123 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
3124 | |
3125 | /* Floating point type? */ | |
3126 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3127 | { | |
3128 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
3129 | fp_return_type = 1; | |
3130 | /* Structs with a single field of float type | |
3131 | are returned in a floating point register. */ | |
3132 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3133 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3134 | && TYPE_NFIELDS (type) == 1) | |
3135 | { | |
3136 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); | |
3137 | ||
3138 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) | |
3139 | fp_return_type = 1; | |
3140 | } | |
3141 | } | |
3142 | ||
3143 | if (fp_return_type) | |
3144 | { | |
3145 | /* A floating-point value belongs in the least significant part | |
3146 | of FP0/FP1. */ | |
3147 | if (mips_debug) | |
3148 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3149 | regnum = mips_regnum (gdbarch)->fp0; | |
3150 | } | |
3151 | else | |
3152 | { | |
3153 | /* An integer value goes in V0/V1. */ | |
3154 | if (mips_debug) | |
3155 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
3156 | regnum = MIPS_V0_REGNUM; | |
3157 | } | |
3158 | for (offset = 0; | |
3159 | offset < TYPE_LENGTH (type); | |
3160 | offset += mips_abi_regsize (gdbarch), regnum++) | |
3161 | { | |
3162 | xfer = mips_abi_regsize (gdbarch); | |
3163 | if (offset + xfer > TYPE_LENGTH (type)) | |
3164 | xfer = TYPE_LENGTH (type) - offset; | |
3165 | mips_xfer_register (gdbarch, regcache, | |
3166 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
3167 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
3168 | offset); | |
3169 | } | |
3170 | ||
9c8fdbfa | 3171 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
3172 | } |
3173 | ||
6d82d43b AC |
3174 | |
3175 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 3176 | |
8d26208a DJ |
3177 | /* Search for a naturally aligned double at OFFSET inside a struct |
3178 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
3179 | registers. */ | |
3180 | ||
3181 | static int | |
74ed0bb4 MD |
3182 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
3183 | int offset) | |
8d26208a DJ |
3184 | { |
3185 | int i; | |
3186 | ||
3187 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
3188 | return 0; | |
3189 | ||
74ed0bb4 | 3190 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
3191 | return 0; |
3192 | ||
3193 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
3194 | return 0; | |
3195 | ||
3196 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
3197 | { | |
3198 | int pos; | |
3199 | struct type *field_type; | |
3200 | ||
3201 | /* We're only looking at normal fields. */ | |
5bc60cfb | 3202 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
8d26208a DJ |
3203 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
3204 | continue; | |
3205 | ||
3206 | /* If we have gone past the offset, there is no double to pass. */ | |
3207 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
3208 | if (pos > offset) | |
3209 | return 0; | |
3210 | ||
3211 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
3212 | ||
3213 | /* If this field is entirely before the requested offset, go | |
3214 | on to the next one. */ | |
3215 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
3216 | continue; | |
3217 | ||
3218 | /* If this is our special aligned double, we can stop. */ | |
3219 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
3220 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
3221 | return 1; | |
3222 | ||
3223 | /* This field starts at or before the requested offset, and | |
3224 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 3225 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
3226 | } |
3227 | ||
3228 | return 0; | |
3229 | } | |
3230 | ||
f7ab6ec6 | 3231 | static CORE_ADDR |
7d9b040b | 3232 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3233 | struct regcache *regcache, CORE_ADDR bp_addr, |
3234 | int nargs, struct value **args, CORE_ADDR sp, | |
3235 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3236 | { |
3237 | int argreg; | |
3238 | int float_argreg; | |
3239 | int argnum; | |
3240 | int len = 0; | |
3241 | int stack_offset = 0; | |
480d3dd2 | 3242 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 3243 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 3244 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 3245 | |
25ab4790 AC |
3246 | /* For shared libraries, "t9" needs to point at the function |
3247 | address. */ | |
4c7d22cb | 3248 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3249 | |
3250 | /* Set the return address register to point to the entry point of | |
3251 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3252 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3253 | |
cb3d25d1 MS |
3254 | /* First ensure that the stack and structure return address (if any) |
3255 | are properly aligned. The stack has to be at least 64-bit | |
3256 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3257 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3258 | aligned, so we round to this widest known alignment. */ | |
3259 | ||
5b03f266 AC |
3260 | sp = align_down (sp, 16); |
3261 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3262 | |
3263 | /* Now make space on the stack for the args. */ | |
3264 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 3265 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 3266 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3267 | |
3268 | if (mips_debug) | |
6d82d43b | 3269 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3270 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
3271 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3272 | |
3273 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3274 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3275 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 3276 | |
46e0f506 | 3277 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3278 | if (struct_return) |
3279 | { | |
3280 | if (mips_debug) | |
3281 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
3282 | "mips_n32n64_push_dummy_call: struct_return reg=%d %s\n", |
3283 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 3284 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
3285 | } |
3286 | ||
3287 | /* Now load as many as possible of the first arguments into | |
3288 | registers, and push the rest onto the stack. Loop thru args | |
3289 | from first to last. */ | |
3290 | for (argnum = 0; argnum < nargs; argnum++) | |
3291 | { | |
47a35522 | 3292 | const gdb_byte *val; |
cb3d25d1 | 3293 | struct value *arg = args[argnum]; |
4991999e | 3294 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
3295 | int len = TYPE_LENGTH (arg_type); |
3296 | enum type_code typecode = TYPE_CODE (arg_type); | |
3297 | ||
3298 | if (mips_debug) | |
3299 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3300 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3301 | argnum + 1, len, (int) typecode); |
3302 | ||
47a35522 | 3303 | val = value_contents (arg); |
cb3d25d1 | 3304 | |
5b68030f JM |
3305 | /* A 128-bit long double value requires an even-odd pair of |
3306 | floating-point registers. */ | |
3307 | if (len == 16 | |
3308 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
3309 | && (float_argreg & 1)) | |
3310 | { | |
3311 | float_argreg++; | |
3312 | argreg++; | |
3313 | } | |
3314 | ||
74ed0bb4 MD |
3315 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3316 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
3317 | { |
3318 | /* This is a floating point value that fits entirely | |
5b68030f JM |
3319 | in a single register or a pair of registers. */ |
3320 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
e17a4113 | 3321 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
cb3d25d1 MS |
3322 | if (mips_debug) |
3323 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 3324 | float_argreg, phex (regval, reglen)); |
8d26208a | 3325 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
3326 | |
3327 | if (mips_debug) | |
3328 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 3329 | argreg, phex (regval, reglen)); |
9c9acae0 | 3330 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
3331 | float_argreg++; |
3332 | argreg++; | |
5b68030f JM |
3333 | if (len == 16) |
3334 | { | |
e17a4113 UW |
3335 | regval = extract_unsigned_integer (val + reglen, |
3336 | reglen, byte_order); | |
5b68030f JM |
3337 | if (mips_debug) |
3338 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3339 | float_argreg, phex (regval, reglen)); | |
3340 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
3341 | ||
3342 | if (mips_debug) | |
3343 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3344 | argreg, phex (regval, reglen)); | |
3345 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
3346 | float_argreg++; | |
3347 | argreg++; | |
3348 | } | |
cb3d25d1 MS |
3349 | } |
3350 | else | |
3351 | { | |
3352 | /* Copy the argument to general registers or the stack in | |
3353 | register-sized pieces. Large arguments are split between | |
3354 | registers and stack. */ | |
ab2e1992 MR |
3355 | /* For N32/N64, structs, unions, or other composite types are |
3356 | treated as a sequence of doublewords, and are passed in integer | |
3357 | or floating point registers as though they were simple scalar | |
3358 | parameters to the extent that they fit, with any excess on the | |
3359 | stack packed according to the normal memory layout of the | |
3360 | object. | |
3361 | The caller does not reserve space for the register arguments; | |
3362 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 3363 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3364 | register are only written to memory. */ |
cb3d25d1 MS |
3365 | while (len > 0) |
3366 | { | |
ad018eee | 3367 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 3368 | int stack_used_p = 0; |
1a69e1e4 | 3369 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
3370 | |
3371 | if (mips_debug) | |
3372 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3373 | partial_len); | |
3374 | ||
74ed0bb4 MD |
3375 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
3376 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 3377 | |
cb3d25d1 | 3378 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 3379 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
3380 | { |
3381 | /* Should shorter than int integer values be | |
3382 | promoted to int before being stored? */ | |
3383 | int longword_offset = 0; | |
3384 | CORE_ADDR addr; | |
3385 | stack_used_p = 1; | |
72a155b4 | 3386 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 3387 | { |
1a69e1e4 | 3388 | if ((typecode == TYPE_CODE_INT |
5b68030f | 3389 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
3390 | && len <= 4) |
3391 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
3392 | } |
3393 | ||
3394 | if (mips_debug) | |
3395 | { | |
5af949e3 UW |
3396 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3397 | paddress (gdbarch, stack_offset)); | |
3398 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3399 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
3400 | } |
3401 | ||
3402 | addr = sp + stack_offset + longword_offset; | |
3403 | ||
3404 | if (mips_debug) | |
3405 | { | |
3406 | int i; | |
5af949e3 UW |
3407 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3408 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
3409 | for (i = 0; i < partial_len; i++) |
3410 | { | |
6d82d43b | 3411 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3412 | val[i] & 0xff); |
3413 | } | |
3414 | } | |
3415 | write_memory (addr, val, partial_len); | |
3416 | } | |
3417 | ||
3418 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 3419 | structs may go thru BOTH paths. */ |
cb3d25d1 | 3420 | /* Write this portion of the argument to a general |
6d82d43b | 3421 | purpose register. */ |
74ed0bb4 | 3422 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 3423 | { |
5863b5d5 MR |
3424 | LONGEST regval; |
3425 | ||
3426 | /* Sign extend pointers, 32-bit integers and signed | |
3427 | 16-bit and 8-bit integers; everything else is taken | |
3428 | as is. */ | |
3429 | ||
3430 | if ((partial_len == 4 | |
3431 | && (typecode == TYPE_CODE_PTR | |
3432 | || typecode == TYPE_CODE_INT)) | |
3433 | || (partial_len < 4 | |
3434 | && typecode == TYPE_CODE_INT | |
3435 | && !TYPE_UNSIGNED (arg_type))) | |
e17a4113 UW |
3436 | regval = extract_signed_integer (val, partial_len, |
3437 | byte_order); | |
5863b5d5 | 3438 | else |
e17a4113 UW |
3439 | regval = extract_unsigned_integer (val, partial_len, |
3440 | byte_order); | |
cb3d25d1 MS |
3441 | |
3442 | /* A non-floating-point argument being passed in a | |
3443 | general register. If a struct or union, and if | |
3444 | the remaining length is smaller than the register | |
3445 | size, we have to adjust the register value on | |
3446 | big endian targets. | |
3447 | ||
3448 | It does not seem to be necessary to do the | |
1a69e1e4 | 3449 | same for integral types. */ |
cb3d25d1 | 3450 | |
72a155b4 | 3451 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3452 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3453 | && (typecode == TYPE_CODE_STRUCT |
3454 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3455 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3456 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
3457 | |
3458 | if (mips_debug) | |
3459 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3460 | argreg, | |
1a69e1e4 | 3461 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3462 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 3463 | |
74ed0bb4 | 3464 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
3465 | TYPE_LENGTH (arg_type) - len)) |
3466 | { | |
3467 | if (mips_debug) | |
3468 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
3469 | float_argreg, | |
3470 | phex (regval, MIPS64_REGSIZE)); | |
3471 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
3472 | regval); | |
3473 | } | |
3474 | ||
3475 | float_argreg++; | |
cb3d25d1 MS |
3476 | argreg++; |
3477 | } | |
3478 | ||
3479 | len -= partial_len; | |
3480 | val += partial_len; | |
3481 | ||
3482 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3483 | will copy the next parameter. |
cb3d25d1 MS |
3484 | |
3485 | In N32 (N64?), the stack_offset only needs to be | |
3486 | adjusted when it has been used. */ | |
3487 | ||
3488 | if (stack_used_p) | |
1a69e1e4 | 3489 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
3490 | } |
3491 | } | |
3492 | if (mips_debug) | |
3493 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3494 | } | |
3495 | ||
f10683bb | 3496 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3497 | |
cb3d25d1 MS |
3498 | /* Return adjusted stack pointer. */ |
3499 | return sp; | |
3500 | } | |
3501 | ||
6d82d43b | 3502 | static enum return_value_convention |
c055b101 | 3503 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
6d82d43b | 3504 | struct type *type, struct regcache *regcache, |
47a35522 | 3505 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 3506 | { |
72a155b4 | 3507 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
3508 | |
3509 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
3510 | ||
3511 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
3512 | if needed), as appropriate for the type. Composite results (struct, | |
3513 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
3514 | following rules: | |
3515 | ||
3516 | * A struct with only one or two floating point fields is returned in $f0 | |
3517 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
3518 | case. | |
3519 | ||
f08877ba | 3520 | * Any other composite results of at most 128 bits are returned in |
b18bb924 MR |
3521 | $2 (first 64 bits) and $3 (remainder, if necessary). |
3522 | ||
3523 | * Larger composite results are handled by converting the function to a | |
3524 | procedure with an implicit first parameter, which is a pointer to an area | |
3525 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
3526 | that all composite results be handled by conversion to implicit first | |
3527 | parameters. The MIPS/SGI Fortran implementation has always made a | |
3528 | specific exception to return COMPLEX results in the floating point | |
3529 | registers.] */ | |
3530 | ||
f08877ba | 3531 | if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 3532 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
3533 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3534 | && TYPE_LENGTH (type) == 16 | |
3535 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3536 | { | |
3537 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
3538 | two registers are used in the same as memory order, so the | |
3539 | eight bytes with the lower memory address are in $f0. */ | |
3540 | if (mips_debug) | |
3541 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 3542 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3543 | gdbarch_num_regs (gdbarch) |
3544 | + mips_regnum (gdbarch)->fp0, | |
3545 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3546 | readbuf, writebuf, 0); |
ba32f989 | 3547 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3548 | gdbarch_num_regs (gdbarch) |
3549 | + mips_regnum (gdbarch)->fp0 + 2, | |
3550 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3551 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
3552 | writebuf ? writebuf + 8 : writebuf, 0); |
3553 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3554 | } | |
6d82d43b AC |
3555 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3556 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3557 | { | |
59aa1faa | 3558 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
3559 | if (mips_debug) |
3560 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3561 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3562 | gdbarch_num_regs (gdbarch) |
3563 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3564 | TYPE_LENGTH (type), |
72a155b4 | 3565 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3566 | readbuf, writebuf, 0); |
6d82d43b AC |
3567 | return RETURN_VALUE_REGISTER_CONVENTION; |
3568 | } | |
3569 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3570 | && TYPE_NFIELDS (type) <= 2 | |
3571 | && TYPE_NFIELDS (type) >= 1 | |
3572 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 3573 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
3574 | == TYPE_CODE_FLT)) |
3575 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 3576 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 3577 | == TYPE_CODE_FLT) |
b18bb924 | 3578 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
5b68030f | 3579 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
3580 | { |
3581 | /* A struct that contains one or two floats. Each value is part | |
3582 | in the least significant part of their floating point | |
5b68030f | 3583 | register (or GPR, for soft float). */ |
6d82d43b AC |
3584 | int regnum; |
3585 | int field; | |
5b68030f JM |
3586 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
3587 | ? mips_regnum (gdbarch)->fp0 | |
3588 | : MIPS_V0_REGNUM); | |
6d82d43b AC |
3589 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3590 | { | |
3591 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3592 | / TARGET_CHAR_BIT); | |
3593 | if (mips_debug) | |
3594 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3595 | offset); | |
5b68030f JM |
3596 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
3597 | { | |
3598 | /* A 16-byte long double field goes in two consecutive | |
3599 | registers. */ | |
3600 | mips_xfer_register (gdbarch, regcache, | |
3601 | gdbarch_num_regs (gdbarch) + regnum, | |
3602 | 8, | |
3603 | gdbarch_byte_order (gdbarch), | |
3604 | readbuf, writebuf, offset); | |
3605 | mips_xfer_register (gdbarch, regcache, | |
3606 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
3607 | 8, | |
3608 | gdbarch_byte_order (gdbarch), | |
3609 | readbuf, writebuf, offset + 8); | |
3610 | } | |
3611 | else | |
3612 | mips_xfer_register (gdbarch, regcache, | |
3613 | gdbarch_num_regs (gdbarch) + regnum, | |
3614 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3615 | gdbarch_byte_order (gdbarch), | |
3616 | readbuf, writebuf, offset); | |
6d82d43b AC |
3617 | } |
3618 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3619 | } | |
3620 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
f08877ba JB |
3621 | || TYPE_CODE (type) == TYPE_CODE_UNION |
3622 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
6d82d43b | 3623 | { |
f08877ba | 3624 | /* A composite type. Extract the left justified value, |
6d82d43b AC |
3625 | regardless of the byte order. I.e. DO NOT USE |
3626 | mips_xfer_lower. */ | |
3627 | int offset; | |
3628 | int regnum; | |
4c7d22cb | 3629 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3630 | offset < TYPE_LENGTH (type); |
72a155b4 | 3631 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3632 | { |
72a155b4 | 3633 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3634 | if (offset + xfer > TYPE_LENGTH (type)) |
3635 | xfer = TYPE_LENGTH (type) - offset; | |
3636 | if (mips_debug) | |
3637 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3638 | offset, xfer, regnum); | |
ba32f989 DJ |
3639 | mips_xfer_register (gdbarch, regcache, |
3640 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
3641 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
3642 | offset); | |
6d82d43b AC |
3643 | } |
3644 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3645 | } | |
3646 | else | |
3647 | { | |
3648 | /* A scalar extract each part but least-significant-byte | |
3649 | justified. */ | |
3650 | int offset; | |
3651 | int regnum; | |
4c7d22cb | 3652 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3653 | offset < TYPE_LENGTH (type); |
72a155b4 | 3654 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3655 | { |
72a155b4 | 3656 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3657 | if (offset + xfer > TYPE_LENGTH (type)) |
3658 | xfer = TYPE_LENGTH (type) - offset; | |
3659 | if (mips_debug) | |
3660 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3661 | offset, xfer, regnum); | |
ba32f989 DJ |
3662 | mips_xfer_register (gdbarch, regcache, |
3663 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 3664 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 3665 | readbuf, writebuf, offset); |
6d82d43b AC |
3666 | } |
3667 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3668 | } | |
3669 | } | |
3670 | ||
3671 | /* O32 ABI stuff. */ | |
3672 | ||
3673 | static CORE_ADDR | |
7d9b040b | 3674 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3675 | struct regcache *regcache, CORE_ADDR bp_addr, |
3676 | int nargs, struct value **args, CORE_ADDR sp, | |
3677 | int struct_return, CORE_ADDR struct_addr) | |
3678 | { | |
3679 | int argreg; | |
3680 | int float_argreg; | |
3681 | int argnum; | |
3682 | int len = 0; | |
3683 | int stack_offset = 0; | |
3684 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
e17a4113 | 3685 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 3686 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3687 | |
3688 | /* For shared libraries, "t9" needs to point at the function | |
3689 | address. */ | |
4c7d22cb | 3690 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3691 | |
3692 | /* Set the return address register to point to the entry point of | |
3693 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3694 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3695 | |
3696 | /* First ensure that the stack and structure return address (if any) | |
3697 | are properly aligned. The stack has to be at least 64-bit | |
3698 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3699 | aligned. For n32 and n64, stack frames need to be 128-bit |
3700 | aligned, so we round to this widest known alignment. */ | |
3701 | ||
5b03f266 AC |
3702 | sp = align_down (sp, 16); |
3703 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3704 | |
3705 | /* Now make space on the stack for the args. */ | |
3706 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3707 | { |
3708 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3709 | int arglen = TYPE_LENGTH (arg_type); | |
3710 | ||
3711 | /* Align to double-word if necessary. */ | |
2afd3f0a | 3712 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 3713 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 3714 | /* Allocate space on the stack. */ |
1a69e1e4 | 3715 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 3716 | } |
5b03f266 | 3717 | sp -= align_up (len, 16); |
ebafbe83 MS |
3718 | |
3719 | if (mips_debug) | |
6d82d43b | 3720 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3721 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
3722 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3723 | |
3724 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3725 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3726 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 3727 | |
bcb0cc15 | 3728 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3729 | if (struct_return) |
3730 | { | |
3731 | if (mips_debug) | |
3732 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
3733 | "mips_o32_push_dummy_call: struct_return reg=%d %s\n", |
3734 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 3735 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3736 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
3737 | } |
3738 | ||
3739 | /* Now load as many as possible of the first arguments into | |
3740 | registers, and push the rest onto the stack. Loop thru args | |
3741 | from first to last. */ | |
3742 | for (argnum = 0; argnum < nargs; argnum++) | |
3743 | { | |
47a35522 | 3744 | const gdb_byte *val; |
ebafbe83 | 3745 | struct value *arg = args[argnum]; |
4991999e | 3746 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3747 | int len = TYPE_LENGTH (arg_type); |
3748 | enum type_code typecode = TYPE_CODE (arg_type); | |
3749 | ||
3750 | if (mips_debug) | |
3751 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3752 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3753 | argnum + 1, len, (int) typecode); |
3754 | ||
47a35522 | 3755 | val = value_contents (arg); |
46cac009 AC |
3756 | |
3757 | /* 32-bit ABIs always start floating point arguments in an | |
3758 | even-numbered floating point register. Round the FP register | |
3759 | up before the check to see if there are any FP registers | |
3760 | left. O32/O64 targets also pass the FP in the integer | |
3761 | registers so also round up normal registers. */ | |
74ed0bb4 | 3762 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
3763 | { |
3764 | if ((float_argreg & 1)) | |
3765 | float_argreg++; | |
3766 | } | |
3767 | ||
3768 | /* Floating point arguments passed in registers have to be | |
3769 | treated specially. On 32-bit architectures, doubles | |
3770 | are passed in register pairs; the even register gets | |
3771 | the low word, and the odd register gets the high word. | |
3772 | On O32/O64, the first two floating point arguments are | |
3773 | also copied to general registers, because MIPS16 functions | |
3774 | don't use float registers for arguments. This duplication of | |
3775 | arguments in general registers can't hurt non-MIPS16 functions | |
3776 | because those registers are normally skipped. */ | |
3777 | ||
74ed0bb4 MD |
3778 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3779 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 3780 | { |
8b07f6d8 | 3781 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 3782 | { |
72a155b4 | 3783 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 3784 | == BFD_ENDIAN_BIG ? 4 : 0; |
46cac009 AC |
3785 | unsigned long regval; |
3786 | ||
3787 | /* Write the low word of the double to the even register(s). */ | |
e17a4113 UW |
3788 | regval = extract_unsigned_integer (val + low_offset, |
3789 | 4, byte_order); | |
46cac009 AC |
3790 | if (mips_debug) |
3791 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3792 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3793 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3794 | if (mips_debug) |
3795 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3796 | argreg, phex (regval, 4)); | |
9c9acae0 | 3797 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3798 | |
3799 | /* Write the high word of the double to the odd register(s). */ | |
e17a4113 UW |
3800 | regval = extract_unsigned_integer (val + 4 - low_offset, |
3801 | 4, byte_order); | |
46cac009 AC |
3802 | if (mips_debug) |
3803 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3804 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3805 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3806 | |
3807 | if (mips_debug) | |
3808 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3809 | argreg, phex (regval, 4)); | |
9c9acae0 | 3810 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3811 | } |
3812 | else | |
3813 | { | |
3814 | /* This is a floating point value that fits entirely | |
3815 | in a single register. */ | |
3816 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3817 | above to ensure that it is even register aligned. */ |
e17a4113 | 3818 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
46cac009 AC |
3819 | if (mips_debug) |
3820 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3821 | float_argreg, phex (regval, len)); | |
9c9acae0 | 3822 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
5b68030f JM |
3823 | /* Although two FP registers are reserved for each |
3824 | argument, only one corresponding integer register is | |
3825 | reserved. */ | |
46cac009 AC |
3826 | if (mips_debug) |
3827 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3828 | argreg, phex (regval, len)); | |
5b68030f | 3829 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3830 | } |
3831 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 3832 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
3833 | } |
3834 | else | |
3835 | { | |
3836 | /* Copy the argument to general registers or the stack in | |
3837 | register-sized pieces. Large arguments are split between | |
3838 | registers and stack. */ | |
1a69e1e4 DJ |
3839 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
3840 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3841 | them in registers where gcc sometimes puts them on the |
3842 | stack. For maximum compatibility, we will put them in | |
3843 | both places. */ | |
1a69e1e4 DJ |
3844 | int odd_sized_struct = (len > MIPS32_REGSIZE |
3845 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
3846 | /* Structures should be aligned to eight bytes (even arg registers) |
3847 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 3848 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
3849 | { |
3850 | if ((argreg & 1)) | |
968b5391 MR |
3851 | { |
3852 | argreg++; | |
1a69e1e4 | 3853 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 3854 | } |
46cac009 | 3855 | } |
46cac009 AC |
3856 | while (len > 0) |
3857 | { | |
3858 | /* Remember if the argument was written to the stack. */ | |
3859 | int stack_used_p = 0; | |
1a69e1e4 | 3860 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
3861 | |
3862 | if (mips_debug) | |
3863 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3864 | partial_len); | |
3865 | ||
3866 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 3867 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 3868 | || odd_sized_struct) |
46cac009 AC |
3869 | { |
3870 | /* Should shorter than int integer values be | |
3871 | promoted to int before being stored? */ | |
3872 | int longword_offset = 0; | |
3873 | CORE_ADDR addr; | |
3874 | stack_used_p = 1; | |
46cac009 AC |
3875 | |
3876 | if (mips_debug) | |
3877 | { | |
5af949e3 UW |
3878 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3879 | paddress (gdbarch, stack_offset)); | |
3880 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3881 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
3882 | } |
3883 | ||
3884 | addr = sp + stack_offset + longword_offset; | |
3885 | ||
3886 | if (mips_debug) | |
3887 | { | |
3888 | int i; | |
5af949e3 UW |
3889 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3890 | paddress (gdbarch, addr)); | |
46cac009 AC |
3891 | for (i = 0; i < partial_len; i++) |
3892 | { | |
6d82d43b | 3893 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3894 | val[i] & 0xff); |
3895 | } | |
3896 | } | |
3897 | write_memory (addr, val, partial_len); | |
3898 | } | |
3899 | ||
3900 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3901 | structs may go thru BOTH paths. */ |
46cac009 | 3902 | /* Write this portion of the argument to a general |
6d82d43b | 3903 | purpose register. */ |
74ed0bb4 | 3904 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 | 3905 | { |
e17a4113 UW |
3906 | LONGEST regval = extract_signed_integer (val, partial_len, |
3907 | byte_order); | |
4246e332 | 3908 | /* Value may need to be sign extended, because |
1b13c4f6 | 3909 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3910 | |
3911 | /* A non-floating-point argument being passed in a | |
3912 | general register. If a struct or union, and if | |
3913 | the remaining length is smaller than the register | |
3914 | size, we have to adjust the register value on | |
3915 | big endian targets. | |
3916 | ||
3917 | It does not seem to be necessary to do the | |
3918 | same for integral types. | |
3919 | ||
3920 | Also don't do this adjustment on O64 binaries. | |
3921 | ||
3922 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3923 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
3924 | mips_abi_regsize(), generates a left shift |
3925 | as part of storing the argument in a register | |
3926 | (the left shift isn't generated when | |
1b13c4f6 | 3927 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3928 | it is quite possible that this is GCC |
3929 | contradicting the LE/O32 ABI, GDB has not been | |
3930 | adjusted to accommodate this. Either someone | |
3931 | needs to demonstrate that the LE/O32 ABI | |
3932 | specifies such a left shift OR this new ABI gets | |
3933 | identified as such and GDB gets tweaked | |
3934 | accordingly. */ | |
3935 | ||
72a155b4 | 3936 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3937 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
3938 | && (typecode == TYPE_CODE_STRUCT |
3939 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3940 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 3941 | * TARGET_CHAR_BIT); |
46cac009 AC |
3942 | |
3943 | if (mips_debug) | |
3944 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3945 | argreg, | |
1a69e1e4 | 3946 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 3947 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
3948 | argreg++; |
3949 | ||
3950 | /* Prevent subsequent floating point arguments from | |
3951 | being passed in floating point registers. */ | |
74ed0bb4 | 3952 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
3953 | } |
3954 | ||
3955 | len -= partial_len; | |
3956 | val += partial_len; | |
3957 | ||
3958 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3959 | will copy the next parameter. |
46cac009 | 3960 | |
6d82d43b AC |
3961 | In older ABIs, the caller reserved space for |
3962 | registers that contained arguments. This was loosely | |
3963 | refered to as their "home". Consequently, space is | |
3964 | always allocated. */ | |
46cac009 | 3965 | |
1a69e1e4 | 3966 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
3967 | } |
3968 | } | |
3969 | if (mips_debug) | |
3970 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3971 | } | |
3972 | ||
f10683bb | 3973 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3974 | |
46cac009 AC |
3975 | /* Return adjusted stack pointer. */ |
3976 | return sp; | |
3977 | } | |
3978 | ||
6d82d43b | 3979 | static enum return_value_convention |
c055b101 CV |
3980 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *func_type, |
3981 | struct type *type, struct regcache *regcache, | |
47a35522 | 3982 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3983 | { |
72a155b4 | 3984 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6d82d43b AC |
3985 | |
3986 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3987 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3988 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3989 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3990 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3991 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3992 | { | |
3993 | /* A single-precision floating-point value. It fits in the | |
3994 | least significant part of FP0. */ | |
3995 | if (mips_debug) | |
3996 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3997 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3998 | gdbarch_num_regs (gdbarch) |
3999 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 4000 | TYPE_LENGTH (type), |
72a155b4 | 4001 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4002 | readbuf, writebuf, 0); |
6d82d43b AC |
4003 | return RETURN_VALUE_REGISTER_CONVENTION; |
4004 | } | |
4005 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4006 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4007 | { | |
4008 | /* A double-precision floating-point value. The most | |
4009 | significant part goes in FP1, and the least significant in | |
4010 | FP0. */ | |
4011 | if (mips_debug) | |
4012 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
72a155b4 | 4013 | switch (gdbarch_byte_order (gdbarch)) |
6d82d43b AC |
4014 | { |
4015 | case BFD_ENDIAN_LITTLE: | |
ba32f989 | 4016 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4017 | gdbarch_num_regs (gdbarch) |
4018 | + mips_regnum (gdbarch)->fp0 + | |
4019 | 0, 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4020 | readbuf, writebuf, 0); |
ba32f989 | 4021 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4022 | gdbarch_num_regs (gdbarch) |
4023 | + mips_regnum (gdbarch)->fp0 + 1, | |
4024 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4025 | readbuf, writebuf, 4); |
6d82d43b AC |
4026 | break; |
4027 | case BFD_ENDIAN_BIG: | |
ba32f989 | 4028 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4029 | gdbarch_num_regs (gdbarch) |
4030 | + mips_regnum (gdbarch)->fp0 + 1, | |
4031 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4032 | readbuf, writebuf, 0); |
ba32f989 | 4033 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4034 | gdbarch_num_regs (gdbarch) |
4035 | + mips_regnum (gdbarch)->fp0 + 0, | |
4036 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4037 | readbuf, writebuf, 4); |
6d82d43b AC |
4038 | break; |
4039 | default: | |
e2e0b3e5 | 4040 | internal_error (__FILE__, __LINE__, _("bad switch")); |
6d82d43b AC |
4041 | } |
4042 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4043 | } | |
4044 | #if 0 | |
4045 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4046 | && TYPE_NFIELDS (type) <= 2 | |
4047 | && TYPE_NFIELDS (type) >= 1 | |
4048 | && ((TYPE_NFIELDS (type) == 1 | |
4049 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4050 | == TYPE_CODE_FLT)) | |
4051 | || (TYPE_NFIELDS (type) == 2 | |
4052 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4053 | == TYPE_CODE_FLT) | |
4054 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4055 | == TYPE_CODE_FLT))) | |
4056 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4057 | { | |
4058 | /* A struct that contains one or two floats. Each value is part | |
4059 | in the least significant part of their floating point | |
4060 | register.. */ | |
870cd05e | 4061 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
4062 | int regnum; |
4063 | int field; | |
72a155b4 | 4064 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
4065 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
4066 | { | |
4067 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4068 | / TARGET_CHAR_BIT); | |
4069 | if (mips_debug) | |
4070 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
4071 | offset); | |
ba32f989 DJ |
4072 | mips_xfer_register (gdbarch, regcache, |
4073 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 4074 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 4075 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4076 | readbuf, writebuf, offset); |
6d82d43b AC |
4077 | } |
4078 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4079 | } | |
4080 | #endif | |
4081 | #if 0 | |
4082 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4083 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4084 | { | |
4085 | /* A structure or union. Extract the left justified value, | |
4086 | regardless of the byte order. I.e. DO NOT USE | |
4087 | mips_xfer_lower. */ | |
4088 | int offset; | |
4089 | int regnum; | |
4c7d22cb | 4090 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 4091 | offset < TYPE_LENGTH (type); |
72a155b4 | 4092 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 4093 | { |
72a155b4 | 4094 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
4095 | if (offset + xfer > TYPE_LENGTH (type)) |
4096 | xfer = TYPE_LENGTH (type) - offset; | |
4097 | if (mips_debug) | |
4098 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4099 | offset, xfer, regnum); | |
ba32f989 DJ |
4100 | mips_xfer_register (gdbarch, regcache, |
4101 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
4102 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
4103 | } | |
4104 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4105 | } | |
4106 | #endif | |
4107 | else | |
4108 | { | |
4109 | /* A scalar extract each part but least-significant-byte | |
4110 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 4111 | the ISA. */ |
6d82d43b AC |
4112 | int offset; |
4113 | int regnum; | |
4c7d22cb | 4114 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 4115 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 4116 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 4117 | { |
1a69e1e4 | 4118 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
4119 | if (offset + xfer > TYPE_LENGTH (type)) |
4120 | xfer = TYPE_LENGTH (type) - offset; | |
4121 | if (mips_debug) | |
4122 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4123 | offset, xfer, regnum); | |
ba32f989 DJ |
4124 | mips_xfer_register (gdbarch, regcache, |
4125 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 4126 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4127 | readbuf, writebuf, offset); |
6d82d43b AC |
4128 | } |
4129 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4130 | } | |
4131 | } | |
4132 | ||
4133 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
4134 | ABI. */ | |
46cac009 AC |
4135 | |
4136 | static CORE_ADDR | |
7d9b040b | 4137 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4138 | struct regcache *regcache, CORE_ADDR bp_addr, |
4139 | int nargs, | |
4140 | struct value **args, CORE_ADDR sp, | |
4141 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
4142 | { |
4143 | int argreg; | |
4144 | int float_argreg; | |
4145 | int argnum; | |
4146 | int len = 0; | |
4147 | int stack_offset = 0; | |
480d3dd2 | 4148 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 4149 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4150 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 4151 | |
25ab4790 AC |
4152 | /* For shared libraries, "t9" needs to point at the function |
4153 | address. */ | |
4c7d22cb | 4154 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4155 | |
4156 | /* Set the return address register to point to the entry point of | |
4157 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4158 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4159 | |
46cac009 AC |
4160 | /* First ensure that the stack and structure return address (if any) |
4161 | are properly aligned. The stack has to be at least 64-bit | |
4162 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4163 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4164 | aligned, so we round to this widest known alignment. */ | |
4165 | ||
5b03f266 AC |
4166 | sp = align_down (sp, 16); |
4167 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
4168 | |
4169 | /* Now make space on the stack for the args. */ | |
4170 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
4171 | { |
4172 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
4173 | int arglen = TYPE_LENGTH (arg_type); | |
4174 | ||
968b5391 | 4175 | /* Allocate space on the stack. */ |
1a69e1e4 | 4176 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 4177 | } |
5b03f266 | 4178 | sp -= align_up (len, 16); |
46cac009 AC |
4179 | |
4180 | if (mips_debug) | |
6d82d43b | 4181 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4182 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
4183 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
46cac009 AC |
4184 | |
4185 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4186 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4187 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
4188 | |
4189 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
4190 | if (struct_return) | |
4191 | { | |
4192 | if (mips_debug) | |
4193 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
4194 | "mips_o64_push_dummy_call: struct_return reg=%d %s\n", |
4195 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 4196 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 4197 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
4198 | } |
4199 | ||
4200 | /* Now load as many as possible of the first arguments into | |
4201 | registers, and push the rest onto the stack. Loop thru args | |
4202 | from first to last. */ | |
4203 | for (argnum = 0; argnum < nargs; argnum++) | |
4204 | { | |
47a35522 | 4205 | const gdb_byte *val; |
930bd0e0 | 4206 | gdb_byte valbuf[MAX_REGISTER_SIZE]; |
46cac009 | 4207 | struct value *arg = args[argnum]; |
4991999e | 4208 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
4209 | int len = TYPE_LENGTH (arg_type); |
4210 | enum type_code typecode = TYPE_CODE (arg_type); | |
4211 | ||
4212 | if (mips_debug) | |
4213 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4214 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
4215 | argnum + 1, len, (int) typecode); |
4216 | ||
47a35522 | 4217 | val = value_contents (arg); |
ebafbe83 | 4218 | |
930bd0e0 KB |
4219 | /* Function pointer arguments to mips16 code need to be made into |
4220 | mips16 pointers. */ | |
4221 | if (typecode == TYPE_CODE_PTR | |
4222 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
4223 | { | |
4224 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
4225 | len, byte_order); | |
4226 | if (mips_pc_is_mips16 (addr)) | |
4227 | { | |
4228 | store_signed_integer (valbuf, len, byte_order, | |
4229 | make_mips16_addr (addr)); | |
4230 | val = valbuf; | |
4231 | } | |
4232 | } | |
4233 | ||
ebafbe83 MS |
4234 | /* Floating point arguments passed in registers have to be |
4235 | treated specially. On 32-bit architectures, doubles | |
4236 | are passed in register pairs; the even register gets | |
4237 | the low word, and the odd register gets the high word. | |
4238 | On O32/O64, the first two floating point arguments are | |
4239 | also copied to general registers, because MIPS16 functions | |
4240 | don't use float registers for arguments. This duplication of | |
4241 | arguments in general registers can't hurt non-MIPS16 functions | |
4242 | because those registers are normally skipped. */ | |
4243 | ||
74ed0bb4 MD |
4244 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4245 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 4246 | { |
e17a4113 | 4247 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
2afd3f0a MR |
4248 | if (mips_debug) |
4249 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4250 | float_argreg, phex (regval, len)); | |
9c9acae0 | 4251 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
4252 | if (mips_debug) |
4253 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4254 | argreg, phex (regval, len)); | |
9c9acae0 | 4255 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 4256 | argreg++; |
ebafbe83 | 4257 | /* Reserve space for the FP register. */ |
1a69e1e4 | 4258 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
4259 | } |
4260 | else | |
4261 | { | |
4262 | /* Copy the argument to general registers or the stack in | |
4263 | register-sized pieces. Large arguments are split between | |
4264 | registers and stack. */ | |
1a69e1e4 | 4265 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
4266 | are treated specially: Irix cc passes them in registers |
4267 | where gcc sometimes puts them on the stack. For maximum | |
4268 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
4269 | int odd_sized_struct = (len > MIPS64_REGSIZE |
4270 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
4271 | while (len > 0) |
4272 | { | |
4273 | /* Remember if the argument was written to the stack. */ | |
4274 | int stack_used_p = 0; | |
1a69e1e4 | 4275 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
4276 | |
4277 | if (mips_debug) | |
4278 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4279 | partial_len); | |
4280 | ||
4281 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 4282 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 4283 | || odd_sized_struct) |
ebafbe83 MS |
4284 | { |
4285 | /* Should shorter than int integer values be | |
4286 | promoted to int before being stored? */ | |
4287 | int longword_offset = 0; | |
4288 | CORE_ADDR addr; | |
4289 | stack_used_p = 1; | |
72a155b4 | 4290 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 4291 | { |
1a69e1e4 DJ |
4292 | if ((typecode == TYPE_CODE_INT |
4293 | || typecode == TYPE_CODE_PTR | |
4294 | || typecode == TYPE_CODE_FLT) | |
4295 | && len <= 4) | |
4296 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
4297 | } |
4298 | ||
4299 | if (mips_debug) | |
4300 | { | |
5af949e3 UW |
4301 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4302 | paddress (gdbarch, stack_offset)); | |
4303 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4304 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
4305 | } |
4306 | ||
4307 | addr = sp + stack_offset + longword_offset; | |
4308 | ||
4309 | if (mips_debug) | |
4310 | { | |
4311 | int i; | |
5af949e3 UW |
4312 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4313 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
4314 | for (i = 0; i < partial_len; i++) |
4315 | { | |
6d82d43b | 4316 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4317 | val[i] & 0xff); |
4318 | } | |
4319 | } | |
4320 | write_memory (addr, val, partial_len); | |
4321 | } | |
4322 | ||
4323 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 4324 | structs may go thru BOTH paths. */ |
ebafbe83 | 4325 | /* Write this portion of the argument to a general |
6d82d43b | 4326 | purpose register. */ |
74ed0bb4 | 4327 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 | 4328 | { |
e17a4113 UW |
4329 | LONGEST regval = extract_signed_integer (val, partial_len, |
4330 | byte_order); | |
4246e332 | 4331 | /* Value may need to be sign extended, because |
1b13c4f6 | 4332 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
4333 | |
4334 | /* A non-floating-point argument being passed in a | |
4335 | general register. If a struct or union, and if | |
4336 | the remaining length is smaller than the register | |
4337 | size, we have to adjust the register value on | |
4338 | big endian targets. | |
4339 | ||
4340 | It does not seem to be necessary to do the | |
401835eb | 4341 | same for integral types. */ |
480d3dd2 | 4342 | |
72a155b4 | 4343 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4344 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
4345 | && (typecode == TYPE_CODE_STRUCT |
4346 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4347 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 4348 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
4349 | |
4350 | if (mips_debug) | |
4351 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4352 | argreg, | |
1a69e1e4 | 4353 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 4354 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
4355 | argreg++; |
4356 | ||
4357 | /* Prevent subsequent floating point arguments from | |
4358 | being passed in floating point registers. */ | |
74ed0bb4 | 4359 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
4360 | } |
4361 | ||
4362 | len -= partial_len; | |
4363 | val += partial_len; | |
4364 | ||
4365 | /* Compute the the offset into the stack at which we | |
6d82d43b | 4366 | will copy the next parameter. |
ebafbe83 | 4367 | |
6d82d43b AC |
4368 | In older ABIs, the caller reserved space for |
4369 | registers that contained arguments. This was loosely | |
4370 | refered to as their "home". Consequently, space is | |
4371 | always allocated. */ | |
ebafbe83 | 4372 | |
1a69e1e4 | 4373 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
4374 | } |
4375 | } | |
4376 | if (mips_debug) | |
4377 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4378 | } | |
4379 | ||
f10683bb | 4380 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4381 | |
ebafbe83 MS |
4382 | /* Return adjusted stack pointer. */ |
4383 | return sp; | |
4384 | } | |
4385 | ||
9c8fdbfa | 4386 | static enum return_value_convention |
c055b101 | 4387 | mips_o64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 4388 | struct type *type, struct regcache *regcache, |
47a35522 | 4389 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4390 | { |
72a155b4 | 4391 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a076fd2 FF |
4392 | |
4393 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4394 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4395 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4396 | return RETURN_VALUE_STRUCT_CONVENTION; | |
74ed0bb4 | 4397 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
7a076fd2 FF |
4398 | { |
4399 | /* A floating-point value. It fits in the least significant | |
4400 | part of FP0. */ | |
4401 | if (mips_debug) | |
4402 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 4403 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4404 | gdbarch_num_regs (gdbarch) |
4405 | + mips_regnum (gdbarch)->fp0, | |
7a076fd2 | 4406 | TYPE_LENGTH (type), |
72a155b4 | 4407 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4408 | readbuf, writebuf, 0); |
7a076fd2 FF |
4409 | return RETURN_VALUE_REGISTER_CONVENTION; |
4410 | } | |
4411 | else | |
4412 | { | |
4413 | /* A scalar extract each part but least-significant-byte | |
4414 | justified. */ | |
4415 | int offset; | |
4416 | int regnum; | |
4417 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
4418 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 4419 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 4420 | { |
1a69e1e4 | 4421 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
4422 | if (offset + xfer > TYPE_LENGTH (type)) |
4423 | xfer = TYPE_LENGTH (type) - offset; | |
4424 | if (mips_debug) | |
4425 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4426 | offset, xfer, regnum); | |
ba32f989 DJ |
4427 | mips_xfer_register (gdbarch, regcache, |
4428 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 4429 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4430 | readbuf, writebuf, offset); |
7a076fd2 FF |
4431 | } |
4432 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4433 | } | |
6d82d43b AC |
4434 | } |
4435 | ||
dd824b04 DJ |
4436 | /* Floating point register management. |
4437 | ||
4438 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4439 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4440 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4441 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4442 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4443 | double precision floats into two 32-bit chunks and store them in | |
4444 | consecutive fp regs. To display 64-bit floats stored in this | |
4445 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4446 | Throw in user-configurable endianness and you have a real mess. | |
4447 | ||
4448 | The way this works is: | |
4449 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4450 | double-precision value will be split across two logical registers. | |
4451 | The lower-numbered logical register will hold the low-order bits, | |
4452 | regardless of the processor's endianness. | |
4453 | - If we are on a 64-bit processor, and we are looking for a | |
4454 | single-precision value, it will be in the low ordered bits | |
4455 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4456 | save slot in memory. | |
4457 | - If we are in 64-bit mode, everything is straightforward. | |
4458 | ||
4459 | Note that this code only deals with "live" registers at the top of the | |
4460 | stack. We will attempt to deal with saved registers later, when | |
4461 | the raw/cooked register interface is in place. (We need a general | |
4462 | interface that can deal with dynamic saved register sizes -- fp | |
4463 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4464 | and below). */ | |
4465 | ||
4466 | /* Copy a 32-bit single-precision value from the current frame | |
4467 | into rare_buffer. */ | |
4468 | ||
4469 | static void | |
e11c53d2 | 4470 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 4471 | gdb_byte *rare_buffer) |
dd824b04 | 4472 | { |
72a155b4 UW |
4473 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4474 | int raw_size = register_size (gdbarch, regno); | |
47a35522 | 4475 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 4476 | |
e11c53d2 | 4477 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 4478 | error (_("can't read register %d (%s)"), |
72a155b4 | 4479 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4480 | if (raw_size == 8) |
4481 | { | |
4482 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4483 | 32 bits. */ |
dd824b04 DJ |
4484 | int offset; |
4485 | ||
72a155b4 | 4486 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
4487 | offset = 4; |
4488 | else | |
4489 | offset = 0; | |
4490 | ||
4491 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4492 | } | |
4493 | else | |
4494 | { | |
4495 | memcpy (rare_buffer, raw_buffer, 4); | |
4496 | } | |
4497 | } | |
4498 | ||
4499 | /* Copy a 64-bit double-precision value from the current frame into | |
4500 | rare_buffer. This may include getting half of it from the next | |
4501 | register. */ | |
4502 | ||
4503 | static void | |
e11c53d2 | 4504 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 4505 | gdb_byte *rare_buffer) |
dd824b04 | 4506 | { |
72a155b4 UW |
4507 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4508 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 4509 | |
9c9acae0 | 4510 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
4511 | { |
4512 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4513 | all 64 bits. */ |
e11c53d2 | 4514 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 4515 | error (_("can't read register %d (%s)"), |
72a155b4 | 4516 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4517 | } |
4518 | else | |
4519 | { | |
72a155b4 | 4520 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 4521 | |
72a155b4 | 4522 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 4523 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
4524 | _("mips_read_fp_register_double: bad access to " |
4525 | "odd-numbered FP register")); | |
dd824b04 DJ |
4526 | |
4527 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4528 | each register. */ |
72a155b4 | 4529 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 4530 | { |
e11c53d2 AC |
4531 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4532 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4533 | } |
361d1df0 | 4534 | else |
dd824b04 | 4535 | { |
e11c53d2 AC |
4536 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4537 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4538 | } |
4539 | } | |
4540 | } | |
4541 | ||
c906108c | 4542 | static void |
e11c53d2 AC |
4543 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4544 | int regnum) | |
c5aa993b | 4545 | { /* do values for FP (float) regs */ |
72a155b4 | 4546 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4547 | gdb_byte *raw_buffer; |
3903d437 AC |
4548 | double doub, flt1; /* doubles extracted from raw hex data */ |
4549 | int inv1, inv2; | |
c5aa993b | 4550 | |
72a155b4 | 4551 | raw_buffer = alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0)); |
c906108c | 4552 | |
72a155b4 | 4553 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 4554 | fprintf_filtered (file, "%*s", |
72a155b4 | 4555 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 4556 | ""); |
f0ef6b29 | 4557 | |
72a155b4 | 4558 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 4559 | { |
79a45b7d TT |
4560 | struct value_print_options opts; |
4561 | ||
f0ef6b29 KB |
4562 | /* 4-byte registers: Print hex and floating. Also print even |
4563 | numbered registers as doubles. */ | |
e11c53d2 | 4564 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 | 4565 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, raw_buffer, &inv1); |
c5aa993b | 4566 | |
79a45b7d | 4567 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4568 | print_scalar_formatted (raw_buffer, |
4569 | builtin_type (gdbarch)->builtin_uint32, | |
4570 | &opts, 'w', file); | |
dd824b04 | 4571 | |
e11c53d2 | 4572 | fprintf_filtered (file, " flt: "); |
1adad886 | 4573 | if (inv1) |
e11c53d2 | 4574 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4575 | else |
e11c53d2 | 4576 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4577 | |
72a155b4 | 4578 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 4579 | { |
e11c53d2 | 4580 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4581 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4582 | raw_buffer, &inv2); | |
1adad886 | 4583 | |
e11c53d2 | 4584 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4585 | if (inv2) |
e11c53d2 | 4586 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4587 | else |
e11c53d2 | 4588 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4589 | } |
c906108c SS |
4590 | } |
4591 | else | |
dd824b04 | 4592 | { |
79a45b7d TT |
4593 | struct value_print_options opts; |
4594 | ||
f0ef6b29 | 4595 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4596 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 UW |
4597 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
4598 | raw_buffer, &inv1); | |
c906108c | 4599 | |
e11c53d2 | 4600 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4601 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4602 | raw_buffer, &inv2); | |
f0ef6b29 | 4603 | |
79a45b7d | 4604 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4605 | print_scalar_formatted (raw_buffer, |
4606 | builtin_type (gdbarch)->builtin_uint64, | |
4607 | &opts, 'g', file); | |
f0ef6b29 | 4608 | |
e11c53d2 | 4609 | fprintf_filtered (file, " flt: "); |
1adad886 | 4610 | if (inv1) |
e11c53d2 | 4611 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4612 | else |
e11c53d2 | 4613 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4614 | |
e11c53d2 | 4615 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4616 | if (inv2) |
e11c53d2 | 4617 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4618 | else |
e11c53d2 | 4619 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4620 | } |
4621 | } | |
4622 | ||
4623 | static void | |
e11c53d2 | 4624 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 4625 | int regnum) |
f0ef6b29 | 4626 | { |
a4b8ebc8 | 4627 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4628 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4629 | int offset; |
79a45b7d | 4630 | struct value_print_options opts; |
1adad886 | 4631 | |
7b9ee6a8 | 4632 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4633 | { |
e11c53d2 | 4634 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4635 | return; |
4636 | } | |
4637 | ||
4638 | /* Get the data in raw format. */ | |
e11c53d2 | 4639 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4640 | { |
c9f4d572 | 4641 | fprintf_filtered (file, "%s: [Invalid]", |
72a155b4 | 4642 | gdbarch_register_name (gdbarch, regnum)); |
f0ef6b29 | 4643 | return; |
c906108c | 4644 | } |
f0ef6b29 | 4645 | |
72a155b4 | 4646 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
4647 | |
4648 | /* The problem with printing numeric register names (r26, etc.) is that | |
4649 | the user can't use them on input. Probably the best solution is to | |
4650 | fix it so that either the numeric or the funky (a2, etc.) names | |
4651 | are accepted on input. */ | |
4652 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4653 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4654 | else |
e11c53d2 | 4655 | fprintf_filtered (file, ": "); |
f0ef6b29 | 4656 | |
72a155b4 | 4657 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4658 | offset = |
72a155b4 | 4659 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
f0ef6b29 KB |
4660 | else |
4661 | offset = 0; | |
4662 | ||
79a45b7d | 4663 | get_formatted_print_options (&opts, 'x'); |
6d82d43b | 4664 | print_scalar_formatted (raw_buffer + offset, |
79a45b7d | 4665 | register_type (gdbarch, regnum), &opts, 0, |
6d82d43b | 4666 | file); |
c906108c SS |
4667 | } |
4668 | ||
f0ef6b29 KB |
4669 | /* Replacement for generic do_registers_info. |
4670 | Print regs in pretty columns. */ | |
4671 | ||
4672 | static int | |
e11c53d2 AC |
4673 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4674 | int regnum) | |
f0ef6b29 | 4675 | { |
e11c53d2 AC |
4676 | fprintf_filtered (file, " "); |
4677 | mips_print_fp_register (file, frame, regnum); | |
4678 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4679 | return regnum + 1; |
4680 | } | |
4681 | ||
4682 | ||
c906108c SS |
4683 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4684 | ||
4685 | static int | |
e11c53d2 | 4686 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4687 | int start_regnum) |
c906108c | 4688 | { |
a4b8ebc8 | 4689 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4690 | /* do values for GP (int) regs */ |
47a35522 | 4691 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 4692 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4693 | int col, byte; |
a4b8ebc8 | 4694 | int regnum; |
c906108c SS |
4695 | |
4696 | /* For GP registers, we print a separate row of names above the vals */ | |
a4b8ebc8 | 4697 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4698 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4699 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4700 | regnum++) |
c906108c | 4701 | { |
72a155b4 | 4702 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4703 | continue; /* unused register */ |
7b9ee6a8 | 4704 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4705 | TYPE_CODE_FLT) |
c5aa993b | 4706 | break; /* end the row: reached FP register */ |
0cc93a06 | 4707 | /* Large registers are handled separately. */ |
72a155b4 | 4708 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4709 | { |
4710 | if (col > 0) | |
4711 | break; /* End the row before this register. */ | |
4712 | ||
4713 | /* Print this register on a row by itself. */ | |
4714 | mips_print_register (file, frame, regnum); | |
4715 | fprintf_filtered (file, "\n"); | |
4716 | return regnum + 1; | |
4717 | } | |
d05f6826 DJ |
4718 | if (col == 0) |
4719 | fprintf_filtered (file, " "); | |
6d82d43b | 4720 | fprintf_filtered (file, |
72a155b4 UW |
4721 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
4722 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
4723 | col++; |
4724 | } | |
d05f6826 DJ |
4725 | |
4726 | if (col == 0) | |
4727 | return regnum; | |
4728 | ||
a4b8ebc8 | 4729 | /* print the R0 to R31 names */ |
72a155b4 | 4730 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 4731 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 4732 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
4733 | else |
4734 | fprintf_filtered (file, "\n "); | |
c906108c | 4735 | |
c906108c | 4736 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4737 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4738 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4739 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4740 | regnum++) |
c906108c | 4741 | { |
72a155b4 | 4742 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4743 | continue; /* unused register */ |
7b9ee6a8 | 4744 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4745 | TYPE_CODE_FLT) |
c5aa993b | 4746 | break; /* end row: reached FP register */ |
72a155b4 | 4747 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4748 | break; /* End row: large register. */ |
4749 | ||
c906108c | 4750 | /* OK: get the data in raw format. */ |
e11c53d2 | 4751 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 | 4752 | error (_("can't read register %d (%s)"), |
72a155b4 | 4753 | regnum, gdbarch_register_name (gdbarch, regnum)); |
c906108c | 4754 | /* pad small registers */ |
4246e332 | 4755 | for (byte = 0; |
72a155b4 UW |
4756 | byte < (mips_abi_regsize (gdbarch) |
4757 | - register_size (gdbarch, regnum)); byte++) | |
c906108c SS |
4758 | printf_filtered (" "); |
4759 | /* Now print the register value in hex, endian order. */ | |
72a155b4 | 4760 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4761 | for (byte = |
72a155b4 UW |
4762 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
4763 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 4764 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 4765 | else |
72a155b4 | 4766 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 4767 | byte >= 0; byte--) |
47a35522 | 4768 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 4769 | fprintf_filtered (file, " "); |
c906108c SS |
4770 | col++; |
4771 | } | |
c5aa993b | 4772 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4773 | fprintf_filtered (file, "\n"); |
c906108c SS |
4774 | |
4775 | return regnum; | |
4776 | } | |
4777 | ||
4778 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4779 | ||
bf1f5b4c | 4780 | static void |
e11c53d2 AC |
4781 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4782 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4783 | { |
c5aa993b | 4784 | if (regnum != -1) /* do one specified register */ |
c906108c | 4785 | { |
72a155b4 UW |
4786 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
4787 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 4788 | error (_("Not a valid register for the current processor type")); |
c906108c | 4789 | |
0cc93a06 | 4790 | mips_print_register (file, frame, regnum); |
e11c53d2 | 4791 | fprintf_filtered (file, "\n"); |
c906108c | 4792 | } |
c5aa993b JM |
4793 | else |
4794 | /* do all (or most) registers */ | |
c906108c | 4795 | { |
72a155b4 UW |
4796 | regnum = gdbarch_num_regs (gdbarch); |
4797 | while (regnum < gdbarch_num_regs (gdbarch) | |
4798 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 4799 | { |
7b9ee6a8 | 4800 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4801 | TYPE_CODE_FLT) |
e11c53d2 AC |
4802 | { |
4803 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4804 | regnum = print_fp_register_row (file, frame, regnum); | |
4805 | else | |
4806 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4807 | } | |
c906108c | 4808 | else |
e11c53d2 | 4809 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4810 | } |
4811 | } | |
4812 | } | |
4813 | ||
c906108c SS |
4814 | /* Is this a branch with a delay slot? */ |
4815 | ||
c906108c | 4816 | static int |
acdb74a0 | 4817 | is_delayed (unsigned long insn) |
c906108c SS |
4818 | { |
4819 | int i; | |
4820 | for (i = 0; i < NUMOPCODES; ++i) | |
4821 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4822 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4823 | break; | |
4824 | return (i < NUMOPCODES | |
4825 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4826 | | INSN_COND_BRANCH_DELAY | |
4827 | | INSN_COND_BRANCH_LIKELY))); | |
4828 | } | |
4829 | ||
63807e1d | 4830 | static int |
3352ef37 AC |
4831 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
4832 | struct frame_info *frame) | |
c906108c | 4833 | { |
e17a4113 | 4834 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3352ef37 | 4835 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 4836 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
4837 | |
4838 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4839 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4840 | return 0; |
4841 | ||
6c95b8df | 4842 | if (!breakpoint_here_p (get_frame_address_space (frame), pc + 4)) |
06648491 MK |
4843 | return 0; |
4844 | ||
3352ef37 AC |
4845 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
4846 | /* If error reading memory, guess that it is not a delayed | |
4847 | branch. */ | |
c906108c | 4848 | return 0; |
e17a4113 | 4849 | return is_delayed (extract_unsigned_integer (buf, sizeof buf, byte_order)); |
c906108c SS |
4850 | } |
4851 | ||
6d82d43b AC |
4852 | /* To skip prologues, I use this predicate. Returns either PC itself |
4853 | if the code at PC does not look like a function prologue; otherwise | |
4854 | returns an address that (if we're lucky) follows the prologue. If | |
4855 | LENIENT, then we must skip everything which is involved in setting | |
4856 | up the frame (it's OK to skip more, just so long as we don't skip | |
4857 | anything which might clobber the registers which are being saved. | |
4858 | We must skip more in the case where part of the prologue is in the | |
4859 | delay slot of a non-prologue instruction). */ | |
4860 | ||
4861 | static CORE_ADDR | |
6093d2eb | 4862 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 4863 | { |
8b622e6a AC |
4864 | CORE_ADDR limit_pc; |
4865 | CORE_ADDR func_addr; | |
4866 | ||
6d82d43b AC |
4867 | /* See if we can determine the end of the prologue via the symbol table. |
4868 | If so, then return either PC, or the PC after the prologue, whichever | |
4869 | is greater. */ | |
8b622e6a AC |
4870 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4871 | { | |
d80b854b UW |
4872 | CORE_ADDR post_prologue_pc |
4873 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a AC |
4874 | if (post_prologue_pc != 0) |
4875 | return max (pc, post_prologue_pc); | |
4876 | } | |
6d82d43b AC |
4877 | |
4878 | /* Can't determine prologue from the symbol table, need to examine | |
4879 | instructions. */ | |
4880 | ||
98b4dd94 JB |
4881 | /* Find an upper limit on the function prologue using the debug |
4882 | information. If the debug information could not be used to provide | |
4883 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 4884 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
4885 | if (limit_pc == 0) |
4886 | limit_pc = pc + 100; /* Magic. */ | |
4887 | ||
0fe7e7c8 | 4888 | if (mips_pc_is_mips16 (pc)) |
e17a4113 | 4889 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
6d82d43b | 4890 | else |
e17a4113 | 4891 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
88658117 AC |
4892 | } |
4893 | ||
97ab0fdd MR |
4894 | /* Check whether the PC is in a function epilogue (32-bit version). |
4895 | This is a helper function for mips_in_function_epilogue_p. */ | |
4896 | static int | |
e17a4113 | 4897 | mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
4898 | { |
4899 | CORE_ADDR func_addr = 0, func_end = 0; | |
4900 | ||
4901 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4902 | { | |
4903 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4904 | CORE_ADDR addr = func_end - 12; | |
4905 | ||
4906 | if (addr < func_addr + 4) | |
4907 | addr = func_addr + 4; | |
4908 | if (pc < addr) | |
4909 | return 0; | |
4910 | ||
4911 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
4912 | { | |
4913 | unsigned long high_word; | |
4914 | unsigned long inst; | |
4915 | ||
e17a4113 | 4916 | inst = mips_fetch_instruction (gdbarch, pc); |
97ab0fdd MR |
4917 | high_word = (inst >> 16) & 0xffff; |
4918 | ||
4919 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
4920 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
4921 | && inst != 0x03e00008 /* jr $ra */ | |
4922 | && inst != 0x00000000) /* nop */ | |
4923 | return 0; | |
4924 | } | |
4925 | ||
4926 | return 1; | |
4927 | } | |
4928 | ||
4929 | return 0; | |
4930 | } | |
4931 | ||
4932 | /* Check whether the PC is in a function epilogue (16-bit version). | |
4933 | This is a helper function for mips_in_function_epilogue_p. */ | |
4934 | static int | |
e17a4113 | 4935 | mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
4936 | { |
4937 | CORE_ADDR func_addr = 0, func_end = 0; | |
4938 | ||
4939 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4940 | { | |
4941 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4942 | CORE_ADDR addr = func_end - 12; | |
4943 | ||
4944 | if (addr < func_addr + 4) | |
4945 | addr = func_addr + 4; | |
4946 | if (pc < addr) | |
4947 | return 0; | |
4948 | ||
4949 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
4950 | { | |
4951 | unsigned short inst; | |
4952 | ||
e17a4113 | 4953 | inst = mips_fetch_instruction (gdbarch, pc); |
97ab0fdd MR |
4954 | |
4955 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
4956 | continue; | |
4957 | ||
4958 | if (inst != 0x6300 /* addiu $sp,offset */ | |
4959 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
4960 | && inst != 0xe820 /* jr $ra */ | |
4961 | && inst != 0xe8a0 /* jrc $ra */ | |
4962 | && inst != 0x6500) /* nop */ | |
4963 | return 0; | |
4964 | } | |
4965 | ||
4966 | return 1; | |
4967 | } | |
4968 | ||
4969 | return 0; | |
4970 | } | |
4971 | ||
4972 | /* The epilogue is defined here as the area at the end of a function, | |
4973 | after an instruction which destroys the function's stack frame. */ | |
4974 | static int | |
4975 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
4976 | { | |
4977 | if (mips_pc_is_mips16 (pc)) | |
e17a4113 | 4978 | return mips16_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd | 4979 | else |
e17a4113 | 4980 | return mips32_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd MR |
4981 | } |
4982 | ||
a5ea2558 AC |
4983 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4984 | used for all MIPS-specific commands. */ | |
4985 | ||
a5ea2558 | 4986 | static void |
acdb74a0 | 4987 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4988 | { |
4989 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4990 | } | |
4991 | ||
a5ea2558 | 4992 | static void |
acdb74a0 | 4993 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 4994 | { |
6d82d43b AC |
4995 | printf_unfiltered |
4996 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
4997 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
4998 | } | |
4999 | ||
c906108c SS |
5000 | /* Commands to show/set the MIPS FPU type. */ |
5001 | ||
c906108c | 5002 | static void |
acdb74a0 | 5003 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 5004 | { |
c906108c | 5005 | char *fpu; |
6ca0852e | 5006 | |
1cf3db46 | 5007 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
6ca0852e UW |
5008 | { |
5009 | printf_unfiltered | |
5010 | ("The MIPS floating-point coprocessor is unknown " | |
5011 | "because the current architecture is not MIPS.\n"); | |
5012 | return; | |
5013 | } | |
5014 | ||
1cf3db46 | 5015 | switch (MIPS_FPU_TYPE (target_gdbarch)) |
c906108c SS |
5016 | { |
5017 | case MIPS_FPU_SINGLE: | |
5018 | fpu = "single-precision"; | |
5019 | break; | |
5020 | case MIPS_FPU_DOUBLE: | |
5021 | fpu = "double-precision"; | |
5022 | break; | |
5023 | case MIPS_FPU_NONE: | |
5024 | fpu = "absent (none)"; | |
5025 | break; | |
93d56215 | 5026 | default: |
e2e0b3e5 | 5027 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
5028 | } |
5029 | if (mips_fpu_type_auto) | |
6d82d43b AC |
5030 | printf_unfiltered |
5031 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
5032 | fpu); | |
c906108c | 5033 | else |
6d82d43b AC |
5034 | printf_unfiltered |
5035 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
5036 | } |
5037 | ||
5038 | ||
c906108c | 5039 | static void |
acdb74a0 | 5040 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 5041 | { |
6d82d43b AC |
5042 | printf_unfiltered |
5043 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
5044 | show_mipsfpu_command (args, from_tty); |
5045 | } | |
5046 | ||
c906108c | 5047 | static void |
acdb74a0 | 5048 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 5049 | { |
8d5838b5 AC |
5050 | struct gdbarch_info info; |
5051 | gdbarch_info_init (&info); | |
c906108c SS |
5052 | mips_fpu_type = MIPS_FPU_SINGLE; |
5053 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5054 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5055 | instead of relying on globals. Doing that would let generic code | |
5056 | handle the search for this specific architecture. */ | |
5057 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5058 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5059 | } |
5060 | ||
c906108c | 5061 | static void |
acdb74a0 | 5062 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 5063 | { |
8d5838b5 AC |
5064 | struct gdbarch_info info; |
5065 | gdbarch_info_init (&info); | |
c906108c SS |
5066 | mips_fpu_type = MIPS_FPU_DOUBLE; |
5067 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5068 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5069 | instead of relying on globals. Doing that would let generic code | |
5070 | handle the search for this specific architecture. */ | |
5071 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5072 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5073 | } |
5074 | ||
c906108c | 5075 | static void |
acdb74a0 | 5076 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 5077 | { |
8d5838b5 AC |
5078 | struct gdbarch_info info; |
5079 | gdbarch_info_init (&info); | |
c906108c SS |
5080 | mips_fpu_type = MIPS_FPU_NONE; |
5081 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5082 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5083 | instead of relying on globals. Doing that would let generic code | |
5084 | handle the search for this specific architecture. */ | |
5085 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5086 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5087 | } |
5088 | ||
c906108c | 5089 | static void |
acdb74a0 | 5090 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5091 | { |
5092 | mips_fpu_type_auto = 1; | |
5093 | } | |
5094 | ||
c906108c | 5095 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
5096 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
5097 | the relevant processor still exists (it dates back to '94) and | |
5098 | secondly this is not the way to do this. The processor type should | |
5099 | be set by forcing an architecture change. */ | |
c906108c | 5100 | |
691c0433 AC |
5101 | void |
5102 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 5103 | { |
bb486190 UW |
5104 | struct regcache *regcache = get_current_regcache (); |
5105 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
5106 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
a9614958 | 5107 | ULONGEST prid; |
c906108c | 5108 | |
bb486190 | 5109 | regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid); |
c906108c | 5110 | if ((prid & ~0xf) == 0x700) |
691c0433 | 5111 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
5112 | } |
5113 | ||
5114 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5115 | callable as an sfunc. */ | |
5116 | ||
5117 | static void | |
acdb74a0 AC |
5118 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5119 | struct cmd_list_element *c) | |
c906108c SS |
5120 | { |
5121 | reinit_frame_cache (); | |
5122 | } | |
5123 | ||
a89aa300 AC |
5124 | static int |
5125 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 5126 | { |
d31431ed AC |
5127 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
5128 | disassembler needs to be able to locally determine the ISA, and | |
5129 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
5130 | work. */ | |
ec4045ea AC |
5131 | if (mips_pc_is_mips16 (memaddr)) |
5132 | info->mach = bfd_mach_mips16; | |
c906108c SS |
5133 | |
5134 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5135 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5136 | |
e5ab0dce | 5137 | /* Set the disassembler options. */ |
9dae60cc | 5138 | if (!info->disassembler_options) |
e5ab0dce AC |
5139 | /* This string is not recognized explicitly by the disassembler, |
5140 | but it tells the disassembler to not try to guess the ABI from | |
5141 | the bfd elf headers, such that, if the user overrides the ABI | |
5142 | of a program linked as NewABI, the disassembly will follow the | |
5143 | register naming conventions specified by the user. */ | |
5144 | info->disassembler_options = "gpr-names=32"; | |
5145 | ||
c906108c | 5146 | /* Call the appropriate disassembler based on the target endian-ness. */ |
40887e1a | 5147 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
5148 | return print_insn_big_mips (memaddr, info); |
5149 | else | |
5150 | return print_insn_little_mips (memaddr, info); | |
5151 | } | |
5152 | ||
9dae60cc UW |
5153 | static int |
5154 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) | |
5155 | { | |
5156 | /* Set up the disassembler info, so that we get the right | |
5157 | register names from libopcodes. */ | |
5158 | info->disassembler_options = "gpr-names=n32"; | |
5159 | info->flavour = bfd_target_elf_flavour; | |
5160 | ||
5161 | return gdb_print_insn_mips (memaddr, info); | |
5162 | } | |
5163 | ||
5164 | static int | |
5165 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) | |
5166 | { | |
5167 | /* Set up the disassembler info, so that we get the right | |
5168 | register names from libopcodes. */ | |
5169 | info->disassembler_options = "gpr-names=64"; | |
5170 | info->flavour = bfd_target_elf_flavour; | |
5171 | ||
5172 | return gdb_print_insn_mips (memaddr, info); | |
5173 | } | |
5174 | ||
3b3b875c UW |
5175 | /* This function implements gdbarch_breakpoint_from_pc. It uses the program |
5176 | counter value to determine whether a 16- or 32-bit breakpoint should be used. | |
5177 | It returns a pointer to a string of bytes that encode a breakpoint | |
5178 | instruction, stores the length of the string to *lenptr, and adjusts pc (if | |
5179 | necessary) to point to the actual memory location where the breakpoint | |
5180 | should be inserted. */ | |
c906108c | 5181 | |
47a35522 | 5182 | static const gdb_byte * |
67d57894 | 5183 | mips_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) |
c906108c | 5184 | { |
67d57894 | 5185 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 5186 | { |
0fe7e7c8 | 5187 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5188 | { |
47a35522 | 5189 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 5190 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5191 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5192 | return mips16_big_breakpoint; |
5193 | } | |
5194 | else | |
5195 | { | |
aaab4dba AC |
5196 | /* The IDT board uses an unusual breakpoint value, and |
5197 | sometimes gets confused when it sees the usual MIPS | |
5198 | breakpoint instruction. */ | |
47a35522 MK |
5199 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
5200 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
5201 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
f2ec0ecf JB |
5202 | /* Likewise, IRIX appears to expect a different breakpoint, |
5203 | although this is not apparent until you try to use pthreads. */ | |
5204 | static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
c906108c | 5205 | |
c5aa993b | 5206 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5207 | |
5208 | if (strcmp (target_shortname, "mips") == 0) | |
5209 | return idt_big_breakpoint; | |
5210 | else if (strcmp (target_shortname, "ddb") == 0 | |
5211 | || strcmp (target_shortname, "pmon") == 0 | |
5212 | || strcmp (target_shortname, "lsi") == 0) | |
5213 | return pmon_big_breakpoint; | |
f2ec0ecf JB |
5214 | else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX) |
5215 | return irix_big_breakpoint; | |
c906108c SS |
5216 | else |
5217 | return big_breakpoint; | |
5218 | } | |
5219 | } | |
5220 | else | |
5221 | { | |
0fe7e7c8 | 5222 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5223 | { |
47a35522 | 5224 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 5225 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5226 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5227 | return mips16_little_breakpoint; |
5228 | } | |
5229 | else | |
5230 | { | |
47a35522 MK |
5231 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5232 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
5233 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 5234 | |
c5aa993b | 5235 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5236 | |
5237 | if (strcmp (target_shortname, "mips") == 0) | |
5238 | return idt_little_breakpoint; | |
5239 | else if (strcmp (target_shortname, "ddb") == 0 | |
5240 | || strcmp (target_shortname, "pmon") == 0 | |
5241 | || strcmp (target_shortname, "lsi") == 0) | |
5242 | return pmon_little_breakpoint; | |
5243 | else | |
5244 | return little_breakpoint; | |
5245 | } | |
5246 | } | |
5247 | } | |
5248 | ||
5249 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5250 | PC, which is either the callee or the caller. There are several | |
5251 | cases which must be handled: | |
5252 | ||
5253 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5254 | target PC is in $31 ($ra). |
c906108c | 5255 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5256 | and the target PC is in $2. |
c906108c | 5257 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5258 | before the jal instruction, this is effectively a call stub |
5259 | and the the target PC is in $2. Otherwise this is effectively | |
5260 | a return stub and the target PC is in $18. | |
c906108c SS |
5261 | |
5262 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 5263 | gory details. */ |
c906108c | 5264 | |
757a7cc6 | 5265 | static CORE_ADDR |
db5f024e | 5266 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 5267 | { |
e17a4113 | 5268 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c SS |
5269 | char *name; |
5270 | CORE_ADDR start_addr; | |
5271 | ||
5272 | /* Find the starting address and name of the function containing the PC. */ | |
5273 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5274 | return 0; | |
5275 | ||
5276 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5277 | target PC is in $31 ($ra). */ | |
5278 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5279 | || strcmp (name, "__mips16_ret_df") == 0) | |
52f729a7 | 5280 | return get_frame_register_signed (frame, MIPS_RA_REGNUM); |
c906108c SS |
5281 | |
5282 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5283 | { | |
5284 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5285 | and the target PC is in $2. */ | |
5286 | if (name[19] >= '0' && name[19] <= '9') | |
52f729a7 | 5287 | return get_frame_register_signed (frame, 2); |
c906108c SS |
5288 | |
5289 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5290 | before the jal instruction, this is effectively a call stub |
5291 | and the the target PC is in $2. Otherwise this is effectively | |
5292 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5293 | else if (name[19] == 's' || name[19] == 'd') |
5294 | { | |
5295 | if (pc == start_addr) | |
5296 | { | |
5297 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5298 | stub. Such a stub for a function bar might have a name |
5299 | like __fn_stub_bar, and might look like this: | |
5300 | mfc1 $4,$f13 | |
5301 | mfc1 $5,$f12 | |
5302 | mfc1 $6,$f15 | |
5303 | mfc1 $7,$f14 | |
5304 | la $1,bar (becomes a lui/addiu pair) | |
5305 | jr $1 | |
5306 | So scan down to the lui/addi and extract the target | |
5307 | address from those two instructions. */ | |
c906108c | 5308 | |
52f729a7 | 5309 | CORE_ADDR target_pc = get_frame_register_signed (frame, 2); |
d37cca3d | 5310 | ULONGEST inst; |
c906108c SS |
5311 | int i; |
5312 | ||
5313 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
5314 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
5315 | 0) | |
c906108c SS |
5316 | return target_pc; |
5317 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5318 | && strcmp (name, "etext") != 0 | |
5319 | && strcmp (name, "_etext") != 0) | |
5320 | return target_pc; | |
5321 | ||
5322 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5323 | The limit on the search is arbitrarily set to 20 |
5324 | instructions. FIXME. */ | |
95ac2dcf | 5325 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
c906108c | 5326 | { |
e17a4113 | 5327 | inst = mips_fetch_instruction (gdbarch, target_pc); |
c5aa993b JM |
5328 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ |
5329 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5330 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5331 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5332 | } |
5333 | ||
5334 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5335 | return target_pc; | |
5336 | } | |
5337 | else | |
5338 | /* This is the 'return' part of a call stub. The return | |
5339 | address is in $r18. */ | |
52f729a7 | 5340 | return get_frame_register_signed (frame, 18); |
c906108c SS |
5341 | } |
5342 | } | |
c5aa993b | 5343 | return 0; /* not a stub */ |
c906108c SS |
5344 | } |
5345 | ||
db5f024e DJ |
5346 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
5347 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
5348 | so that $t9 has the correct value at function entry. */ | |
5349 | ||
5350 | static CORE_ADDR | |
5351 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5352 | { | |
e17a4113 UW |
5353 | struct gdbarch *gdbarch = get_frame_arch (frame); |
5354 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
db5f024e DJ |
5355 | struct minimal_symbol *msym; |
5356 | int i; | |
5357 | gdb_byte stub_code[16]; | |
5358 | int32_t stub_words[4]; | |
5359 | ||
5360 | /* The stub for foo is named ".pic.foo", and is either two | |
5361 | instructions inserted before foo or a three instruction sequence | |
5362 | which jumps to foo. */ | |
5363 | msym = lookup_minimal_symbol_by_pc (pc); | |
5364 | if (msym == NULL | |
5365 | || SYMBOL_VALUE_ADDRESS (msym) != pc | |
5366 | || SYMBOL_LINKAGE_NAME (msym) == NULL | |
5367 | || strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) != 0) | |
5368 | return 0; | |
5369 | ||
5370 | /* A two-instruction header. */ | |
5371 | if (MSYMBOL_SIZE (msym) == 8) | |
5372 | return pc + 8; | |
5373 | ||
5374 | /* A three-instruction (plus delay slot) trampoline. */ | |
5375 | if (MSYMBOL_SIZE (msym) == 16) | |
5376 | { | |
5377 | if (target_read_memory (pc, stub_code, 16) != 0) | |
5378 | return 0; | |
5379 | for (i = 0; i < 4; i++) | |
e17a4113 UW |
5380 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
5381 | 4, byte_order); | |
db5f024e DJ |
5382 | |
5383 | /* A stub contains these instructions: | |
5384 | lui t9, %hi(target) | |
5385 | j target | |
5386 | addiu t9, t9, %lo(target) | |
5387 | nop | |
5388 | ||
5389 | This works even for N64, since stubs are only generated with | |
5390 | -msym32. */ | |
5391 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
5392 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
5393 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
5394 | && stub_words[3] == 0x00000000) | |
5395 | return (((stub_words[0] & 0x0000ffff) << 16) | |
5396 | + (stub_words[2] & 0x0000ffff)); | |
5397 | } | |
5398 | ||
5399 | /* Not a recognized stub. */ | |
5400 | return 0; | |
5401 | } | |
5402 | ||
5403 | static CORE_ADDR | |
5404 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5405 | { | |
5406 | CORE_ADDR target_pc; | |
5407 | ||
5408 | target_pc = mips_skip_mips16_trampoline_code (frame, pc); | |
5409 | if (target_pc) | |
5410 | return target_pc; | |
5411 | ||
5412 | target_pc = find_solib_trampoline_target (frame, pc); | |
5413 | if (target_pc) | |
5414 | return target_pc; | |
5415 | ||
5416 | target_pc = mips_skip_pic_trampoline_code (frame, pc); | |
5417 | if (target_pc) | |
5418 | return target_pc; | |
5419 | ||
5420 | return 0; | |
5421 | } | |
5422 | ||
a4b8ebc8 | 5423 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 5424 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5425 | |
5426 | static int | |
d3f73121 | 5427 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5428 | { |
a4b8ebc8 | 5429 | int regnum; |
2f38ef89 | 5430 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5431 | regnum = num; |
2f38ef89 | 5432 | else if (num >= 38 && num < 70) |
d3f73121 | 5433 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 5434 | else if (num == 70) |
d3f73121 | 5435 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5436 | else if (num == 71) |
d3f73121 | 5437 | regnum = mips_regnum (gdbarch)->lo; |
2f38ef89 | 5438 | else |
a4b8ebc8 AC |
5439 | /* This will hopefully (eventually) provoke a warning. Should |
5440 | we be calling complaint() here? */ | |
d3f73121 MD |
5441 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5442 | return gdbarch_num_regs (gdbarch) + regnum; | |
88c72b7d AC |
5443 | } |
5444 | ||
2f38ef89 | 5445 | |
a4b8ebc8 | 5446 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 5447 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5448 | |
5449 | static int | |
d3f73121 | 5450 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5451 | { |
a4b8ebc8 | 5452 | int regnum; |
2f38ef89 | 5453 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5454 | regnum = num; |
2f38ef89 | 5455 | else if (num >= 32 && num < 64) |
d3f73121 | 5456 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 5457 | else if (num == 64) |
d3f73121 | 5458 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5459 | else if (num == 65) |
d3f73121 | 5460 | regnum = mips_regnum (gdbarch)->lo; |
2f38ef89 | 5461 | else |
a4b8ebc8 AC |
5462 | /* This will hopefully (eventually) provoke a warning. Should we |
5463 | be calling complaint() here? */ | |
d3f73121 MD |
5464 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5465 | return gdbarch_num_regs (gdbarch) + regnum; | |
a4b8ebc8 AC |
5466 | } |
5467 | ||
5468 | static int | |
e7faf938 | 5469 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
5470 | { |
5471 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 5472 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
5473 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
5474 | decide if it is valid. Should instead define a standard sim/gdb | |
5475 | register numbering scheme. */ | |
e7faf938 MD |
5476 | if (gdbarch_register_name (gdbarch, |
5477 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
5478 | && gdbarch_register_name (gdbarch, | |
5479 | gdbarch_num_regs (gdbarch) + regnum)[0] != '\0') | |
a4b8ebc8 AC |
5480 | return regnum; |
5481 | else | |
6d82d43b | 5482 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
5483 | } |
5484 | ||
2f38ef89 | 5485 | |
4844f454 CV |
5486 | /* Convert an integer into an address. Extracting the value signed |
5487 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
5488 | |
5489 | static CORE_ADDR | |
79dd2d24 | 5490 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 5491 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 5492 | { |
e17a4113 UW |
5493 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
5494 | return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); | |
fc0c74b1 AC |
5495 | } |
5496 | ||
82e91389 DJ |
5497 | /* Dummy virtual frame pointer method. This is no more or less accurate |
5498 | than most other architectures; we just need to be explicit about it, | |
5499 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
5500 | an assertion failure. */ | |
5501 | ||
5502 | static void | |
a54fba4c MD |
5503 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
5504 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
5505 | { |
5506 | *reg = MIPS_SP_REGNUM; | |
5507 | *offset = 0; | |
5508 | } | |
5509 | ||
caaa3122 DJ |
5510 | static void |
5511 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5512 | { | |
5513 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5514 | const char *name = bfd_get_section_name (abfd, sect); | |
5515 | ||
5516 | if (*abip != MIPS_ABI_UNKNOWN) | |
5517 | return; | |
5518 | ||
5519 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5520 | return; | |
5521 | ||
5522 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5523 | *abip = MIPS_ABI_O32; | |
5524 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5525 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5526 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5527 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5528 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5529 | *abip = MIPS_ABI_O64; | |
5530 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5531 | *abip = MIPS_ABI_EABI32; | |
5532 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5533 | *abip = MIPS_ABI_EABI64; | |
5534 | else | |
8a3fe4f8 | 5535 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
5536 | } |
5537 | ||
22e47e37 FF |
5538 | static void |
5539 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
5540 | { | |
5541 | int *lbp = (int *) obj; | |
5542 | const char *name = bfd_get_section_name (abfd, sect); | |
5543 | ||
5544 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
5545 | *lbp = 32; | |
5546 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
5547 | *lbp = 64; | |
5548 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
5549 | warning (_("unrecognized .gcc_compiled_longXX")); | |
5550 | } | |
5551 | ||
2e4ebe70 DJ |
5552 | static enum mips_abi |
5553 | global_mips_abi (void) | |
5554 | { | |
5555 | int i; | |
5556 | ||
5557 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5558 | if (mips_abi_strings[i] == mips_abi_string) | |
5559 | return (enum mips_abi) i; | |
5560 | ||
e2e0b3e5 | 5561 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
5562 | } |
5563 | ||
29709017 DJ |
5564 | static void |
5565 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
5566 | { | |
29709017 DJ |
5567 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
5568 | assume that's what we've got. */ | |
4eb0ad19 DJ |
5569 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
5570 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5571 | |
5572 | /* If the size matches the full set of registers GDB traditionally | |
5573 | knows about, including floating point, for either 32-bit or | |
5574 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
5575 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
5576 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5577 | |
5578 | /* Otherwise we don't have a useful guess. */ | |
5579 | } | |
5580 | ||
f8b73d13 DJ |
5581 | static struct value * |
5582 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
5583 | { | |
5584 | const int *reg_p = baton; | |
5585 | return value_of_register (*reg_p, frame); | |
5586 | } | |
5587 | ||
c2d11a7d | 5588 | static struct gdbarch * |
6d82d43b | 5589 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5590 | { |
c2d11a7d JM |
5591 | struct gdbarch *gdbarch; |
5592 | struct gdbarch_tdep *tdep; | |
5593 | int elf_flags; | |
2e4ebe70 | 5594 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 5595 | int i, num_regs; |
8d5838b5 | 5596 | enum mips_fpu_type fpu_type; |
f8b73d13 | 5597 | struct tdesc_arch_data *tdesc_data = NULL; |
609ca2b9 | 5598 | int elf_fpu_type = 0; |
f8b73d13 DJ |
5599 | |
5600 | /* Check any target description for validity. */ | |
5601 | if (tdesc_has_registers (info.target_desc)) | |
5602 | { | |
5603 | static const char *const mips_gprs[] = { | |
5604 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
5605 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
5606 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
5607 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
5608 | }; | |
5609 | static const char *const mips_fprs[] = { | |
5610 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
5611 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
5612 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
5613 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
5614 | }; | |
5615 | ||
5616 | const struct tdesc_feature *feature; | |
5617 | int valid_p; | |
5618 | ||
5619 | feature = tdesc_find_feature (info.target_desc, | |
5620 | "org.gnu.gdb.mips.cpu"); | |
5621 | if (feature == NULL) | |
5622 | return NULL; | |
5623 | ||
5624 | tdesc_data = tdesc_data_alloc (); | |
5625 | ||
5626 | valid_p = 1; | |
5627 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
5628 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
5629 | mips_gprs[i]); | |
5630 | ||
5631 | ||
5632 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5633 | MIPS_EMBED_LO_REGNUM, "lo"); | |
5634 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5635 | MIPS_EMBED_HI_REGNUM, "hi"); | |
5636 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5637 | MIPS_EMBED_PC_REGNUM, "pc"); | |
5638 | ||
5639 | if (!valid_p) | |
5640 | { | |
5641 | tdesc_data_cleanup (tdesc_data); | |
5642 | return NULL; | |
5643 | } | |
5644 | ||
5645 | feature = tdesc_find_feature (info.target_desc, | |
5646 | "org.gnu.gdb.mips.cp0"); | |
5647 | if (feature == NULL) | |
5648 | { | |
5649 | tdesc_data_cleanup (tdesc_data); | |
5650 | return NULL; | |
5651 | } | |
5652 | ||
5653 | valid_p = 1; | |
5654 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5655 | MIPS_EMBED_BADVADDR_REGNUM, | |
5656 | "badvaddr"); | |
5657 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5658 | MIPS_PS_REGNUM, "status"); | |
5659 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5660 | MIPS_EMBED_CAUSE_REGNUM, "cause"); | |
5661 | ||
5662 | if (!valid_p) | |
5663 | { | |
5664 | tdesc_data_cleanup (tdesc_data); | |
5665 | return NULL; | |
5666 | } | |
5667 | ||
5668 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
5669 | backend is not prepared for that, though. */ | |
5670 | feature = tdesc_find_feature (info.target_desc, | |
5671 | "org.gnu.gdb.mips.fpu"); | |
5672 | if (feature == NULL) | |
5673 | { | |
5674 | tdesc_data_cleanup (tdesc_data); | |
5675 | return NULL; | |
5676 | } | |
5677 | ||
5678 | valid_p = 1; | |
5679 | for (i = 0; i < 32; i++) | |
5680 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5681 | i + MIPS_EMBED_FP0_REGNUM, | |
5682 | mips_fprs[i]); | |
5683 | ||
5684 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5685 | MIPS_EMBED_FP0_REGNUM + 32, "fcsr"); | |
5686 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5687 | MIPS_EMBED_FP0_REGNUM + 33, "fir"); | |
5688 | ||
5689 | if (!valid_p) | |
5690 | { | |
5691 | tdesc_data_cleanup (tdesc_data); | |
5692 | return NULL; | |
5693 | } | |
5694 | ||
5695 | /* It would be nice to detect an attempt to use a 64-bit ABI | |
5696 | when only 32-bit registers are provided. */ | |
5697 | } | |
c2d11a7d | 5698 | |
ec03c1ac AC |
5699 | /* First of all, extract the elf_flags, if available. */ |
5700 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5701 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5702 | else if (arches != NULL) |
5703 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5704 | else |
5705 | elf_flags = 0; | |
5706 | if (gdbarch_debug) | |
5707 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5708 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5709 | |
102182a9 | 5710 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5711 | switch ((elf_flags & EF_MIPS_ABI)) |
5712 | { | |
5713 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5714 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5715 | break; |
5716 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5717 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5718 | break; |
5719 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5720 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5721 | break; |
5722 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5723 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5724 | break; |
5725 | default: | |
acdb74a0 | 5726 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5727 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5728 | else |
ec03c1ac | 5729 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5730 | break; |
5731 | } | |
acdb74a0 | 5732 | |
caaa3122 | 5733 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5734 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5735 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5736 | |
dc305454 | 5737 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
5738 | MIPS architecture (if there is one). */ |
5739 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5740 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5741 | |
32a6503c | 5742 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5743 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5744 | && info.bfd_arch_info != NULL |
5745 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5746 | { | |
5747 | switch (info.bfd_arch_info->mach) | |
5748 | { | |
5749 | case bfd_mach_mips3900: | |
ec03c1ac | 5750 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5751 | break; |
5752 | case bfd_mach_mips4100: | |
5753 | case bfd_mach_mips5000: | |
ec03c1ac | 5754 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5755 | break; |
1d06468c EZ |
5756 | case bfd_mach_mips8000: |
5757 | case bfd_mach_mips10000: | |
32a6503c KB |
5758 | /* On Irix, ELF64 executables use the N64 ABI. The |
5759 | pseudo-sections which describe the ABI aren't present | |
5760 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5761 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5762 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5763 | found_abi = MIPS_ABI_N64; |
28d169de | 5764 | else |
ec03c1ac | 5765 | found_abi = MIPS_ABI_N32; |
1d06468c | 5766 | break; |
bf64bfd6 AC |
5767 | } |
5768 | } | |
2e4ebe70 | 5769 | |
26c53e50 DJ |
5770 | /* Default 64-bit objects to N64 instead of O32. */ |
5771 | if (found_abi == MIPS_ABI_UNKNOWN | |
5772 | && info.abfd != NULL | |
5773 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
5774 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5775 | found_abi = MIPS_ABI_N64; | |
5776 | ||
ec03c1ac AC |
5777 | if (gdbarch_debug) |
5778 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5779 | found_abi); | |
5780 | ||
5781 | /* What has the user specified from the command line? */ | |
5782 | wanted_abi = global_mips_abi (); | |
5783 | if (gdbarch_debug) | |
5784 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5785 | wanted_abi); | |
2e4ebe70 DJ |
5786 | |
5787 | /* Now that we have found what the ABI for this binary would be, | |
5788 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5789 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5790 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5791 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5792 | mips_abi = found_abi; | |
5793 | else | |
5794 | mips_abi = MIPS_ABI_O32; | |
5795 | if (gdbarch_debug) | |
5796 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5797 | mips_abi); | |
2e4ebe70 | 5798 | |
ec03c1ac | 5799 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5800 | if (gdbarch_debug) |
ec03c1ac AC |
5801 | fprintf_unfiltered (gdb_stdlog, |
5802 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
5803 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 5804 | |
8d5838b5 | 5805 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
5806 | #ifdef HAVE_ELF |
5807 | if (info.abfd | |
5808 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5809 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
5810 | Tag_GNU_MIPS_ABI_FP); | |
5811 | #endif /* HAVE_ELF */ | |
5812 | ||
8d5838b5 AC |
5813 | if (!mips_fpu_type_auto) |
5814 | fpu_type = mips_fpu_type; | |
609ca2b9 DJ |
5815 | else if (elf_fpu_type != 0) |
5816 | { | |
5817 | switch (elf_fpu_type) | |
5818 | { | |
5819 | case 1: | |
5820 | fpu_type = MIPS_FPU_DOUBLE; | |
5821 | break; | |
5822 | case 2: | |
5823 | fpu_type = MIPS_FPU_SINGLE; | |
5824 | break; | |
5825 | case 3: | |
5826 | default: | |
5827 | /* Soft float or unknown. */ | |
5828 | fpu_type = MIPS_FPU_NONE; | |
5829 | break; | |
5830 | } | |
5831 | } | |
8d5838b5 AC |
5832 | else if (info.bfd_arch_info != NULL |
5833 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5834 | switch (info.bfd_arch_info->mach) | |
5835 | { | |
5836 | case bfd_mach_mips3900: | |
5837 | case bfd_mach_mips4100: | |
5838 | case bfd_mach_mips4111: | |
a9d61c86 | 5839 | case bfd_mach_mips4120: |
8d5838b5 AC |
5840 | fpu_type = MIPS_FPU_NONE; |
5841 | break; | |
5842 | case bfd_mach_mips4650: | |
5843 | fpu_type = MIPS_FPU_SINGLE; | |
5844 | break; | |
5845 | default: | |
5846 | fpu_type = MIPS_FPU_DOUBLE; | |
5847 | break; | |
5848 | } | |
5849 | else if (arches != NULL) | |
5850 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5851 | else | |
5852 | fpu_type = MIPS_FPU_DOUBLE; | |
5853 | if (gdbarch_debug) | |
5854 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5855 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5856 | |
29709017 DJ |
5857 | /* Check for blatant incompatibilities. */ |
5858 | ||
5859 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
5860 | ABI. */ | |
5861 | if (info.target_desc | |
5862 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
5863 | && mips_abi != MIPS_ABI_EABI32 | |
5864 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
5865 | { |
5866 | if (tdesc_data != NULL) | |
5867 | tdesc_data_cleanup (tdesc_data); | |
5868 | return NULL; | |
5869 | } | |
29709017 | 5870 | |
c2d11a7d JM |
5871 | /* try to find a pre-existing architecture */ |
5872 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5873 | arches != NULL; | |
5874 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5875 | { | |
5876 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5877 | using. */ |
9103eae0 | 5878 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5879 | continue; |
9103eae0 | 5880 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5881 | continue; |
719ec221 AC |
5882 | /* Need to be pedantic about which register virtual size is |
5883 | used. */ | |
5884 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5885 | != mips64_transfers_32bit_regs_p) | |
5886 | continue; | |
8d5838b5 AC |
5887 | /* Be pedantic about which FPU is selected. */ |
5888 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5889 | continue; | |
f8b73d13 DJ |
5890 | |
5891 | if (tdesc_data != NULL) | |
5892 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 5893 | return arches->gdbarch; |
c2d11a7d JM |
5894 | } |
5895 | ||
102182a9 | 5896 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5897 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5898 | gdbarch = gdbarch_alloc (&info, tdep); | |
5899 | tdep->elf_flags = elf_flags; | |
719ec221 | 5900 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5901 | tdep->found_abi = found_abi; |
5902 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5903 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
5904 | tdep->register_size_valid_p = 0; |
5905 | tdep->register_size = 0; | |
50e8a0d5 HZ |
5906 | tdep->gregset = NULL; |
5907 | tdep->gregset64 = NULL; | |
5908 | tdep->fpregset = NULL; | |
5909 | tdep->fpregset64 = NULL; | |
29709017 DJ |
5910 | |
5911 | if (info.target_desc) | |
5912 | { | |
5913 | /* Some useful properties can be inferred from the target. */ | |
5914 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
5915 | { | |
5916 | tdep->register_size_valid_p = 1; | |
5917 | tdep->register_size = 4; | |
5918 | } | |
5919 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
5920 | { | |
5921 | tdep->register_size_valid_p = 1; | |
5922 | tdep->register_size = 8; | |
5923 | } | |
5924 | } | |
c2d11a7d | 5925 | |
102182a9 | 5926 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5927 | set_gdbarch_short_bit (gdbarch, 16); |
5928 | set_gdbarch_int_bit (gdbarch, 32); | |
5929 | set_gdbarch_float_bit (gdbarch, 32); | |
5930 | set_gdbarch_double_bit (gdbarch, 64); | |
5931 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5932 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5933 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5934 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5935 | |
6d82d43b | 5936 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
5937 | mips_elf_make_msymbol_special); |
5938 | ||
16e109ca | 5939 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5940 | { |
16e109ca | 5941 | const char **reg_names; |
56cea623 AC |
5942 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5943 | struct mips_regnum); | |
f8b73d13 DJ |
5944 | if (tdesc_has_registers (info.target_desc)) |
5945 | { | |
5946 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5947 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5948 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5949 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5950 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5951 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5952 | regnum->fp_control_status = 70; | |
5953 | regnum->fp_implementation_revision = 71; | |
5954 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
5955 | reg_names = NULL; | |
5956 | } | |
5957 | else if (info.osabi == GDB_OSABI_IRIX) | |
56cea623 AC |
5958 | { |
5959 | regnum->fp0 = 32; | |
5960 | regnum->pc = 64; | |
5961 | regnum->cause = 65; | |
5962 | regnum->badvaddr = 66; | |
5963 | regnum->hi = 67; | |
5964 | regnum->lo = 68; | |
5965 | regnum->fp_control_status = 69; | |
5966 | regnum->fp_implementation_revision = 70; | |
5967 | num_regs = 71; | |
16e109ca | 5968 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5969 | } |
5970 | else | |
5971 | { | |
5972 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5973 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5974 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5975 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5976 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5977 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5978 | regnum->fp_control_status = 70; | |
5979 | regnum->fp_implementation_revision = 71; | |
5980 | num_regs = 90; | |
16e109ca AC |
5981 | if (info.bfd_arch_info != NULL |
5982 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5983 | reg_names = mips_tx39_reg_names; | |
5984 | else | |
5985 | reg_names = mips_generic_reg_names; | |
56cea623 | 5986 | } |
3e8c568d | 5987 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been |
fb14de7b | 5988 | replaced by gdbarch_read_pc? */ |
f10683bb MH |
5989 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
5990 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
5991 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
5992 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5993 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca | 5994 | set_gdbarch_register_name (gdbarch, mips_register_name); |
82e91389 | 5995 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); |
16e109ca AC |
5996 | tdep->mips_processor_reg_names = reg_names; |
5997 | tdep->regnum = regnum; | |
56cea623 | 5998 | } |
fe29b929 | 5999 | |
0dadbba0 | 6000 | switch (mips_abi) |
c2d11a7d | 6001 | { |
0dadbba0 | 6002 | case MIPS_ABI_O32: |
25ab4790 | 6003 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 6004 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 6005 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 6006 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 6007 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6008 | set_gdbarch_long_bit (gdbarch, 32); |
6009 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6010 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6011 | break; | |
0dadbba0 | 6012 | case MIPS_ABI_O64: |
25ab4790 | 6013 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 6014 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 6015 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 6016 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 6017 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6018 | set_gdbarch_long_bit (gdbarch, 32); |
6019 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6020 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6021 | break; | |
0dadbba0 | 6022 | case MIPS_ABI_EABI32: |
25ab4790 | 6023 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 6024 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 6025 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6026 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6027 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6028 | set_gdbarch_long_bit (gdbarch, 32); |
6029 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6030 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6031 | break; | |
0dadbba0 | 6032 | case MIPS_ABI_EABI64: |
25ab4790 | 6033 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 6034 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 6035 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6036 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6037 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6038 | set_gdbarch_long_bit (gdbarch, 64); |
6039 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6040 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6041 | break; | |
0dadbba0 | 6042 | case MIPS_ABI_N32: |
25ab4790 | 6043 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 6044 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 6045 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6046 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6047 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
6048 | set_gdbarch_long_bit (gdbarch, 32); |
6049 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6050 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 6051 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 6052 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
6053 | break; |
6054 | case MIPS_ABI_N64: | |
25ab4790 | 6055 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 6056 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 6057 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6058 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
6059 | tdep->default_mask_address_p = 0; |
6060 | set_gdbarch_long_bit (gdbarch, 64); | |
6061 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6062 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 6063 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 6064 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 6065 | break; |
c2d11a7d | 6066 | default: |
e2e0b3e5 | 6067 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
6068 | } |
6069 | ||
22e47e37 FF |
6070 | /* GCC creates a pseudo-section whose name specifies the size of |
6071 | longs, since -mlong32 or -mlong64 may be used independent of | |
6072 | other options. How those options affect pointer sizes is ABI and | |
6073 | architecture dependent, so use them to override the default sizes | |
6074 | set by the ABI. This table shows the relationship between ABI, | |
6075 | -mlongXX, and size of pointers: | |
6076 | ||
6077 | ABI -mlongXX ptr bits | |
6078 | --- -------- -------- | |
6079 | o32 32 32 | |
6080 | o32 64 32 | |
6081 | n32 32 32 | |
6082 | n32 64 64 | |
6083 | o64 32 32 | |
6084 | o64 64 64 | |
6085 | n64 32 32 | |
6086 | n64 64 64 | |
6087 | eabi32 32 32 | |
6088 | eabi32 64 32 | |
6089 | eabi64 32 32 | |
6090 | eabi64 64 64 | |
6091 | ||
6092 | Note that for o32 and eabi32, pointers are always 32 bits | |
6093 | regardless of any -mlongXX option. For all others, pointers and | |
6094 | longs are the same, as set by -mlongXX or set by defaults. | |
6095 | */ | |
6096 | ||
6097 | if (info.abfd != NULL) | |
6098 | { | |
6099 | int long_bit = 0; | |
6100 | ||
6101 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
6102 | if (long_bit) | |
6103 | { | |
6104 | set_gdbarch_long_bit (gdbarch, long_bit); | |
6105 | switch (mips_abi) | |
6106 | { | |
6107 | case MIPS_ABI_O32: | |
6108 | case MIPS_ABI_EABI32: | |
6109 | break; | |
6110 | case MIPS_ABI_N32: | |
6111 | case MIPS_ABI_O64: | |
6112 | case MIPS_ABI_N64: | |
6113 | case MIPS_ABI_EABI64: | |
6114 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
6115 | break; | |
6116 | default: | |
6117 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
6118 | } | |
6119 | } | |
6120 | } | |
6121 | ||
a5ea2558 AC |
6122 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
6123 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
6124 | comment: | |
6125 | ||
6126 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
6127 | flag in object files because to do so would make it impossible to | |
102182a9 | 6128 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 6129 | unnecessarily restrictive. |
361d1df0 | 6130 | |
a5ea2558 AC |
6131 | We could solve this problem by adding "-gp32" multilibs to gcc, |
6132 | but to set this flag before gcc is built with such multilibs will | |
6133 | break too many systems.'' | |
6134 | ||
6135 | But even more unhelpfully, the default linker output target for | |
6136 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
6137 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 6138 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
6139 | this flag to detect 32-bit mode would do the wrong thing given |
6140 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 6141 | as 32-bit programs by default. */ |
a5ea2558 | 6142 | |
6c997a34 | 6143 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 6144 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 6145 | |
102182a9 MS |
6146 | /* Add/remove bits from an address. The MIPS needs be careful to |
6147 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
6148 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
6149 | ||
58dfe9ff AC |
6150 | /* Unwind the frame. */ |
6151 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 6152 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 6153 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 6154 | |
102182a9 | 6155 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 6156 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
6157 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
6158 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
6159 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
6160 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 6161 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 6162 | |
c2d11a7d JM |
6163 | /* MIPS version of CALL_DUMMY */ |
6164 | ||
9710e734 AC |
6165 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
6166 | replaced by a command, and all targets will default to on stack | |
6167 | (regardless of the stack's execute status). */ | |
6168 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 6169 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 6170 | |
87783b8b AC |
6171 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
6172 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
6173 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
6174 | ||
f7b9e9fc AC |
6175 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
6176 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
6177 | |
6178 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 6179 | |
97ab0fdd MR |
6180 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
6181 | ||
fc0c74b1 AC |
6182 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
6183 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
6184 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 6185 | |
a4b8ebc8 | 6186 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 6187 | |
e11c53d2 | 6188 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 6189 | |
9dae60cc UW |
6190 | if (mips_abi == MIPS_ABI_N32) |
6191 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); | |
6192 | else if (mips_abi == MIPS_ABI_N64) | |
6193 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); | |
6194 | else | |
6195 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); | |
e5ab0dce | 6196 | |
d92524f1 PM |
6197 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
6198 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 6199 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
6200 | being used as guards for target_stopped_by_watchpoint, why not have |
6201 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
6202 | is sitting on? */ |
6203 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6204 | ||
e7d6a6d2 | 6205 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 6206 | |
3352ef37 AC |
6207 | set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay); |
6208 | ||
0d5de010 DJ |
6209 | /* Virtual tables. */ |
6210 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
6211 | ||
29709017 DJ |
6212 | mips_register_g_packet_guesses (gdbarch); |
6213 | ||
6de918a6 | 6214 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 6215 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 6216 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 6217 | |
5792a79b | 6218 | /* Unwind the frame. */ |
b8a22b94 DJ |
6219 | dwarf2_append_unwinders (gdbarch); |
6220 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
6221 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
6222 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); | |
2bd0c3d7 | 6223 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 6224 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
6225 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
6226 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 6227 | |
f8b73d13 DJ |
6228 | if (tdesc_data) |
6229 | { | |
6230 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 6231 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
6232 | |
6233 | /* Override the normal target description methods to handle our | |
6234 | dual real and pseudo registers. */ | |
6235 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
6236 | set_gdbarch_register_reggroup_p (gdbarch, mips_tdesc_register_reggroup_p); | |
6237 | ||
6238 | num_regs = gdbarch_num_regs (gdbarch); | |
6239 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
6240 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
6241 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
6242 | } | |
6243 | ||
6244 | /* Add ABI-specific aliases for the registers. */ | |
6245 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
6246 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
6247 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
6248 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
6249 | else | |
6250 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
6251 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
6252 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
6253 | ||
6254 | /* Add some other standard aliases. */ | |
6255 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
6256 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
6257 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
6258 | ||
865093a3 AR |
6259 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
6260 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
6261 | value_of_mips_user_reg, | |
6262 | &mips_numeric_register_aliases[i].regnum); | |
6263 | ||
4b9b3959 AC |
6264 | return gdbarch; |
6265 | } | |
6266 | ||
2e4ebe70 | 6267 | static void |
6d82d43b | 6268 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
6269 | { |
6270 | struct gdbarch_info info; | |
6271 | ||
6272 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6273 | mips_gdbarch_init will take care of the rest. */ | |
6274 | gdbarch_info_init (&info); | |
6275 | gdbarch_update_p (info); | |
6276 | } | |
6277 | ||
ad188201 KB |
6278 | /* Print out which MIPS ABI is in use. */ |
6279 | ||
6280 | static void | |
1f8ca57c JB |
6281 | show_mips_abi (struct ui_file *file, |
6282 | int from_tty, | |
6283 | struct cmd_list_element *ignored_cmd, | |
6284 | const char *ignored_value) | |
ad188201 | 6285 | { |
1cf3db46 | 6286 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
1f8ca57c JB |
6287 | fprintf_filtered |
6288 | (file, | |
6289 | "The MIPS ABI is unknown because the current architecture " | |
6290 | "is not MIPS.\n"); | |
ad188201 KB |
6291 | else |
6292 | { | |
6293 | enum mips_abi global_abi = global_mips_abi (); | |
1cf3db46 | 6294 | enum mips_abi actual_abi = mips_abi (target_gdbarch); |
ad188201 KB |
6295 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
6296 | ||
6297 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
6298 | fprintf_filtered |
6299 | (file, | |
6300 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 6301 | actual_abi_str); |
ad188201 | 6302 | else if (global_abi == actual_abi) |
1f8ca57c JB |
6303 | fprintf_filtered |
6304 | (file, | |
6305 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 6306 | actual_abi_str); |
ad188201 KB |
6307 | else |
6308 | { | |
6309 | /* Probably shouldn't happen... */ | |
1f8ca57c JB |
6310 | fprintf_filtered |
6311 | (file, | |
6312 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6d82d43b | 6313 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
6314 | } |
6315 | } | |
6316 | } | |
6317 | ||
4b9b3959 | 6318 | static void |
72a155b4 | 6319 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 6320 | { |
72a155b4 | 6321 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 6322 | if (tdep != NULL) |
c2d11a7d | 6323 | { |
acdb74a0 AC |
6324 | int ef_mips_arch; |
6325 | int ef_mips_32bitmode; | |
f49e4e6d | 6326 | /* Determine the ISA. */ |
acdb74a0 AC |
6327 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
6328 | { | |
6329 | case E_MIPS_ARCH_1: | |
6330 | ef_mips_arch = 1; | |
6331 | break; | |
6332 | case E_MIPS_ARCH_2: | |
6333 | ef_mips_arch = 2; | |
6334 | break; | |
6335 | case E_MIPS_ARCH_3: | |
6336 | ef_mips_arch = 3; | |
6337 | break; | |
6338 | case E_MIPS_ARCH_4: | |
93d56215 | 6339 | ef_mips_arch = 4; |
acdb74a0 AC |
6340 | break; |
6341 | default: | |
93d56215 | 6342 | ef_mips_arch = 0; |
acdb74a0 AC |
6343 | break; |
6344 | } | |
f49e4e6d | 6345 | /* Determine the size of a pointer. */ |
acdb74a0 | 6346 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
6347 | fprintf_unfiltered (file, |
6348 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6349 | tdep->elf_flags); |
4b9b3959 | 6350 | fprintf_unfiltered (file, |
acdb74a0 AC |
6351 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6352 | ef_mips_32bitmode); | |
6353 | fprintf_unfiltered (file, | |
6354 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6355 | ef_mips_arch); | |
6356 | fprintf_unfiltered (file, | |
6357 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 6358 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
6359 | fprintf_unfiltered (file, |
6360 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 6361 | mips_mask_address_p (tdep), |
4014092b | 6362 | tdep->default_mask_address_p); |
c2d11a7d | 6363 | } |
4b9b3959 AC |
6364 | fprintf_unfiltered (file, |
6365 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6366 | MIPS_DEFAULT_FPU_TYPE, | |
6367 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6368 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6369 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6370 | : "???")); | |
74ed0bb4 MD |
6371 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
6372 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
6373 | fprintf_unfiltered (file, |
6374 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 MD |
6375 | MIPS_FPU_TYPE (gdbarch), |
6376 | (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" | |
6377 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" | |
6378 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" | |
4b9b3959 | 6379 | : "???")); |
c2d11a7d JM |
6380 | } |
6381 | ||
6d82d43b | 6382 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 6383 | |
c906108c | 6384 | void |
acdb74a0 | 6385 | _initialize_mips_tdep (void) |
c906108c SS |
6386 | { |
6387 | static struct cmd_list_element *mipsfpulist = NULL; | |
6388 | struct cmd_list_element *c; | |
6389 | ||
6d82d43b | 6390 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
6391 | if (MIPS_ABI_LAST + 1 |
6392 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 6393 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 6394 | |
4b9b3959 | 6395 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6396 | |
8d5f9dcb DJ |
6397 | mips_pdr_data = register_objfile_data (); |
6398 | ||
4eb0ad19 DJ |
6399 | /* Create feature sets with the appropriate properties. The values |
6400 | are not important. */ | |
6401 | mips_tdesc_gp32 = allocate_target_description (); | |
6402 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
6403 | ||
6404 | mips_tdesc_gp64 = allocate_target_description (); | |
6405 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
6406 | ||
a5ea2558 AC |
6407 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6408 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
1bedd215 | 6409 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6410 | &setmipscmdlist, "set mips ", 0, &setlist); |
6411 | ||
6412 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 6413 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6414 | &showmipscmdlist, "show mips ", 0, &showlist); |
6415 | ||
2e4ebe70 | 6416 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
6417 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
6418 | &mips_abi_string, _("\ | |
6419 | Set the MIPS ABI used by this program."), _("\ | |
6420 | Show the MIPS ABI used by this program."), _("\ | |
6421 | This option can be set to one of:\n\ | |
6422 | auto - the default ABI associated with the current binary\n\ | |
6423 | o32\n\ | |
6424 | o64\n\ | |
6425 | n32\n\ | |
6426 | n64\n\ | |
6427 | eabi32\n\ | |
6428 | eabi64"), | |
6429 | mips_abi_update, | |
6430 | show_mips_abi, | |
6431 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 6432 | |
c906108c SS |
6433 | /* Let the user turn off floating point and set the fence post for |
6434 | heuristic_proc_start. */ | |
6435 | ||
6436 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 6437 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
6438 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
6439 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 6440 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
6441 | &mipsfpulist); |
6442 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 6443 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
6444 | &mipsfpulist); |
6445 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6446 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6447 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6448 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 6449 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
6450 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
6451 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6452 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6453 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 6454 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
6455 | &mipsfpulist); |
6456 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 6457 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
6458 | &showlist); |
6459 | ||
c906108c SS |
6460 | /* We really would like to have both "0" and "unlimited" work, but |
6461 | command.c doesn't deal with that. So make it a var_zinteger | |
6462 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 6463 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
6464 | &heuristic_fence_post, _("\ |
6465 | Set the distance searched for the start of a function."), _("\ | |
6466 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
6467 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
6468 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 6469 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 6470 | reinit_frame_cache_sfunc, |
7915a72c | 6471 | NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */ |
6bcadd06 | 6472 | &setlist, &showlist); |
c906108c SS |
6473 | |
6474 | /* Allow the user to control whether the upper bits of 64-bit | |
6475 | addresses should be zeroed. */ | |
7915a72c AC |
6476 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
6477 | &mask_address_var, _("\ | |
6478 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
6479 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
cce7e648 | 6480 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
7915a72c | 6481 | allow GDB to determine the correct value."), |
08546159 AC |
6482 | NULL, show_mask_address, |
6483 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6484 | |
6485 | /* Allow the user to control the size of 32 bit registers within the | |
6486 | raw remote packet. */ | |
b3f42336 | 6487 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
6488 | &mips64_transfers_32bit_regs_p, _("\ |
6489 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6490 | _("\ | |
6491 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6492 | _("\ | |
719ec221 AC |
6493 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6494 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 6495 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 6496 | set_mips64_transfers_32bit_regs, |
7915a72c | 6497 | NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */ |
7915a72c | 6498 | &setlist, &showlist); |
9ace0497 AC |
6499 | |
6500 | /* Debug this files internals. */ | |
6bcadd06 | 6501 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
6502 | &mips_debug, _("\ |
6503 | Set mips debugging."), _("\ | |
6504 | Show mips debugging."), _("\ | |
6505 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 6506 | NULL, |
7915a72c | 6507 | NULL, /* FIXME: i18n: Mips debugging is currently %s. */ |
6bcadd06 | 6508 | &setdebuglist, &showdebuglist); |
c906108c | 6509 | } |