Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
6aba47ca DJ |
3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 | |
47a35522 | 5 | Free Software Foundation, Inc. |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2 of the License, or | |
15 | (at your option) any later version. | |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b JM |
22 | You should have received a copy of the GNU General Public License |
23 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
24 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
25 | Boston, MA 02110-1301, USA. */ | |
c906108c SS |
26 | |
27 | #include "defs.h" | |
28 | #include "gdb_string.h" | |
5e2e9765 | 29 | #include "gdb_assert.h" |
c906108c SS |
30 | #include "frame.h" |
31 | #include "inferior.h" | |
32 | #include "symtab.h" | |
33 | #include "value.h" | |
34 | #include "gdbcmd.h" | |
35 | #include "language.h" | |
36 | #include "gdbcore.h" | |
37 | #include "symfile.h" | |
38 | #include "objfiles.h" | |
39 | #include "gdbtypes.h" | |
40 | #include "target.h" | |
28d069e6 | 41 | #include "arch-utils.h" |
4e052eda | 42 | #include "regcache.h" |
70f80edf | 43 | #include "osabi.h" |
d1973055 | 44 | #include "mips-tdep.h" |
fe898f56 | 45 | #include "block.h" |
a4b8ebc8 | 46 | #include "reggroups.h" |
c906108c | 47 | #include "opcode/mips.h" |
c2d11a7d JM |
48 | #include "elf/mips.h" |
49 | #include "elf-bfd.h" | |
2475bac3 | 50 | #include "symcat.h" |
a4b8ebc8 | 51 | #include "sim-regno.h" |
a89aa300 | 52 | #include "dis-asm.h" |
edfae063 AC |
53 | #include "frame-unwind.h" |
54 | #include "frame-base.h" | |
55 | #include "trad-frame.h" | |
7d9b040b | 56 | #include "infcall.h" |
fed7ba43 | 57 | #include "floatformat.h" |
29709017 DJ |
58 | #include "remote.h" |
59 | #include "target-descriptions.h" | |
2bd0c3d7 | 60 | #include "dwarf2-frame.h" |
f8b73d13 | 61 | #include "user-regs.h" |
c906108c | 62 | |
8d5f9dcb DJ |
63 | static const struct objfile_data *mips_pdr_data; |
64 | ||
5bbcb741 | 65 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 66 | |
24e05951 | 67 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
68 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
69 | #define ST0_FR (1 << 26) | |
70 | ||
b0069a17 AC |
71 | /* The sizes of floating point registers. */ |
72 | ||
73 | enum | |
74 | { | |
75 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
76 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
77 | }; | |
78 | ||
1a69e1e4 DJ |
79 | enum |
80 | { | |
81 | MIPS32_REGSIZE = 4, | |
82 | MIPS64_REGSIZE = 8 | |
83 | }; | |
0dadbba0 | 84 | |
2e4ebe70 DJ |
85 | static const char *mips_abi_string; |
86 | ||
87 | static const char *mips_abi_strings[] = { | |
88 | "auto", | |
89 | "n32", | |
90 | "o32", | |
28d169de | 91 | "n64", |
2e4ebe70 DJ |
92 | "o64", |
93 | "eabi32", | |
94 | "eabi64", | |
95 | NULL | |
96 | }; | |
97 | ||
f8b73d13 DJ |
98 | /* The standard register names, and all the valid aliases for them. */ |
99 | struct register_alias | |
100 | { | |
101 | const char *name; | |
102 | int regnum; | |
103 | }; | |
104 | ||
105 | /* Aliases for o32 and most other ABIs. */ | |
106 | const struct register_alias mips_o32_aliases[] = { | |
107 | { "ta0", 12 }, | |
108 | { "ta1", 13 }, | |
109 | { "ta2", 14 }, | |
110 | { "ta3", 15 } | |
111 | }; | |
112 | ||
113 | /* Aliases for n32 and n64. */ | |
114 | const struct register_alias mips_n32_n64_aliases[] = { | |
115 | { "ta0", 8 }, | |
116 | { "ta1", 9 }, | |
117 | { "ta2", 10 }, | |
118 | { "ta3", 11 } | |
119 | }; | |
120 | ||
121 | /* Aliases for ABI-independent registers. */ | |
122 | const struct register_alias mips_register_aliases[] = { | |
123 | /* The architecture manuals specify these ABI-independent names for | |
124 | the GPRs. */ | |
125 | #define R(n) { "r" #n, n } | |
126 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
127 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
128 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
129 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
130 | #undef R | |
131 | ||
132 | /* k0 and k1 are sometimes called these instead (for "kernel | |
133 | temp"). */ | |
134 | { "kt0", 26 }, | |
135 | { "kt1", 27 }, | |
136 | ||
137 | /* This is the traditional GDB name for the CP0 status register. */ | |
138 | { "sr", MIPS_PS_REGNUM }, | |
139 | ||
140 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
141 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
142 | ||
143 | /* This is the traditional GDB name for the FCSR. */ | |
144 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
145 | }; | |
146 | ||
7a292a7a | 147 | /* Some MIPS boards don't support floating point while others only |
ceae6e75 | 148 | support single-precision floating-point operations. */ |
c906108c SS |
149 | |
150 | enum mips_fpu_type | |
6d82d43b AC |
151 | { |
152 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
153 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
154 | MIPS_FPU_NONE /* No floating point. */ | |
155 | }; | |
c906108c SS |
156 | |
157 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
158 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
159 | #endif | |
160 | static int mips_fpu_type_auto = 1; | |
161 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 162 | |
9ace0497 | 163 | static int mips_debug = 0; |
7a292a7a | 164 | |
29709017 DJ |
165 | /* Properties (for struct target_desc) describing the g/G packet |
166 | layout. */ | |
167 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
168 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
169 | ||
c2d11a7d JM |
170 | /* MIPS specific per-architecture information */ |
171 | struct gdbarch_tdep | |
6d82d43b AC |
172 | { |
173 | /* from the elf header */ | |
174 | int elf_flags; | |
175 | ||
176 | /* mips options */ | |
177 | enum mips_abi mips_abi; | |
178 | enum mips_abi found_abi; | |
179 | enum mips_fpu_type mips_fpu_type; | |
180 | int mips_last_arg_regnum; | |
181 | int mips_last_fp_arg_regnum; | |
6d82d43b AC |
182 | int default_mask_address_p; |
183 | /* Is the target using 64-bit raw integer registers but only | |
184 | storing a left-aligned 32-bit value in each? */ | |
185 | int mips64_transfers_32bit_regs_p; | |
186 | /* Indexes for various registers. IRIX and embedded have | |
187 | different values. This contains the "public" fields. Don't | |
188 | add any that do not need to be public. */ | |
189 | const struct mips_regnum *regnum; | |
190 | /* Register names table for the current register set. */ | |
191 | const char **mips_processor_reg_names; | |
29709017 DJ |
192 | |
193 | /* The size of register data available from the target, if known. | |
194 | This doesn't quite obsolete the manual | |
195 | mips64_transfers_32bit_regs_p, since that is documented to force | |
196 | left alignment even for big endian (very strange). */ | |
197 | int register_size_valid_p; | |
198 | int register_size; | |
6d82d43b | 199 | }; |
c2d11a7d | 200 | |
fed7ba43 JB |
201 | static int |
202 | n32n64_floatformat_always_valid (const struct floatformat *fmt, | |
2244f671 | 203 | const void *from) |
fed7ba43 JB |
204 | { |
205 | return 1; | |
206 | } | |
207 | ||
208 | /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long. | |
209 | They are implemented as a pair of 64bit doubles where the high | |
210 | part holds the result of the operation rounded to double, and | |
211 | the low double holds the difference between the exact result and | |
212 | the rounded result. So "high" + "low" contains the result with | |
213 | added precision. Unfortunately, the floatformat structure used | |
214 | by GDB is not powerful enough to describe this format. As a temporary | |
215 | measure, we define a 128bit floatformat that only uses the high part. | |
216 | We lose a bit of precision but that's probably the best we can do | |
217 | for now with the current infrastructure. */ | |
218 | ||
219 | static const struct floatformat floatformat_n32n64_long_double_big = | |
220 | { | |
221 | floatformat_big, 128, 0, 1, 11, 1023, 2047, 12, 52, | |
222 | floatformat_intbit_no, | |
8da61cc4 | 223 | "floatformat_n32n64_long_double_big", |
fed7ba43 JB |
224 | n32n64_floatformat_always_valid |
225 | }; | |
226 | ||
8da61cc4 DJ |
227 | static const struct floatformat *floatformats_n32n64_long[BFD_ENDIAN_UNKNOWN] = |
228 | { | |
229 | &floatformat_n32n64_long_double_big, | |
230 | &floatformat_n32n64_long_double_big | |
231 | }; | |
232 | ||
56cea623 AC |
233 | const struct mips_regnum * |
234 | mips_regnum (struct gdbarch *gdbarch) | |
235 | { | |
236 | return gdbarch_tdep (gdbarch)->regnum; | |
237 | } | |
238 | ||
239 | static int | |
240 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
241 | { | |
242 | return mips_regnum (gdbarch)->fp0 + 12; | |
243 | } | |
244 | ||
0dadbba0 | 245 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 246 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 247 | |
c2d11a7d | 248 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 249 | |
c2d11a7d | 250 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 251 | |
c2d11a7d | 252 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 253 | |
95404a3e AC |
254 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
255 | functions to test, set, or clear bit 0 of addresses. */ | |
256 | ||
257 | static CORE_ADDR | |
258 | is_mips16_addr (CORE_ADDR addr) | |
259 | { | |
260 | return ((addr) & 1); | |
261 | } | |
262 | ||
95404a3e AC |
263 | static CORE_ADDR |
264 | unmake_mips16_addr (CORE_ADDR addr) | |
265 | { | |
5b652102 | 266 | return ((addr) & ~(CORE_ADDR) 1); |
95404a3e AC |
267 | } |
268 | ||
22540ece AC |
269 | /* Return the contents of register REGNUM as a signed integer. */ |
270 | ||
271 | static LONGEST | |
272 | read_signed_register (int regnum) | |
273 | { | |
1d93fe1a AC |
274 | LONGEST val; |
275 | regcache_cooked_read_signed (current_regcache, regnum, &val); | |
276 | return val; | |
22540ece AC |
277 | } |
278 | ||
279 | static LONGEST | |
280 | read_signed_register_pid (int regnum, ptid_t ptid) | |
281 | { | |
282 | ptid_t save_ptid; | |
283 | LONGEST retval; | |
284 | ||
285 | if (ptid_equal (ptid, inferior_ptid)) | |
286 | return read_signed_register (regnum); | |
287 | ||
288 | save_ptid = inferior_ptid; | |
289 | ||
290 | inferior_ptid = ptid; | |
291 | ||
292 | retval = read_signed_register (regnum); | |
293 | ||
294 | inferior_ptid = save_ptid; | |
295 | ||
296 | return retval; | |
297 | } | |
298 | ||
d1973055 KB |
299 | /* Return the MIPS ABI associated with GDBARCH. */ |
300 | enum mips_abi | |
301 | mips_abi (struct gdbarch *gdbarch) | |
302 | { | |
303 | return gdbarch_tdep (gdbarch)->mips_abi; | |
304 | } | |
305 | ||
4246e332 | 306 | int |
1b13c4f6 | 307 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 308 | { |
29709017 DJ |
309 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
310 | ||
311 | /* If we know how big the registers are, use that size. */ | |
312 | if (tdep->register_size_valid_p) | |
313 | return tdep->register_size; | |
314 | ||
315 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
316 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
317 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
318 | } | |
319 | ||
480d3dd2 AC |
320 | /* Return the currently configured (or set) saved register size. */ |
321 | ||
e6bc2e8a | 322 | unsigned int |
13326b4e | 323 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 324 | { |
1a69e1e4 DJ |
325 | switch (mips_abi (gdbarch)) |
326 | { | |
327 | case MIPS_ABI_EABI32: | |
328 | case MIPS_ABI_O32: | |
329 | return 4; | |
330 | case MIPS_ABI_N32: | |
331 | case MIPS_ABI_N64: | |
332 | case MIPS_ABI_O64: | |
333 | case MIPS_ABI_EABI64: | |
334 | return 8; | |
335 | case MIPS_ABI_UNKNOWN: | |
336 | case MIPS_ABI_LAST: | |
337 | default: | |
338 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
339 | } | |
d929b26f AC |
340 | } |
341 | ||
71b8ef93 | 342 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 343 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 344 | "info" field is used for this purpose. |
5a89d8aa | 345 | |
95f1da47 | 346 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
5a89d8aa MS |
347 | i.e. refers to a 16-bit function, and sets a "special" bit in a |
348 | minimal symbol to mark it as a 16-bit function | |
349 | ||
f594e5e9 | 350 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 351 | |
5a89d8aa | 352 | static void |
6d82d43b AC |
353 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
354 | { | |
355 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
356 | { | |
357 | MSYMBOL_INFO (msym) = (char *) | |
358 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
359 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
360 | } | |
5a89d8aa MS |
361 | } |
362 | ||
71b8ef93 MS |
363 | static int |
364 | msymbol_is_special (struct minimal_symbol *msym) | |
365 | { | |
366 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
367 | } | |
368 | ||
88658117 AC |
369 | /* XFER a value from the big/little/left end of the register. |
370 | Depending on the size of the value it might occupy the entire | |
371 | register or just part of it. Make an allowance for this, aligning | |
372 | things accordingly. */ | |
373 | ||
374 | static void | |
375 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
870cd05e MK |
376 | enum bfd_endian endian, gdb_byte *in, |
377 | const gdb_byte *out, int buf_offset) | |
88658117 | 378 | { |
88658117 | 379 | int reg_offset = 0; |
f57d151a | 380 | gdb_assert (reg_num >= gdbarch_num_regs (current_gdbarch)); |
cb1d2653 AC |
381 | /* Need to transfer the left or right part of the register, based on |
382 | the targets byte order. */ | |
88658117 AC |
383 | switch (endian) |
384 | { | |
385 | case BFD_ENDIAN_BIG: | |
719ec221 | 386 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
387 | break; |
388 | case BFD_ENDIAN_LITTLE: | |
389 | reg_offset = 0; | |
390 | break; | |
6d82d43b | 391 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
392 | reg_offset = 0; |
393 | break; | |
394 | default: | |
e2e0b3e5 | 395 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
396 | } |
397 | if (mips_debug) | |
cb1d2653 AC |
398 | fprintf_unfiltered (gdb_stderr, |
399 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
400 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
401 | if (mips_debug && out != NULL) |
402 | { | |
403 | int i; | |
cb1d2653 | 404 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 405 | for (i = 0; i < length; i++) |
cb1d2653 | 406 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
407 | } |
408 | if (in != NULL) | |
6d82d43b AC |
409 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
410 | in + buf_offset); | |
88658117 | 411 | if (out != NULL) |
6d82d43b AC |
412 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
413 | out + buf_offset); | |
88658117 AC |
414 | if (mips_debug && in != NULL) |
415 | { | |
416 | int i; | |
cb1d2653 | 417 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 418 | for (i = 0; i < length; i++) |
cb1d2653 | 419 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
420 | } |
421 | if (mips_debug) | |
422 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
423 | } | |
424 | ||
dd824b04 DJ |
425 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
426 | compatiblity mode. A return value of 1 means that we have | |
427 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
428 | ||
429 | static int | |
430 | mips2_fp_compat (void) | |
431 | { | |
432 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
433 | meaningful. */ | |
6d82d43b AC |
434 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == |
435 | 4) | |
dd824b04 DJ |
436 | return 0; |
437 | ||
438 | #if 0 | |
439 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
440 | in all the places we deal with FP registers. PR gdb/413. */ | |
441 | /* Otherwise check the FR bit in the status register - it controls | |
442 | the FP compatiblity mode. If it is clear we are in compatibility | |
443 | mode. */ | |
24e05951 | 444 | if ((read_register (MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
445 | return 1; |
446 | #endif | |
361d1df0 | 447 | |
dd824b04 DJ |
448 | return 0; |
449 | } | |
450 | ||
7a292a7a | 451 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 452 | |
a14ed312 | 453 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 454 | |
a14ed312 | 455 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 456 | |
a14ed312 | 457 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 458 | |
67b2c998 DJ |
459 | static struct type *mips_float_register_type (void); |
460 | static struct type *mips_double_register_type (void); | |
461 | ||
acdb74a0 AC |
462 | /* The list of available "set mips " and "show mips " commands */ |
463 | ||
464 | static struct cmd_list_element *setmipscmdlist = NULL; | |
465 | static struct cmd_list_element *showmipscmdlist = NULL; | |
466 | ||
5e2e9765 KB |
467 | /* Integer registers 0 thru 31 are handled explicitly by |
468 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 469 | are listed in the following tables. */ |
691c0433 | 470 | |
6d82d43b AC |
471 | enum |
472 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
473 | |
474 | /* Generic MIPS. */ | |
475 | ||
476 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
477 | "sr", "lo", "hi", "bad", "cause", "pc", |
478 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
479 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
480 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
481 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
482 | "fsr", "fir", "" /*"fp" */ , "", | |
483 | "", "", "", "", "", "", "", "", | |
484 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
485 | }; |
486 | ||
487 | /* Names of IDT R3041 registers. */ | |
488 | ||
489 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
490 | "sr", "lo", "hi", "bad", "cause", "pc", |
491 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
492 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
493 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
494 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
495 | "fsr", "fir", "", /*"fp" */ "", | |
496 | "", "", "bus", "ccfg", "", "", "", "", | |
497 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
498 | }; |
499 | ||
500 | /* Names of tx39 registers. */ | |
501 | ||
502 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
503 | "sr", "lo", "hi", "bad", "cause", "pc", |
504 | "", "", "", "", "", "", "", "", | |
505 | "", "", "", "", "", "", "", "", | |
506 | "", "", "", "", "", "", "", "", | |
507 | "", "", "", "", "", "", "", "", | |
508 | "", "", "", "", | |
509 | "", "", "", "", "", "", "", "", | |
510 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
511 | }; |
512 | ||
513 | /* Names of IRIX registers. */ | |
514 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
515 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
516 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
517 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
518 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
519 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
520 | }; |
521 | ||
cce74817 | 522 | |
5e2e9765 | 523 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 524 | static const char * |
5e2e9765 | 525 | mips_register_name (int regno) |
cce74817 | 526 | { |
691c0433 | 527 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
528 | /* GPR names for all ABIs other than n32/n64. */ |
529 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
530 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
531 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
532 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
533 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
534 | }; |
535 | ||
536 | /* GPR names for n32 and n64 ABIs. */ | |
537 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
538 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
539 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
540 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
541 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
542 | }; |
543 | ||
544 | enum mips_abi abi = mips_abi (current_gdbarch); | |
545 | ||
f57d151a UW |
546 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
547 | but then don't make the raw register names visible. */ | |
548 | int rawnum = regno % gdbarch_num_regs (current_gdbarch); | |
549 | if (regno < gdbarch_num_regs (current_gdbarch)) | |
a4b8ebc8 AC |
550 | return ""; |
551 | ||
5e2e9765 KB |
552 | /* The MIPS integer registers are always mapped from 0 to 31. The |
553 | names of the registers (which reflects the conventions regarding | |
554 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 555 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
556 | { |
557 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 558 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 559 | else |
a4b8ebc8 | 560 | return mips_gpr_names[rawnum]; |
5e2e9765 | 561 | } |
f8b73d13 DJ |
562 | else if (tdesc_has_registers (gdbarch_target_desc (current_gdbarch))) |
563 | return tdesc_register_name (rawnum); | |
f57d151a | 564 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (current_gdbarch)) |
691c0433 AC |
565 | { |
566 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
567 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
568 | } | |
5e2e9765 KB |
569 | else |
570 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 571 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 572 | } |
5e2e9765 | 573 | |
a4b8ebc8 | 574 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 575 | |
a4b8ebc8 AC |
576 | static int |
577 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
578 | struct reggroup *reggroup) | |
579 | { | |
580 | int vector_p; | |
581 | int float_p; | |
582 | int raw_p; | |
f57d151a UW |
583 | int rawnum = regnum % gdbarch_num_regs (current_gdbarch); |
584 | int pseudo = regnum / gdbarch_num_regs (current_gdbarch); | |
a4b8ebc8 AC |
585 | if (reggroup == all_reggroup) |
586 | return pseudo; | |
587 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
588 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
589 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
590 | (gdbarch), as not all architectures are multi-arch. */ | |
f57d151a | 591 | raw_p = rawnum < gdbarch_num_regs (current_gdbarch); |
c9f4d572 UW |
592 | if (gdbarch_register_name (current_gdbarch, regnum) == NULL |
593 | || gdbarch_register_name (current_gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
594 | return 0; |
595 | if (reggroup == float_reggroup) | |
596 | return float_p && pseudo; | |
597 | if (reggroup == vector_reggroup) | |
598 | return vector_p && pseudo; | |
599 | if (reggroup == general_reggroup) | |
600 | return (!vector_p && !float_p) && pseudo; | |
601 | /* Save the pseudo registers. Need to make certain that any code | |
602 | extracting register values from a saved register cache also uses | |
603 | pseudo registers. */ | |
604 | if (reggroup == save_reggroup) | |
605 | return raw_p && pseudo; | |
606 | /* Restore the same pseudo register. */ | |
607 | if (reggroup == restore_reggroup) | |
608 | return raw_p && pseudo; | |
6d82d43b | 609 | return 0; |
a4b8ebc8 AC |
610 | } |
611 | ||
f8b73d13 DJ |
612 | /* Return the groups that a MIPS register can be categorised into. |
613 | This version is only used if we have a target description which | |
614 | describes real registers (and their groups). */ | |
615 | ||
616 | static int | |
617 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
618 | struct reggroup *reggroup) | |
619 | { | |
620 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
621 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
622 | int ret; | |
623 | ||
624 | /* Only save, restore, and display the pseudo registers. Need to | |
625 | make certain that any code extracting register values from a | |
626 | saved register cache also uses pseudo registers. | |
627 | ||
628 | Note: saving and restoring the pseudo registers is slightly | |
629 | strange; if we have 64 bits, we should save and restore all | |
630 | 64 bits. But this is hard and has little benefit. */ | |
631 | if (!pseudo) | |
632 | return 0; | |
633 | ||
634 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
635 | if (ret != -1) | |
636 | return ret; | |
637 | ||
638 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
639 | } | |
640 | ||
a4b8ebc8 | 641 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 642 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 643 | registers. Take care of alignment and size problems. */ |
c5aa993b | 644 | |
a4b8ebc8 AC |
645 | static void |
646 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
47a35522 | 647 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 648 | { |
f57d151a UW |
649 | int rawnum = cookednum % gdbarch_num_regs (current_gdbarch); |
650 | gdb_assert (cookednum >= gdbarch_num_regs (current_gdbarch) | |
651 | && cookednum < 2 * gdbarch_num_regs (current_gdbarch)); | |
47ebcfbe | 652 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 653 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
654 | else if (register_size (gdbarch, rawnum) > |
655 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
656 | { |
657 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
4c6b5505 | 658 | || gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
659 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
660 | else | |
661 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
662 | } | |
663 | else | |
e2e0b3e5 | 664 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
665 | } |
666 | ||
667 | static void | |
6d82d43b AC |
668 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
669 | struct regcache *regcache, int cookednum, | |
47a35522 | 670 | const gdb_byte *buf) |
a4b8ebc8 | 671 | { |
f57d151a UW |
672 | int rawnum = cookednum % gdbarch_num_regs (current_gdbarch); |
673 | gdb_assert (cookednum >= gdbarch_num_regs (current_gdbarch) | |
674 | && cookednum < 2 * gdbarch_num_regs (current_gdbarch)); | |
47ebcfbe | 675 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 676 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
677 | else if (register_size (gdbarch, rawnum) > |
678 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
679 | { |
680 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
4c6b5505 | 681 | || gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
682 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
683 | else | |
684 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
685 | } | |
686 | else | |
e2e0b3e5 | 687 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 688 | } |
c5aa993b | 689 | |
c906108c | 690 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 691 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
692 | |
693 | /* Heuristic_proc_start may hunt through the text section for a long | |
694 | time across a 2400 baud serial line. Allows the user to limit this | |
695 | search. */ | |
696 | ||
697 | static unsigned int heuristic_fence_post = 0; | |
698 | ||
46cd78fb | 699 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
700 | register N. NOTE: This defines the pseudo register type so need to |
701 | rebuild the architecture vector. */ | |
43e526b9 JM |
702 | |
703 | static int mips64_transfers_32bit_regs_p = 0; | |
704 | ||
719ec221 AC |
705 | static void |
706 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
707 | struct cmd_list_element *c) | |
43e526b9 | 708 | { |
719ec221 AC |
709 | struct gdbarch_info info; |
710 | gdbarch_info_init (&info); | |
711 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
712 | instead of relying on globals. Doing that would let generic code | |
713 | handle the search for this specific architecture. */ | |
714 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 715 | { |
719ec221 | 716 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 717 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 718 | } |
a4b8ebc8 AC |
719 | } |
720 | ||
47ebcfbe | 721 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 722 | |
ff2e87ac AC |
723 | static int |
724 | mips_convert_register_p (int regnum, struct type *type) | |
725 | { | |
4c6b5505 | 726 | return (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
719ec221 | 727 | && register_size (current_gdbarch, regnum) == 4 |
f57d151a UW |
728 | && (regnum % gdbarch_num_regs (current_gdbarch)) |
729 | >= mips_regnum (current_gdbarch)->fp0 | |
730 | && (regnum % gdbarch_num_regs (current_gdbarch)) | |
731 | < mips_regnum (current_gdbarch)->fp0 + 32 | |
6d82d43b | 732 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
733 | } |
734 | ||
42c466d7 | 735 | static void |
ff2e87ac | 736 | mips_register_to_value (struct frame_info *frame, int regnum, |
47a35522 | 737 | struct type *type, gdb_byte *to) |
102182a9 | 738 | { |
47a35522 MK |
739 | get_frame_register (frame, regnum + 0, to + 4); |
740 | get_frame_register (frame, regnum + 1, to + 0); | |
102182a9 MS |
741 | } |
742 | ||
42c466d7 | 743 | static void |
ff2e87ac | 744 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 745 | struct type *type, const gdb_byte *from) |
102182a9 | 746 | { |
47a35522 MK |
747 | put_frame_register (frame, regnum + 0, from + 4); |
748 | put_frame_register (frame, regnum + 1, from + 0); | |
102182a9 MS |
749 | } |
750 | ||
a4b8ebc8 AC |
751 | /* Return the GDB type object for the "standard" data type of data in |
752 | register REG. */ | |
78fde5f8 KB |
753 | |
754 | static struct type * | |
a4b8ebc8 AC |
755 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
756 | { | |
f57d151a UW |
757 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (current_gdbarch)); |
758 | if ((regnum % gdbarch_num_regs (current_gdbarch)) | |
759 | >= mips_regnum (current_gdbarch)->fp0 | |
760 | && (regnum % gdbarch_num_regs (current_gdbarch)) | |
761 | < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 762 | { |
5ef80fb0 | 763 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 764 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 DJ |
765 | if (mips_isa_regsize (gdbarch) == 4) |
766 | return builtin_type_ieee_single; | |
767 | else | |
768 | return builtin_type_ieee_double; | |
a6425924 | 769 | } |
f57d151a | 770 | else if (regnum < gdbarch_num_regs (current_gdbarch)) |
d5ac5a39 AC |
771 | { |
772 | /* The raw or ISA registers. These are all sized according to | |
773 | the ISA regsize. */ | |
774 | if (mips_isa_regsize (gdbarch) == 4) | |
775 | return builtin_type_int32; | |
776 | else | |
777 | return builtin_type_int64; | |
778 | } | |
78fde5f8 | 779 | else |
d5ac5a39 AC |
780 | { |
781 | /* The cooked or ABI registers. These are sized according to | |
782 | the ABI (with a few complications). */ | |
f57d151a | 783 | if (regnum >= (gdbarch_num_regs (current_gdbarch) |
d5ac5a39 | 784 | + mips_regnum (current_gdbarch)->fp_control_status) |
f57d151a UW |
785 | && regnum <= gdbarch_num_regs (current_gdbarch) |
786 | + MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
787 | /* The pseudo/cooked view of the embedded registers is always |
788 | 32-bit. The raw view is handled below. */ | |
789 | return builtin_type_int32; | |
790 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
791 | /* The target, while possibly using a 64-bit register buffer, | |
792 | is only transfering 32-bits of each integer register. | |
793 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
794 | return builtin_type_int32; | |
795 | else if (mips_abi_regsize (gdbarch) == 4) | |
796 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
797 | 32- or 64-bit). */ | |
798 | return builtin_type_int32; | |
799 | else | |
800 | /* 64-bit ABI. */ | |
801 | return builtin_type_int64; | |
802 | } | |
78fde5f8 KB |
803 | } |
804 | ||
f8b73d13 DJ |
805 | /* Return the GDB type for the pseudo register REGNUM, which is the |
806 | ABI-level view. This function is only called if there is a target | |
807 | description which includes registers, so we know precisely the | |
808 | types of hardware registers. */ | |
809 | ||
810 | static struct type * | |
811 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
812 | { | |
813 | const int num_regs = gdbarch_num_regs (gdbarch); | |
814 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
815 | int rawnum = regnum % num_regs; | |
816 | struct type *rawtype; | |
817 | ||
818 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
819 | ||
820 | /* Absent registers are still absent. */ | |
821 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
822 | if (TYPE_LENGTH (rawtype) == 0) | |
823 | return rawtype; | |
824 | ||
825 | if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32) | |
826 | /* Present the floating point registers however the hardware did; | |
827 | do not try to convert between FPU layouts. */ | |
828 | return rawtype; | |
829 | ||
830 | if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
831 | { | |
832 | /* The pseudo/cooked view of embedded registers is always | |
833 | 32-bit, even if the target transfers 64-bit values for them. | |
834 | New targets relying on XML descriptions should only transfer | |
835 | the necessary 32 bits, but older versions of GDB expected 64, | |
836 | so allow the target to provide 64 bits without interfering | |
837 | with the displayed type. */ | |
838 | return builtin_type_int32; | |
839 | } | |
840 | ||
841 | /* Use pointer types for registers if we can. For n32 we can not, | |
842 | since we do not have a 64-bit pointer type. */ | |
843 | if (mips_abi_regsize (gdbarch) == TYPE_LENGTH (builtin_type_void_data_ptr)) | |
844 | { | |
845 | if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM) | |
846 | return builtin_type_void_data_ptr; | |
847 | else if (rawnum == MIPS_EMBED_PC_REGNUM) | |
848 | return builtin_type_void_func_ptr; | |
849 | } | |
850 | ||
851 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
852 | && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM) | |
853 | return builtin_type_int32; | |
854 | ||
855 | /* For all other registers, pass through the hardware type. */ | |
856 | return rawtype; | |
857 | } | |
bcb0cc15 | 858 | |
c906108c | 859 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 860 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
861 | |
862 | static int | |
480d3dd2 | 863 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
864 | { |
865 | switch (mask_address_var) | |
866 | { | |
7f19b9a2 | 867 | case AUTO_BOOLEAN_TRUE: |
4014092b | 868 | return 1; |
7f19b9a2 | 869 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
870 | return 0; |
871 | break; | |
7f19b9a2 | 872 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 873 | return tdep->default_mask_address_p; |
4014092b | 874 | default: |
e2e0b3e5 | 875 | internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch")); |
4014092b | 876 | return -1; |
361d1df0 | 877 | } |
4014092b AC |
878 | } |
879 | ||
880 | static void | |
08546159 AC |
881 | show_mask_address (struct ui_file *file, int from_tty, |
882 | struct cmd_list_element *c, const char *value) | |
4014092b | 883 | { |
480d3dd2 | 884 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
08546159 AC |
885 | |
886 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
887 | switch (mask_address_var) |
888 | { | |
7f19b9a2 | 889 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
890 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
891 | break; | |
7f19b9a2 | 892 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
893 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
894 | break; | |
7f19b9a2 | 895 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
896 | printf_filtered |
897 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
898 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
899 | break; |
900 | default: | |
e2e0b3e5 | 901 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 902 | break; |
361d1df0 | 903 | } |
4014092b | 904 | } |
c906108c | 905 | |
c906108c SS |
906 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
907 | ||
0fe7e7c8 AC |
908 | int |
909 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
910 | { |
911 | struct minimal_symbol *sym; | |
912 | ||
913 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 914 | if (is_mips16_addr (memaddr)) |
c906108c SS |
915 | return 1; |
916 | ||
917 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
918 | the high bit of the info field. Use this to decide if the function is | |
919 | MIPS16 or normal MIPS. */ | |
920 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
921 | if (sym) | |
71b8ef93 | 922 | return msymbol_is_special (sym); |
c906108c SS |
923 | else |
924 | return 0; | |
925 | } | |
926 | ||
b2fa5097 | 927 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
928 | all registers should be sign extended for simplicity? */ |
929 | ||
930 | static CORE_ADDR | |
39f77062 | 931 | mips_read_pc (ptid_t ptid) |
6c997a34 | 932 | { |
b6cb9035 AC |
933 | return read_signed_register_pid (mips_regnum (current_gdbarch)->pc, ptid); |
934 | } | |
935 | ||
58dfe9ff AC |
936 | static CORE_ADDR |
937 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
938 | { | |
edfae063 | 939 | return frame_unwind_register_signed (next_frame, |
f57d151a UW |
940 | gdbarch_num_regs (current_gdbarch) |
941 | + mips_regnum (gdbarch)->pc); | |
edfae063 AC |
942 | } |
943 | ||
30244cd8 UW |
944 | static CORE_ADDR |
945 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
946 | { | |
f57d151a UW |
947 | return frame_unwind_register_signed (next_frame, |
948 | gdbarch_num_regs (current_gdbarch) | |
949 | + MIPS_SP_REGNUM); | |
30244cd8 UW |
950 | } |
951 | ||
edfae063 AC |
952 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
953 | dummy frame. The frame ID's base needs to match the TOS value | |
954 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
955 | breakpoint. */ | |
956 | ||
957 | static struct frame_id | |
958 | mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
959 | { | |
f57d151a UW |
960 | return frame_id_build |
961 | (frame_unwind_register_signed (next_frame, | |
962 | gdbarch_num_regs (current_gdbarch) | |
963 | + MIPS_SP_REGNUM), | |
964 | frame_pc_unwind (next_frame)); | |
58dfe9ff AC |
965 | } |
966 | ||
b6cb9035 AC |
967 | static void |
968 | mips_write_pc (CORE_ADDR pc, ptid_t ptid) | |
969 | { | |
970 | write_register_pid (mips_regnum (current_gdbarch)->pc, pc, ptid); | |
6c997a34 | 971 | } |
c906108c | 972 | |
c906108c SS |
973 | /* Fetch and return instruction from the specified location. If the PC |
974 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
975 | ||
d37cca3d | 976 | static ULONGEST |
acdb74a0 | 977 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c | 978 | { |
47a35522 | 979 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
980 | int instlen; |
981 | int status; | |
982 | ||
0fe7e7c8 | 983 | if (mips_pc_is_mips16 (addr)) |
c906108c | 984 | { |
95ac2dcf | 985 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 986 | addr = unmake_mips16_addr (addr); |
c906108c SS |
987 | } |
988 | else | |
95ac2dcf | 989 | instlen = MIPS_INSN32_SIZE; |
359a9262 | 990 | status = read_memory_nobpt (addr, buf, instlen); |
c906108c SS |
991 | if (status) |
992 | memory_error (status, addr); | |
993 | return extract_unsigned_integer (buf, instlen); | |
994 | } | |
995 | ||
c906108c | 996 | /* These the fields of 32 bit mips instructions */ |
e135b889 DJ |
997 | #define mips32_op(x) (x >> 26) |
998 | #define itype_op(x) (x >> 26) | |
999 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1000 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1001 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1002 | |
e135b889 DJ |
1003 | #define jtype_op(x) (x >> 26) |
1004 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1005 | |
e135b889 DJ |
1006 | #define rtype_op(x) (x >> 26) |
1007 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1008 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1009 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1010 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1011 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 1012 | |
06987e64 MK |
1013 | static LONGEST |
1014 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 1015 | { |
06987e64 | 1016 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
1017 | } |
1018 | ||
f49e4e6d MS |
1019 | /* Determine where to set a single step breakpoint while considering |
1020 | branch prediction. */ | |
5a89d8aa | 1021 | static CORE_ADDR |
c5aa993b JM |
1022 | mips32_next_pc (CORE_ADDR pc) |
1023 | { | |
1024 | unsigned long inst; | |
1025 | int op; | |
1026 | inst = mips_fetch_instruction (pc); | |
e135b889 | 1027 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 1028 | { |
e135b889 | 1029 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1030 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1031 | { |
e135b889 | 1032 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1033 | switch (op) |
1034 | { | |
e135b889 DJ |
1035 | case 0: /* BEQL */ |
1036 | goto equal_branch; | |
1037 | case 1: /* BNEL */ | |
1038 | goto neq_branch; | |
1039 | case 2: /* BLEZL */ | |
1040 | goto less_branch; | |
1041 | case 3: /* BGTZ */ | |
1042 | goto greater_branch; | |
c5aa993b JM |
1043 | default: |
1044 | pc += 4; | |
c906108c SS |
1045 | } |
1046 | } | |
e135b889 | 1047 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1048 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
1049 | { |
1050 | int tf = itype_rt (inst) & 0x01; | |
1051 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b AC |
1052 | int fcrcs = |
1053 | read_signed_register (mips_regnum (current_gdbarch)-> | |
1054 | fp_control_status); | |
e135b889 DJ |
1055 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1056 | ||
1057 | if (((cond >> cnum) & 0x01) == tf) | |
1058 | pc += mips32_relative_offset (inst) + 4; | |
1059 | else | |
1060 | pc += 8; | |
1061 | } | |
c5aa993b JM |
1062 | else |
1063 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1064 | } |
1065 | else | |
c5aa993b JM |
1066 | { /* This gets way messy */ |
1067 | ||
c906108c | 1068 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1069 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1070 | { |
c5aa993b JM |
1071 | case 0: /* SPECIAL */ |
1072 | op = rtype_funct (inst); | |
1073 | switch (op) | |
1074 | { | |
1075 | case 8: /* JR */ | |
1076 | case 9: /* JALR */ | |
6c997a34 AC |
1077 | /* Set PC to that address */ |
1078 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
1079 | break; |
1080 | default: | |
1081 | pc += 4; | |
1082 | } | |
1083 | ||
6d82d43b | 1084 | break; /* end SPECIAL */ |
c5aa993b | 1085 | case 1: /* REGIMM */ |
c906108c | 1086 | { |
e135b889 DJ |
1087 | op = itype_rt (inst); /* branch condition */ |
1088 | switch (op) | |
c906108c | 1089 | { |
c5aa993b | 1090 | case 0: /* BLTZ */ |
e135b889 DJ |
1091 | case 2: /* BLTZL */ |
1092 | case 16: /* BLTZAL */ | |
c5aa993b | 1093 | case 18: /* BLTZALL */ |
c906108c | 1094 | less_branch: |
6c997a34 | 1095 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
1096 | pc += mips32_relative_offset (inst) + 4; |
1097 | else | |
1098 | pc += 8; /* after the delay slot */ | |
1099 | break; | |
e135b889 | 1100 | case 1: /* BGEZ */ |
c5aa993b JM |
1101 | case 3: /* BGEZL */ |
1102 | case 17: /* BGEZAL */ | |
1103 | case 19: /* BGEZALL */ | |
6c997a34 | 1104 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
1105 | pc += mips32_relative_offset (inst) + 4; |
1106 | else | |
1107 | pc += 8; /* after the delay slot */ | |
1108 | break; | |
e135b889 | 1109 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1110 | default: |
1111 | pc += 4; | |
c906108c SS |
1112 | } |
1113 | } | |
6d82d43b | 1114 | break; /* end REGIMM */ |
c5aa993b JM |
1115 | case 2: /* J */ |
1116 | case 3: /* JAL */ | |
1117 | { | |
1118 | unsigned long reg; | |
1119 | reg = jtype_target (inst) << 2; | |
e135b889 | 1120 | /* Upper four bits get never changed... */ |
5b652102 | 1121 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1122 | } |
c5aa993b JM |
1123 | break; |
1124 | /* FIXME case JALX : */ | |
1125 | { | |
1126 | unsigned long reg; | |
1127 | reg = jtype_target (inst) << 2; | |
5b652102 | 1128 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ |
c906108c SS |
1129 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1130 | } | |
c5aa993b | 1131 | break; /* The new PC will be alternate mode */ |
e135b889 | 1132 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1133 | equal_branch: |
6c997a34 AC |
1134 | if (read_signed_register (itype_rs (inst)) == |
1135 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1136 | pc += mips32_relative_offset (inst) + 4; |
1137 | else | |
1138 | pc += 8; | |
1139 | break; | |
e135b889 | 1140 | case 5: /* BNE, BNEL */ |
c5aa993b | 1141 | neq_branch: |
6c997a34 | 1142 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1143 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1144 | pc += mips32_relative_offset (inst) + 4; |
1145 | else | |
1146 | pc += 8; | |
1147 | break; | |
e135b889 | 1148 | case 6: /* BLEZ, BLEZL */ |
1fd8cd20 | 1149 | if (read_signed_register (itype_rs (inst)) <= 0) |
c5aa993b JM |
1150 | pc += mips32_relative_offset (inst) + 4; |
1151 | else | |
1152 | pc += 8; | |
1153 | break; | |
1154 | case 7: | |
e135b889 DJ |
1155 | default: |
1156 | greater_branch: /* BGTZ, BGTZL */ | |
1fd8cd20 | 1157 | if (read_signed_register (itype_rs (inst)) > 0) |
c5aa993b JM |
1158 | pc += mips32_relative_offset (inst) + 4; |
1159 | else | |
1160 | pc += 8; | |
1161 | break; | |
c5aa993b JM |
1162 | } /* switch */ |
1163 | } /* else */ | |
1164 | return pc; | |
1165 | } /* mips32_next_pc */ | |
c906108c SS |
1166 | |
1167 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1168 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1169 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1170 | We dont want to set a single step instruction on the extend instruction | |
1171 | either. | |
c5aa993b | 1172 | */ |
c906108c SS |
1173 | |
1174 | /* Lots of mips16 instruction formats */ | |
1175 | /* Predicting jumps requires itype,ritype,i8type | |
1176 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1177 | */ |
c906108c SS |
1178 | enum mips16_inst_fmts |
1179 | { | |
c5aa993b JM |
1180 | itype, /* 0 immediate 5,10 */ |
1181 | ritype, /* 1 5,3,8 */ | |
1182 | rrtype, /* 2 5,3,3,5 */ | |
1183 | rritype, /* 3 5,3,3,5 */ | |
1184 | rrrtype, /* 4 5,3,3,3,2 */ | |
1185 | rriatype, /* 5 5,3,3,1,4 */ | |
1186 | shifttype, /* 6 5,3,3,3,2 */ | |
1187 | i8type, /* 7 5,3,8 */ | |
1188 | i8movtype, /* 8 5,3,3,5 */ | |
1189 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1190 | i64type, /* 10 5,3,8 */ | |
1191 | ri64type, /* 11 5,3,3,5 */ | |
1192 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1193 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1194 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1195 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1196 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1197 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1198 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1199 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1200 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1201 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1202 | }; | |
12f02c2a AC |
1203 | /* I am heaping all the fields of the formats into one structure and |
1204 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1205 | struct upk_mips16 |
6d82d43b AC |
1206 | { |
1207 | CORE_ADDR offset; | |
1208 | unsigned int regx; /* Function in i8 type */ | |
1209 | unsigned int regy; | |
1210 | }; | |
c906108c SS |
1211 | |
1212 | ||
12f02c2a AC |
1213 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1214 | for the bits which make up the immediatate extension. */ | |
c906108c | 1215 | |
12f02c2a AC |
1216 | static CORE_ADDR |
1217 | extended_offset (unsigned int extension) | |
c906108c | 1218 | { |
12f02c2a | 1219 | CORE_ADDR value; |
c5aa993b JM |
1220 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1221 | value = value << 6; | |
1222 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1223 | value = value << 5; | |
1224 | value |= extension & 0x01f; /* extract 4:0 */ | |
1225 | return value; | |
c906108c SS |
1226 | } |
1227 | ||
1228 | /* Only call this function if you know that this is an extendable | |
1229 | instruction, It wont malfunction, but why make excess remote memory references? | |
1230 | If the immediate operands get sign extended or somthing, do it after | |
1231 | the extension is performed. | |
c5aa993b | 1232 | */ |
c906108c SS |
1233 | /* FIXME: Every one of these cases needs to worry about sign extension |
1234 | when the offset is to be used in relative addressing */ | |
1235 | ||
1236 | ||
12f02c2a | 1237 | static unsigned int |
c5aa993b | 1238 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1239 | { |
47a35522 | 1240 | gdb_byte buf[8]; |
c5aa993b JM |
1241 | pc &= 0xfffffffe; /* clear the low order bit */ |
1242 | target_read_memory (pc, buf, 2); | |
1243 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1244 | } |
1245 | ||
1246 | static void | |
c5aa993b | 1247 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1248 | unsigned int extension, |
1249 | unsigned int inst, | |
6d82d43b | 1250 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1251 | { |
12f02c2a AC |
1252 | CORE_ADDR offset; |
1253 | int regx; | |
1254 | int regy; | |
1255 | switch (insn_format) | |
c906108c | 1256 | { |
c5aa993b | 1257 | case itype: |
c906108c | 1258 | { |
12f02c2a AC |
1259 | CORE_ADDR value; |
1260 | if (extension) | |
c5aa993b JM |
1261 | { |
1262 | value = extended_offset (extension); | |
1263 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1264 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1265 | } |
1266 | else | |
c5aa993b | 1267 | { |
12f02c2a | 1268 | value = inst & 0x7ff; |
c5aa993b | 1269 | /* FIXME : Consider sign extension */ |
c906108c | 1270 | } |
12f02c2a AC |
1271 | offset = value; |
1272 | regx = -1; | |
1273 | regy = -1; | |
c906108c | 1274 | } |
c5aa993b JM |
1275 | break; |
1276 | case ritype: | |
1277 | case i8type: | |
1278 | { /* A register identifier and an offset */ | |
c906108c SS |
1279 | /* Most of the fields are the same as I type but the |
1280 | immediate value is of a different length */ | |
12f02c2a AC |
1281 | CORE_ADDR value; |
1282 | if (extension) | |
c906108c | 1283 | { |
c5aa993b JM |
1284 | value = extended_offset (extension); |
1285 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1286 | value |= inst & 0xff; /* eleven bits from instruction */ |
1287 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1288 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1289 | { | |
1290 | value &= ~0x3fff; /* remove the sign bit */ | |
1291 | value = -value; | |
c906108c SS |
1292 | } |
1293 | } | |
c5aa993b JM |
1294 | else |
1295 | { | |
12f02c2a AC |
1296 | value = inst & 0xff; /* 8 bits */ |
1297 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1298 | /* FIXME: Do sign extension , this format needs it */ |
1299 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1300 | { | |
1301 | value &= 0xef; /* remove the sign bit */ | |
1302 | value = -value; | |
1303 | } | |
c5aa993b | 1304 | } |
12f02c2a AC |
1305 | offset = value; |
1306 | regy = -1; | |
c5aa993b | 1307 | break; |
c906108c | 1308 | } |
c5aa993b | 1309 | case jalxtype: |
c906108c | 1310 | { |
c5aa993b | 1311 | unsigned long value; |
12f02c2a AC |
1312 | unsigned int nexthalf; |
1313 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1314 | value = value << 16; |
1315 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1316 | value |= nexthalf; | |
12f02c2a AC |
1317 | offset = value; |
1318 | regx = -1; | |
1319 | regy = -1; | |
c5aa993b | 1320 | break; |
c906108c SS |
1321 | } |
1322 | default: | |
e2e0b3e5 | 1323 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1324 | } |
12f02c2a AC |
1325 | upk->offset = offset; |
1326 | upk->regx = regx; | |
1327 | upk->regy = regy; | |
c906108c SS |
1328 | } |
1329 | ||
1330 | ||
c5aa993b JM |
1331 | static CORE_ADDR |
1332 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1333 | { |
5b652102 | 1334 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
1335 | } |
1336 | ||
12f02c2a AC |
1337 | static CORE_ADDR |
1338 | extended_mips16_next_pc (CORE_ADDR pc, | |
6d82d43b | 1339 | unsigned int extension, unsigned int insn) |
c906108c | 1340 | { |
12f02c2a AC |
1341 | int op = (insn >> 11); |
1342 | switch (op) | |
c906108c | 1343 | { |
6d82d43b | 1344 | case 2: /* Branch */ |
12f02c2a AC |
1345 | { |
1346 | CORE_ADDR offset; | |
1347 | struct upk_mips16 upk; | |
1348 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1349 | offset = upk.offset; | |
1350 | if (offset & 0x800) | |
1351 | { | |
1352 | offset &= 0xeff; | |
1353 | offset = -offset; | |
1354 | } | |
1355 | pc += (offset << 1) + 2; | |
1356 | break; | |
1357 | } | |
6d82d43b | 1358 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1359 | { |
1360 | struct upk_mips16 upk; | |
1361 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1362 | pc = add_offset_16 (pc, upk.offset); | |
1363 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1364 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1365 | else | |
1366 | pc |= 0x01; | |
1367 | break; | |
1368 | } | |
6d82d43b | 1369 | case 4: /* beqz */ |
12f02c2a AC |
1370 | { |
1371 | struct upk_mips16 upk; | |
1372 | int reg; | |
1373 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1374 | reg = read_signed_register (upk.regx); | |
1375 | if (reg == 0) | |
1376 | pc += (upk.offset << 1) + 2; | |
1377 | else | |
1378 | pc += 2; | |
1379 | break; | |
1380 | } | |
6d82d43b | 1381 | case 5: /* bnez */ |
12f02c2a AC |
1382 | { |
1383 | struct upk_mips16 upk; | |
1384 | int reg; | |
1385 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1386 | reg = read_signed_register (upk.regx); | |
1387 | if (reg != 0) | |
1388 | pc += (upk.offset << 1) + 2; | |
1389 | else | |
1390 | pc += 2; | |
1391 | break; | |
1392 | } | |
6d82d43b | 1393 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1394 | { |
1395 | struct upk_mips16 upk; | |
1396 | int reg; | |
1397 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1398 | /* upk.regx contains the opcode */ | |
1399 | reg = read_signed_register (24); /* Test register is 24 */ | |
1400 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1401 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1402 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1403 | pc += (upk.offset << 1) + 2; | |
1404 | else | |
1405 | pc += 2; | |
1406 | break; | |
1407 | } | |
6d82d43b | 1408 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1409 | { |
1410 | struct upk_mips16 upk; | |
1411 | /* upk.fmt = rrtype; */ | |
1412 | op = insn & 0x1f; | |
1413 | if (op == 0) | |
c5aa993b | 1414 | { |
12f02c2a AC |
1415 | int reg; |
1416 | upk.regx = (insn >> 8) & 0x07; | |
1417 | upk.regy = (insn >> 5) & 0x07; | |
1418 | switch (upk.regy) | |
c5aa993b | 1419 | { |
12f02c2a AC |
1420 | case 0: |
1421 | reg = upk.regx; | |
1422 | break; | |
1423 | case 1: | |
1424 | reg = 31; | |
6d82d43b | 1425 | break; /* Function return instruction */ |
12f02c2a AC |
1426 | case 2: |
1427 | reg = upk.regx; | |
1428 | break; | |
1429 | default: | |
1430 | reg = 31; | |
6d82d43b | 1431 | break; /* BOGUS Guess */ |
c906108c | 1432 | } |
12f02c2a | 1433 | pc = read_signed_register (reg); |
c906108c | 1434 | } |
12f02c2a | 1435 | else |
c5aa993b | 1436 | pc += 2; |
12f02c2a AC |
1437 | break; |
1438 | } | |
1439 | case 30: | |
1440 | /* This is an instruction extension. Fetch the real instruction | |
1441 | (which follows the extension) and decode things based on | |
1442 | that. */ | |
1443 | { | |
1444 | pc += 2; | |
1445 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1446 | break; | |
1447 | } | |
1448 | default: | |
1449 | { | |
1450 | pc += 2; | |
1451 | break; | |
1452 | } | |
c906108c | 1453 | } |
c5aa993b | 1454 | return pc; |
12f02c2a | 1455 | } |
c906108c | 1456 | |
5a89d8aa | 1457 | static CORE_ADDR |
12f02c2a AC |
1458 | mips16_next_pc (CORE_ADDR pc) |
1459 | { | |
1460 | unsigned int insn = fetch_mips_16 (pc); | |
1461 | return extended_mips16_next_pc (pc, 0, insn); | |
1462 | } | |
1463 | ||
1464 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1465 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1466 | It works by decoding the current instruction and predicting where a |
1467 | branch will go. This isnt hard because all the data is available. | |
1468 | The MIPS32 and MIPS16 variants are quite different */ | |
ad527d2e | 1469 | static CORE_ADDR |
c5aa993b | 1470 | mips_next_pc (CORE_ADDR pc) |
c906108c | 1471 | { |
c5aa993b JM |
1472 | if (pc & 0x01) |
1473 | return mips16_next_pc (pc); | |
1474 | else | |
1475 | return mips32_next_pc (pc); | |
12f02c2a | 1476 | } |
c906108c | 1477 | |
edfae063 AC |
1478 | struct mips_frame_cache |
1479 | { | |
1480 | CORE_ADDR base; | |
1481 | struct trad_frame_saved_reg *saved_regs; | |
1482 | }; | |
1483 | ||
29639122 JB |
1484 | /* Set a register's saved stack address in temp_saved_regs. If an |
1485 | address has already been set for this register, do nothing; this | |
1486 | way we will only recognize the first save of a given register in a | |
1487 | function prologue. | |
eec63939 | 1488 | |
f57d151a UW |
1489 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
1490 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
1491 | Strictly speaking, only the second range is used as it is only second | |
1492 | range (the ABI instead of ISA registers) that comes into play when finding | |
1493 | saved registers in a frame. */ | |
eec63939 AC |
1494 | |
1495 | static void | |
29639122 JB |
1496 | set_reg_offset (struct mips_frame_cache *this_cache, int regnum, |
1497 | CORE_ADDR offset) | |
eec63939 | 1498 | { |
29639122 JB |
1499 | if (this_cache != NULL |
1500 | && this_cache->saved_regs[regnum].addr == -1) | |
1501 | { | |
f57d151a UW |
1502 | this_cache->saved_regs[regnum |
1503 | + 0 * gdbarch_num_regs (current_gdbarch)].addr | |
1504 | = offset; | |
1505 | this_cache->saved_regs[regnum | |
1506 | + 1 * gdbarch_num_regs (current_gdbarch)].addr | |
1507 | = offset; | |
29639122 | 1508 | } |
eec63939 AC |
1509 | } |
1510 | ||
eec63939 | 1511 | |
29639122 JB |
1512 | /* Fetch the immediate value from a MIPS16 instruction. |
1513 | If the previous instruction was an EXTEND, use it to extend | |
1514 | the upper bits of the immediate value. This is a helper function | |
1515 | for mips16_scan_prologue. */ | |
eec63939 | 1516 | |
29639122 JB |
1517 | static int |
1518 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1519 | unsigned short inst, /* current instruction */ | |
1520 | int nbits, /* number of bits in imm field */ | |
1521 | int scale, /* scale factor to be applied to imm */ | |
1522 | int is_signed) /* is the imm field signed? */ | |
eec63939 | 1523 | { |
29639122 | 1524 | int offset; |
eec63939 | 1525 | |
29639122 JB |
1526 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1527 | { | |
1528 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1529 | if (offset & 0x8000) /* check for negative extend */ | |
1530 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1531 | return offset | (inst & 0x1f); | |
1532 | } | |
eec63939 | 1533 | else |
29639122 JB |
1534 | { |
1535 | int max_imm = 1 << nbits; | |
1536 | int mask = max_imm - 1; | |
1537 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1538 | |
29639122 JB |
1539 | offset = inst & mask; |
1540 | if (is_signed && (offset & sign_bit)) | |
1541 | offset = 0 - (max_imm - offset); | |
1542 | return offset * scale; | |
1543 | } | |
1544 | } | |
eec63939 | 1545 | |
65596487 | 1546 | |
29639122 JB |
1547 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1548 | the associated FRAME_CACHE if not null. | |
1549 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1550 | |
29639122 JB |
1551 | static CORE_ADDR |
1552 | mips16_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
1553 | struct frame_info *next_frame, | |
1554 | struct mips_frame_cache *this_cache) | |
1555 | { | |
1556 | CORE_ADDR cur_pc; | |
1557 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1558 | CORE_ADDR sp; | |
1559 | long frame_offset = 0; /* Size of stack frame. */ | |
1560 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1561 | int frame_reg = MIPS_SP_REGNUM; | |
1562 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1563 | unsigned inst = 0; /* current instruction */ | |
1564 | unsigned entry_inst = 0; /* the entry instruction */ | |
1565 | int reg, offset; | |
a343eb3c | 1566 | |
29639122 JB |
1567 | int extend_bytes = 0; |
1568 | int prev_extend_bytes; | |
1569 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 1570 | |
29639122 JB |
1571 | /* Can be called when there's no process, and hence when there's no |
1572 | NEXT_FRAME. */ | |
1573 | if (next_frame != NULL) | |
f57d151a UW |
1574 | sp = read_next_frame_reg (next_frame, gdbarch_num_regs (current_gdbarch) |
1575 | + MIPS_SP_REGNUM); | |
29639122 JB |
1576 | else |
1577 | sp = 0; | |
eec63939 | 1578 | |
29639122 JB |
1579 | if (limit_pc > start_pc + 200) |
1580 | limit_pc = start_pc + 200; | |
eec63939 | 1581 | |
95ac2dcf | 1582 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1583 | { |
1584 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1585 | the immediate offset extension from it in mips16_get_imm. */ | |
1586 | prev_inst = inst; | |
eec63939 | 1587 | |
29639122 JB |
1588 | /* Fetch and decode the instruction. */ |
1589 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
eec63939 | 1590 | |
29639122 JB |
1591 | /* Normally we ignore extend instructions. However, if it is |
1592 | not followed by a valid prologue instruction, then this | |
1593 | instruction is not part of the prologue either. We must | |
1594 | remember in this case to adjust the end_prologue_addr back | |
1595 | over the extend. */ | |
1596 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1597 | { | |
95ac2dcf | 1598 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1599 | continue; |
1600 | } | |
eec63939 | 1601 | |
29639122 JB |
1602 | prev_extend_bytes = extend_bytes; |
1603 | extend_bytes = 0; | |
eec63939 | 1604 | |
29639122 JB |
1605 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1606 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1607 | { | |
1608 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
1609 | if (offset < 0) /* negative stack adjustment? */ | |
1610 | frame_offset -= offset; | |
1611 | else | |
1612 | /* Exit loop if a positive stack adjustment is found, which | |
1613 | usually means that the stack cleanup code in the function | |
1614 | epilogue is reached. */ | |
1615 | break; | |
1616 | } | |
1617 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1618 | { | |
1619 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1620 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
1621 | set_reg_offset (this_cache, reg, sp + offset); | |
1622 | } | |
1623 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1624 | { | |
1625 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1626 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1627 | set_reg_offset (this_cache, reg, sp + offset); | |
1628 | } | |
1629 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1630 | { | |
1631 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4c7d22cb | 1632 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1633 | } |
1634 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1635 | { | |
1636 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
4c7d22cb | 1637 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1638 | } |
1639 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1640 | { | |
1641 | frame_addr = sp; | |
1642 | frame_reg = 17; | |
1643 | } | |
1644 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1645 | { | |
1646 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1647 | frame_addr = sp + offset; | |
1648 | frame_reg = 17; | |
1649 | frame_adjust = offset; | |
1650 | } | |
1651 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1652 | { | |
1653 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1654 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1655 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1656 | } | |
1657 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1658 | { | |
1659 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1660 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1661 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1662 | } | |
1663 | else if ((inst & 0xf81f) == 0xe809 | |
1664 | && (inst & 0x700) != 0x700) /* entry */ | |
1665 | entry_inst = inst; /* save for later processing */ | |
1666 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ | |
95ac2dcf | 1667 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1668 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1669 | { | |
1670 | /* This instruction is part of the prologue, but we don't | |
1671 | need to do anything special to handle it. */ | |
1672 | } | |
1673 | else | |
1674 | { | |
1675 | /* This instruction is not an instruction typically found | |
1676 | in a prologue, so we must have reached the end of the | |
1677 | prologue. */ | |
1678 | if (end_prologue_addr == 0) | |
1679 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1680 | } | |
1681 | } | |
eec63939 | 1682 | |
29639122 JB |
1683 | /* The entry instruction is typically the first instruction in a function, |
1684 | and it stores registers at offsets relative to the value of the old SP | |
1685 | (before the prologue). But the value of the sp parameter to this | |
1686 | function is the new SP (after the prologue has been executed). So we | |
1687 | can't calculate those offsets until we've seen the entire prologue, | |
1688 | and can calculate what the old SP must have been. */ | |
1689 | if (entry_inst != 0) | |
1690 | { | |
1691 | int areg_count = (entry_inst >> 8) & 7; | |
1692 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1693 | |
29639122 JB |
1694 | /* The entry instruction always subtracts 32 from the SP. */ |
1695 | frame_offset += 32; | |
1696 | ||
1697 | /* Now we can calculate what the SP must have been at the | |
1698 | start of the function prologue. */ | |
1699 | sp += frame_offset; | |
1700 | ||
1701 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1702 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1703 | { | |
1704 | set_reg_offset (this_cache, reg, sp + offset); | |
1705 | offset += mips_abi_regsize (current_gdbarch); | |
1706 | } | |
1707 | ||
1708 | /* Check if the ra register was pushed on the stack. */ | |
1709 | offset = -4; | |
1710 | if (entry_inst & 0x20) | |
1711 | { | |
4c7d22cb | 1712 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1713 | offset -= mips_abi_regsize (current_gdbarch); |
1714 | } | |
1715 | ||
1716 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1717 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1718 | { | |
1719 | set_reg_offset (this_cache, reg, sp + offset); | |
1720 | offset -= mips_abi_regsize (current_gdbarch); | |
1721 | } | |
1722 | } | |
1723 | ||
1724 | if (this_cache != NULL) | |
1725 | { | |
1726 | this_cache->base = | |
f57d151a UW |
1727 | (frame_unwind_register_signed (next_frame, |
1728 | gdbarch_num_regs (current_gdbarch) | |
1729 | + frame_reg) | |
29639122 JB |
1730 | + frame_offset - frame_adjust); |
1731 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
1732 | be able to get rid of the assignment below, evetually. But it's | |
1733 | still needed for now. */ | |
f57d151a UW |
1734 | this_cache->saved_regs[gdbarch_num_regs (current_gdbarch) |
1735 | + mips_regnum (current_gdbarch)->pc] | |
1736 | = this_cache->saved_regs[gdbarch_num_regs (current_gdbarch) | |
1737 | + MIPS_RA_REGNUM]; | |
29639122 JB |
1738 | } |
1739 | ||
1740 | /* If we didn't reach the end of the prologue when scanning the function | |
1741 | instructions, then set end_prologue_addr to the address of the | |
1742 | instruction immediately after the last one we scanned. */ | |
1743 | if (end_prologue_addr == 0) | |
1744 | end_prologue_addr = cur_pc; | |
1745 | ||
1746 | return end_prologue_addr; | |
eec63939 AC |
1747 | } |
1748 | ||
29639122 JB |
1749 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1750 | Procedures that use the 32-bit instruction set are handled by the | |
1751 | mips_insn32 unwinder. */ | |
1752 | ||
1753 | static struct mips_frame_cache * | |
1754 | mips_insn16_frame_cache (struct frame_info *next_frame, void **this_cache) | |
eec63939 | 1755 | { |
29639122 | 1756 | struct mips_frame_cache *cache; |
eec63939 AC |
1757 | |
1758 | if ((*this_cache) != NULL) | |
1759 | return (*this_cache); | |
29639122 JB |
1760 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1761 | (*this_cache) = cache; | |
1762 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
eec63939 | 1763 | |
29639122 JB |
1764 | /* Analyze the function prologue. */ |
1765 | { | |
6de5b849 JB |
1766 | const CORE_ADDR pc = |
1767 | frame_unwind_address_in_block (next_frame, NORMAL_FRAME); | |
29639122 | 1768 | CORE_ADDR start_addr; |
eec63939 | 1769 | |
29639122 JB |
1770 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1771 | if (start_addr == 0) | |
1772 | start_addr = heuristic_proc_start (pc); | |
1773 | /* We can't analyze the prologue if we couldn't find the begining | |
1774 | of the function. */ | |
1775 | if (start_addr == 0) | |
1776 | return cache; | |
eec63939 | 1777 | |
29639122 JB |
1778 | mips16_scan_prologue (start_addr, pc, next_frame, *this_cache); |
1779 | } | |
1780 | ||
1781 | /* SP_REGNUM, contains the value and not the address. */ | |
f57d151a UW |
1782 | trad_frame_set_value (cache->saved_regs, gdbarch_num_regs (current_gdbarch) |
1783 | + MIPS_SP_REGNUM, cache->base); | |
eec63939 | 1784 | |
29639122 | 1785 | return (*this_cache); |
eec63939 AC |
1786 | } |
1787 | ||
1788 | static void | |
29639122 JB |
1789 | mips_insn16_frame_this_id (struct frame_info *next_frame, void **this_cache, |
1790 | struct frame_id *this_id) | |
eec63939 | 1791 | { |
29639122 JB |
1792 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1793 | this_cache); | |
93d42b30 DJ |
1794 | (*this_id) = frame_id_build (info->base, |
1795 | frame_func_unwind (next_frame, NORMAL_FRAME)); | |
eec63939 AC |
1796 | } |
1797 | ||
1798 | static void | |
29639122 | 1799 | mips_insn16_frame_prev_register (struct frame_info *next_frame, |
eec63939 AC |
1800 | void **this_cache, |
1801 | int regnum, int *optimizedp, | |
1802 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 1803 | int *realnump, gdb_byte *valuep) |
eec63939 | 1804 | { |
29639122 JB |
1805 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1806 | this_cache); | |
1807 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
1808 | optimizedp, lvalp, addrp, realnump, valuep); | |
eec63939 AC |
1809 | } |
1810 | ||
29639122 | 1811 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
1812 | { |
1813 | NORMAL_FRAME, | |
29639122 JB |
1814 | mips_insn16_frame_this_id, |
1815 | mips_insn16_frame_prev_register | |
eec63939 AC |
1816 | }; |
1817 | ||
1818 | static const struct frame_unwind * | |
29639122 | 1819 | mips_insn16_frame_sniffer (struct frame_info *next_frame) |
eec63939 | 1820 | { |
6de5b849 | 1821 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
0fe7e7c8 | 1822 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
1823 | return &mips_insn16_frame_unwind; |
1824 | return NULL; | |
eec63939 AC |
1825 | } |
1826 | ||
1827 | static CORE_ADDR | |
29639122 JB |
1828 | mips_insn16_frame_base_address (struct frame_info *next_frame, |
1829 | void **this_cache) | |
eec63939 | 1830 | { |
29639122 JB |
1831 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1832 | this_cache); | |
1833 | return info->base; | |
eec63939 AC |
1834 | } |
1835 | ||
29639122 | 1836 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 1837 | { |
29639122 JB |
1838 | &mips_insn16_frame_unwind, |
1839 | mips_insn16_frame_base_address, | |
1840 | mips_insn16_frame_base_address, | |
1841 | mips_insn16_frame_base_address | |
eec63939 AC |
1842 | }; |
1843 | ||
1844 | static const struct frame_base * | |
29639122 | 1845 | mips_insn16_frame_base_sniffer (struct frame_info *next_frame) |
eec63939 | 1846 | { |
29639122 JB |
1847 | if (mips_insn16_frame_sniffer (next_frame) != NULL) |
1848 | return &mips_insn16_frame_base; | |
eec63939 AC |
1849 | else |
1850 | return NULL; | |
edfae063 AC |
1851 | } |
1852 | ||
29639122 JB |
1853 | /* Mark all the registers as unset in the saved_regs array |
1854 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
1855 | ||
1856 | void | |
1857 | reset_saved_regs (struct mips_frame_cache *this_cache) | |
c906108c | 1858 | { |
29639122 JB |
1859 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
1860 | return; | |
1861 | ||
1862 | { | |
f57d151a | 1863 | const int num_regs = gdbarch_num_regs (current_gdbarch); |
29639122 | 1864 | int i; |
64159455 | 1865 | |
29639122 JB |
1866 | for (i = 0; i < num_regs; i++) |
1867 | { | |
1868 | this_cache->saved_regs[i].addr = -1; | |
1869 | } | |
1870 | } | |
c906108c SS |
1871 | } |
1872 | ||
29639122 JB |
1873 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1874 | the associated FRAME_CACHE if not null. | |
1875 | Return the address of the first instruction past the prologue. */ | |
c906108c | 1876 | |
875e1767 | 1877 | static CORE_ADDR |
29639122 JB |
1878 | mips32_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1879 | struct frame_info *next_frame, | |
1880 | struct mips_frame_cache *this_cache) | |
c906108c | 1881 | { |
29639122 JB |
1882 | CORE_ADDR cur_pc; |
1883 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
1884 | CORE_ADDR sp; | |
1885 | long frame_offset; | |
1886 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 1887 | |
29639122 JB |
1888 | CORE_ADDR end_prologue_addr = 0; |
1889 | int seen_sp_adjust = 0; | |
1890 | int load_immediate_bytes = 0; | |
8fa9cfa1 | 1891 | |
29639122 JB |
1892 | /* Can be called when there's no process, and hence when there's no |
1893 | NEXT_FRAME. */ | |
1894 | if (next_frame != NULL) | |
f57d151a UW |
1895 | sp = read_next_frame_reg (next_frame, gdbarch_num_regs (current_gdbarch) |
1896 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 1897 | else |
29639122 | 1898 | sp = 0; |
9022177c | 1899 | |
29639122 JB |
1900 | if (limit_pc > start_pc + 200) |
1901 | limit_pc = start_pc + 200; | |
9022177c | 1902 | |
29639122 | 1903 | restart: |
9022177c | 1904 | |
29639122 | 1905 | frame_offset = 0; |
95ac2dcf | 1906 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 1907 | { |
29639122 JB |
1908 | unsigned long inst, high_word, low_word; |
1909 | int reg; | |
9022177c | 1910 | |
29639122 JB |
1911 | /* Fetch the instruction. */ |
1912 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
9022177c | 1913 | |
29639122 JB |
1914 | /* Save some code by pre-extracting some useful fields. */ |
1915 | high_word = (inst >> 16) & 0xffff; | |
1916 | low_word = inst & 0xffff; | |
1917 | reg = high_word & 0x1f; | |
fe29b929 | 1918 | |
29639122 JB |
1919 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
1920 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
1921 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1922 | { | |
1923 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
1924 | frame_offset += 0x10000 - low_word; | |
1925 | else | |
1926 | /* Exit loop if a positive stack adjustment is found, which | |
1927 | usually means that the stack cleanup code in the function | |
1928 | epilogue is reached. */ | |
1929 | break; | |
1930 | seen_sp_adjust = 1; | |
1931 | } | |
1932 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
1933 | { | |
1934 | set_reg_offset (this_cache, reg, sp + low_word); | |
1935 | } | |
1936 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
1937 | { | |
1938 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
1939 | set_reg_offset (this_cache, reg, sp + low_word); | |
1940 | } | |
1941 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
1942 | { | |
1943 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
1944 | if ((long) low_word != frame_offset) | |
1945 | frame_addr = sp + low_word; | |
1946 | else if (frame_reg == MIPS_SP_REGNUM) | |
1947 | { | |
1948 | unsigned alloca_adjust; | |
a4b8ebc8 | 1949 | |
29639122 | 1950 | frame_reg = 30; |
f57d151a UW |
1951 | frame_addr = read_next_frame_reg (next_frame, |
1952 | gdbarch_num_regs | |
1953 | (current_gdbarch) + 30); | |
29639122 JB |
1954 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
1955 | if (alloca_adjust > 0) | |
1956 | { | |
1957 | /* FP > SP + frame_size. This may be because of | |
1958 | an alloca or somethings similar. Fix sp to | |
1959 | "pre-alloca" value, and try again. */ | |
1960 | sp += alloca_adjust; | |
1961 | /* Need to reset the status of all registers. Otherwise, | |
1962 | we will hit a guard that prevents the new address | |
1963 | for each register to be recomputed during the second | |
1964 | pass. */ | |
1965 | reset_saved_regs (this_cache); | |
1966 | goto restart; | |
1967 | } | |
1968 | } | |
1969 | } | |
1970 | /* move $30,$sp. With different versions of gas this will be either | |
1971 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
1972 | Accept any one of these. */ | |
1973 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
1974 | { | |
1975 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
1976 | if (frame_reg == MIPS_SP_REGNUM) | |
1977 | { | |
1978 | unsigned alloca_adjust; | |
c906108c | 1979 | |
29639122 | 1980 | frame_reg = 30; |
f57d151a UW |
1981 | frame_addr = read_next_frame_reg (next_frame, |
1982 | gdbarch_num_regs | |
1983 | (current_gdbarch) + 30); | |
29639122 JB |
1984 | alloca_adjust = (unsigned) (frame_addr - sp); |
1985 | if (alloca_adjust > 0) | |
1986 | { | |
1987 | /* FP > SP + frame_size. This may be because of | |
1988 | an alloca or somethings similar. Fix sp to | |
1989 | "pre-alloca" value, and try again. */ | |
1990 | sp = frame_addr; | |
1991 | /* Need to reset the status of all registers. Otherwise, | |
1992 | we will hit a guard that prevents the new address | |
1993 | for each register to be recomputed during the second | |
1994 | pass. */ | |
1995 | reset_saved_regs (this_cache); | |
1996 | goto restart; | |
1997 | } | |
1998 | } | |
1999 | } | |
2000 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ | |
2001 | { | |
2002 | set_reg_offset (this_cache, reg, frame_addr + low_word); | |
2003 | } | |
2004 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
2005 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
2006 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
2007 | || high_word == 0x3c1c /* lui $gp,n */ | |
2008 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
2009 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
2010 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
2011 | ) | |
2012 | { | |
2013 | /* These instructions are part of the prologue, but we don't | |
2014 | need to do anything special to handle them. */ | |
2015 | } | |
2016 | /* The instructions below load $at or $t0 with an immediate | |
2017 | value in preparation for a stack adjustment via | |
2018 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
2019 | initialize a local variable, so we accept them only before | |
2020 | a stack adjustment instruction was seen. */ | |
2021 | else if (!seen_sp_adjust | |
2022 | && (high_word == 0x3c01 /* lui $at,n */ | |
2023 | || high_word == 0x3c08 /* lui $t0,n */ | |
2024 | || high_word == 0x3421 /* ori $at,$at,n */ | |
2025 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
2026 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
2027 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
2028 | )) | |
2029 | { | |
95ac2dcf | 2030 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
29639122 JB |
2031 | } |
2032 | else | |
2033 | { | |
2034 | /* This instruction is not an instruction typically found | |
2035 | in a prologue, so we must have reached the end of the | |
2036 | prologue. */ | |
2037 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
2038 | loop now? Why would we need to continue scanning the function | |
2039 | instructions? */ | |
2040 | if (end_prologue_addr == 0) | |
2041 | end_prologue_addr = cur_pc; | |
2042 | } | |
a4b8ebc8 | 2043 | } |
c906108c | 2044 | |
29639122 JB |
2045 | if (this_cache != NULL) |
2046 | { | |
2047 | this_cache->base = | |
f57d151a UW |
2048 | (frame_unwind_register_signed (next_frame, |
2049 | gdbarch_num_regs (current_gdbarch) | |
2050 | + frame_reg) | |
29639122 JB |
2051 | + frame_offset); |
2052 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2053 | this assignment below, eventually. But it's still needed | |
2054 | for now. */ | |
f57d151a UW |
2055 | this_cache->saved_regs[gdbarch_num_regs (current_gdbarch) |
2056 | + mips_regnum (current_gdbarch)->pc] | |
2057 | = this_cache->saved_regs[gdbarch_num_regs (current_gdbarch) | |
2058 | + MIPS_RA_REGNUM]; | |
29639122 | 2059 | } |
c906108c | 2060 | |
29639122 JB |
2061 | /* If we didn't reach the end of the prologue when scanning the function |
2062 | instructions, then set end_prologue_addr to the address of the | |
2063 | instruction immediately after the last one we scanned. */ | |
2064 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2065 | we may as well be careful and do our best if we have a null | |
2066 | end_prologue_addr. */ | |
2067 | if (end_prologue_addr == 0) | |
2068 | end_prologue_addr = cur_pc; | |
2069 | ||
2070 | /* In a frameless function, we might have incorrectly | |
2071 | skipped some load immediate instructions. Undo the skipping | |
2072 | if the load immediate was not followed by a stack adjustment. */ | |
2073 | if (load_immediate_bytes && !seen_sp_adjust) | |
2074 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2075 | |
29639122 | 2076 | return end_prologue_addr; |
c906108c SS |
2077 | } |
2078 | ||
29639122 JB |
2079 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2080 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2081 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2082 | unwinder. */ | |
c906108c | 2083 | |
29639122 JB |
2084 | static struct mips_frame_cache * |
2085 | mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache) | |
c906108c | 2086 | { |
29639122 | 2087 | struct mips_frame_cache *cache; |
c906108c | 2088 | |
29639122 JB |
2089 | if ((*this_cache) != NULL) |
2090 | return (*this_cache); | |
c5aa993b | 2091 | |
29639122 JB |
2092 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2093 | (*this_cache) = cache; | |
2094 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
c5aa993b | 2095 | |
29639122 JB |
2096 | /* Analyze the function prologue. */ |
2097 | { | |
6de5b849 JB |
2098 | const CORE_ADDR pc = |
2099 | frame_unwind_address_in_block (next_frame, NORMAL_FRAME); | |
29639122 | 2100 | CORE_ADDR start_addr; |
c906108c | 2101 | |
29639122 JB |
2102 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2103 | if (start_addr == 0) | |
2104 | start_addr = heuristic_proc_start (pc); | |
2105 | /* We can't analyze the prologue if we couldn't find the begining | |
2106 | of the function. */ | |
2107 | if (start_addr == 0) | |
2108 | return cache; | |
c5aa993b | 2109 | |
29639122 JB |
2110 | mips32_scan_prologue (start_addr, pc, next_frame, *this_cache); |
2111 | } | |
2112 | ||
2113 | /* SP_REGNUM, contains the value and not the address. */ | |
f57d151a UW |
2114 | trad_frame_set_value (cache->saved_regs, |
2115 | gdbarch_num_regs (current_gdbarch) + MIPS_SP_REGNUM, | |
2116 | cache->base); | |
c5aa993b | 2117 | |
29639122 | 2118 | return (*this_cache); |
c906108c SS |
2119 | } |
2120 | ||
29639122 JB |
2121 | static void |
2122 | mips_insn32_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2123 | struct frame_id *this_id) | |
c906108c | 2124 | { |
29639122 JB |
2125 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
2126 | this_cache); | |
93d42b30 DJ |
2127 | (*this_id) = frame_id_build (info->base, |
2128 | frame_func_unwind (next_frame, NORMAL_FRAME)); | |
29639122 | 2129 | } |
c906108c | 2130 | |
29639122 JB |
2131 | static void |
2132 | mips_insn32_frame_prev_register (struct frame_info *next_frame, | |
2133 | void **this_cache, | |
2134 | int regnum, int *optimizedp, | |
2135 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 2136 | int *realnump, gdb_byte *valuep) |
29639122 JB |
2137 | { |
2138 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, | |
2139 | this_cache); | |
2140 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
2141 | optimizedp, lvalp, addrp, realnump, valuep); | |
c906108c SS |
2142 | } |
2143 | ||
29639122 JB |
2144 | static const struct frame_unwind mips_insn32_frame_unwind = |
2145 | { | |
2146 | NORMAL_FRAME, | |
2147 | mips_insn32_frame_this_id, | |
2148 | mips_insn32_frame_prev_register | |
2149 | }; | |
c906108c | 2150 | |
29639122 JB |
2151 | static const struct frame_unwind * |
2152 | mips_insn32_frame_sniffer (struct frame_info *next_frame) | |
2153 | { | |
6de5b849 | 2154 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
0fe7e7c8 | 2155 | if (! mips_pc_is_mips16 (pc)) |
29639122 JB |
2156 | return &mips_insn32_frame_unwind; |
2157 | return NULL; | |
2158 | } | |
c906108c | 2159 | |
1c645fec | 2160 | static CORE_ADDR |
29639122 JB |
2161 | mips_insn32_frame_base_address (struct frame_info *next_frame, |
2162 | void **this_cache) | |
c906108c | 2163 | { |
29639122 JB |
2164 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
2165 | this_cache); | |
2166 | return info->base; | |
2167 | } | |
c906108c | 2168 | |
29639122 JB |
2169 | static const struct frame_base mips_insn32_frame_base = |
2170 | { | |
2171 | &mips_insn32_frame_unwind, | |
2172 | mips_insn32_frame_base_address, | |
2173 | mips_insn32_frame_base_address, | |
2174 | mips_insn32_frame_base_address | |
2175 | }; | |
1c645fec | 2176 | |
29639122 JB |
2177 | static const struct frame_base * |
2178 | mips_insn32_frame_base_sniffer (struct frame_info *next_frame) | |
2179 | { | |
2180 | if (mips_insn32_frame_sniffer (next_frame) != NULL) | |
2181 | return &mips_insn32_frame_base; | |
a65bbe44 | 2182 | else |
29639122 JB |
2183 | return NULL; |
2184 | } | |
a65bbe44 | 2185 | |
29639122 JB |
2186 | static struct trad_frame_cache * |
2187 | mips_stub_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2188 | { | |
2189 | CORE_ADDR pc; | |
2190 | CORE_ADDR start_addr; | |
2191 | CORE_ADDR stack_addr; | |
2192 | struct trad_frame_cache *this_trad_cache; | |
c906108c | 2193 | |
29639122 JB |
2194 | if ((*this_cache) != NULL) |
2195 | return (*this_cache); | |
2196 | this_trad_cache = trad_frame_cache_zalloc (next_frame); | |
2197 | (*this_cache) = this_trad_cache; | |
1c645fec | 2198 | |
29639122 | 2199 | /* The return address is in the link register. */ |
4c7d22cb | 2200 | trad_frame_set_reg_realreg (this_trad_cache, PC_REGNUM, MIPS_RA_REGNUM); |
1c645fec | 2201 | |
29639122 JB |
2202 | /* Frame ID, since it's a frameless / stackless function, no stack |
2203 | space is allocated and SP on entry is the current SP. */ | |
2204 | pc = frame_pc_unwind (next_frame); | |
2205 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
4c7d22cb | 2206 | stack_addr = frame_unwind_register_signed (next_frame, MIPS_SP_REGNUM); |
29639122 | 2207 | trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr)); |
1c645fec | 2208 | |
29639122 JB |
2209 | /* Assume that the frame's base is the same as the |
2210 | stack-pointer. */ | |
2211 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2212 | |
29639122 JB |
2213 | return this_trad_cache; |
2214 | } | |
c906108c | 2215 | |
29639122 JB |
2216 | static void |
2217 | mips_stub_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2218 | struct frame_id *this_id) | |
2219 | { | |
2220 | struct trad_frame_cache *this_trad_cache | |
2221 | = mips_stub_frame_cache (next_frame, this_cache); | |
2222 | trad_frame_get_id (this_trad_cache, this_id); | |
2223 | } | |
c906108c | 2224 | |
29639122 JB |
2225 | static void |
2226 | mips_stub_frame_prev_register (struct frame_info *next_frame, | |
2227 | void **this_cache, | |
2228 | int regnum, int *optimizedp, | |
2229 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 2230 | int *realnump, gdb_byte *valuep) |
29639122 JB |
2231 | { |
2232 | struct trad_frame_cache *this_trad_cache | |
2233 | = mips_stub_frame_cache (next_frame, this_cache); | |
2234 | trad_frame_get_register (this_trad_cache, next_frame, regnum, optimizedp, | |
2235 | lvalp, addrp, realnump, valuep); | |
2236 | } | |
c906108c | 2237 | |
29639122 JB |
2238 | static const struct frame_unwind mips_stub_frame_unwind = |
2239 | { | |
2240 | NORMAL_FRAME, | |
2241 | mips_stub_frame_this_id, | |
2242 | mips_stub_frame_prev_register | |
2243 | }; | |
c906108c | 2244 | |
29639122 JB |
2245 | static const struct frame_unwind * |
2246 | mips_stub_frame_sniffer (struct frame_info *next_frame) | |
2247 | { | |
979b38e0 | 2248 | struct obj_section *s; |
93d42b30 | 2249 | CORE_ADDR pc = frame_unwind_address_in_block (next_frame, NORMAL_FRAME); |
979b38e0 | 2250 | |
29639122 JB |
2251 | if (in_plt_section (pc, NULL)) |
2252 | return &mips_stub_frame_unwind; | |
979b38e0 DJ |
2253 | |
2254 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2255 | s = find_pc_section (pc); | |
2256 | ||
2257 | if (s != NULL | |
2258 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2259 | ".MIPS.stubs") == 0) | |
2260 | return &mips_stub_frame_unwind; | |
2261 | ||
2262 | return NULL; | |
29639122 | 2263 | } |
c906108c | 2264 | |
29639122 JB |
2265 | static CORE_ADDR |
2266 | mips_stub_frame_base_address (struct frame_info *next_frame, | |
2267 | void **this_cache) | |
2268 | { | |
2269 | struct trad_frame_cache *this_trad_cache | |
2270 | = mips_stub_frame_cache (next_frame, this_cache); | |
2271 | return trad_frame_get_this_base (this_trad_cache); | |
2272 | } | |
0fce0821 | 2273 | |
29639122 JB |
2274 | static const struct frame_base mips_stub_frame_base = |
2275 | { | |
2276 | &mips_stub_frame_unwind, | |
2277 | mips_stub_frame_base_address, | |
2278 | mips_stub_frame_base_address, | |
2279 | mips_stub_frame_base_address | |
2280 | }; | |
2281 | ||
2282 | static const struct frame_base * | |
2283 | mips_stub_frame_base_sniffer (struct frame_info *next_frame) | |
2284 | { | |
2285 | if (mips_stub_frame_sniffer (next_frame) != NULL) | |
2286 | return &mips_stub_frame_base; | |
2287 | else | |
2288 | return NULL; | |
2289 | } | |
2290 | ||
2291 | static CORE_ADDR | |
2292 | read_next_frame_reg (struct frame_info *fi, int regno) | |
2293 | { | |
2294 | /* Always a pseudo. */ | |
f57d151a | 2295 | gdb_assert (regno >= gdbarch_num_regs (current_gdbarch)); |
29639122 | 2296 | if (fi == NULL) |
0fce0821 | 2297 | { |
29639122 JB |
2298 | LONGEST val; |
2299 | regcache_cooked_read_signed (current_regcache, regno, &val); | |
2300 | return val; | |
0fce0821 | 2301 | } |
29639122 JB |
2302 | else |
2303 | return frame_unwind_register_signed (fi, regno); | |
1c645fec | 2304 | |
c906108c SS |
2305 | } |
2306 | ||
29639122 | 2307 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2308 | |
29639122 JB |
2309 | static CORE_ADDR |
2310 | mips_addr_bits_remove (CORE_ADDR addr) | |
65596487 | 2311 | { |
29639122 JB |
2312 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2313 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) | |
2314 | /* This hack is a work-around for existing boards using PMON, the | |
2315 | simulator, and any other 64-bit targets that doesn't have true | |
2316 | 64-bit addressing. On these targets, the upper 32 bits of | |
2317 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2318 | likely to have been sign extended to all 1s by instruction | |
2319 | sequences that load 32-bit addresses. For example, a typical | |
2320 | piece of code that loads an address is this: | |
65596487 | 2321 | |
29639122 JB |
2322 | lui $r2, <upper 16 bits> |
2323 | ori $r2, <lower 16 bits> | |
65596487 | 2324 | |
29639122 JB |
2325 | But the lui sign-extends the value such that the upper 32 bits |
2326 | may be all 1s. The workaround is simply to mask off these | |
2327 | bits. In the future, gcc may be changed to support true 64-bit | |
2328 | addressing, and this masking will have to be disabled. */ | |
2329 | return addr &= 0xffffffffUL; | |
2330 | else | |
2331 | return addr; | |
65596487 JB |
2332 | } |
2333 | ||
29639122 JB |
2334 | /* mips_software_single_step() is called just before we want to resume |
2335 | the inferior, if we want to single-step it but there is no hardware | |
2336 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 2337 | the target of the coming instruction and breakpoint it. */ |
29639122 | 2338 | |
e6590a1b | 2339 | int |
e0cd558a | 2340 | mips_software_single_step (struct regcache *regcache) |
c906108c | 2341 | { |
8181d85f | 2342 | CORE_ADDR pc, next_pc; |
65596487 | 2343 | |
e0cd558a UW |
2344 | pc = read_register (mips_regnum (current_gdbarch)->pc); |
2345 | next_pc = mips_next_pc (pc); | |
e6590a1b | 2346 | |
e0cd558a | 2347 | insert_single_step_breakpoint (next_pc); |
e6590a1b | 2348 | return 1; |
29639122 | 2349 | } |
a65bbe44 | 2350 | |
29639122 JB |
2351 | /* Test whether the PC points to the return instruction at the |
2352 | end of a function. */ | |
65596487 | 2353 | |
29639122 JB |
2354 | static int |
2355 | mips_about_to_return (CORE_ADDR pc) | |
2356 | { | |
0fe7e7c8 | 2357 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2358 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2359 | generates a "jr $ra"; other times it generates code to load | |
2360 | the return address from the stack to an accessible register (such | |
2361 | as $a3), then a "jr" using that register. This second case | |
2362 | is almost impossible to distinguish from an indirect jump | |
2363 | used for switch statements, so we don't even try. */ | |
2364 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
2365 | else | |
2366 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
2367 | } | |
c906108c | 2368 | |
c906108c | 2369 | |
29639122 JB |
2370 | /* This fencepost looks highly suspicious to me. Removing it also |
2371 | seems suspicious as it could affect remote debugging across serial | |
2372 | lines. */ | |
c906108c | 2373 | |
29639122 JB |
2374 | static CORE_ADDR |
2375 | heuristic_proc_start (CORE_ADDR pc) | |
2376 | { | |
2377 | CORE_ADDR start_pc; | |
2378 | CORE_ADDR fence; | |
2379 | int instlen; | |
2380 | int seen_adjsp = 0; | |
65596487 | 2381 | |
bf6ae464 | 2382 | pc = gdbarch_addr_bits_remove (current_gdbarch, pc); |
29639122 JB |
2383 | start_pc = pc; |
2384 | fence = start_pc - heuristic_fence_post; | |
2385 | if (start_pc == 0) | |
2386 | return 0; | |
65596487 | 2387 | |
29639122 JB |
2388 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2389 | fence = VM_MIN_ADDRESS; | |
65596487 | 2390 | |
95ac2dcf | 2391 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2392 | |
29639122 JB |
2393 | /* search back for previous return */ |
2394 | for (start_pc -= instlen;; start_pc -= instlen) | |
2395 | if (start_pc < fence) | |
2396 | { | |
2397 | /* It's not clear to me why we reach this point when | |
2398 | stop_soon, but with this test, at least we | |
2399 | don't print out warnings for every child forked (eg, on | |
2400 | decstation). 22apr93 rich@cygnus.com. */ | |
2401 | if (stop_soon == NO_STOP_QUIETLY) | |
2402 | { | |
2403 | static int blurb_printed = 0; | |
98b4dd94 | 2404 | |
8a3fe4f8 | 2405 | warning (_("GDB can't find the start of the function at 0x%s."), |
29639122 JB |
2406 | paddr_nz (pc)); |
2407 | ||
2408 | if (!blurb_printed) | |
2409 | { | |
2410 | /* This actually happens frequently in embedded | |
2411 | development, when you first connect to a board | |
2412 | and your stack pointer and pc are nowhere in | |
2413 | particular. This message needs to give people | |
2414 | in that situation enough information to | |
2415 | determine that it's no big deal. */ | |
2416 | printf_filtered ("\n\ | |
2417 | GDB is unable to find the start of the function at 0x%s\n\ | |
2418 | and thus can't determine the size of that function's stack frame.\n\ | |
2419 | This means that GDB may be unable to access that stack frame, or\n\ | |
2420 | the frames below it.\n\ | |
2421 | This problem is most likely caused by an invalid program counter or\n\ | |
2422 | stack pointer.\n\ | |
2423 | However, if you think GDB should simply search farther back\n\ | |
2424 | from 0x%s for code which looks like the beginning of a\n\ | |
2425 | function, you can increase the range of the search using the `set\n\ | |
2426 | heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); | |
2427 | blurb_printed = 1; | |
2428 | } | |
2429 | } | |
2430 | ||
2431 | return 0; | |
2432 | } | |
0fe7e7c8 | 2433 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2434 | { |
2435 | unsigned short inst; | |
2436 | ||
2437 | /* On MIPS16, any one of the following is likely to be the | |
2438 | start of a function: | |
2439 | entry | |
2440 | addiu sp,-n | |
2441 | daddiu sp,-n | |
2442 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
2443 | inst = mips_fetch_instruction (start_pc); | |
2444 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
2445 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2446 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2447 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
2448 | break; | |
2449 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2450 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2451 | seen_adjsp = 1; | |
2452 | else | |
2453 | seen_adjsp = 0; | |
2454 | } | |
2455 | else if (mips_about_to_return (start_pc)) | |
2456 | { | |
4c7d22cb | 2457 | /* Skip return and its delay slot. */ |
95ac2dcf | 2458 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2459 | break; |
2460 | } | |
2461 | ||
2462 | return start_pc; | |
c906108c SS |
2463 | } |
2464 | ||
6c0d6680 DJ |
2465 | struct mips_objfile_private |
2466 | { | |
2467 | bfd_size_type size; | |
2468 | char *contents; | |
2469 | }; | |
2470 | ||
f09ded24 AC |
2471 | /* According to the current ABI, should the type be passed in a |
2472 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 2473 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 AC |
2474 | FP registers and, consequently this returns false - forces FP |
2475 | arguments into integer registers. */ | |
2476 | ||
2477 | static int | |
2478 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2479 | { | |
2480 | return ((typecode == TYPE_CODE_FLT | |
2481 | || (MIPS_EABI | |
6d82d43b AC |
2482 | && (typecode == TYPE_CODE_STRUCT |
2483 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 2484 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
2485 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
2486 | == TYPE_CODE_FLT)) | |
c86b5b38 | 2487 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2488 | } |
2489 | ||
49e790b0 DJ |
2490 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2491 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2492 | ||
2493 | static int | |
2494 | mips_type_needs_double_align (struct type *type) | |
2495 | { | |
2496 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2497 | |
49e790b0 DJ |
2498 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2499 | return 1; | |
2500 | else if (typecode == TYPE_CODE_STRUCT) | |
2501 | { | |
2502 | if (TYPE_NFIELDS (type) < 1) | |
2503 | return 0; | |
2504 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2505 | } | |
2506 | else if (typecode == TYPE_CODE_UNION) | |
2507 | { | |
361d1df0 | 2508 | int i, n; |
49e790b0 DJ |
2509 | |
2510 | n = TYPE_NFIELDS (type); | |
2511 | for (i = 0; i < n; i++) | |
2512 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2513 | return 1; | |
2514 | return 0; | |
2515 | } | |
2516 | return 0; | |
2517 | } | |
2518 | ||
dc604539 AC |
2519 | /* Adjust the address downward (direction of stack growth) so that it |
2520 | is correctly aligned for a new stack frame. */ | |
2521 | static CORE_ADDR | |
2522 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2523 | { | |
5b03f266 | 2524 | return align_down (addr, 16); |
dc604539 AC |
2525 | } |
2526 | ||
f7ab6ec6 | 2527 | static CORE_ADDR |
7d9b040b | 2528 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2529 | struct regcache *regcache, CORE_ADDR bp_addr, |
2530 | int nargs, struct value **args, CORE_ADDR sp, | |
2531 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2532 | { |
2533 | int argreg; | |
2534 | int float_argreg; | |
2535 | int argnum; | |
2536 | int len = 0; | |
2537 | int stack_offset = 0; | |
480d3dd2 | 2538 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2539 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 2540 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 2541 | |
25ab4790 AC |
2542 | /* For shared libraries, "t9" needs to point at the function |
2543 | address. */ | |
4c7d22cb | 2544 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2545 | |
2546 | /* Set the return address register to point to the entry point of | |
2547 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2548 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2549 | |
c906108c | 2550 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2551 | are properly aligned. The stack has to be at least 64-bit |
2552 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2553 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2554 | aligned, so we round to this widest known alignment. */ | |
2555 | ||
5b03f266 AC |
2556 | sp = align_down (sp, 16); |
2557 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2558 | |
46e0f506 | 2559 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2560 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2561 | passed in registers, but that's OK. */ |
c906108c | 2562 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 2563 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 2564 | sp -= align_up (len, 16); |
c906108c | 2565 | |
9ace0497 | 2566 | if (mips_debug) |
6d82d43b | 2567 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2568 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2569 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2570 | |
c906108c | 2571 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2572 | argreg = MIPS_A0_REGNUM; |
56cea623 | 2573 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 2574 | |
46e0f506 | 2575 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2576 | if (struct_return) |
9ace0497 AC |
2577 | { |
2578 | if (mips_debug) | |
2579 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2580 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2581 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
2582 | write_register (argreg++, struct_addr); |
2583 | } | |
c906108c SS |
2584 | |
2585 | /* Now load as many as possible of the first arguments into | |
2586 | registers, and push the rest onto the stack. Loop thru args | |
2587 | from first to last. */ | |
2588 | for (argnum = 0; argnum < nargs; argnum++) | |
2589 | { | |
47a35522 MK |
2590 | const gdb_byte *val; |
2591 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 2592 | struct value *arg = args[argnum]; |
4991999e | 2593 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
2594 | int len = TYPE_LENGTH (arg_type); |
2595 | enum type_code typecode = TYPE_CODE (arg_type); | |
2596 | ||
9ace0497 AC |
2597 | if (mips_debug) |
2598 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2599 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2600 | argnum + 1, len, (int) typecode); |
9ace0497 | 2601 | |
c906108c | 2602 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2603 | reference. */ |
1a69e1e4 | 2604 | if (len > regsize |
9ace0497 | 2605 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2606 | { |
1a69e1e4 | 2607 | store_unsigned_integer (valbuf, regsize, VALUE_ADDRESS (arg)); |
c906108c | 2608 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 2609 | len = regsize; |
c906108c | 2610 | val = valbuf; |
9ace0497 AC |
2611 | if (mips_debug) |
2612 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2613 | } |
2614 | else | |
47a35522 | 2615 | val = value_contents (arg); |
c906108c SS |
2616 | |
2617 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2618 | even-numbered floating point register. Round the FP register |
2619 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2620 | left. Non MIPS_EABI targets also pass the FP in the integer |
2621 | registers so also round up normal registers. */ | |
1a69e1e4 | 2622 | if (regsize < 8 && fp_register_arg_p (typecode, arg_type)) |
acdb74a0 AC |
2623 | { |
2624 | if ((float_argreg & 1)) | |
2625 | float_argreg++; | |
2626 | } | |
c906108c SS |
2627 | |
2628 | /* Floating point arguments passed in registers have to be | |
2629 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2630 | are passed in register pairs; the even register gets |
2631 | the low word, and the odd register gets the high word. | |
2632 | On non-EABI processors, the first two floating point arguments are | |
2633 | also copied to general registers, because MIPS16 functions | |
2634 | don't use float registers for arguments. This duplication of | |
2635 | arguments in general registers can't hurt non-MIPS16 functions | |
2636 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2637 | /* MIPS_EABI squeezes a struct that contains a single floating |
2638 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2639 | stack. */ |
f09ded24 AC |
2640 | if (fp_register_arg_p (typecode, arg_type) |
2641 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c | 2642 | { |
6da397e0 KB |
2643 | /* EABI32 will pass doubles in consecutive registers, even on |
2644 | 64-bit cores. At one time, we used to check the size of | |
2645 | `float_argreg' to determine whether or not to pass doubles | |
2646 | in consecutive registers, but this is not sufficient for | |
2647 | making the ABI determination. */ | |
2648 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 2649 | { |
4c6b5505 UW |
2650 | int low_offset = gdbarch_byte_order (current_gdbarch) |
2651 | == BFD_ENDIAN_BIG ? 4 : 0; | |
c906108c SS |
2652 | unsigned long regval; |
2653 | ||
2654 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2655 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2656 | if (mips_debug) |
acdb74a0 | 2657 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2658 | float_argreg, phex (regval, 4)); |
c906108c | 2659 | write_register (float_argreg++, regval); |
c906108c SS |
2660 | |
2661 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2662 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2663 | if (mips_debug) |
acdb74a0 | 2664 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2665 | float_argreg, phex (regval, 4)); |
c906108c | 2666 | write_register (float_argreg++, regval); |
c906108c SS |
2667 | } |
2668 | else | |
2669 | { | |
2670 | /* This is a floating point value that fits entirely | |
2671 | in a single register. */ | |
53a5351d | 2672 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 2673 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2674 | LONGEST regval = extract_unsigned_integer (val, len); |
2675 | if (mips_debug) | |
acdb74a0 | 2676 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2677 | float_argreg, phex (regval, len)); |
c906108c | 2678 | write_register (float_argreg++, regval); |
c906108c SS |
2679 | } |
2680 | } | |
2681 | else | |
2682 | { | |
2683 | /* Copy the argument to general registers or the stack in | |
2684 | register-sized pieces. Large arguments are split between | |
2685 | registers and stack. */ | |
1a69e1e4 DJ |
2686 | /* Note: structs whose size is not a multiple of regsize |
2687 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
2688 | them in registers where gcc sometimes puts them on the |
2689 | stack. For maximum compatibility, we will put them in | |
2690 | both places. */ | |
1a69e1e4 | 2691 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 2692 | |
f09ded24 | 2693 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2694 | register are only written to memory. */ |
c906108c SS |
2695 | while (len > 0) |
2696 | { | |
ebafbe83 | 2697 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2698 | int stack_used_p = 0; |
1a69e1e4 | 2699 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 2700 | |
acdb74a0 AC |
2701 | if (mips_debug) |
2702 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2703 | partial_len); | |
2704 | ||
566f0f7a | 2705 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2706 | if (argreg > MIPS_LAST_ARG_REGNUM |
2707 | || odd_sized_struct | |
2708 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2709 | { |
c906108c SS |
2710 | /* Should shorter than int integer values be |
2711 | promoted to int before being stored? */ | |
c906108c | 2712 | int longword_offset = 0; |
9ace0497 | 2713 | CORE_ADDR addr; |
566f0f7a | 2714 | stack_used_p = 1; |
4c6b5505 | 2715 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 2716 | { |
1a69e1e4 | 2717 | if (regsize == 8 |
480d3dd2 AC |
2718 | && (typecode == TYPE_CODE_INT |
2719 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 2720 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 2721 | longword_offset = regsize - len; |
480d3dd2 AC |
2722 | else if ((typecode == TYPE_CODE_STRUCT |
2723 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
2724 | && TYPE_LENGTH (arg_type) < regsize) |
2725 | longword_offset = regsize - len; | |
7a292a7a | 2726 | } |
c5aa993b | 2727 | |
9ace0497 AC |
2728 | if (mips_debug) |
2729 | { | |
cb3d25d1 MS |
2730 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2731 | paddr_nz (stack_offset)); | |
2732 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2733 | paddr_nz (longword_offset)); | |
9ace0497 | 2734 | } |
361d1df0 | 2735 | |
9ace0497 AC |
2736 | addr = sp + stack_offset + longword_offset; |
2737 | ||
2738 | if (mips_debug) | |
2739 | { | |
2740 | int i; | |
6d82d43b | 2741 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 | 2742 | paddr_nz (addr)); |
9ace0497 AC |
2743 | for (i = 0; i < partial_len; i++) |
2744 | { | |
6d82d43b | 2745 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 2746 | val[i] & 0xff); |
9ace0497 AC |
2747 | } |
2748 | } | |
2749 | write_memory (addr, val, partial_len); | |
c906108c SS |
2750 | } |
2751 | ||
f09ded24 AC |
2752 | /* Note!!! This is NOT an else clause. Odd sized |
2753 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2754 | arguments will not. */ |
566f0f7a | 2755 | /* Write this portion of the argument to a general |
6d82d43b | 2756 | purpose register. */ |
f09ded24 AC |
2757 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2758 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2759 | { |
6d82d43b AC |
2760 | LONGEST regval = |
2761 | extract_unsigned_integer (val, partial_len); | |
c906108c | 2762 | |
9ace0497 | 2763 | if (mips_debug) |
acdb74a0 | 2764 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 2765 | argreg, |
1a69e1e4 | 2766 | phex (regval, regsize)); |
c906108c SS |
2767 | write_register (argreg, regval); |
2768 | argreg++; | |
c906108c | 2769 | } |
c5aa993b | 2770 | |
c906108c SS |
2771 | len -= partial_len; |
2772 | val += partial_len; | |
2773 | ||
566f0f7a | 2774 | /* Compute the the offset into the stack at which we |
6d82d43b | 2775 | will copy the next parameter. |
566f0f7a | 2776 | |
566f0f7a | 2777 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2778 | only needs to be adjusted when it has been used. */ |
c906108c | 2779 | |
46e0f506 | 2780 | if (stack_used_p) |
1a69e1e4 | 2781 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
2782 | } |
2783 | } | |
9ace0497 AC |
2784 | if (mips_debug) |
2785 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2786 | } |
2787 | ||
f10683bb | 2788 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 2789 | |
0f71a2f6 JM |
2790 | /* Return adjusted stack pointer. */ |
2791 | return sp; | |
2792 | } | |
2793 | ||
a1f5b845 | 2794 | /* Determine the return value convention being used. */ |
6d82d43b | 2795 | |
9c8fdbfa AC |
2796 | static enum return_value_convention |
2797 | mips_eabi_return_value (struct gdbarch *gdbarch, | |
2798 | struct type *type, struct regcache *regcache, | |
47a35522 | 2799 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 2800 | { |
9c8fdbfa AC |
2801 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
2802 | return RETURN_VALUE_STRUCT_CONVENTION; | |
2803 | if (readbuf) | |
2804 | memset (readbuf, 0, TYPE_LENGTH (type)); | |
2805 | return RETURN_VALUE_REGISTER_CONVENTION; | |
6d82d43b AC |
2806 | } |
2807 | ||
6d82d43b AC |
2808 | |
2809 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 2810 | |
f7ab6ec6 | 2811 | static CORE_ADDR |
7d9b040b | 2812 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2813 | struct regcache *regcache, CORE_ADDR bp_addr, |
2814 | int nargs, struct value **args, CORE_ADDR sp, | |
2815 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
2816 | { |
2817 | int argreg; | |
2818 | int float_argreg; | |
2819 | int argnum; | |
2820 | int len = 0; | |
2821 | int stack_offset = 0; | |
480d3dd2 | 2822 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2823 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 2824 | |
25ab4790 AC |
2825 | /* For shared libraries, "t9" needs to point at the function |
2826 | address. */ | |
4c7d22cb | 2827 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2828 | |
2829 | /* Set the return address register to point to the entry point of | |
2830 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2831 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2832 | |
cb3d25d1 MS |
2833 | /* First ensure that the stack and structure return address (if any) |
2834 | are properly aligned. The stack has to be at least 64-bit | |
2835 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2836 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2837 | aligned, so we round to this widest known alignment. */ | |
2838 | ||
5b03f266 AC |
2839 | sp = align_down (sp, 16); |
2840 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
2841 | |
2842 | /* Now make space on the stack for the args. */ | |
2843 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 2844 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 2845 | sp -= align_up (len, 16); |
cb3d25d1 MS |
2846 | |
2847 | if (mips_debug) | |
6d82d43b | 2848 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2849 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
2850 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
2851 | |
2852 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 2853 | argreg = MIPS_A0_REGNUM; |
56cea623 | 2854 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 2855 | |
46e0f506 | 2856 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
2857 | if (struct_return) |
2858 | { | |
2859 | if (mips_debug) | |
2860 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2861 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
2862 | argreg, paddr_nz (struct_addr)); |
2863 | write_register (argreg++, struct_addr); | |
2864 | } | |
2865 | ||
2866 | /* Now load as many as possible of the first arguments into | |
2867 | registers, and push the rest onto the stack. Loop thru args | |
2868 | from first to last. */ | |
2869 | for (argnum = 0; argnum < nargs; argnum++) | |
2870 | { | |
47a35522 | 2871 | const gdb_byte *val; |
cb3d25d1 | 2872 | struct value *arg = args[argnum]; |
4991999e | 2873 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
2874 | int len = TYPE_LENGTH (arg_type); |
2875 | enum type_code typecode = TYPE_CODE (arg_type); | |
2876 | ||
2877 | if (mips_debug) | |
2878 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2879 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
2880 | argnum + 1, len, (int) typecode); |
2881 | ||
47a35522 | 2882 | val = value_contents (arg); |
cb3d25d1 MS |
2883 | |
2884 | if (fp_register_arg_p (typecode, arg_type) | |
2885 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
2886 | { | |
2887 | /* This is a floating point value that fits entirely | |
2888 | in a single register. */ | |
2889 | /* On 32 bit ABI's the float_argreg is further adjusted | |
2890 | above to ensure that it is even register aligned. */ | |
2891 | LONGEST regval = extract_unsigned_integer (val, len); | |
2892 | if (mips_debug) | |
2893 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
2894 | float_argreg, phex (regval, len)); | |
2895 | write_register (float_argreg++, regval); | |
2896 | ||
2897 | if (mips_debug) | |
2898 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
2899 | argreg, phex (regval, len)); | |
2900 | write_register (argreg, regval); | |
2901 | argreg += 1; | |
2902 | } | |
2903 | else | |
2904 | { | |
2905 | /* Copy the argument to general registers or the stack in | |
2906 | register-sized pieces. Large arguments are split between | |
2907 | registers and stack. */ | |
1a69e1e4 | 2908 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
2909 | are treated specially: Irix cc passes them in registers |
2910 | where gcc sometimes puts them on the stack. For maximum | |
2911 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
2912 | int odd_sized_struct = (len > MIPS64_REGSIZE |
2913 | && len % MIPS64_REGSIZE != 0); | |
cb3d25d1 | 2914 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2915 | register are only written to memory. */ |
cb3d25d1 MS |
2916 | while (len > 0) |
2917 | { | |
ad018eee | 2918 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 2919 | int stack_used_p = 0; |
1a69e1e4 | 2920 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
2921 | |
2922 | if (mips_debug) | |
2923 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2924 | partial_len); | |
2925 | ||
2926 | /* Write this portion of the argument to the stack. */ | |
2927 | if (argreg > MIPS_LAST_ARG_REGNUM | |
2928 | || odd_sized_struct | |
2929 | || fp_register_arg_p (typecode, arg_type)) | |
2930 | { | |
2931 | /* Should shorter than int integer values be | |
2932 | promoted to int before being stored? */ | |
2933 | int longword_offset = 0; | |
2934 | CORE_ADDR addr; | |
2935 | stack_used_p = 1; | |
4c6b5505 | 2936 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 2937 | { |
1a69e1e4 DJ |
2938 | if ((typecode == TYPE_CODE_INT |
2939 | || typecode == TYPE_CODE_PTR | |
2940 | || typecode == TYPE_CODE_FLT) | |
2941 | && len <= 4) | |
2942 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
2943 | } |
2944 | ||
2945 | if (mips_debug) | |
2946 | { | |
2947 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
2948 | paddr_nz (stack_offset)); | |
2949 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2950 | paddr_nz (longword_offset)); | |
2951 | } | |
2952 | ||
2953 | addr = sp + stack_offset + longword_offset; | |
2954 | ||
2955 | if (mips_debug) | |
2956 | { | |
2957 | int i; | |
6d82d43b | 2958 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 MS |
2959 | paddr_nz (addr)); |
2960 | for (i = 0; i < partial_len; i++) | |
2961 | { | |
6d82d43b | 2962 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
2963 | val[i] & 0xff); |
2964 | } | |
2965 | } | |
2966 | write_memory (addr, val, partial_len); | |
2967 | } | |
2968 | ||
2969 | /* Note!!! This is NOT an else clause. Odd sized | |
2970 | structs may go thru BOTH paths. Floating point | |
2971 | arguments will not. */ | |
2972 | /* Write this portion of the argument to a general | |
6d82d43b | 2973 | purpose register. */ |
cb3d25d1 MS |
2974 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2975 | && !fp_register_arg_p (typecode, arg_type)) | |
2976 | { | |
6d82d43b AC |
2977 | LONGEST regval = |
2978 | extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
2979 | |
2980 | /* A non-floating-point argument being passed in a | |
2981 | general register. If a struct or union, and if | |
2982 | the remaining length is smaller than the register | |
2983 | size, we have to adjust the register value on | |
2984 | big endian targets. | |
2985 | ||
2986 | It does not seem to be necessary to do the | |
1a69e1e4 | 2987 | same for integral types. */ |
cb3d25d1 | 2988 | |
4c6b5505 | 2989 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 2990 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
2991 | && (typecode == TYPE_CODE_STRUCT |
2992 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 2993 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 2994 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
2995 | |
2996 | if (mips_debug) | |
2997 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
2998 | argreg, | |
1a69e1e4 | 2999 | phex (regval, MIPS64_REGSIZE)); |
cb3d25d1 MS |
3000 | write_register (argreg, regval); |
3001 | argreg++; | |
3002 | } | |
3003 | ||
3004 | len -= partial_len; | |
3005 | val += partial_len; | |
3006 | ||
3007 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3008 | will copy the next parameter. |
cb3d25d1 MS |
3009 | |
3010 | In N32 (N64?), the stack_offset only needs to be | |
3011 | adjusted when it has been used. */ | |
3012 | ||
3013 | if (stack_used_p) | |
1a69e1e4 | 3014 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
3015 | } |
3016 | } | |
3017 | if (mips_debug) | |
3018 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3019 | } | |
3020 | ||
f10683bb | 3021 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3022 | |
cb3d25d1 MS |
3023 | /* Return adjusted stack pointer. */ |
3024 | return sp; | |
3025 | } | |
3026 | ||
6d82d43b AC |
3027 | static enum return_value_convention |
3028 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
3029 | struct type *type, struct regcache *regcache, | |
47a35522 | 3030 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 3031 | { |
6d82d43b AC |
3032 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3033 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3034 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3035 | || TYPE_CODE (type) == TYPE_CODE_ARRAY | |
1a69e1e4 | 3036 | || TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 3037 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
3038 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3039 | && TYPE_LENGTH (type) == 16 | |
3040 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3041 | { | |
3042 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
3043 | two registers are used in the same as memory order, so the | |
3044 | eight bytes with the lower memory address are in $f0. */ | |
3045 | if (mips_debug) | |
3046 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
3047 | mips_xfer_register (regcache, | |
f57d151a UW |
3048 | gdbarch_num_regs (current_gdbarch) |
3049 | + mips_regnum (current_gdbarch)->fp0, | |
4c6b5505 UW |
3050 | 8, gdbarch_byte_order (current_gdbarch), |
3051 | readbuf, writebuf, 0); | |
d05f6826 | 3052 | mips_xfer_register (regcache, |
f57d151a UW |
3053 | gdbarch_num_regs (current_gdbarch) |
3054 | + mips_regnum (current_gdbarch)->fp0 + 2, | |
4c6b5505 UW |
3055 | 8, gdbarch_byte_order (current_gdbarch), |
3056 | readbuf ? readbuf + 8 : readbuf, | |
d05f6826 DJ |
3057 | writebuf ? writebuf + 8 : writebuf, 0); |
3058 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3059 | } | |
6d82d43b AC |
3060 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3061 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3062 | { | |
3063 | /* A floating-point value belongs in the least significant part | |
3064 | of FP0. */ | |
3065 | if (mips_debug) | |
3066 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3067 | mips_xfer_register (regcache, | |
f57d151a UW |
3068 | gdbarch_num_regs (current_gdbarch) |
3069 | + mips_regnum (current_gdbarch)->fp0, | |
6d82d43b | 3070 | TYPE_LENGTH (type), |
4c6b5505 UW |
3071 | gdbarch_byte_order (current_gdbarch), |
3072 | readbuf, writebuf, 0); | |
6d82d43b AC |
3073 | return RETURN_VALUE_REGISTER_CONVENTION; |
3074 | } | |
3075 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3076 | && TYPE_NFIELDS (type) <= 2 | |
3077 | && TYPE_NFIELDS (type) >= 1 | |
3078 | && ((TYPE_NFIELDS (type) == 1 | |
3079 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3080 | == TYPE_CODE_FLT)) | |
3081 | || (TYPE_NFIELDS (type) == 2 | |
3082 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3083 | == TYPE_CODE_FLT) | |
3084 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3085 | == TYPE_CODE_FLT))) | |
3086 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3087 | { | |
3088 | /* A struct that contains one or two floats. Each value is part | |
3089 | in the least significant part of their floating point | |
3090 | register.. */ | |
6d82d43b AC |
3091 | int regnum; |
3092 | int field; | |
3093 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3094 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3095 | { | |
3096 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3097 | / TARGET_CHAR_BIT); | |
3098 | if (mips_debug) | |
3099 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3100 | offset); | |
f57d151a UW |
3101 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3102 | + regnum, | |
6d82d43b | 3103 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
4c6b5505 UW |
3104 | gdbarch_byte_order (current_gdbarch), |
3105 | readbuf, writebuf, offset); | |
6d82d43b AC |
3106 | } |
3107 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3108 | } | |
3109 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3110 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3111 | { | |
3112 | /* A structure or union. Extract the left justified value, | |
3113 | regardless of the byte order. I.e. DO NOT USE | |
3114 | mips_xfer_lower. */ | |
3115 | int offset; | |
3116 | int regnum; | |
4c7d22cb | 3117 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3118 | offset < TYPE_LENGTH (type); |
3119 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3120 | { | |
3121 | int xfer = register_size (current_gdbarch, regnum); | |
3122 | if (offset + xfer > TYPE_LENGTH (type)) | |
3123 | xfer = TYPE_LENGTH (type) - offset; | |
3124 | if (mips_debug) | |
3125 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3126 | offset, xfer, regnum); | |
f57d151a UW |
3127 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3128 | + regnum, xfer, | |
6d82d43b AC |
3129 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
3130 | } | |
3131 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3132 | } | |
3133 | else | |
3134 | { | |
3135 | /* A scalar extract each part but least-significant-byte | |
3136 | justified. */ | |
3137 | int offset; | |
3138 | int regnum; | |
4c7d22cb | 3139 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3140 | offset < TYPE_LENGTH (type); |
3141 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3142 | { | |
3143 | int xfer = register_size (current_gdbarch, regnum); | |
6d82d43b AC |
3144 | if (offset + xfer > TYPE_LENGTH (type)) |
3145 | xfer = TYPE_LENGTH (type) - offset; | |
3146 | if (mips_debug) | |
3147 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3148 | offset, xfer, regnum); | |
f57d151a UW |
3149 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3150 | + regnum, xfer, | |
4c6b5505 UW |
3151 | gdbarch_byte_order (current_gdbarch), |
3152 | readbuf, writebuf, offset); | |
6d82d43b AC |
3153 | } |
3154 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3155 | } | |
3156 | } | |
3157 | ||
3158 | /* O32 ABI stuff. */ | |
3159 | ||
3160 | static CORE_ADDR | |
7d9b040b | 3161 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3162 | struct regcache *regcache, CORE_ADDR bp_addr, |
3163 | int nargs, struct value **args, CORE_ADDR sp, | |
3164 | int struct_return, CORE_ADDR struct_addr) | |
3165 | { | |
3166 | int argreg; | |
3167 | int float_argreg; | |
3168 | int argnum; | |
3169 | int len = 0; | |
3170 | int stack_offset = 0; | |
3171 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7d9b040b | 3172 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3173 | |
3174 | /* For shared libraries, "t9" needs to point at the function | |
3175 | address. */ | |
4c7d22cb | 3176 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3177 | |
3178 | /* Set the return address register to point to the entry point of | |
3179 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3180 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3181 | |
3182 | /* First ensure that the stack and structure return address (if any) | |
3183 | are properly aligned. The stack has to be at least 64-bit | |
3184 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3185 | aligned. For n32 and n64, stack frames need to be 128-bit |
3186 | aligned, so we round to this widest known alignment. */ | |
3187 | ||
5b03f266 AC |
3188 | sp = align_down (sp, 16); |
3189 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3190 | |
3191 | /* Now make space on the stack for the args. */ | |
3192 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3193 | { |
3194 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3195 | int arglen = TYPE_LENGTH (arg_type); | |
3196 | ||
3197 | /* Align to double-word if necessary. */ | |
2afd3f0a | 3198 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 3199 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 3200 | /* Allocate space on the stack. */ |
1a69e1e4 | 3201 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 3202 | } |
5b03f266 | 3203 | sp -= align_up (len, 16); |
ebafbe83 MS |
3204 | |
3205 | if (mips_debug) | |
6d82d43b | 3206 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3207 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3208 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3209 | |
3210 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3211 | argreg = MIPS_A0_REGNUM; |
56cea623 | 3212 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 3213 | |
bcb0cc15 | 3214 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3215 | if (struct_return) |
3216 | { | |
3217 | if (mips_debug) | |
3218 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3219 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
3220 | argreg, paddr_nz (struct_addr)); |
3221 | write_register (argreg++, struct_addr); | |
1a69e1e4 | 3222 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
3223 | } |
3224 | ||
3225 | /* Now load as many as possible of the first arguments into | |
3226 | registers, and push the rest onto the stack. Loop thru args | |
3227 | from first to last. */ | |
3228 | for (argnum = 0; argnum < nargs; argnum++) | |
3229 | { | |
47a35522 | 3230 | const gdb_byte *val; |
ebafbe83 | 3231 | struct value *arg = args[argnum]; |
4991999e | 3232 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3233 | int len = TYPE_LENGTH (arg_type); |
3234 | enum type_code typecode = TYPE_CODE (arg_type); | |
3235 | ||
3236 | if (mips_debug) | |
3237 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3238 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3239 | argnum + 1, len, (int) typecode); |
3240 | ||
47a35522 | 3241 | val = value_contents (arg); |
46cac009 AC |
3242 | |
3243 | /* 32-bit ABIs always start floating point arguments in an | |
3244 | even-numbered floating point register. Round the FP register | |
3245 | up before the check to see if there are any FP registers | |
3246 | left. O32/O64 targets also pass the FP in the integer | |
3247 | registers so also round up normal registers. */ | |
2afd3f0a | 3248 | if (fp_register_arg_p (typecode, arg_type)) |
46cac009 AC |
3249 | { |
3250 | if ((float_argreg & 1)) | |
3251 | float_argreg++; | |
3252 | } | |
3253 | ||
3254 | /* Floating point arguments passed in registers have to be | |
3255 | treated specially. On 32-bit architectures, doubles | |
3256 | are passed in register pairs; the even register gets | |
3257 | the low word, and the odd register gets the high word. | |
3258 | On O32/O64, the first two floating point arguments are | |
3259 | also copied to general registers, because MIPS16 functions | |
3260 | don't use float registers for arguments. This duplication of | |
3261 | arguments in general registers can't hurt non-MIPS16 functions | |
3262 | because those registers are normally skipped. */ | |
3263 | ||
3264 | if (fp_register_arg_p (typecode, arg_type) | |
3265 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3266 | { | |
8b07f6d8 | 3267 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 3268 | { |
4c6b5505 UW |
3269 | int low_offset = gdbarch_byte_order (current_gdbarch) |
3270 | == BFD_ENDIAN_BIG ? 4 : 0; | |
46cac009 AC |
3271 | unsigned long regval; |
3272 | ||
3273 | /* Write the low word of the double to the even register(s). */ | |
3274 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3275 | if (mips_debug) | |
3276 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3277 | float_argreg, phex (regval, 4)); | |
3278 | write_register (float_argreg++, regval); | |
3279 | if (mips_debug) | |
3280 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3281 | argreg, phex (regval, 4)); | |
3282 | write_register (argreg++, regval); | |
3283 | ||
3284 | /* Write the high word of the double to the odd register(s). */ | |
3285 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3286 | if (mips_debug) | |
3287 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3288 | float_argreg, phex (regval, 4)); | |
3289 | write_register (float_argreg++, regval); | |
3290 | ||
3291 | if (mips_debug) | |
3292 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3293 | argreg, phex (regval, 4)); | |
3294 | write_register (argreg++, regval); | |
3295 | } | |
3296 | else | |
3297 | { | |
3298 | /* This is a floating point value that fits entirely | |
3299 | in a single register. */ | |
3300 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3301 | above to ensure that it is even register aligned. */ |
46cac009 AC |
3302 | LONGEST regval = extract_unsigned_integer (val, len); |
3303 | if (mips_debug) | |
3304 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3305 | float_argreg, phex (regval, len)); | |
3306 | write_register (float_argreg++, regval); | |
3307 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
3308 | registers for each argument. The below is (my |
3309 | guess) to ensure that the corresponding integer | |
3310 | register has reserved the same space. */ | |
46cac009 AC |
3311 | if (mips_debug) |
3312 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3313 | argreg, phex (regval, len)); | |
3314 | write_register (argreg, regval); | |
2afd3f0a | 3315 | argreg += 2; |
46cac009 AC |
3316 | } |
3317 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 3318 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
3319 | } |
3320 | else | |
3321 | { | |
3322 | /* Copy the argument to general registers or the stack in | |
3323 | register-sized pieces. Large arguments are split between | |
3324 | registers and stack. */ | |
1a69e1e4 DJ |
3325 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
3326 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3327 | them in registers where gcc sometimes puts them on the |
3328 | stack. For maximum compatibility, we will put them in | |
3329 | both places. */ | |
1a69e1e4 DJ |
3330 | int odd_sized_struct = (len > MIPS32_REGSIZE |
3331 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
3332 | /* Structures should be aligned to eight bytes (even arg registers) |
3333 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 3334 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
3335 | { |
3336 | if ((argreg & 1)) | |
968b5391 MR |
3337 | { |
3338 | argreg++; | |
1a69e1e4 | 3339 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 3340 | } |
46cac009 | 3341 | } |
46cac009 AC |
3342 | while (len > 0) |
3343 | { | |
3344 | /* Remember if the argument was written to the stack. */ | |
3345 | int stack_used_p = 0; | |
1a69e1e4 | 3346 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
3347 | |
3348 | if (mips_debug) | |
3349 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3350 | partial_len); | |
3351 | ||
3352 | /* Write this portion of the argument to the stack. */ | |
3353 | if (argreg > MIPS_LAST_ARG_REGNUM | |
968b5391 | 3354 | || odd_sized_struct) |
46cac009 AC |
3355 | { |
3356 | /* Should shorter than int integer values be | |
3357 | promoted to int before being stored? */ | |
3358 | int longword_offset = 0; | |
3359 | CORE_ADDR addr; | |
3360 | stack_used_p = 1; | |
46cac009 AC |
3361 | |
3362 | if (mips_debug) | |
3363 | { | |
3364 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3365 | paddr_nz (stack_offset)); | |
3366 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3367 | paddr_nz (longword_offset)); | |
3368 | } | |
3369 | ||
3370 | addr = sp + stack_offset + longword_offset; | |
3371 | ||
3372 | if (mips_debug) | |
3373 | { | |
3374 | int i; | |
6d82d43b | 3375 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
46cac009 AC |
3376 | paddr_nz (addr)); |
3377 | for (i = 0; i < partial_len; i++) | |
3378 | { | |
6d82d43b | 3379 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3380 | val[i] & 0xff); |
3381 | } | |
3382 | } | |
3383 | write_memory (addr, val, partial_len); | |
3384 | } | |
3385 | ||
3386 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3387 | structs may go thru BOTH paths. */ |
46cac009 | 3388 | /* Write this portion of the argument to a general |
6d82d43b | 3389 | purpose register. */ |
968b5391 | 3390 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
46cac009 AC |
3391 | { |
3392 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3393 | /* Value may need to be sign extended, because |
1b13c4f6 | 3394 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3395 | |
3396 | /* A non-floating-point argument being passed in a | |
3397 | general register. If a struct or union, and if | |
3398 | the remaining length is smaller than the register | |
3399 | size, we have to adjust the register value on | |
3400 | big endian targets. | |
3401 | ||
3402 | It does not seem to be necessary to do the | |
3403 | same for integral types. | |
3404 | ||
3405 | Also don't do this adjustment on O64 binaries. | |
3406 | ||
3407 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3408 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
3409 | mips_abi_regsize(), generates a left shift |
3410 | as part of storing the argument in a register | |
3411 | (the left shift isn't generated when | |
1b13c4f6 | 3412 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3413 | it is quite possible that this is GCC |
3414 | contradicting the LE/O32 ABI, GDB has not been | |
3415 | adjusted to accommodate this. Either someone | |
3416 | needs to demonstrate that the LE/O32 ABI | |
3417 | specifies such a left shift OR this new ABI gets | |
3418 | identified as such and GDB gets tweaked | |
3419 | accordingly. */ | |
3420 | ||
4c6b5505 | 3421 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3422 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
3423 | && (typecode == TYPE_CODE_STRUCT |
3424 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3425 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 3426 | * TARGET_CHAR_BIT); |
46cac009 AC |
3427 | |
3428 | if (mips_debug) | |
3429 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3430 | argreg, | |
1a69e1e4 | 3431 | phex (regval, MIPS32_REGSIZE)); |
46cac009 AC |
3432 | write_register (argreg, regval); |
3433 | argreg++; | |
3434 | ||
3435 | /* Prevent subsequent floating point arguments from | |
3436 | being passed in floating point registers. */ | |
3437 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3438 | } | |
3439 | ||
3440 | len -= partial_len; | |
3441 | val += partial_len; | |
3442 | ||
3443 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3444 | will copy the next parameter. |
46cac009 | 3445 | |
6d82d43b AC |
3446 | In older ABIs, the caller reserved space for |
3447 | registers that contained arguments. This was loosely | |
3448 | refered to as their "home". Consequently, space is | |
3449 | always allocated. */ | |
46cac009 | 3450 | |
1a69e1e4 | 3451 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
3452 | } |
3453 | } | |
3454 | if (mips_debug) | |
3455 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3456 | } | |
3457 | ||
f10683bb | 3458 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3459 | |
46cac009 AC |
3460 | /* Return adjusted stack pointer. */ |
3461 | return sp; | |
3462 | } | |
3463 | ||
6d82d43b AC |
3464 | static enum return_value_convention |
3465 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
3466 | struct regcache *regcache, | |
47a35522 | 3467 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b AC |
3468 | { |
3469 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3470 | ||
3471 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3472 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3473 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3474 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3475 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3476 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3477 | { | |
3478 | /* A single-precision floating-point value. It fits in the | |
3479 | least significant part of FP0. */ | |
3480 | if (mips_debug) | |
3481 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3482 | mips_xfer_register (regcache, | |
f57d151a UW |
3483 | gdbarch_num_regs (current_gdbarch) |
3484 | + mips_regnum (current_gdbarch)->fp0, | |
6d82d43b | 3485 | TYPE_LENGTH (type), |
4c6b5505 UW |
3486 | gdbarch_byte_order (current_gdbarch), |
3487 | readbuf, writebuf, 0); | |
6d82d43b AC |
3488 | return RETURN_VALUE_REGISTER_CONVENTION; |
3489 | } | |
3490 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3491 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3492 | { | |
3493 | /* A double-precision floating-point value. The most | |
3494 | significant part goes in FP1, and the least significant in | |
3495 | FP0. */ | |
3496 | if (mips_debug) | |
3497 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
4c6b5505 | 3498 | switch (gdbarch_byte_order (current_gdbarch)) |
6d82d43b AC |
3499 | { |
3500 | case BFD_ENDIAN_LITTLE: | |
3501 | mips_xfer_register (regcache, | |
f57d151a UW |
3502 | gdbarch_num_regs (current_gdbarch) |
3503 | + mips_regnum (current_gdbarch)->fp0 + | |
4c6b5505 UW |
3504 | 0, 4, gdbarch_byte_order (current_gdbarch), |
3505 | readbuf, writebuf, 0); | |
6d82d43b | 3506 | mips_xfer_register (regcache, |
f57d151a UW |
3507 | gdbarch_num_regs (current_gdbarch) |
3508 | + mips_regnum (current_gdbarch)->fp0 + 1, | |
4c6b5505 UW |
3509 | 4, gdbarch_byte_order (current_gdbarch), |
3510 | readbuf, writebuf, 4); | |
6d82d43b AC |
3511 | break; |
3512 | case BFD_ENDIAN_BIG: | |
3513 | mips_xfer_register (regcache, | |
f57d151a UW |
3514 | gdbarch_num_regs (current_gdbarch) |
3515 | + mips_regnum (current_gdbarch)->fp0 + 1, | |
4c6b5505 UW |
3516 | 4, gdbarch_byte_order (current_gdbarch), |
3517 | readbuf, writebuf, 0); | |
6d82d43b | 3518 | mips_xfer_register (regcache, |
f57d151a UW |
3519 | gdbarch_num_regs (current_gdbarch) |
3520 | + mips_regnum (current_gdbarch)->fp0 + 0, | |
4c6b5505 UW |
3521 | 4, gdbarch_byte_order (current_gdbarch), |
3522 | readbuf, writebuf, 4); | |
6d82d43b AC |
3523 | break; |
3524 | default: | |
e2e0b3e5 | 3525 | internal_error (__FILE__, __LINE__, _("bad switch")); |
6d82d43b AC |
3526 | } |
3527 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3528 | } | |
3529 | #if 0 | |
3530 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3531 | && TYPE_NFIELDS (type) <= 2 | |
3532 | && TYPE_NFIELDS (type) >= 1 | |
3533 | && ((TYPE_NFIELDS (type) == 1 | |
3534 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3535 | == TYPE_CODE_FLT)) | |
3536 | || (TYPE_NFIELDS (type) == 2 | |
3537 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3538 | == TYPE_CODE_FLT) | |
3539 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3540 | == TYPE_CODE_FLT))) | |
3541 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3542 | { | |
3543 | /* A struct that contains one or two floats. Each value is part | |
3544 | in the least significant part of their floating point | |
3545 | register.. */ | |
870cd05e | 3546 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
3547 | int regnum; |
3548 | int field; | |
3549 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3550 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3551 | { | |
3552 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3553 | / TARGET_CHAR_BIT); | |
3554 | if (mips_debug) | |
3555 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3556 | offset); | |
f57d151a UW |
3557 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3558 | + regnum, | |
6d82d43b | 3559 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
4c6b5505 UW |
3560 | gdbarch_byte_order (current_gdbarch), |
3561 | readbuf, writebuf, offset); | |
6d82d43b AC |
3562 | } |
3563 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3564 | } | |
3565 | #endif | |
3566 | #if 0 | |
3567 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3568 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3569 | { | |
3570 | /* A structure or union. Extract the left justified value, | |
3571 | regardless of the byte order. I.e. DO NOT USE | |
3572 | mips_xfer_lower. */ | |
3573 | int offset; | |
3574 | int regnum; | |
4c7d22cb | 3575 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3576 | offset < TYPE_LENGTH (type); |
3577 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3578 | { | |
3579 | int xfer = register_size (current_gdbarch, regnum); | |
3580 | if (offset + xfer > TYPE_LENGTH (type)) | |
3581 | xfer = TYPE_LENGTH (type) - offset; | |
3582 | if (mips_debug) | |
3583 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3584 | offset, xfer, regnum); | |
f57d151a UW |
3585 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3586 | + regnum, xfer, | |
6d82d43b AC |
3587 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
3588 | } | |
3589 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3590 | } | |
3591 | #endif | |
3592 | else | |
3593 | { | |
3594 | /* A scalar extract each part but least-significant-byte | |
3595 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 3596 | the ISA. */ |
6d82d43b AC |
3597 | int offset; |
3598 | int regnum; | |
4c7d22cb | 3599 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3600 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 3601 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 3602 | { |
1a69e1e4 | 3603 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
3604 | if (offset + xfer > TYPE_LENGTH (type)) |
3605 | xfer = TYPE_LENGTH (type) - offset; | |
3606 | if (mips_debug) | |
3607 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3608 | offset, xfer, regnum); | |
f57d151a UW |
3609 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3610 | + regnum, xfer, | |
4c6b5505 UW |
3611 | gdbarch_byte_order (current_gdbarch), |
3612 | readbuf, writebuf, offset); | |
6d82d43b AC |
3613 | } |
3614 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3615 | } | |
3616 | } | |
3617 | ||
3618 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
3619 | ABI. */ | |
46cac009 AC |
3620 | |
3621 | static CORE_ADDR | |
7d9b040b | 3622 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3623 | struct regcache *regcache, CORE_ADDR bp_addr, |
3624 | int nargs, | |
3625 | struct value **args, CORE_ADDR sp, | |
3626 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
3627 | { |
3628 | int argreg; | |
3629 | int float_argreg; | |
3630 | int argnum; | |
3631 | int len = 0; | |
3632 | int stack_offset = 0; | |
480d3dd2 | 3633 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3634 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 3635 | |
25ab4790 AC |
3636 | /* For shared libraries, "t9" needs to point at the function |
3637 | address. */ | |
4c7d22cb | 3638 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3639 | |
3640 | /* Set the return address register to point to the entry point of | |
3641 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3642 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3643 | |
46cac009 AC |
3644 | /* First ensure that the stack and structure return address (if any) |
3645 | are properly aligned. The stack has to be at least 64-bit | |
3646 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3647 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3648 | aligned, so we round to this widest known alignment. */ | |
3649 | ||
5b03f266 AC |
3650 | sp = align_down (sp, 16); |
3651 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3652 | |
3653 | /* Now make space on the stack for the args. */ | |
3654 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3655 | { |
3656 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3657 | int arglen = TYPE_LENGTH (arg_type); | |
3658 | ||
968b5391 | 3659 | /* Allocate space on the stack. */ |
1a69e1e4 | 3660 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 3661 | } |
5b03f266 | 3662 | sp -= align_up (len, 16); |
46cac009 AC |
3663 | |
3664 | if (mips_debug) | |
6d82d43b | 3665 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3666 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
3667 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
3668 | |
3669 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3670 | argreg = MIPS_A0_REGNUM; |
56cea623 | 3671 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
3672 | |
3673 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3674 | if (struct_return) | |
3675 | { | |
3676 | if (mips_debug) | |
3677 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3678 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
3679 | argreg, paddr_nz (struct_addr)); |
3680 | write_register (argreg++, struct_addr); | |
1a69e1e4 | 3681 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
3682 | } |
3683 | ||
3684 | /* Now load as many as possible of the first arguments into | |
3685 | registers, and push the rest onto the stack. Loop thru args | |
3686 | from first to last. */ | |
3687 | for (argnum = 0; argnum < nargs; argnum++) | |
3688 | { | |
47a35522 | 3689 | const gdb_byte *val; |
46cac009 | 3690 | struct value *arg = args[argnum]; |
4991999e | 3691 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
3692 | int len = TYPE_LENGTH (arg_type); |
3693 | enum type_code typecode = TYPE_CODE (arg_type); | |
3694 | ||
3695 | if (mips_debug) | |
3696 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3697 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
3698 | argnum + 1, len, (int) typecode); |
3699 | ||
47a35522 | 3700 | val = value_contents (arg); |
ebafbe83 | 3701 | |
ebafbe83 MS |
3702 | /* Floating point arguments passed in registers have to be |
3703 | treated specially. On 32-bit architectures, doubles | |
3704 | are passed in register pairs; the even register gets | |
3705 | the low word, and the odd register gets the high word. | |
3706 | On O32/O64, the first two floating point arguments are | |
3707 | also copied to general registers, because MIPS16 functions | |
3708 | don't use float registers for arguments. This duplication of | |
3709 | arguments in general registers can't hurt non-MIPS16 functions | |
3710 | because those registers are normally skipped. */ | |
3711 | ||
3712 | if (fp_register_arg_p (typecode, arg_type) | |
3713 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3714 | { | |
2afd3f0a MR |
3715 | LONGEST regval = extract_unsigned_integer (val, len); |
3716 | if (mips_debug) | |
3717 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3718 | float_argreg, phex (regval, len)); | |
3719 | write_register (float_argreg++, regval); | |
3720 | if (mips_debug) | |
3721 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3722 | argreg, phex (regval, len)); | |
3723 | write_register (argreg, regval); | |
3724 | argreg++; | |
ebafbe83 | 3725 | /* Reserve space for the FP register. */ |
1a69e1e4 | 3726 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
3727 | } |
3728 | else | |
3729 | { | |
3730 | /* Copy the argument to general registers or the stack in | |
3731 | register-sized pieces. Large arguments are split between | |
3732 | registers and stack. */ | |
1a69e1e4 | 3733 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
3734 | are treated specially: Irix cc passes them in registers |
3735 | where gcc sometimes puts them on the stack. For maximum | |
3736 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
3737 | int odd_sized_struct = (len > MIPS64_REGSIZE |
3738 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
3739 | while (len > 0) |
3740 | { | |
3741 | /* Remember if the argument was written to the stack. */ | |
3742 | int stack_used_p = 0; | |
1a69e1e4 | 3743 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
3744 | |
3745 | if (mips_debug) | |
3746 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3747 | partial_len); | |
3748 | ||
3749 | /* Write this portion of the argument to the stack. */ | |
3750 | if (argreg > MIPS_LAST_ARG_REGNUM | |
968b5391 | 3751 | || odd_sized_struct) |
ebafbe83 MS |
3752 | { |
3753 | /* Should shorter than int integer values be | |
3754 | promoted to int before being stored? */ | |
3755 | int longword_offset = 0; | |
3756 | CORE_ADDR addr; | |
3757 | stack_used_p = 1; | |
4c6b5505 | 3758 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 3759 | { |
1a69e1e4 DJ |
3760 | if ((typecode == TYPE_CODE_INT |
3761 | || typecode == TYPE_CODE_PTR | |
3762 | || typecode == TYPE_CODE_FLT) | |
3763 | && len <= 4) | |
3764 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
3765 | } |
3766 | ||
3767 | if (mips_debug) | |
3768 | { | |
3769 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3770 | paddr_nz (stack_offset)); | |
3771 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3772 | paddr_nz (longword_offset)); | |
3773 | } | |
3774 | ||
3775 | addr = sp + stack_offset + longword_offset; | |
3776 | ||
3777 | if (mips_debug) | |
3778 | { | |
3779 | int i; | |
6d82d43b | 3780 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
ebafbe83 MS |
3781 | paddr_nz (addr)); |
3782 | for (i = 0; i < partial_len; i++) | |
3783 | { | |
6d82d43b | 3784 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
3785 | val[i] & 0xff); |
3786 | } | |
3787 | } | |
3788 | write_memory (addr, val, partial_len); | |
3789 | } | |
3790 | ||
3791 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3792 | structs may go thru BOTH paths. */ |
ebafbe83 | 3793 | /* Write this portion of the argument to a general |
6d82d43b | 3794 | purpose register. */ |
968b5391 | 3795 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
ebafbe83 MS |
3796 | { |
3797 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3798 | /* Value may need to be sign extended, because |
1b13c4f6 | 3799 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
3800 | |
3801 | /* A non-floating-point argument being passed in a | |
3802 | general register. If a struct or union, and if | |
3803 | the remaining length is smaller than the register | |
3804 | size, we have to adjust the register value on | |
3805 | big endian targets. | |
3806 | ||
3807 | It does not seem to be necessary to do the | |
401835eb | 3808 | same for integral types. */ |
480d3dd2 | 3809 | |
4c6b5505 | 3810 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3811 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3812 | && (typecode == TYPE_CODE_STRUCT |
3813 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3814 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3815 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
3816 | |
3817 | if (mips_debug) | |
3818 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3819 | argreg, | |
1a69e1e4 | 3820 | phex (regval, MIPS64_REGSIZE)); |
ebafbe83 MS |
3821 | write_register (argreg, regval); |
3822 | argreg++; | |
3823 | ||
3824 | /* Prevent subsequent floating point arguments from | |
3825 | being passed in floating point registers. */ | |
3826 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3827 | } | |
3828 | ||
3829 | len -= partial_len; | |
3830 | val += partial_len; | |
3831 | ||
3832 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3833 | will copy the next parameter. |
ebafbe83 | 3834 | |
6d82d43b AC |
3835 | In older ABIs, the caller reserved space for |
3836 | registers that contained arguments. This was loosely | |
3837 | refered to as their "home". Consequently, space is | |
3838 | always allocated. */ | |
ebafbe83 | 3839 | |
1a69e1e4 | 3840 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
3841 | } |
3842 | } | |
3843 | if (mips_debug) | |
3844 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3845 | } | |
3846 | ||
f10683bb | 3847 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3848 | |
ebafbe83 MS |
3849 | /* Return adjusted stack pointer. */ |
3850 | return sp; | |
3851 | } | |
3852 | ||
9c8fdbfa AC |
3853 | static enum return_value_convention |
3854 | mips_o64_return_value (struct gdbarch *gdbarch, | |
3855 | struct type *type, struct regcache *regcache, | |
47a35522 | 3856 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3857 | { |
7a076fd2 FF |
3858 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3859 | ||
3860 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3861 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3862 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3863 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3864 | else if (fp_register_arg_p (TYPE_CODE (type), type)) | |
3865 | { | |
3866 | /* A floating-point value. It fits in the least significant | |
3867 | part of FP0. */ | |
3868 | if (mips_debug) | |
3869 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3870 | mips_xfer_register (regcache, | |
f57d151a UW |
3871 | gdbarch_num_regs (current_gdbarch) |
3872 | + mips_regnum (current_gdbarch)->fp0, | |
7a076fd2 | 3873 | TYPE_LENGTH (type), |
4c6b5505 UW |
3874 | gdbarch_byte_order (current_gdbarch), |
3875 | readbuf, writebuf, 0); | |
7a076fd2 FF |
3876 | return RETURN_VALUE_REGISTER_CONVENTION; |
3877 | } | |
3878 | else | |
3879 | { | |
3880 | /* A scalar extract each part but least-significant-byte | |
3881 | justified. */ | |
3882 | int offset; | |
3883 | int regnum; | |
3884 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
3885 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 3886 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 3887 | { |
1a69e1e4 | 3888 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
3889 | if (offset + xfer > TYPE_LENGTH (type)) |
3890 | xfer = TYPE_LENGTH (type) - offset; | |
3891 | if (mips_debug) | |
3892 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3893 | offset, xfer, regnum); | |
f57d151a UW |
3894 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3895 | + regnum, xfer, | |
4c6b5505 UW |
3896 | gdbarch_byte_order (current_gdbarch), |
3897 | readbuf, writebuf, offset); | |
7a076fd2 FF |
3898 | } |
3899 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3900 | } | |
6d82d43b AC |
3901 | } |
3902 | ||
dd824b04 DJ |
3903 | /* Floating point register management. |
3904 | ||
3905 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
3906 | 64bit operations, these early MIPS cpus treat fp register pairs | |
3907 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
3908 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
3909 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
3910 | double precision floats into two 32-bit chunks and store them in | |
3911 | consecutive fp regs. To display 64-bit floats stored in this | |
3912 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
3913 | Throw in user-configurable endianness and you have a real mess. | |
3914 | ||
3915 | The way this works is: | |
3916 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
3917 | double-precision value will be split across two logical registers. | |
3918 | The lower-numbered logical register will hold the low-order bits, | |
3919 | regardless of the processor's endianness. | |
3920 | - If we are on a 64-bit processor, and we are looking for a | |
3921 | single-precision value, it will be in the low ordered bits | |
3922 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
3923 | save slot in memory. | |
3924 | - If we are in 64-bit mode, everything is straightforward. | |
3925 | ||
3926 | Note that this code only deals with "live" registers at the top of the | |
3927 | stack. We will attempt to deal with saved registers later, when | |
3928 | the raw/cooked register interface is in place. (We need a general | |
3929 | interface that can deal with dynamic saved register sizes -- fp | |
3930 | regs could be 32 bits wide in one frame and 64 on the frame above | |
3931 | and below). */ | |
3932 | ||
67b2c998 DJ |
3933 | static struct type * |
3934 | mips_float_register_type (void) | |
3935 | { | |
8da61cc4 | 3936 | return builtin_type_ieee_single; |
67b2c998 DJ |
3937 | } |
3938 | ||
3939 | static struct type * | |
3940 | mips_double_register_type (void) | |
3941 | { | |
8da61cc4 | 3942 | return builtin_type_ieee_double; |
67b2c998 DJ |
3943 | } |
3944 | ||
dd824b04 DJ |
3945 | /* Copy a 32-bit single-precision value from the current frame |
3946 | into rare_buffer. */ | |
3947 | ||
3948 | static void | |
e11c53d2 | 3949 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 3950 | gdb_byte *rare_buffer) |
dd824b04 | 3951 | { |
719ec221 | 3952 | int raw_size = register_size (current_gdbarch, regno); |
47a35522 | 3953 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 3954 | |
e11c53d2 | 3955 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 UW |
3956 | error (_("can't read register %d (%s)"), |
3957 | regno, gdbarch_register_name (current_gdbarch, regno)); | |
dd824b04 DJ |
3958 | if (raw_size == 8) |
3959 | { | |
3960 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 3961 | 32 bits. */ |
dd824b04 DJ |
3962 | int offset; |
3963 | ||
4c6b5505 | 3964 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
3965 | offset = 4; |
3966 | else | |
3967 | offset = 0; | |
3968 | ||
3969 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
3970 | } | |
3971 | else | |
3972 | { | |
3973 | memcpy (rare_buffer, raw_buffer, 4); | |
3974 | } | |
3975 | } | |
3976 | ||
3977 | /* Copy a 64-bit double-precision value from the current frame into | |
3978 | rare_buffer. This may include getting half of it from the next | |
3979 | register. */ | |
3980 | ||
3981 | static void | |
e11c53d2 | 3982 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 3983 | gdb_byte *rare_buffer) |
dd824b04 | 3984 | { |
719ec221 | 3985 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
3986 | |
3987 | if (raw_size == 8 && !mips2_fp_compat ()) | |
3988 | { | |
3989 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 3990 | all 64 bits. */ |
e11c53d2 | 3991 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 UW |
3992 | error (_("can't read register %d (%s)"), |
3993 | regno, gdbarch_register_name (current_gdbarch, regno)); | |
dd824b04 DJ |
3994 | } |
3995 | else | |
3996 | { | |
56cea623 | 3997 | if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) |
dd824b04 | 3998 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
3999 | _("mips_read_fp_register_double: bad access to " |
4000 | "odd-numbered FP register")); | |
dd824b04 DJ |
4001 | |
4002 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4003 | each register. */ |
4c6b5505 | 4004 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 4005 | { |
e11c53d2 AC |
4006 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4007 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4008 | } |
361d1df0 | 4009 | else |
dd824b04 | 4010 | { |
e11c53d2 AC |
4011 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4012 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4013 | } |
4014 | } | |
4015 | } | |
4016 | ||
c906108c | 4017 | static void |
e11c53d2 AC |
4018 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4019 | int regnum) | |
c5aa993b | 4020 | { /* do values for FP (float) regs */ |
47a35522 | 4021 | gdb_byte *raw_buffer; |
3903d437 AC |
4022 | double doub, flt1; /* doubles extracted from raw hex data */ |
4023 | int inv1, inv2; | |
c5aa993b | 4024 | |
47a35522 MK |
4025 | raw_buffer = alloca (2 * register_size (current_gdbarch, |
4026 | mips_regnum (current_gdbarch)->fp0)); | |
c906108c | 4027 | |
c9f4d572 UW |
4028 | fprintf_filtered (file, "%s:", |
4029 | gdbarch_register_name (current_gdbarch, regnum)); | |
4030 | fprintf_filtered (file, "%*s", | |
4031 | 4 - (int) strlen (gdbarch_register_name | |
4032 | (current_gdbarch, regnum)), | |
e11c53d2 | 4033 | ""); |
f0ef6b29 | 4034 | |
719ec221 | 4035 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ()) |
c906108c | 4036 | { |
f0ef6b29 KB |
4037 | /* 4-byte registers: Print hex and floating. Also print even |
4038 | numbered registers as doubles. */ | |
e11c53d2 | 4039 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4040 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4041 | |
6d82d43b AC |
4042 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', |
4043 | file); | |
dd824b04 | 4044 | |
e11c53d2 | 4045 | fprintf_filtered (file, " flt: "); |
1adad886 | 4046 | if (inv1) |
e11c53d2 | 4047 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4048 | else |
e11c53d2 | 4049 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4050 | |
f0ef6b29 KB |
4051 | if (regnum % 2 == 0) |
4052 | { | |
e11c53d2 | 4053 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 | 4054 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
6d82d43b | 4055 | &inv2); |
1adad886 | 4056 | |
e11c53d2 | 4057 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4058 | if (inv2) |
e11c53d2 | 4059 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4060 | else |
e11c53d2 | 4061 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4062 | } |
c906108c SS |
4063 | } |
4064 | else | |
dd824b04 | 4065 | { |
f0ef6b29 | 4066 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4067 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4068 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4069 | |
e11c53d2 | 4070 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4071 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4072 | ||
361d1df0 | 4073 | |
6d82d43b AC |
4074 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', |
4075 | file); | |
f0ef6b29 | 4076 | |
e11c53d2 | 4077 | fprintf_filtered (file, " flt: "); |
1adad886 | 4078 | if (inv1) |
e11c53d2 | 4079 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4080 | else |
e11c53d2 | 4081 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4082 | |
e11c53d2 | 4083 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4084 | if (inv2) |
e11c53d2 | 4085 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4086 | else |
e11c53d2 | 4087 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4088 | } |
4089 | } | |
4090 | ||
4091 | static void | |
e11c53d2 | 4092 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 4093 | int regnum) |
f0ef6b29 | 4094 | { |
a4b8ebc8 | 4095 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4096 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4097 | int offset; |
1adad886 | 4098 | |
7b9ee6a8 | 4099 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4100 | { |
e11c53d2 | 4101 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4102 | return; |
4103 | } | |
4104 | ||
4105 | /* Get the data in raw format. */ | |
e11c53d2 | 4106 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4107 | { |
c9f4d572 UW |
4108 | fprintf_filtered (file, "%s: [Invalid]", |
4109 | gdbarch_register_name (current_gdbarch, regnum)); | |
f0ef6b29 | 4110 | return; |
c906108c | 4111 | } |
f0ef6b29 | 4112 | |
c9f4d572 | 4113 | fputs_filtered (gdbarch_register_name (current_gdbarch, regnum), file); |
f0ef6b29 KB |
4114 | |
4115 | /* The problem with printing numeric register names (r26, etc.) is that | |
4116 | the user can't use them on input. Probably the best solution is to | |
4117 | fix it so that either the numeric or the funky (a2, etc.) names | |
4118 | are accepted on input. */ | |
4119 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4120 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4121 | else |
e11c53d2 | 4122 | fprintf_filtered (file, ": "); |
f0ef6b29 | 4123 | |
4c6b5505 | 4124 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b AC |
4125 | offset = |
4126 | register_size (current_gdbarch, | |
4127 | regnum) - register_size (current_gdbarch, regnum); | |
f0ef6b29 KB |
4128 | else |
4129 | offset = 0; | |
4130 | ||
6d82d43b | 4131 | print_scalar_formatted (raw_buffer + offset, |
7b9ee6a8 | 4132 | register_type (gdbarch, regnum), 'x', 0, |
6d82d43b | 4133 | file); |
c906108c SS |
4134 | } |
4135 | ||
f0ef6b29 KB |
4136 | /* Replacement for generic do_registers_info. |
4137 | Print regs in pretty columns. */ | |
4138 | ||
4139 | static int | |
e11c53d2 AC |
4140 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4141 | int regnum) | |
f0ef6b29 | 4142 | { |
e11c53d2 AC |
4143 | fprintf_filtered (file, " "); |
4144 | mips_print_fp_register (file, frame, regnum); | |
4145 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4146 | return regnum + 1; |
4147 | } | |
4148 | ||
4149 | ||
c906108c SS |
4150 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4151 | ||
4152 | static int | |
e11c53d2 | 4153 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4154 | int start_regnum) |
c906108c | 4155 | { |
a4b8ebc8 | 4156 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4157 | /* do values for GP (int) regs */ |
47a35522 | 4158 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 4159 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4160 | int col, byte; |
a4b8ebc8 | 4161 | int regnum; |
c906108c SS |
4162 | |
4163 | /* For GP registers, we print a separate row of names above the vals */ | |
a4b8ebc8 | 4164 | for (col = 0, regnum = start_regnum; |
f57d151a UW |
4165 | col < ncols && regnum < gdbarch_num_regs (current_gdbarch) |
4166 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4167 | regnum++) | |
c906108c | 4168 | { |
c9f4d572 | 4169 | if (*gdbarch_register_name (current_gdbarch, regnum) == '\0') |
c5aa993b | 4170 | continue; /* unused register */ |
7b9ee6a8 | 4171 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4172 | TYPE_CODE_FLT) |
c5aa993b | 4173 | break; /* end the row: reached FP register */ |
0cc93a06 DJ |
4174 | /* Large registers are handled separately. */ |
4175 | if (register_size (current_gdbarch, regnum) | |
4176 | > mips_abi_regsize (current_gdbarch)) | |
4177 | { | |
4178 | if (col > 0) | |
4179 | break; /* End the row before this register. */ | |
4180 | ||
4181 | /* Print this register on a row by itself. */ | |
4182 | mips_print_register (file, frame, regnum); | |
4183 | fprintf_filtered (file, "\n"); | |
4184 | return regnum + 1; | |
4185 | } | |
d05f6826 DJ |
4186 | if (col == 0) |
4187 | fprintf_filtered (file, " "); | |
6d82d43b | 4188 | fprintf_filtered (file, |
d5ac5a39 | 4189 | mips_abi_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", |
c9f4d572 | 4190 | gdbarch_register_name (current_gdbarch, regnum)); |
c906108c SS |
4191 | col++; |
4192 | } | |
d05f6826 DJ |
4193 | |
4194 | if (col == 0) | |
4195 | return regnum; | |
4196 | ||
a4b8ebc8 | 4197 | /* print the R0 to R31 names */ |
f57d151a UW |
4198 | if ((start_regnum % gdbarch_num_regs (current_gdbarch)) < MIPS_NUMREGS) |
4199 | fprintf_filtered (file, "\n R%-4d", | |
4200 | start_regnum % gdbarch_num_regs (current_gdbarch)); | |
20e6603c AC |
4201 | else |
4202 | fprintf_filtered (file, "\n "); | |
c906108c | 4203 | |
c906108c | 4204 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4205 | for (col = 0, regnum = start_regnum; |
f57d151a UW |
4206 | col < ncols && regnum < gdbarch_num_regs (current_gdbarch) |
4207 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4208 | regnum++) | |
c906108c | 4209 | { |
c9f4d572 | 4210 | if (*gdbarch_register_name (current_gdbarch, regnum) == '\0') |
c5aa993b | 4211 | continue; /* unused register */ |
7b9ee6a8 | 4212 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4213 | TYPE_CODE_FLT) |
c5aa993b | 4214 | break; /* end row: reached FP register */ |
0cc93a06 DJ |
4215 | if (register_size (current_gdbarch, regnum) |
4216 | > mips_abi_regsize (current_gdbarch)) | |
4217 | break; /* End row: large register. */ | |
4218 | ||
c906108c | 4219 | /* OK: get the data in raw format. */ |
e11c53d2 | 4220 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 UW |
4221 | error (_("can't read register %d (%s)"), |
4222 | regnum, gdbarch_register_name (current_gdbarch, regnum)); | |
c906108c | 4223 | /* pad small registers */ |
4246e332 | 4224 | for (byte = 0; |
d5ac5a39 | 4225 | byte < (mips_abi_regsize (current_gdbarch) |
6d82d43b | 4226 | - register_size (current_gdbarch, regnum)); byte++) |
c906108c SS |
4227 | printf_filtered (" "); |
4228 | /* Now print the register value in hex, endian order. */ | |
4c6b5505 | 4229 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b AC |
4230 | for (byte = |
4231 | register_size (current_gdbarch, | |
4232 | regnum) - register_size (current_gdbarch, regnum); | |
4233 | byte < register_size (current_gdbarch, regnum); byte++) | |
47a35522 | 4234 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 4235 | else |
c73e8f27 | 4236 | for (byte = register_size (current_gdbarch, regnum) - 1; |
6d82d43b | 4237 | byte >= 0; byte--) |
47a35522 | 4238 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 4239 | fprintf_filtered (file, " "); |
c906108c SS |
4240 | col++; |
4241 | } | |
c5aa993b | 4242 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4243 | fprintf_filtered (file, "\n"); |
c906108c SS |
4244 | |
4245 | return regnum; | |
4246 | } | |
4247 | ||
4248 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4249 | ||
bf1f5b4c | 4250 | static void |
e11c53d2 AC |
4251 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4252 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4253 | { |
c5aa993b | 4254 | if (regnum != -1) /* do one specified register */ |
c906108c | 4255 | { |
f57d151a | 4256 | gdb_assert (regnum >= gdbarch_num_regs (current_gdbarch)); |
c9f4d572 | 4257 | if (*(gdbarch_register_name (current_gdbarch, regnum)) == '\0') |
8a3fe4f8 | 4258 | error (_("Not a valid register for the current processor type")); |
c906108c | 4259 | |
0cc93a06 | 4260 | mips_print_register (file, frame, regnum); |
e11c53d2 | 4261 | fprintf_filtered (file, "\n"); |
c906108c | 4262 | } |
c5aa993b JM |
4263 | else |
4264 | /* do all (or most) registers */ | |
c906108c | 4265 | { |
f57d151a UW |
4266 | regnum = gdbarch_num_regs (current_gdbarch); |
4267 | while (regnum < gdbarch_num_regs (current_gdbarch) | |
4268 | + gdbarch_num_pseudo_regs (current_gdbarch)) | |
c906108c | 4269 | { |
7b9ee6a8 | 4270 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4271 | TYPE_CODE_FLT) |
e11c53d2 AC |
4272 | { |
4273 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4274 | regnum = print_fp_register_row (file, frame, regnum); | |
4275 | else | |
4276 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4277 | } | |
c906108c | 4278 | else |
e11c53d2 | 4279 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4280 | } |
4281 | } | |
4282 | } | |
4283 | ||
c906108c SS |
4284 | /* Is this a branch with a delay slot? */ |
4285 | ||
c906108c | 4286 | static int |
acdb74a0 | 4287 | is_delayed (unsigned long insn) |
c906108c SS |
4288 | { |
4289 | int i; | |
4290 | for (i = 0; i < NUMOPCODES; ++i) | |
4291 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4292 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4293 | break; | |
4294 | return (i < NUMOPCODES | |
4295 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4296 | | INSN_COND_BRANCH_DELAY | |
4297 | | INSN_COND_BRANCH_LIKELY))); | |
4298 | } | |
4299 | ||
4300 | int | |
3352ef37 AC |
4301 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
4302 | struct frame_info *frame) | |
c906108c | 4303 | { |
3352ef37 | 4304 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 4305 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
4306 | |
4307 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4308 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4309 | return 0; |
4310 | ||
06648491 MK |
4311 | if (!breakpoint_here_p (pc + 4)) |
4312 | return 0; | |
4313 | ||
3352ef37 AC |
4314 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
4315 | /* If error reading memory, guess that it is not a delayed | |
4316 | branch. */ | |
c906108c | 4317 | return 0; |
4c7d22cb | 4318 | return is_delayed (extract_unsigned_integer (buf, sizeof buf)); |
c906108c SS |
4319 | } |
4320 | ||
6d82d43b AC |
4321 | /* To skip prologues, I use this predicate. Returns either PC itself |
4322 | if the code at PC does not look like a function prologue; otherwise | |
4323 | returns an address that (if we're lucky) follows the prologue. If | |
4324 | LENIENT, then we must skip everything which is involved in setting | |
4325 | up the frame (it's OK to skip more, just so long as we don't skip | |
4326 | anything which might clobber the registers which are being saved. | |
4327 | We must skip more in the case where part of the prologue is in the | |
4328 | delay slot of a non-prologue instruction). */ | |
4329 | ||
4330 | static CORE_ADDR | |
4331 | mips_skip_prologue (CORE_ADDR pc) | |
4332 | { | |
8b622e6a AC |
4333 | CORE_ADDR limit_pc; |
4334 | CORE_ADDR func_addr; | |
4335 | ||
6d82d43b AC |
4336 | /* See if we can determine the end of the prologue via the symbol table. |
4337 | If so, then return either PC, or the PC after the prologue, whichever | |
4338 | is greater. */ | |
8b622e6a AC |
4339 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4340 | { | |
4341 | CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr); | |
4342 | if (post_prologue_pc != 0) | |
4343 | return max (pc, post_prologue_pc); | |
4344 | } | |
6d82d43b AC |
4345 | |
4346 | /* Can't determine prologue from the symbol table, need to examine | |
4347 | instructions. */ | |
4348 | ||
98b4dd94 JB |
4349 | /* Find an upper limit on the function prologue using the debug |
4350 | information. If the debug information could not be used to provide | |
4351 | that bound, then use an arbitrary large number as the upper bound. */ | |
4352 | limit_pc = skip_prologue_using_sal (pc); | |
4353 | if (limit_pc == 0) | |
4354 | limit_pc = pc + 100; /* Magic. */ | |
4355 | ||
0fe7e7c8 | 4356 | if (mips_pc_is_mips16 (pc)) |
a65bbe44 | 4357 | return mips16_scan_prologue (pc, limit_pc, NULL, NULL); |
6d82d43b | 4358 | else |
a65bbe44 | 4359 | return mips32_scan_prologue (pc, limit_pc, NULL, NULL); |
88658117 AC |
4360 | } |
4361 | ||
a5ea2558 AC |
4362 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4363 | used for all MIPS-specific commands. */ | |
4364 | ||
a5ea2558 | 4365 | static void |
acdb74a0 | 4366 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4367 | { |
4368 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4369 | } | |
4370 | ||
a5ea2558 | 4371 | static void |
acdb74a0 | 4372 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 4373 | { |
6d82d43b AC |
4374 | printf_unfiltered |
4375 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
4376 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
4377 | } | |
4378 | ||
c906108c SS |
4379 | /* Commands to show/set the MIPS FPU type. */ |
4380 | ||
c906108c | 4381 | static void |
acdb74a0 | 4382 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4383 | { |
c906108c SS |
4384 | char *fpu; |
4385 | switch (MIPS_FPU_TYPE) | |
4386 | { | |
4387 | case MIPS_FPU_SINGLE: | |
4388 | fpu = "single-precision"; | |
4389 | break; | |
4390 | case MIPS_FPU_DOUBLE: | |
4391 | fpu = "double-precision"; | |
4392 | break; | |
4393 | case MIPS_FPU_NONE: | |
4394 | fpu = "absent (none)"; | |
4395 | break; | |
93d56215 | 4396 | default: |
e2e0b3e5 | 4397 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
4398 | } |
4399 | if (mips_fpu_type_auto) | |
6d82d43b AC |
4400 | printf_unfiltered |
4401 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4402 | fpu); | |
c906108c | 4403 | else |
6d82d43b AC |
4404 | printf_unfiltered |
4405 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
4406 | } |
4407 | ||
4408 | ||
c906108c | 4409 | static void |
acdb74a0 | 4410 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 4411 | { |
6d82d43b AC |
4412 | printf_unfiltered |
4413 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
4414 | show_mipsfpu_command (args, from_tty); |
4415 | } | |
4416 | ||
c906108c | 4417 | static void |
acdb74a0 | 4418 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 4419 | { |
8d5838b5 AC |
4420 | struct gdbarch_info info; |
4421 | gdbarch_info_init (&info); | |
c906108c SS |
4422 | mips_fpu_type = MIPS_FPU_SINGLE; |
4423 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4424 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4425 | instead of relying on globals. Doing that would let generic code | |
4426 | handle the search for this specific architecture. */ | |
4427 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4428 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4429 | } |
4430 | ||
c906108c | 4431 | static void |
acdb74a0 | 4432 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 4433 | { |
8d5838b5 AC |
4434 | struct gdbarch_info info; |
4435 | gdbarch_info_init (&info); | |
c906108c SS |
4436 | mips_fpu_type = MIPS_FPU_DOUBLE; |
4437 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4438 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4439 | instead of relying on globals. Doing that would let generic code | |
4440 | handle the search for this specific architecture. */ | |
4441 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4442 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4443 | } |
4444 | ||
c906108c | 4445 | static void |
acdb74a0 | 4446 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 4447 | { |
8d5838b5 AC |
4448 | struct gdbarch_info info; |
4449 | gdbarch_info_init (&info); | |
c906108c SS |
4450 | mips_fpu_type = MIPS_FPU_NONE; |
4451 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4452 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4453 | instead of relying on globals. Doing that would let generic code | |
4454 | handle the search for this specific architecture. */ | |
4455 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4456 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4457 | } |
4458 | ||
c906108c | 4459 | static void |
acdb74a0 | 4460 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
4461 | { |
4462 | mips_fpu_type_auto = 1; | |
4463 | } | |
4464 | ||
c906108c | 4465 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
4466 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
4467 | the relevant processor still exists (it dates back to '94) and | |
4468 | secondly this is not the way to do this. The processor type should | |
4469 | be set by forcing an architecture change. */ | |
c906108c | 4470 | |
691c0433 AC |
4471 | void |
4472 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 4473 | { |
691c0433 | 4474 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
4475 | CORE_ADDR prid; |
4476 | ||
a5c9623c | 4477 | prid = read_register (MIPS_PRID_REGNUM); |
c906108c SS |
4478 | |
4479 | if ((prid & ~0xf) == 0x700) | |
691c0433 | 4480 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
4481 | } |
4482 | ||
4483 | /* Just like reinit_frame_cache, but with the right arguments to be | |
4484 | callable as an sfunc. */ | |
4485 | ||
4486 | static void | |
acdb74a0 AC |
4487 | reinit_frame_cache_sfunc (char *args, int from_tty, |
4488 | struct cmd_list_element *c) | |
c906108c SS |
4489 | { |
4490 | reinit_frame_cache (); | |
4491 | } | |
4492 | ||
a89aa300 AC |
4493 | static int |
4494 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 4495 | { |
e5ab0dce | 4496 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 4497 | |
d31431ed AC |
4498 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
4499 | disassembler needs to be able to locally determine the ISA, and | |
4500 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
4501 | work. */ | |
ec4045ea AC |
4502 | if (mips_pc_is_mips16 (memaddr)) |
4503 | info->mach = bfd_mach_mips16; | |
c906108c SS |
4504 | |
4505 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 4506 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 4507 | |
e5ab0dce | 4508 | /* Set the disassembler options. */ |
6d82d43b | 4509 | if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64) |
e5ab0dce AC |
4510 | { |
4511 | /* Set up the disassembler info, so that we get the right | |
6d82d43b | 4512 | register names from libopcodes. */ |
e5ab0dce AC |
4513 | if (tdep->mips_abi == MIPS_ABI_N32) |
4514 | info->disassembler_options = "gpr-names=n32"; | |
4515 | else | |
4516 | info->disassembler_options = "gpr-names=64"; | |
4517 | info->flavour = bfd_target_elf_flavour; | |
4518 | } | |
4519 | else | |
4520 | /* This string is not recognized explicitly by the disassembler, | |
4521 | but it tells the disassembler to not try to guess the ABI from | |
4522 | the bfd elf headers, such that, if the user overrides the ABI | |
4523 | of a program linked as NewABI, the disassembly will follow the | |
4524 | register naming conventions specified by the user. */ | |
4525 | info->disassembler_options = "gpr-names=32"; | |
4526 | ||
c906108c | 4527 | /* Call the appropriate disassembler based on the target endian-ness. */ |
4c6b5505 | 4528 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
c906108c SS |
4529 | return print_insn_big_mips (memaddr, info); |
4530 | else | |
4531 | return print_insn_little_mips (memaddr, info); | |
4532 | } | |
4533 | ||
3b3b875c UW |
4534 | /* This function implements gdbarch_breakpoint_from_pc. It uses the program |
4535 | counter value to determine whether a 16- or 32-bit breakpoint should be used. | |
4536 | It returns a pointer to a string of bytes that encode a breakpoint | |
4537 | instruction, stores the length of the string to *lenptr, and adjusts pc (if | |
4538 | necessary) to point to the actual memory location where the breakpoint | |
4539 | should be inserted. */ | |
c906108c | 4540 | |
47a35522 | 4541 | static const gdb_byte * |
6d82d43b | 4542 | mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 4543 | { |
4c6b5505 | 4544 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 4545 | { |
0fe7e7c8 | 4546 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4547 | { |
47a35522 | 4548 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 4549 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4550 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
4551 | return mips16_big_breakpoint; |
4552 | } | |
4553 | else | |
4554 | { | |
aaab4dba AC |
4555 | /* The IDT board uses an unusual breakpoint value, and |
4556 | sometimes gets confused when it sees the usual MIPS | |
4557 | breakpoint instruction. */ | |
47a35522 MK |
4558 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
4559 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
4560 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 4561 | |
c5aa993b | 4562 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
4563 | |
4564 | if (strcmp (target_shortname, "mips") == 0) | |
4565 | return idt_big_breakpoint; | |
4566 | else if (strcmp (target_shortname, "ddb") == 0 | |
4567 | || strcmp (target_shortname, "pmon") == 0 | |
4568 | || strcmp (target_shortname, "lsi") == 0) | |
4569 | return pmon_big_breakpoint; | |
4570 | else | |
4571 | return big_breakpoint; | |
4572 | } | |
4573 | } | |
4574 | else | |
4575 | { | |
0fe7e7c8 | 4576 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4577 | { |
47a35522 | 4578 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 4579 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4580 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
4581 | return mips16_little_breakpoint; |
4582 | } | |
4583 | else | |
4584 | { | |
47a35522 MK |
4585 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
4586 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
4587 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 4588 | |
c5aa993b | 4589 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
4590 | |
4591 | if (strcmp (target_shortname, "mips") == 0) | |
4592 | return idt_little_breakpoint; | |
4593 | else if (strcmp (target_shortname, "ddb") == 0 | |
4594 | || strcmp (target_shortname, "pmon") == 0 | |
4595 | || strcmp (target_shortname, "lsi") == 0) | |
4596 | return pmon_little_breakpoint; | |
4597 | else | |
4598 | return little_breakpoint; | |
4599 | } | |
4600 | } | |
4601 | } | |
4602 | ||
4603 | /* If PC is in a mips16 call or return stub, return the address of the target | |
4604 | PC, which is either the callee or the caller. There are several | |
4605 | cases which must be handled: | |
4606 | ||
4607 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 4608 | target PC is in $31 ($ra). |
c906108c | 4609 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 4610 | and the target PC is in $2. |
c906108c | 4611 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
4612 | before the jal instruction, this is effectively a call stub |
4613 | and the the target PC is in $2. Otherwise this is effectively | |
4614 | a return stub and the target PC is in $18. | |
c906108c SS |
4615 | |
4616 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 4617 | gory details. */ |
c906108c | 4618 | |
757a7cc6 | 4619 | static CORE_ADDR |
e7d6a6d2 | 4620 | mips_skip_trampoline_code (CORE_ADDR pc) |
c906108c SS |
4621 | { |
4622 | char *name; | |
4623 | CORE_ADDR start_addr; | |
4624 | ||
4625 | /* Find the starting address and name of the function containing the PC. */ | |
4626 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
4627 | return 0; | |
4628 | ||
4629 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
4630 | target PC is in $31 ($ra). */ | |
4631 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
4632 | || strcmp (name, "__mips16_ret_df") == 0) | |
4c7d22cb | 4633 | return read_signed_register (MIPS_RA_REGNUM); |
c906108c SS |
4634 | |
4635 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
4636 | { | |
4637 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
4638 | and the target PC is in $2. */ | |
4639 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 4640 | return read_signed_register (2); |
c906108c SS |
4641 | |
4642 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
4643 | before the jal instruction, this is effectively a call stub |
4644 | and the the target PC is in $2. Otherwise this is effectively | |
4645 | a return stub and the target PC is in $18. */ | |
c906108c SS |
4646 | else if (name[19] == 's' || name[19] == 'd') |
4647 | { | |
4648 | if (pc == start_addr) | |
4649 | { | |
4650 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
4651 | stub. Such a stub for a function bar might have a name |
4652 | like __fn_stub_bar, and might look like this: | |
4653 | mfc1 $4,$f13 | |
4654 | mfc1 $5,$f12 | |
4655 | mfc1 $6,$f15 | |
4656 | mfc1 $7,$f14 | |
4657 | la $1,bar (becomes a lui/addiu pair) | |
4658 | jr $1 | |
4659 | So scan down to the lui/addi and extract the target | |
4660 | address from those two instructions. */ | |
c906108c | 4661 | |
6c997a34 | 4662 | CORE_ADDR target_pc = read_signed_register (2); |
d37cca3d | 4663 | ULONGEST inst; |
c906108c SS |
4664 | int i; |
4665 | ||
4666 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
4667 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
4668 | 0) | |
c906108c SS |
4669 | return target_pc; |
4670 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
4671 | && strcmp (name, "etext") != 0 | |
4672 | && strcmp (name, "_etext") != 0) | |
4673 | return target_pc; | |
4674 | ||
4675 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
4676 | The limit on the search is arbitrarily set to 20 |
4677 | instructions. FIXME. */ | |
95ac2dcf | 4678 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
c906108c | 4679 | { |
c5aa993b JM |
4680 | inst = mips_fetch_instruction (target_pc); |
4681 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
4682 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
4683 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
4684 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
4685 | } |
4686 | ||
4687 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
4688 | return target_pc; | |
4689 | } | |
4690 | else | |
4691 | /* This is the 'return' part of a call stub. The return | |
4692 | address is in $r18. */ | |
6c997a34 | 4693 | return read_signed_register (18); |
c906108c SS |
4694 | } |
4695 | } | |
c5aa993b | 4696 | return 0; /* not a stub */ |
c906108c SS |
4697 | } |
4698 | ||
a4b8ebc8 | 4699 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 4700 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
4701 | |
4702 | static int | |
4703 | mips_stab_reg_to_regnum (int num) | |
4704 | { | |
a4b8ebc8 | 4705 | int regnum; |
2f38ef89 | 4706 | if (num >= 0 && num < 32) |
a4b8ebc8 | 4707 | regnum = num; |
2f38ef89 | 4708 | else if (num >= 38 && num < 70) |
56cea623 | 4709 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 4710 | else if (num == 70) |
56cea623 | 4711 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 4712 | else if (num == 71) |
56cea623 | 4713 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 4714 | else |
a4b8ebc8 AC |
4715 | /* This will hopefully (eventually) provoke a warning. Should |
4716 | we be calling complaint() here? */ | |
f57d151a UW |
4717 | return gdbarch_num_regs (current_gdbarch) |
4718 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4719 | return gdbarch_num_regs (current_gdbarch) + regnum; | |
88c72b7d AC |
4720 | } |
4721 | ||
2f38ef89 | 4722 | |
a4b8ebc8 | 4723 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 4724 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
4725 | |
4726 | static int | |
2f38ef89 | 4727 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 4728 | { |
a4b8ebc8 | 4729 | int regnum; |
2f38ef89 | 4730 | if (num >= 0 && num < 32) |
a4b8ebc8 | 4731 | regnum = num; |
2f38ef89 | 4732 | else if (num >= 32 && num < 64) |
56cea623 | 4733 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 4734 | else if (num == 64) |
56cea623 | 4735 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 4736 | else if (num == 65) |
56cea623 | 4737 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 4738 | else |
a4b8ebc8 AC |
4739 | /* This will hopefully (eventually) provoke a warning. Should we |
4740 | be calling complaint() here? */ | |
f57d151a UW |
4741 | return gdbarch_num_regs (current_gdbarch) |
4742 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4743 | return gdbarch_num_regs (current_gdbarch) + regnum; | |
a4b8ebc8 AC |
4744 | } |
4745 | ||
4746 | static int | |
4747 | mips_register_sim_regno (int regnum) | |
4748 | { | |
4749 | /* Only makes sense to supply raw registers. */ | |
f57d151a | 4750 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch)); |
a4b8ebc8 AC |
4751 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
4752 | decide if it is valid. Should instead define a standard sim/gdb | |
4753 | register numbering scheme. */ | |
c9f4d572 UW |
4754 | if (gdbarch_register_name (current_gdbarch, |
4755 | gdbarch_num_regs | |
4756 | (current_gdbarch) + regnum) != NULL | |
4757 | && gdbarch_register_name (current_gdbarch, | |
4758 | gdbarch_num_regs | |
4759 | (current_gdbarch) + regnum)[0] != '\0') | |
a4b8ebc8 AC |
4760 | return regnum; |
4761 | else | |
6d82d43b | 4762 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
4763 | } |
4764 | ||
2f38ef89 | 4765 | |
4844f454 CV |
4766 | /* Convert an integer into an address. Extracting the value signed |
4767 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
4768 | |
4769 | static CORE_ADDR | |
79dd2d24 | 4770 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 4771 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 4772 | { |
4844f454 | 4773 | return (CORE_ADDR) extract_signed_integer (buf, TYPE_LENGTH (type)); |
fc0c74b1 AC |
4774 | } |
4775 | ||
caaa3122 DJ |
4776 | static void |
4777 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
4778 | { | |
4779 | enum mips_abi *abip = (enum mips_abi *) obj; | |
4780 | const char *name = bfd_get_section_name (abfd, sect); | |
4781 | ||
4782 | if (*abip != MIPS_ABI_UNKNOWN) | |
4783 | return; | |
4784 | ||
4785 | if (strncmp (name, ".mdebug.", 8) != 0) | |
4786 | return; | |
4787 | ||
4788 | if (strcmp (name, ".mdebug.abi32") == 0) | |
4789 | *abip = MIPS_ABI_O32; | |
4790 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
4791 | *abip = MIPS_ABI_N32; | |
62a49b2c | 4792 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 4793 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
4794 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
4795 | *abip = MIPS_ABI_O64; | |
4796 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
4797 | *abip = MIPS_ABI_EABI32; | |
4798 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
4799 | *abip = MIPS_ABI_EABI64; | |
4800 | else | |
8a3fe4f8 | 4801 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
4802 | } |
4803 | ||
22e47e37 FF |
4804 | static void |
4805 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
4806 | { | |
4807 | int *lbp = (int *) obj; | |
4808 | const char *name = bfd_get_section_name (abfd, sect); | |
4809 | ||
4810 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
4811 | *lbp = 32; | |
4812 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
4813 | *lbp = 64; | |
4814 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
4815 | warning (_("unrecognized .gcc_compiled_longXX")); | |
4816 | } | |
4817 | ||
2e4ebe70 DJ |
4818 | static enum mips_abi |
4819 | global_mips_abi (void) | |
4820 | { | |
4821 | int i; | |
4822 | ||
4823 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
4824 | if (mips_abi_strings[i] == mips_abi_string) | |
4825 | return (enum mips_abi) i; | |
4826 | ||
e2e0b3e5 | 4827 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
4828 | } |
4829 | ||
29709017 DJ |
4830 | static void |
4831 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
4832 | { | |
4833 | static struct target_desc *tdesc_gp32, *tdesc_gp64; | |
4834 | ||
4835 | if (tdesc_gp32 == NULL) | |
4836 | { | |
4837 | /* Create feature sets with the appropriate properties. The values | |
4838 | are not important. */ | |
4839 | ||
4840 | tdesc_gp32 = allocate_target_description (); | |
4841 | set_tdesc_property (tdesc_gp32, PROPERTY_GP32, ""); | |
4842 | ||
4843 | tdesc_gp64 = allocate_target_description (); | |
4844 | set_tdesc_property (tdesc_gp64, PROPERTY_GP64, ""); | |
4845 | } | |
4846 | ||
4847 | /* If the size matches the set of 32-bit or 64-bit integer registers, | |
4848 | assume that's what we've got. */ | |
4849 | register_remote_g_packet_guess (gdbarch, 38 * 4, tdesc_gp32); | |
4850 | register_remote_g_packet_guess (gdbarch, 38 * 8, tdesc_gp64); | |
4851 | ||
4852 | /* If the size matches the full set of registers GDB traditionally | |
4853 | knows about, including floating point, for either 32-bit or | |
4854 | 64-bit, assume that's what we've got. */ | |
4855 | register_remote_g_packet_guess (gdbarch, 90 * 4, tdesc_gp32); | |
4856 | register_remote_g_packet_guess (gdbarch, 90 * 8, tdesc_gp64); | |
4857 | ||
4858 | /* Otherwise we don't have a useful guess. */ | |
4859 | } | |
4860 | ||
f8b73d13 DJ |
4861 | static struct value * |
4862 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
4863 | { | |
4864 | const int *reg_p = baton; | |
4865 | return value_of_register (*reg_p, frame); | |
4866 | } | |
4867 | ||
c2d11a7d | 4868 | static struct gdbarch * |
6d82d43b | 4869 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 4870 | { |
c2d11a7d JM |
4871 | struct gdbarch *gdbarch; |
4872 | struct gdbarch_tdep *tdep; | |
4873 | int elf_flags; | |
2e4ebe70 | 4874 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 4875 | int i, num_regs; |
8d5838b5 | 4876 | enum mips_fpu_type fpu_type; |
f8b73d13 DJ |
4877 | struct tdesc_arch_data *tdesc_data = NULL; |
4878 | ||
4879 | /* Check any target description for validity. */ | |
4880 | if (tdesc_has_registers (info.target_desc)) | |
4881 | { | |
4882 | static const char *const mips_gprs[] = { | |
4883 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
4884 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
4885 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
4886 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
4887 | }; | |
4888 | static const char *const mips_fprs[] = { | |
4889 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
4890 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
4891 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
4892 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
4893 | }; | |
4894 | ||
4895 | const struct tdesc_feature *feature; | |
4896 | int valid_p; | |
4897 | ||
4898 | feature = tdesc_find_feature (info.target_desc, | |
4899 | "org.gnu.gdb.mips.cpu"); | |
4900 | if (feature == NULL) | |
4901 | return NULL; | |
4902 | ||
4903 | tdesc_data = tdesc_data_alloc (); | |
4904 | ||
4905 | valid_p = 1; | |
4906 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
4907 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
4908 | mips_gprs[i]); | |
4909 | ||
4910 | ||
4911 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4912 | MIPS_EMBED_LO_REGNUM, "lo"); | |
4913 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4914 | MIPS_EMBED_HI_REGNUM, "hi"); | |
4915 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4916 | MIPS_EMBED_PC_REGNUM, "pc"); | |
4917 | ||
4918 | if (!valid_p) | |
4919 | { | |
4920 | tdesc_data_cleanup (tdesc_data); | |
4921 | return NULL; | |
4922 | } | |
4923 | ||
4924 | feature = tdesc_find_feature (info.target_desc, | |
4925 | "org.gnu.gdb.mips.cp0"); | |
4926 | if (feature == NULL) | |
4927 | { | |
4928 | tdesc_data_cleanup (tdesc_data); | |
4929 | return NULL; | |
4930 | } | |
4931 | ||
4932 | valid_p = 1; | |
4933 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4934 | MIPS_EMBED_BADVADDR_REGNUM, | |
4935 | "badvaddr"); | |
4936 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4937 | MIPS_PS_REGNUM, "status"); | |
4938 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4939 | MIPS_EMBED_CAUSE_REGNUM, "cause"); | |
4940 | ||
4941 | if (!valid_p) | |
4942 | { | |
4943 | tdesc_data_cleanup (tdesc_data); | |
4944 | return NULL; | |
4945 | } | |
4946 | ||
4947 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
4948 | backend is not prepared for that, though. */ | |
4949 | feature = tdesc_find_feature (info.target_desc, | |
4950 | "org.gnu.gdb.mips.fpu"); | |
4951 | if (feature == NULL) | |
4952 | { | |
4953 | tdesc_data_cleanup (tdesc_data); | |
4954 | return NULL; | |
4955 | } | |
4956 | ||
4957 | valid_p = 1; | |
4958 | for (i = 0; i < 32; i++) | |
4959 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4960 | i + MIPS_EMBED_FP0_REGNUM, | |
4961 | mips_fprs[i]); | |
4962 | ||
4963 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4964 | MIPS_EMBED_FP0_REGNUM + 32, "fcsr"); | |
4965 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4966 | MIPS_EMBED_FP0_REGNUM + 33, "fir"); | |
4967 | ||
4968 | if (!valid_p) | |
4969 | { | |
4970 | tdesc_data_cleanup (tdesc_data); | |
4971 | return NULL; | |
4972 | } | |
4973 | ||
4974 | /* It would be nice to detect an attempt to use a 64-bit ABI | |
4975 | when only 32-bit registers are provided. */ | |
4976 | } | |
c2d11a7d | 4977 | |
ec03c1ac AC |
4978 | /* First of all, extract the elf_flags, if available. */ |
4979 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
4980 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
4981 | else if (arches != NULL) |
4982 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
4983 | else |
4984 | elf_flags = 0; | |
4985 | if (gdbarch_debug) | |
4986 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 4987 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 4988 | |
102182a9 | 4989 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
4990 | switch ((elf_flags & EF_MIPS_ABI)) |
4991 | { | |
4992 | case E_MIPS_ABI_O32: | |
ec03c1ac | 4993 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
4994 | break; |
4995 | case E_MIPS_ABI_O64: | |
ec03c1ac | 4996 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
4997 | break; |
4998 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 4999 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5000 | break; |
5001 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5002 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5003 | break; |
5004 | default: | |
acdb74a0 | 5005 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5006 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5007 | else |
ec03c1ac | 5008 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5009 | break; |
5010 | } | |
acdb74a0 | 5011 | |
caaa3122 | 5012 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5013 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5014 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5015 | |
dc305454 | 5016 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
5017 | MIPS architecture (if there is one). */ |
5018 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5019 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5020 | |
32a6503c | 5021 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5022 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5023 | && info.bfd_arch_info != NULL |
5024 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5025 | { | |
5026 | switch (info.bfd_arch_info->mach) | |
5027 | { | |
5028 | case bfd_mach_mips3900: | |
ec03c1ac | 5029 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5030 | break; |
5031 | case bfd_mach_mips4100: | |
5032 | case bfd_mach_mips5000: | |
ec03c1ac | 5033 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5034 | break; |
1d06468c EZ |
5035 | case bfd_mach_mips8000: |
5036 | case bfd_mach_mips10000: | |
32a6503c KB |
5037 | /* On Irix, ELF64 executables use the N64 ABI. The |
5038 | pseudo-sections which describe the ABI aren't present | |
5039 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5040 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5041 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5042 | found_abi = MIPS_ABI_N64; |
28d169de | 5043 | else |
ec03c1ac | 5044 | found_abi = MIPS_ABI_N32; |
1d06468c | 5045 | break; |
bf64bfd6 AC |
5046 | } |
5047 | } | |
2e4ebe70 | 5048 | |
26c53e50 DJ |
5049 | /* Default 64-bit objects to N64 instead of O32. */ |
5050 | if (found_abi == MIPS_ABI_UNKNOWN | |
5051 | && info.abfd != NULL | |
5052 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
5053 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5054 | found_abi = MIPS_ABI_N64; | |
5055 | ||
ec03c1ac AC |
5056 | if (gdbarch_debug) |
5057 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5058 | found_abi); | |
5059 | ||
5060 | /* What has the user specified from the command line? */ | |
5061 | wanted_abi = global_mips_abi (); | |
5062 | if (gdbarch_debug) | |
5063 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5064 | wanted_abi); | |
2e4ebe70 DJ |
5065 | |
5066 | /* Now that we have found what the ABI for this binary would be, | |
5067 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5068 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5069 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5070 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5071 | mips_abi = found_abi; | |
5072 | else | |
5073 | mips_abi = MIPS_ABI_O32; | |
5074 | if (gdbarch_debug) | |
5075 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5076 | mips_abi); | |
2e4ebe70 | 5077 | |
ec03c1ac | 5078 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5079 | if (gdbarch_debug) |
ec03c1ac AC |
5080 | fprintf_unfiltered (gdb_stdlog, |
5081 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
5082 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 5083 | |
8d5838b5 AC |
5084 | /* Determine the MIPS FPU type. */ |
5085 | if (!mips_fpu_type_auto) | |
5086 | fpu_type = mips_fpu_type; | |
5087 | else if (info.bfd_arch_info != NULL | |
5088 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5089 | switch (info.bfd_arch_info->mach) | |
5090 | { | |
5091 | case bfd_mach_mips3900: | |
5092 | case bfd_mach_mips4100: | |
5093 | case bfd_mach_mips4111: | |
a9d61c86 | 5094 | case bfd_mach_mips4120: |
8d5838b5 AC |
5095 | fpu_type = MIPS_FPU_NONE; |
5096 | break; | |
5097 | case bfd_mach_mips4650: | |
5098 | fpu_type = MIPS_FPU_SINGLE; | |
5099 | break; | |
5100 | default: | |
5101 | fpu_type = MIPS_FPU_DOUBLE; | |
5102 | break; | |
5103 | } | |
5104 | else if (arches != NULL) | |
5105 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5106 | else | |
5107 | fpu_type = MIPS_FPU_DOUBLE; | |
5108 | if (gdbarch_debug) | |
5109 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5110 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5111 | |
29709017 DJ |
5112 | /* Check for blatant incompatibilities. */ |
5113 | ||
5114 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
5115 | ABI. */ | |
5116 | if (info.target_desc | |
5117 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
5118 | && mips_abi != MIPS_ABI_EABI32 | |
5119 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
5120 | { |
5121 | if (tdesc_data != NULL) | |
5122 | tdesc_data_cleanup (tdesc_data); | |
5123 | return NULL; | |
5124 | } | |
29709017 | 5125 | |
c2d11a7d JM |
5126 | /* try to find a pre-existing architecture */ |
5127 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5128 | arches != NULL; | |
5129 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5130 | { | |
5131 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5132 | using. */ |
9103eae0 | 5133 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5134 | continue; |
9103eae0 | 5135 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5136 | continue; |
719ec221 AC |
5137 | /* Need to be pedantic about which register virtual size is |
5138 | used. */ | |
5139 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5140 | != mips64_transfers_32bit_regs_p) | |
5141 | continue; | |
8d5838b5 AC |
5142 | /* Be pedantic about which FPU is selected. */ |
5143 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5144 | continue; | |
f8b73d13 DJ |
5145 | |
5146 | if (tdesc_data != NULL) | |
5147 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 5148 | return arches->gdbarch; |
c2d11a7d JM |
5149 | } |
5150 | ||
102182a9 | 5151 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5152 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5153 | gdbarch = gdbarch_alloc (&info, tdep); | |
5154 | tdep->elf_flags = elf_flags; | |
719ec221 | 5155 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5156 | tdep->found_abi = found_abi; |
5157 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5158 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
5159 | tdep->register_size_valid_p = 0; |
5160 | tdep->register_size = 0; | |
5161 | ||
5162 | if (info.target_desc) | |
5163 | { | |
5164 | /* Some useful properties can be inferred from the target. */ | |
5165 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
5166 | { | |
5167 | tdep->register_size_valid_p = 1; | |
5168 | tdep->register_size = 4; | |
5169 | } | |
5170 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
5171 | { | |
5172 | tdep->register_size_valid_p = 1; | |
5173 | tdep->register_size = 8; | |
5174 | } | |
5175 | } | |
c2d11a7d | 5176 | |
102182a9 | 5177 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5178 | set_gdbarch_short_bit (gdbarch, 16); |
5179 | set_gdbarch_int_bit (gdbarch, 32); | |
5180 | set_gdbarch_float_bit (gdbarch, 32); | |
5181 | set_gdbarch_double_bit (gdbarch, 64); | |
5182 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5183 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5184 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5185 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5186 | |
6d82d43b | 5187 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
5188 | mips_elf_make_msymbol_special); |
5189 | ||
16e109ca | 5190 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5191 | { |
16e109ca | 5192 | const char **reg_names; |
56cea623 AC |
5193 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5194 | struct mips_regnum); | |
f8b73d13 DJ |
5195 | if (tdesc_has_registers (info.target_desc)) |
5196 | { | |
5197 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5198 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5199 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5200 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5201 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5202 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5203 | regnum->fp_control_status = 70; | |
5204 | regnum->fp_implementation_revision = 71; | |
5205 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
5206 | reg_names = NULL; | |
5207 | } | |
5208 | else if (info.osabi == GDB_OSABI_IRIX) | |
56cea623 AC |
5209 | { |
5210 | regnum->fp0 = 32; | |
5211 | regnum->pc = 64; | |
5212 | regnum->cause = 65; | |
5213 | regnum->badvaddr = 66; | |
5214 | regnum->hi = 67; | |
5215 | regnum->lo = 68; | |
5216 | regnum->fp_control_status = 69; | |
5217 | regnum->fp_implementation_revision = 70; | |
5218 | num_regs = 71; | |
16e109ca | 5219 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5220 | } |
5221 | else | |
5222 | { | |
5223 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5224 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5225 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5226 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5227 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5228 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5229 | regnum->fp_control_status = 70; | |
5230 | regnum->fp_implementation_revision = 71; | |
5231 | num_regs = 90; | |
16e109ca AC |
5232 | if (info.bfd_arch_info != NULL |
5233 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5234 | reg_names = mips_tx39_reg_names; | |
5235 | else | |
5236 | reg_names = mips_generic_reg_names; | |
56cea623 AC |
5237 | } |
5238 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been | |
5239 | replaced by read_pc? */ | |
f10683bb MH |
5240 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
5241 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
5242 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
5243 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5244 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca AC |
5245 | set_gdbarch_register_name (gdbarch, mips_register_name); |
5246 | tdep->mips_processor_reg_names = reg_names; | |
5247 | tdep->regnum = regnum; | |
56cea623 | 5248 | } |
fe29b929 | 5249 | |
0dadbba0 | 5250 | switch (mips_abi) |
c2d11a7d | 5251 | { |
0dadbba0 | 5252 | case MIPS_ABI_O32: |
25ab4790 | 5253 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5254 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 5255 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5256 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5257 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5258 | set_gdbarch_long_bit (gdbarch, 32); |
5259 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5260 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5261 | break; | |
0dadbba0 | 5262 | case MIPS_ABI_O64: |
25ab4790 | 5263 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 5264 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 5265 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5266 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5267 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5268 | set_gdbarch_long_bit (gdbarch, 32); |
5269 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5270 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5271 | break; | |
0dadbba0 | 5272 | case MIPS_ABI_EABI32: |
25ab4790 | 5273 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5274 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5275 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5276 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5277 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5278 | set_gdbarch_long_bit (gdbarch, 32); |
5279 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5280 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5281 | break; | |
0dadbba0 | 5282 | case MIPS_ABI_EABI64: |
25ab4790 | 5283 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5284 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5285 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5286 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5287 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5288 | set_gdbarch_long_bit (gdbarch, 64); |
5289 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5290 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5291 | break; | |
0dadbba0 | 5292 | case MIPS_ABI_N32: |
25ab4790 | 5293 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5294 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5295 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5296 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5297 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5298 | set_gdbarch_long_bit (gdbarch, 32); |
5299 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5300 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5301 | set_gdbarch_long_double_bit (gdbarch, 128); |
8da61cc4 | 5302 | set_gdbarch_long_double_format (gdbarch, floatformats_n32n64_long); |
28d169de KB |
5303 | break; |
5304 | case MIPS_ABI_N64: | |
25ab4790 | 5305 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5306 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5307 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5308 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5309 | tdep->default_mask_address_p = 0; |
5310 | set_gdbarch_long_bit (gdbarch, 64); | |
5311 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5312 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5313 | set_gdbarch_long_double_bit (gdbarch, 128); |
8da61cc4 | 5314 | set_gdbarch_long_double_format (gdbarch, floatformats_n32n64_long); |
0dadbba0 | 5315 | break; |
c2d11a7d | 5316 | default: |
e2e0b3e5 | 5317 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
5318 | } |
5319 | ||
22e47e37 FF |
5320 | /* GCC creates a pseudo-section whose name specifies the size of |
5321 | longs, since -mlong32 or -mlong64 may be used independent of | |
5322 | other options. How those options affect pointer sizes is ABI and | |
5323 | architecture dependent, so use them to override the default sizes | |
5324 | set by the ABI. This table shows the relationship between ABI, | |
5325 | -mlongXX, and size of pointers: | |
5326 | ||
5327 | ABI -mlongXX ptr bits | |
5328 | --- -------- -------- | |
5329 | o32 32 32 | |
5330 | o32 64 32 | |
5331 | n32 32 32 | |
5332 | n32 64 64 | |
5333 | o64 32 32 | |
5334 | o64 64 64 | |
5335 | n64 32 32 | |
5336 | n64 64 64 | |
5337 | eabi32 32 32 | |
5338 | eabi32 64 32 | |
5339 | eabi64 32 32 | |
5340 | eabi64 64 64 | |
5341 | ||
5342 | Note that for o32 and eabi32, pointers are always 32 bits | |
5343 | regardless of any -mlongXX option. For all others, pointers and | |
5344 | longs are the same, as set by -mlongXX or set by defaults. | |
5345 | */ | |
5346 | ||
5347 | if (info.abfd != NULL) | |
5348 | { | |
5349 | int long_bit = 0; | |
5350 | ||
5351 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
5352 | if (long_bit) | |
5353 | { | |
5354 | set_gdbarch_long_bit (gdbarch, long_bit); | |
5355 | switch (mips_abi) | |
5356 | { | |
5357 | case MIPS_ABI_O32: | |
5358 | case MIPS_ABI_EABI32: | |
5359 | break; | |
5360 | case MIPS_ABI_N32: | |
5361 | case MIPS_ABI_O64: | |
5362 | case MIPS_ABI_N64: | |
5363 | case MIPS_ABI_EABI64: | |
5364 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
5365 | break; | |
5366 | default: | |
5367 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
5368 | } | |
5369 | } | |
5370 | } | |
5371 | ||
a5ea2558 AC |
5372 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5373 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5374 | comment: | |
5375 | ||
5376 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5377 | flag in object files because to do so would make it impossible to | |
102182a9 | 5378 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5379 | unnecessarily restrictive. |
361d1df0 | 5380 | |
a5ea2558 AC |
5381 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5382 | but to set this flag before gcc is built with such multilibs will | |
5383 | break too many systems.'' | |
5384 | ||
5385 | But even more unhelpfully, the default linker output target for | |
5386 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5387 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5388 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5389 | this flag to detect 32-bit mode would do the wrong thing given |
5390 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5391 | as 32-bit programs by default. */ |
a5ea2558 | 5392 | |
6c997a34 | 5393 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 5394 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 5395 | |
102182a9 MS |
5396 | /* Add/remove bits from an address. The MIPS needs be careful to |
5397 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5398 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5399 | ||
58dfe9ff AC |
5400 | /* Unwind the frame. */ |
5401 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 5402 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
edfae063 | 5403 | set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id); |
10312cc4 | 5404 | |
102182a9 | 5405 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5406 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
5407 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
5408 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5409 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, | |
5410 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5411 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, | |
5412 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5413 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5414 | |
c2d11a7d JM |
5415 | /* MIPS version of CALL_DUMMY */ |
5416 | ||
9710e734 AC |
5417 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
5418 | replaced by a command, and all targets will default to on stack | |
5419 | (regardless of the stack's execute status). */ | |
5420 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 5421 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 5422 | |
87783b8b AC |
5423 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
5424 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
5425 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
5426 | ||
f7b9e9fc AC |
5427 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5428 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
5429 | |
5430 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 5431 | |
fc0c74b1 AC |
5432 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5433 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5434 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5435 | |
a4b8ebc8 | 5436 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 5437 | |
e11c53d2 | 5438 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 5439 | |
e5ab0dce AC |
5440 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
5441 | ||
3a3bc038 AC |
5442 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
5443 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
5444 | need to all be folded into the target vector. Since they are | |
5445 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
5446 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
5447 | is sitting on? */ | |
5448 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
5449 | ||
e7d6a6d2 | 5450 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 5451 | |
3352ef37 AC |
5452 | set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay); |
5453 | ||
0d5de010 DJ |
5454 | /* Virtual tables. */ |
5455 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
5456 | ||
29709017 DJ |
5457 | mips_register_g_packet_guesses (gdbarch); |
5458 | ||
6de918a6 DJ |
5459 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
5460 | gdbarch_init_osabi (info, gdbarch); | |
757a7cc6 | 5461 | |
5792a79b | 5462 | /* Unwind the frame. */ |
2bd0c3d7 | 5463 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
eec63939 | 5464 | frame_unwind_append_sniffer (gdbarch, mips_stub_frame_sniffer); |
45c9dd44 AC |
5465 | frame_unwind_append_sniffer (gdbarch, mips_insn16_frame_sniffer); |
5466 | frame_unwind_append_sniffer (gdbarch, mips_insn32_frame_sniffer); | |
2bd0c3d7 | 5467 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 5468 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
5469 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
5470 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 5471 | |
f8b73d13 DJ |
5472 | if (tdesc_data) |
5473 | { | |
5474 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
5475 | tdesc_use_registers (gdbarch, tdesc_data); | |
5476 | ||
5477 | /* Override the normal target description methods to handle our | |
5478 | dual real and pseudo registers. */ | |
5479 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
5480 | set_gdbarch_register_reggroup_p (gdbarch, mips_tdesc_register_reggroup_p); | |
5481 | ||
5482 | num_regs = gdbarch_num_regs (gdbarch); | |
5483 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
5484 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
5485 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
5486 | } | |
5487 | ||
5488 | /* Add ABI-specific aliases for the registers. */ | |
5489 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
5490 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
5491 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
5492 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
5493 | else | |
5494 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
5495 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
5496 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
5497 | ||
5498 | /* Add some other standard aliases. */ | |
5499 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
5500 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
5501 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
5502 | ||
4b9b3959 AC |
5503 | return gdbarch; |
5504 | } | |
5505 | ||
2e4ebe70 | 5506 | static void |
6d82d43b | 5507 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
5508 | { |
5509 | struct gdbarch_info info; | |
5510 | ||
5511 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
5512 | mips_gdbarch_init will take care of the rest. */ | |
5513 | gdbarch_info_init (&info); | |
5514 | gdbarch_update_p (info); | |
5515 | } | |
5516 | ||
ad188201 KB |
5517 | /* Print out which MIPS ABI is in use. */ |
5518 | ||
5519 | static void | |
1f8ca57c JB |
5520 | show_mips_abi (struct ui_file *file, |
5521 | int from_tty, | |
5522 | struct cmd_list_element *ignored_cmd, | |
5523 | const char *ignored_value) | |
ad188201 KB |
5524 | { |
5525 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
1f8ca57c JB |
5526 | fprintf_filtered |
5527 | (file, | |
5528 | "The MIPS ABI is unknown because the current architecture " | |
5529 | "is not MIPS.\n"); | |
ad188201 KB |
5530 | else |
5531 | { | |
5532 | enum mips_abi global_abi = global_mips_abi (); | |
5533 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
5534 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
5535 | ||
5536 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
5537 | fprintf_filtered |
5538 | (file, | |
5539 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 5540 | actual_abi_str); |
ad188201 | 5541 | else if (global_abi == actual_abi) |
1f8ca57c JB |
5542 | fprintf_filtered |
5543 | (file, | |
5544 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 5545 | actual_abi_str); |
ad188201 KB |
5546 | else |
5547 | { | |
5548 | /* Probably shouldn't happen... */ | |
1f8ca57c JB |
5549 | fprintf_filtered |
5550 | (file, | |
5551 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6d82d43b | 5552 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
5553 | } |
5554 | } | |
5555 | } | |
5556 | ||
4b9b3959 AC |
5557 | static void |
5558 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
5559 | { | |
5560 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
5561 | if (tdep != NULL) | |
c2d11a7d | 5562 | { |
acdb74a0 AC |
5563 | int ef_mips_arch; |
5564 | int ef_mips_32bitmode; | |
f49e4e6d | 5565 | /* Determine the ISA. */ |
acdb74a0 AC |
5566 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
5567 | { | |
5568 | case E_MIPS_ARCH_1: | |
5569 | ef_mips_arch = 1; | |
5570 | break; | |
5571 | case E_MIPS_ARCH_2: | |
5572 | ef_mips_arch = 2; | |
5573 | break; | |
5574 | case E_MIPS_ARCH_3: | |
5575 | ef_mips_arch = 3; | |
5576 | break; | |
5577 | case E_MIPS_ARCH_4: | |
93d56215 | 5578 | ef_mips_arch = 4; |
acdb74a0 AC |
5579 | break; |
5580 | default: | |
93d56215 | 5581 | ef_mips_arch = 0; |
acdb74a0 AC |
5582 | break; |
5583 | } | |
f49e4e6d | 5584 | /* Determine the size of a pointer. */ |
acdb74a0 | 5585 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
5586 | fprintf_unfiltered (file, |
5587 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 5588 | tdep->elf_flags); |
4b9b3959 | 5589 | fprintf_unfiltered (file, |
acdb74a0 AC |
5590 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
5591 | ef_mips_32bitmode); | |
5592 | fprintf_unfiltered (file, | |
5593 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
5594 | ef_mips_arch); | |
5595 | fprintf_unfiltered (file, | |
5596 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 5597 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
5598 | fprintf_unfiltered (file, |
5599 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 5600 | mips_mask_address_p (tdep), |
4014092b | 5601 | tdep->default_mask_address_p); |
c2d11a7d | 5602 | } |
4b9b3959 AC |
5603 | fprintf_unfiltered (file, |
5604 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
5605 | MIPS_DEFAULT_FPU_TYPE, | |
5606 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5607 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5608 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5609 | : "???")); | |
6d82d43b | 5610 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI); |
4b9b3959 AC |
5611 | fprintf_unfiltered (file, |
5612 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
5613 | MIPS_FPU_TYPE, | |
5614 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5615 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5616 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5617 | : "???")); | |
c2d11a7d JM |
5618 | } |
5619 | ||
6d82d43b | 5620 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 5621 | |
c906108c | 5622 | void |
acdb74a0 | 5623 | _initialize_mips_tdep (void) |
c906108c SS |
5624 | { |
5625 | static struct cmd_list_element *mipsfpulist = NULL; | |
5626 | struct cmd_list_element *c; | |
5627 | ||
6d82d43b | 5628 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
5629 | if (MIPS_ABI_LAST + 1 |
5630 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 5631 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 5632 | |
4b9b3959 | 5633 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 5634 | |
8d5f9dcb DJ |
5635 | mips_pdr_data = register_objfile_data (); |
5636 | ||
a5ea2558 AC |
5637 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
5638 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
1bedd215 | 5639 | _("Various MIPS specific commands."), |
a5ea2558 AC |
5640 | &setmipscmdlist, "set mips ", 0, &setlist); |
5641 | ||
5642 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 5643 | _("Various MIPS specific commands."), |
a5ea2558 AC |
5644 | &showmipscmdlist, "show mips ", 0, &showlist); |
5645 | ||
2e4ebe70 | 5646 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
5647 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
5648 | &mips_abi_string, _("\ | |
5649 | Set the MIPS ABI used by this program."), _("\ | |
5650 | Show the MIPS ABI used by this program."), _("\ | |
5651 | This option can be set to one of:\n\ | |
5652 | auto - the default ABI associated with the current binary\n\ | |
5653 | o32\n\ | |
5654 | o64\n\ | |
5655 | n32\n\ | |
5656 | n64\n\ | |
5657 | eabi32\n\ | |
5658 | eabi64"), | |
5659 | mips_abi_update, | |
5660 | show_mips_abi, | |
5661 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 5662 | |
c906108c SS |
5663 | /* Let the user turn off floating point and set the fence post for |
5664 | heuristic_proc_start. */ | |
5665 | ||
5666 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 5667 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
5668 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
5669 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 5670 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
5671 | &mipsfpulist); |
5672 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 5673 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
5674 | &mipsfpulist); |
5675 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
5676 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
5677 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
5678 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 5679 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
5680 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
5681 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
5682 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
5683 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 5684 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
5685 | &mipsfpulist); |
5686 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 5687 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
5688 | &showlist); |
5689 | ||
c906108c SS |
5690 | /* We really would like to have both "0" and "unlimited" work, but |
5691 | command.c doesn't deal with that. So make it a var_zinteger | |
5692 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 5693 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
5694 | &heuristic_fence_post, _("\ |
5695 | Set the distance searched for the start of a function."), _("\ | |
5696 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
5697 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
5698 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 5699 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 5700 | reinit_frame_cache_sfunc, |
7915a72c | 5701 | NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */ |
6bcadd06 | 5702 | &setlist, &showlist); |
c906108c SS |
5703 | |
5704 | /* Allow the user to control whether the upper bits of 64-bit | |
5705 | addresses should be zeroed. */ | |
7915a72c AC |
5706 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
5707 | &mask_address_var, _("\ | |
5708 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
5709 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
e9e68a56 | 5710 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ |
7915a72c | 5711 | allow GDB to determine the correct value."), |
08546159 AC |
5712 | NULL, show_mask_address, |
5713 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
5714 | |
5715 | /* Allow the user to control the size of 32 bit registers within the | |
5716 | raw remote packet. */ | |
b3f42336 | 5717 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
5718 | &mips64_transfers_32bit_regs_p, _("\ |
5719 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
5720 | _("\ | |
5721 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
5722 | _("\ | |
719ec221 AC |
5723 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
5724 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 5725 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 5726 | set_mips64_transfers_32bit_regs, |
7915a72c | 5727 | NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */ |
7915a72c | 5728 | &setlist, &showlist); |
9ace0497 AC |
5729 | |
5730 | /* Debug this files internals. */ | |
6bcadd06 | 5731 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
5732 | &mips_debug, _("\ |
5733 | Set mips debugging."), _("\ | |
5734 | Show mips debugging."), _("\ | |
5735 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 5736 | NULL, |
7915a72c | 5737 | NULL, /* FIXME: i18n: Mips debugging is currently %s. */ |
6bcadd06 | 5738 | &setdebuglist, &showdebuglist); |
c906108c | 5739 | } |