Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
6aba47ca DJ |
3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 | |
47a35522 | 5 | Free Software Foundation, Inc. |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2 of the License, or | |
15 | (at your option) any later version. | |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b JM |
22 | You should have received a copy of the GNU General Public License |
23 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
24 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
25 | Boston, MA 02110-1301, USA. */ | |
c906108c SS |
26 | |
27 | #include "defs.h" | |
28 | #include "gdb_string.h" | |
5e2e9765 | 29 | #include "gdb_assert.h" |
c906108c SS |
30 | #include "frame.h" |
31 | #include "inferior.h" | |
32 | #include "symtab.h" | |
33 | #include "value.h" | |
34 | #include "gdbcmd.h" | |
35 | #include "language.h" | |
36 | #include "gdbcore.h" | |
37 | #include "symfile.h" | |
38 | #include "objfiles.h" | |
39 | #include "gdbtypes.h" | |
40 | #include "target.h" | |
28d069e6 | 41 | #include "arch-utils.h" |
4e052eda | 42 | #include "regcache.h" |
70f80edf | 43 | #include "osabi.h" |
d1973055 | 44 | #include "mips-tdep.h" |
fe898f56 | 45 | #include "block.h" |
a4b8ebc8 | 46 | #include "reggroups.h" |
c906108c | 47 | #include "opcode/mips.h" |
c2d11a7d JM |
48 | #include "elf/mips.h" |
49 | #include "elf-bfd.h" | |
2475bac3 | 50 | #include "symcat.h" |
a4b8ebc8 | 51 | #include "sim-regno.h" |
a89aa300 | 52 | #include "dis-asm.h" |
edfae063 AC |
53 | #include "frame-unwind.h" |
54 | #include "frame-base.h" | |
55 | #include "trad-frame.h" | |
7d9b040b | 56 | #include "infcall.h" |
fed7ba43 | 57 | #include "floatformat.h" |
29709017 DJ |
58 | #include "remote.h" |
59 | #include "target-descriptions.h" | |
2bd0c3d7 | 60 | #include "dwarf2-frame.h" |
f8b73d13 | 61 | #include "user-regs.h" |
c906108c | 62 | |
8d5f9dcb DJ |
63 | static const struct objfile_data *mips_pdr_data; |
64 | ||
5bbcb741 | 65 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 66 | |
24e05951 | 67 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
68 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
69 | #define ST0_FR (1 << 26) | |
70 | ||
b0069a17 AC |
71 | /* The sizes of floating point registers. */ |
72 | ||
73 | enum | |
74 | { | |
75 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
76 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
77 | }; | |
78 | ||
1a69e1e4 DJ |
79 | enum |
80 | { | |
81 | MIPS32_REGSIZE = 4, | |
82 | MIPS64_REGSIZE = 8 | |
83 | }; | |
0dadbba0 | 84 | |
2e4ebe70 DJ |
85 | static const char *mips_abi_string; |
86 | ||
87 | static const char *mips_abi_strings[] = { | |
88 | "auto", | |
89 | "n32", | |
90 | "o32", | |
28d169de | 91 | "n64", |
2e4ebe70 DJ |
92 | "o64", |
93 | "eabi32", | |
94 | "eabi64", | |
95 | NULL | |
96 | }; | |
97 | ||
f8b73d13 DJ |
98 | /* The standard register names, and all the valid aliases for them. */ |
99 | struct register_alias | |
100 | { | |
101 | const char *name; | |
102 | int regnum; | |
103 | }; | |
104 | ||
105 | /* Aliases for o32 and most other ABIs. */ | |
106 | const struct register_alias mips_o32_aliases[] = { | |
107 | { "ta0", 12 }, | |
108 | { "ta1", 13 }, | |
109 | { "ta2", 14 }, | |
110 | { "ta3", 15 } | |
111 | }; | |
112 | ||
113 | /* Aliases for n32 and n64. */ | |
114 | const struct register_alias mips_n32_n64_aliases[] = { | |
115 | { "ta0", 8 }, | |
116 | { "ta1", 9 }, | |
117 | { "ta2", 10 }, | |
118 | { "ta3", 11 } | |
119 | }; | |
120 | ||
121 | /* Aliases for ABI-independent registers. */ | |
122 | const struct register_alias mips_register_aliases[] = { | |
123 | /* The architecture manuals specify these ABI-independent names for | |
124 | the GPRs. */ | |
125 | #define R(n) { "r" #n, n } | |
126 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
127 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
128 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
129 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
130 | #undef R | |
131 | ||
132 | /* k0 and k1 are sometimes called these instead (for "kernel | |
133 | temp"). */ | |
134 | { "kt0", 26 }, | |
135 | { "kt1", 27 }, | |
136 | ||
137 | /* This is the traditional GDB name for the CP0 status register. */ | |
138 | { "sr", MIPS_PS_REGNUM }, | |
139 | ||
140 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
141 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
142 | ||
143 | /* This is the traditional GDB name for the FCSR. */ | |
144 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
145 | }; | |
146 | ||
7a292a7a | 147 | /* Some MIPS boards don't support floating point while others only |
ceae6e75 | 148 | support single-precision floating-point operations. */ |
c906108c SS |
149 | |
150 | enum mips_fpu_type | |
6d82d43b AC |
151 | { |
152 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
153 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
154 | MIPS_FPU_NONE /* No floating point. */ | |
155 | }; | |
c906108c SS |
156 | |
157 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
158 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
159 | #endif | |
160 | static int mips_fpu_type_auto = 1; | |
161 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 162 | |
9ace0497 | 163 | static int mips_debug = 0; |
7a292a7a | 164 | |
29709017 DJ |
165 | /* Properties (for struct target_desc) describing the g/G packet |
166 | layout. */ | |
167 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
168 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
169 | ||
c2d11a7d JM |
170 | /* MIPS specific per-architecture information */ |
171 | struct gdbarch_tdep | |
6d82d43b AC |
172 | { |
173 | /* from the elf header */ | |
174 | int elf_flags; | |
175 | ||
176 | /* mips options */ | |
177 | enum mips_abi mips_abi; | |
178 | enum mips_abi found_abi; | |
179 | enum mips_fpu_type mips_fpu_type; | |
180 | int mips_last_arg_regnum; | |
181 | int mips_last_fp_arg_regnum; | |
6d82d43b AC |
182 | int default_mask_address_p; |
183 | /* Is the target using 64-bit raw integer registers but only | |
184 | storing a left-aligned 32-bit value in each? */ | |
185 | int mips64_transfers_32bit_regs_p; | |
186 | /* Indexes for various registers. IRIX and embedded have | |
187 | different values. This contains the "public" fields. Don't | |
188 | add any that do not need to be public. */ | |
189 | const struct mips_regnum *regnum; | |
190 | /* Register names table for the current register set. */ | |
191 | const char **mips_processor_reg_names; | |
29709017 DJ |
192 | |
193 | /* The size of register data available from the target, if known. | |
194 | This doesn't quite obsolete the manual | |
195 | mips64_transfers_32bit_regs_p, since that is documented to force | |
196 | left alignment even for big endian (very strange). */ | |
197 | int register_size_valid_p; | |
198 | int register_size; | |
6d82d43b | 199 | }; |
c2d11a7d | 200 | |
fed7ba43 JB |
201 | static int |
202 | n32n64_floatformat_always_valid (const struct floatformat *fmt, | |
2244f671 | 203 | const void *from) |
fed7ba43 JB |
204 | { |
205 | return 1; | |
206 | } | |
207 | ||
208 | /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long. | |
209 | They are implemented as a pair of 64bit doubles where the high | |
210 | part holds the result of the operation rounded to double, and | |
211 | the low double holds the difference between the exact result and | |
212 | the rounded result. So "high" + "low" contains the result with | |
213 | added precision. Unfortunately, the floatformat structure used | |
214 | by GDB is not powerful enough to describe this format. As a temporary | |
215 | measure, we define a 128bit floatformat that only uses the high part. | |
216 | We lose a bit of precision but that's probably the best we can do | |
217 | for now with the current infrastructure. */ | |
218 | ||
219 | static const struct floatformat floatformat_n32n64_long_double_big = | |
220 | { | |
221 | floatformat_big, 128, 0, 1, 11, 1023, 2047, 12, 52, | |
222 | floatformat_intbit_no, | |
8da61cc4 | 223 | "floatformat_n32n64_long_double_big", |
fed7ba43 JB |
224 | n32n64_floatformat_always_valid |
225 | }; | |
226 | ||
8da61cc4 DJ |
227 | static const struct floatformat *floatformats_n32n64_long[BFD_ENDIAN_UNKNOWN] = |
228 | { | |
229 | &floatformat_n32n64_long_double_big, | |
230 | &floatformat_n32n64_long_double_big | |
231 | }; | |
232 | ||
56cea623 AC |
233 | const struct mips_regnum * |
234 | mips_regnum (struct gdbarch *gdbarch) | |
235 | { | |
236 | return gdbarch_tdep (gdbarch)->regnum; | |
237 | } | |
238 | ||
239 | static int | |
240 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
241 | { | |
242 | return mips_regnum (gdbarch)->fp0 + 12; | |
243 | } | |
244 | ||
0dadbba0 | 245 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 246 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 247 | |
c2d11a7d | 248 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 249 | |
c2d11a7d | 250 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 251 | |
c2d11a7d | 252 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 253 | |
95404a3e AC |
254 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
255 | functions to test, set, or clear bit 0 of addresses. */ | |
256 | ||
257 | static CORE_ADDR | |
258 | is_mips16_addr (CORE_ADDR addr) | |
259 | { | |
260 | return ((addr) & 1); | |
261 | } | |
262 | ||
95404a3e AC |
263 | static CORE_ADDR |
264 | unmake_mips16_addr (CORE_ADDR addr) | |
265 | { | |
5b652102 | 266 | return ((addr) & ~(CORE_ADDR) 1); |
95404a3e AC |
267 | } |
268 | ||
d1973055 KB |
269 | /* Return the MIPS ABI associated with GDBARCH. */ |
270 | enum mips_abi | |
271 | mips_abi (struct gdbarch *gdbarch) | |
272 | { | |
273 | return gdbarch_tdep (gdbarch)->mips_abi; | |
274 | } | |
275 | ||
4246e332 | 276 | int |
1b13c4f6 | 277 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 278 | { |
29709017 DJ |
279 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
280 | ||
281 | /* If we know how big the registers are, use that size. */ | |
282 | if (tdep->register_size_valid_p) | |
283 | return tdep->register_size; | |
284 | ||
285 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
286 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
287 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
288 | } | |
289 | ||
480d3dd2 AC |
290 | /* Return the currently configured (or set) saved register size. */ |
291 | ||
e6bc2e8a | 292 | unsigned int |
13326b4e | 293 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 294 | { |
1a69e1e4 DJ |
295 | switch (mips_abi (gdbarch)) |
296 | { | |
297 | case MIPS_ABI_EABI32: | |
298 | case MIPS_ABI_O32: | |
299 | return 4; | |
300 | case MIPS_ABI_N32: | |
301 | case MIPS_ABI_N64: | |
302 | case MIPS_ABI_O64: | |
303 | case MIPS_ABI_EABI64: | |
304 | return 8; | |
305 | case MIPS_ABI_UNKNOWN: | |
306 | case MIPS_ABI_LAST: | |
307 | default: | |
308 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
309 | } | |
d929b26f AC |
310 | } |
311 | ||
71b8ef93 | 312 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 313 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 314 | "info" field is used for this purpose. |
5a89d8aa | 315 | |
95f1da47 | 316 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
5a89d8aa MS |
317 | i.e. refers to a 16-bit function, and sets a "special" bit in a |
318 | minimal symbol to mark it as a 16-bit function | |
319 | ||
f594e5e9 | 320 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 321 | |
5a89d8aa | 322 | static void |
6d82d43b AC |
323 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
324 | { | |
325 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
326 | { | |
327 | MSYMBOL_INFO (msym) = (char *) | |
328 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
329 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
330 | } | |
5a89d8aa MS |
331 | } |
332 | ||
71b8ef93 MS |
333 | static int |
334 | msymbol_is_special (struct minimal_symbol *msym) | |
335 | { | |
336 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
337 | } | |
338 | ||
88658117 AC |
339 | /* XFER a value from the big/little/left end of the register. |
340 | Depending on the size of the value it might occupy the entire | |
341 | register or just part of it. Make an allowance for this, aligning | |
342 | things accordingly. */ | |
343 | ||
344 | static void | |
345 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
870cd05e MK |
346 | enum bfd_endian endian, gdb_byte *in, |
347 | const gdb_byte *out, int buf_offset) | |
88658117 | 348 | { |
88658117 | 349 | int reg_offset = 0; |
f57d151a | 350 | gdb_assert (reg_num >= gdbarch_num_regs (current_gdbarch)); |
cb1d2653 AC |
351 | /* Need to transfer the left or right part of the register, based on |
352 | the targets byte order. */ | |
88658117 AC |
353 | switch (endian) |
354 | { | |
355 | case BFD_ENDIAN_BIG: | |
719ec221 | 356 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
357 | break; |
358 | case BFD_ENDIAN_LITTLE: | |
359 | reg_offset = 0; | |
360 | break; | |
6d82d43b | 361 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
362 | reg_offset = 0; |
363 | break; | |
364 | default: | |
e2e0b3e5 | 365 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
366 | } |
367 | if (mips_debug) | |
cb1d2653 AC |
368 | fprintf_unfiltered (gdb_stderr, |
369 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
370 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
371 | if (mips_debug && out != NULL) |
372 | { | |
373 | int i; | |
cb1d2653 | 374 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 375 | for (i = 0; i < length; i++) |
cb1d2653 | 376 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
377 | } |
378 | if (in != NULL) | |
6d82d43b AC |
379 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
380 | in + buf_offset); | |
88658117 | 381 | if (out != NULL) |
6d82d43b AC |
382 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
383 | out + buf_offset); | |
88658117 AC |
384 | if (mips_debug && in != NULL) |
385 | { | |
386 | int i; | |
cb1d2653 | 387 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 388 | for (i = 0; i < length; i++) |
cb1d2653 | 389 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
390 | } |
391 | if (mips_debug) | |
392 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
393 | } | |
394 | ||
dd824b04 DJ |
395 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
396 | compatiblity mode. A return value of 1 means that we have | |
397 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
398 | ||
399 | static int | |
9c9acae0 | 400 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 DJ |
401 | { |
402 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
403 | meaningful. */ | |
6d82d43b AC |
404 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == |
405 | 4) | |
dd824b04 DJ |
406 | return 0; |
407 | ||
408 | #if 0 | |
409 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
410 | in all the places we deal with FP registers. PR gdb/413. */ | |
411 | /* Otherwise check the FR bit in the status register - it controls | |
412 | the FP compatiblity mode. If it is clear we are in compatibility | |
413 | mode. */ | |
9c9acae0 | 414 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
415 | return 1; |
416 | #endif | |
361d1df0 | 417 | |
dd824b04 DJ |
418 | return 0; |
419 | } | |
420 | ||
7a292a7a | 421 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 422 | |
a14ed312 | 423 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 424 | |
a14ed312 | 425 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 426 | |
67b2c998 DJ |
427 | static struct type *mips_float_register_type (void); |
428 | static struct type *mips_double_register_type (void); | |
429 | ||
acdb74a0 AC |
430 | /* The list of available "set mips " and "show mips " commands */ |
431 | ||
432 | static struct cmd_list_element *setmipscmdlist = NULL; | |
433 | static struct cmd_list_element *showmipscmdlist = NULL; | |
434 | ||
5e2e9765 KB |
435 | /* Integer registers 0 thru 31 are handled explicitly by |
436 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 437 | are listed in the following tables. */ |
691c0433 | 438 | |
6d82d43b AC |
439 | enum |
440 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
441 | |
442 | /* Generic MIPS. */ | |
443 | ||
444 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
445 | "sr", "lo", "hi", "bad", "cause", "pc", |
446 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
447 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
448 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
449 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
450 | "fsr", "fir", "" /*"fp" */ , "", | |
451 | "", "", "", "", "", "", "", "", | |
452 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
453 | }; |
454 | ||
455 | /* Names of IDT R3041 registers. */ | |
456 | ||
457 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
458 | "sr", "lo", "hi", "bad", "cause", "pc", |
459 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
460 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
461 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
462 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
463 | "fsr", "fir", "", /*"fp" */ "", | |
464 | "", "", "bus", "ccfg", "", "", "", "", | |
465 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
466 | }; |
467 | ||
468 | /* Names of tx39 registers. */ | |
469 | ||
470 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
471 | "sr", "lo", "hi", "bad", "cause", "pc", |
472 | "", "", "", "", "", "", "", "", | |
473 | "", "", "", "", "", "", "", "", | |
474 | "", "", "", "", "", "", "", "", | |
475 | "", "", "", "", "", "", "", "", | |
476 | "", "", "", "", | |
477 | "", "", "", "", "", "", "", "", | |
478 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
479 | }; |
480 | ||
481 | /* Names of IRIX registers. */ | |
482 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
483 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
484 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
485 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
486 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
487 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
488 | }; |
489 | ||
cce74817 | 490 | |
5e2e9765 | 491 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 492 | static const char * |
5e2e9765 | 493 | mips_register_name (int regno) |
cce74817 | 494 | { |
691c0433 | 495 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
496 | /* GPR names for all ABIs other than n32/n64. */ |
497 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
498 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
499 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
500 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
501 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
502 | }; |
503 | ||
504 | /* GPR names for n32 and n64 ABIs. */ | |
505 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
506 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
507 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
508 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
509 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
510 | }; |
511 | ||
512 | enum mips_abi abi = mips_abi (current_gdbarch); | |
513 | ||
f57d151a UW |
514 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
515 | but then don't make the raw register names visible. */ | |
516 | int rawnum = regno % gdbarch_num_regs (current_gdbarch); | |
517 | if (regno < gdbarch_num_regs (current_gdbarch)) | |
a4b8ebc8 AC |
518 | return ""; |
519 | ||
5e2e9765 KB |
520 | /* The MIPS integer registers are always mapped from 0 to 31. The |
521 | names of the registers (which reflects the conventions regarding | |
522 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 523 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
524 | { |
525 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 526 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 527 | else |
a4b8ebc8 | 528 | return mips_gpr_names[rawnum]; |
5e2e9765 | 529 | } |
f8b73d13 DJ |
530 | else if (tdesc_has_registers (gdbarch_target_desc (current_gdbarch))) |
531 | return tdesc_register_name (rawnum); | |
f57d151a | 532 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (current_gdbarch)) |
691c0433 AC |
533 | { |
534 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
535 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
536 | } | |
5e2e9765 KB |
537 | else |
538 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 539 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 540 | } |
5e2e9765 | 541 | |
a4b8ebc8 | 542 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 543 | |
a4b8ebc8 AC |
544 | static int |
545 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
546 | struct reggroup *reggroup) | |
547 | { | |
548 | int vector_p; | |
549 | int float_p; | |
550 | int raw_p; | |
f57d151a UW |
551 | int rawnum = regnum % gdbarch_num_regs (current_gdbarch); |
552 | int pseudo = regnum / gdbarch_num_regs (current_gdbarch); | |
a4b8ebc8 AC |
553 | if (reggroup == all_reggroup) |
554 | return pseudo; | |
555 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
556 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
557 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
558 | (gdbarch), as not all architectures are multi-arch. */ | |
f57d151a | 559 | raw_p = rawnum < gdbarch_num_regs (current_gdbarch); |
c9f4d572 UW |
560 | if (gdbarch_register_name (current_gdbarch, regnum) == NULL |
561 | || gdbarch_register_name (current_gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
562 | return 0; |
563 | if (reggroup == float_reggroup) | |
564 | return float_p && pseudo; | |
565 | if (reggroup == vector_reggroup) | |
566 | return vector_p && pseudo; | |
567 | if (reggroup == general_reggroup) | |
568 | return (!vector_p && !float_p) && pseudo; | |
569 | /* Save the pseudo registers. Need to make certain that any code | |
570 | extracting register values from a saved register cache also uses | |
571 | pseudo registers. */ | |
572 | if (reggroup == save_reggroup) | |
573 | return raw_p && pseudo; | |
574 | /* Restore the same pseudo register. */ | |
575 | if (reggroup == restore_reggroup) | |
576 | return raw_p && pseudo; | |
6d82d43b | 577 | return 0; |
a4b8ebc8 AC |
578 | } |
579 | ||
f8b73d13 DJ |
580 | /* Return the groups that a MIPS register can be categorised into. |
581 | This version is only used if we have a target description which | |
582 | describes real registers (and their groups). */ | |
583 | ||
584 | static int | |
585 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
586 | struct reggroup *reggroup) | |
587 | { | |
588 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
589 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
590 | int ret; | |
591 | ||
592 | /* Only save, restore, and display the pseudo registers. Need to | |
593 | make certain that any code extracting register values from a | |
594 | saved register cache also uses pseudo registers. | |
595 | ||
596 | Note: saving and restoring the pseudo registers is slightly | |
597 | strange; if we have 64 bits, we should save and restore all | |
598 | 64 bits. But this is hard and has little benefit. */ | |
599 | if (!pseudo) | |
600 | return 0; | |
601 | ||
602 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
603 | if (ret != -1) | |
604 | return ret; | |
605 | ||
606 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
607 | } | |
608 | ||
a4b8ebc8 | 609 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 610 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 611 | registers. Take care of alignment and size problems. */ |
c5aa993b | 612 | |
a4b8ebc8 AC |
613 | static void |
614 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
47a35522 | 615 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 616 | { |
f57d151a UW |
617 | int rawnum = cookednum % gdbarch_num_regs (current_gdbarch); |
618 | gdb_assert (cookednum >= gdbarch_num_regs (current_gdbarch) | |
619 | && cookednum < 2 * gdbarch_num_regs (current_gdbarch)); | |
47ebcfbe | 620 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 621 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
622 | else if (register_size (gdbarch, rawnum) > |
623 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
624 | { |
625 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
4c6b5505 | 626 | || gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
627 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
628 | else | |
629 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
630 | } | |
631 | else | |
e2e0b3e5 | 632 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
633 | } |
634 | ||
635 | static void | |
6d82d43b AC |
636 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
637 | struct regcache *regcache, int cookednum, | |
47a35522 | 638 | const gdb_byte *buf) |
a4b8ebc8 | 639 | { |
f57d151a UW |
640 | int rawnum = cookednum % gdbarch_num_regs (current_gdbarch); |
641 | gdb_assert (cookednum >= gdbarch_num_regs (current_gdbarch) | |
642 | && cookednum < 2 * gdbarch_num_regs (current_gdbarch)); | |
47ebcfbe | 643 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 644 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
645 | else if (register_size (gdbarch, rawnum) > |
646 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
647 | { |
648 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
4c6b5505 | 649 | || gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
650 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
651 | else | |
652 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
653 | } | |
654 | else | |
e2e0b3e5 | 655 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 656 | } |
c5aa993b | 657 | |
c906108c | 658 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 659 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
660 | |
661 | /* Heuristic_proc_start may hunt through the text section for a long | |
662 | time across a 2400 baud serial line. Allows the user to limit this | |
663 | search. */ | |
664 | ||
665 | static unsigned int heuristic_fence_post = 0; | |
666 | ||
46cd78fb | 667 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
668 | register N. NOTE: This defines the pseudo register type so need to |
669 | rebuild the architecture vector. */ | |
43e526b9 JM |
670 | |
671 | static int mips64_transfers_32bit_regs_p = 0; | |
672 | ||
719ec221 AC |
673 | static void |
674 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
675 | struct cmd_list_element *c) | |
43e526b9 | 676 | { |
719ec221 AC |
677 | struct gdbarch_info info; |
678 | gdbarch_info_init (&info); | |
679 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
680 | instead of relying on globals. Doing that would let generic code | |
681 | handle the search for this specific architecture. */ | |
682 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 683 | { |
719ec221 | 684 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 685 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 686 | } |
a4b8ebc8 AC |
687 | } |
688 | ||
47ebcfbe | 689 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 690 | |
ff2e87ac AC |
691 | static int |
692 | mips_convert_register_p (int regnum, struct type *type) | |
693 | { | |
4c6b5505 | 694 | return (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
719ec221 | 695 | && register_size (current_gdbarch, regnum) == 4 |
f57d151a UW |
696 | && (regnum % gdbarch_num_regs (current_gdbarch)) |
697 | >= mips_regnum (current_gdbarch)->fp0 | |
698 | && (regnum % gdbarch_num_regs (current_gdbarch)) | |
699 | < mips_regnum (current_gdbarch)->fp0 + 32 | |
6d82d43b | 700 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
701 | } |
702 | ||
42c466d7 | 703 | static void |
ff2e87ac | 704 | mips_register_to_value (struct frame_info *frame, int regnum, |
47a35522 | 705 | struct type *type, gdb_byte *to) |
102182a9 | 706 | { |
47a35522 MK |
707 | get_frame_register (frame, regnum + 0, to + 4); |
708 | get_frame_register (frame, regnum + 1, to + 0); | |
102182a9 MS |
709 | } |
710 | ||
42c466d7 | 711 | static void |
ff2e87ac | 712 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 713 | struct type *type, const gdb_byte *from) |
102182a9 | 714 | { |
47a35522 MK |
715 | put_frame_register (frame, regnum + 0, from + 4); |
716 | put_frame_register (frame, regnum + 1, from + 0); | |
102182a9 MS |
717 | } |
718 | ||
a4b8ebc8 AC |
719 | /* Return the GDB type object for the "standard" data type of data in |
720 | register REG. */ | |
78fde5f8 KB |
721 | |
722 | static struct type * | |
a4b8ebc8 AC |
723 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
724 | { | |
f57d151a UW |
725 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (current_gdbarch)); |
726 | if ((regnum % gdbarch_num_regs (current_gdbarch)) | |
727 | >= mips_regnum (current_gdbarch)->fp0 | |
728 | && (regnum % gdbarch_num_regs (current_gdbarch)) | |
729 | < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 730 | { |
5ef80fb0 | 731 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 732 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 DJ |
733 | if (mips_isa_regsize (gdbarch) == 4) |
734 | return builtin_type_ieee_single; | |
735 | else | |
736 | return builtin_type_ieee_double; | |
a6425924 | 737 | } |
f57d151a | 738 | else if (regnum < gdbarch_num_regs (current_gdbarch)) |
d5ac5a39 AC |
739 | { |
740 | /* The raw or ISA registers. These are all sized according to | |
741 | the ISA regsize. */ | |
742 | if (mips_isa_regsize (gdbarch) == 4) | |
743 | return builtin_type_int32; | |
744 | else | |
745 | return builtin_type_int64; | |
746 | } | |
78fde5f8 | 747 | else |
d5ac5a39 AC |
748 | { |
749 | /* The cooked or ABI registers. These are sized according to | |
750 | the ABI (with a few complications). */ | |
f57d151a | 751 | if (regnum >= (gdbarch_num_regs (current_gdbarch) |
d5ac5a39 | 752 | + mips_regnum (current_gdbarch)->fp_control_status) |
f57d151a UW |
753 | && regnum <= gdbarch_num_regs (current_gdbarch) |
754 | + MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
755 | /* The pseudo/cooked view of the embedded registers is always |
756 | 32-bit. The raw view is handled below. */ | |
757 | return builtin_type_int32; | |
758 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
759 | /* The target, while possibly using a 64-bit register buffer, | |
760 | is only transfering 32-bits of each integer register. | |
761 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
762 | return builtin_type_int32; | |
763 | else if (mips_abi_regsize (gdbarch) == 4) | |
764 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
765 | 32- or 64-bit). */ | |
766 | return builtin_type_int32; | |
767 | else | |
768 | /* 64-bit ABI. */ | |
769 | return builtin_type_int64; | |
770 | } | |
78fde5f8 KB |
771 | } |
772 | ||
f8b73d13 DJ |
773 | /* Return the GDB type for the pseudo register REGNUM, which is the |
774 | ABI-level view. This function is only called if there is a target | |
775 | description which includes registers, so we know precisely the | |
776 | types of hardware registers. */ | |
777 | ||
778 | static struct type * | |
779 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
780 | { | |
781 | const int num_regs = gdbarch_num_regs (gdbarch); | |
782 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
783 | int rawnum = regnum % num_regs; | |
784 | struct type *rawtype; | |
785 | ||
786 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
787 | ||
788 | /* Absent registers are still absent. */ | |
789 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
790 | if (TYPE_LENGTH (rawtype) == 0) | |
791 | return rawtype; | |
792 | ||
793 | if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32) | |
794 | /* Present the floating point registers however the hardware did; | |
795 | do not try to convert between FPU layouts. */ | |
796 | return rawtype; | |
797 | ||
798 | if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
799 | { | |
800 | /* The pseudo/cooked view of embedded registers is always | |
801 | 32-bit, even if the target transfers 64-bit values for them. | |
802 | New targets relying on XML descriptions should only transfer | |
803 | the necessary 32 bits, but older versions of GDB expected 64, | |
804 | so allow the target to provide 64 bits without interfering | |
805 | with the displayed type. */ | |
806 | return builtin_type_int32; | |
807 | } | |
808 | ||
809 | /* Use pointer types for registers if we can. For n32 we can not, | |
810 | since we do not have a 64-bit pointer type. */ | |
811 | if (mips_abi_regsize (gdbarch) == TYPE_LENGTH (builtin_type_void_data_ptr)) | |
812 | { | |
813 | if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM) | |
814 | return builtin_type_void_data_ptr; | |
815 | else if (rawnum == MIPS_EMBED_PC_REGNUM) | |
816 | return builtin_type_void_func_ptr; | |
817 | } | |
818 | ||
819 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
820 | && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM) | |
821 | return builtin_type_int32; | |
822 | ||
823 | /* For all other registers, pass through the hardware type. */ | |
824 | return rawtype; | |
825 | } | |
bcb0cc15 | 826 | |
c906108c | 827 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 828 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
829 | |
830 | static int | |
480d3dd2 | 831 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
832 | { |
833 | switch (mask_address_var) | |
834 | { | |
7f19b9a2 | 835 | case AUTO_BOOLEAN_TRUE: |
4014092b | 836 | return 1; |
7f19b9a2 | 837 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
838 | return 0; |
839 | break; | |
7f19b9a2 | 840 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 841 | return tdep->default_mask_address_p; |
4014092b | 842 | default: |
e2e0b3e5 | 843 | internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch")); |
4014092b | 844 | return -1; |
361d1df0 | 845 | } |
4014092b AC |
846 | } |
847 | ||
848 | static void | |
08546159 AC |
849 | show_mask_address (struct ui_file *file, int from_tty, |
850 | struct cmd_list_element *c, const char *value) | |
4014092b | 851 | { |
480d3dd2 | 852 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
08546159 AC |
853 | |
854 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
855 | switch (mask_address_var) |
856 | { | |
7f19b9a2 | 857 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
858 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
859 | break; | |
7f19b9a2 | 860 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
861 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
862 | break; | |
7f19b9a2 | 863 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
864 | printf_filtered |
865 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
866 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
867 | break; |
868 | default: | |
e2e0b3e5 | 869 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 870 | break; |
361d1df0 | 871 | } |
4014092b | 872 | } |
c906108c | 873 | |
c906108c SS |
874 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
875 | ||
0fe7e7c8 AC |
876 | int |
877 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
878 | { |
879 | struct minimal_symbol *sym; | |
880 | ||
881 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 882 | if (is_mips16_addr (memaddr)) |
c906108c SS |
883 | return 1; |
884 | ||
885 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
886 | the high bit of the info field. Use this to decide if the function is | |
887 | MIPS16 or normal MIPS. */ | |
888 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
889 | if (sym) | |
71b8ef93 | 890 | return msymbol_is_special (sym); |
c906108c SS |
891 | else |
892 | return 0; | |
893 | } | |
894 | ||
b2fa5097 | 895 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
896 | all registers should be sign extended for simplicity? */ |
897 | ||
898 | static CORE_ADDR | |
61a1198a | 899 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 900 | { |
61a1198a UW |
901 | ULONGEST pc; |
902 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; | |
903 | regcache_cooked_read_signed (regcache, regnum, &pc); | |
904 | return pc; | |
b6cb9035 AC |
905 | } |
906 | ||
58dfe9ff AC |
907 | static CORE_ADDR |
908 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
909 | { | |
edfae063 | 910 | return frame_unwind_register_signed (next_frame, |
f57d151a UW |
911 | gdbarch_num_regs (current_gdbarch) |
912 | + mips_regnum (gdbarch)->pc); | |
edfae063 AC |
913 | } |
914 | ||
30244cd8 UW |
915 | static CORE_ADDR |
916 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
917 | { | |
f57d151a UW |
918 | return frame_unwind_register_signed (next_frame, |
919 | gdbarch_num_regs (current_gdbarch) | |
920 | + MIPS_SP_REGNUM); | |
30244cd8 UW |
921 | } |
922 | ||
edfae063 AC |
923 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
924 | dummy frame. The frame ID's base needs to match the TOS value | |
925 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
926 | breakpoint. */ | |
927 | ||
928 | static struct frame_id | |
929 | mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
930 | { | |
f57d151a UW |
931 | return frame_id_build |
932 | (frame_unwind_register_signed (next_frame, | |
933 | gdbarch_num_regs (current_gdbarch) | |
934 | + MIPS_SP_REGNUM), | |
935 | frame_pc_unwind (next_frame)); | |
58dfe9ff AC |
936 | } |
937 | ||
b6cb9035 | 938 | static void |
61a1198a | 939 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 940 | { |
61a1198a UW |
941 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; |
942 | regcache_cooked_write_unsigned (regcache, regnum, pc); | |
6c997a34 | 943 | } |
c906108c | 944 | |
c906108c SS |
945 | /* Fetch and return instruction from the specified location. If the PC |
946 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
947 | ||
d37cca3d | 948 | static ULONGEST |
acdb74a0 | 949 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c | 950 | { |
47a35522 | 951 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
952 | int instlen; |
953 | int status; | |
954 | ||
0fe7e7c8 | 955 | if (mips_pc_is_mips16 (addr)) |
c906108c | 956 | { |
95ac2dcf | 957 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 958 | addr = unmake_mips16_addr (addr); |
c906108c SS |
959 | } |
960 | else | |
95ac2dcf | 961 | instlen = MIPS_INSN32_SIZE; |
359a9262 | 962 | status = read_memory_nobpt (addr, buf, instlen); |
c906108c SS |
963 | if (status) |
964 | memory_error (status, addr); | |
965 | return extract_unsigned_integer (buf, instlen); | |
966 | } | |
967 | ||
c906108c | 968 | /* These the fields of 32 bit mips instructions */ |
e135b889 DJ |
969 | #define mips32_op(x) (x >> 26) |
970 | #define itype_op(x) (x >> 26) | |
971 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 972 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 973 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 974 | |
e135b889 DJ |
975 | #define jtype_op(x) (x >> 26) |
976 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 977 | |
e135b889 DJ |
978 | #define rtype_op(x) (x >> 26) |
979 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
980 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
981 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
982 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
983 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 984 | |
06987e64 MK |
985 | static LONGEST |
986 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 987 | { |
06987e64 | 988 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
989 | } |
990 | ||
f49e4e6d MS |
991 | /* Determine where to set a single step breakpoint while considering |
992 | branch prediction. */ | |
5a89d8aa | 993 | static CORE_ADDR |
0b1b3e42 | 994 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b JM |
995 | { |
996 | unsigned long inst; | |
997 | int op; | |
998 | inst = mips_fetch_instruction (pc); | |
e135b889 | 999 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 1000 | { |
e135b889 | 1001 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1002 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1003 | { |
e135b889 | 1004 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1005 | switch (op) |
1006 | { | |
e135b889 DJ |
1007 | case 0: /* BEQL */ |
1008 | goto equal_branch; | |
1009 | case 1: /* BNEL */ | |
1010 | goto neq_branch; | |
1011 | case 2: /* BLEZL */ | |
1012 | goto less_branch; | |
1013 | case 3: /* BGTZ */ | |
1014 | goto greater_branch; | |
c5aa993b JM |
1015 | default: |
1016 | pc += 4; | |
c906108c SS |
1017 | } |
1018 | } | |
e135b889 | 1019 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1020 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
1021 | { |
1022 | int tf = itype_rt (inst) & 0x01; | |
1023 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b | 1024 | int fcrcs = |
0b1b3e42 UW |
1025 | get_frame_register_signed (frame, mips_regnum (current_gdbarch)-> |
1026 | fp_control_status); | |
e135b889 DJ |
1027 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1028 | ||
1029 | if (((cond >> cnum) & 0x01) == tf) | |
1030 | pc += mips32_relative_offset (inst) + 4; | |
1031 | else | |
1032 | pc += 8; | |
1033 | } | |
c5aa993b JM |
1034 | else |
1035 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1036 | } |
1037 | else | |
c5aa993b JM |
1038 | { /* This gets way messy */ |
1039 | ||
c906108c | 1040 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1041 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1042 | { |
c5aa993b JM |
1043 | case 0: /* SPECIAL */ |
1044 | op = rtype_funct (inst); | |
1045 | switch (op) | |
1046 | { | |
1047 | case 8: /* JR */ | |
1048 | case 9: /* JALR */ | |
6c997a34 | 1049 | /* Set PC to that address */ |
0b1b3e42 | 1050 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b JM |
1051 | break; |
1052 | default: | |
1053 | pc += 4; | |
1054 | } | |
1055 | ||
6d82d43b | 1056 | break; /* end SPECIAL */ |
c5aa993b | 1057 | case 1: /* REGIMM */ |
c906108c | 1058 | { |
e135b889 DJ |
1059 | op = itype_rt (inst); /* branch condition */ |
1060 | switch (op) | |
c906108c | 1061 | { |
c5aa993b | 1062 | case 0: /* BLTZ */ |
e135b889 DJ |
1063 | case 2: /* BLTZL */ |
1064 | case 16: /* BLTZAL */ | |
c5aa993b | 1065 | case 18: /* BLTZALL */ |
c906108c | 1066 | less_branch: |
0b1b3e42 | 1067 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1068 | pc += mips32_relative_offset (inst) + 4; |
1069 | else | |
1070 | pc += 8; /* after the delay slot */ | |
1071 | break; | |
e135b889 | 1072 | case 1: /* BGEZ */ |
c5aa993b JM |
1073 | case 3: /* BGEZL */ |
1074 | case 17: /* BGEZAL */ | |
1075 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1076 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1077 | pc += mips32_relative_offset (inst) + 4; |
1078 | else | |
1079 | pc += 8; /* after the delay slot */ | |
1080 | break; | |
e135b889 | 1081 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1082 | default: |
1083 | pc += 4; | |
c906108c SS |
1084 | } |
1085 | } | |
6d82d43b | 1086 | break; /* end REGIMM */ |
c5aa993b JM |
1087 | case 2: /* J */ |
1088 | case 3: /* JAL */ | |
1089 | { | |
1090 | unsigned long reg; | |
1091 | reg = jtype_target (inst) << 2; | |
e135b889 | 1092 | /* Upper four bits get never changed... */ |
5b652102 | 1093 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1094 | } |
c5aa993b JM |
1095 | break; |
1096 | /* FIXME case JALX : */ | |
1097 | { | |
1098 | unsigned long reg; | |
1099 | reg = jtype_target (inst) << 2; | |
5b652102 | 1100 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ |
c906108c SS |
1101 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1102 | } | |
c5aa993b | 1103 | break; /* The new PC will be alternate mode */ |
e135b889 | 1104 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1105 | equal_branch: |
0b1b3e42 UW |
1106 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1107 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1108 | pc += mips32_relative_offset (inst) + 4; |
1109 | else | |
1110 | pc += 8; | |
1111 | break; | |
e135b889 | 1112 | case 5: /* BNE, BNEL */ |
c5aa993b | 1113 | neq_branch: |
0b1b3e42 UW |
1114 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1115 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1116 | pc += mips32_relative_offset (inst) + 4; |
1117 | else | |
1118 | pc += 8; | |
1119 | break; | |
e135b889 | 1120 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1121 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1122 | pc += mips32_relative_offset (inst) + 4; |
1123 | else | |
1124 | pc += 8; | |
1125 | break; | |
1126 | case 7: | |
e135b889 DJ |
1127 | default: |
1128 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1129 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1130 | pc += mips32_relative_offset (inst) + 4; |
1131 | else | |
1132 | pc += 8; | |
1133 | break; | |
c5aa993b JM |
1134 | } /* switch */ |
1135 | } /* else */ | |
1136 | return pc; | |
1137 | } /* mips32_next_pc */ | |
c906108c SS |
1138 | |
1139 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1140 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1141 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1142 | We dont want to set a single step instruction on the extend instruction | |
1143 | either. | |
c5aa993b | 1144 | */ |
c906108c SS |
1145 | |
1146 | /* Lots of mips16 instruction formats */ | |
1147 | /* Predicting jumps requires itype,ritype,i8type | |
1148 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1149 | */ |
c906108c SS |
1150 | enum mips16_inst_fmts |
1151 | { | |
c5aa993b JM |
1152 | itype, /* 0 immediate 5,10 */ |
1153 | ritype, /* 1 5,3,8 */ | |
1154 | rrtype, /* 2 5,3,3,5 */ | |
1155 | rritype, /* 3 5,3,3,5 */ | |
1156 | rrrtype, /* 4 5,3,3,3,2 */ | |
1157 | rriatype, /* 5 5,3,3,1,4 */ | |
1158 | shifttype, /* 6 5,3,3,3,2 */ | |
1159 | i8type, /* 7 5,3,8 */ | |
1160 | i8movtype, /* 8 5,3,3,5 */ | |
1161 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1162 | i64type, /* 10 5,3,8 */ | |
1163 | ri64type, /* 11 5,3,3,5 */ | |
1164 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1165 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1166 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1167 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1168 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1169 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1170 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1171 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1172 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1173 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1174 | }; | |
12f02c2a AC |
1175 | /* I am heaping all the fields of the formats into one structure and |
1176 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1177 | struct upk_mips16 |
6d82d43b AC |
1178 | { |
1179 | CORE_ADDR offset; | |
1180 | unsigned int regx; /* Function in i8 type */ | |
1181 | unsigned int regy; | |
1182 | }; | |
c906108c SS |
1183 | |
1184 | ||
12f02c2a AC |
1185 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1186 | for the bits which make up the immediatate extension. */ | |
c906108c | 1187 | |
12f02c2a AC |
1188 | static CORE_ADDR |
1189 | extended_offset (unsigned int extension) | |
c906108c | 1190 | { |
12f02c2a | 1191 | CORE_ADDR value; |
c5aa993b JM |
1192 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1193 | value = value << 6; | |
1194 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1195 | value = value << 5; | |
1196 | value |= extension & 0x01f; /* extract 4:0 */ | |
1197 | return value; | |
c906108c SS |
1198 | } |
1199 | ||
1200 | /* Only call this function if you know that this is an extendable | |
1201 | instruction, It wont malfunction, but why make excess remote memory references? | |
1202 | If the immediate operands get sign extended or somthing, do it after | |
1203 | the extension is performed. | |
c5aa993b | 1204 | */ |
c906108c SS |
1205 | /* FIXME: Every one of these cases needs to worry about sign extension |
1206 | when the offset is to be used in relative addressing */ | |
1207 | ||
1208 | ||
12f02c2a | 1209 | static unsigned int |
c5aa993b | 1210 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1211 | { |
47a35522 | 1212 | gdb_byte buf[8]; |
c5aa993b JM |
1213 | pc &= 0xfffffffe; /* clear the low order bit */ |
1214 | target_read_memory (pc, buf, 2); | |
1215 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1216 | } |
1217 | ||
1218 | static void | |
c5aa993b | 1219 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1220 | unsigned int extension, |
1221 | unsigned int inst, | |
6d82d43b | 1222 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1223 | { |
12f02c2a AC |
1224 | CORE_ADDR offset; |
1225 | int regx; | |
1226 | int regy; | |
1227 | switch (insn_format) | |
c906108c | 1228 | { |
c5aa993b | 1229 | case itype: |
c906108c | 1230 | { |
12f02c2a AC |
1231 | CORE_ADDR value; |
1232 | if (extension) | |
c5aa993b JM |
1233 | { |
1234 | value = extended_offset (extension); | |
1235 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1236 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1237 | } |
1238 | else | |
c5aa993b | 1239 | { |
12f02c2a | 1240 | value = inst & 0x7ff; |
c5aa993b | 1241 | /* FIXME : Consider sign extension */ |
c906108c | 1242 | } |
12f02c2a AC |
1243 | offset = value; |
1244 | regx = -1; | |
1245 | regy = -1; | |
c906108c | 1246 | } |
c5aa993b JM |
1247 | break; |
1248 | case ritype: | |
1249 | case i8type: | |
1250 | { /* A register identifier and an offset */ | |
c906108c SS |
1251 | /* Most of the fields are the same as I type but the |
1252 | immediate value is of a different length */ | |
12f02c2a AC |
1253 | CORE_ADDR value; |
1254 | if (extension) | |
c906108c | 1255 | { |
c5aa993b JM |
1256 | value = extended_offset (extension); |
1257 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1258 | value |= inst & 0xff; /* eleven bits from instruction */ |
1259 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1260 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1261 | { | |
1262 | value &= ~0x3fff; /* remove the sign bit */ | |
1263 | value = -value; | |
c906108c SS |
1264 | } |
1265 | } | |
c5aa993b JM |
1266 | else |
1267 | { | |
12f02c2a AC |
1268 | value = inst & 0xff; /* 8 bits */ |
1269 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1270 | /* FIXME: Do sign extension , this format needs it */ |
1271 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1272 | { | |
1273 | value &= 0xef; /* remove the sign bit */ | |
1274 | value = -value; | |
1275 | } | |
c5aa993b | 1276 | } |
12f02c2a AC |
1277 | offset = value; |
1278 | regy = -1; | |
c5aa993b | 1279 | break; |
c906108c | 1280 | } |
c5aa993b | 1281 | case jalxtype: |
c906108c | 1282 | { |
c5aa993b | 1283 | unsigned long value; |
12f02c2a AC |
1284 | unsigned int nexthalf; |
1285 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1286 | value = value << 16; |
1287 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1288 | value |= nexthalf; | |
12f02c2a AC |
1289 | offset = value; |
1290 | regx = -1; | |
1291 | regy = -1; | |
c5aa993b | 1292 | break; |
c906108c SS |
1293 | } |
1294 | default: | |
e2e0b3e5 | 1295 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1296 | } |
12f02c2a AC |
1297 | upk->offset = offset; |
1298 | upk->regx = regx; | |
1299 | upk->regy = regy; | |
c906108c SS |
1300 | } |
1301 | ||
1302 | ||
c5aa993b JM |
1303 | static CORE_ADDR |
1304 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1305 | { |
5b652102 | 1306 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
1307 | } |
1308 | ||
12f02c2a | 1309 | static CORE_ADDR |
0b1b3e42 | 1310 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 1311 | unsigned int extension, unsigned int insn) |
c906108c | 1312 | { |
12f02c2a AC |
1313 | int op = (insn >> 11); |
1314 | switch (op) | |
c906108c | 1315 | { |
6d82d43b | 1316 | case 2: /* Branch */ |
12f02c2a AC |
1317 | { |
1318 | CORE_ADDR offset; | |
1319 | struct upk_mips16 upk; | |
1320 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1321 | offset = upk.offset; | |
1322 | if (offset & 0x800) | |
1323 | { | |
1324 | offset &= 0xeff; | |
1325 | offset = -offset; | |
1326 | } | |
1327 | pc += (offset << 1) + 2; | |
1328 | break; | |
1329 | } | |
6d82d43b | 1330 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1331 | { |
1332 | struct upk_mips16 upk; | |
1333 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1334 | pc = add_offset_16 (pc, upk.offset); | |
1335 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1336 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1337 | else | |
1338 | pc |= 0x01; | |
1339 | break; | |
1340 | } | |
6d82d43b | 1341 | case 4: /* beqz */ |
12f02c2a AC |
1342 | { |
1343 | struct upk_mips16 upk; | |
1344 | int reg; | |
1345 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
0b1b3e42 | 1346 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1347 | if (reg == 0) |
1348 | pc += (upk.offset << 1) + 2; | |
1349 | else | |
1350 | pc += 2; | |
1351 | break; | |
1352 | } | |
6d82d43b | 1353 | case 5: /* bnez */ |
12f02c2a AC |
1354 | { |
1355 | struct upk_mips16 upk; | |
1356 | int reg; | |
1357 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
0b1b3e42 | 1358 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1359 | if (reg != 0) |
1360 | pc += (upk.offset << 1) + 2; | |
1361 | else | |
1362 | pc += 2; | |
1363 | break; | |
1364 | } | |
6d82d43b | 1365 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1366 | { |
1367 | struct upk_mips16 upk; | |
1368 | int reg; | |
1369 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1370 | /* upk.regx contains the opcode */ | |
0b1b3e42 | 1371 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
1372 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
1373 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1374 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1375 | pc += (upk.offset << 1) + 2; | |
1376 | else | |
1377 | pc += 2; | |
1378 | break; | |
1379 | } | |
6d82d43b | 1380 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1381 | { |
1382 | struct upk_mips16 upk; | |
1383 | /* upk.fmt = rrtype; */ | |
1384 | op = insn & 0x1f; | |
1385 | if (op == 0) | |
c5aa993b | 1386 | { |
12f02c2a AC |
1387 | int reg; |
1388 | upk.regx = (insn >> 8) & 0x07; | |
1389 | upk.regy = (insn >> 5) & 0x07; | |
1390 | switch (upk.regy) | |
c5aa993b | 1391 | { |
12f02c2a AC |
1392 | case 0: |
1393 | reg = upk.regx; | |
1394 | break; | |
1395 | case 1: | |
1396 | reg = 31; | |
6d82d43b | 1397 | break; /* Function return instruction */ |
12f02c2a AC |
1398 | case 2: |
1399 | reg = upk.regx; | |
1400 | break; | |
1401 | default: | |
1402 | reg = 31; | |
6d82d43b | 1403 | break; /* BOGUS Guess */ |
c906108c | 1404 | } |
0b1b3e42 | 1405 | pc = get_frame_register_signed (frame, reg); |
c906108c | 1406 | } |
12f02c2a | 1407 | else |
c5aa993b | 1408 | pc += 2; |
12f02c2a AC |
1409 | break; |
1410 | } | |
1411 | case 30: | |
1412 | /* This is an instruction extension. Fetch the real instruction | |
1413 | (which follows the extension) and decode things based on | |
1414 | that. */ | |
1415 | { | |
1416 | pc += 2; | |
0b1b3e42 | 1417 | pc = extended_mips16_next_pc (frame, pc, insn, fetch_mips_16 (pc)); |
12f02c2a AC |
1418 | break; |
1419 | } | |
1420 | default: | |
1421 | { | |
1422 | pc += 2; | |
1423 | break; | |
1424 | } | |
c906108c | 1425 | } |
c5aa993b | 1426 | return pc; |
12f02c2a | 1427 | } |
c906108c | 1428 | |
5a89d8aa | 1429 | static CORE_ADDR |
0b1b3e42 | 1430 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a AC |
1431 | { |
1432 | unsigned int insn = fetch_mips_16 (pc); | |
0b1b3e42 | 1433 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
1434 | } |
1435 | ||
1436 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1437 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1438 | It works by decoding the current instruction and predicting where a |
1439 | branch will go. This isnt hard because all the data is available. | |
1440 | The MIPS32 and MIPS16 variants are quite different */ | |
ad527d2e | 1441 | static CORE_ADDR |
0b1b3e42 | 1442 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1443 | { |
c5aa993b | 1444 | if (pc & 0x01) |
0b1b3e42 | 1445 | return mips16_next_pc (frame, pc); |
c5aa993b | 1446 | else |
0b1b3e42 | 1447 | return mips32_next_pc (frame, pc); |
12f02c2a | 1448 | } |
c906108c | 1449 | |
edfae063 AC |
1450 | struct mips_frame_cache |
1451 | { | |
1452 | CORE_ADDR base; | |
1453 | struct trad_frame_saved_reg *saved_regs; | |
1454 | }; | |
1455 | ||
29639122 JB |
1456 | /* Set a register's saved stack address in temp_saved_regs. If an |
1457 | address has already been set for this register, do nothing; this | |
1458 | way we will only recognize the first save of a given register in a | |
1459 | function prologue. | |
eec63939 | 1460 | |
f57d151a UW |
1461 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
1462 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
1463 | Strictly speaking, only the second range is used as it is only second | |
1464 | range (the ABI instead of ISA registers) that comes into play when finding | |
1465 | saved registers in a frame. */ | |
eec63939 AC |
1466 | |
1467 | static void | |
29639122 JB |
1468 | set_reg_offset (struct mips_frame_cache *this_cache, int regnum, |
1469 | CORE_ADDR offset) | |
eec63939 | 1470 | { |
29639122 JB |
1471 | if (this_cache != NULL |
1472 | && this_cache->saved_regs[regnum].addr == -1) | |
1473 | { | |
f57d151a UW |
1474 | this_cache->saved_regs[regnum |
1475 | + 0 * gdbarch_num_regs (current_gdbarch)].addr | |
1476 | = offset; | |
1477 | this_cache->saved_regs[regnum | |
1478 | + 1 * gdbarch_num_regs (current_gdbarch)].addr | |
1479 | = offset; | |
29639122 | 1480 | } |
eec63939 AC |
1481 | } |
1482 | ||
eec63939 | 1483 | |
29639122 JB |
1484 | /* Fetch the immediate value from a MIPS16 instruction. |
1485 | If the previous instruction was an EXTEND, use it to extend | |
1486 | the upper bits of the immediate value. This is a helper function | |
1487 | for mips16_scan_prologue. */ | |
eec63939 | 1488 | |
29639122 JB |
1489 | static int |
1490 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1491 | unsigned short inst, /* current instruction */ | |
1492 | int nbits, /* number of bits in imm field */ | |
1493 | int scale, /* scale factor to be applied to imm */ | |
1494 | int is_signed) /* is the imm field signed? */ | |
eec63939 | 1495 | { |
29639122 | 1496 | int offset; |
eec63939 | 1497 | |
29639122 JB |
1498 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1499 | { | |
1500 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1501 | if (offset & 0x8000) /* check for negative extend */ | |
1502 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1503 | return offset | (inst & 0x1f); | |
1504 | } | |
eec63939 | 1505 | else |
29639122 JB |
1506 | { |
1507 | int max_imm = 1 << nbits; | |
1508 | int mask = max_imm - 1; | |
1509 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1510 | |
29639122 JB |
1511 | offset = inst & mask; |
1512 | if (is_signed && (offset & sign_bit)) | |
1513 | offset = 0 - (max_imm - offset); | |
1514 | return offset * scale; | |
1515 | } | |
1516 | } | |
eec63939 | 1517 | |
65596487 | 1518 | |
29639122 JB |
1519 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1520 | the associated FRAME_CACHE if not null. | |
1521 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1522 | |
29639122 JB |
1523 | static CORE_ADDR |
1524 | mips16_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
1525 | struct frame_info *next_frame, | |
1526 | struct mips_frame_cache *this_cache) | |
1527 | { | |
1528 | CORE_ADDR cur_pc; | |
1529 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1530 | CORE_ADDR sp; | |
1531 | long frame_offset = 0; /* Size of stack frame. */ | |
1532 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1533 | int frame_reg = MIPS_SP_REGNUM; | |
1534 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1535 | unsigned inst = 0; /* current instruction */ | |
1536 | unsigned entry_inst = 0; /* the entry instruction */ | |
1537 | int reg, offset; | |
a343eb3c | 1538 | |
29639122 JB |
1539 | int extend_bytes = 0; |
1540 | int prev_extend_bytes; | |
1541 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 1542 | |
29639122 JB |
1543 | /* Can be called when there's no process, and hence when there's no |
1544 | NEXT_FRAME. */ | |
1545 | if (next_frame != NULL) | |
d2ca4222 UW |
1546 | sp = frame_unwind_register_signed (next_frame, |
1547 | gdbarch_num_regs (current_gdbarch) | |
1548 | + MIPS_SP_REGNUM); | |
29639122 JB |
1549 | else |
1550 | sp = 0; | |
eec63939 | 1551 | |
29639122 JB |
1552 | if (limit_pc > start_pc + 200) |
1553 | limit_pc = start_pc + 200; | |
eec63939 | 1554 | |
95ac2dcf | 1555 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1556 | { |
1557 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1558 | the immediate offset extension from it in mips16_get_imm. */ | |
1559 | prev_inst = inst; | |
eec63939 | 1560 | |
29639122 JB |
1561 | /* Fetch and decode the instruction. */ |
1562 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
eec63939 | 1563 | |
29639122 JB |
1564 | /* Normally we ignore extend instructions. However, if it is |
1565 | not followed by a valid prologue instruction, then this | |
1566 | instruction is not part of the prologue either. We must | |
1567 | remember in this case to adjust the end_prologue_addr back | |
1568 | over the extend. */ | |
1569 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1570 | { | |
95ac2dcf | 1571 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1572 | continue; |
1573 | } | |
eec63939 | 1574 | |
29639122 JB |
1575 | prev_extend_bytes = extend_bytes; |
1576 | extend_bytes = 0; | |
eec63939 | 1577 | |
29639122 JB |
1578 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1579 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1580 | { | |
1581 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
1582 | if (offset < 0) /* negative stack adjustment? */ | |
1583 | frame_offset -= offset; | |
1584 | else | |
1585 | /* Exit loop if a positive stack adjustment is found, which | |
1586 | usually means that the stack cleanup code in the function | |
1587 | epilogue is reached. */ | |
1588 | break; | |
1589 | } | |
1590 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1591 | { | |
1592 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1593 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
1594 | set_reg_offset (this_cache, reg, sp + offset); | |
1595 | } | |
1596 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1597 | { | |
1598 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1599 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1600 | set_reg_offset (this_cache, reg, sp + offset); | |
1601 | } | |
1602 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1603 | { | |
1604 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4c7d22cb | 1605 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1606 | } |
1607 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1608 | { | |
1609 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
4c7d22cb | 1610 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1611 | } |
1612 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1613 | { | |
1614 | frame_addr = sp; | |
1615 | frame_reg = 17; | |
1616 | } | |
1617 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1618 | { | |
1619 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1620 | frame_addr = sp + offset; | |
1621 | frame_reg = 17; | |
1622 | frame_adjust = offset; | |
1623 | } | |
1624 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1625 | { | |
1626 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1627 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1628 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1629 | } | |
1630 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1631 | { | |
1632 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1633 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1634 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1635 | } | |
1636 | else if ((inst & 0xf81f) == 0xe809 | |
1637 | && (inst & 0x700) != 0x700) /* entry */ | |
1638 | entry_inst = inst; /* save for later processing */ | |
1639 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ | |
95ac2dcf | 1640 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1641 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1642 | { | |
1643 | /* This instruction is part of the prologue, but we don't | |
1644 | need to do anything special to handle it. */ | |
1645 | } | |
1646 | else | |
1647 | { | |
1648 | /* This instruction is not an instruction typically found | |
1649 | in a prologue, so we must have reached the end of the | |
1650 | prologue. */ | |
1651 | if (end_prologue_addr == 0) | |
1652 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1653 | } | |
1654 | } | |
eec63939 | 1655 | |
29639122 JB |
1656 | /* The entry instruction is typically the first instruction in a function, |
1657 | and it stores registers at offsets relative to the value of the old SP | |
1658 | (before the prologue). But the value of the sp parameter to this | |
1659 | function is the new SP (after the prologue has been executed). So we | |
1660 | can't calculate those offsets until we've seen the entire prologue, | |
1661 | and can calculate what the old SP must have been. */ | |
1662 | if (entry_inst != 0) | |
1663 | { | |
1664 | int areg_count = (entry_inst >> 8) & 7; | |
1665 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1666 | |
29639122 JB |
1667 | /* The entry instruction always subtracts 32 from the SP. */ |
1668 | frame_offset += 32; | |
1669 | ||
1670 | /* Now we can calculate what the SP must have been at the | |
1671 | start of the function prologue. */ | |
1672 | sp += frame_offset; | |
1673 | ||
1674 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1675 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1676 | { | |
1677 | set_reg_offset (this_cache, reg, sp + offset); | |
1678 | offset += mips_abi_regsize (current_gdbarch); | |
1679 | } | |
1680 | ||
1681 | /* Check if the ra register was pushed on the stack. */ | |
1682 | offset = -4; | |
1683 | if (entry_inst & 0x20) | |
1684 | { | |
4c7d22cb | 1685 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1686 | offset -= mips_abi_regsize (current_gdbarch); |
1687 | } | |
1688 | ||
1689 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1690 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1691 | { | |
1692 | set_reg_offset (this_cache, reg, sp + offset); | |
1693 | offset -= mips_abi_regsize (current_gdbarch); | |
1694 | } | |
1695 | } | |
1696 | ||
1697 | if (this_cache != NULL) | |
1698 | { | |
1699 | this_cache->base = | |
f57d151a UW |
1700 | (frame_unwind_register_signed (next_frame, |
1701 | gdbarch_num_regs (current_gdbarch) | |
1702 | + frame_reg) | |
29639122 JB |
1703 | + frame_offset - frame_adjust); |
1704 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
1705 | be able to get rid of the assignment below, evetually. But it's | |
1706 | still needed for now. */ | |
f57d151a UW |
1707 | this_cache->saved_regs[gdbarch_num_regs (current_gdbarch) |
1708 | + mips_regnum (current_gdbarch)->pc] | |
1709 | = this_cache->saved_regs[gdbarch_num_regs (current_gdbarch) | |
1710 | + MIPS_RA_REGNUM]; | |
29639122 JB |
1711 | } |
1712 | ||
1713 | /* If we didn't reach the end of the prologue when scanning the function | |
1714 | instructions, then set end_prologue_addr to the address of the | |
1715 | instruction immediately after the last one we scanned. */ | |
1716 | if (end_prologue_addr == 0) | |
1717 | end_prologue_addr = cur_pc; | |
1718 | ||
1719 | return end_prologue_addr; | |
eec63939 AC |
1720 | } |
1721 | ||
29639122 JB |
1722 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1723 | Procedures that use the 32-bit instruction set are handled by the | |
1724 | mips_insn32 unwinder. */ | |
1725 | ||
1726 | static struct mips_frame_cache * | |
1727 | mips_insn16_frame_cache (struct frame_info *next_frame, void **this_cache) | |
eec63939 | 1728 | { |
29639122 | 1729 | struct mips_frame_cache *cache; |
eec63939 AC |
1730 | |
1731 | if ((*this_cache) != NULL) | |
1732 | return (*this_cache); | |
29639122 JB |
1733 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1734 | (*this_cache) = cache; | |
1735 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
eec63939 | 1736 | |
29639122 JB |
1737 | /* Analyze the function prologue. */ |
1738 | { | |
6de5b849 JB |
1739 | const CORE_ADDR pc = |
1740 | frame_unwind_address_in_block (next_frame, NORMAL_FRAME); | |
29639122 | 1741 | CORE_ADDR start_addr; |
eec63939 | 1742 | |
29639122 JB |
1743 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1744 | if (start_addr == 0) | |
1745 | start_addr = heuristic_proc_start (pc); | |
1746 | /* We can't analyze the prologue if we couldn't find the begining | |
1747 | of the function. */ | |
1748 | if (start_addr == 0) | |
1749 | return cache; | |
eec63939 | 1750 | |
29639122 JB |
1751 | mips16_scan_prologue (start_addr, pc, next_frame, *this_cache); |
1752 | } | |
1753 | ||
3e8c568d | 1754 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a UW |
1755 | trad_frame_set_value (cache->saved_regs, gdbarch_num_regs (current_gdbarch) |
1756 | + MIPS_SP_REGNUM, cache->base); | |
eec63939 | 1757 | |
29639122 | 1758 | return (*this_cache); |
eec63939 AC |
1759 | } |
1760 | ||
1761 | static void | |
29639122 JB |
1762 | mips_insn16_frame_this_id (struct frame_info *next_frame, void **this_cache, |
1763 | struct frame_id *this_id) | |
eec63939 | 1764 | { |
29639122 JB |
1765 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1766 | this_cache); | |
93d42b30 DJ |
1767 | (*this_id) = frame_id_build (info->base, |
1768 | frame_func_unwind (next_frame, NORMAL_FRAME)); | |
eec63939 AC |
1769 | } |
1770 | ||
1771 | static void | |
29639122 | 1772 | mips_insn16_frame_prev_register (struct frame_info *next_frame, |
eec63939 AC |
1773 | void **this_cache, |
1774 | int regnum, int *optimizedp, | |
1775 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 1776 | int *realnump, gdb_byte *valuep) |
eec63939 | 1777 | { |
29639122 JB |
1778 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1779 | this_cache); | |
1780 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
1781 | optimizedp, lvalp, addrp, realnump, valuep); | |
eec63939 AC |
1782 | } |
1783 | ||
29639122 | 1784 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
1785 | { |
1786 | NORMAL_FRAME, | |
29639122 JB |
1787 | mips_insn16_frame_this_id, |
1788 | mips_insn16_frame_prev_register | |
eec63939 AC |
1789 | }; |
1790 | ||
1791 | static const struct frame_unwind * | |
29639122 | 1792 | mips_insn16_frame_sniffer (struct frame_info *next_frame) |
eec63939 | 1793 | { |
6de5b849 | 1794 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
0fe7e7c8 | 1795 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
1796 | return &mips_insn16_frame_unwind; |
1797 | return NULL; | |
eec63939 AC |
1798 | } |
1799 | ||
1800 | static CORE_ADDR | |
29639122 JB |
1801 | mips_insn16_frame_base_address (struct frame_info *next_frame, |
1802 | void **this_cache) | |
eec63939 | 1803 | { |
29639122 JB |
1804 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1805 | this_cache); | |
1806 | return info->base; | |
eec63939 AC |
1807 | } |
1808 | ||
29639122 | 1809 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 1810 | { |
29639122 JB |
1811 | &mips_insn16_frame_unwind, |
1812 | mips_insn16_frame_base_address, | |
1813 | mips_insn16_frame_base_address, | |
1814 | mips_insn16_frame_base_address | |
eec63939 AC |
1815 | }; |
1816 | ||
1817 | static const struct frame_base * | |
29639122 | 1818 | mips_insn16_frame_base_sniffer (struct frame_info *next_frame) |
eec63939 | 1819 | { |
29639122 JB |
1820 | if (mips_insn16_frame_sniffer (next_frame) != NULL) |
1821 | return &mips_insn16_frame_base; | |
eec63939 AC |
1822 | else |
1823 | return NULL; | |
edfae063 AC |
1824 | } |
1825 | ||
29639122 JB |
1826 | /* Mark all the registers as unset in the saved_regs array |
1827 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
1828 | ||
1829 | void | |
1830 | reset_saved_regs (struct mips_frame_cache *this_cache) | |
c906108c | 1831 | { |
29639122 JB |
1832 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
1833 | return; | |
1834 | ||
1835 | { | |
f57d151a | 1836 | const int num_regs = gdbarch_num_regs (current_gdbarch); |
29639122 | 1837 | int i; |
64159455 | 1838 | |
29639122 JB |
1839 | for (i = 0; i < num_regs; i++) |
1840 | { | |
1841 | this_cache->saved_regs[i].addr = -1; | |
1842 | } | |
1843 | } | |
c906108c SS |
1844 | } |
1845 | ||
29639122 JB |
1846 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1847 | the associated FRAME_CACHE if not null. | |
1848 | Return the address of the first instruction past the prologue. */ | |
c906108c | 1849 | |
875e1767 | 1850 | static CORE_ADDR |
29639122 JB |
1851 | mips32_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1852 | struct frame_info *next_frame, | |
1853 | struct mips_frame_cache *this_cache) | |
c906108c | 1854 | { |
29639122 JB |
1855 | CORE_ADDR cur_pc; |
1856 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
1857 | CORE_ADDR sp; | |
1858 | long frame_offset; | |
1859 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 1860 | |
29639122 JB |
1861 | CORE_ADDR end_prologue_addr = 0; |
1862 | int seen_sp_adjust = 0; | |
1863 | int load_immediate_bytes = 0; | |
8fa9cfa1 | 1864 | |
29639122 JB |
1865 | /* Can be called when there's no process, and hence when there's no |
1866 | NEXT_FRAME. */ | |
1867 | if (next_frame != NULL) | |
d2ca4222 UW |
1868 | sp = frame_unwind_register_signed (next_frame, |
1869 | gdbarch_num_regs (current_gdbarch) | |
1870 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 1871 | else |
29639122 | 1872 | sp = 0; |
9022177c | 1873 | |
29639122 JB |
1874 | if (limit_pc > start_pc + 200) |
1875 | limit_pc = start_pc + 200; | |
9022177c | 1876 | |
29639122 | 1877 | restart: |
9022177c | 1878 | |
29639122 | 1879 | frame_offset = 0; |
95ac2dcf | 1880 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 1881 | { |
29639122 JB |
1882 | unsigned long inst, high_word, low_word; |
1883 | int reg; | |
9022177c | 1884 | |
29639122 JB |
1885 | /* Fetch the instruction. */ |
1886 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
9022177c | 1887 | |
29639122 JB |
1888 | /* Save some code by pre-extracting some useful fields. */ |
1889 | high_word = (inst >> 16) & 0xffff; | |
1890 | low_word = inst & 0xffff; | |
1891 | reg = high_word & 0x1f; | |
fe29b929 | 1892 | |
29639122 JB |
1893 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
1894 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
1895 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1896 | { | |
1897 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
1898 | frame_offset += 0x10000 - low_word; | |
1899 | else | |
1900 | /* Exit loop if a positive stack adjustment is found, which | |
1901 | usually means that the stack cleanup code in the function | |
1902 | epilogue is reached. */ | |
1903 | break; | |
1904 | seen_sp_adjust = 1; | |
1905 | } | |
1906 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
1907 | { | |
1908 | set_reg_offset (this_cache, reg, sp + low_word); | |
1909 | } | |
1910 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
1911 | { | |
1912 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
1913 | set_reg_offset (this_cache, reg, sp + low_word); | |
1914 | } | |
1915 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
1916 | { | |
1917 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
1918 | if ((long) low_word != frame_offset) | |
1919 | frame_addr = sp + low_word; | |
d2ca4222 | 1920 | else if (next_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
1921 | { |
1922 | unsigned alloca_adjust; | |
a4b8ebc8 | 1923 | |
29639122 | 1924 | frame_reg = 30; |
d2ca4222 UW |
1925 | frame_addr = frame_unwind_register_signed |
1926 | (next_frame, | |
1927 | gdbarch_num_regs (current_gdbarch) + 30); | |
1928 | ||
29639122 JB |
1929 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
1930 | if (alloca_adjust > 0) | |
1931 | { | |
1932 | /* FP > SP + frame_size. This may be because of | |
1933 | an alloca or somethings similar. Fix sp to | |
1934 | "pre-alloca" value, and try again. */ | |
1935 | sp += alloca_adjust; | |
1936 | /* Need to reset the status of all registers. Otherwise, | |
1937 | we will hit a guard that prevents the new address | |
1938 | for each register to be recomputed during the second | |
1939 | pass. */ | |
1940 | reset_saved_regs (this_cache); | |
1941 | goto restart; | |
1942 | } | |
1943 | } | |
1944 | } | |
1945 | /* move $30,$sp. With different versions of gas this will be either | |
1946 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
1947 | Accept any one of these. */ | |
1948 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
1949 | { | |
1950 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
d2ca4222 | 1951 | if (next_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
1952 | { |
1953 | unsigned alloca_adjust; | |
c906108c | 1954 | |
29639122 | 1955 | frame_reg = 30; |
d2ca4222 UW |
1956 | frame_addr = frame_unwind_register_signed |
1957 | (next_frame, | |
1958 | gdbarch_num_regs (current_gdbarch) + 30); | |
1959 | ||
29639122 JB |
1960 | alloca_adjust = (unsigned) (frame_addr - sp); |
1961 | if (alloca_adjust > 0) | |
1962 | { | |
1963 | /* FP > SP + frame_size. This may be because of | |
1964 | an alloca or somethings similar. Fix sp to | |
1965 | "pre-alloca" value, and try again. */ | |
1966 | sp = frame_addr; | |
1967 | /* Need to reset the status of all registers. Otherwise, | |
1968 | we will hit a guard that prevents the new address | |
1969 | for each register to be recomputed during the second | |
1970 | pass. */ | |
1971 | reset_saved_regs (this_cache); | |
1972 | goto restart; | |
1973 | } | |
1974 | } | |
1975 | } | |
1976 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ | |
1977 | { | |
1978 | set_reg_offset (this_cache, reg, frame_addr + low_word); | |
1979 | } | |
1980 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
1981 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
1982 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
1983 | || high_word == 0x3c1c /* lui $gp,n */ | |
1984 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
1985 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
1986 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
1987 | ) | |
1988 | { | |
1989 | /* These instructions are part of the prologue, but we don't | |
1990 | need to do anything special to handle them. */ | |
1991 | } | |
1992 | /* The instructions below load $at or $t0 with an immediate | |
1993 | value in preparation for a stack adjustment via | |
1994 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
1995 | initialize a local variable, so we accept them only before | |
1996 | a stack adjustment instruction was seen. */ | |
1997 | else if (!seen_sp_adjust | |
1998 | && (high_word == 0x3c01 /* lui $at,n */ | |
1999 | || high_word == 0x3c08 /* lui $t0,n */ | |
2000 | || high_word == 0x3421 /* ori $at,$at,n */ | |
2001 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
2002 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
2003 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
2004 | )) | |
2005 | { | |
95ac2dcf | 2006 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
29639122 JB |
2007 | } |
2008 | else | |
2009 | { | |
2010 | /* This instruction is not an instruction typically found | |
2011 | in a prologue, so we must have reached the end of the | |
2012 | prologue. */ | |
2013 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
2014 | loop now? Why would we need to continue scanning the function | |
2015 | instructions? */ | |
2016 | if (end_prologue_addr == 0) | |
2017 | end_prologue_addr = cur_pc; | |
2018 | } | |
a4b8ebc8 | 2019 | } |
c906108c | 2020 | |
29639122 JB |
2021 | if (this_cache != NULL) |
2022 | { | |
2023 | this_cache->base = | |
f57d151a UW |
2024 | (frame_unwind_register_signed (next_frame, |
2025 | gdbarch_num_regs (current_gdbarch) | |
2026 | + frame_reg) | |
29639122 JB |
2027 | + frame_offset); |
2028 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2029 | this assignment below, eventually. But it's still needed | |
2030 | for now. */ | |
f57d151a UW |
2031 | this_cache->saved_regs[gdbarch_num_regs (current_gdbarch) |
2032 | + mips_regnum (current_gdbarch)->pc] | |
2033 | = this_cache->saved_regs[gdbarch_num_regs (current_gdbarch) | |
2034 | + MIPS_RA_REGNUM]; | |
29639122 | 2035 | } |
c906108c | 2036 | |
29639122 JB |
2037 | /* If we didn't reach the end of the prologue when scanning the function |
2038 | instructions, then set end_prologue_addr to the address of the | |
2039 | instruction immediately after the last one we scanned. */ | |
2040 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2041 | we may as well be careful and do our best if we have a null | |
2042 | end_prologue_addr. */ | |
2043 | if (end_prologue_addr == 0) | |
2044 | end_prologue_addr = cur_pc; | |
2045 | ||
2046 | /* In a frameless function, we might have incorrectly | |
2047 | skipped some load immediate instructions. Undo the skipping | |
2048 | if the load immediate was not followed by a stack adjustment. */ | |
2049 | if (load_immediate_bytes && !seen_sp_adjust) | |
2050 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2051 | |
29639122 | 2052 | return end_prologue_addr; |
c906108c SS |
2053 | } |
2054 | ||
29639122 JB |
2055 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2056 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2057 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2058 | unwinder. */ | |
c906108c | 2059 | |
29639122 JB |
2060 | static struct mips_frame_cache * |
2061 | mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache) | |
c906108c | 2062 | { |
29639122 | 2063 | struct mips_frame_cache *cache; |
c906108c | 2064 | |
29639122 JB |
2065 | if ((*this_cache) != NULL) |
2066 | return (*this_cache); | |
c5aa993b | 2067 | |
29639122 JB |
2068 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2069 | (*this_cache) = cache; | |
2070 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
c5aa993b | 2071 | |
29639122 JB |
2072 | /* Analyze the function prologue. */ |
2073 | { | |
6de5b849 JB |
2074 | const CORE_ADDR pc = |
2075 | frame_unwind_address_in_block (next_frame, NORMAL_FRAME); | |
29639122 | 2076 | CORE_ADDR start_addr; |
c906108c | 2077 | |
29639122 JB |
2078 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2079 | if (start_addr == 0) | |
2080 | start_addr = heuristic_proc_start (pc); | |
2081 | /* We can't analyze the prologue if we couldn't find the begining | |
2082 | of the function. */ | |
2083 | if (start_addr == 0) | |
2084 | return cache; | |
c5aa993b | 2085 | |
29639122 JB |
2086 | mips32_scan_prologue (start_addr, pc, next_frame, *this_cache); |
2087 | } | |
2088 | ||
3e8c568d | 2089 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a UW |
2090 | trad_frame_set_value (cache->saved_regs, |
2091 | gdbarch_num_regs (current_gdbarch) + MIPS_SP_REGNUM, | |
2092 | cache->base); | |
c5aa993b | 2093 | |
29639122 | 2094 | return (*this_cache); |
c906108c SS |
2095 | } |
2096 | ||
29639122 JB |
2097 | static void |
2098 | mips_insn32_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2099 | struct frame_id *this_id) | |
c906108c | 2100 | { |
29639122 JB |
2101 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
2102 | this_cache); | |
93d42b30 DJ |
2103 | (*this_id) = frame_id_build (info->base, |
2104 | frame_func_unwind (next_frame, NORMAL_FRAME)); | |
29639122 | 2105 | } |
c906108c | 2106 | |
29639122 JB |
2107 | static void |
2108 | mips_insn32_frame_prev_register (struct frame_info *next_frame, | |
2109 | void **this_cache, | |
2110 | int regnum, int *optimizedp, | |
2111 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 2112 | int *realnump, gdb_byte *valuep) |
29639122 JB |
2113 | { |
2114 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, | |
2115 | this_cache); | |
2116 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
2117 | optimizedp, lvalp, addrp, realnump, valuep); | |
c906108c SS |
2118 | } |
2119 | ||
29639122 JB |
2120 | static const struct frame_unwind mips_insn32_frame_unwind = |
2121 | { | |
2122 | NORMAL_FRAME, | |
2123 | mips_insn32_frame_this_id, | |
2124 | mips_insn32_frame_prev_register | |
2125 | }; | |
c906108c | 2126 | |
29639122 JB |
2127 | static const struct frame_unwind * |
2128 | mips_insn32_frame_sniffer (struct frame_info *next_frame) | |
2129 | { | |
6de5b849 | 2130 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
0fe7e7c8 | 2131 | if (! mips_pc_is_mips16 (pc)) |
29639122 JB |
2132 | return &mips_insn32_frame_unwind; |
2133 | return NULL; | |
2134 | } | |
c906108c | 2135 | |
1c645fec | 2136 | static CORE_ADDR |
29639122 JB |
2137 | mips_insn32_frame_base_address (struct frame_info *next_frame, |
2138 | void **this_cache) | |
c906108c | 2139 | { |
29639122 JB |
2140 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
2141 | this_cache); | |
2142 | return info->base; | |
2143 | } | |
c906108c | 2144 | |
29639122 JB |
2145 | static const struct frame_base mips_insn32_frame_base = |
2146 | { | |
2147 | &mips_insn32_frame_unwind, | |
2148 | mips_insn32_frame_base_address, | |
2149 | mips_insn32_frame_base_address, | |
2150 | mips_insn32_frame_base_address | |
2151 | }; | |
1c645fec | 2152 | |
29639122 JB |
2153 | static const struct frame_base * |
2154 | mips_insn32_frame_base_sniffer (struct frame_info *next_frame) | |
2155 | { | |
2156 | if (mips_insn32_frame_sniffer (next_frame) != NULL) | |
2157 | return &mips_insn32_frame_base; | |
a65bbe44 | 2158 | else |
29639122 JB |
2159 | return NULL; |
2160 | } | |
a65bbe44 | 2161 | |
29639122 JB |
2162 | static struct trad_frame_cache * |
2163 | mips_stub_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2164 | { | |
2165 | CORE_ADDR pc; | |
2166 | CORE_ADDR start_addr; | |
2167 | CORE_ADDR stack_addr; | |
2168 | struct trad_frame_cache *this_trad_cache; | |
c906108c | 2169 | |
29639122 JB |
2170 | if ((*this_cache) != NULL) |
2171 | return (*this_cache); | |
2172 | this_trad_cache = trad_frame_cache_zalloc (next_frame); | |
2173 | (*this_cache) = this_trad_cache; | |
1c645fec | 2174 | |
29639122 | 2175 | /* The return address is in the link register. */ |
3e8c568d UW |
2176 | trad_frame_set_reg_realreg (this_trad_cache, |
2177 | gdbarch_pc_regnum (current_gdbarch), | |
2178 | MIPS_RA_REGNUM); | |
1c645fec | 2179 | |
29639122 JB |
2180 | /* Frame ID, since it's a frameless / stackless function, no stack |
2181 | space is allocated and SP on entry is the current SP. */ | |
2182 | pc = frame_pc_unwind (next_frame); | |
2183 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
4c7d22cb | 2184 | stack_addr = frame_unwind_register_signed (next_frame, MIPS_SP_REGNUM); |
29639122 | 2185 | trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr)); |
1c645fec | 2186 | |
29639122 JB |
2187 | /* Assume that the frame's base is the same as the |
2188 | stack-pointer. */ | |
2189 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2190 | |
29639122 JB |
2191 | return this_trad_cache; |
2192 | } | |
c906108c | 2193 | |
29639122 JB |
2194 | static void |
2195 | mips_stub_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2196 | struct frame_id *this_id) | |
2197 | { | |
2198 | struct trad_frame_cache *this_trad_cache | |
2199 | = mips_stub_frame_cache (next_frame, this_cache); | |
2200 | trad_frame_get_id (this_trad_cache, this_id); | |
2201 | } | |
c906108c | 2202 | |
29639122 JB |
2203 | static void |
2204 | mips_stub_frame_prev_register (struct frame_info *next_frame, | |
2205 | void **this_cache, | |
2206 | int regnum, int *optimizedp, | |
2207 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 2208 | int *realnump, gdb_byte *valuep) |
29639122 JB |
2209 | { |
2210 | struct trad_frame_cache *this_trad_cache | |
2211 | = mips_stub_frame_cache (next_frame, this_cache); | |
2212 | trad_frame_get_register (this_trad_cache, next_frame, regnum, optimizedp, | |
2213 | lvalp, addrp, realnump, valuep); | |
2214 | } | |
c906108c | 2215 | |
29639122 JB |
2216 | static const struct frame_unwind mips_stub_frame_unwind = |
2217 | { | |
2218 | NORMAL_FRAME, | |
2219 | mips_stub_frame_this_id, | |
2220 | mips_stub_frame_prev_register | |
2221 | }; | |
c906108c | 2222 | |
29639122 JB |
2223 | static const struct frame_unwind * |
2224 | mips_stub_frame_sniffer (struct frame_info *next_frame) | |
2225 | { | |
979b38e0 | 2226 | struct obj_section *s; |
93d42b30 | 2227 | CORE_ADDR pc = frame_unwind_address_in_block (next_frame, NORMAL_FRAME); |
979b38e0 | 2228 | |
29639122 JB |
2229 | if (in_plt_section (pc, NULL)) |
2230 | return &mips_stub_frame_unwind; | |
979b38e0 DJ |
2231 | |
2232 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2233 | s = find_pc_section (pc); | |
2234 | ||
2235 | if (s != NULL | |
2236 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2237 | ".MIPS.stubs") == 0) | |
2238 | return &mips_stub_frame_unwind; | |
2239 | ||
2240 | return NULL; | |
29639122 | 2241 | } |
c906108c | 2242 | |
29639122 JB |
2243 | static CORE_ADDR |
2244 | mips_stub_frame_base_address (struct frame_info *next_frame, | |
2245 | void **this_cache) | |
2246 | { | |
2247 | struct trad_frame_cache *this_trad_cache | |
2248 | = mips_stub_frame_cache (next_frame, this_cache); | |
2249 | return trad_frame_get_this_base (this_trad_cache); | |
2250 | } | |
0fce0821 | 2251 | |
29639122 JB |
2252 | static const struct frame_base mips_stub_frame_base = |
2253 | { | |
2254 | &mips_stub_frame_unwind, | |
2255 | mips_stub_frame_base_address, | |
2256 | mips_stub_frame_base_address, | |
2257 | mips_stub_frame_base_address | |
2258 | }; | |
2259 | ||
2260 | static const struct frame_base * | |
2261 | mips_stub_frame_base_sniffer (struct frame_info *next_frame) | |
2262 | { | |
2263 | if (mips_stub_frame_sniffer (next_frame) != NULL) | |
2264 | return &mips_stub_frame_base; | |
2265 | else | |
2266 | return NULL; | |
2267 | } | |
2268 | ||
29639122 | 2269 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2270 | |
29639122 JB |
2271 | static CORE_ADDR |
2272 | mips_addr_bits_remove (CORE_ADDR addr) | |
65596487 | 2273 | { |
29639122 JB |
2274 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2275 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) | |
2276 | /* This hack is a work-around for existing boards using PMON, the | |
2277 | simulator, and any other 64-bit targets that doesn't have true | |
2278 | 64-bit addressing. On these targets, the upper 32 bits of | |
2279 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2280 | likely to have been sign extended to all 1s by instruction | |
2281 | sequences that load 32-bit addresses. For example, a typical | |
2282 | piece of code that loads an address is this: | |
65596487 | 2283 | |
29639122 JB |
2284 | lui $r2, <upper 16 bits> |
2285 | ori $r2, <lower 16 bits> | |
65596487 | 2286 | |
29639122 JB |
2287 | But the lui sign-extends the value such that the upper 32 bits |
2288 | may be all 1s. The workaround is simply to mask off these | |
2289 | bits. In the future, gcc may be changed to support true 64-bit | |
2290 | addressing, and this masking will have to be disabled. */ | |
2291 | return addr &= 0xffffffffUL; | |
2292 | else | |
2293 | return addr; | |
65596487 JB |
2294 | } |
2295 | ||
29639122 JB |
2296 | /* mips_software_single_step() is called just before we want to resume |
2297 | the inferior, if we want to single-step it but there is no hardware | |
2298 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 2299 | the target of the coming instruction and breakpoint it. */ |
29639122 | 2300 | |
e6590a1b | 2301 | int |
0b1b3e42 | 2302 | mips_software_single_step (struct frame_info *frame) |
c906108c | 2303 | { |
8181d85f | 2304 | CORE_ADDR pc, next_pc; |
65596487 | 2305 | |
0b1b3e42 UW |
2306 | pc = get_frame_pc (frame); |
2307 | next_pc = mips_next_pc (frame, pc); | |
e6590a1b | 2308 | |
e0cd558a | 2309 | insert_single_step_breakpoint (next_pc); |
e6590a1b | 2310 | return 1; |
29639122 | 2311 | } |
a65bbe44 | 2312 | |
29639122 JB |
2313 | /* Test whether the PC points to the return instruction at the |
2314 | end of a function. */ | |
65596487 | 2315 | |
29639122 JB |
2316 | static int |
2317 | mips_about_to_return (CORE_ADDR pc) | |
2318 | { | |
0fe7e7c8 | 2319 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2320 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2321 | generates a "jr $ra"; other times it generates code to load | |
2322 | the return address from the stack to an accessible register (such | |
2323 | as $a3), then a "jr" using that register. This second case | |
2324 | is almost impossible to distinguish from an indirect jump | |
2325 | used for switch statements, so we don't even try. */ | |
2326 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
2327 | else | |
2328 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
2329 | } | |
c906108c | 2330 | |
c906108c | 2331 | |
29639122 JB |
2332 | /* This fencepost looks highly suspicious to me. Removing it also |
2333 | seems suspicious as it could affect remote debugging across serial | |
2334 | lines. */ | |
c906108c | 2335 | |
29639122 JB |
2336 | static CORE_ADDR |
2337 | heuristic_proc_start (CORE_ADDR pc) | |
2338 | { | |
2339 | CORE_ADDR start_pc; | |
2340 | CORE_ADDR fence; | |
2341 | int instlen; | |
2342 | int seen_adjsp = 0; | |
65596487 | 2343 | |
bf6ae464 | 2344 | pc = gdbarch_addr_bits_remove (current_gdbarch, pc); |
29639122 JB |
2345 | start_pc = pc; |
2346 | fence = start_pc - heuristic_fence_post; | |
2347 | if (start_pc == 0) | |
2348 | return 0; | |
65596487 | 2349 | |
29639122 JB |
2350 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2351 | fence = VM_MIN_ADDRESS; | |
65596487 | 2352 | |
95ac2dcf | 2353 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2354 | |
29639122 JB |
2355 | /* search back for previous return */ |
2356 | for (start_pc -= instlen;; start_pc -= instlen) | |
2357 | if (start_pc < fence) | |
2358 | { | |
2359 | /* It's not clear to me why we reach this point when | |
2360 | stop_soon, but with this test, at least we | |
2361 | don't print out warnings for every child forked (eg, on | |
2362 | decstation). 22apr93 rich@cygnus.com. */ | |
2363 | if (stop_soon == NO_STOP_QUIETLY) | |
2364 | { | |
2365 | static int blurb_printed = 0; | |
98b4dd94 | 2366 | |
8a3fe4f8 | 2367 | warning (_("GDB can't find the start of the function at 0x%s."), |
29639122 JB |
2368 | paddr_nz (pc)); |
2369 | ||
2370 | if (!blurb_printed) | |
2371 | { | |
2372 | /* This actually happens frequently in embedded | |
2373 | development, when you first connect to a board | |
2374 | and your stack pointer and pc are nowhere in | |
2375 | particular. This message needs to give people | |
2376 | in that situation enough information to | |
2377 | determine that it's no big deal. */ | |
2378 | printf_filtered ("\n\ | |
2379 | GDB is unable to find the start of the function at 0x%s\n\ | |
2380 | and thus can't determine the size of that function's stack frame.\n\ | |
2381 | This means that GDB may be unable to access that stack frame, or\n\ | |
2382 | the frames below it.\n\ | |
2383 | This problem is most likely caused by an invalid program counter or\n\ | |
2384 | stack pointer.\n\ | |
2385 | However, if you think GDB should simply search farther back\n\ | |
2386 | from 0x%s for code which looks like the beginning of a\n\ | |
2387 | function, you can increase the range of the search using the `set\n\ | |
2388 | heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); | |
2389 | blurb_printed = 1; | |
2390 | } | |
2391 | } | |
2392 | ||
2393 | return 0; | |
2394 | } | |
0fe7e7c8 | 2395 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2396 | { |
2397 | unsigned short inst; | |
2398 | ||
2399 | /* On MIPS16, any one of the following is likely to be the | |
2400 | start of a function: | |
2401 | entry | |
2402 | addiu sp,-n | |
2403 | daddiu sp,-n | |
2404 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
2405 | inst = mips_fetch_instruction (start_pc); | |
2406 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
2407 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2408 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2409 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
2410 | break; | |
2411 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2412 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2413 | seen_adjsp = 1; | |
2414 | else | |
2415 | seen_adjsp = 0; | |
2416 | } | |
2417 | else if (mips_about_to_return (start_pc)) | |
2418 | { | |
4c7d22cb | 2419 | /* Skip return and its delay slot. */ |
95ac2dcf | 2420 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2421 | break; |
2422 | } | |
2423 | ||
2424 | return start_pc; | |
c906108c SS |
2425 | } |
2426 | ||
6c0d6680 DJ |
2427 | struct mips_objfile_private |
2428 | { | |
2429 | bfd_size_type size; | |
2430 | char *contents; | |
2431 | }; | |
2432 | ||
f09ded24 AC |
2433 | /* According to the current ABI, should the type be passed in a |
2434 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 2435 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 AC |
2436 | FP registers and, consequently this returns false - forces FP |
2437 | arguments into integer registers. */ | |
2438 | ||
2439 | static int | |
2440 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2441 | { | |
2442 | return ((typecode == TYPE_CODE_FLT | |
2443 | || (MIPS_EABI | |
6d82d43b AC |
2444 | && (typecode == TYPE_CODE_STRUCT |
2445 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 2446 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
2447 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
2448 | == TYPE_CODE_FLT)) | |
c86b5b38 | 2449 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2450 | } |
2451 | ||
49e790b0 DJ |
2452 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2453 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2454 | ||
2455 | static int | |
2456 | mips_type_needs_double_align (struct type *type) | |
2457 | { | |
2458 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2459 | |
49e790b0 DJ |
2460 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2461 | return 1; | |
2462 | else if (typecode == TYPE_CODE_STRUCT) | |
2463 | { | |
2464 | if (TYPE_NFIELDS (type) < 1) | |
2465 | return 0; | |
2466 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2467 | } | |
2468 | else if (typecode == TYPE_CODE_UNION) | |
2469 | { | |
361d1df0 | 2470 | int i, n; |
49e790b0 DJ |
2471 | |
2472 | n = TYPE_NFIELDS (type); | |
2473 | for (i = 0; i < n; i++) | |
2474 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2475 | return 1; | |
2476 | return 0; | |
2477 | } | |
2478 | return 0; | |
2479 | } | |
2480 | ||
dc604539 AC |
2481 | /* Adjust the address downward (direction of stack growth) so that it |
2482 | is correctly aligned for a new stack frame. */ | |
2483 | static CORE_ADDR | |
2484 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2485 | { | |
5b03f266 | 2486 | return align_down (addr, 16); |
dc604539 AC |
2487 | } |
2488 | ||
f7ab6ec6 | 2489 | static CORE_ADDR |
7d9b040b | 2490 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2491 | struct regcache *regcache, CORE_ADDR bp_addr, |
2492 | int nargs, struct value **args, CORE_ADDR sp, | |
2493 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2494 | { |
2495 | int argreg; | |
2496 | int float_argreg; | |
2497 | int argnum; | |
2498 | int len = 0; | |
2499 | int stack_offset = 0; | |
480d3dd2 | 2500 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2501 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 2502 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 2503 | |
25ab4790 AC |
2504 | /* For shared libraries, "t9" needs to point at the function |
2505 | address. */ | |
4c7d22cb | 2506 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2507 | |
2508 | /* Set the return address register to point to the entry point of | |
2509 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2510 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2511 | |
c906108c | 2512 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2513 | are properly aligned. The stack has to be at least 64-bit |
2514 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2515 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2516 | aligned, so we round to this widest known alignment. */ | |
2517 | ||
5b03f266 AC |
2518 | sp = align_down (sp, 16); |
2519 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2520 | |
46e0f506 | 2521 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2522 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2523 | passed in registers, but that's OK. */ |
c906108c | 2524 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 2525 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 2526 | sp -= align_up (len, 16); |
c906108c | 2527 | |
9ace0497 | 2528 | if (mips_debug) |
6d82d43b | 2529 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2530 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2531 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2532 | |
c906108c | 2533 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2534 | argreg = MIPS_A0_REGNUM; |
56cea623 | 2535 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 2536 | |
46e0f506 | 2537 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2538 | if (struct_return) |
9ace0497 AC |
2539 | { |
2540 | if (mips_debug) | |
2541 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2542 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2543 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 2544 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 2545 | } |
c906108c SS |
2546 | |
2547 | /* Now load as many as possible of the first arguments into | |
2548 | registers, and push the rest onto the stack. Loop thru args | |
2549 | from first to last. */ | |
2550 | for (argnum = 0; argnum < nargs; argnum++) | |
2551 | { | |
47a35522 MK |
2552 | const gdb_byte *val; |
2553 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 2554 | struct value *arg = args[argnum]; |
4991999e | 2555 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
2556 | int len = TYPE_LENGTH (arg_type); |
2557 | enum type_code typecode = TYPE_CODE (arg_type); | |
2558 | ||
9ace0497 AC |
2559 | if (mips_debug) |
2560 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2561 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2562 | argnum + 1, len, (int) typecode); |
9ace0497 | 2563 | |
c906108c | 2564 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2565 | reference. */ |
1a69e1e4 | 2566 | if (len > regsize |
9ace0497 | 2567 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2568 | { |
1a69e1e4 | 2569 | store_unsigned_integer (valbuf, regsize, VALUE_ADDRESS (arg)); |
c906108c | 2570 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 2571 | len = regsize; |
c906108c | 2572 | val = valbuf; |
9ace0497 AC |
2573 | if (mips_debug) |
2574 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2575 | } |
2576 | else | |
47a35522 | 2577 | val = value_contents (arg); |
c906108c SS |
2578 | |
2579 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2580 | even-numbered floating point register. Round the FP register |
2581 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2582 | left. Non MIPS_EABI targets also pass the FP in the integer |
2583 | registers so also round up normal registers. */ | |
1a69e1e4 | 2584 | if (regsize < 8 && fp_register_arg_p (typecode, arg_type)) |
acdb74a0 AC |
2585 | { |
2586 | if ((float_argreg & 1)) | |
2587 | float_argreg++; | |
2588 | } | |
c906108c SS |
2589 | |
2590 | /* Floating point arguments passed in registers have to be | |
2591 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2592 | are passed in register pairs; the even register gets |
2593 | the low word, and the odd register gets the high word. | |
2594 | On non-EABI processors, the first two floating point arguments are | |
2595 | also copied to general registers, because MIPS16 functions | |
2596 | don't use float registers for arguments. This duplication of | |
2597 | arguments in general registers can't hurt non-MIPS16 functions | |
2598 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2599 | /* MIPS_EABI squeezes a struct that contains a single floating |
2600 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2601 | stack. */ |
f09ded24 AC |
2602 | if (fp_register_arg_p (typecode, arg_type) |
2603 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c | 2604 | { |
6da397e0 KB |
2605 | /* EABI32 will pass doubles in consecutive registers, even on |
2606 | 64-bit cores. At one time, we used to check the size of | |
2607 | `float_argreg' to determine whether or not to pass doubles | |
2608 | in consecutive registers, but this is not sufficient for | |
2609 | making the ABI determination. */ | |
2610 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 2611 | { |
4c6b5505 UW |
2612 | int low_offset = gdbarch_byte_order (current_gdbarch) |
2613 | == BFD_ENDIAN_BIG ? 4 : 0; | |
c906108c SS |
2614 | unsigned long regval; |
2615 | ||
2616 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2617 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2618 | if (mips_debug) |
acdb74a0 | 2619 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2620 | float_argreg, phex (regval, 4)); |
9c9acae0 | 2621 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2622 | |
2623 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2624 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2625 | if (mips_debug) |
acdb74a0 | 2626 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2627 | float_argreg, phex (regval, 4)); |
9c9acae0 | 2628 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2629 | } |
2630 | else | |
2631 | { | |
2632 | /* This is a floating point value that fits entirely | |
2633 | in a single register. */ | |
53a5351d | 2634 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 2635 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2636 | LONGEST regval = extract_unsigned_integer (val, len); |
2637 | if (mips_debug) | |
acdb74a0 | 2638 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2639 | float_argreg, phex (regval, len)); |
9c9acae0 | 2640 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2641 | } |
2642 | } | |
2643 | else | |
2644 | { | |
2645 | /* Copy the argument to general registers or the stack in | |
2646 | register-sized pieces. Large arguments are split between | |
2647 | registers and stack. */ | |
1a69e1e4 DJ |
2648 | /* Note: structs whose size is not a multiple of regsize |
2649 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
2650 | them in registers where gcc sometimes puts them on the |
2651 | stack. For maximum compatibility, we will put them in | |
2652 | both places. */ | |
1a69e1e4 | 2653 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 2654 | |
f09ded24 | 2655 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2656 | register are only written to memory. */ |
c906108c SS |
2657 | while (len > 0) |
2658 | { | |
ebafbe83 | 2659 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2660 | int stack_used_p = 0; |
1a69e1e4 | 2661 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 2662 | |
acdb74a0 AC |
2663 | if (mips_debug) |
2664 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2665 | partial_len); | |
2666 | ||
566f0f7a | 2667 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2668 | if (argreg > MIPS_LAST_ARG_REGNUM |
2669 | || odd_sized_struct | |
2670 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2671 | { |
c906108c SS |
2672 | /* Should shorter than int integer values be |
2673 | promoted to int before being stored? */ | |
c906108c | 2674 | int longword_offset = 0; |
9ace0497 | 2675 | CORE_ADDR addr; |
566f0f7a | 2676 | stack_used_p = 1; |
4c6b5505 | 2677 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 2678 | { |
1a69e1e4 | 2679 | if (regsize == 8 |
480d3dd2 AC |
2680 | && (typecode == TYPE_CODE_INT |
2681 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 2682 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 2683 | longword_offset = regsize - len; |
480d3dd2 AC |
2684 | else if ((typecode == TYPE_CODE_STRUCT |
2685 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
2686 | && TYPE_LENGTH (arg_type) < regsize) |
2687 | longword_offset = regsize - len; | |
7a292a7a | 2688 | } |
c5aa993b | 2689 | |
9ace0497 AC |
2690 | if (mips_debug) |
2691 | { | |
cb3d25d1 MS |
2692 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2693 | paddr_nz (stack_offset)); | |
2694 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2695 | paddr_nz (longword_offset)); | |
9ace0497 | 2696 | } |
361d1df0 | 2697 | |
9ace0497 AC |
2698 | addr = sp + stack_offset + longword_offset; |
2699 | ||
2700 | if (mips_debug) | |
2701 | { | |
2702 | int i; | |
6d82d43b | 2703 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 | 2704 | paddr_nz (addr)); |
9ace0497 AC |
2705 | for (i = 0; i < partial_len; i++) |
2706 | { | |
6d82d43b | 2707 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 2708 | val[i] & 0xff); |
9ace0497 AC |
2709 | } |
2710 | } | |
2711 | write_memory (addr, val, partial_len); | |
c906108c SS |
2712 | } |
2713 | ||
f09ded24 AC |
2714 | /* Note!!! This is NOT an else clause. Odd sized |
2715 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2716 | arguments will not. */ |
566f0f7a | 2717 | /* Write this portion of the argument to a general |
6d82d43b | 2718 | purpose register. */ |
f09ded24 AC |
2719 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2720 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2721 | { |
6d82d43b AC |
2722 | LONGEST regval = |
2723 | extract_unsigned_integer (val, partial_len); | |
c906108c | 2724 | |
9ace0497 | 2725 | if (mips_debug) |
acdb74a0 | 2726 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 2727 | argreg, |
1a69e1e4 | 2728 | phex (regval, regsize)); |
9c9acae0 | 2729 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
c906108c | 2730 | argreg++; |
c906108c | 2731 | } |
c5aa993b | 2732 | |
c906108c SS |
2733 | len -= partial_len; |
2734 | val += partial_len; | |
2735 | ||
566f0f7a | 2736 | /* Compute the the offset into the stack at which we |
6d82d43b | 2737 | will copy the next parameter. |
566f0f7a | 2738 | |
566f0f7a | 2739 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2740 | only needs to be adjusted when it has been used. */ |
c906108c | 2741 | |
46e0f506 | 2742 | if (stack_used_p) |
1a69e1e4 | 2743 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
2744 | } |
2745 | } | |
9ace0497 AC |
2746 | if (mips_debug) |
2747 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2748 | } |
2749 | ||
f10683bb | 2750 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 2751 | |
0f71a2f6 JM |
2752 | /* Return adjusted stack pointer. */ |
2753 | return sp; | |
2754 | } | |
2755 | ||
a1f5b845 | 2756 | /* Determine the return value convention being used. */ |
6d82d43b | 2757 | |
9c8fdbfa AC |
2758 | static enum return_value_convention |
2759 | mips_eabi_return_value (struct gdbarch *gdbarch, | |
2760 | struct type *type, struct regcache *regcache, | |
47a35522 | 2761 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 2762 | { |
9c8fdbfa AC |
2763 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
2764 | return RETURN_VALUE_STRUCT_CONVENTION; | |
2765 | if (readbuf) | |
2766 | memset (readbuf, 0, TYPE_LENGTH (type)); | |
2767 | return RETURN_VALUE_REGISTER_CONVENTION; | |
6d82d43b AC |
2768 | } |
2769 | ||
6d82d43b AC |
2770 | |
2771 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 2772 | |
f7ab6ec6 | 2773 | static CORE_ADDR |
7d9b040b | 2774 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2775 | struct regcache *regcache, CORE_ADDR bp_addr, |
2776 | int nargs, struct value **args, CORE_ADDR sp, | |
2777 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
2778 | { |
2779 | int argreg; | |
2780 | int float_argreg; | |
2781 | int argnum; | |
2782 | int len = 0; | |
2783 | int stack_offset = 0; | |
480d3dd2 | 2784 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2785 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 2786 | |
25ab4790 AC |
2787 | /* For shared libraries, "t9" needs to point at the function |
2788 | address. */ | |
4c7d22cb | 2789 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2790 | |
2791 | /* Set the return address register to point to the entry point of | |
2792 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2793 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2794 | |
cb3d25d1 MS |
2795 | /* First ensure that the stack and structure return address (if any) |
2796 | are properly aligned. The stack has to be at least 64-bit | |
2797 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2798 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2799 | aligned, so we round to this widest known alignment. */ | |
2800 | ||
5b03f266 AC |
2801 | sp = align_down (sp, 16); |
2802 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
2803 | |
2804 | /* Now make space on the stack for the args. */ | |
2805 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 2806 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 2807 | sp -= align_up (len, 16); |
cb3d25d1 MS |
2808 | |
2809 | if (mips_debug) | |
6d82d43b | 2810 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2811 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
2812 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
2813 | |
2814 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 2815 | argreg = MIPS_A0_REGNUM; |
56cea623 | 2816 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 2817 | |
46e0f506 | 2818 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
2819 | if (struct_return) |
2820 | { | |
2821 | if (mips_debug) | |
2822 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2823 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2824 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 2825 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
2826 | } |
2827 | ||
2828 | /* Now load as many as possible of the first arguments into | |
2829 | registers, and push the rest onto the stack. Loop thru args | |
2830 | from first to last. */ | |
2831 | for (argnum = 0; argnum < nargs; argnum++) | |
2832 | { | |
47a35522 | 2833 | const gdb_byte *val; |
cb3d25d1 | 2834 | struct value *arg = args[argnum]; |
4991999e | 2835 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
2836 | int len = TYPE_LENGTH (arg_type); |
2837 | enum type_code typecode = TYPE_CODE (arg_type); | |
2838 | ||
2839 | if (mips_debug) | |
2840 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2841 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
2842 | argnum + 1, len, (int) typecode); |
2843 | ||
47a35522 | 2844 | val = value_contents (arg); |
cb3d25d1 MS |
2845 | |
2846 | if (fp_register_arg_p (typecode, arg_type) | |
2847 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
2848 | { | |
2849 | /* This is a floating point value that fits entirely | |
2850 | in a single register. */ | |
2851 | /* On 32 bit ABI's the float_argreg is further adjusted | |
2852 | above to ensure that it is even register aligned. */ | |
2853 | LONGEST regval = extract_unsigned_integer (val, len); | |
2854 | if (mips_debug) | |
2855 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
2856 | float_argreg, phex (regval, len)); | |
9c9acae0 | 2857 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
cb3d25d1 MS |
2858 | |
2859 | if (mips_debug) | |
2860 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
2861 | argreg, phex (regval, len)); | |
9c9acae0 | 2862 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
cb3d25d1 MS |
2863 | argreg += 1; |
2864 | } | |
2865 | else | |
2866 | { | |
2867 | /* Copy the argument to general registers or the stack in | |
2868 | register-sized pieces. Large arguments are split between | |
2869 | registers and stack. */ | |
1a69e1e4 | 2870 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
2871 | are treated specially: Irix cc passes them in registers |
2872 | where gcc sometimes puts them on the stack. For maximum | |
2873 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
2874 | int odd_sized_struct = (len > MIPS64_REGSIZE |
2875 | && len % MIPS64_REGSIZE != 0); | |
cb3d25d1 | 2876 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2877 | register are only written to memory. */ |
cb3d25d1 MS |
2878 | while (len > 0) |
2879 | { | |
ad018eee | 2880 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 2881 | int stack_used_p = 0; |
1a69e1e4 | 2882 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
2883 | |
2884 | if (mips_debug) | |
2885 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2886 | partial_len); | |
2887 | ||
2888 | /* Write this portion of the argument to the stack. */ | |
2889 | if (argreg > MIPS_LAST_ARG_REGNUM | |
2890 | || odd_sized_struct | |
2891 | || fp_register_arg_p (typecode, arg_type)) | |
2892 | { | |
2893 | /* Should shorter than int integer values be | |
2894 | promoted to int before being stored? */ | |
2895 | int longword_offset = 0; | |
2896 | CORE_ADDR addr; | |
2897 | stack_used_p = 1; | |
4c6b5505 | 2898 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 2899 | { |
1a69e1e4 DJ |
2900 | if ((typecode == TYPE_CODE_INT |
2901 | || typecode == TYPE_CODE_PTR | |
2902 | || typecode == TYPE_CODE_FLT) | |
2903 | && len <= 4) | |
2904 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
2905 | } |
2906 | ||
2907 | if (mips_debug) | |
2908 | { | |
2909 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
2910 | paddr_nz (stack_offset)); | |
2911 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2912 | paddr_nz (longword_offset)); | |
2913 | } | |
2914 | ||
2915 | addr = sp + stack_offset + longword_offset; | |
2916 | ||
2917 | if (mips_debug) | |
2918 | { | |
2919 | int i; | |
6d82d43b | 2920 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 MS |
2921 | paddr_nz (addr)); |
2922 | for (i = 0; i < partial_len; i++) | |
2923 | { | |
6d82d43b | 2924 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
2925 | val[i] & 0xff); |
2926 | } | |
2927 | } | |
2928 | write_memory (addr, val, partial_len); | |
2929 | } | |
2930 | ||
2931 | /* Note!!! This is NOT an else clause. Odd sized | |
2932 | structs may go thru BOTH paths. Floating point | |
2933 | arguments will not. */ | |
2934 | /* Write this portion of the argument to a general | |
6d82d43b | 2935 | purpose register. */ |
cb3d25d1 MS |
2936 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2937 | && !fp_register_arg_p (typecode, arg_type)) | |
2938 | { | |
6d82d43b AC |
2939 | LONGEST regval = |
2940 | extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
2941 | |
2942 | /* A non-floating-point argument being passed in a | |
2943 | general register. If a struct or union, and if | |
2944 | the remaining length is smaller than the register | |
2945 | size, we have to adjust the register value on | |
2946 | big endian targets. | |
2947 | ||
2948 | It does not seem to be necessary to do the | |
1a69e1e4 | 2949 | same for integral types. */ |
cb3d25d1 | 2950 | |
4c6b5505 | 2951 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 2952 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
2953 | && (typecode == TYPE_CODE_STRUCT |
2954 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 2955 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 2956 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
2957 | |
2958 | if (mips_debug) | |
2959 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
2960 | argreg, | |
1a69e1e4 | 2961 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 2962 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
cb3d25d1 MS |
2963 | argreg++; |
2964 | } | |
2965 | ||
2966 | len -= partial_len; | |
2967 | val += partial_len; | |
2968 | ||
2969 | /* Compute the the offset into the stack at which we | |
6d82d43b | 2970 | will copy the next parameter. |
cb3d25d1 MS |
2971 | |
2972 | In N32 (N64?), the stack_offset only needs to be | |
2973 | adjusted when it has been used. */ | |
2974 | ||
2975 | if (stack_used_p) | |
1a69e1e4 | 2976 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
2977 | } |
2978 | } | |
2979 | if (mips_debug) | |
2980 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
2981 | } | |
2982 | ||
f10683bb | 2983 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 2984 | |
cb3d25d1 MS |
2985 | /* Return adjusted stack pointer. */ |
2986 | return sp; | |
2987 | } | |
2988 | ||
6d82d43b AC |
2989 | static enum return_value_convention |
2990 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
2991 | struct type *type, struct regcache *regcache, | |
47a35522 | 2992 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 2993 | { |
6d82d43b AC |
2994 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2995 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2996 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
2997 | || TYPE_CODE (type) == TYPE_CODE_ARRAY | |
1a69e1e4 | 2998 | || TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 2999 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
3000 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3001 | && TYPE_LENGTH (type) == 16 | |
3002 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3003 | { | |
3004 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
3005 | two registers are used in the same as memory order, so the | |
3006 | eight bytes with the lower memory address are in $f0. */ | |
3007 | if (mips_debug) | |
3008 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
3009 | mips_xfer_register (regcache, | |
f57d151a UW |
3010 | gdbarch_num_regs (current_gdbarch) |
3011 | + mips_regnum (current_gdbarch)->fp0, | |
4c6b5505 UW |
3012 | 8, gdbarch_byte_order (current_gdbarch), |
3013 | readbuf, writebuf, 0); | |
d05f6826 | 3014 | mips_xfer_register (regcache, |
f57d151a UW |
3015 | gdbarch_num_regs (current_gdbarch) |
3016 | + mips_regnum (current_gdbarch)->fp0 + 2, | |
4c6b5505 UW |
3017 | 8, gdbarch_byte_order (current_gdbarch), |
3018 | readbuf ? readbuf + 8 : readbuf, | |
d05f6826 DJ |
3019 | writebuf ? writebuf + 8 : writebuf, 0); |
3020 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3021 | } | |
6d82d43b AC |
3022 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3023 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3024 | { | |
3025 | /* A floating-point value belongs in the least significant part | |
3026 | of FP0. */ | |
3027 | if (mips_debug) | |
3028 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3029 | mips_xfer_register (regcache, | |
f57d151a UW |
3030 | gdbarch_num_regs (current_gdbarch) |
3031 | + mips_regnum (current_gdbarch)->fp0, | |
6d82d43b | 3032 | TYPE_LENGTH (type), |
4c6b5505 UW |
3033 | gdbarch_byte_order (current_gdbarch), |
3034 | readbuf, writebuf, 0); | |
6d82d43b AC |
3035 | return RETURN_VALUE_REGISTER_CONVENTION; |
3036 | } | |
3037 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3038 | && TYPE_NFIELDS (type) <= 2 | |
3039 | && TYPE_NFIELDS (type) >= 1 | |
3040 | && ((TYPE_NFIELDS (type) == 1 | |
3041 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3042 | == TYPE_CODE_FLT)) | |
3043 | || (TYPE_NFIELDS (type) == 2 | |
3044 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3045 | == TYPE_CODE_FLT) | |
3046 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3047 | == TYPE_CODE_FLT))) | |
3048 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3049 | { | |
3050 | /* A struct that contains one or two floats. Each value is part | |
3051 | in the least significant part of their floating point | |
3052 | register.. */ | |
6d82d43b AC |
3053 | int regnum; |
3054 | int field; | |
3055 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3056 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3057 | { | |
3058 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3059 | / TARGET_CHAR_BIT); | |
3060 | if (mips_debug) | |
3061 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3062 | offset); | |
f57d151a UW |
3063 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3064 | + regnum, | |
6d82d43b | 3065 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
4c6b5505 UW |
3066 | gdbarch_byte_order (current_gdbarch), |
3067 | readbuf, writebuf, offset); | |
6d82d43b AC |
3068 | } |
3069 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3070 | } | |
3071 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3072 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3073 | { | |
3074 | /* A structure or union. Extract the left justified value, | |
3075 | regardless of the byte order. I.e. DO NOT USE | |
3076 | mips_xfer_lower. */ | |
3077 | int offset; | |
3078 | int regnum; | |
4c7d22cb | 3079 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3080 | offset < TYPE_LENGTH (type); |
3081 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3082 | { | |
3083 | int xfer = register_size (current_gdbarch, regnum); | |
3084 | if (offset + xfer > TYPE_LENGTH (type)) | |
3085 | xfer = TYPE_LENGTH (type) - offset; | |
3086 | if (mips_debug) | |
3087 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3088 | offset, xfer, regnum); | |
f57d151a UW |
3089 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3090 | + regnum, xfer, | |
6d82d43b AC |
3091 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
3092 | } | |
3093 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3094 | } | |
3095 | else | |
3096 | { | |
3097 | /* A scalar extract each part but least-significant-byte | |
3098 | justified. */ | |
3099 | int offset; | |
3100 | int regnum; | |
4c7d22cb | 3101 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3102 | offset < TYPE_LENGTH (type); |
3103 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3104 | { | |
3105 | int xfer = register_size (current_gdbarch, regnum); | |
6d82d43b AC |
3106 | if (offset + xfer > TYPE_LENGTH (type)) |
3107 | xfer = TYPE_LENGTH (type) - offset; | |
3108 | if (mips_debug) | |
3109 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3110 | offset, xfer, regnum); | |
f57d151a UW |
3111 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3112 | + regnum, xfer, | |
4c6b5505 UW |
3113 | gdbarch_byte_order (current_gdbarch), |
3114 | readbuf, writebuf, offset); | |
6d82d43b AC |
3115 | } |
3116 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3117 | } | |
3118 | } | |
3119 | ||
3120 | /* O32 ABI stuff. */ | |
3121 | ||
3122 | static CORE_ADDR | |
7d9b040b | 3123 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3124 | struct regcache *regcache, CORE_ADDR bp_addr, |
3125 | int nargs, struct value **args, CORE_ADDR sp, | |
3126 | int struct_return, CORE_ADDR struct_addr) | |
3127 | { | |
3128 | int argreg; | |
3129 | int float_argreg; | |
3130 | int argnum; | |
3131 | int len = 0; | |
3132 | int stack_offset = 0; | |
3133 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7d9b040b | 3134 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3135 | |
3136 | /* For shared libraries, "t9" needs to point at the function | |
3137 | address. */ | |
4c7d22cb | 3138 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3139 | |
3140 | /* Set the return address register to point to the entry point of | |
3141 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3142 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3143 | |
3144 | /* First ensure that the stack and structure return address (if any) | |
3145 | are properly aligned. The stack has to be at least 64-bit | |
3146 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3147 | aligned. For n32 and n64, stack frames need to be 128-bit |
3148 | aligned, so we round to this widest known alignment. */ | |
3149 | ||
5b03f266 AC |
3150 | sp = align_down (sp, 16); |
3151 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3152 | |
3153 | /* Now make space on the stack for the args. */ | |
3154 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3155 | { |
3156 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3157 | int arglen = TYPE_LENGTH (arg_type); | |
3158 | ||
3159 | /* Align to double-word if necessary. */ | |
2afd3f0a | 3160 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 3161 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 3162 | /* Allocate space on the stack. */ |
1a69e1e4 | 3163 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 3164 | } |
5b03f266 | 3165 | sp -= align_up (len, 16); |
ebafbe83 MS |
3166 | |
3167 | if (mips_debug) | |
6d82d43b | 3168 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3169 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3170 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3171 | |
3172 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3173 | argreg = MIPS_A0_REGNUM; |
56cea623 | 3174 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 3175 | |
bcb0cc15 | 3176 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3177 | if (struct_return) |
3178 | { | |
3179 | if (mips_debug) | |
3180 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3181 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 | 3182 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 3183 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3184 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
3185 | } |
3186 | ||
3187 | /* Now load as many as possible of the first arguments into | |
3188 | registers, and push the rest onto the stack. Loop thru args | |
3189 | from first to last. */ | |
3190 | for (argnum = 0; argnum < nargs; argnum++) | |
3191 | { | |
47a35522 | 3192 | const gdb_byte *val; |
ebafbe83 | 3193 | struct value *arg = args[argnum]; |
4991999e | 3194 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3195 | int len = TYPE_LENGTH (arg_type); |
3196 | enum type_code typecode = TYPE_CODE (arg_type); | |
3197 | ||
3198 | if (mips_debug) | |
3199 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3200 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3201 | argnum + 1, len, (int) typecode); |
3202 | ||
47a35522 | 3203 | val = value_contents (arg); |
46cac009 AC |
3204 | |
3205 | /* 32-bit ABIs always start floating point arguments in an | |
3206 | even-numbered floating point register. Round the FP register | |
3207 | up before the check to see if there are any FP registers | |
3208 | left. O32/O64 targets also pass the FP in the integer | |
3209 | registers so also round up normal registers. */ | |
2afd3f0a | 3210 | if (fp_register_arg_p (typecode, arg_type)) |
46cac009 AC |
3211 | { |
3212 | if ((float_argreg & 1)) | |
3213 | float_argreg++; | |
3214 | } | |
3215 | ||
3216 | /* Floating point arguments passed in registers have to be | |
3217 | treated specially. On 32-bit architectures, doubles | |
3218 | are passed in register pairs; the even register gets | |
3219 | the low word, and the odd register gets the high word. | |
3220 | On O32/O64, the first two floating point arguments are | |
3221 | also copied to general registers, because MIPS16 functions | |
3222 | don't use float registers for arguments. This duplication of | |
3223 | arguments in general registers can't hurt non-MIPS16 functions | |
3224 | because those registers are normally skipped. */ | |
3225 | ||
3226 | if (fp_register_arg_p (typecode, arg_type) | |
3227 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3228 | { | |
8b07f6d8 | 3229 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 3230 | { |
4c6b5505 UW |
3231 | int low_offset = gdbarch_byte_order (current_gdbarch) |
3232 | == BFD_ENDIAN_BIG ? 4 : 0; | |
46cac009 AC |
3233 | unsigned long regval; |
3234 | ||
3235 | /* Write the low word of the double to the even register(s). */ | |
3236 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3237 | if (mips_debug) | |
3238 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3239 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3240 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3241 | if (mips_debug) |
3242 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3243 | argreg, phex (regval, 4)); | |
9c9acae0 | 3244 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3245 | |
3246 | /* Write the high word of the double to the odd register(s). */ | |
3247 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3248 | if (mips_debug) | |
3249 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3250 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3251 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3252 | |
3253 | if (mips_debug) | |
3254 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3255 | argreg, phex (regval, 4)); | |
9c9acae0 | 3256 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3257 | } |
3258 | else | |
3259 | { | |
3260 | /* This is a floating point value that fits entirely | |
3261 | in a single register. */ | |
3262 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3263 | above to ensure that it is even register aligned. */ |
46cac009 AC |
3264 | LONGEST regval = extract_unsigned_integer (val, len); |
3265 | if (mips_debug) | |
3266 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3267 | float_argreg, phex (regval, len)); | |
9c9acae0 | 3268 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 | 3269 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP |
6d82d43b AC |
3270 | registers for each argument. The below is (my |
3271 | guess) to ensure that the corresponding integer | |
3272 | register has reserved the same space. */ | |
46cac009 AC |
3273 | if (mips_debug) |
3274 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3275 | argreg, phex (regval, len)); | |
9c9acae0 | 3276 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 3277 | argreg += 2; |
46cac009 AC |
3278 | } |
3279 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 3280 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
3281 | } |
3282 | else | |
3283 | { | |
3284 | /* Copy the argument to general registers or the stack in | |
3285 | register-sized pieces. Large arguments are split between | |
3286 | registers and stack. */ | |
1a69e1e4 DJ |
3287 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
3288 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3289 | them in registers where gcc sometimes puts them on the |
3290 | stack. For maximum compatibility, we will put them in | |
3291 | both places. */ | |
1a69e1e4 DJ |
3292 | int odd_sized_struct = (len > MIPS32_REGSIZE |
3293 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
3294 | /* Structures should be aligned to eight bytes (even arg registers) |
3295 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 3296 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
3297 | { |
3298 | if ((argreg & 1)) | |
968b5391 MR |
3299 | { |
3300 | argreg++; | |
1a69e1e4 | 3301 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 3302 | } |
46cac009 | 3303 | } |
46cac009 AC |
3304 | while (len > 0) |
3305 | { | |
3306 | /* Remember if the argument was written to the stack. */ | |
3307 | int stack_used_p = 0; | |
1a69e1e4 | 3308 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
3309 | |
3310 | if (mips_debug) | |
3311 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3312 | partial_len); | |
3313 | ||
3314 | /* Write this portion of the argument to the stack. */ | |
3315 | if (argreg > MIPS_LAST_ARG_REGNUM | |
968b5391 | 3316 | || odd_sized_struct) |
46cac009 AC |
3317 | { |
3318 | /* Should shorter than int integer values be | |
3319 | promoted to int before being stored? */ | |
3320 | int longword_offset = 0; | |
3321 | CORE_ADDR addr; | |
3322 | stack_used_p = 1; | |
46cac009 AC |
3323 | |
3324 | if (mips_debug) | |
3325 | { | |
3326 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3327 | paddr_nz (stack_offset)); | |
3328 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3329 | paddr_nz (longword_offset)); | |
3330 | } | |
3331 | ||
3332 | addr = sp + stack_offset + longword_offset; | |
3333 | ||
3334 | if (mips_debug) | |
3335 | { | |
3336 | int i; | |
6d82d43b | 3337 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
46cac009 AC |
3338 | paddr_nz (addr)); |
3339 | for (i = 0; i < partial_len; i++) | |
3340 | { | |
6d82d43b | 3341 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3342 | val[i] & 0xff); |
3343 | } | |
3344 | } | |
3345 | write_memory (addr, val, partial_len); | |
3346 | } | |
3347 | ||
3348 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3349 | structs may go thru BOTH paths. */ |
46cac009 | 3350 | /* Write this portion of the argument to a general |
6d82d43b | 3351 | purpose register. */ |
968b5391 | 3352 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
46cac009 AC |
3353 | { |
3354 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3355 | /* Value may need to be sign extended, because |
1b13c4f6 | 3356 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3357 | |
3358 | /* A non-floating-point argument being passed in a | |
3359 | general register. If a struct or union, and if | |
3360 | the remaining length is smaller than the register | |
3361 | size, we have to adjust the register value on | |
3362 | big endian targets. | |
3363 | ||
3364 | It does not seem to be necessary to do the | |
3365 | same for integral types. | |
3366 | ||
3367 | Also don't do this adjustment on O64 binaries. | |
3368 | ||
3369 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3370 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
3371 | mips_abi_regsize(), generates a left shift |
3372 | as part of storing the argument in a register | |
3373 | (the left shift isn't generated when | |
1b13c4f6 | 3374 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3375 | it is quite possible that this is GCC |
3376 | contradicting the LE/O32 ABI, GDB has not been | |
3377 | adjusted to accommodate this. Either someone | |
3378 | needs to demonstrate that the LE/O32 ABI | |
3379 | specifies such a left shift OR this new ABI gets | |
3380 | identified as such and GDB gets tweaked | |
3381 | accordingly. */ | |
3382 | ||
4c6b5505 | 3383 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3384 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
3385 | && (typecode == TYPE_CODE_STRUCT |
3386 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3387 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 3388 | * TARGET_CHAR_BIT); |
46cac009 AC |
3389 | |
3390 | if (mips_debug) | |
3391 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3392 | argreg, | |
1a69e1e4 | 3393 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 3394 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
3395 | argreg++; |
3396 | ||
3397 | /* Prevent subsequent floating point arguments from | |
3398 | being passed in floating point registers. */ | |
3399 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3400 | } | |
3401 | ||
3402 | len -= partial_len; | |
3403 | val += partial_len; | |
3404 | ||
3405 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3406 | will copy the next parameter. |
46cac009 | 3407 | |
6d82d43b AC |
3408 | In older ABIs, the caller reserved space for |
3409 | registers that contained arguments. This was loosely | |
3410 | refered to as their "home". Consequently, space is | |
3411 | always allocated. */ | |
46cac009 | 3412 | |
1a69e1e4 | 3413 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
3414 | } |
3415 | } | |
3416 | if (mips_debug) | |
3417 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3418 | } | |
3419 | ||
f10683bb | 3420 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3421 | |
46cac009 AC |
3422 | /* Return adjusted stack pointer. */ |
3423 | return sp; | |
3424 | } | |
3425 | ||
6d82d43b AC |
3426 | static enum return_value_convention |
3427 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
3428 | struct regcache *regcache, | |
47a35522 | 3429 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b AC |
3430 | { |
3431 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3432 | ||
3433 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3434 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3435 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3436 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3437 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3438 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3439 | { | |
3440 | /* A single-precision floating-point value. It fits in the | |
3441 | least significant part of FP0. */ | |
3442 | if (mips_debug) | |
3443 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3444 | mips_xfer_register (regcache, | |
f57d151a UW |
3445 | gdbarch_num_regs (current_gdbarch) |
3446 | + mips_regnum (current_gdbarch)->fp0, | |
6d82d43b | 3447 | TYPE_LENGTH (type), |
4c6b5505 UW |
3448 | gdbarch_byte_order (current_gdbarch), |
3449 | readbuf, writebuf, 0); | |
6d82d43b AC |
3450 | return RETURN_VALUE_REGISTER_CONVENTION; |
3451 | } | |
3452 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3453 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3454 | { | |
3455 | /* A double-precision floating-point value. The most | |
3456 | significant part goes in FP1, and the least significant in | |
3457 | FP0. */ | |
3458 | if (mips_debug) | |
3459 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
4c6b5505 | 3460 | switch (gdbarch_byte_order (current_gdbarch)) |
6d82d43b AC |
3461 | { |
3462 | case BFD_ENDIAN_LITTLE: | |
3463 | mips_xfer_register (regcache, | |
f57d151a UW |
3464 | gdbarch_num_regs (current_gdbarch) |
3465 | + mips_regnum (current_gdbarch)->fp0 + | |
4c6b5505 UW |
3466 | 0, 4, gdbarch_byte_order (current_gdbarch), |
3467 | readbuf, writebuf, 0); | |
6d82d43b | 3468 | mips_xfer_register (regcache, |
f57d151a UW |
3469 | gdbarch_num_regs (current_gdbarch) |
3470 | + mips_regnum (current_gdbarch)->fp0 + 1, | |
4c6b5505 UW |
3471 | 4, gdbarch_byte_order (current_gdbarch), |
3472 | readbuf, writebuf, 4); | |
6d82d43b AC |
3473 | break; |
3474 | case BFD_ENDIAN_BIG: | |
3475 | mips_xfer_register (regcache, | |
f57d151a UW |
3476 | gdbarch_num_regs (current_gdbarch) |
3477 | + mips_regnum (current_gdbarch)->fp0 + 1, | |
4c6b5505 UW |
3478 | 4, gdbarch_byte_order (current_gdbarch), |
3479 | readbuf, writebuf, 0); | |
6d82d43b | 3480 | mips_xfer_register (regcache, |
f57d151a UW |
3481 | gdbarch_num_regs (current_gdbarch) |
3482 | + mips_regnum (current_gdbarch)->fp0 + 0, | |
4c6b5505 UW |
3483 | 4, gdbarch_byte_order (current_gdbarch), |
3484 | readbuf, writebuf, 4); | |
6d82d43b AC |
3485 | break; |
3486 | default: | |
e2e0b3e5 | 3487 | internal_error (__FILE__, __LINE__, _("bad switch")); |
6d82d43b AC |
3488 | } |
3489 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3490 | } | |
3491 | #if 0 | |
3492 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3493 | && TYPE_NFIELDS (type) <= 2 | |
3494 | && TYPE_NFIELDS (type) >= 1 | |
3495 | && ((TYPE_NFIELDS (type) == 1 | |
3496 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3497 | == TYPE_CODE_FLT)) | |
3498 | || (TYPE_NFIELDS (type) == 2 | |
3499 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3500 | == TYPE_CODE_FLT) | |
3501 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3502 | == TYPE_CODE_FLT))) | |
3503 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3504 | { | |
3505 | /* A struct that contains one or two floats. Each value is part | |
3506 | in the least significant part of their floating point | |
3507 | register.. */ | |
870cd05e | 3508 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
3509 | int regnum; |
3510 | int field; | |
3511 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3512 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3513 | { | |
3514 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3515 | / TARGET_CHAR_BIT); | |
3516 | if (mips_debug) | |
3517 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3518 | offset); | |
f57d151a UW |
3519 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3520 | + regnum, | |
6d82d43b | 3521 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
4c6b5505 UW |
3522 | gdbarch_byte_order (current_gdbarch), |
3523 | readbuf, writebuf, offset); | |
6d82d43b AC |
3524 | } |
3525 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3526 | } | |
3527 | #endif | |
3528 | #if 0 | |
3529 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3530 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3531 | { | |
3532 | /* A structure or union. Extract the left justified value, | |
3533 | regardless of the byte order. I.e. DO NOT USE | |
3534 | mips_xfer_lower. */ | |
3535 | int offset; | |
3536 | int regnum; | |
4c7d22cb | 3537 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3538 | offset < TYPE_LENGTH (type); |
3539 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3540 | { | |
3541 | int xfer = register_size (current_gdbarch, regnum); | |
3542 | if (offset + xfer > TYPE_LENGTH (type)) | |
3543 | xfer = TYPE_LENGTH (type) - offset; | |
3544 | if (mips_debug) | |
3545 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3546 | offset, xfer, regnum); | |
f57d151a UW |
3547 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3548 | + regnum, xfer, | |
6d82d43b AC |
3549 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
3550 | } | |
3551 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3552 | } | |
3553 | #endif | |
3554 | else | |
3555 | { | |
3556 | /* A scalar extract each part but least-significant-byte | |
3557 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 3558 | the ISA. */ |
6d82d43b AC |
3559 | int offset; |
3560 | int regnum; | |
4c7d22cb | 3561 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3562 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 3563 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 3564 | { |
1a69e1e4 | 3565 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
3566 | if (offset + xfer > TYPE_LENGTH (type)) |
3567 | xfer = TYPE_LENGTH (type) - offset; | |
3568 | if (mips_debug) | |
3569 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3570 | offset, xfer, regnum); | |
f57d151a UW |
3571 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3572 | + regnum, xfer, | |
4c6b5505 UW |
3573 | gdbarch_byte_order (current_gdbarch), |
3574 | readbuf, writebuf, offset); | |
6d82d43b AC |
3575 | } |
3576 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3577 | } | |
3578 | } | |
3579 | ||
3580 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
3581 | ABI. */ | |
46cac009 AC |
3582 | |
3583 | static CORE_ADDR | |
7d9b040b | 3584 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3585 | struct regcache *regcache, CORE_ADDR bp_addr, |
3586 | int nargs, | |
3587 | struct value **args, CORE_ADDR sp, | |
3588 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
3589 | { |
3590 | int argreg; | |
3591 | int float_argreg; | |
3592 | int argnum; | |
3593 | int len = 0; | |
3594 | int stack_offset = 0; | |
480d3dd2 | 3595 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3596 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 3597 | |
25ab4790 AC |
3598 | /* For shared libraries, "t9" needs to point at the function |
3599 | address. */ | |
4c7d22cb | 3600 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3601 | |
3602 | /* Set the return address register to point to the entry point of | |
3603 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3604 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3605 | |
46cac009 AC |
3606 | /* First ensure that the stack and structure return address (if any) |
3607 | are properly aligned. The stack has to be at least 64-bit | |
3608 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3609 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3610 | aligned, so we round to this widest known alignment. */ | |
3611 | ||
5b03f266 AC |
3612 | sp = align_down (sp, 16); |
3613 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3614 | |
3615 | /* Now make space on the stack for the args. */ | |
3616 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3617 | { |
3618 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3619 | int arglen = TYPE_LENGTH (arg_type); | |
3620 | ||
968b5391 | 3621 | /* Allocate space on the stack. */ |
1a69e1e4 | 3622 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 3623 | } |
5b03f266 | 3624 | sp -= align_up (len, 16); |
46cac009 AC |
3625 | |
3626 | if (mips_debug) | |
6d82d43b | 3627 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3628 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
3629 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
3630 | |
3631 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3632 | argreg = MIPS_A0_REGNUM; |
56cea623 | 3633 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
3634 | |
3635 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3636 | if (struct_return) | |
3637 | { | |
3638 | if (mips_debug) | |
3639 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3640 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 | 3641 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 3642 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3643 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
3644 | } |
3645 | ||
3646 | /* Now load as many as possible of the first arguments into | |
3647 | registers, and push the rest onto the stack. Loop thru args | |
3648 | from first to last. */ | |
3649 | for (argnum = 0; argnum < nargs; argnum++) | |
3650 | { | |
47a35522 | 3651 | const gdb_byte *val; |
46cac009 | 3652 | struct value *arg = args[argnum]; |
4991999e | 3653 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
3654 | int len = TYPE_LENGTH (arg_type); |
3655 | enum type_code typecode = TYPE_CODE (arg_type); | |
3656 | ||
3657 | if (mips_debug) | |
3658 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3659 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
3660 | argnum + 1, len, (int) typecode); |
3661 | ||
47a35522 | 3662 | val = value_contents (arg); |
ebafbe83 | 3663 | |
ebafbe83 MS |
3664 | /* Floating point arguments passed in registers have to be |
3665 | treated specially. On 32-bit architectures, doubles | |
3666 | are passed in register pairs; the even register gets | |
3667 | the low word, and the odd register gets the high word. | |
3668 | On O32/O64, the first two floating point arguments are | |
3669 | also copied to general registers, because MIPS16 functions | |
3670 | don't use float registers for arguments. This duplication of | |
3671 | arguments in general registers can't hurt non-MIPS16 functions | |
3672 | because those registers are normally skipped. */ | |
3673 | ||
3674 | if (fp_register_arg_p (typecode, arg_type) | |
3675 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3676 | { | |
2afd3f0a MR |
3677 | LONGEST regval = extract_unsigned_integer (val, len); |
3678 | if (mips_debug) | |
3679 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3680 | float_argreg, phex (regval, len)); | |
9c9acae0 | 3681 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
3682 | if (mips_debug) |
3683 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3684 | argreg, phex (regval, len)); | |
9c9acae0 | 3685 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 3686 | argreg++; |
ebafbe83 | 3687 | /* Reserve space for the FP register. */ |
1a69e1e4 | 3688 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
3689 | } |
3690 | else | |
3691 | { | |
3692 | /* Copy the argument to general registers or the stack in | |
3693 | register-sized pieces. Large arguments are split between | |
3694 | registers and stack. */ | |
1a69e1e4 | 3695 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
3696 | are treated specially: Irix cc passes them in registers |
3697 | where gcc sometimes puts them on the stack. For maximum | |
3698 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
3699 | int odd_sized_struct = (len > MIPS64_REGSIZE |
3700 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
3701 | while (len > 0) |
3702 | { | |
3703 | /* Remember if the argument was written to the stack. */ | |
3704 | int stack_used_p = 0; | |
1a69e1e4 | 3705 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
3706 | |
3707 | if (mips_debug) | |
3708 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3709 | partial_len); | |
3710 | ||
3711 | /* Write this portion of the argument to the stack. */ | |
3712 | if (argreg > MIPS_LAST_ARG_REGNUM | |
968b5391 | 3713 | || odd_sized_struct) |
ebafbe83 MS |
3714 | { |
3715 | /* Should shorter than int integer values be | |
3716 | promoted to int before being stored? */ | |
3717 | int longword_offset = 0; | |
3718 | CORE_ADDR addr; | |
3719 | stack_used_p = 1; | |
4c6b5505 | 3720 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 3721 | { |
1a69e1e4 DJ |
3722 | if ((typecode == TYPE_CODE_INT |
3723 | || typecode == TYPE_CODE_PTR | |
3724 | || typecode == TYPE_CODE_FLT) | |
3725 | && len <= 4) | |
3726 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
3727 | } |
3728 | ||
3729 | if (mips_debug) | |
3730 | { | |
3731 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3732 | paddr_nz (stack_offset)); | |
3733 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3734 | paddr_nz (longword_offset)); | |
3735 | } | |
3736 | ||
3737 | addr = sp + stack_offset + longword_offset; | |
3738 | ||
3739 | if (mips_debug) | |
3740 | { | |
3741 | int i; | |
6d82d43b | 3742 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
ebafbe83 MS |
3743 | paddr_nz (addr)); |
3744 | for (i = 0; i < partial_len; i++) | |
3745 | { | |
6d82d43b | 3746 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
3747 | val[i] & 0xff); |
3748 | } | |
3749 | } | |
3750 | write_memory (addr, val, partial_len); | |
3751 | } | |
3752 | ||
3753 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3754 | structs may go thru BOTH paths. */ |
ebafbe83 | 3755 | /* Write this portion of the argument to a general |
6d82d43b | 3756 | purpose register. */ |
968b5391 | 3757 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
ebafbe83 MS |
3758 | { |
3759 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3760 | /* Value may need to be sign extended, because |
1b13c4f6 | 3761 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
3762 | |
3763 | /* A non-floating-point argument being passed in a | |
3764 | general register. If a struct or union, and if | |
3765 | the remaining length is smaller than the register | |
3766 | size, we have to adjust the register value on | |
3767 | big endian targets. | |
3768 | ||
3769 | It does not seem to be necessary to do the | |
401835eb | 3770 | same for integral types. */ |
480d3dd2 | 3771 | |
4c6b5505 | 3772 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3773 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3774 | && (typecode == TYPE_CODE_STRUCT |
3775 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3776 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3777 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
3778 | |
3779 | if (mips_debug) | |
3780 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3781 | argreg, | |
1a69e1e4 | 3782 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3783 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
3784 | argreg++; |
3785 | ||
3786 | /* Prevent subsequent floating point arguments from | |
3787 | being passed in floating point registers. */ | |
3788 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3789 | } | |
3790 | ||
3791 | len -= partial_len; | |
3792 | val += partial_len; | |
3793 | ||
3794 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3795 | will copy the next parameter. |
ebafbe83 | 3796 | |
6d82d43b AC |
3797 | In older ABIs, the caller reserved space for |
3798 | registers that contained arguments. This was loosely | |
3799 | refered to as their "home". Consequently, space is | |
3800 | always allocated. */ | |
ebafbe83 | 3801 | |
1a69e1e4 | 3802 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
3803 | } |
3804 | } | |
3805 | if (mips_debug) | |
3806 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3807 | } | |
3808 | ||
f10683bb | 3809 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3810 | |
ebafbe83 MS |
3811 | /* Return adjusted stack pointer. */ |
3812 | return sp; | |
3813 | } | |
3814 | ||
9c8fdbfa AC |
3815 | static enum return_value_convention |
3816 | mips_o64_return_value (struct gdbarch *gdbarch, | |
3817 | struct type *type, struct regcache *regcache, | |
47a35522 | 3818 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3819 | { |
7a076fd2 FF |
3820 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3821 | ||
3822 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3823 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3824 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3825 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3826 | else if (fp_register_arg_p (TYPE_CODE (type), type)) | |
3827 | { | |
3828 | /* A floating-point value. It fits in the least significant | |
3829 | part of FP0. */ | |
3830 | if (mips_debug) | |
3831 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3832 | mips_xfer_register (regcache, | |
f57d151a UW |
3833 | gdbarch_num_regs (current_gdbarch) |
3834 | + mips_regnum (current_gdbarch)->fp0, | |
7a076fd2 | 3835 | TYPE_LENGTH (type), |
4c6b5505 UW |
3836 | gdbarch_byte_order (current_gdbarch), |
3837 | readbuf, writebuf, 0); | |
7a076fd2 FF |
3838 | return RETURN_VALUE_REGISTER_CONVENTION; |
3839 | } | |
3840 | else | |
3841 | { | |
3842 | /* A scalar extract each part but least-significant-byte | |
3843 | justified. */ | |
3844 | int offset; | |
3845 | int regnum; | |
3846 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
3847 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 3848 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 3849 | { |
1a69e1e4 | 3850 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
3851 | if (offset + xfer > TYPE_LENGTH (type)) |
3852 | xfer = TYPE_LENGTH (type) - offset; | |
3853 | if (mips_debug) | |
3854 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3855 | offset, xfer, regnum); | |
f57d151a UW |
3856 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3857 | + regnum, xfer, | |
4c6b5505 UW |
3858 | gdbarch_byte_order (current_gdbarch), |
3859 | readbuf, writebuf, offset); | |
7a076fd2 FF |
3860 | } |
3861 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3862 | } | |
6d82d43b AC |
3863 | } |
3864 | ||
dd824b04 DJ |
3865 | /* Floating point register management. |
3866 | ||
3867 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
3868 | 64bit operations, these early MIPS cpus treat fp register pairs | |
3869 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
3870 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
3871 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
3872 | double precision floats into two 32-bit chunks and store them in | |
3873 | consecutive fp regs. To display 64-bit floats stored in this | |
3874 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
3875 | Throw in user-configurable endianness and you have a real mess. | |
3876 | ||
3877 | The way this works is: | |
3878 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
3879 | double-precision value will be split across two logical registers. | |
3880 | The lower-numbered logical register will hold the low-order bits, | |
3881 | regardless of the processor's endianness. | |
3882 | - If we are on a 64-bit processor, and we are looking for a | |
3883 | single-precision value, it will be in the low ordered bits | |
3884 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
3885 | save slot in memory. | |
3886 | - If we are in 64-bit mode, everything is straightforward. | |
3887 | ||
3888 | Note that this code only deals with "live" registers at the top of the | |
3889 | stack. We will attempt to deal with saved registers later, when | |
3890 | the raw/cooked register interface is in place. (We need a general | |
3891 | interface that can deal with dynamic saved register sizes -- fp | |
3892 | regs could be 32 bits wide in one frame and 64 on the frame above | |
3893 | and below). */ | |
3894 | ||
67b2c998 DJ |
3895 | static struct type * |
3896 | mips_float_register_type (void) | |
3897 | { | |
8da61cc4 | 3898 | return builtin_type_ieee_single; |
67b2c998 DJ |
3899 | } |
3900 | ||
3901 | static struct type * | |
3902 | mips_double_register_type (void) | |
3903 | { | |
8da61cc4 | 3904 | return builtin_type_ieee_double; |
67b2c998 DJ |
3905 | } |
3906 | ||
dd824b04 DJ |
3907 | /* Copy a 32-bit single-precision value from the current frame |
3908 | into rare_buffer. */ | |
3909 | ||
3910 | static void | |
e11c53d2 | 3911 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 3912 | gdb_byte *rare_buffer) |
dd824b04 | 3913 | { |
719ec221 | 3914 | int raw_size = register_size (current_gdbarch, regno); |
47a35522 | 3915 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 3916 | |
e11c53d2 | 3917 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 UW |
3918 | error (_("can't read register %d (%s)"), |
3919 | regno, gdbarch_register_name (current_gdbarch, regno)); | |
dd824b04 DJ |
3920 | if (raw_size == 8) |
3921 | { | |
3922 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 3923 | 32 bits. */ |
dd824b04 DJ |
3924 | int offset; |
3925 | ||
4c6b5505 | 3926 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
3927 | offset = 4; |
3928 | else | |
3929 | offset = 0; | |
3930 | ||
3931 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
3932 | } | |
3933 | else | |
3934 | { | |
3935 | memcpy (rare_buffer, raw_buffer, 4); | |
3936 | } | |
3937 | } | |
3938 | ||
3939 | /* Copy a 64-bit double-precision value from the current frame into | |
3940 | rare_buffer. This may include getting half of it from the next | |
3941 | register. */ | |
3942 | ||
3943 | static void | |
e11c53d2 | 3944 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 3945 | gdb_byte *rare_buffer) |
dd824b04 | 3946 | { |
719ec221 | 3947 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 | 3948 | |
9c9acae0 | 3949 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
3950 | { |
3951 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 3952 | all 64 bits. */ |
e11c53d2 | 3953 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 UW |
3954 | error (_("can't read register %d (%s)"), |
3955 | regno, gdbarch_register_name (current_gdbarch, regno)); | |
dd824b04 DJ |
3956 | } |
3957 | else | |
3958 | { | |
56cea623 | 3959 | if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) |
dd824b04 | 3960 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
3961 | _("mips_read_fp_register_double: bad access to " |
3962 | "odd-numbered FP register")); | |
dd824b04 DJ |
3963 | |
3964 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 3965 | each register. */ |
4c6b5505 | 3966 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 3967 | { |
e11c53d2 AC |
3968 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
3969 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 3970 | } |
361d1df0 | 3971 | else |
dd824b04 | 3972 | { |
e11c53d2 AC |
3973 | mips_read_fp_register_single (frame, regno, rare_buffer); |
3974 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
3975 | } |
3976 | } | |
3977 | } | |
3978 | ||
c906108c | 3979 | static void |
e11c53d2 AC |
3980 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
3981 | int regnum) | |
c5aa993b | 3982 | { /* do values for FP (float) regs */ |
47a35522 | 3983 | gdb_byte *raw_buffer; |
3903d437 AC |
3984 | double doub, flt1; /* doubles extracted from raw hex data */ |
3985 | int inv1, inv2; | |
c5aa993b | 3986 | |
47a35522 MK |
3987 | raw_buffer = alloca (2 * register_size (current_gdbarch, |
3988 | mips_regnum (current_gdbarch)->fp0)); | |
c906108c | 3989 | |
c9f4d572 UW |
3990 | fprintf_filtered (file, "%s:", |
3991 | gdbarch_register_name (current_gdbarch, regnum)); | |
3992 | fprintf_filtered (file, "%*s", | |
3993 | 4 - (int) strlen (gdbarch_register_name | |
3994 | (current_gdbarch, regnum)), | |
e11c53d2 | 3995 | ""); |
f0ef6b29 | 3996 | |
9c9acae0 | 3997 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 3998 | { |
f0ef6b29 KB |
3999 | /* 4-byte registers: Print hex and floating. Also print even |
4000 | numbered registers as doubles. */ | |
e11c53d2 | 4001 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4002 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4003 | |
6d82d43b AC |
4004 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', |
4005 | file); | |
dd824b04 | 4006 | |
e11c53d2 | 4007 | fprintf_filtered (file, " flt: "); |
1adad886 | 4008 | if (inv1) |
e11c53d2 | 4009 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4010 | else |
e11c53d2 | 4011 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4012 | |
f0ef6b29 KB |
4013 | if (regnum % 2 == 0) |
4014 | { | |
e11c53d2 | 4015 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 | 4016 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
6d82d43b | 4017 | &inv2); |
1adad886 | 4018 | |
e11c53d2 | 4019 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4020 | if (inv2) |
e11c53d2 | 4021 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4022 | else |
e11c53d2 | 4023 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4024 | } |
c906108c SS |
4025 | } |
4026 | else | |
dd824b04 | 4027 | { |
f0ef6b29 | 4028 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4029 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4030 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4031 | |
e11c53d2 | 4032 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4033 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4034 | ||
361d1df0 | 4035 | |
6d82d43b AC |
4036 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', |
4037 | file); | |
f0ef6b29 | 4038 | |
e11c53d2 | 4039 | fprintf_filtered (file, " flt: "); |
1adad886 | 4040 | if (inv1) |
e11c53d2 | 4041 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4042 | else |
e11c53d2 | 4043 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4044 | |
e11c53d2 | 4045 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4046 | if (inv2) |
e11c53d2 | 4047 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4048 | else |
e11c53d2 | 4049 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4050 | } |
4051 | } | |
4052 | ||
4053 | static void | |
e11c53d2 | 4054 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 4055 | int regnum) |
f0ef6b29 | 4056 | { |
a4b8ebc8 | 4057 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4058 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4059 | int offset; |
1adad886 | 4060 | |
7b9ee6a8 | 4061 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4062 | { |
e11c53d2 | 4063 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4064 | return; |
4065 | } | |
4066 | ||
4067 | /* Get the data in raw format. */ | |
e11c53d2 | 4068 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4069 | { |
c9f4d572 UW |
4070 | fprintf_filtered (file, "%s: [Invalid]", |
4071 | gdbarch_register_name (current_gdbarch, regnum)); | |
f0ef6b29 | 4072 | return; |
c906108c | 4073 | } |
f0ef6b29 | 4074 | |
c9f4d572 | 4075 | fputs_filtered (gdbarch_register_name (current_gdbarch, regnum), file); |
f0ef6b29 KB |
4076 | |
4077 | /* The problem with printing numeric register names (r26, etc.) is that | |
4078 | the user can't use them on input. Probably the best solution is to | |
4079 | fix it so that either the numeric or the funky (a2, etc.) names | |
4080 | are accepted on input. */ | |
4081 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4082 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4083 | else |
e11c53d2 | 4084 | fprintf_filtered (file, ": "); |
f0ef6b29 | 4085 | |
4c6b5505 | 4086 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b AC |
4087 | offset = |
4088 | register_size (current_gdbarch, | |
4089 | regnum) - register_size (current_gdbarch, regnum); | |
f0ef6b29 KB |
4090 | else |
4091 | offset = 0; | |
4092 | ||
6d82d43b | 4093 | print_scalar_formatted (raw_buffer + offset, |
7b9ee6a8 | 4094 | register_type (gdbarch, regnum), 'x', 0, |
6d82d43b | 4095 | file); |
c906108c SS |
4096 | } |
4097 | ||
f0ef6b29 KB |
4098 | /* Replacement for generic do_registers_info. |
4099 | Print regs in pretty columns. */ | |
4100 | ||
4101 | static int | |
e11c53d2 AC |
4102 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4103 | int regnum) | |
f0ef6b29 | 4104 | { |
e11c53d2 AC |
4105 | fprintf_filtered (file, " "); |
4106 | mips_print_fp_register (file, frame, regnum); | |
4107 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4108 | return regnum + 1; |
4109 | } | |
4110 | ||
4111 | ||
c906108c SS |
4112 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4113 | ||
4114 | static int | |
e11c53d2 | 4115 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4116 | int start_regnum) |
c906108c | 4117 | { |
a4b8ebc8 | 4118 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4119 | /* do values for GP (int) regs */ |
47a35522 | 4120 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 4121 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4122 | int col, byte; |
a4b8ebc8 | 4123 | int regnum; |
c906108c SS |
4124 | |
4125 | /* For GP registers, we print a separate row of names above the vals */ | |
a4b8ebc8 | 4126 | for (col = 0, regnum = start_regnum; |
f57d151a UW |
4127 | col < ncols && regnum < gdbarch_num_regs (current_gdbarch) |
4128 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4129 | regnum++) | |
c906108c | 4130 | { |
c9f4d572 | 4131 | if (*gdbarch_register_name (current_gdbarch, regnum) == '\0') |
c5aa993b | 4132 | continue; /* unused register */ |
7b9ee6a8 | 4133 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4134 | TYPE_CODE_FLT) |
c5aa993b | 4135 | break; /* end the row: reached FP register */ |
0cc93a06 DJ |
4136 | /* Large registers are handled separately. */ |
4137 | if (register_size (current_gdbarch, regnum) | |
4138 | > mips_abi_regsize (current_gdbarch)) | |
4139 | { | |
4140 | if (col > 0) | |
4141 | break; /* End the row before this register. */ | |
4142 | ||
4143 | /* Print this register on a row by itself. */ | |
4144 | mips_print_register (file, frame, regnum); | |
4145 | fprintf_filtered (file, "\n"); | |
4146 | return regnum + 1; | |
4147 | } | |
d05f6826 DJ |
4148 | if (col == 0) |
4149 | fprintf_filtered (file, " "); | |
6d82d43b | 4150 | fprintf_filtered (file, |
d5ac5a39 | 4151 | mips_abi_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", |
c9f4d572 | 4152 | gdbarch_register_name (current_gdbarch, regnum)); |
c906108c SS |
4153 | col++; |
4154 | } | |
d05f6826 DJ |
4155 | |
4156 | if (col == 0) | |
4157 | return regnum; | |
4158 | ||
a4b8ebc8 | 4159 | /* print the R0 to R31 names */ |
f57d151a UW |
4160 | if ((start_regnum % gdbarch_num_regs (current_gdbarch)) < MIPS_NUMREGS) |
4161 | fprintf_filtered (file, "\n R%-4d", | |
4162 | start_regnum % gdbarch_num_regs (current_gdbarch)); | |
20e6603c AC |
4163 | else |
4164 | fprintf_filtered (file, "\n "); | |
c906108c | 4165 | |
c906108c | 4166 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4167 | for (col = 0, regnum = start_regnum; |
f57d151a UW |
4168 | col < ncols && regnum < gdbarch_num_regs (current_gdbarch) |
4169 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4170 | regnum++) | |
c906108c | 4171 | { |
c9f4d572 | 4172 | if (*gdbarch_register_name (current_gdbarch, regnum) == '\0') |
c5aa993b | 4173 | continue; /* unused register */ |
7b9ee6a8 | 4174 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4175 | TYPE_CODE_FLT) |
c5aa993b | 4176 | break; /* end row: reached FP register */ |
0cc93a06 DJ |
4177 | if (register_size (current_gdbarch, regnum) |
4178 | > mips_abi_regsize (current_gdbarch)) | |
4179 | break; /* End row: large register. */ | |
4180 | ||
c906108c | 4181 | /* OK: get the data in raw format. */ |
e11c53d2 | 4182 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 UW |
4183 | error (_("can't read register %d (%s)"), |
4184 | regnum, gdbarch_register_name (current_gdbarch, regnum)); | |
c906108c | 4185 | /* pad small registers */ |
4246e332 | 4186 | for (byte = 0; |
d5ac5a39 | 4187 | byte < (mips_abi_regsize (current_gdbarch) |
6d82d43b | 4188 | - register_size (current_gdbarch, regnum)); byte++) |
c906108c SS |
4189 | printf_filtered (" "); |
4190 | /* Now print the register value in hex, endian order. */ | |
4c6b5505 | 4191 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b AC |
4192 | for (byte = |
4193 | register_size (current_gdbarch, | |
4194 | regnum) - register_size (current_gdbarch, regnum); | |
4195 | byte < register_size (current_gdbarch, regnum); byte++) | |
47a35522 | 4196 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 4197 | else |
c73e8f27 | 4198 | for (byte = register_size (current_gdbarch, regnum) - 1; |
6d82d43b | 4199 | byte >= 0; byte--) |
47a35522 | 4200 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 4201 | fprintf_filtered (file, " "); |
c906108c SS |
4202 | col++; |
4203 | } | |
c5aa993b | 4204 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4205 | fprintf_filtered (file, "\n"); |
c906108c SS |
4206 | |
4207 | return regnum; | |
4208 | } | |
4209 | ||
4210 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4211 | ||
bf1f5b4c | 4212 | static void |
e11c53d2 AC |
4213 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4214 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4215 | { |
c5aa993b | 4216 | if (regnum != -1) /* do one specified register */ |
c906108c | 4217 | { |
f57d151a | 4218 | gdb_assert (regnum >= gdbarch_num_regs (current_gdbarch)); |
c9f4d572 | 4219 | if (*(gdbarch_register_name (current_gdbarch, regnum)) == '\0') |
8a3fe4f8 | 4220 | error (_("Not a valid register for the current processor type")); |
c906108c | 4221 | |
0cc93a06 | 4222 | mips_print_register (file, frame, regnum); |
e11c53d2 | 4223 | fprintf_filtered (file, "\n"); |
c906108c | 4224 | } |
c5aa993b JM |
4225 | else |
4226 | /* do all (or most) registers */ | |
c906108c | 4227 | { |
f57d151a UW |
4228 | regnum = gdbarch_num_regs (current_gdbarch); |
4229 | while (regnum < gdbarch_num_regs (current_gdbarch) | |
4230 | + gdbarch_num_pseudo_regs (current_gdbarch)) | |
c906108c | 4231 | { |
7b9ee6a8 | 4232 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4233 | TYPE_CODE_FLT) |
e11c53d2 AC |
4234 | { |
4235 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4236 | regnum = print_fp_register_row (file, frame, regnum); | |
4237 | else | |
4238 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4239 | } | |
c906108c | 4240 | else |
e11c53d2 | 4241 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4242 | } |
4243 | } | |
4244 | } | |
4245 | ||
c906108c SS |
4246 | /* Is this a branch with a delay slot? */ |
4247 | ||
c906108c | 4248 | static int |
acdb74a0 | 4249 | is_delayed (unsigned long insn) |
c906108c SS |
4250 | { |
4251 | int i; | |
4252 | for (i = 0; i < NUMOPCODES; ++i) | |
4253 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4254 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4255 | break; | |
4256 | return (i < NUMOPCODES | |
4257 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4258 | | INSN_COND_BRANCH_DELAY | |
4259 | | INSN_COND_BRANCH_LIKELY))); | |
4260 | } | |
4261 | ||
4262 | int | |
3352ef37 AC |
4263 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
4264 | struct frame_info *frame) | |
c906108c | 4265 | { |
3352ef37 | 4266 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 4267 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
4268 | |
4269 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4270 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4271 | return 0; |
4272 | ||
06648491 MK |
4273 | if (!breakpoint_here_p (pc + 4)) |
4274 | return 0; | |
4275 | ||
3352ef37 AC |
4276 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
4277 | /* If error reading memory, guess that it is not a delayed | |
4278 | branch. */ | |
c906108c | 4279 | return 0; |
4c7d22cb | 4280 | return is_delayed (extract_unsigned_integer (buf, sizeof buf)); |
c906108c SS |
4281 | } |
4282 | ||
6d82d43b AC |
4283 | /* To skip prologues, I use this predicate. Returns either PC itself |
4284 | if the code at PC does not look like a function prologue; otherwise | |
4285 | returns an address that (if we're lucky) follows the prologue. If | |
4286 | LENIENT, then we must skip everything which is involved in setting | |
4287 | up the frame (it's OK to skip more, just so long as we don't skip | |
4288 | anything which might clobber the registers which are being saved. | |
4289 | We must skip more in the case where part of the prologue is in the | |
4290 | delay slot of a non-prologue instruction). */ | |
4291 | ||
4292 | static CORE_ADDR | |
4293 | mips_skip_prologue (CORE_ADDR pc) | |
4294 | { | |
8b622e6a AC |
4295 | CORE_ADDR limit_pc; |
4296 | CORE_ADDR func_addr; | |
4297 | ||
6d82d43b AC |
4298 | /* See if we can determine the end of the prologue via the symbol table. |
4299 | If so, then return either PC, or the PC after the prologue, whichever | |
4300 | is greater. */ | |
8b622e6a AC |
4301 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4302 | { | |
4303 | CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr); | |
4304 | if (post_prologue_pc != 0) | |
4305 | return max (pc, post_prologue_pc); | |
4306 | } | |
6d82d43b AC |
4307 | |
4308 | /* Can't determine prologue from the symbol table, need to examine | |
4309 | instructions. */ | |
4310 | ||
98b4dd94 JB |
4311 | /* Find an upper limit on the function prologue using the debug |
4312 | information. If the debug information could not be used to provide | |
4313 | that bound, then use an arbitrary large number as the upper bound. */ | |
4314 | limit_pc = skip_prologue_using_sal (pc); | |
4315 | if (limit_pc == 0) | |
4316 | limit_pc = pc + 100; /* Magic. */ | |
4317 | ||
0fe7e7c8 | 4318 | if (mips_pc_is_mips16 (pc)) |
a65bbe44 | 4319 | return mips16_scan_prologue (pc, limit_pc, NULL, NULL); |
6d82d43b | 4320 | else |
a65bbe44 | 4321 | return mips32_scan_prologue (pc, limit_pc, NULL, NULL); |
88658117 AC |
4322 | } |
4323 | ||
a5ea2558 AC |
4324 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4325 | used for all MIPS-specific commands. */ | |
4326 | ||
a5ea2558 | 4327 | static void |
acdb74a0 | 4328 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4329 | { |
4330 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4331 | } | |
4332 | ||
a5ea2558 | 4333 | static void |
acdb74a0 | 4334 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 4335 | { |
6d82d43b AC |
4336 | printf_unfiltered |
4337 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
4338 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
4339 | } | |
4340 | ||
c906108c SS |
4341 | /* Commands to show/set the MIPS FPU type. */ |
4342 | ||
c906108c | 4343 | static void |
acdb74a0 | 4344 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4345 | { |
c906108c SS |
4346 | char *fpu; |
4347 | switch (MIPS_FPU_TYPE) | |
4348 | { | |
4349 | case MIPS_FPU_SINGLE: | |
4350 | fpu = "single-precision"; | |
4351 | break; | |
4352 | case MIPS_FPU_DOUBLE: | |
4353 | fpu = "double-precision"; | |
4354 | break; | |
4355 | case MIPS_FPU_NONE: | |
4356 | fpu = "absent (none)"; | |
4357 | break; | |
93d56215 | 4358 | default: |
e2e0b3e5 | 4359 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
4360 | } |
4361 | if (mips_fpu_type_auto) | |
6d82d43b AC |
4362 | printf_unfiltered |
4363 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4364 | fpu); | |
c906108c | 4365 | else |
6d82d43b AC |
4366 | printf_unfiltered |
4367 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
4368 | } |
4369 | ||
4370 | ||
c906108c | 4371 | static void |
acdb74a0 | 4372 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 4373 | { |
6d82d43b AC |
4374 | printf_unfiltered |
4375 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
4376 | show_mipsfpu_command (args, from_tty); |
4377 | } | |
4378 | ||
c906108c | 4379 | static void |
acdb74a0 | 4380 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 4381 | { |
8d5838b5 AC |
4382 | struct gdbarch_info info; |
4383 | gdbarch_info_init (&info); | |
c906108c SS |
4384 | mips_fpu_type = MIPS_FPU_SINGLE; |
4385 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4386 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4387 | instead of relying on globals. Doing that would let generic code | |
4388 | handle the search for this specific architecture. */ | |
4389 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4390 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4391 | } |
4392 | ||
c906108c | 4393 | static void |
acdb74a0 | 4394 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 4395 | { |
8d5838b5 AC |
4396 | struct gdbarch_info info; |
4397 | gdbarch_info_init (&info); | |
c906108c SS |
4398 | mips_fpu_type = MIPS_FPU_DOUBLE; |
4399 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4400 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4401 | instead of relying on globals. Doing that would let generic code | |
4402 | handle the search for this specific architecture. */ | |
4403 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4404 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4405 | } |
4406 | ||
c906108c | 4407 | static void |
acdb74a0 | 4408 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 4409 | { |
8d5838b5 AC |
4410 | struct gdbarch_info info; |
4411 | gdbarch_info_init (&info); | |
c906108c SS |
4412 | mips_fpu_type = MIPS_FPU_NONE; |
4413 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4414 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4415 | instead of relying on globals. Doing that would let generic code | |
4416 | handle the search for this specific architecture. */ | |
4417 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4418 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4419 | } |
4420 | ||
c906108c | 4421 | static void |
acdb74a0 | 4422 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
4423 | { |
4424 | mips_fpu_type_auto = 1; | |
4425 | } | |
4426 | ||
c906108c | 4427 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
4428 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
4429 | the relevant processor still exists (it dates back to '94) and | |
4430 | secondly this is not the way to do this. The processor type should | |
4431 | be set by forcing an architecture change. */ | |
c906108c | 4432 | |
691c0433 AC |
4433 | void |
4434 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 4435 | { |
691c0433 | 4436 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
a9614958 | 4437 | ULONGEST prid; |
c906108c | 4438 | |
594f7785 | 4439 | regcache_cooked_read_unsigned (get_current_regcache (), |
a9614958 | 4440 | MIPS_PRID_REGNUM, &prid); |
c906108c | 4441 | if ((prid & ~0xf) == 0x700) |
691c0433 | 4442 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
4443 | } |
4444 | ||
4445 | /* Just like reinit_frame_cache, but with the right arguments to be | |
4446 | callable as an sfunc. */ | |
4447 | ||
4448 | static void | |
acdb74a0 AC |
4449 | reinit_frame_cache_sfunc (char *args, int from_tty, |
4450 | struct cmd_list_element *c) | |
c906108c SS |
4451 | { |
4452 | reinit_frame_cache (); | |
4453 | } | |
4454 | ||
a89aa300 AC |
4455 | static int |
4456 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 4457 | { |
e5ab0dce | 4458 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 4459 | |
d31431ed AC |
4460 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
4461 | disassembler needs to be able to locally determine the ISA, and | |
4462 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
4463 | work. */ | |
ec4045ea AC |
4464 | if (mips_pc_is_mips16 (memaddr)) |
4465 | info->mach = bfd_mach_mips16; | |
c906108c SS |
4466 | |
4467 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 4468 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 4469 | |
e5ab0dce | 4470 | /* Set the disassembler options. */ |
6d82d43b | 4471 | if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64) |
e5ab0dce AC |
4472 | { |
4473 | /* Set up the disassembler info, so that we get the right | |
6d82d43b | 4474 | register names from libopcodes. */ |
e5ab0dce AC |
4475 | if (tdep->mips_abi == MIPS_ABI_N32) |
4476 | info->disassembler_options = "gpr-names=n32"; | |
4477 | else | |
4478 | info->disassembler_options = "gpr-names=64"; | |
4479 | info->flavour = bfd_target_elf_flavour; | |
4480 | } | |
4481 | else | |
4482 | /* This string is not recognized explicitly by the disassembler, | |
4483 | but it tells the disassembler to not try to guess the ABI from | |
4484 | the bfd elf headers, such that, if the user overrides the ABI | |
4485 | of a program linked as NewABI, the disassembly will follow the | |
4486 | register naming conventions specified by the user. */ | |
4487 | info->disassembler_options = "gpr-names=32"; | |
4488 | ||
c906108c | 4489 | /* Call the appropriate disassembler based on the target endian-ness. */ |
4c6b5505 | 4490 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
c906108c SS |
4491 | return print_insn_big_mips (memaddr, info); |
4492 | else | |
4493 | return print_insn_little_mips (memaddr, info); | |
4494 | } | |
4495 | ||
3b3b875c UW |
4496 | /* This function implements gdbarch_breakpoint_from_pc. It uses the program |
4497 | counter value to determine whether a 16- or 32-bit breakpoint should be used. | |
4498 | It returns a pointer to a string of bytes that encode a breakpoint | |
4499 | instruction, stores the length of the string to *lenptr, and adjusts pc (if | |
4500 | necessary) to point to the actual memory location where the breakpoint | |
4501 | should be inserted. */ | |
c906108c | 4502 | |
47a35522 | 4503 | static const gdb_byte * |
6d82d43b | 4504 | mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 4505 | { |
4c6b5505 | 4506 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 4507 | { |
0fe7e7c8 | 4508 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4509 | { |
47a35522 | 4510 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 4511 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4512 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
4513 | return mips16_big_breakpoint; |
4514 | } | |
4515 | else | |
4516 | { | |
aaab4dba AC |
4517 | /* The IDT board uses an unusual breakpoint value, and |
4518 | sometimes gets confused when it sees the usual MIPS | |
4519 | breakpoint instruction. */ | |
47a35522 MK |
4520 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
4521 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
4522 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 4523 | |
c5aa993b | 4524 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
4525 | |
4526 | if (strcmp (target_shortname, "mips") == 0) | |
4527 | return idt_big_breakpoint; | |
4528 | else if (strcmp (target_shortname, "ddb") == 0 | |
4529 | || strcmp (target_shortname, "pmon") == 0 | |
4530 | || strcmp (target_shortname, "lsi") == 0) | |
4531 | return pmon_big_breakpoint; | |
4532 | else | |
4533 | return big_breakpoint; | |
4534 | } | |
4535 | } | |
4536 | else | |
4537 | { | |
0fe7e7c8 | 4538 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4539 | { |
47a35522 | 4540 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 4541 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4542 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
4543 | return mips16_little_breakpoint; |
4544 | } | |
4545 | else | |
4546 | { | |
47a35522 MK |
4547 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
4548 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
4549 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 4550 | |
c5aa993b | 4551 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
4552 | |
4553 | if (strcmp (target_shortname, "mips") == 0) | |
4554 | return idt_little_breakpoint; | |
4555 | else if (strcmp (target_shortname, "ddb") == 0 | |
4556 | || strcmp (target_shortname, "pmon") == 0 | |
4557 | || strcmp (target_shortname, "lsi") == 0) | |
4558 | return pmon_little_breakpoint; | |
4559 | else | |
4560 | return little_breakpoint; | |
4561 | } | |
4562 | } | |
4563 | } | |
4564 | ||
4565 | /* If PC is in a mips16 call or return stub, return the address of the target | |
4566 | PC, which is either the callee or the caller. There are several | |
4567 | cases which must be handled: | |
4568 | ||
4569 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 4570 | target PC is in $31 ($ra). |
c906108c | 4571 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 4572 | and the target PC is in $2. |
c906108c | 4573 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
4574 | before the jal instruction, this is effectively a call stub |
4575 | and the the target PC is in $2. Otherwise this is effectively | |
4576 | a return stub and the target PC is in $18. | |
c906108c SS |
4577 | |
4578 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 4579 | gory details. */ |
c906108c | 4580 | |
757a7cc6 | 4581 | static CORE_ADDR |
52f729a7 | 4582 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c SS |
4583 | { |
4584 | char *name; | |
4585 | CORE_ADDR start_addr; | |
4586 | ||
4587 | /* Find the starting address and name of the function containing the PC. */ | |
4588 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
4589 | return 0; | |
4590 | ||
4591 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
4592 | target PC is in $31 ($ra). */ | |
4593 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
4594 | || strcmp (name, "__mips16_ret_df") == 0) | |
52f729a7 | 4595 | return get_frame_register_signed (frame, MIPS_RA_REGNUM); |
c906108c SS |
4596 | |
4597 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
4598 | { | |
4599 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
4600 | and the target PC is in $2. */ | |
4601 | if (name[19] >= '0' && name[19] <= '9') | |
52f729a7 | 4602 | return get_frame_register_signed (frame, 2); |
c906108c SS |
4603 | |
4604 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
4605 | before the jal instruction, this is effectively a call stub |
4606 | and the the target PC is in $2. Otherwise this is effectively | |
4607 | a return stub and the target PC is in $18. */ | |
c906108c SS |
4608 | else if (name[19] == 's' || name[19] == 'd') |
4609 | { | |
4610 | if (pc == start_addr) | |
4611 | { | |
4612 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
4613 | stub. Such a stub for a function bar might have a name |
4614 | like __fn_stub_bar, and might look like this: | |
4615 | mfc1 $4,$f13 | |
4616 | mfc1 $5,$f12 | |
4617 | mfc1 $6,$f15 | |
4618 | mfc1 $7,$f14 | |
4619 | la $1,bar (becomes a lui/addiu pair) | |
4620 | jr $1 | |
4621 | So scan down to the lui/addi and extract the target | |
4622 | address from those two instructions. */ | |
c906108c | 4623 | |
52f729a7 | 4624 | CORE_ADDR target_pc = get_frame_register_signed (frame, 2); |
d37cca3d | 4625 | ULONGEST inst; |
c906108c SS |
4626 | int i; |
4627 | ||
4628 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
4629 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
4630 | 0) | |
c906108c SS |
4631 | return target_pc; |
4632 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
4633 | && strcmp (name, "etext") != 0 | |
4634 | && strcmp (name, "_etext") != 0) | |
4635 | return target_pc; | |
4636 | ||
4637 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
4638 | The limit on the search is arbitrarily set to 20 |
4639 | instructions. FIXME. */ | |
95ac2dcf | 4640 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
c906108c | 4641 | { |
c5aa993b JM |
4642 | inst = mips_fetch_instruction (target_pc); |
4643 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
4644 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
4645 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
4646 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
4647 | } |
4648 | ||
4649 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
4650 | return target_pc; | |
4651 | } | |
4652 | else | |
4653 | /* This is the 'return' part of a call stub. The return | |
4654 | address is in $r18. */ | |
52f729a7 | 4655 | return get_frame_register_signed (frame, 18); |
c906108c SS |
4656 | } |
4657 | } | |
c5aa993b | 4658 | return 0; /* not a stub */ |
c906108c SS |
4659 | } |
4660 | ||
a4b8ebc8 | 4661 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 4662 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
4663 | |
4664 | static int | |
4665 | mips_stab_reg_to_regnum (int num) | |
4666 | { | |
a4b8ebc8 | 4667 | int regnum; |
2f38ef89 | 4668 | if (num >= 0 && num < 32) |
a4b8ebc8 | 4669 | regnum = num; |
2f38ef89 | 4670 | else if (num >= 38 && num < 70) |
56cea623 | 4671 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 4672 | else if (num == 70) |
56cea623 | 4673 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 4674 | else if (num == 71) |
56cea623 | 4675 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 4676 | else |
a4b8ebc8 AC |
4677 | /* This will hopefully (eventually) provoke a warning. Should |
4678 | we be calling complaint() here? */ | |
f57d151a UW |
4679 | return gdbarch_num_regs (current_gdbarch) |
4680 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4681 | return gdbarch_num_regs (current_gdbarch) + regnum; | |
88c72b7d AC |
4682 | } |
4683 | ||
2f38ef89 | 4684 | |
a4b8ebc8 | 4685 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 4686 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
4687 | |
4688 | static int | |
2f38ef89 | 4689 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 4690 | { |
a4b8ebc8 | 4691 | int regnum; |
2f38ef89 | 4692 | if (num >= 0 && num < 32) |
a4b8ebc8 | 4693 | regnum = num; |
2f38ef89 | 4694 | else if (num >= 32 && num < 64) |
56cea623 | 4695 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 4696 | else if (num == 64) |
56cea623 | 4697 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 4698 | else if (num == 65) |
56cea623 | 4699 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 4700 | else |
a4b8ebc8 AC |
4701 | /* This will hopefully (eventually) provoke a warning. Should we |
4702 | be calling complaint() here? */ | |
f57d151a UW |
4703 | return gdbarch_num_regs (current_gdbarch) |
4704 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4705 | return gdbarch_num_regs (current_gdbarch) + regnum; | |
a4b8ebc8 AC |
4706 | } |
4707 | ||
4708 | static int | |
4709 | mips_register_sim_regno (int regnum) | |
4710 | { | |
4711 | /* Only makes sense to supply raw registers. */ | |
f57d151a | 4712 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch)); |
a4b8ebc8 AC |
4713 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
4714 | decide if it is valid. Should instead define a standard sim/gdb | |
4715 | register numbering scheme. */ | |
c9f4d572 UW |
4716 | if (gdbarch_register_name (current_gdbarch, |
4717 | gdbarch_num_regs | |
4718 | (current_gdbarch) + regnum) != NULL | |
4719 | && gdbarch_register_name (current_gdbarch, | |
4720 | gdbarch_num_regs | |
4721 | (current_gdbarch) + regnum)[0] != '\0') | |
a4b8ebc8 AC |
4722 | return regnum; |
4723 | else | |
6d82d43b | 4724 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
4725 | } |
4726 | ||
2f38ef89 | 4727 | |
4844f454 CV |
4728 | /* Convert an integer into an address. Extracting the value signed |
4729 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
4730 | |
4731 | static CORE_ADDR | |
79dd2d24 | 4732 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 4733 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 4734 | { |
4844f454 | 4735 | return (CORE_ADDR) extract_signed_integer (buf, TYPE_LENGTH (type)); |
fc0c74b1 AC |
4736 | } |
4737 | ||
caaa3122 DJ |
4738 | static void |
4739 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
4740 | { | |
4741 | enum mips_abi *abip = (enum mips_abi *) obj; | |
4742 | const char *name = bfd_get_section_name (abfd, sect); | |
4743 | ||
4744 | if (*abip != MIPS_ABI_UNKNOWN) | |
4745 | return; | |
4746 | ||
4747 | if (strncmp (name, ".mdebug.", 8) != 0) | |
4748 | return; | |
4749 | ||
4750 | if (strcmp (name, ".mdebug.abi32") == 0) | |
4751 | *abip = MIPS_ABI_O32; | |
4752 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
4753 | *abip = MIPS_ABI_N32; | |
62a49b2c | 4754 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 4755 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
4756 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
4757 | *abip = MIPS_ABI_O64; | |
4758 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
4759 | *abip = MIPS_ABI_EABI32; | |
4760 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
4761 | *abip = MIPS_ABI_EABI64; | |
4762 | else | |
8a3fe4f8 | 4763 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
4764 | } |
4765 | ||
22e47e37 FF |
4766 | static void |
4767 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
4768 | { | |
4769 | int *lbp = (int *) obj; | |
4770 | const char *name = bfd_get_section_name (abfd, sect); | |
4771 | ||
4772 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
4773 | *lbp = 32; | |
4774 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
4775 | *lbp = 64; | |
4776 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
4777 | warning (_("unrecognized .gcc_compiled_longXX")); | |
4778 | } | |
4779 | ||
2e4ebe70 DJ |
4780 | static enum mips_abi |
4781 | global_mips_abi (void) | |
4782 | { | |
4783 | int i; | |
4784 | ||
4785 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
4786 | if (mips_abi_strings[i] == mips_abi_string) | |
4787 | return (enum mips_abi) i; | |
4788 | ||
e2e0b3e5 | 4789 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
4790 | } |
4791 | ||
29709017 DJ |
4792 | static void |
4793 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
4794 | { | |
4795 | static struct target_desc *tdesc_gp32, *tdesc_gp64; | |
4796 | ||
4797 | if (tdesc_gp32 == NULL) | |
4798 | { | |
4799 | /* Create feature sets with the appropriate properties. The values | |
4800 | are not important. */ | |
4801 | ||
4802 | tdesc_gp32 = allocate_target_description (); | |
4803 | set_tdesc_property (tdesc_gp32, PROPERTY_GP32, ""); | |
4804 | ||
4805 | tdesc_gp64 = allocate_target_description (); | |
4806 | set_tdesc_property (tdesc_gp64, PROPERTY_GP64, ""); | |
4807 | } | |
4808 | ||
4809 | /* If the size matches the set of 32-bit or 64-bit integer registers, | |
4810 | assume that's what we've got. */ | |
4811 | register_remote_g_packet_guess (gdbarch, 38 * 4, tdesc_gp32); | |
4812 | register_remote_g_packet_guess (gdbarch, 38 * 8, tdesc_gp64); | |
4813 | ||
4814 | /* If the size matches the full set of registers GDB traditionally | |
4815 | knows about, including floating point, for either 32-bit or | |
4816 | 64-bit, assume that's what we've got. */ | |
4817 | register_remote_g_packet_guess (gdbarch, 90 * 4, tdesc_gp32); | |
4818 | register_remote_g_packet_guess (gdbarch, 90 * 8, tdesc_gp64); | |
4819 | ||
4820 | /* Otherwise we don't have a useful guess. */ | |
4821 | } | |
4822 | ||
f8b73d13 DJ |
4823 | static struct value * |
4824 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
4825 | { | |
4826 | const int *reg_p = baton; | |
4827 | return value_of_register (*reg_p, frame); | |
4828 | } | |
4829 | ||
c2d11a7d | 4830 | static struct gdbarch * |
6d82d43b | 4831 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 4832 | { |
c2d11a7d JM |
4833 | struct gdbarch *gdbarch; |
4834 | struct gdbarch_tdep *tdep; | |
4835 | int elf_flags; | |
2e4ebe70 | 4836 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 4837 | int i, num_regs; |
8d5838b5 | 4838 | enum mips_fpu_type fpu_type; |
f8b73d13 DJ |
4839 | struct tdesc_arch_data *tdesc_data = NULL; |
4840 | ||
4841 | /* Check any target description for validity. */ | |
4842 | if (tdesc_has_registers (info.target_desc)) | |
4843 | { | |
4844 | static const char *const mips_gprs[] = { | |
4845 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
4846 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
4847 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
4848 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
4849 | }; | |
4850 | static const char *const mips_fprs[] = { | |
4851 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
4852 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
4853 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
4854 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
4855 | }; | |
4856 | ||
4857 | const struct tdesc_feature *feature; | |
4858 | int valid_p; | |
4859 | ||
4860 | feature = tdesc_find_feature (info.target_desc, | |
4861 | "org.gnu.gdb.mips.cpu"); | |
4862 | if (feature == NULL) | |
4863 | return NULL; | |
4864 | ||
4865 | tdesc_data = tdesc_data_alloc (); | |
4866 | ||
4867 | valid_p = 1; | |
4868 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
4869 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
4870 | mips_gprs[i]); | |
4871 | ||
4872 | ||
4873 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4874 | MIPS_EMBED_LO_REGNUM, "lo"); | |
4875 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4876 | MIPS_EMBED_HI_REGNUM, "hi"); | |
4877 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4878 | MIPS_EMBED_PC_REGNUM, "pc"); | |
4879 | ||
4880 | if (!valid_p) | |
4881 | { | |
4882 | tdesc_data_cleanup (tdesc_data); | |
4883 | return NULL; | |
4884 | } | |
4885 | ||
4886 | feature = tdesc_find_feature (info.target_desc, | |
4887 | "org.gnu.gdb.mips.cp0"); | |
4888 | if (feature == NULL) | |
4889 | { | |
4890 | tdesc_data_cleanup (tdesc_data); | |
4891 | return NULL; | |
4892 | } | |
4893 | ||
4894 | valid_p = 1; | |
4895 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4896 | MIPS_EMBED_BADVADDR_REGNUM, | |
4897 | "badvaddr"); | |
4898 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4899 | MIPS_PS_REGNUM, "status"); | |
4900 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4901 | MIPS_EMBED_CAUSE_REGNUM, "cause"); | |
4902 | ||
4903 | if (!valid_p) | |
4904 | { | |
4905 | tdesc_data_cleanup (tdesc_data); | |
4906 | return NULL; | |
4907 | } | |
4908 | ||
4909 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
4910 | backend is not prepared for that, though. */ | |
4911 | feature = tdesc_find_feature (info.target_desc, | |
4912 | "org.gnu.gdb.mips.fpu"); | |
4913 | if (feature == NULL) | |
4914 | { | |
4915 | tdesc_data_cleanup (tdesc_data); | |
4916 | return NULL; | |
4917 | } | |
4918 | ||
4919 | valid_p = 1; | |
4920 | for (i = 0; i < 32; i++) | |
4921 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4922 | i + MIPS_EMBED_FP0_REGNUM, | |
4923 | mips_fprs[i]); | |
4924 | ||
4925 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4926 | MIPS_EMBED_FP0_REGNUM + 32, "fcsr"); | |
4927 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4928 | MIPS_EMBED_FP0_REGNUM + 33, "fir"); | |
4929 | ||
4930 | if (!valid_p) | |
4931 | { | |
4932 | tdesc_data_cleanup (tdesc_data); | |
4933 | return NULL; | |
4934 | } | |
4935 | ||
4936 | /* It would be nice to detect an attempt to use a 64-bit ABI | |
4937 | when only 32-bit registers are provided. */ | |
4938 | } | |
c2d11a7d | 4939 | |
ec03c1ac AC |
4940 | /* First of all, extract the elf_flags, if available. */ |
4941 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
4942 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
4943 | else if (arches != NULL) |
4944 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
4945 | else |
4946 | elf_flags = 0; | |
4947 | if (gdbarch_debug) | |
4948 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 4949 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 4950 | |
102182a9 | 4951 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
4952 | switch ((elf_flags & EF_MIPS_ABI)) |
4953 | { | |
4954 | case E_MIPS_ABI_O32: | |
ec03c1ac | 4955 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
4956 | break; |
4957 | case E_MIPS_ABI_O64: | |
ec03c1ac | 4958 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
4959 | break; |
4960 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 4961 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
4962 | break; |
4963 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 4964 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
4965 | break; |
4966 | default: | |
acdb74a0 | 4967 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 4968 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 4969 | else |
ec03c1ac | 4970 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
4971 | break; |
4972 | } | |
acdb74a0 | 4973 | |
caaa3122 | 4974 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
4975 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
4976 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 4977 | |
dc305454 | 4978 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
4979 | MIPS architecture (if there is one). */ |
4980 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
4981 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 4982 | |
32a6503c | 4983 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 4984 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
4985 | && info.bfd_arch_info != NULL |
4986 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
4987 | { | |
4988 | switch (info.bfd_arch_info->mach) | |
4989 | { | |
4990 | case bfd_mach_mips3900: | |
ec03c1ac | 4991 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
4992 | break; |
4993 | case bfd_mach_mips4100: | |
4994 | case bfd_mach_mips5000: | |
ec03c1ac | 4995 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 4996 | break; |
1d06468c EZ |
4997 | case bfd_mach_mips8000: |
4998 | case bfd_mach_mips10000: | |
32a6503c KB |
4999 | /* On Irix, ELF64 executables use the N64 ABI. The |
5000 | pseudo-sections which describe the ABI aren't present | |
5001 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5002 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5003 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5004 | found_abi = MIPS_ABI_N64; |
28d169de | 5005 | else |
ec03c1ac | 5006 | found_abi = MIPS_ABI_N32; |
1d06468c | 5007 | break; |
bf64bfd6 AC |
5008 | } |
5009 | } | |
2e4ebe70 | 5010 | |
26c53e50 DJ |
5011 | /* Default 64-bit objects to N64 instead of O32. */ |
5012 | if (found_abi == MIPS_ABI_UNKNOWN | |
5013 | && info.abfd != NULL | |
5014 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
5015 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5016 | found_abi = MIPS_ABI_N64; | |
5017 | ||
ec03c1ac AC |
5018 | if (gdbarch_debug) |
5019 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5020 | found_abi); | |
5021 | ||
5022 | /* What has the user specified from the command line? */ | |
5023 | wanted_abi = global_mips_abi (); | |
5024 | if (gdbarch_debug) | |
5025 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5026 | wanted_abi); | |
2e4ebe70 DJ |
5027 | |
5028 | /* Now that we have found what the ABI for this binary would be, | |
5029 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5030 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5031 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5032 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5033 | mips_abi = found_abi; | |
5034 | else | |
5035 | mips_abi = MIPS_ABI_O32; | |
5036 | if (gdbarch_debug) | |
5037 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5038 | mips_abi); | |
2e4ebe70 | 5039 | |
ec03c1ac | 5040 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5041 | if (gdbarch_debug) |
ec03c1ac AC |
5042 | fprintf_unfiltered (gdb_stdlog, |
5043 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
5044 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 5045 | |
8d5838b5 AC |
5046 | /* Determine the MIPS FPU type. */ |
5047 | if (!mips_fpu_type_auto) | |
5048 | fpu_type = mips_fpu_type; | |
5049 | else if (info.bfd_arch_info != NULL | |
5050 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5051 | switch (info.bfd_arch_info->mach) | |
5052 | { | |
5053 | case bfd_mach_mips3900: | |
5054 | case bfd_mach_mips4100: | |
5055 | case bfd_mach_mips4111: | |
a9d61c86 | 5056 | case bfd_mach_mips4120: |
8d5838b5 AC |
5057 | fpu_type = MIPS_FPU_NONE; |
5058 | break; | |
5059 | case bfd_mach_mips4650: | |
5060 | fpu_type = MIPS_FPU_SINGLE; | |
5061 | break; | |
5062 | default: | |
5063 | fpu_type = MIPS_FPU_DOUBLE; | |
5064 | break; | |
5065 | } | |
5066 | else if (arches != NULL) | |
5067 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5068 | else | |
5069 | fpu_type = MIPS_FPU_DOUBLE; | |
5070 | if (gdbarch_debug) | |
5071 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5072 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5073 | |
29709017 DJ |
5074 | /* Check for blatant incompatibilities. */ |
5075 | ||
5076 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
5077 | ABI. */ | |
5078 | if (info.target_desc | |
5079 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
5080 | && mips_abi != MIPS_ABI_EABI32 | |
5081 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
5082 | { |
5083 | if (tdesc_data != NULL) | |
5084 | tdesc_data_cleanup (tdesc_data); | |
5085 | return NULL; | |
5086 | } | |
29709017 | 5087 | |
c2d11a7d JM |
5088 | /* try to find a pre-existing architecture */ |
5089 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5090 | arches != NULL; | |
5091 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5092 | { | |
5093 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5094 | using. */ |
9103eae0 | 5095 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5096 | continue; |
9103eae0 | 5097 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5098 | continue; |
719ec221 AC |
5099 | /* Need to be pedantic about which register virtual size is |
5100 | used. */ | |
5101 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5102 | != mips64_transfers_32bit_regs_p) | |
5103 | continue; | |
8d5838b5 AC |
5104 | /* Be pedantic about which FPU is selected. */ |
5105 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5106 | continue; | |
f8b73d13 DJ |
5107 | |
5108 | if (tdesc_data != NULL) | |
5109 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 5110 | return arches->gdbarch; |
c2d11a7d JM |
5111 | } |
5112 | ||
102182a9 | 5113 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5114 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5115 | gdbarch = gdbarch_alloc (&info, tdep); | |
5116 | tdep->elf_flags = elf_flags; | |
719ec221 | 5117 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5118 | tdep->found_abi = found_abi; |
5119 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5120 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
5121 | tdep->register_size_valid_p = 0; |
5122 | tdep->register_size = 0; | |
5123 | ||
5124 | if (info.target_desc) | |
5125 | { | |
5126 | /* Some useful properties can be inferred from the target. */ | |
5127 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
5128 | { | |
5129 | tdep->register_size_valid_p = 1; | |
5130 | tdep->register_size = 4; | |
5131 | } | |
5132 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
5133 | { | |
5134 | tdep->register_size_valid_p = 1; | |
5135 | tdep->register_size = 8; | |
5136 | } | |
5137 | } | |
c2d11a7d | 5138 | |
102182a9 | 5139 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5140 | set_gdbarch_short_bit (gdbarch, 16); |
5141 | set_gdbarch_int_bit (gdbarch, 32); | |
5142 | set_gdbarch_float_bit (gdbarch, 32); | |
5143 | set_gdbarch_double_bit (gdbarch, 64); | |
5144 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5145 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5146 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5147 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5148 | |
6d82d43b | 5149 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
5150 | mips_elf_make_msymbol_special); |
5151 | ||
16e109ca | 5152 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5153 | { |
16e109ca | 5154 | const char **reg_names; |
56cea623 AC |
5155 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5156 | struct mips_regnum); | |
f8b73d13 DJ |
5157 | if (tdesc_has_registers (info.target_desc)) |
5158 | { | |
5159 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5160 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5161 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5162 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5163 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5164 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5165 | regnum->fp_control_status = 70; | |
5166 | regnum->fp_implementation_revision = 71; | |
5167 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
5168 | reg_names = NULL; | |
5169 | } | |
5170 | else if (info.osabi == GDB_OSABI_IRIX) | |
56cea623 AC |
5171 | { |
5172 | regnum->fp0 = 32; | |
5173 | regnum->pc = 64; | |
5174 | regnum->cause = 65; | |
5175 | regnum->badvaddr = 66; | |
5176 | regnum->hi = 67; | |
5177 | regnum->lo = 68; | |
5178 | regnum->fp_control_status = 69; | |
5179 | regnum->fp_implementation_revision = 70; | |
5180 | num_regs = 71; | |
16e109ca | 5181 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5182 | } |
5183 | else | |
5184 | { | |
5185 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5186 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5187 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5188 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5189 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5190 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5191 | regnum->fp_control_status = 70; | |
5192 | regnum->fp_implementation_revision = 71; | |
5193 | num_regs = 90; | |
16e109ca AC |
5194 | if (info.bfd_arch_info != NULL |
5195 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5196 | reg_names = mips_tx39_reg_names; | |
5197 | else | |
5198 | reg_names = mips_generic_reg_names; | |
56cea623 | 5199 | } |
3e8c568d | 5200 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been |
56cea623 | 5201 | replaced by read_pc? */ |
f10683bb MH |
5202 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
5203 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
5204 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
5205 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5206 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca AC |
5207 | set_gdbarch_register_name (gdbarch, mips_register_name); |
5208 | tdep->mips_processor_reg_names = reg_names; | |
5209 | tdep->regnum = regnum; | |
56cea623 | 5210 | } |
fe29b929 | 5211 | |
0dadbba0 | 5212 | switch (mips_abi) |
c2d11a7d | 5213 | { |
0dadbba0 | 5214 | case MIPS_ABI_O32: |
25ab4790 | 5215 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5216 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 5217 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5218 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5219 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5220 | set_gdbarch_long_bit (gdbarch, 32); |
5221 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5222 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5223 | break; | |
0dadbba0 | 5224 | case MIPS_ABI_O64: |
25ab4790 | 5225 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 5226 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 5227 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5228 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5229 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5230 | set_gdbarch_long_bit (gdbarch, 32); |
5231 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5232 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5233 | break; | |
0dadbba0 | 5234 | case MIPS_ABI_EABI32: |
25ab4790 | 5235 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5236 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5237 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5238 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5239 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5240 | set_gdbarch_long_bit (gdbarch, 32); |
5241 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5242 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5243 | break; | |
0dadbba0 | 5244 | case MIPS_ABI_EABI64: |
25ab4790 | 5245 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5246 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5247 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5248 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5249 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5250 | set_gdbarch_long_bit (gdbarch, 64); |
5251 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5252 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5253 | break; | |
0dadbba0 | 5254 | case MIPS_ABI_N32: |
25ab4790 | 5255 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5256 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5257 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5258 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5259 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5260 | set_gdbarch_long_bit (gdbarch, 32); |
5261 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5262 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5263 | set_gdbarch_long_double_bit (gdbarch, 128); |
8da61cc4 | 5264 | set_gdbarch_long_double_format (gdbarch, floatformats_n32n64_long); |
28d169de KB |
5265 | break; |
5266 | case MIPS_ABI_N64: | |
25ab4790 | 5267 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5268 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5269 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5270 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5271 | tdep->default_mask_address_p = 0; |
5272 | set_gdbarch_long_bit (gdbarch, 64); | |
5273 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5274 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5275 | set_gdbarch_long_double_bit (gdbarch, 128); |
8da61cc4 | 5276 | set_gdbarch_long_double_format (gdbarch, floatformats_n32n64_long); |
0dadbba0 | 5277 | break; |
c2d11a7d | 5278 | default: |
e2e0b3e5 | 5279 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
5280 | } |
5281 | ||
22e47e37 FF |
5282 | /* GCC creates a pseudo-section whose name specifies the size of |
5283 | longs, since -mlong32 or -mlong64 may be used independent of | |
5284 | other options. How those options affect pointer sizes is ABI and | |
5285 | architecture dependent, so use them to override the default sizes | |
5286 | set by the ABI. This table shows the relationship between ABI, | |
5287 | -mlongXX, and size of pointers: | |
5288 | ||
5289 | ABI -mlongXX ptr bits | |
5290 | --- -------- -------- | |
5291 | o32 32 32 | |
5292 | o32 64 32 | |
5293 | n32 32 32 | |
5294 | n32 64 64 | |
5295 | o64 32 32 | |
5296 | o64 64 64 | |
5297 | n64 32 32 | |
5298 | n64 64 64 | |
5299 | eabi32 32 32 | |
5300 | eabi32 64 32 | |
5301 | eabi64 32 32 | |
5302 | eabi64 64 64 | |
5303 | ||
5304 | Note that for o32 and eabi32, pointers are always 32 bits | |
5305 | regardless of any -mlongXX option. For all others, pointers and | |
5306 | longs are the same, as set by -mlongXX or set by defaults. | |
5307 | */ | |
5308 | ||
5309 | if (info.abfd != NULL) | |
5310 | { | |
5311 | int long_bit = 0; | |
5312 | ||
5313 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
5314 | if (long_bit) | |
5315 | { | |
5316 | set_gdbarch_long_bit (gdbarch, long_bit); | |
5317 | switch (mips_abi) | |
5318 | { | |
5319 | case MIPS_ABI_O32: | |
5320 | case MIPS_ABI_EABI32: | |
5321 | break; | |
5322 | case MIPS_ABI_N32: | |
5323 | case MIPS_ABI_O64: | |
5324 | case MIPS_ABI_N64: | |
5325 | case MIPS_ABI_EABI64: | |
5326 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
5327 | break; | |
5328 | default: | |
5329 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
5330 | } | |
5331 | } | |
5332 | } | |
5333 | ||
a5ea2558 AC |
5334 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5335 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5336 | comment: | |
5337 | ||
5338 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5339 | flag in object files because to do so would make it impossible to | |
102182a9 | 5340 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5341 | unnecessarily restrictive. |
361d1df0 | 5342 | |
a5ea2558 AC |
5343 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5344 | but to set this flag before gcc is built with such multilibs will | |
5345 | break too many systems.'' | |
5346 | ||
5347 | But even more unhelpfully, the default linker output target for | |
5348 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5349 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5350 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5351 | this flag to detect 32-bit mode would do the wrong thing given |
5352 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5353 | as 32-bit programs by default. */ |
a5ea2558 | 5354 | |
6c997a34 | 5355 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 5356 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 5357 | |
102182a9 MS |
5358 | /* Add/remove bits from an address. The MIPS needs be careful to |
5359 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5360 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5361 | ||
58dfe9ff AC |
5362 | /* Unwind the frame. */ |
5363 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 5364 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
edfae063 | 5365 | set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id); |
10312cc4 | 5366 | |
102182a9 | 5367 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5368 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
5369 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
5370 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5371 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, | |
5372 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5373 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, | |
5374 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5375 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5376 | |
c2d11a7d JM |
5377 | /* MIPS version of CALL_DUMMY */ |
5378 | ||
9710e734 AC |
5379 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
5380 | replaced by a command, and all targets will default to on stack | |
5381 | (regardless of the stack's execute status). */ | |
5382 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 5383 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 5384 | |
87783b8b AC |
5385 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
5386 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
5387 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
5388 | ||
f7b9e9fc AC |
5389 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5390 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
5391 | |
5392 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 5393 | |
fc0c74b1 AC |
5394 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5395 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5396 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5397 | |
a4b8ebc8 | 5398 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 5399 | |
e11c53d2 | 5400 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 5401 | |
e5ab0dce AC |
5402 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
5403 | ||
3a3bc038 AC |
5404 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
5405 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
5406 | need to all be folded into the target vector. Since they are | |
5407 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
5408 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
5409 | is sitting on? */ | |
5410 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
5411 | ||
e7d6a6d2 | 5412 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 5413 | |
3352ef37 AC |
5414 | set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay); |
5415 | ||
0d5de010 DJ |
5416 | /* Virtual tables. */ |
5417 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
5418 | ||
29709017 DJ |
5419 | mips_register_g_packet_guesses (gdbarch); |
5420 | ||
6de918a6 | 5421 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 5422 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 5423 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 5424 | |
5792a79b | 5425 | /* Unwind the frame. */ |
2bd0c3d7 | 5426 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
eec63939 | 5427 | frame_unwind_append_sniffer (gdbarch, mips_stub_frame_sniffer); |
45c9dd44 AC |
5428 | frame_unwind_append_sniffer (gdbarch, mips_insn16_frame_sniffer); |
5429 | frame_unwind_append_sniffer (gdbarch, mips_insn32_frame_sniffer); | |
2bd0c3d7 | 5430 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 5431 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
5432 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
5433 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 5434 | |
f8b73d13 DJ |
5435 | if (tdesc_data) |
5436 | { | |
5437 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
5438 | tdesc_use_registers (gdbarch, tdesc_data); | |
5439 | ||
5440 | /* Override the normal target description methods to handle our | |
5441 | dual real and pseudo registers. */ | |
5442 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
5443 | set_gdbarch_register_reggroup_p (gdbarch, mips_tdesc_register_reggroup_p); | |
5444 | ||
5445 | num_regs = gdbarch_num_regs (gdbarch); | |
5446 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
5447 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
5448 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
5449 | } | |
5450 | ||
5451 | /* Add ABI-specific aliases for the registers. */ | |
5452 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
5453 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
5454 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
5455 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
5456 | else | |
5457 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
5458 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
5459 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
5460 | ||
5461 | /* Add some other standard aliases. */ | |
5462 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
5463 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
5464 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
5465 | ||
4b9b3959 AC |
5466 | return gdbarch; |
5467 | } | |
5468 | ||
2e4ebe70 | 5469 | static void |
6d82d43b | 5470 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
5471 | { |
5472 | struct gdbarch_info info; | |
5473 | ||
5474 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
5475 | mips_gdbarch_init will take care of the rest. */ | |
5476 | gdbarch_info_init (&info); | |
5477 | gdbarch_update_p (info); | |
5478 | } | |
5479 | ||
ad188201 KB |
5480 | /* Print out which MIPS ABI is in use. */ |
5481 | ||
5482 | static void | |
1f8ca57c JB |
5483 | show_mips_abi (struct ui_file *file, |
5484 | int from_tty, | |
5485 | struct cmd_list_element *ignored_cmd, | |
5486 | const char *ignored_value) | |
ad188201 KB |
5487 | { |
5488 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
1f8ca57c JB |
5489 | fprintf_filtered |
5490 | (file, | |
5491 | "The MIPS ABI is unknown because the current architecture " | |
5492 | "is not MIPS.\n"); | |
ad188201 KB |
5493 | else |
5494 | { | |
5495 | enum mips_abi global_abi = global_mips_abi (); | |
5496 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
5497 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
5498 | ||
5499 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
5500 | fprintf_filtered |
5501 | (file, | |
5502 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 5503 | actual_abi_str); |
ad188201 | 5504 | else if (global_abi == actual_abi) |
1f8ca57c JB |
5505 | fprintf_filtered |
5506 | (file, | |
5507 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 5508 | actual_abi_str); |
ad188201 KB |
5509 | else |
5510 | { | |
5511 | /* Probably shouldn't happen... */ | |
1f8ca57c JB |
5512 | fprintf_filtered |
5513 | (file, | |
5514 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6d82d43b | 5515 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
5516 | } |
5517 | } | |
5518 | } | |
5519 | ||
4b9b3959 AC |
5520 | static void |
5521 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
5522 | { | |
5523 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
5524 | if (tdep != NULL) | |
c2d11a7d | 5525 | { |
acdb74a0 AC |
5526 | int ef_mips_arch; |
5527 | int ef_mips_32bitmode; | |
f49e4e6d | 5528 | /* Determine the ISA. */ |
acdb74a0 AC |
5529 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
5530 | { | |
5531 | case E_MIPS_ARCH_1: | |
5532 | ef_mips_arch = 1; | |
5533 | break; | |
5534 | case E_MIPS_ARCH_2: | |
5535 | ef_mips_arch = 2; | |
5536 | break; | |
5537 | case E_MIPS_ARCH_3: | |
5538 | ef_mips_arch = 3; | |
5539 | break; | |
5540 | case E_MIPS_ARCH_4: | |
93d56215 | 5541 | ef_mips_arch = 4; |
acdb74a0 AC |
5542 | break; |
5543 | default: | |
93d56215 | 5544 | ef_mips_arch = 0; |
acdb74a0 AC |
5545 | break; |
5546 | } | |
f49e4e6d | 5547 | /* Determine the size of a pointer. */ |
acdb74a0 | 5548 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
5549 | fprintf_unfiltered (file, |
5550 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 5551 | tdep->elf_flags); |
4b9b3959 | 5552 | fprintf_unfiltered (file, |
acdb74a0 AC |
5553 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
5554 | ef_mips_32bitmode); | |
5555 | fprintf_unfiltered (file, | |
5556 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
5557 | ef_mips_arch); | |
5558 | fprintf_unfiltered (file, | |
5559 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 5560 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
5561 | fprintf_unfiltered (file, |
5562 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 5563 | mips_mask_address_p (tdep), |
4014092b | 5564 | tdep->default_mask_address_p); |
c2d11a7d | 5565 | } |
4b9b3959 AC |
5566 | fprintf_unfiltered (file, |
5567 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
5568 | MIPS_DEFAULT_FPU_TYPE, | |
5569 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5570 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5571 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5572 | : "???")); | |
6d82d43b | 5573 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI); |
4b9b3959 AC |
5574 | fprintf_unfiltered (file, |
5575 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
5576 | MIPS_FPU_TYPE, | |
5577 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5578 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5579 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5580 | : "???")); | |
c2d11a7d JM |
5581 | } |
5582 | ||
6d82d43b | 5583 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 5584 | |
c906108c | 5585 | void |
acdb74a0 | 5586 | _initialize_mips_tdep (void) |
c906108c SS |
5587 | { |
5588 | static struct cmd_list_element *mipsfpulist = NULL; | |
5589 | struct cmd_list_element *c; | |
5590 | ||
6d82d43b | 5591 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
5592 | if (MIPS_ABI_LAST + 1 |
5593 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 5594 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 5595 | |
4b9b3959 | 5596 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 5597 | |
8d5f9dcb DJ |
5598 | mips_pdr_data = register_objfile_data (); |
5599 | ||
a5ea2558 AC |
5600 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
5601 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
1bedd215 | 5602 | _("Various MIPS specific commands."), |
a5ea2558 AC |
5603 | &setmipscmdlist, "set mips ", 0, &setlist); |
5604 | ||
5605 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 5606 | _("Various MIPS specific commands."), |
a5ea2558 AC |
5607 | &showmipscmdlist, "show mips ", 0, &showlist); |
5608 | ||
2e4ebe70 | 5609 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
5610 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
5611 | &mips_abi_string, _("\ | |
5612 | Set the MIPS ABI used by this program."), _("\ | |
5613 | Show the MIPS ABI used by this program."), _("\ | |
5614 | This option can be set to one of:\n\ | |
5615 | auto - the default ABI associated with the current binary\n\ | |
5616 | o32\n\ | |
5617 | o64\n\ | |
5618 | n32\n\ | |
5619 | n64\n\ | |
5620 | eabi32\n\ | |
5621 | eabi64"), | |
5622 | mips_abi_update, | |
5623 | show_mips_abi, | |
5624 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 5625 | |
c906108c SS |
5626 | /* Let the user turn off floating point and set the fence post for |
5627 | heuristic_proc_start. */ | |
5628 | ||
5629 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 5630 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
5631 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
5632 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 5633 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
5634 | &mipsfpulist); |
5635 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 5636 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
5637 | &mipsfpulist); |
5638 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
5639 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
5640 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
5641 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 5642 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
5643 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
5644 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
5645 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
5646 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 5647 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
5648 | &mipsfpulist); |
5649 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 5650 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
5651 | &showlist); |
5652 | ||
c906108c SS |
5653 | /* We really would like to have both "0" and "unlimited" work, but |
5654 | command.c doesn't deal with that. So make it a var_zinteger | |
5655 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 5656 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
5657 | &heuristic_fence_post, _("\ |
5658 | Set the distance searched for the start of a function."), _("\ | |
5659 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
5660 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
5661 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 5662 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 5663 | reinit_frame_cache_sfunc, |
7915a72c | 5664 | NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */ |
6bcadd06 | 5665 | &setlist, &showlist); |
c906108c SS |
5666 | |
5667 | /* Allow the user to control whether the upper bits of 64-bit | |
5668 | addresses should be zeroed. */ | |
7915a72c AC |
5669 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
5670 | &mask_address_var, _("\ | |
5671 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
5672 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
e9e68a56 | 5673 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ |
7915a72c | 5674 | allow GDB to determine the correct value."), |
08546159 AC |
5675 | NULL, show_mask_address, |
5676 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
5677 | |
5678 | /* Allow the user to control the size of 32 bit registers within the | |
5679 | raw remote packet. */ | |
b3f42336 | 5680 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
5681 | &mips64_transfers_32bit_regs_p, _("\ |
5682 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
5683 | _("\ | |
5684 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
5685 | _("\ | |
719ec221 AC |
5686 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
5687 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 5688 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 5689 | set_mips64_transfers_32bit_regs, |
7915a72c | 5690 | NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */ |
7915a72c | 5691 | &setlist, &showlist); |
9ace0497 AC |
5692 | |
5693 | /* Debug this files internals. */ | |
6bcadd06 | 5694 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
5695 | &mips_debug, _("\ |
5696 | Set mips debugging."), _("\ | |
5697 | Show mips debugging."), _("\ | |
5698 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 5699 | NULL, |
7915a72c | 5700 | NULL, /* FIXME: i18n: Mips debugging is currently %s. */ |
6bcadd06 | 5701 | &setdebuglist, &showdebuglist); |
c906108c | 5702 | } |