[deliverable/binutils-gdb.git] / gdb / mips-tdep.h

/* Target-dependent header for the MIPS architecture, for GDB, the GNU Debugger.

   Copyright (C) 2002-2016 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef MIPS_TDEP_H
#define MIPS_TDEP_H

#include "objfiles.h"

struct gdbarch;

/* All the possible MIPS ABIs.  */
enum mips_abi
  {
    MIPS_ABI_UNKNOWN = 0,
    MIPS_ABI_N32,
    MIPS_ABI_O32,
    MIPS_ABI_N64,
    MIPS_ABI_O64,
    MIPS_ABI_EABI32,
    MIPS_ABI_EABI64,
    MIPS_ABI_LAST
  };

/* Return the MIPS ABI associated with GDBARCH.  */
enum mips_abi mips_abi (struct gdbarch *gdbarch);

/* Base and compressed MIPS ISA variations.  */
enum mips_isa
  {
    ISA_MIPS = -1,		/* mips_compression_string depends on it.  */
    ISA_MIPS16,
    ISA_MICROMIPS
  };

/* Corresponding MSYMBOL_TARGET_FLAG aliases.  */
#define MSYMBOL_TARGET_FLAG_MIPS16 MSYMBOL_TARGET_FLAG_1
#define MSYMBOL_TARGET_FLAG_MICROMIPS MSYMBOL_TARGET_FLAG_2

/* Return the MIPS ISA's register size.  Just a short cut to the BFD
   architecture's word size.  */
extern int mips_isa_regsize (struct gdbarch *gdbarch);

/* Return the current index for various MIPS registers.  */
struct mips_regnum
{
  int pc;
  int fp0;
  int fp_implementation_revision;
  int fp_control_status;
  int badvaddr;		/* Bad vaddr for addressing exception.  */
  int cause;		/* Describes last exception.  */
  int hi;		/* Multiply/divide temp.  */
  int lo;		/* ...  */
  int dspacc;		/* SmartMIPS/DSP accumulators.  */
  int dspctl;		/* DSP control.  */
};
extern const struct mips_regnum *mips_regnum (struct gdbarch *gdbarch);

/* Some MIPS boards don't support floating point while others only
   support single-precision floating-point operations.  */

enum mips_fpu_type
{
  MIPS_FPU_DOUBLE,		/* Full double precision floating point.  */
  MIPS_FPU_SINGLE,		/* Single precision floating point (R4650).  */
  MIPS_FPU_NONE			/* No floating point.  */
};

/* MIPS specific per-architecture information.  */
struct gdbarch_tdep
{
  /* from the elf header */
  int elf_flags;

  /* mips options */
  enum mips_abi mips_abi;
  enum mips_abi found_abi;
  enum mips_isa mips_isa;
  enum mips_fpu_type mips_fpu_type;
  int mips_last_arg_regnum;
  int mips_last_fp_arg_regnum;
  int default_mask_address_p;
  /* Is the target using 64-bit raw integer registers but only
     storing a left-aligned 32-bit value in each?  */
  int mips64_transfers_32bit_regs_p;
  /* Indexes for various registers.  IRIX and embedded have
     different values.  This contains the "public" fields.  Don't
     add any that do not need to be public.  */
  const struct mips_regnum *regnum;
  /* Register names table for the current register set.  */
  const char **mips_processor_reg_names;

  /* The size of register data available from the target, if known.
     This doesn't quite obsolete the manual
     mips64_transfers_32bit_regs_p, since that is documented to force
     left alignment even for big endian (very strange).  */
  int register_size_valid_p;
  int register_size;

  /* Return the expected next PC if FRAME is stopped at a syscall
     instruction.  */
  CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
};

/* Register numbers of various important registers.  */

enum
{
  MIPS_ZERO_REGNUM = 0,		/* Read-only register, always 0.  */
  MIPS_AT_REGNUM = 1,
  MIPS_V0_REGNUM = 2,		/* Function integer return value.  */
  MIPS_A0_REGNUM = 4,		/* Loc of first arg during a subr call.  */
  MIPS_S2_REGNUM = 18,		/* Contains return address in MIPS16 thunks. */
  MIPS_T9_REGNUM = 25,		/* Contains address of callee in PIC.  */
  MIPS_GP_REGNUM = 28,
  MIPS_SP_REGNUM = 29,
  MIPS_RA_REGNUM = 31,
  MIPS_PS_REGNUM = 32,		/* Contains processor status.  */
  MIPS_EMBED_LO_REGNUM = 33,
  MIPS_EMBED_HI_REGNUM = 34,
  MIPS_EMBED_BADVADDR_REGNUM = 35,
  MIPS_EMBED_CAUSE_REGNUM = 36,
  MIPS_EMBED_PC_REGNUM = 37,
  MIPS_EMBED_FP0_REGNUM = 38,
  MIPS_UNUSED_REGNUM = 73,	/* Never used, FIXME.  */
  MIPS_FIRST_EMBED_REGNUM = 74,	/* First CP0 register for embedded use.  */
  MIPS_PRID_REGNUM = 89,	/* Processor ID.  */
  MIPS_LAST_EMBED_REGNUM = 89	/* Last one.  */
};

/* Instruction sizes and other useful constants.  */
enum
{
  MIPS_INSN16_SIZE = 2,
  MIPS_INSN32_SIZE = 4,
  /* The number of floating-point or integer registers.  */
  MIPS_NUMREGS = 32
};

/* Single step based on where the current instruction will take us.  */
extern int mips_software_single_step (struct frame_info *frame);

/* Strip the ISA (compression) bit off from ADDR.  */
extern CORE_ADDR mips_unmake_compact_addr (CORE_ADDR addr);

/* Tell if the program counter value in MEMADDR is in a standard
   MIPS function.  */
extern int mips_pc_is_mips (bfd_vma memaddr);

/* Tell if the program counter value in MEMADDR is in a MIPS16
   function.  */
extern int mips_pc_is_mips16 (struct gdbarch *gdbarch, bfd_vma memaddr);

/* Tell if the program counter value in MEMADDR is in a microMIPS
   function.  */
extern int mips_pc_is_micromips (struct gdbarch *gdbarch, bfd_vma memaddr);

/* Return the currently configured (or set) saved register size.  */
extern unsigned int mips_abi_regsize (struct gdbarch *gdbarch);

/* Make PC the address of the next instruction to execute.  */
extern void mips_write_pc (struct regcache *regcache, CORE_ADDR pc);

/* Target descriptions which only indicate the size of general
   registers.  */
extern struct target_desc *mips_tdesc_gp32;
extern struct target_desc *mips_tdesc_gp64;

/* Return non-zero if PC is in a MIPS SVR4 lazy binding stub section.  */

static inline int
in_mips_stubs_section (CORE_ADDR pc)
{
  return pc_in_section (pc, ".MIPS.stubs");
}

#endif /* MIPS_TDEP_H */
Commit	Line	Data
d1973055 KB	1	/* Target-dependent header for the MIPS architecture, for GDB, the GNU Debugger.
d1973055 KB	2
618f726f	3	Copyright (C) 2002-2016 Free Software Foundation, Inc.
d1973055 KB	4
	5	This file is part of GDB.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
a9762ec7	9	the Free Software Foundation; either version 3 of the License, or
d1973055 KB	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
a9762ec7	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
d1973055 KB	19
	20	#ifndef MIPS_TDEP_H
	21	#define MIPS_TDEP_H
	22
3e5d3a5a MR	23	#include "objfiles.h"
3e5d3a5a MR	24
da3331ec AC	25	struct gdbarch;
da3331ec AC	26
025bb325	27	/* All the possible MIPS ABIs. */
d1973055 KB	28	enum mips_abi
	29	{
	30	MIPS_ABI_UNKNOWN = 0,
	31	MIPS_ABI_N32,
	32	MIPS_ABI_O32,
	33	MIPS_ABI_N64,
	34	MIPS_ABI_O64,
	35	MIPS_ABI_EABI32,
	36	MIPS_ABI_EABI64,
	37	MIPS_ABI_LAST
	38	};
	39
	40	/* Return the MIPS ABI associated with GDBARCH. */
	41	enum mips_abi mips_abi (struct gdbarch *gdbarch);
	42
4cc0665f MR	43	/* Base and compressed MIPS ISA variations. */
	44	enum mips_isa
	45	{
	46	ISA_MIPS = -1, /* mips_compression_string depends on it. */
	47	ISA_MIPS16,
	48	ISA_MICROMIPS
	49	};
	50
f161c171 MR	51	/* Corresponding MSYMBOL_TARGET_FLAG aliases. */
	52	#define MSYMBOL_TARGET_FLAG_MIPS16 MSYMBOL_TARGET_FLAG_1
	53	#define MSYMBOL_TARGET_FLAG_MICROMIPS MSYMBOL_TARGET_FLAG_2
	54
1b13c4f6	55	/* Return the MIPS ISA's register size. Just a short cut to the BFD
4246e332	56	architecture's word size. */
1b13c4f6	57	extern int mips_isa_regsize (struct gdbarch *gdbarch);
4246e332	58
56cea623 AC	59	/* Return the current index for various MIPS registers. */
	60	struct mips_regnum
	61	{
	62	int pc;
	63	int fp0;
	64	int fp_implementation_revision;
	65	int fp_control_status;
	66	int badvaddr; /* Bad vaddr for addressing exception. */
	67	int cause; /* Describes last exception. */
	68	int hi; /* Multiply/divide temp. */
	69	int lo; /* ... */
1faeff08 MR	70	int dspacc; /* SmartMIPS/DSP accumulators. */
1faeff08 MR	71	int dspctl; /* DSP control. */
56cea623 AC	72	};
	73	extern const struct mips_regnum mips_regnum (struct gdbarch gdbarch);
	74
e38d4e1a DJ	75	/* Some MIPS boards don't support floating point while others only
	76	support single-precision floating-point operations. */
	77
	78	enum mips_fpu_type
	79	{
	80	MIPS_FPU_DOUBLE, /* Full double precision floating point. */
	81	MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
	82	MIPS_FPU_NONE /* No floating point. */
	83	};
	84
025bb325	85	/* MIPS specific per-architecture information. */
e38d4e1a DJ	86	struct gdbarch_tdep
	87	{
	88	/* from the elf header */
	89	int elf_flags;
	90
	91	/* mips options */
	92	enum mips_abi mips_abi;
	93	enum mips_abi found_abi;
4cc0665f	94	enum mips_isa mips_isa;
e38d4e1a DJ	95	enum mips_fpu_type mips_fpu_type;
	96	int mips_last_arg_regnum;
	97	int mips_last_fp_arg_regnum;
	98	int default_mask_address_p;
	99	/* Is the target using 64-bit raw integer registers but only
	100	storing a left-aligned 32-bit value in each? */
	101	int mips64_transfers_32bit_regs_p;
	102	/* Indexes for various registers. IRIX and embedded have
	103	different values. This contains the "public" fields. Don't
	104	add any that do not need to be public. */
	105	const struct mips_regnum *regnum;
	106	/* Register names table for the current register set. */
	107	const char **mips_processor_reg_names;
	108
	109	/* The size of register data available from the target, if known.
	110	This doesn't quite obsolete the manual
	111	mips64_transfers_32bit_regs_p, since that is documented to force
	112	left alignment even for big endian (very strange). */
	113	int register_size_valid_p;
	114	int register_size;
	115
	116	/* Return the expected next PC if FRAME is stopped at a syscall
	117	instruction. */
	118	CORE_ADDR (syscall_next_pc) (struct frame_info frame);
	119	};
	120
7157eed4	121	/* Register numbers of various important registers. */
613e114f	122
9c46b6f0 MK	123	enum
9c46b6f0 MK	124	{
613e114f	125	MIPS_ZERO_REGNUM = 0, /* Read-only register, always 0. */
9c46b6f0	126	MIPS_AT_REGNUM = 1,
613e114f	127	MIPS_V0_REGNUM = 2, /* Function integer return value. */
025bb325	128	MIPS_A0_REGNUM = 4, /* Loc of first arg during a subr call. */
14132e89	129	MIPS_S2_REGNUM = 18, /* Contains return address in MIPS16 thunks. */
613e114f	130	MIPS_T9_REGNUM = 25, /* Contains address of callee in PIC. */
14132e89	131	MIPS_GP_REGNUM = 28,
f10683bb	132	MIPS_SP_REGNUM = 29,
9c46b6f0	133	MIPS_RA_REGNUM = 31,
24e05951	134	MIPS_PS_REGNUM = 32, /* Contains processor status. */
56cea623 AC	135	MIPS_EMBED_LO_REGNUM = 33,
	136	MIPS_EMBED_HI_REGNUM = 34,
	137	MIPS_EMBED_BADVADDR_REGNUM = 35,
	138	MIPS_EMBED_CAUSE_REGNUM = 36,
	139	MIPS_EMBED_PC_REGNUM = 37,
613e114f	140	MIPS_EMBED_FP0_REGNUM = 38,
025bb325	141	MIPS_UNUSED_REGNUM = 73, /* Never used, FIXME. */
607fc93c	142	MIPS_FIRST_EMBED_REGNUM = 74, /* First CP0 register for embedded use. */
a5c9623c	143	MIPS_PRID_REGNUM = 89, /* Processor ID. */
607fc93c	144	MIPS_LAST_EMBED_REGNUM = 89 /* Last one. */
56cea623 AC	145	};
56cea623 AC	146
95ac2dcf AC	147	/* Instruction sizes and other useful constants. */
95ac2dcf AC	148	enum
9c46b6f0	149	{
95ac2dcf AC	150	MIPS_INSN16_SIZE = 2,
	151	MIPS_INSN32_SIZE = 4,
	152	/* The number of floating-point or integer registers. */
	153	MIPS_NUMREGS = 32
9c46b6f0 MK	154	};
9c46b6f0 MK	155
0d0266c6	156	/* Single step based on where the current instruction will take us. */
0b1b3e42	157	extern int mips_software_single_step (struct frame_info *frame);
691c0433	158
3e29f34a MR	159	/* Strip the ISA (compression) bit off from ADDR. */
	160	extern CORE_ADDR mips_unmake_compact_addr (CORE_ADDR addr);
	161
4cc0665f MR	162	/* Tell if the program counter value in MEMADDR is in a standard
	163	MIPS function. */
	164	extern int mips_pc_is_mips (bfd_vma memaddr);
	165
0fe7e7c8 AC	166	/* Tell if the program counter value in MEMADDR is in a MIPS16
0fe7e7c8 AC	167	function. */
4cc0665f MR	168	extern int mips_pc_is_mips16 (struct gdbarch *gdbarch, bfd_vma memaddr);
	169
	170	/* Tell if the program counter value in MEMADDR is in a microMIPS
	171	function. */
	172	extern int mips_pc_is_micromips (struct gdbarch *gdbarch, bfd_vma memaddr);
0fe7e7c8	173
025bb325	174	/* Return the currently configured (or set) saved register size. */
e6bc2e8a AC	175	extern unsigned int mips_abi_regsize (struct gdbarch *gdbarch);
e6bc2e8a AC	176
5a439849 MR	177	/* Make PC the address of the next instruction to execute. */
	178	extern void mips_write_pc (struct regcache *regcache, CORE_ADDR pc);
	179
4eb0ad19 DJ	180	/* Target descriptions which only indicate the size of general
	181	registers. */
	182	extern struct target_desc *mips_tdesc_gp32;
	183	extern struct target_desc *mips_tdesc_gp64;
	184
3e5d3a5a MR	185	/* Return non-zero if PC is in a MIPS SVR4 lazy binding stub section. */
	186
	187	static inline int
	188	in_mips_stubs_section (CORE_ADDR pc)
	189	{
	190	return pc_in_section (pc, ".MIPS.stubs");
	191	}
	192
d1973055	193	#endif /* MIPS_TDEP_H */