[deliverable/binutils-gdb.git] / gdb / nat / mips-linux-watch.c

/* Copyright (C) 2009-2014 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifdef GDBSERVER
#include "server.h"
#else
#include "defs.h"
#endif
#include <sys/ptrace.h>
#include "mips-linux-watch.h"
#include "gdb_assert.h"

/* Assuming usable watch registers REGS, return the irw_mask of
   register N.  */

uint32_t
mips_linux_watch_get_irw_mask (struct pt_watch_regs *regs, int n)
{
  switch (regs->style)
    {
    case pt_watch_style_mips32:
      return regs->mips32.watch_masks[n] & IRW_MASK;
    case pt_watch_style_mips64:
      return regs->mips64.watch_masks[n] & IRW_MASK;
    default:
      internal_error (__FILE__, __LINE__,
		      _("Unrecognized watch register style"));
    }
}

/* Assuming usable watch registers REGS, return the reg_mask of
   register N.  */

static uint32_t
get_reg_mask (struct pt_watch_regs *regs, int n)
{
  switch (regs->style)
    {
    case pt_watch_style_mips32:
      return regs->mips32.watch_masks[n] & ~IRW_MASK;
    case pt_watch_style_mips64:
      return regs->mips64.watch_masks[n] & ~IRW_MASK;
    default:
      internal_error (__FILE__, __LINE__,
		      _("Unrecognized watch register style"));
    }
}

/* Assuming usable watch registers REGS, return the num_valid.  */

uint32_t
mips_linux_watch_get_num_valid (struct pt_watch_regs *regs)
{
  switch (regs->style)
    {
    case pt_watch_style_mips32:
      return regs->mips32.num_valid;
    case pt_watch_style_mips64:
      return regs->mips64.num_valid;
    default:
      internal_error (__FILE__, __LINE__,
		      _("Unrecognized watch register style"));
    }
}

/* Assuming usable watch registers REGS, return the watchlo of
   register N.  */

CORE_ADDR
mips_linux_watch_get_watchlo (struct pt_watch_regs *regs, int n)
{
  switch (regs->style)
    {
    case pt_watch_style_mips32:
      return regs->mips32.watchlo[n];
    case pt_watch_style_mips64:
      return regs->mips64.watchlo[n];
    default:
      internal_error (__FILE__, __LINE__,
		      _("Unrecognized watch register style"));
    }
}

/* Assuming usable watch registers REGS, set watchlo of register N to
   VALUE.  */

void
mips_linux_watch_set_watchlo (struct pt_watch_regs *regs, int n,
			      CORE_ADDR value)
{
  switch (regs->style)
    {
    case pt_watch_style_mips32:
      /*  The cast will never throw away bits as 64 bit addresses can
	  never be used on a 32 bit kernel.  */
      regs->mips32.watchlo[n] = (uint32_t) value;
      break;
    case pt_watch_style_mips64:
      regs->mips64.watchlo[n] = value;
      break;
    default:
      internal_error (__FILE__, __LINE__,
		      _("Unrecognized watch register style"));
    }
}

/* Assuming usable watch registers REGS, return the watchhi of
   register N.  */

uint32_t
mips_linux_watch_get_watchhi (struct pt_watch_regs *regs, int n)
{
  switch (regs->style)
    {
    case pt_watch_style_mips32:
      return regs->mips32.watchhi[n];
    case pt_watch_style_mips64:
      return regs->mips64.watchhi[n];
    default:
      internal_error (__FILE__, __LINE__,
		      _("Unrecognized watch register style"));
    }
}

/* Assuming usable watch registers REGS, set watchhi of register N to
   VALUE.  */

void
mips_linux_watch_set_watchhi (struct pt_watch_regs *regs, int n,
			      uint16_t value)
{
  switch (regs->style)
    {
    case pt_watch_style_mips32:
      regs->mips32.watchhi[n] = value;
      break;
    case pt_watch_style_mips64:
      regs->mips64.watchhi[n] = value;
      break;
    default:
      internal_error (__FILE__, __LINE__,
		      _("Unrecognized watch register style"));
    }
}

/* Read the watch registers of process LWPID and store it in
   WATCH_READBACK.  Save true to *WATCH_READBACK_VALID if watch
   registers are valid.  Return 1 if watch registers are usable.
   Cached information is used unless FORCE is true.  */

int
mips_linux_read_watch_registers (long lwpid,
				 struct pt_watch_regs *watch_readback,
				 int *watch_readback_valid, int force)
{
  if (force || *watch_readback_valid == 0)
    {
      if (ptrace (PTRACE_GET_WATCH_REGS, lwpid, watch_readback) == -1)
	{
	  *watch_readback_valid = -1;
	  return 0;
	}
      switch (watch_readback->style)
	{
	case pt_watch_style_mips32:
	  if (watch_readback->mips32.num_valid == 0)
	    {
	      *watch_readback_valid = -1;
	      return 0;
	    }
	  break;
	case pt_watch_style_mips64:
	  if (watch_readback->mips64.num_valid == 0)
	    {
	      *watch_readback_valid = -1;
	      return 0;
	    }
	  break;
	default:
	  *watch_readback_valid = -1;
	  return 0;
	}
      /* Watch registers appear to be usable.  */
      *watch_readback_valid = 1;
    }
  return (*watch_readback_valid == 1) ? 1 : 0;
}

/* Convert GDB's TYPE to an IRW mask.  */

uint32_t
mips_linux_watch_type_to_irw (int type)
{
  switch (type)
    {
    case hw_write:
      return W_MASK;
    case hw_read:
      return R_MASK;
    case hw_access:
      return (W_MASK | R_MASK);
    default:
      return 0;
    }
}

/* Set any low order bits in MASK that are not set.  */

static CORE_ADDR
fill_mask (CORE_ADDR mask)
{
  CORE_ADDR f = 1;

  while (f && f < mask)
    {
      mask |= f;
      f <<= 1;
    }
  return mask;
}

/* Try to add a single watch to the specified registers REGS.  The
   address of added watch is ADDR, the length is LEN, and the mask
   is IRW.  Return 1 on success, 0 on failure.  */

int
mips_linux_watch_try_one_watch (struct pt_watch_regs *regs,
				CORE_ADDR addr, int len, uint32_t irw)
{
  CORE_ADDR base_addr, last_byte, break_addr, segment_len;
  CORE_ADDR mask_bits, t_low;
  uint16_t t_hi;
  int i, free_watches;
  struct pt_watch_regs regs_copy;

  if (len <= 0)
    return 0;

  last_byte = addr + len - 1;
  mask_bits = fill_mask (addr ^ last_byte) | IRW_MASK;
  base_addr = addr & ~mask_bits;

  /* Check to see if it is covered by current registers.  */
  for (i = 0; i < mips_linux_watch_get_num_valid (regs); i++)
    {
      t_low = mips_linux_watch_get_watchlo (regs, i);
      if (t_low != 0 && irw == ((uint32_t) t_low & irw))
	{
	  t_hi = mips_linux_watch_get_watchhi (regs, i) | IRW_MASK;
	  t_low &= ~(CORE_ADDR) t_hi;
	  if (addr >= t_low && last_byte <= (t_low + t_hi))
	    return 1;
	}
    }
  /* Try to find an empty register.  */
  free_watches = 0;
  for (i = 0; i < mips_linux_watch_get_num_valid (regs); i++)
    {
      t_low = mips_linux_watch_get_watchlo (regs, i);
      if (t_low == 0
	  && irw == (mips_linux_watch_get_irw_mask (regs, i) & irw))
	{
	  if (mask_bits <= (get_reg_mask (regs, i) | IRW_MASK))
	    {
	      /* It fits, we'll take it.  */
	      mips_linux_watch_set_watchlo (regs, i, base_addr | irw);
	      mips_linux_watch_set_watchhi (regs, i, mask_bits & ~IRW_MASK);
	      return 1;
	    }
	  else
	    {
	      /* It doesn't fit, but has the proper IRW capabilities.  */
	      free_watches++;
	    }
	}
    }
  if (free_watches > 1)
    {
      /* Try to split it across several registers.  */
      regs_copy = *regs;
      for (i = 0; i < mips_linux_watch_get_num_valid (&regs_copy); i++)
	{
	  t_low = mips_linux_watch_get_watchlo (&regs_copy, i);
	  t_hi = get_reg_mask (&regs_copy, i) | IRW_MASK;
	  if (t_low == 0 && irw == (t_hi & irw))
	    {
	      t_low = addr & ~(CORE_ADDR) t_hi;
	      break_addr = t_low + t_hi + 1;
	      if (break_addr >= addr + len)
		segment_len = len;
	      else
		segment_len = break_addr - addr;
	      mask_bits = fill_mask (addr ^ (addr + segment_len - 1));
	      mips_linux_watch_set_watchlo (&regs_copy, i,
					    (addr & ~mask_bits) | irw);
	      mips_linux_watch_set_watchhi (&regs_copy, i,
					    mask_bits & ~IRW_MASK);
	      if (break_addr >= addr + len)
		{
		  *regs = regs_copy;
		  return 1;
		}
	      len = addr + len - break_addr;
	      addr = break_addr;
	    }
	}
    }
  /* It didn't fit anywhere, we failed.  */
  return 0;
}

/* Fill in the watch registers REGS with the currently cached
   watches CURRENT_WATCHES.  */

void
mips_linux_watch_populate_regs (struct mips_watchpoint *current_watches,
				struct pt_watch_regs *regs)
{
  struct mips_watchpoint *w;
  int i;

  /* Clear them out.  */
  for (i = 0; i < mips_linux_watch_get_num_valid (regs); i++)
    {
      mips_linux_watch_set_watchlo (regs, i, 0);
      mips_linux_watch_set_watchhi (regs, i, 0);
    }

  w = current_watches;
  while (w)
    {
      uint32_t irw = mips_linux_watch_type_to_irw (w->type);

      i = mips_linux_watch_try_one_watch (regs, w->addr, w->len, irw);
      /* They must all fit, because we previously calculated that they
	 would.  */
      gdb_assert (i);
      w = w->next;
    }
}
Commit	Line	Data
ecd75fc8	1	/* Copyright (C) 2009-2014 Free Software Foundation, Inc.
aaee2056 YQ	2
	3	This file is part of GDB.
	4
	5	This program is free software; you can redistribute it and/or modify
	6	it under the terms of the GNU General Public License as published by
	7	the Free Software Foundation; either version 3 of the License, or
	8	(at your option) any later version.
	9
	10	This program is distributed in the hope that it will be useful,
	11	but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	GNU General Public License for more details.
	14
	15	You should have received a copy of the GNU General Public License
	16	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	17
d41f6d8e GB	18	#ifdef GDBSERVER
	19	#include "server.h"
	20	#else
	21	#include "defs.h"
	22	#endif
aaee2056 YQ	23	#include <sys/ptrace.h>
	24	#include "mips-linux-watch.h"
	25	#include "gdb_assert.h"
	26
	27	/* Assuming usable watch registers REGS, return the irw_mask of
	28	register N. */
	29
	30	uint32_t
	31	mips_linux_watch_get_irw_mask (struct pt_watch_regs *regs, int n)
	32	{
	33	switch (regs->style)
	34	{
	35	case pt_watch_style_mips32:
	36	return regs->mips32.watch_masks[n] & IRW_MASK;
	37	case pt_watch_style_mips64:
	38	return regs->mips64.watch_masks[n] & IRW_MASK;
	39	default:
	40	internal_error (__FILE__, __LINE__,
	41	_("Unrecognized watch register style"));
	42	}
	43	}
	44
	45	/* Assuming usable watch registers REGS, return the reg_mask of
	46	register N. */
	47
	48	static uint32_t
	49	get_reg_mask (struct pt_watch_regs *regs, int n)
	50	{
	51	switch (regs->style)
	52	{
	53	case pt_watch_style_mips32:
	54	return regs->mips32.watch_masks[n] & ~IRW_MASK;
	55	case pt_watch_style_mips64:
	56	return regs->mips64.watch_masks[n] & ~IRW_MASK;
	57	default:
	58	internal_error (__FILE__, __LINE__,
	59	_("Unrecognized watch register style"));
	60	}
	61	}
	62
	63	/* Assuming usable watch registers REGS, return the num_valid. */
	64
	65	uint32_t
	66	mips_linux_watch_get_num_valid (struct pt_watch_regs *regs)
	67	{
	68	switch (regs->style)
	69	{
	70	case pt_watch_style_mips32:
	71	return regs->mips32.num_valid;
	72	case pt_watch_style_mips64:
	73	return regs->mips64.num_valid;
	74	default:
	75	internal_error (__FILE__, __LINE__,
	76	_("Unrecognized watch register style"));
	77	}
	78	}
	79
	80	/* Assuming usable watch registers REGS, return the watchlo of
	81	register N. */
	82
	83	CORE_ADDR
	84	mips_linux_watch_get_watchlo (struct pt_watch_regs *regs, int n)
	85	{
	86	switch (regs->style)
87	{
88	case pt_watch_style_mips32:
89	return regs->mips32.watchlo[n];
90	case pt_watch_style_mips64:
91	return regs->mips64.watchlo[n];
92	default:
93	internal_error (__FILE__, __LINE__,
94	_("Unrecognized watch register style"));
95	}
96	}
97
98	/* Assuming usable watch registers REGS, set watchlo of register N to
99	VALUE. */
100
101	void
102	mips_linux_watch_set_watchlo (struct pt_watch_regs *regs, int n,
103	CORE_ADDR value)
104	{
105	switch (regs->style)
106	{
107	case pt_watch_style_mips32:
108	/* The cast will never throw away bits as 64 bit addresses can
109	never be used on a 32 bit kernel. */
110	regs->mips32.watchlo[n] = (uint32_t) value;
111	break;
112	case pt_watch_style_mips64:
113	regs->mips64.watchlo[n] = value;
114	break;
115	default:
116	internal_error (__FILE__, __LINE__,
117	_("Unrecognized watch register style"));
118	}
119	}
120
121	/* Assuming usable watch registers REGS, return the watchhi of
122	register N. */
123
124	uint32_t
125	mips_linux_watch_get_watchhi (struct pt_watch_regs *regs, int n)
126	{
127	switch (regs->style)
128	{
129	case pt_watch_style_mips32:
130	return regs->mips32.watchhi[n];
131	case pt_watch_style_mips64:
132	return regs->mips64.watchhi[n];
133	default:
134	internal_error (__FILE__, __LINE__,
135	_("Unrecognized watch register style"));
136	}
137	}
138
139	/* Assuming usable watch registers REGS, set watchhi of register N to
140	VALUE. */
141
142	void
143	mips_linux_watch_set_watchhi (struct pt_watch_regs *regs, int n,
144	uint16_t value)
145	{
146	switch (regs->style)
147	{
148	case pt_watch_style_mips32:
149	regs->mips32.watchhi[n] = value;
150	break;
151	case pt_watch_style_mips64:
152	regs->mips64.watchhi[n] = value;
153	break;
154	default:
155	internal_error (__FILE__, __LINE__,
156	_("Unrecognized watch register style"));
157	}
158	}
159
160	/* Read the watch registers of process LWPID and store it in
161	WATCH_READBACK. Save true to *WATCH_READBACK_VALID if watch
162	registers are valid. Return 1 if watch registers are usable.
163	Cached information is used unless FORCE is true. */
164
165	int
166	mips_linux_read_watch_registers (long lwpid,
167	struct pt_watch_regs *watch_readback,
168	int *watch_readback_valid, int force)
169	{
170	if (force \|\| *watch_readback_valid == 0)
171	{
172	if (ptrace (PTRACE_GET_WATCH_REGS, lwpid, watch_readback) == -1)
173	{
174	*watch_readback_valid = -1;
175	return 0;
176	}
177	switch (watch_readback->style)
178	{
179	case pt_watch_style_mips32:
180	if (watch_readback->mips32.num_valid == 0)
181	{
182	*watch_readback_valid = -1;
183	return 0;
184	}
185	break;
186	case pt_watch_style_mips64:
187	if (watch_readback->mips64.num_valid == 0)
188	{
189	*watch_readback_valid = -1;
190	return 0;
191	}
192	break;
193	default:
194	*watch_readback_valid = -1;
195	return 0;
196	}
197	/* Watch registers appear to be usable. */
198	*watch_readback_valid = 1;
199	}
200	return (*watch_readback_valid == 1) ? 1 : 0;
201	}
202
203	/* Convert GDB's TYPE to an IRW mask. */
204
205	uint32_t
206	mips_linux_watch_type_to_irw (int type)
207	{
208	switch (type)
209	{
210	case hw_write:
211	return W_MASK;
212	case hw_read:
213	return R_MASK;
214	case hw_access:
215	return (W_MASK \| R_MASK);
216	default:
217	return 0;
218	}
219	}
220
221	/* Set any low order bits in MASK that are not set. */
222
223	static CORE_ADDR
224	fill_mask (CORE_ADDR mask)
225	{
226	CORE_ADDR f = 1;
227
228	while (f && f < mask)
229	{
230	mask \|= f;
231	f <<= 1;
232	}
233	return mask;
234	}
235
236	/* Try to add a single watch to the specified registers REGS. The
237	address of added watch is ADDR, the length is LEN, and the mask
238	is IRW. Return 1 on success, 0 on failure. */
239
240	int
241	mips_linux_watch_try_one_watch (struct pt_watch_regs *regs,
242	CORE_ADDR addr, int len, uint32_t irw)
243	{
244	CORE_ADDR base_addr, last_byte, break_addr, segment_len;
245	CORE_ADDR mask_bits, t_low;
246	uint16_t t_hi;
247	int i, free_watches;
248	struct pt_watch_regs regs_copy;
249
250	if (len <= 0)
251	return 0;
252
253	last_byte = addr + len - 1;
254	mask_bits = fill_mask (addr ^ last_byte) \| IRW_MASK;
255	base_addr = addr & ~mask_bits;
256
257	/* Check to see if it is covered by current registers. */
258	for (i = 0; i < mips_linux_watch_get_num_valid (regs); i++)
259	{
260	t_low = mips_linux_watch_get_watchlo (regs, i);
261	if (t_low != 0 && irw == ((uint32_t) t_low & irw))
262	{
263	t_hi = mips_linux_watch_get_watchhi (regs, i) \| IRW_MASK;
264	t_low &= ~(CORE_ADDR) t_hi;
265	if (addr >= t_low && last_byte <= (t_low + t_hi))
266	return 1;
267	}
268	}
269	/* Try to find an empty register. */
270	free_watches = 0;
271	for (i = 0; i < mips_linux_watch_get_num_valid (regs); i++)
272	{
273	t_low = mips_linux_watch_get_watchlo (regs, i);
274	if (t_low == 0
275	&& irw == (mips_linux_watch_get_irw_mask (regs, i) & irw))
276	{
277	if (mask_bits <= (get_reg_mask (regs, i) \| IRW_MASK))
278	{
279	/* It fits, we'll take it. */
280	mips_linux_watch_set_watchlo (regs, i, base_addr \| irw);
281	mips_linux_watch_set_watchhi (regs, i, mask_bits & ~IRW_MASK);
282	return 1;
283	}
284	else
285	{
286	/* It doesn't fit, but has the proper IRW capabilities. */
287	free_watches++;
288	}
289	}
290	}
291	if (free_watches > 1)
292	{
293	/* Try to split it across several registers. */
294	regs_copy = *regs;
295	for (i = 0; i < mips_linux_watch_get_num_valid (&regs_copy); i++)
296	{
297	t_low = mips_linux_watch_get_watchlo (&regs_copy, i);
298	t_hi = get_reg_mask (&regs_copy, i) \| IRW_MASK;
299	if (t_low == 0 && irw == (t_hi & irw))
300	{
301	t_low = addr & ~(CORE_ADDR) t_hi;
302	break_addr = t_low + t_hi + 1;
303	if (break_addr >= addr + len)
304	segment_len = len;
305	else
306	segment_len = break_addr - addr;
307	mask_bits = fill_mask (addr ^ (addr + segment_len - 1));
308	mips_linux_watch_set_watchlo (&regs_copy, i,
309	(addr & ~mask_bits) \| irw);
310	mips_linux_watch_set_watchhi (&regs_copy, i,
311	mask_bits & ~IRW_MASK);
312	if (break_addr >= addr + len)
313	{
314	*regs = regs_copy;
315	return 1;
316	}
317	len = addr + len - break_addr;
318	addr = break_addr;
319	}
320	}
321	}
322	/* It didn't fit anywhere, we failed. */
323	return 0;
324	}
325
326	/* Fill in the watch registers REGS with the currently cached
327	watches CURRENT_WATCHES. */
328
329	void
330	mips_linux_watch_populate_regs (struct mips_watchpoint *current_watches,
331	struct pt_watch_regs *regs)
332	{
333	struct mips_watchpoint *w;
334	int i;
335
336	/* Clear them out. */
337	for (i = 0; i < mips_linux_watch_get_num_valid (regs); i++)
338	{
339	mips_linux_watch_set_watchlo (regs, i, 0);
340	mips_linux_watch_set_watchhi (regs, i, 0);
341	}
342
343	w = current_watches;
344	while (w)
345	{
346	uint32_t irw = mips_linux_watch_type_to_irw (w->type);
347
348	i = mips_linux_watch_try_one_watch (regs, w->addr, w->len, irw);
349	/* They must all fit, because we previously calculated that they
350	would. */
351	gdb_assert (i);
352	w = w->next;
353	}
354	}