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[deliverable/binutils-gdb.git] / gdb / nds32-tdep.c
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a28d8e50
YTL		 1/* Target-dependent code for the NDS32 architecture, for GDB.
2
3 Copyright (C) 2013-2016 Free Software Foundation, Inc.
4 Contributed by Andes Technology Corporation.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "defs.h"
22#include "frame.h"
23#include "frame-unwind.h"
24#include "frame-base.h"
25#include "symtab.h"
26#include "gdbtypes.h"
27#include "gdbcore.h"
28#include "value.h"
29#include "reggroups.h"
30#include "inferior.h"
31#include "osabi.h"
32#include "arch-utils.h"
33#include "regcache.h"
34#include "dis-asm.h"
35#include "user-regs.h"
36#include "elf-bfd.h"
37#include "dwarf2-frame.h"
38#include "remote.h"
39#include "target-descriptions.h"
40
41#include "nds32-tdep.h"
42#include "elf/nds32.h"
43#include "opcode/nds32.h"
325fac50
PA		 44#include <algorithm>
45
a28d8e50
YTL		 46#include "features/nds32.c"
47
48/* Simple macros for instruction analysis. */
49#define CHOP_BITS(insn, n) (insn & ~__MASK (n))
50#define N32_LSMW_ENABLE4(insn) (((insn) >> 6) & 0xf)
51#define N32_SMW_ADM \
52 N32_TYPE4 (LSMW, 0, 0, 0, 1, (N32_LSMW_ADM << 2) | N32_LSMW_LSMW)
53#define N32_LMW_BIM \
54 N32_TYPE4 (LSMW, 0, 0, 0, 0, (N32_LSMW_BIM << 2) | N32_LSMW_LSMW)
55#define N32_FLDI_SP \
56 N32_TYPE2 (LDC, 0, REG_SP, 0)
57
58extern void _initialize_nds32_tdep (void);
59
60/* Use an invalid address value as 'not available' marker. */
61enum { REG_UNAVAIL = (CORE_ADDR) -1 };
62
63/* Use an impossible value as invalid offset. */
64enum { INVALID_OFFSET = (CORE_ADDR) -1 };
65
66/* Instruction groups for NDS32 epilogue analysis. */
67enum
68{
69 /* Instructions used everywhere, not only in epilogue. */
70 INSN_NORMAL,
71 /* Instructions used to reset sp for local vars, arguments, etc. */
72 INSN_RESET_SP,
73 /* Instructions used to recover saved regs and to recover padding. */
74 INSN_RECOVER,
75 /* Instructions used to return to the caller. */
76 INSN_RETURN,
77 /* Instructions used to recover saved regs and to return to the caller. */
78 INSN_RECOVER_RETURN,
79};
80
81static const char *const nds32_register_names[] =
82{
83 /* 32 GPRs. */
84 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
85 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
86 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
87 "r24", "r25", "r26", "r27", "fp", "gp", "lp", "sp",
88 /* PC. */
89 "pc",
90};
91
92static const char *const nds32_fdr_register_names[] =
93{
94 "fd0", "fd1", "fd2", "fd3", "fd4", "fd5", "fd6", "fd7",
95 "fd8", "fd9", "fd10", "fd11", "fd12", "fd13", "fd14", "fd15",
96 "fd16", "fd17", "fd18", "fd19", "fd20", "fd21", "fd22", "fd23",
97 "fd24", "fd25", "fd26", "fd27", "fd28", "fd29", "fd30", "fd31"
98};
99
100static const char *const nds32_fsr_register_names[] =
101{
102 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
103 "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
104 "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23",
105 "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"
106};
107
108/* The number of registers for four FPU configuration options. */
109const int num_fdr_map[] = { 4, 8, 16, 32 };
110const int num_fsr_map[] = { 8, 16, 32, 32 };
111
112/* Aliases for registers. */
113static const struct
114{
115 const char *name;
116 const char *alias;
117} nds32_register_aliases[] =
118{
119 {"r15", "ta"},
120 {"r26", "p0"},
121 {"r27", "p1"},
122 {"fp", "r28"},
123 {"gp", "r29"},
124 {"lp", "r30"},
125 {"sp", "r31"},
126
127 {"cr0", "cpu_ver"},
128 {"cr1", "icm_cfg"},
129 {"cr2", "dcm_cfg"},
130 {"cr3", "mmu_cfg"},
131 {"cr4", "msc_cfg"},
132 {"cr5", "core_id"},
133 {"cr6", "fucop_exist"},
134 {"cr7", "msc_cfg2"},
135
136 {"ir0", "psw"},
137 {"ir1", "ipsw"},
138 {"ir2", "p_psw"},
139 {"ir3", "ivb"},
140 {"ir4", "eva"},
141 {"ir5", "p_eva"},
142 {"ir6", "itype"},
143 {"ir7", "p_itype"},
144 {"ir8", "merr"},
145 {"ir9", "ipc"},
146 {"ir10", "p_ipc"},
147 {"ir11", "oipc"},
148 {"ir12", "p_p0"},
149 {"ir13", "p_p1"},
150 {"ir14", "int_mask"},
151 {"ir15", "int_pend"},
152 {"ir16", "sp_usr"},
153 {"ir17", "sp_priv"},
154 {"ir18", "int_pri"},
155 {"ir19", "int_ctrl"},
156 {"ir20", "sp_usr1"},
157 {"ir21", "sp_priv1"},
158 {"ir22", "sp_usr2"},
159 {"ir23", "sp_priv2"},
160 {"ir24", "sp_usr3"},
161 {"ir25", "sp_priv3"},
162 {"ir26", "int_mask2"},
163 {"ir27", "int_pend2"},
164 {"ir28", "int_pri2"},
165 {"ir29", "int_trigger"},
166
167 {"mr0", "mmu_ctl"},
168 {"mr1", "l1_pptb"},
169 {"mr2", "tlb_vpn"},
170 {"mr3", "tlb_data"},
171 {"mr4", "tlb_misc"},
172 {"mr5", "vlpt_idx"},
173 {"mr6", "ilmb"},
174 {"mr7", "dlmb"},
175 {"mr8", "cache_ctl"},
176 {"mr9", "hsmp_saddr"},
177 {"mr10", "hsmp_eaddr"},
178 {"mr11", "bg_region"},
179
180 {"dr0", "bpc0"},
181 {"dr1", "bpc1"},
182 {"dr2", "bpc2"},
183 {"dr3", "bpc3"},
184 {"dr4", "bpc4"},
185 {"dr5", "bpc5"},
186 {"dr6", "bpc6"},
187 {"dr7", "bpc7"},
188 {"dr8", "bpa0"},
189 {"dr9", "bpa1"},
190 {"dr10", "bpa2"},
191 {"dr11", "bpa3"},
192 {"dr12", "bpa4"},
193 {"dr13", "bpa5"},
194 {"dr14", "bpa6"},
195 {"dr15", "bpa7"},
196 {"dr16", "bpam0"},
197 {"dr17", "bpam1"},
198 {"dr18", "bpam2"},
199 {"dr19", "bpam3"},
200 {"dr20", "bpam4"},
201 {"dr21", "bpam5"},
202 {"dr22", "bpam6"},
203 {"dr23", "bpam7"},
204 {"dr24", "bpv0"},
205 {"dr25", "bpv1"},
206 {"dr26", "bpv2"},
207 {"dr27", "bpv3"},
208 {"dr28", "bpv4"},
209 {"dr29", "bpv5"},
210 {"dr30", "bpv6"},
211 {"dr31", "bpv7"},
212 {"dr32", "bpcid0"},
213 {"dr33", "bpcid1"},
214 {"dr34", "bpcid2"},
215 {"dr35", "bpcid3"},
216 {"dr36", "bpcid4"},
217 {"dr37", "bpcid5"},
218 {"dr38", "bpcid6"},
219 {"dr39", "bpcid7"},
220 {"dr40", "edm_cfg"},
221 {"dr41", "edmsw"},
222 {"dr42", "edm_ctl"},
223 {"dr43", "edm_dtr"},
224 {"dr44", "bpmtc"},
225 {"dr45", "dimbr"},
226 {"dr46", "tecr0"},
227 {"dr47", "tecr1"},
228
229 {"hspr0", "hsp_ctl"},
230 {"hspr1", "sp_bound"},
231 {"hspr2", "sp_bound_priv"},
232
233 {"pfr0", "pfmc0"},
234 {"pfr1", "pfmc1"},
235 {"pfr2", "pfmc2"},
236 {"pfr3", "pfm_ctl"},
237 {"pfr4", "pft_ctl"},
238
239 {"dmar0", "dma_cfg"},
240 {"dmar1", "dma_gcsw"},
241 {"dmar2", "dma_chnsel"},
242 {"dmar3", "dma_act"},
243 {"dmar4", "dma_setup"},
244 {"dmar5", "dma_isaddr"},
245 {"dmar6", "dma_esaddr"},
246 {"dmar7", "dma_tcnt"},
247 {"dmar8", "dma_status"},
248 {"dmar9", "dma_2dset"},
249 {"dmar10", "dma_2dsctl"},
250 {"dmar11", "dma_rcnt"},
251 {"dmar12", "dma_hstatus"},
252
253 {"racr0", "prusr_acc_ctl"},
254 {"fucpr", "fucop_ctl"},
255
256 {"idr0", "sdz_ctl"},
257 {"idr1", "misc_ctl"},
258 {"idr2", "ecc_misc"},
259
260 {"secur0", "sfcr"},
261 {"secur1", "sign"},
262 {"secur2", "isign"},
263 {"secur3", "p_isign"},
264};
265
266/* Value of a register alias. BATON is the regnum of the corresponding
267 register. */
268
269static struct value *
270value_of_nds32_reg (struct frame_info *frame, const void *baton)
271{
272 return value_of_register ((int) (intptr_t) baton, frame);
273}
274\f
275/* Implement the "frame_align" gdbarch method. */
276
277static CORE_ADDR
278nds32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
279{
280 /* 8-byte aligned. */
281 return align_down (sp, 8);
282}
283
284/* Implement the "breakpoint_from_pc" gdbarch method.
285
286 Use the program counter to determine the contents and size of a
287 breakpoint instruction. Return a pointer to a string of bytes that
288 encode a breakpoint instruction, store the length of the string in
289 *LENPTR and optionally adjust *PCPTR to point to the correct memory
290 location for inserting the breakpoint. */
291
292static const gdb_byte *
293nds32_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
294 int *lenptr)
295{
296 /* The same insn machine code is used for little-endian and big-endian. */
297 static const gdb_byte break_insn[] = { 0xEA, 0x00 };
298
299 *lenptr = sizeof (break_insn);
300 return break_insn;
301}
302
303/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
304
305static int
306nds32_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
307{
308 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
309 const int FSR = 38;
310 const int FDR = FSR + 32;
311
312 if (num >= 0 && num < 32)
313 {
314 /* General-purpose registers (R0 - R31). */
315 return num;
316 }
317 else if (num >= FSR && num < FSR + 32)
318 {
319 /* Single precision floating-point registers (FS0 - FS31). */
320 return num - FSR + tdep->fs0_regnum;
321 }
322 else if (num >= FDR && num < FDR + 32)
323 {
324 /* Double precision floating-point registers (FD0 - FD31). */
325 return num - FDR + NDS32_FD0_REGNUM;
326 }
327
328 /* No match, return a inaccessible register number. */
329 return -1;
330}
331\f
332/* NDS32 register groups. */
333static struct reggroup *nds32_cr_reggroup;
334static struct reggroup *nds32_ir_reggroup;
335static struct reggroup *nds32_mr_reggroup;
336static struct reggroup *nds32_dr_reggroup;
337static struct reggroup *nds32_pfr_reggroup;
338static struct reggroup *nds32_hspr_reggroup;
339static struct reggroup *nds32_dmar_reggroup;
340static struct reggroup *nds32_racr_reggroup;
341static struct reggroup *nds32_idr_reggroup;
342static struct reggroup *nds32_secur_reggroup;
343
344static void
345nds32_init_reggroups (void)
346{
347 nds32_cr_reggroup = reggroup_new ("cr", USER_REGGROUP);
348 nds32_ir_reggroup = reggroup_new ("ir", USER_REGGROUP);
349 nds32_mr_reggroup = reggroup_new ("mr", USER_REGGROUP);
350 nds32_dr_reggroup = reggroup_new ("dr", USER_REGGROUP);
351 nds32_pfr_reggroup = reggroup_new ("pfr", USER_REGGROUP);
352 nds32_hspr_reggroup = reggroup_new ("hspr", USER_REGGROUP);
353 nds32_dmar_reggroup = reggroup_new ("dmar", USER_REGGROUP);
354 nds32_racr_reggroup = reggroup_new ("racr", USER_REGGROUP);
355 nds32_idr_reggroup = reggroup_new ("idr", USER_REGGROUP);
356 nds32_secur_reggroup = reggroup_new ("secur", USER_REGGROUP);
357}
358
359static void
360nds32_add_reggroups (struct gdbarch *gdbarch)
361{
362 /* Add pre-defined register groups. */
363 reggroup_add (gdbarch, general_reggroup);
364 reggroup_add (gdbarch, float_reggroup);
365 reggroup_add (gdbarch, system_reggroup);
366 reggroup_add (gdbarch, all_reggroup);
367 reggroup_add (gdbarch, save_reggroup);
368 reggroup_add (gdbarch, restore_reggroup);
369
370 /* Add NDS32 register groups. */
371 reggroup_add (gdbarch, nds32_cr_reggroup);
372 reggroup_add (gdbarch, nds32_ir_reggroup);
373 reggroup_add (gdbarch, nds32_mr_reggroup);
374 reggroup_add (gdbarch, nds32_dr_reggroup);
375 reggroup_add (gdbarch, nds32_pfr_reggroup);
376 reggroup_add (gdbarch, nds32_hspr_reggroup);
377 reggroup_add (gdbarch, nds32_dmar_reggroup);
378 reggroup_add (gdbarch, nds32_racr_reggroup);
379 reggroup_add (gdbarch, nds32_idr_reggroup);
380 reggroup_add (gdbarch, nds32_secur_reggroup);
381}
382
383/* Implement the "register_reggroup_p" gdbarch method. */
384
385static int
386nds32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
387 struct reggroup *reggroup)
388{
389 const char *reg_name;
390 const char *group_name;
391 int ret;
392
393 if (reggroup == all_reggroup)
394 return 1;
395
396 /* General reggroup contains only GPRs and PC. */
397 if (reggroup == general_reggroup)
398 return regnum <= NDS32_PC_REGNUM;
399
400 if (reggroup == float_reggroup || reggroup == save_reggroup
401 || reggroup == restore_reggroup)
402 {
403 ret = tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup);
404 if (ret != -1)
405 return ret;
406
407 return default_register_reggroup_p (gdbarch, regnum, reggroup);
408 }
409
410 if (reggroup == system_reggroup)
411 return (regnum > NDS32_PC_REGNUM)
412 && !nds32_register_reggroup_p (gdbarch, regnum, float_reggroup);
413
414 /* The NDS32 reggroup contains registers whose name is prefixed
415 by reggroup name. */
416 reg_name = gdbarch_register_name (gdbarch, regnum);
417 group_name = reggroup_name (reggroup);
418 return !strncmp (reg_name, group_name, strlen (group_name));
419}
420\f
421/* Implement the "pseudo_register_type" tdesc_arch_data method. */
422
423static struct type *
424nds32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
425{
426 regnum -= gdbarch_num_regs (gdbarch);
427
428 /* Currently, only FSRs could be defined as pseudo registers. */
429 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
430 return arch_float_type (gdbarch, -1, "builtin_type_ieee_single",
431 floatformats_ieee_single);
432
433 warning (_("Unknown nds32 pseudo register %d."), regnum);
434 return NULL;
435}
436
437/* Implement the "pseudo_register_name" tdesc_arch_data method. */
438
439static const char *
440nds32_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
441{
442 regnum -= gdbarch_num_regs (gdbarch);
443
444 /* Currently, only FSRs could be defined as pseudo registers. */
445 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
446 return nds32_fsr_register_names[regnum];
447
448 warning (_("Unknown nds32 pseudo register %d."), regnum);
449 return NULL;
450}
451
452/* Implement the "pseudo_register_read" gdbarch method. */
453
454static enum register_status
455nds32_pseudo_register_read (struct gdbarch *gdbarch,
456 struct regcache *regcache, int regnum,
457 gdb_byte *buf)
458{
459 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
460 gdb_byte reg_buf[8];
461 int offset, fdr_regnum;
462 enum register_status status = REG_UNKNOWN;
463
464 /* Sanity check. */
465 if (tdep->fpu_freg == -1 || tdep->use_pseudo_fsrs == 0)
466 return status;
467
468 regnum -= gdbarch_num_regs (gdbarch);
469
470 /* Currently, only FSRs could be defined as pseudo registers. */
471 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
472 {
473 /* fs0 is always the most significant half of fd0. */
474 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
475 offset = (regnum & 1) ? 4 : 0;
476 else
477 offset = (regnum & 1) ? 0 : 4;
478
479 fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
480 status = regcache_raw_read (regcache, fdr_regnum, reg_buf);
481 if (status == REG_VALID)
482 memcpy (buf, reg_buf + offset, 4);
483 }
484
485 return status;
486}
487
488/* Implement the "pseudo_register_write" gdbarch method. */
489
490static void
491nds32_pseudo_register_write (struct gdbarch *gdbarch,
492 struct regcache *regcache, int regnum,
493 const gdb_byte *buf)
494{
495 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
496 gdb_byte reg_buf[8];
497 int offset, fdr_regnum;
498
499 /* Sanity check. */
500 if (tdep->fpu_freg == -1 || tdep->use_pseudo_fsrs == 0)
501 return;
502
503 regnum -= gdbarch_num_regs (gdbarch);
504
505 /* Currently, only FSRs could be defined as pseudo registers. */
506 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
507 {
508 /* fs0 is always the most significant half of fd0. */
509 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
510 offset = (regnum & 1) ? 4 : 0;
511 else
512 offset = (regnum & 1) ? 0 : 4;
513
514 fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
515 regcache_raw_read (regcache, fdr_regnum, reg_buf);
516 memcpy (reg_buf + offset, buf, 4);
517 regcache_raw_write (regcache, fdr_regnum, reg_buf);
518 }
519}
520\f
521/* Helper function for NDS32 ABI. Return true if FPRs can be used
522 to pass function arguments and return value. */
523
524static int
525nds32_abi_use_fpr (int elf_abi)
526{
527 return elf_abi == E_NDS_ABI_V2FP_PLUS;
528}
529
530/* Helper function for NDS32 ABI. Return true if GPRs and stack
531 can be used together to pass an argument. */
532
533static int
534nds32_abi_split (int elf_abi)
535{
536 return elf_abi == E_NDS_ABI_AABI;
537}
538
539#define NDS32_NUM_SAVED_REGS (NDS32_LP_REGNUM + 1)
540
541struct nds32_frame_cache
542{
543 /* The previous frame's inner most stack address. Used as this
544 frame ID's stack_addr. */
545 CORE_ADDR prev_sp;
546
547 /* The frame's base, optionally used by the high-level debug info. */
548 CORE_ADDR base;
549
550 /* During prologue analysis, keep how far the SP and FP have been offset
551 from the start of the stack frame (as defined by the previous frame's
552 stack pointer).
553 During epilogue analysis, keep how far the SP has been offset from the
554 current stack pointer. */
555 CORE_ADDR sp_offset;
556 CORE_ADDR fp_offset;
557
558 /* The address of the first instruction in this function. */
559 CORE_ADDR pc;
560
561 /* Saved registers. */
562 CORE_ADDR saved_regs[NDS32_NUM_SAVED_REGS];
563};
564
565/* Allocate and initialize a frame cache. */
566
567static struct nds32_frame_cache *
568nds32_alloc_frame_cache (void)
569{
570 struct nds32_frame_cache *cache;
571 int i;
572
573 cache = FRAME_OBSTACK_ZALLOC (struct nds32_frame_cache);
574
575 /* Initialize fp_offset to check if FP is set in prologue. */
576 cache->fp_offset = INVALID_OFFSET;
577
578 /* Saved registers. We initialize these to -1 since zero is a valid
579 offset. */
580 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
581 cache->saved_regs[i] = REG_UNAVAIL;
582
583 return cache;
584}
585
586/* Helper function for instructions used to push multiple words. */
587
588static void
589nds32_push_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
590 int enable4)
591{
592 CORE_ADDR sp_offset = cache->sp_offset;
593 int i;
594
595 /* Check LP, GP, FP in enable4. */
596 for (i = 1; i <= 3; i++)
597 {
598 if ((enable4 >> i) & 0x1)
599 {
600 sp_offset += 4;
601 cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
602 }
603 }
604
605 /* Skip case where re == rb == sp. */
606 if ((rb < REG_FP) && (re < REG_FP))
607 {
608 for (i = re; i >= rb; i--)
609 {
610 sp_offset += 4;
611 cache->saved_regs[i] = sp_offset;
612 }
613 }
614
615 /* For sp, update the offset. */
616 cache->sp_offset = sp_offset;
617}
618
619/* Analyze the instructions within the given address range. If CACHE
620 is non-NULL, fill it in. Return the first address beyond the given
621 address range. If CACHE is NULL, return the first address not
622 recognized as a prologue instruction. */
623
624static CORE_ADDR
625nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
626 CORE_ADDR limit_pc, struct nds32_frame_cache *cache)
627{
628 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
629 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
630 /* Current scanning status. */
631 int in_prologue_bb = 0;
632 int val_ta = 0;
633 uint32_t insn, insn_len;
634
635 for (; pc < limit_pc; pc += insn_len)
636 {
637 insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
638
639 if ((insn & 0x80000000) == 0)
640 {
641 /* 32-bit instruction */
642 insn_len = 4;
643
644 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0))
645 {
646 /* addi $sp, $sp, imm15s */
647 int imm15s = N32_IMM15S (insn);
648
649 if (imm15s < 0)
650 {
651 if (cache != NULL)
652 cache->sp_offset += -imm15s;
653
654 in_prologue_bb = 1;
655 continue;
656 }
657 }
658 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_FP, REG_SP, 0))
659 {
660 /* addi $fp, $sp, imm15s */
661 int imm15s = N32_IMM15S (insn);
662
663 if (imm15s > 0)
664 {
665 if (cache != NULL)
666 cache->fp_offset = cache->sp_offset - imm15s;
667
668 in_prologue_bb = 1;
669 continue;
670 }
671 }
672 else if ((insn & ~(__MASK (19) << 6)) == N32_SMW_ADM
673 && N32_RA5 (insn) == REG_SP)
674 {
675 /* smw.adm Rb, [$sp], Re, enable4 */
676 if (cache != NULL)
677 nds32_push_multiple_words (cache, N32_RT5 (insn),
678 N32_RB5 (insn),
679 N32_LSMW_ENABLE4 (insn));
680 in_prologue_bb = 1;
681 continue;
682 }
683 else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
684 || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
685 {
686 /* add $sp, $sp, $ta */
687 /* add $sp, $ta, $sp */
688 if (val_ta < 0)
689 {
690 if (cache != NULL)
691 cache->sp_offset += -val_ta;
692
693 in_prologue_bb = 1;
694 continue;
695 }
696 }
697 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_TA, 0))
698 {
699 /* movi $ta, imm20s */
700 if (cache != NULL)
701 val_ta = N32_IMM20S (insn);
702
703 continue;
704 }
705 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_TA, 0))
706 {
707 /* sethi $ta, imm20u */
708 if (cache != NULL)
709 val_ta = N32_IMM20U (insn) << 12;
710
711 continue;
712 }
713 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_TA, REG_TA, 0))
714 {
715 /* ori $ta, $ta, imm15u */
716 if (cache != NULL)
717 val_ta |= N32_IMM15U (insn);
718
719 continue;
720 }
721 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_TA, REG_TA, 0))
722 {
723 /* addi $ta, $ta, imm15s */
724 if (cache != NULL)
725 val_ta += N32_IMM15S (insn);
726
727 continue;
728 }
729 if (insn == N32_ALU1 (ADD, REG_GP, REG_TA, REG_GP)
730 || insn == N32_ALU1 (ADD, REG_GP, REG_GP, REG_TA))
731 {
732 /* add $gp, $ta, $gp */
733 /* add $gp, $gp, $ta */
734 in_prologue_bb = 1;
735 continue;
736 }
737 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_GP, 0))
738 {
739 /* movi $gp, imm20s */
740 in_prologue_bb = 1;
741 continue;
742 }
743 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_GP, 0))
744 {
745 /* sethi $gp, imm20u */
746 in_prologue_bb = 1;
747 continue;
748 }
749 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_GP, REG_GP, 0))
750 {
751 /* ori $gp, $gp, imm15u */
752 in_prologue_bb = 1;
753 continue;
754 }
755 else
756 {
757 /* Jump/Branch insns never appear in prologue basic block.
758 The loop can be escaped early when these insns are met. */
759 if (in_prologue_bb == 1)
760 {
761 int op = N32_OP6 (insn);
762
763 if (op == N32_OP6_JI
764 || op == N32_OP6_JREG
765 || op == N32_OP6_BR1
766 || op == N32_OP6_BR2
767 || op == N32_OP6_BR3)
768 break;
769 }
770 }
771
772 if (abi_use_fpr && N32_OP6 (insn) == N32_OP6_SDC
773 && __GF (insn, 12, 3) == 0)
774 {
775 /* For FPU insns, CP (bit [13:14]) should be CP0, and only
776 normal form (bit [12] == 0) is used. */
777
778 /* fsdi FDt, [$sp + (imm12s << 2)] */
779 if (N32_RA5 (insn) == REG_SP)
780 continue;
781 }
782
783 /* The optimizer might shove anything into the prologue, if
784 we build up cache (cache != NULL) from analyzing prologue,
785 we just skip what we don't recognize and analyze further to
786 make cache as complete as possible. However, if we skip
787 prologue, we'll stop immediately on unrecognized
788 instruction. */
789 if (cache == NULL)
790 break;
791 }
792 else
793 {
794 /* 16-bit instruction */
795 insn_len = 2;
796
797 insn >>= 16;
798
799 if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
800 {
801 /* addi10s.sp */
802 int imm10s = N16_IMM10S (insn);
803
804 if (imm10s < 0)
805 {
806 if (cache != NULL)
807 cache->sp_offset += -imm10s;
808
809 in_prologue_bb = 1;
810 continue;
811 }
812 }
813 else if (__GF (insn, 7, 8) == N16_T25_PUSH25)
814 {
815 /* push25 */
816 if (cache != NULL)
817 {
818 int imm8u = (insn & 0x1f) << 3;
819 int re = (insn >> 5) & 0x3;
820 const int reg_map[] = { 6, 8, 10, 14 };
821
822 /* Operation 1 -- smw.adm R6, [$sp], Re, #0xe */
823 nds32_push_multiple_words (cache, 6, reg_map[re], 0xe);
824
825 /* Operation 2 -- sp = sp - (imm5u << 3) */
826 cache->sp_offset += imm8u;
827 }
828
829 in_prologue_bb = 1;
830 continue;
831 }
832 else if (insn == N16_TYPE5 (ADD5PC, REG_GP))
833 {
834 /* add5.pc $gp */
835 in_prologue_bb = 1;
836 continue;
837 }
838 else if (CHOP_BITS (insn, 5) == N16_TYPE55 (MOVI55, REG_GP, 0))
839 {
840 /* movi55 $gp, imm5s */
841 in_prologue_bb = 1;
842 continue;
843 }
844 else
845 {
846 /* Jump/Branch insns never appear in prologue basic block.
847 The loop can be escaped early when these insns are met. */
848 if (in_prologue_bb == 1)
849 {
850 uint32_t insn5 = CHOP_BITS (insn, 5);
851 uint32_t insn8 = CHOP_BITS (insn, 8);
852 uint32_t insn38 = CHOP_BITS (insn, 11);
853
854 if (insn5 == N16_TYPE5 (JR5, 0)
855 || insn5 == N16_TYPE5 (JRAL5, 0)
856 || insn5 == N16_TYPE5 (RET5, 0)
857 || insn8 == N16_TYPE8 (J8, 0)
858 || insn8 == N16_TYPE8 (BEQZS8, 0)
859 || insn8 == N16_TYPE8 (BNEZS8, 0)
860 || insn38 == N16_TYPE38 (BEQZ38, 0, 0)
861 || insn38 == N16_TYPE38 (BNEZ38, 0, 0)
862 || insn38 == N16_TYPE38 (BEQS38, 0, 0)
863 || insn38 == N16_TYPE38 (BNES38, 0, 0))
864 break;
865 }
866 }
867
868 /* The optimizer might shove anything into the prologue, if
869 we build up cache (cache != NULL) from analyzing prologue,
870 we just skip what we don't recognize and analyze further to
871 make cache as complete as possible. However, if we skip
872 prologue, we'll stop immediately on unrecognized
873 instruction. */
874 if (cache == NULL)
875 break;
876 }
877 }
878
879 return pc;
880}
881
882/* Implement the "skip_prologue" gdbarch method.
883
884 Find the end of function prologue. */
885
886static CORE_ADDR
887nds32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
888{
889 CORE_ADDR func_addr, limit_pc;
890
891 /* See if we can determine the end of the prologue via the symbol table.
892 If so, then return either PC, or the PC after the prologue, whichever
893 is greater. */
894 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
895 {
896 CORE_ADDR post_prologue_pc
897 = skip_prologue_using_sal (gdbarch, func_addr);
898 if (post_prologue_pc != 0)
325fac50 899 return std::max (pc, post_prologue_pc);
a28d8e50
YTL		 900 }
901
902 /* Can't determine prologue from the symbol table, need to examine
903 instructions. */
904
905 /* Find an upper limit on the function prologue using the debug
906 information. If the debug information could not be used to provide
907 that bound, then use an arbitrary large number as the upper bound. */
908 limit_pc = skip_prologue_using_sal (gdbarch, pc);
909 if (limit_pc == 0)
910 limit_pc = pc + 128; /* Magic. */
911
912 /* Find the end of prologue. */
913 return nds32_analyze_prologue (gdbarch, pc, limit_pc, NULL);
914}
915
916/* Allocate and fill in *THIS_CACHE with information about the prologue of
917 *THIS_FRAME. Do not do this if *THIS_CACHE was already allocated. Return
918 a pointer to the current nds32_frame_cache in *THIS_CACHE. */
919
920static struct nds32_frame_cache *
921nds32_frame_cache (struct frame_info *this_frame, void **this_cache)
922{
923 struct gdbarch *gdbarch = get_frame_arch (this_frame);
924 struct nds32_frame_cache *cache;
925 CORE_ADDR current_pc;
926 ULONGEST prev_sp;
927 ULONGEST this_base;
928 int i;
929
930 if (*this_cache)
931 return (struct nds32_frame_cache *) *this_cache;
932
933 cache = nds32_alloc_frame_cache ();
934 *this_cache = cache;
935
936 cache->pc = get_frame_func (this_frame);
937 current_pc = get_frame_pc (this_frame);
938 nds32_analyze_prologue (gdbarch, cache->pc, current_pc, cache);
939
940 /* Compute the previous frame's stack pointer (which is also the
941 frame's ID's stack address), and this frame's base pointer. */
942 if (cache->fp_offset != INVALID_OFFSET)
943 {
944 /* FP is set in prologue, so it can be used to calculate other info. */
945 this_base = get_frame_register_unsigned (this_frame, NDS32_FP_REGNUM);
946 prev_sp = this_base + cache->fp_offset;
947 }
948 else
949 {
950 this_base = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
951 prev_sp = this_base + cache->sp_offset;
952 }
953
954 cache->prev_sp = prev_sp;
955 cache->base = this_base;
956
957 /* Adjust all the saved registers such that they contain addresses
958 instead of offsets. */
959 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
960 if (cache->saved_regs[i] != REG_UNAVAIL)
961 cache->saved_regs[i] = cache->prev_sp - cache->saved_regs[i];
962
963 return cache;
964}
965
966/* Implement the "this_id" frame_unwind method.
967
968 Our frame ID for a normal frame is the current function's starting
969 PC and the caller's SP when we were called. */
970
971static void
972nds32_frame_this_id (struct frame_info *this_frame,
973 void **this_cache, struct frame_id *this_id)
974{
975 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
976
977 /* This marks the outermost frame. */
978 if (cache->prev_sp == 0)
979 return;
980
981 *this_id = frame_id_build (cache->prev_sp, cache->pc);
982}
983
984/* Implement the "prev_register" frame_unwind method. */
985
986static struct value *
987nds32_frame_prev_register (struct frame_info *this_frame, void **this_cache,
988 int regnum)
989{
990 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
991
992 if (regnum == NDS32_SP_REGNUM)
993 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
994
995 /* The PC of the previous frame is stored in the LP register of
996 the current frame. */
997 if (regnum == NDS32_PC_REGNUM)
998 regnum = NDS32_LP_REGNUM;
999
1000 if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
1001 return frame_unwind_got_memory (this_frame, regnum,
1002 cache->saved_regs[regnum]);
1003
1004 return frame_unwind_got_register (this_frame, regnum, regnum);
1005}
1006
1007static const struct frame_unwind nds32_frame_unwind =
1008{
1009 NORMAL_FRAME,
1010 default_frame_unwind_stop_reason,
1011 nds32_frame_this_id,
1012 nds32_frame_prev_register,
1013 NULL,
1014 default_frame_sniffer,
1015};
1016
1017/* Return the frame base address of *THIS_FRAME. */
1018
1019static CORE_ADDR
1020nds32_frame_base_address (struct frame_info *this_frame, void **this_cache)
1021{
1022 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
1023
1024 return cache->base;
1025}
1026
1027static const struct frame_base nds32_frame_base =
1028{
1029 &nds32_frame_unwind,
1030 nds32_frame_base_address,
1031 nds32_frame_base_address,
1032 nds32_frame_base_address
1033};
1034\f
1035/* Helper function for instructions used to pop multiple words. */
1036
1037static void
1038nds32_pop_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
1039 int enable4)
1040{
1041 CORE_ADDR sp_offset = cache->sp_offset;
1042 int i;
1043
1044 /* Skip case where re == rb == sp. */
1045 if ((rb < REG_FP) && (re < REG_FP))
1046 {
1047 for (i = rb; i <= re; i++)
1048 {
1049 cache->saved_regs[i] = sp_offset;
1050 sp_offset += 4;
1051 }
1052 }
1053
1054 /* Check FP, GP, LP in enable4. */
1055 for (i = 3; i >= 1; i--)
1056 {
1057 if ((enable4 >> i) & 0x1)
1058 {
1059 cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
1060 sp_offset += 4;
1061 }
1062 }
1063
1064 /* For sp, update the offset. */
1065 cache->sp_offset = sp_offset;
1066}
1067
1068/* The instruction sequences in NDS32 epilogue are
1069
1070 INSN_RESET_SP (optional)
1071 (If exists, this must be the first instruction in epilogue
1072 and the stack has not been destroyed.).
1073 INSN_RECOVER (optional).
1074 INSN_RETURN/INSN_RECOVER_RETURN (required). */
1075
1076/* Helper function for analyzing the given 32-bit INSN. If CACHE is non-NULL,
1077 the necessary information will be recorded. */
1078
1079static inline int
1080nds32_analyze_epilogue_insn32 (int abi_use_fpr, uint32_t insn,
1081 struct nds32_frame_cache *cache)
1082{
1083 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0)
1084 && N32_IMM15S (insn) > 0)
1085 /* addi $sp, $sp, imm15s */
1086 return INSN_RESET_SP;
1087 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_FP, 0)
1088 && N32_IMM15S (insn) < 0)
1089 /* addi $sp, $fp, imm15s */
1090 return INSN_RESET_SP;
1091 else if ((insn & ~(__MASK (19) << 6)) == N32_LMW_BIM
1092 && N32_RA5 (insn) == REG_SP)
1093 {
1094 /* lmw.bim Rb, [$sp], Re, enable4 */
1095 if (cache != NULL)
1096 nds32_pop_multiple_words (cache, N32_RT5 (insn),
1097 N32_RB5 (insn), N32_LSMW_ENABLE4 (insn));
1098
1099 return INSN_RECOVER;
1100 }
1101 else if (insn == N32_JREG (JR, 0, REG_LP, 0, 1))
1102 /* ret $lp */
1103 return INSN_RETURN;
1104 else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
1105 || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
1106 /* add $sp, $sp, $ta */
1107 /* add $sp, $ta, $sp */
1108 return INSN_RESET_SP;
1109 else if (abi_use_fpr
1110 && (insn & ~(__MASK (5) << 20 | __MASK (13))) == N32_FLDI_SP)
1111 {
1112 if (__GF (insn, 12, 1) == 0)
1113 /* fldi FDt, [$sp + (imm12s << 2)] */
1114 return INSN_RECOVER;
1115 else
1116 {
1117 /* fldi.bi FDt, [$sp], (imm12s << 2) */
1118 int offset = N32_IMM12S (insn) << 2;
1119
1120 if (offset == 8 || offset == 12)
1121 {
1122 if (cache != NULL)
1123 cache->sp_offset += offset;
1124
1125 return INSN_RECOVER;
1126 }
1127 }
1128 }
1129
1130 return INSN_NORMAL;
1131}
1132
1133/* Helper function for analyzing the given 16-bit INSN. If CACHE is non-NULL,
1134 the necessary information will be recorded. */
1135
1136static inline int
1137nds32_analyze_epilogue_insn16 (uint32_t insn, struct nds32_frame_cache *cache)
1138{
1139 if (insn == N16_TYPE5 (RET5, REG_LP))
1140 /* ret5 $lp */
1141 return INSN_RETURN;
1142 else if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
1143 {
1144 /* addi10s.sp */
1145 int imm10s = N16_IMM10S (insn);
1146
1147 if (imm10s > 0)
1148 {
1149 if (cache != NULL)
1150 cache->sp_offset += imm10s;
1151
1152 return INSN_RECOVER;
1153 }
1154 }
1155 else if (__GF (insn, 7, 8) == N16_T25_POP25)
1156 {
1157 /* pop25 */
1158 if (cache != NULL)
1159 {
1160 int imm8u = (insn & 0x1f) << 3;
1161 int re = (insn >> 5) & 0x3;
1162 const int reg_map[] = { 6, 8, 10, 14 };
1163
1164 /* Operation 1 -- sp = sp + (imm5u << 3) */
1165 cache->sp_offset += imm8u;
1166
1167 /* Operation 2 -- lmw.bim R6, [$sp], Re, #0xe */
1168 nds32_pop_multiple_words (cache, 6, reg_map[re], 0xe);
1169 }
1170
1171 /* Operation 3 -- ret $lp */
1172 return INSN_RECOVER_RETURN;
1173 }
1174
1175 return INSN_NORMAL;
1176}
1177
1178/* Analyze a reasonable amount of instructions from the given PC to find
1179 the instruction used to return to the caller. Return 1 if the 'return'
1180 instruction could be found, 0 otherwise.
1181
1182 If CACHE is non-NULL, fill it in. */
1183
1184static int
1185nds32_analyze_epilogue (struct gdbarch *gdbarch, CORE_ADDR pc,
1186 struct nds32_frame_cache *cache)
1187{
1188 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1189 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1190 CORE_ADDR limit_pc;
1191 uint32_t insn, insn_len;
1192 int insn_type = INSN_NORMAL;
1193
1194 if (abi_use_fpr)
1195 limit_pc = pc + 48;
1196 else
1197 limit_pc = pc + 16;
1198
1199 for (; pc < limit_pc; pc += insn_len)
1200 {
1201 insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
1202
1203 if ((insn & 0x80000000) == 0)
1204 {
1205 /* 32-bit instruction */
1206 insn_len = 4;
1207
1208 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, cache);
1209 if (insn_type == INSN_RETURN)
1210 return 1;
1211 else if (insn_type == INSN_RECOVER)
1212 continue;
1213 }
1214 else
1215 {
1216 /* 16-bit instruction */
1217 insn_len = 2;
1218
1219 insn >>= 16;
1220 insn_type = nds32_analyze_epilogue_insn16 (insn, cache);
1221 if (insn_type == INSN_RETURN || insn_type == INSN_RECOVER_RETURN)
1222 return 1;
1223 else if (insn_type == INSN_RECOVER)
1224 continue;
1225 }
1226
1227 /* Stop the scan if this is an unexpected instruction. */
1228 break;
1229 }
1230
1231 return 0;
1232}
1233
1234/* Implement the "stack_frame_destroyed_p" gdbarch method. */
1235
1236static int
1237nds32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR addr)
1238{
1239 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1240 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1241 int insn_type = INSN_NORMAL;
1242 int ret_found = 0;
1243 uint32_t insn;
1244
1245 insn = read_memory_unsigned_integer (addr, 4, BFD_ENDIAN_BIG);
1246
1247 if ((insn & 0x80000000) == 0)
1248 {
1249 /* 32-bit instruction */
1250
1251 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1252 }
1253 else
1254 {
1255 /* 16-bit instruction */
1256
1257 insn >>= 16;
1258 insn_type = nds32_analyze_epilogue_insn16 (insn, NULL);
1259 }
1260
1261 if (insn_type == INSN_NORMAL || insn_type == INSN_RESET_SP)
1262 return 0;
1263
1264 /* Search the required 'return' instruction within the following reasonable
1265 instructions. */
1266 ret_found = nds32_analyze_epilogue (gdbarch, addr, NULL);
1267 if (ret_found == 0)
1268 return 0;
1269
1270 /* Scan backwards to make sure that the last instruction has adjusted
1271 stack. Both a 16-bit and a 32-bit instruction will be tried. This is
1272 just a heuristic, so the false positives will be acceptable. */
1273 insn = read_memory_unsigned_integer (addr - 2, 4, BFD_ENDIAN_BIG);
1274
1275 /* Only 16-bit instructions are possible at addr - 2. */
1276 if ((insn & 0x80000000) != 0)
1277 {
1278 /* This may be a 16-bit instruction or part of a 32-bit instruction. */
1279
1280 insn_type = nds32_analyze_epilogue_insn16 (insn >> 16, NULL);
1281 if (insn_type == INSN_RECOVER)
1282 return 1;
1283 }
1284
1285 insn = read_memory_unsigned_integer (addr - 4, 4, BFD_ENDIAN_BIG);
1286
1287 /* If this is a 16-bit instruction at addr - 4, then there must be another
1288 16-bit instruction at addr - 2, so only 32-bit instructions need to
1289 be analyzed here. */
1290 if ((insn & 0x80000000) == 0)
1291 {
1292 /* This may be a 32-bit instruction or part of a 32-bit instruction. */
1293
1294 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1295 if (insn_type == INSN_RECOVER || insn_type == INSN_RESET_SP)
1296 return 1;
1297 }
1298
1299 return 0;
1300}
1301
1302/* Implement the "sniffer" frame_unwind method. */
1303
1304static int
1305nds32_epilogue_frame_sniffer (const struct frame_unwind *self,
1306 struct frame_info *this_frame, void **this_cache)
1307{
1308 if (frame_relative_level (this_frame) == 0)
1309 return nds32_stack_frame_destroyed_p (get_frame_arch (this_frame),
1310 get_frame_pc (this_frame));
1311 else
1312 return 0;
1313}
1314
1315/* Allocate and fill in *THIS_CACHE with information needed to unwind
1316 *THIS_FRAME within epilogue. Do not do this if *THIS_CACHE was already
1317 allocated. Return a pointer to the current nds32_frame_cache in
1318 *THIS_CACHE. */
1319
1320static struct nds32_frame_cache *
1321nds32_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
1322{
1323 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1324 struct nds32_frame_cache *cache;
1325 CORE_ADDR current_pc, current_sp;
1326 int i;
1327
1328 if (*this_cache)
1329 return (struct nds32_frame_cache *) *this_cache;
1330
1331 cache = nds32_alloc_frame_cache ();
1332 *this_cache = cache;
1333
1334 cache->pc = get_frame_func (this_frame);
1335 current_pc = get_frame_pc (this_frame);
1336 nds32_analyze_epilogue (gdbarch, current_pc, cache);
1337
1338 current_sp = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
1339 cache->prev_sp = current_sp + cache->sp_offset;
1340
1341 /* Adjust all the saved registers such that they contain addresses
1342 instead of offsets. */
1343 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
1344 if (cache->saved_regs[i] != REG_UNAVAIL)
1345 cache->saved_regs[i] = current_sp + cache->saved_regs[i];
1346
1347 return cache;
1348}
1349
1350/* Implement the "this_id" frame_unwind method. */
1351
1352static void
1353nds32_epilogue_frame_this_id (struct frame_info *this_frame,
1354 void **this_cache, struct frame_id *this_id)
1355{
1356 struct nds32_frame_cache *cache
1357 = nds32_epilogue_frame_cache (this_frame, this_cache);
1358
1359 /* This marks the outermost frame. */
1360 if (cache->prev_sp == 0)
1361 return;
1362
1363 *this_id = frame_id_build (cache->prev_sp, cache->pc);
1364}
1365
1366/* Implement the "prev_register" frame_unwind method. */
1367
1368static struct value *
1369nds32_epilogue_frame_prev_register (struct frame_info *this_frame,
1370 void **this_cache, int regnum)
1371{
1372 struct nds32_frame_cache *cache
1373 = nds32_epilogue_frame_cache (this_frame, this_cache);
1374
1375 if (regnum == NDS32_SP_REGNUM)
1376 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
1377
1378 /* The PC of the previous frame is stored in the LP register of
1379 the current frame. */
1380 if (regnum == NDS32_PC_REGNUM)
1381 regnum = NDS32_LP_REGNUM;
1382
1383 if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
1384 return frame_unwind_got_memory (this_frame, regnum,
1385 cache->saved_regs[regnum]);
1386
1387 return frame_unwind_got_register (this_frame, regnum, regnum);
1388}
1389
1390static const struct frame_unwind nds32_epilogue_frame_unwind =
1391{
1392 NORMAL_FRAME,
1393 default_frame_unwind_stop_reason,
1394 nds32_epilogue_frame_this_id,
1395 nds32_epilogue_frame_prev_register,
1396 NULL,
1397 nds32_epilogue_frame_sniffer
1398};
1399\f
1400/* Implement the "dummy_id" gdbarch method. */
1401
1402static struct frame_id
1403nds32_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1404{
1405 CORE_ADDR sp = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
1406
1407 return frame_id_build (sp, get_frame_pc (this_frame));
1408}
1409
1410/* Implement the "unwind_pc" gdbarch method. */
1411
1412static CORE_ADDR
1413nds32_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1414{
1415 return frame_unwind_register_unsigned (next_frame, NDS32_PC_REGNUM);
1416}
1417
1418/* Implement the "unwind_sp" gdbarch method. */
1419
1420static CORE_ADDR
1421nds32_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1422{
1423 return frame_unwind_register_unsigned (next_frame, NDS32_SP_REGNUM);
1424}
1425\f
1426/* Floating type and struct type that has only one floating type member
1427 can pass value using FPU registers (when FPU ABI is used). */
1428
1429static int
1430nds32_check_calling_use_fpr (struct type *type)
1431{
1432 struct type *t;
1433 enum type_code typecode;
1434
1435 t = type;
1436 while (1)
1437 {
1438 t = check_typedef (t);
1439 typecode = TYPE_CODE (t);
1440 if (typecode != TYPE_CODE_STRUCT)
1441 break;
1442 else if (TYPE_NFIELDS (t) != 1)
1443 return 0;
1444 else
1445 t = TYPE_FIELD_TYPE (t, 0);
1446 }
1447
1448 return typecode == TYPE_CODE_FLT;
1449}
1450
1451/* Return the alignment (in bytes) of the given type. */
1452
1453static int
1454nds32_type_align (struct type *type)
1455{
1456 int n;
1457 int align;
1458 int falign;
1459
1460 type = check_typedef (type);
1461 switch (TYPE_CODE (type))
1462 {
1463 default:
1464 /* Should never happen. */
1465 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1466 return 4;
1467
1468 case TYPE_CODE_PTR:
1469 case TYPE_CODE_ENUM:
1470 case TYPE_CODE_INT:
1471 case TYPE_CODE_FLT:
1472 case TYPE_CODE_SET:
1473 case TYPE_CODE_RANGE:
1474 case TYPE_CODE_REF:
1475 case TYPE_CODE_CHAR:
1476 case TYPE_CODE_BOOL:
1477 return TYPE_LENGTH (type);
1478
1479 case TYPE_CODE_ARRAY:
1480 case TYPE_CODE_COMPLEX:
1481 return nds32_type_align (TYPE_TARGET_TYPE (type));
1482
1483 case TYPE_CODE_STRUCT:
1484 case TYPE_CODE_UNION:
1485 align = 1;
1486 for (n = 0; n < TYPE_NFIELDS (type); n++)
1487 {
1488 falign = nds32_type_align (TYPE_FIELD_TYPE (type, n));
1489 if (falign > align)
1490 align = falign;
1491 }
1492 return align;
1493 }
1494}
1495
1496/* Implement the "push_dummy_call" gdbarch method. */
1497
1498static CORE_ADDR
1499nds32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1500 struct regcache *regcache, CORE_ADDR bp_addr,
1501 int nargs, struct value **args, CORE_ADDR sp,
1502 int struct_return, CORE_ADDR struct_addr)
1503{
1504 const int REND = 6; /* End for register offset. */
1505 int goff = 0; /* Current gpr offset for argument. */
1506 int foff = 0; /* Current fpr offset for argument. */
1507 int soff = 0; /* Current stack offset for argument. */
1508 int i;
1509 ULONGEST regval;
1510 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1511 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1512 struct type *func_type = value_type (function);
1513 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1514 int abi_split = nds32_abi_split (tdep->elf_abi);
1515
1516 /* Set the return address. For the NDS32, the return breakpoint is
1517 always at BP_ADDR. */
1518 regcache_cooked_write_unsigned (regcache, NDS32_LP_REGNUM, bp_addr);
1519
1520 /* If STRUCT_RETURN is true, then the struct return address (in
1521 STRUCT_ADDR) will consume the first argument-passing register.
1522 Both adjust the register count and store that value. */
1523 if (struct_return)
1524 {
1525 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, struct_addr);
1526 goff++;
1527 }
1528
1529 /* Now make sure there's space on the stack */
1530 for (i = 0; i < nargs; i++)
1531 {
1532 struct type *type = value_type (args[i]);
1533 int align = nds32_type_align (type);
1534
1535 /* If align is zero, it may be an empty struct.
1536 Just ignore the argument of empty struct. */
1537 if (align == 0)
1538 continue;
1539
1540 sp -= TYPE_LENGTH (type);
1541 sp = align_down (sp, align);
1542 }
1543
1544 /* Stack must be 8-byte aligned. */
1545 sp = align_down (sp, 8);
1546
1547 soff = 0;
1548 for (i = 0; i < nargs; i++)
1549 {
1550 const gdb_byte *val;
1551 int align, len;
1552 struct type *type;
1553 int calling_use_fpr;
1554 int use_fpr = 0;
1555
1556 type = value_type (args[i]);
1557 calling_use_fpr = nds32_check_calling_use_fpr (type);
1558 len = TYPE_LENGTH (type);
1559 align = nds32_type_align (type);
1560 val = value_contents (args[i]);
1561
1562 /* The size of a composite type larger than 4 bytes will be rounded
1563 up to the nearest multiple of 4. */
1564 if (len > 4)
1565 len = align_up (len, 4);
1566
1567 /* Variadic functions are handled differently between AABI and ABI2FP+.
1568
1569 For AABI, the caller pushes arguments in registers, callee stores
1570 unnamed arguments in stack, and then va_arg fetch arguments in stack.
1571 Therefore, we don't have to handle variadic functions specially.
1572
1573 For ABI2FP+, the caller pushes only named arguments in registers
1574 and pushes all unnamed arguments in stack. */
1575
1576 if (abi_use_fpr && TYPE_VARARGS (func_type)
1577 && i >= TYPE_NFIELDS (func_type))
1578 goto use_stack;
1579
1580 /* Try to use FPRs to pass arguments only when
1581 1. The program is built using toolchain with FPU support.
1582 2. The type of this argument can use FPR to pass value. */
1583 use_fpr = abi_use_fpr && calling_use_fpr;
1584
1585 if (use_fpr)
1586 {
1587 if (tdep->fpu_freg == -1)
1588 goto error_no_fpr;
1589
1590 /* Adjust alignment. */
1591 if ((align >> 2) > 0)
1592 foff = align_up (foff, align >> 2);
1593
1594 if (foff < REND)
1595 {
1596 switch (len)
1597 {
1598 case 4:
1599 regcache_cooked_write (regcache,
1600 tdep->fs0_regnum + foff, val);
1601 foff++;
1602 break;
1603 case 8:
1604 regcache_cooked_write (regcache,
1605 NDS32_FD0_REGNUM + (foff >> 1), val);
1606 foff += 2;
1607 break;
1608 default:
1609 /* Long double? */
1610 internal_error (__FILE__, __LINE__,
1611 "Do not know how to handle %d-byte double.\n",
1612 len);
1613 break;
1614 }
1615 continue;
1616 }
1617 }
1618 else
1619 {
1620 /*
1621 When passing arguments using GPRs,
1622
1623 * A composite type not larger than 4 bytes is passed in $rN.
1624 The format is as if the value is loaded with load instruction
1625 of corresponding size (e.g., LB, LH, LW).
1626
1627 For example,
1628
1629 r0
1630 31 0
1631 LITTLE: [x x b a]
1632 BIG: [x x a b]
1633
1634 * Otherwise, a composite type is passed in consecutive registers.
1635 The size is rounded up to the nearest multiple of 4.
1636 The successive registers hold the parts of the argument as if
1637 were loaded using lmw instructions.
1638
1639 For example,
1640
1641 r0 r1
1642 31 0 31 0
1643 LITTLE: [d c b a] [x x x e]
1644 BIG: [a b c d] [e x x x]
1645 */
1646
1647 /* Adjust alignment. */
1648 if ((align >> 2) > 0)
1649 goff = align_up (goff, align >> 2);
1650
1651 if (len <= (REND - goff) * 4)
1652 {
1653 /* This argument can be passed wholly via GPRs. */
1654 while (len > 0)
1655 {
1656 regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1657 byte_order);
1658 regcache_cooked_write_unsigned (regcache,
1659 NDS32_R0_REGNUM + goff,
1660 regval);
1661 len -= 4;
1662 val += 4;
1663 goff++;
1664 }
1665 continue;
1666 }
1667 else if (abi_split)
1668 {
1669 /* Some parts of this argument can be passed via GPRs. */
1670 while (goff < REND)
1671 {
1672 regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1673 byte_order);
1674 regcache_cooked_write_unsigned (regcache,
1675 NDS32_R0_REGNUM + goff,
1676 regval);
1677 len -= 4;
1678 val += 4;
1679 goff++;
1680 }
1681 }
1682 }
1683
1684use_stack:
1685 /*
1686 When pushing (split parts of) an argument into stack,
1687
1688 * A composite type not larger than 4 bytes is copied to different
1689 base address.
1690 In little-endian, the first byte of this argument is aligned
1691 at the low address of the next free word.
1692 In big-endian, the last byte of this argument is aligned
1693 at the high address of the next free word.
1694
1695 For example,
1696
1697 sp [ - ] [ c ] hi
1698 [ c ] [ b ]
1699 [ b ] [ a ]
1700 [ a ] [ - ] lo
1701 LITTLE BIG
1702 */
1703
1704 /* Adjust alignment. */
1705 soff = align_up (soff, align);
1706
1707 while (len > 0)
1708 {
1709 int rlen = (len > 4) ? 4 : len;
1710
1711 if (byte_order == BFD_ENDIAN_BIG)
1712 write_memory (sp + soff + 4 - rlen, val, rlen);
1713 else
1714 write_memory (sp + soff, val, rlen);
1715
1716 len -= 4;
1717 val += 4;
1718 soff += 4;
1719 }
1720 }
1721
1722 /* Finally, update the SP register. */
1723 regcache_cooked_write_unsigned (regcache, NDS32_SP_REGNUM, sp);
1724
1725 return sp;
1726
1727error_no_fpr:
1728 /* If use_fpr, but no floating-point register exists,
1729 then it is an error. */
1730 error (_("Fail to call. FPU registers are required."));
1731}
1732\f
1733/* Read, for architecture GDBARCH, a function return value of TYPE
1734 from REGCACHE, and copy that into VALBUF. */
1735
1736static void
1737nds32_extract_return_value (struct gdbarch *gdbarch, struct type *type,
1738 struct regcache *regcache, gdb_byte *valbuf)
1739{
1740 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1741 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1742 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1743 int calling_use_fpr;
1744 int len;
1745
1746 calling_use_fpr = nds32_check_calling_use_fpr (type);
1747 len = TYPE_LENGTH (type);
1748
1749 if (abi_use_fpr && calling_use_fpr)
1750 {
1751 if (len == 4)
1752 regcache_cooked_read (regcache, tdep->fs0_regnum, valbuf);
1753 else if (len == 8)
1754 regcache_cooked_read (regcache, NDS32_FD0_REGNUM, valbuf);
1755 else
1756 internal_error (__FILE__, __LINE__,
1757 _("Cannot extract return value of %d bytes "
1758 "long floating-point."), len);
1759 }
1760 else
1761 {
1762 /*
1763 When returning result,
1764
1765 * A composite type not larger than 4 bytes is returned in $r0.
1766 The format is as if the result is loaded with load instruction
1767 of corresponding size (e.g., LB, LH, LW).
1768
1769 For example,
1770
1771 r0
1772 31 0
1773 LITTLE: [x x b a]
1774 BIG: [x x a b]
1775
1776 * Otherwise, a composite type not larger than 8 bytes is returned
1777 in $r0 and $r1.
1778 In little-endian, the first word is loaded in $r0.
1779 In big-endian, the last word is loaded in $r1.
1780
1781 For example,
1782
1783 r0 r1
1784 31 0 31 0
1785 LITTLE: [d c b a] [x x x e]
1786 BIG: [x x x a] [b c d e]
1787 */
1788
1789 ULONGEST tmp;
1790
1791 if (len < 4)
1792 {
1793 /* By using store_unsigned_integer we avoid having to do
1794 anything special for small big-endian values. */
1795 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1796 store_unsigned_integer (valbuf, len, byte_order, tmp);
1797 }
1798 else if (len == 4)
1799 {
1800 regcache_cooked_read (regcache, NDS32_R0_REGNUM, valbuf);
1801 }
1802 else if (len < 8)
1803 {
1804 int len1, len2;
1805
1806 len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1807 len2 = len - len1;
1808
1809 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1810 store_unsigned_integer (valbuf, len1, byte_order, tmp);
1811
1812 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM + 1, &tmp);
1813 store_unsigned_integer (valbuf + len1, len2, byte_order, tmp);
1814 }
1815 else
1816 {
1817 regcache_cooked_read (regcache, NDS32_R0_REGNUM, valbuf);
1818 regcache_cooked_read (regcache, NDS32_R0_REGNUM + 1, valbuf + 4);
1819 }
1820 }
1821}
1822
1823/* Write, for architecture GDBARCH, a function return value of TYPE
1824 from VALBUF into REGCACHE. */
1825
1826static void
1827nds32_store_return_value (struct gdbarch *gdbarch, struct type *type,
1828 struct regcache *regcache, const gdb_byte *valbuf)
1829{
1830 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1831 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1832 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1833 int calling_use_fpr;
1834 int len;
1835
1836 calling_use_fpr = nds32_check_calling_use_fpr (type);
1837 len = TYPE_LENGTH (type);
1838
1839 if (abi_use_fpr && calling_use_fpr)
1840 {
1841 if (len == 4)
1842 regcache_cooked_write (regcache, tdep->fs0_regnum, valbuf);
1843 else if (len == 8)
1844 regcache_cooked_write (regcache, NDS32_FD0_REGNUM, valbuf);
1845 else
1846 internal_error (__FILE__, __LINE__,
1847 _("Cannot store return value of %d bytes "
1848 "long floating-point."), len);
1849 }
1850 else
1851 {
1852 ULONGEST regval;
1853
1854 if (len < 4)
1855 {
1856 regval = extract_unsigned_integer (valbuf, len, byte_order);
1857 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1858 }
1859 else if (len == 4)
1860 {
1861 regcache_cooked_write (regcache, NDS32_R0_REGNUM, valbuf);
1862 }
1863 else if (len < 8)
1864 {
1865 int len1, len2;
1866
1867 len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1868 len2 = len - len1;
1869
1870 regval = extract_unsigned_integer (valbuf, len1, byte_order);
1871 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1872
1873 regval = extract_unsigned_integer (valbuf + len1, len2, byte_order);
1874 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM + 1,
1875 regval);
1876 }
1877 else
1878 {
1879 regcache_cooked_write (regcache, NDS32_R0_REGNUM, valbuf);
1880 regcache_cooked_write (regcache, NDS32_R0_REGNUM + 1, valbuf + 4);
1881 }
1882 }
1883}
1884
1885/* Implement the "return_value" gdbarch method.
1886
1887 Determine, for architecture GDBARCH, how a return value of TYPE
1888 should be returned. If it is supposed to be returned in registers,
1889 and READBUF is non-zero, read the appropriate value from REGCACHE,
1890 and copy it into READBUF. If WRITEBUF is non-zero, write the value
1891 from WRITEBUF into REGCACHE. */
1892
1893static enum return_value_convention
1894nds32_return_value (struct gdbarch *gdbarch, struct value *func_type,
1895 struct type *type, struct regcache *regcache,
1896 gdb_byte *readbuf, const gdb_byte *writebuf)
1897{
1898 if (TYPE_LENGTH (type) > 8)
1899 {
1900 return RETURN_VALUE_STRUCT_CONVENTION;
1901 }
1902 else
1903 {
1904 if (readbuf != NULL)
1905 nds32_extract_return_value (gdbarch, type, regcache, readbuf);
1906 if (writebuf != NULL)
1907 nds32_store_return_value (gdbarch, type, regcache, writebuf);
1908
1909 return RETURN_VALUE_REGISTER_CONVENTION;
1910 }
1911}
1912\f
1913/* Implement the "get_longjmp_target" gdbarch method. */
1914
1915static int
1916nds32_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1917{
1918 gdb_byte buf[4];
1919 CORE_ADDR jb_addr;
1920 struct gdbarch *gdbarch = get_frame_arch (frame);
1921 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1922
1923 jb_addr = get_frame_register_unsigned (frame, NDS32_R0_REGNUM);
1924
1925 if (target_read_memory (jb_addr + 11 * 4, buf, 4))
1926 return 0;
1927
1928 *pc = extract_unsigned_integer (buf, 4, byte_order);
1929 return 1;
1930}
1931\f
1932/* Validate the given TDESC, and fixed-number some registers in it.
1933 Return 0 if the given TDESC does not contain the required feature
1934 or not contain required registers. */
1935
1936static int
1937nds32_validate_tdesc_p (const struct target_desc *tdesc,
1938 struct tdesc_arch_data *tdesc_data,
1939 int *fpu_freg, int *use_pseudo_fsrs)
1940{
1941 const struct tdesc_feature *feature;
1942 int i, valid_p;
1943
1944 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.core");
1945 if (feature == NULL)
1946 return 0;
1947
1948 valid_p = 1;
1949 /* Validate and fixed-number R0-R10. */
1950 for (i = NDS32_R0_REGNUM; i <= NDS32_R0_REGNUM + 10; i++)
1951 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1952 nds32_register_names[i]);
1953
1954 /* Validate R15. */
1955 valid_p &= tdesc_unnumbered_register (feature,
1956 nds32_register_names[NDS32_TA_REGNUM]);
1957
1958 /* Validate and fixed-number FP, GP, LP, SP, PC. */
1959 for (i = NDS32_FP_REGNUM; i <= NDS32_PC_REGNUM; i++)
1960 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1961 nds32_register_names[i]);
1962
1963 if (!valid_p)
1964 return 0;
1965
1966 /* Fixed-number R11-R27. */
1967 for (i = NDS32_R0_REGNUM + 11; i <= NDS32_R0_REGNUM + 27; i++)
1968 tdesc_numbered_register (feature, tdesc_data, i, nds32_register_names[i]);
1969
1970 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.fpu");
1971 if (feature != NULL)
1972 {
1973 int num_fdr_regs, num_fsr_regs, fs0_regnum, num_listed_fsr;
1974 int freg = -1;
1975
1976 /* Guess FPU configuration via listed registers. */
1977 if (tdesc_unnumbered_register (feature, "fd31"))
1978 freg = 3;
1979 else if (tdesc_unnumbered_register (feature, "fd15"))
1980 freg = 2;
1981 else if (tdesc_unnumbered_register (feature, "fd7"))
1982 freg = 1;
1983 else if (tdesc_unnumbered_register (feature, "fd3"))
1984 freg = 0;
1985
1986 if (freg == -1)
1987 /* Required FDR is not found. */
1988 return 0;
1989 else
1990 *fpu_freg = freg;
1991
1992 /* Validate and fixed-number required FDRs. */
1993 num_fdr_regs = num_fdr_map[freg];
1994 for (i = 0; i < num_fdr_regs; i++)
1995 valid_p &= tdesc_numbered_register (feature, tdesc_data,
1996 NDS32_FD0_REGNUM + i,
1997 nds32_fdr_register_names[i]);
1998 if (!valid_p)
1999 return 0;
2000
2001 /* Count the number of listed FSRs, and fixed-number them if present. */
2002 num_fsr_regs = num_fsr_map[freg];
2003 fs0_regnum = NDS32_FD0_REGNUM + num_fdr_regs;
2004 num_listed_fsr = 0;
2005 for (i = 0; i < num_fsr_regs; i++)
2006 num_listed_fsr += tdesc_numbered_register (feature, tdesc_data,
2007 fs0_regnum + i,
2008 nds32_fsr_register_names[i]);
2009
2010 if (num_listed_fsr == 0)
2011 /* No required FSRs are listed explicitly, make them pseudo registers
2012 of FDRs. */
2013 *use_pseudo_fsrs = 1;
2014 else if (num_listed_fsr == num_fsr_regs)
2015 /* All required FSRs are listed explicitly. */
2016 *use_pseudo_fsrs = 0;
2017 else
2018 /* Some required FSRs are missing. */
2019 return 0;
2020 }
2021
2022 return 1;
2023}
2024
2025/* Initialize the current architecture based on INFO. If possible,
2026 re-use an architecture from ARCHES, which is a list of
2027 architectures already created during this debugging session.
2028
2029 Called e.g. at program startup, when reading a core file, and when
2030 reading a binary file. */
2031
2032static struct gdbarch *
2033nds32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2034{
2035 struct gdbarch *gdbarch;
2036 struct gdbarch_tdep *tdep;
2037 struct gdbarch_list *best_arch;
2038 struct tdesc_arch_data *tdesc_data = NULL;
2039 const struct target_desc *tdesc = info.target_desc;
2040 int elf_abi = E_NDS_ABI_AABI;
2041 int fpu_freg = -1;
2042 int use_pseudo_fsrs = 0;
2043 int i, num_regs, maxregs;
2044
2045 /* Extract the elf_flags if available. */
2046 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2047 elf_abi = elf_elfheader (info.abfd)->e_flags & EF_NDS_ABI;
2048
2049 /* If there is already a candidate, use it. */
2050 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
2051 best_arch != NULL;
2052 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
2053 {
2054 struct gdbarch_tdep *idep = gdbarch_tdep (best_arch->gdbarch);
2055
2056 if (idep->elf_abi != elf_abi)
2057 continue;
2058
2059 /* Found a match. */
2060 break;
2061 }
2062
2063 if (best_arch != NULL)
2064 return best_arch->gdbarch;
2065
2066 if (!tdesc_has_registers (tdesc))
2067 tdesc = tdesc_nds32;
2068
2069 tdesc_data = tdesc_data_alloc ();
2070
2071 if (!nds32_validate_tdesc_p (tdesc, tdesc_data, &fpu_freg, &use_pseudo_fsrs))
2072 {
2073 tdesc_data_cleanup (tdesc_data);
2074 return NULL;
2075 }
2076
2077 /* Allocate space for the new architecture. */
2078 tdep = XCNEW (struct gdbarch_tdep);
2079 tdep->fpu_freg = fpu_freg;
2080 tdep->use_pseudo_fsrs = use_pseudo_fsrs;
2081 tdep->fs0_regnum = -1;
2082 tdep->elf_abi = elf_abi;
2083
2084 gdbarch = gdbarch_alloc (&info, tdep);
2085
2086 if (fpu_freg == -1)
2087 num_regs = NDS32_NUM_REGS;
2088 else if (use_pseudo_fsrs == 1)
2089 {
2090 set_gdbarch_pseudo_register_read (gdbarch, nds32_pseudo_register_read);
2091 set_gdbarch_pseudo_register_write (gdbarch, nds32_pseudo_register_write);
2092 set_tdesc_pseudo_register_name (gdbarch, nds32_pseudo_register_name);
2093 set_tdesc_pseudo_register_type (gdbarch, nds32_pseudo_register_type);
2094 set_gdbarch_num_pseudo_regs (gdbarch, num_fsr_map[fpu_freg]);
2095
2096 num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg];
2097 }
2098 else
2099 num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg] + num_fsr_map[fpu_freg];
2100
2101 set_gdbarch_num_regs (gdbarch, num_regs);
2102 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
2103
2104 /* Cache the register number of fs0. */
2105 if (fpu_freg != -1)
2106 tdep->fs0_regnum = user_reg_map_name_to_regnum (gdbarch, "fs0", -1);
2107
2108 /* Add NDS32 register aliases. To avoid search in user register name space,
2109 user_reg_map_name_to_regnum is not used. */
2110 maxregs = (gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch));
2111 for (i = 0; i < ARRAY_SIZE (nds32_register_aliases); i++)
2112 {
2113 int regnum, j;
2114
2115 regnum = -1;
2116 /* Search register name space. */
2117 for (j = 0; j < maxregs; j++)
2118 {
2119 const char *regname = gdbarch_register_name (gdbarch, j);
2120
2121 if (regname != NULL
2122 && strcmp (regname, nds32_register_aliases[i].name) == 0)
2123 {
2124 regnum = j;
2125 break;
2126 }
2127 }
2128
2129 /* Try next alias entry if the given name can not be found in register
2130 name space. */
2131 if (regnum == -1)
2132 continue;
2133
2134 user_reg_add (gdbarch, nds32_register_aliases[i].alias,
2135 value_of_nds32_reg, (const void *) (intptr_t) regnum);
2136 }
2137
2138 nds32_add_reggroups (gdbarch);
2139
2140 /* Hook in ABI-specific overrides, if they have been registered. */
2141 info.tdep_info = (void *) tdesc_data;
2142 gdbarch_init_osabi (info, gdbarch);
2143
2144 /* Override tdesc_register callbacks for system registers. */
2145 set_gdbarch_register_reggroup_p (gdbarch, nds32_register_reggroup_p);
2146
2147 set_gdbarch_sp_regnum (gdbarch, NDS32_SP_REGNUM);
2148 set_gdbarch_pc_regnum (gdbarch, NDS32_PC_REGNUM);
2149 set_gdbarch_unwind_sp (gdbarch, nds32_unwind_sp);
2150 set_gdbarch_unwind_pc (gdbarch, nds32_unwind_pc);
2151 set_gdbarch_stack_frame_destroyed_p (gdbarch, nds32_stack_frame_destroyed_p);
2152 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, nds32_dwarf2_reg_to_regnum);
2153
2154 set_gdbarch_push_dummy_call (gdbarch, nds32_push_dummy_call);
2155 set_gdbarch_return_value (gdbarch, nds32_return_value);
2156 set_gdbarch_dummy_id (gdbarch, nds32_dummy_id);
2157
2158 set_gdbarch_skip_prologue (gdbarch, nds32_skip_prologue);
2159 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2160 set_gdbarch_breakpoint_from_pc (gdbarch, nds32_breakpoint_from_pc);
2161
2162 set_gdbarch_frame_align (gdbarch, nds32_frame_align);
2163 frame_base_set_default (gdbarch, &nds32_frame_base);
2164
2165 set_gdbarch_print_insn (gdbarch, print_insn_nds32);
2166
2167 /* Handle longjmp. */
2168 set_gdbarch_get_longjmp_target (gdbarch, nds32_get_longjmp_target);
2169
2170 /* The order of appending is the order it check frame. */
2171 dwarf2_append_unwinders (gdbarch);
2172 frame_unwind_append_unwinder (gdbarch, &nds32_epilogue_frame_unwind);
2173 frame_unwind_append_unwinder (gdbarch, &nds32_frame_unwind);
2174
2175 return gdbarch;
2176}
2177
2178void
2179_initialize_nds32_tdep (void)
2180{
2181 /* Initialize gdbarch. */
2182 register_gdbarch_init (bfd_arch_nds32, nds32_gdbarch_init);
2183
2184 initialize_tdesc_nds32 ();
2185 nds32_init_reggroups ();
2186}
GDB Binutils - Deliverables
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