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9abe5450 | 1 | /* PPC GNU/Linux native support. |
2555fe1a | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002, 2003, |
0fb0cc75 | 4 | 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. |
c877c8e6 KB |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
c877c8e6 KB |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c877c8e6 KB |
20 | |
21 | #include "defs.h" | |
e162d11b | 22 | #include "gdb_string.h" |
c877c8e6 KB |
23 | #include "frame.h" |
24 | #include "inferior.h" | |
25 | #include "gdbcore.h" | |
4e052eda | 26 | #include "regcache.h" |
383f0f5b | 27 | #include "gdb_assert.h" |
10d6c8cd DJ |
28 | #include "target.h" |
29 | #include "linux-nat.h" | |
c877c8e6 | 30 | |
411cb3f9 | 31 | #include <stdint.h> |
c877c8e6 KB |
32 | #include <sys/types.h> |
33 | #include <sys/param.h> | |
34 | #include <signal.h> | |
35 | #include <sys/user.h> | |
36 | #include <sys/ioctl.h> | |
2555fe1a | 37 | #include "gdb_wait.h" |
c877c8e6 KB |
38 | #include <fcntl.h> |
39 | #include <sys/procfs.h> | |
45229ea4 | 40 | #include <sys/ptrace.h> |
c877c8e6 | 41 | |
c60c0f5f MS |
42 | /* Prototypes for supply_gregset etc. */ |
43 | #include "gregset.h" | |
16333c4f | 44 | #include "ppc-tdep.h" |
7284e1be UW |
45 | #include "ppc-linux-tdep.h" |
46 | ||
b7622095 LM |
47 | /* Required when using the AUXV. */ |
48 | #include "elf/common.h" | |
49 | #include "auxv.h" | |
50 | ||
7284e1be UW |
51 | /* This sometimes isn't defined. */ |
52 | #ifndef PT_ORIG_R3 | |
53 | #define PT_ORIG_R3 34 | |
54 | #endif | |
55 | #ifndef PT_TRAP | |
56 | #define PT_TRAP 40 | |
57 | #endif | |
c60c0f5f | 58 | |
69abc51c TJB |
59 | /* The PPC_FEATURE_* defines should be provided by <asm/cputable.h>. |
60 | If they aren't, we can provide them ourselves (their values are fixed | |
61 | because they are part of the kernel ABI). They are used in the AT_HWCAP | |
62 | entry of the AUXV. */ | |
b7622095 LM |
63 | #ifndef PPC_FEATURE_BOOKE |
64 | #define PPC_FEATURE_BOOKE 0x00008000 | |
65 | #endif | |
f04c6d38 TJB |
66 | #ifndef PPC_FEATURE_HAS_DFP |
67 | #define PPC_FEATURE_HAS_DFP 0x00000400 /* Decimal Floating Point. */ | |
69abc51c | 68 | #endif |
b7622095 | 69 | |
9abe5450 EZ |
70 | /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a |
71 | configure time check. Some older glibc's (for instance 2.2.1) | |
72 | don't have a specific powerpc version of ptrace.h, and fall back on | |
73 | a generic one. In such cases, sys/ptrace.h defines | |
74 | PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that | |
75 | ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and | |
76 | PTRACE_SETVRREGS to be. This also makes a configury check pretty | |
77 | much useless. */ | |
78 | ||
79 | /* These definitions should really come from the glibc header files, | |
80 | but Glibc doesn't know about the vrregs yet. */ | |
81 | #ifndef PTRACE_GETVRREGS | |
82 | #define PTRACE_GETVRREGS 18 | |
83 | #define PTRACE_SETVRREGS 19 | |
84 | #endif | |
85 | ||
604c2f83 LM |
86 | /* PTRACE requests for POWER7 VSX registers. */ |
87 | #ifndef PTRACE_GETVSXREGS | |
88 | #define PTRACE_GETVSXREGS 27 | |
89 | #define PTRACE_SETVSXREGS 28 | |
90 | #endif | |
01904826 JB |
91 | |
92 | /* Similarly for the ptrace requests for getting / setting the SPE | |
93 | registers (ev0 -- ev31, acc, and spefscr). See the description of | |
94 | gdb_evrregset_t for details. */ | |
95 | #ifndef PTRACE_GETEVRREGS | |
96 | #define PTRACE_GETEVRREGS 20 | |
97 | #define PTRACE_SETEVRREGS 21 | |
98 | #endif | |
99 | ||
e0d24f8d WZ |
100 | /* Similarly for the hardware watchpoint support. */ |
101 | #ifndef PTRACE_GET_DEBUGREG | |
102 | #define PTRACE_GET_DEBUGREG 25 | |
103 | #endif | |
104 | #ifndef PTRACE_SET_DEBUGREG | |
105 | #define PTRACE_SET_DEBUGREG 26 | |
106 | #endif | |
107 | #ifndef PTRACE_GETSIGINFO | |
108 | #define PTRACE_GETSIGINFO 0x4202 | |
109 | #endif | |
01904826 | 110 | |
9abe5450 EZ |
111 | /* This oddity is because the Linux kernel defines elf_vrregset_t as |
112 | an array of 33 16 bytes long elements. I.e. it leaves out vrsave. | |
113 | However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return | |
114 | the vrsave as an extra 4 bytes at the end. I opted for creating a | |
115 | flat array of chars, so that it is easier to manipulate for gdb. | |
116 | ||
117 | There are 32 vector registers 16 bytes longs, plus a VSCR register | |
118 | which is only 4 bytes long, but is fetched as a 16 bytes | |
119 | quantity. Up to here we have the elf_vrregset_t structure. | |
120 | Appended to this there is space for the VRSAVE register: 4 bytes. | |
121 | Even though this vrsave register is not included in the regset | |
122 | typedef, it is handled by the ptrace requests. | |
123 | ||
124 | Note that GNU/Linux doesn't support little endian PPC hardware, | |
125 | therefore the offset at which the real value of the VSCR register | |
126 | is located will be always 12 bytes. | |
127 | ||
128 | The layout is like this (where x is the actual value of the vscr reg): */ | |
129 | ||
130 | /* *INDENT-OFF* */ | |
131 | /* | |
132 | |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| | |
133 | <-------> <-------><-------><-> | |
134 | VR0 VR31 VSCR VRSAVE | |
135 | */ | |
136 | /* *INDENT-ON* */ | |
137 | ||
138 | #define SIZEOF_VRREGS 33*16+4 | |
139 | ||
140 | typedef char gdb_vrregset_t[SIZEOF_VRREGS]; | |
141 | ||
604c2f83 LM |
142 | /* This is the layout of the POWER7 VSX registers and the way they overlap |
143 | with the existing FPR and VMX registers. | |
144 | ||
145 | VSR doubleword 0 VSR doubleword 1 | |
146 | ---------------------------------------------------------------- | |
147 | VSR[0] | FPR[0] | | | |
148 | ---------------------------------------------------------------- | |
149 | VSR[1] | FPR[1] | | | |
150 | ---------------------------------------------------------------- | |
151 | | ... | | | |
152 | | ... | | | |
153 | ---------------------------------------------------------------- | |
154 | VSR[30] | FPR[30] | | | |
155 | ---------------------------------------------------------------- | |
156 | VSR[31] | FPR[31] | | | |
157 | ---------------------------------------------------------------- | |
158 | VSR[32] | VR[0] | | |
159 | ---------------------------------------------------------------- | |
160 | VSR[33] | VR[1] | | |
161 | ---------------------------------------------------------------- | |
162 | | ... | | |
163 | | ... | | |
164 | ---------------------------------------------------------------- | |
165 | VSR[62] | VR[30] | | |
166 | ---------------------------------------------------------------- | |
167 | VSR[63] | VR[31] | | |
168 | ---------------------------------------------------------------- | |
169 | ||
170 | VSX has 64 128bit registers. The first 32 registers overlap with | |
171 | the FP registers (doubleword 0) and hence extend them with additional | |
172 | 64 bits (doubleword 1). The other 32 regs overlap with the VMX | |
173 | registers. */ | |
174 | #define SIZEOF_VSXREGS 32*8 | |
175 | ||
176 | typedef char gdb_vsxregset_t[SIZEOF_VSXREGS]; | |
01904826 JB |
177 | |
178 | /* On PPC processors that support the the Signal Processing Extension | |
179 | (SPE) APU, the general-purpose registers are 64 bits long. | |
411cb3f9 PG |
180 | However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER |
181 | ptrace calls only access the lower half of each register, to allow | |
182 | them to behave the same way they do on non-SPE systems. There's a | |
183 | separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that | |
184 | read and write the top halves of all the general-purpose registers | |
185 | at once, along with some SPE-specific registers. | |
01904826 JB |
186 | |
187 | GDB itself continues to claim the general-purpose registers are 32 | |
6ced10dd JB |
188 | bits long. It has unnamed raw registers that hold the upper halves |
189 | of the gprs, and the the full 64-bit SIMD views of the registers, | |
190 | 'ev0' -- 'ev31', are pseudo-registers that splice the top and | |
191 | bottom halves together. | |
01904826 JB |
192 | |
193 | This is the structure filled in by PTRACE_GETEVRREGS and written to | |
194 | the inferior's registers by PTRACE_SETEVRREGS. */ | |
195 | struct gdb_evrregset_t | |
196 | { | |
197 | unsigned long evr[32]; | |
198 | unsigned long long acc; | |
199 | unsigned long spefscr; | |
200 | }; | |
201 | ||
604c2f83 LM |
202 | /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and |
203 | PTRACE_SETVSXREGS requests, for reading and writing the VSX | |
204 | POWER7 registers 0 through 31. Zero if we've tried one of them and | |
205 | gotten an error. Note that VSX registers 32 through 63 overlap | |
206 | with VR registers 0 through 31. */ | |
207 | int have_ptrace_getsetvsxregs = 1; | |
01904826 JB |
208 | |
209 | /* Non-zero if our kernel may support the PTRACE_GETVRREGS and | |
210 | PTRACE_SETVRREGS requests, for reading and writing the Altivec | |
211 | registers. Zero if we've tried one of them and gotten an | |
212 | error. */ | |
9abe5450 EZ |
213 | int have_ptrace_getvrregs = 1; |
214 | ||
01904826 JB |
215 | /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and |
216 | PTRACE_SETEVRREGS requests, for reading and writing the SPE | |
217 | registers. Zero if we've tried one of them and gotten an | |
218 | error. */ | |
219 | int have_ptrace_getsetevrregs = 1; | |
220 | ||
16333c4f EZ |
221 | /* *INDENT-OFF* */ |
222 | /* registers layout, as presented by the ptrace interface: | |
223 | PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, | |
224 | PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15, | |
225 | PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23, | |
226 | PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31, | |
227 | PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14, | |
228 | PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30, | |
229 | PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46, | |
230 | PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62, | |
231 | PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */ | |
232 | /* *INDENT_ON * */ | |
c877c8e6 | 233 | |
45229ea4 | 234 | static int |
e101270f | 235 | ppc_register_u_addr (struct gdbarch *gdbarch, int regno) |
c877c8e6 | 236 | { |
16333c4f | 237 | int u_addr = -1; |
e101270f | 238 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
56d0d96a AC |
239 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
240 | interface, and not the wordsize of the program's ABI. */ | |
411cb3f9 | 241 | int wordsize = sizeof (long); |
16333c4f EZ |
242 | |
243 | /* General purpose registers occupy 1 slot each in the buffer */ | |
8bf659e8 JB |
244 | if (regno >= tdep->ppc_gp0_regnum |
245 | && regno < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
26e75e5c | 246 | u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize); |
16333c4f | 247 | |
49ff75ad JB |
248 | /* Floating point regs: eight bytes each in both 32- and 64-bit |
249 | ptrace interfaces. Thus, two slots each in 32-bit interface, one | |
250 | slot each in 64-bit interface. */ | |
383f0f5b JB |
251 | if (tdep->ppc_fp0_regnum >= 0 |
252 | && regno >= tdep->ppc_fp0_regnum | |
366f009f JB |
253 | && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) |
254 | u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8); | |
16333c4f EZ |
255 | |
256 | /* UISA special purpose registers: 1 slot each */ | |
e101270f | 257 | if (regno == gdbarch_pc_regnum (gdbarch)) |
49ff75ad | 258 | u_addr = PT_NIP * wordsize; |
dc5cfeb6 | 259 | if (regno == tdep->ppc_lr_regnum) |
49ff75ad | 260 | u_addr = PT_LNK * wordsize; |
dc5cfeb6 | 261 | if (regno == tdep->ppc_cr_regnum) |
49ff75ad | 262 | u_addr = PT_CCR * wordsize; |
dc5cfeb6 | 263 | if (regno == tdep->ppc_xer_regnum) |
49ff75ad | 264 | u_addr = PT_XER * wordsize; |
dc5cfeb6 | 265 | if (regno == tdep->ppc_ctr_regnum) |
49ff75ad | 266 | u_addr = PT_CTR * wordsize; |
f8c59253 | 267 | #ifdef PT_MQ |
dc5cfeb6 | 268 | if (regno == tdep->ppc_mq_regnum) |
49ff75ad | 269 | u_addr = PT_MQ * wordsize; |
f8c59253 | 270 | #endif |
dc5cfeb6 | 271 | if (regno == tdep->ppc_ps_regnum) |
49ff75ad | 272 | u_addr = PT_MSR * wordsize; |
7284e1be UW |
273 | if (regno == PPC_ORIG_R3_REGNUM) |
274 | u_addr = PT_ORIG_R3 * wordsize; | |
275 | if (regno == PPC_TRAP_REGNUM) | |
276 | u_addr = PT_TRAP * wordsize; | |
383f0f5b JB |
277 | if (tdep->ppc_fpscr_regnum >= 0 |
278 | && regno == tdep->ppc_fpscr_regnum) | |
8f135812 AC |
279 | { |
280 | /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the | |
281 | kernel headers incorrectly contained the 32-bit definition of | |
282 | PT_FPSCR. For the 32-bit definition, floating-point | |
283 | registers occupy two 32-bit "slots", and the FPSCR lives in | |
69abc51c | 284 | the second half of such a slot-pair (hence +1). For 64-bit, |
8f135812 AC |
285 | the FPSCR instead occupies the full 64-bit 2-word-slot and |
286 | hence no adjustment is necessary. Hack around this. */ | |
287 | if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1)) | |
288 | u_addr = (48 + 32) * wordsize; | |
69abc51c TJB |
289 | /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit |
290 | slot and not just its second word. The PT_FPSCR supplied when | |
291 | GDB is compiled as a 32-bit app doesn't reflect this. */ | |
292 | else if (wordsize == 4 && register_size (gdbarch, regno) == 8 | |
293 | && PT_FPSCR == (48 + 2*32 + 1)) | |
294 | u_addr = (48 + 2*32) * wordsize; | |
8f135812 AC |
295 | else |
296 | u_addr = PT_FPSCR * wordsize; | |
297 | } | |
16333c4f | 298 | return u_addr; |
c877c8e6 KB |
299 | } |
300 | ||
604c2f83 LM |
301 | /* The Linux kernel ptrace interface for POWER7 VSX registers uses the |
302 | registers set mechanism, as opposed to the interface for all the | |
303 | other registers, that stores/fetches each register individually. */ | |
304 | static void | |
305 | fetch_vsx_register (struct regcache *regcache, int tid, int regno) | |
306 | { | |
307 | int ret; | |
308 | gdb_vsxregset_t regs; | |
309 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
310 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
311 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
312 | ||
313 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
314 | if (ret < 0) | |
315 | { | |
316 | if (errno == EIO) | |
317 | { | |
318 | have_ptrace_getsetvsxregs = 0; | |
319 | return; | |
320 | } | |
321 | perror_with_name (_("Unable to fetch VSX register")); | |
322 | } | |
323 | ||
324 | regcache_raw_supply (regcache, regno, | |
325 | regs + (regno - tdep->ppc_vsr0_upper_regnum) | |
326 | * vsxregsize); | |
327 | } | |
328 | ||
9abe5450 EZ |
329 | /* The Linux kernel ptrace interface for AltiVec registers uses the |
330 | registers set mechanism, as opposed to the interface for all the | |
331 | other registers, that stores/fetches each register individually. */ | |
332 | static void | |
56be3814 | 333 | fetch_altivec_register (struct regcache *regcache, int tid, int regno) |
9abe5450 EZ |
334 | { |
335 | int ret; | |
336 | int offset = 0; | |
337 | gdb_vrregset_t regs; | |
40a6adc1 MD |
338 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
339 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
340 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); | |
9abe5450 EZ |
341 | |
342 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
343 | if (ret < 0) | |
344 | { | |
345 | if (errno == EIO) | |
346 | { | |
347 | have_ptrace_getvrregs = 0; | |
348 | return; | |
349 | } | |
e2e0b3e5 | 350 | perror_with_name (_("Unable to fetch AltiVec register")); |
9abe5450 EZ |
351 | } |
352 | ||
353 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
354 | long on the hardware. We deal only with the lower 4 bytes of the | |
355 | vector. VRSAVE is at the end of the array in a 4 bytes slot, so | |
356 | there is no need to define an offset for it. */ | |
357 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
40a6adc1 | 358 | offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
9abe5450 | 359 | |
56be3814 | 360 | regcache_raw_supply (regcache, regno, |
23a6d369 | 361 | regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); |
9abe5450 EZ |
362 | } |
363 | ||
01904826 JB |
364 | /* Fetch the top 32 bits of TID's general-purpose registers and the |
365 | SPE-specific registers, and place the results in EVRREGSET. If we | |
366 | don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with | |
367 | zeros. | |
368 | ||
369 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
370 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
371 | set_spe_registers. */ | |
372 | static void | |
373 | get_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
374 | { | |
375 | if (have_ptrace_getsetevrregs) | |
376 | { | |
377 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0) | |
378 | return; | |
379 | else | |
380 | { | |
381 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported; | |
382 | we just return zeros. */ | |
383 | if (errno == EIO) | |
384 | have_ptrace_getsetevrregs = 0; | |
385 | else | |
386 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 387 | perror_with_name (_("Unable to fetch SPE registers")); |
01904826 JB |
388 | } |
389 | } | |
390 | ||
391 | memset (evrregset, 0, sizeof (*evrregset)); | |
392 | } | |
393 | ||
6ced10dd JB |
394 | /* Supply values from TID for SPE-specific raw registers: the upper |
395 | halves of the GPRs, the accumulator, and the spefscr. REGNO must | |
396 | be the number of an upper half register, acc, spefscr, or -1 to | |
397 | supply the values of all registers. */ | |
01904826 | 398 | static void |
56be3814 | 399 | fetch_spe_register (struct regcache *regcache, int tid, int regno) |
01904826 | 400 | { |
40a6adc1 MD |
401 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
402 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
01904826 JB |
403 | struct gdb_evrregset_t evrregs; |
404 | ||
6ced10dd | 405 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 406 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 407 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 408 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 409 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 410 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
6ced10dd | 411 | |
01904826 JB |
412 | get_spe_registers (tid, &evrregs); |
413 | ||
6ced10dd | 414 | if (regno == -1) |
01904826 | 415 | { |
6ced10dd JB |
416 | int i; |
417 | ||
418 | for (i = 0; i < ppc_num_gprs; i++) | |
56be3814 | 419 | regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i, |
6ced10dd | 420 | &evrregs.evr[i]); |
01904826 | 421 | } |
6ced10dd JB |
422 | else if (tdep->ppc_ev0_upper_regnum <= regno |
423 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
56be3814 | 424 | regcache_raw_supply (regcache, regno, |
6ced10dd JB |
425 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
426 | ||
427 | if (regno == -1 | |
428 | || regno == tdep->ppc_acc_regnum) | |
56be3814 | 429 | regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc); |
6ced10dd JB |
430 | |
431 | if (regno == -1 | |
432 | || regno == tdep->ppc_spefscr_regnum) | |
56be3814 | 433 | regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum, |
6ced10dd | 434 | &evrregs.spefscr); |
01904826 JB |
435 | } |
436 | ||
45229ea4 | 437 | static void |
56be3814 | 438 | fetch_register (struct regcache *regcache, int tid, int regno) |
45229ea4 | 439 | { |
40a6adc1 MD |
440 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
441 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
45229ea4 | 442 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 443 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
4a19ea35 | 444 | int bytes_transferred; |
45229ea4 | 445 | unsigned int offset; /* Offset of registers within the u area. */ |
d9d9c31f | 446 | char buf[MAX_REGISTER_SIZE]; |
45229ea4 | 447 | |
be8626e0 | 448 | if (altivec_register_p (gdbarch, regno)) |
9abe5450 EZ |
449 | { |
450 | /* If this is the first time through, or if it is not the first | |
451 | time through, and we have comfirmed that there is kernel | |
452 | support for such a ptrace request, then go and fetch the | |
453 | register. */ | |
454 | if (have_ptrace_getvrregs) | |
455 | { | |
56be3814 | 456 | fetch_altivec_register (regcache, tid, regno); |
9abe5450 EZ |
457 | return; |
458 | } | |
459 | /* If we have discovered that there is no ptrace support for | |
460 | AltiVec registers, fall through and return zeroes, because | |
461 | regaddr will be -1 in this case. */ | |
462 | } | |
604c2f83 LM |
463 | if (vsx_register_p (gdbarch, regno)) |
464 | { | |
465 | if (have_ptrace_getsetvsxregs) | |
466 | { | |
467 | fetch_vsx_register (regcache, tid, regno); | |
468 | return; | |
469 | } | |
470 | } | |
be8626e0 | 471 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 472 | { |
56be3814 | 473 | fetch_spe_register (regcache, tid, regno); |
01904826 JB |
474 | return; |
475 | } | |
9abe5450 | 476 | |
45229ea4 EZ |
477 | if (regaddr == -1) |
478 | { | |
40a6adc1 | 479 | memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ |
56be3814 | 480 | regcache_raw_supply (regcache, regno, buf); |
45229ea4 EZ |
481 | return; |
482 | } | |
483 | ||
411cb3f9 | 484 | /* Read the raw register using sizeof(long) sized chunks. On a |
56d0d96a AC |
485 | 32-bit platform, 64-bit floating-point registers will require two |
486 | transfers. */ | |
4a19ea35 | 487 | for (bytes_transferred = 0; |
40a6adc1 | 488 | bytes_transferred < register_size (gdbarch, regno); |
411cb3f9 | 489 | bytes_transferred += sizeof (long)) |
45229ea4 EZ |
490 | { |
491 | errno = 0; | |
411cb3f9 PG |
492 | *(long *) &buf[bytes_transferred] |
493 | = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); | |
494 | regaddr += sizeof (long); | |
45229ea4 EZ |
495 | if (errno != 0) |
496 | { | |
bc97b3ba JB |
497 | char message[128]; |
498 | sprintf (message, "reading register %s (#%d)", | |
40a6adc1 | 499 | gdbarch_register_name (gdbarch, regno), regno); |
bc97b3ba | 500 | perror_with_name (message); |
45229ea4 EZ |
501 | } |
502 | } | |
56d0d96a | 503 | |
4a19ea35 JB |
504 | /* Now supply the register. Keep in mind that the regcache's idea |
505 | of the register's size may not be a multiple of sizeof | |
411cb3f9 | 506 | (long). */ |
40a6adc1 | 507 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
4a19ea35 JB |
508 | { |
509 | /* Little-endian values are always found at the left end of the | |
510 | bytes transferred. */ | |
56be3814 | 511 | regcache_raw_supply (regcache, regno, buf); |
4a19ea35 | 512 | } |
40a6adc1 | 513 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
514 | { |
515 | /* Big-endian values are found at the right end of the bytes | |
516 | transferred. */ | |
40a6adc1 | 517 | size_t padding = (bytes_transferred - register_size (gdbarch, regno)); |
56be3814 | 518 | regcache_raw_supply (regcache, regno, buf + padding); |
4a19ea35 JB |
519 | } |
520 | else | |
a44bddec | 521 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 522 | _("fetch_register: unexpected byte order: %d"), |
40a6adc1 | 523 | gdbarch_byte_order (gdbarch)); |
45229ea4 EZ |
524 | } |
525 | ||
604c2f83 LM |
526 | static void |
527 | supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) | |
528 | { | |
529 | int i; | |
530 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
531 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
532 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
533 | ||
534 | for (i = 0; i < ppc_num_vshrs; i++) | |
535 | { | |
536 | regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i, | |
537 | *vsxregsetp + i * vsxregsize); | |
538 | } | |
539 | } | |
540 | ||
9abe5450 | 541 | static void |
56be3814 | 542 | supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
9abe5450 EZ |
543 | { |
544 | int i; | |
40a6adc1 MD |
545 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
546 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9abe5450 | 547 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; |
40a6adc1 MD |
548 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
549 | int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
550 | |
551 | for (i = 0; i < num_of_vrregs; i++) | |
552 | { | |
553 | /* The last 2 registers of this set are only 32 bit long, not | |
554 | 128. However an offset is necessary only for VSCR because it | |
555 | occupies a whole vector, while VRSAVE occupies a full 4 bytes | |
556 | slot. */ | |
557 | if (i == (num_of_vrregs - 2)) | |
56be3814 | 558 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
23a6d369 | 559 | *vrregsetp + i * vrregsize + offset); |
9abe5450 | 560 | else |
56be3814 | 561 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
23a6d369 | 562 | *vrregsetp + i * vrregsize); |
9abe5450 EZ |
563 | } |
564 | } | |
565 | ||
604c2f83 LM |
566 | static void |
567 | fetch_vsx_registers (struct regcache *regcache, int tid) | |
568 | { | |
569 | int ret; | |
570 | gdb_vsxregset_t regs; | |
571 | ||
572 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
573 | if (ret < 0) | |
574 | { | |
575 | if (errno == EIO) | |
576 | { | |
577 | have_ptrace_getsetvsxregs = 0; | |
578 | return; | |
579 | } | |
580 | perror_with_name (_("Unable to fetch VSX registers")); | |
581 | } | |
582 | supply_vsxregset (regcache, ®s); | |
583 | } | |
584 | ||
9abe5450 | 585 | static void |
56be3814 | 586 | fetch_altivec_registers (struct regcache *regcache, int tid) |
9abe5450 EZ |
587 | { |
588 | int ret; | |
589 | gdb_vrregset_t regs; | |
590 | ||
591 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
592 | if (ret < 0) | |
593 | { | |
594 | if (errno == EIO) | |
595 | { | |
596 | have_ptrace_getvrregs = 0; | |
597 | return; | |
598 | } | |
e2e0b3e5 | 599 | perror_with_name (_("Unable to fetch AltiVec registers")); |
9abe5450 | 600 | } |
56be3814 | 601 | supply_vrregset (regcache, ®s); |
9abe5450 EZ |
602 | } |
603 | ||
45229ea4 | 604 | static void |
56be3814 | 605 | fetch_ppc_registers (struct regcache *regcache, int tid) |
45229ea4 EZ |
606 | { |
607 | int i; | |
40a6adc1 MD |
608 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
609 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9abe5450 | 610 | |
6ced10dd | 611 | for (i = 0; i < ppc_num_gprs; i++) |
56be3814 | 612 | fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
32b99774 JB |
613 | if (tdep->ppc_fp0_regnum >= 0) |
614 | for (i = 0; i < ppc_num_fprs; i++) | |
56be3814 | 615 | fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i); |
40a6adc1 | 616 | fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 617 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 618 | fetch_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 619 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 620 | fetch_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 621 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 622 | fetch_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 623 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 624 | fetch_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 625 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 626 | fetch_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 627 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 628 | fetch_register (regcache, tid, tdep->ppc_mq_regnum); |
7284e1be UW |
629 | if (ppc_linux_trap_reg_p (gdbarch)) |
630 | { | |
631 | fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
632 | fetch_register (regcache, tid, PPC_TRAP_REGNUM); | |
633 | } | |
32b99774 | 634 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 635 | fetch_register (regcache, tid, tdep->ppc_fpscr_regnum); |
9abe5450 EZ |
636 | if (have_ptrace_getvrregs) |
637 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
56be3814 | 638 | fetch_altivec_registers (regcache, tid); |
604c2f83 LM |
639 | if (have_ptrace_getsetvsxregs) |
640 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
641 | fetch_vsx_registers (regcache, tid); | |
6ced10dd | 642 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 643 | fetch_spe_register (regcache, tid, -1); |
45229ea4 EZ |
644 | } |
645 | ||
646 | /* Fetch registers from the child process. Fetch all registers if | |
647 | regno == -1, otherwise fetch all general registers or all floating | |
648 | point registers depending upon the value of regno. */ | |
10d6c8cd | 649 | static void |
28439f5e PA |
650 | ppc_linux_fetch_inferior_registers (struct target_ops *ops, |
651 | struct regcache *regcache, int regno) | |
45229ea4 | 652 | { |
9abe5450 | 653 | /* Overload thread id onto process id */ |
05f13b9c EZ |
654 | int tid = TIDGET (inferior_ptid); |
655 | ||
656 | /* No thread id, just use process id */ | |
657 | if (tid == 0) | |
658 | tid = PIDGET (inferior_ptid); | |
659 | ||
9abe5450 | 660 | if (regno == -1) |
56be3814 | 661 | fetch_ppc_registers (regcache, tid); |
45229ea4 | 662 | else |
56be3814 | 663 | fetch_register (regcache, tid, regno); |
45229ea4 EZ |
664 | } |
665 | ||
604c2f83 LM |
666 | /* Store one VSX register. */ |
667 | static void | |
668 | store_vsx_register (const struct regcache *regcache, int tid, int regno) | |
669 | { | |
670 | int ret; | |
671 | gdb_vsxregset_t regs; | |
672 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
673 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
674 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
675 | ||
676 | ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); | |
677 | if (ret < 0) | |
678 | { | |
679 | if (errno == EIO) | |
680 | { | |
681 | have_ptrace_getsetvsxregs = 0; | |
682 | return; | |
683 | } | |
684 | perror_with_name (_("Unable to fetch VSX register")); | |
685 | } | |
686 | ||
687 | regcache_raw_collect (regcache, regno, regs + | |
688 | (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize); | |
689 | ||
690 | ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); | |
691 | if (ret < 0) | |
692 | perror_with_name (_("Unable to store VSX register")); | |
693 | } | |
694 | ||
45229ea4 | 695 | /* Store one register. */ |
9abe5450 | 696 | static void |
56be3814 | 697 | store_altivec_register (const struct regcache *regcache, int tid, int regno) |
9abe5450 EZ |
698 | { |
699 | int ret; | |
700 | int offset = 0; | |
701 | gdb_vrregset_t regs; | |
40a6adc1 MD |
702 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
703 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
704 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); | |
9abe5450 EZ |
705 | |
706 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
707 | if (ret < 0) | |
708 | { | |
709 | if (errno == EIO) | |
710 | { | |
711 | have_ptrace_getvrregs = 0; | |
712 | return; | |
713 | } | |
e2e0b3e5 | 714 | perror_with_name (_("Unable to fetch AltiVec register")); |
9abe5450 EZ |
715 | } |
716 | ||
717 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
718 | long on the hardware. */ | |
719 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
40a6adc1 | 720 | offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
9abe5450 | 721 | |
56be3814 | 722 | regcache_raw_collect (regcache, regno, |
822c9732 | 723 | regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); |
9abe5450 EZ |
724 | |
725 | ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); | |
726 | if (ret < 0) | |
e2e0b3e5 | 727 | perror_with_name (_("Unable to store AltiVec register")); |
9abe5450 EZ |
728 | } |
729 | ||
01904826 JB |
730 | /* Assuming TID referrs to an SPE process, set the top halves of TID's |
731 | general-purpose registers and its SPE-specific registers to the | |
732 | values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do | |
733 | nothing. | |
734 | ||
735 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
736 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
737 | get_spe_registers. */ | |
738 | static void | |
739 | set_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
740 | { | |
741 | if (have_ptrace_getsetevrregs) | |
742 | { | |
743 | if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0) | |
744 | return; | |
745 | else | |
746 | { | |
747 | /* EIO means that the PTRACE_SETEVRREGS request isn't | |
748 | supported; we fail silently, and don't try the call | |
749 | again. */ | |
750 | if (errno == EIO) | |
751 | have_ptrace_getsetevrregs = 0; | |
752 | else | |
753 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 754 | perror_with_name (_("Unable to set SPE registers")); |
01904826 JB |
755 | } |
756 | } | |
757 | } | |
758 | ||
6ced10dd JB |
759 | /* Write GDB's value for the SPE-specific raw register REGNO to TID. |
760 | If REGNO is -1, write the values of all the SPE-specific | |
761 | registers. */ | |
01904826 | 762 | static void |
56be3814 | 763 | store_spe_register (const struct regcache *regcache, int tid, int regno) |
01904826 | 764 | { |
40a6adc1 MD |
765 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
766 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
01904826 JB |
767 | struct gdb_evrregset_t evrregs; |
768 | ||
6ced10dd | 769 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 770 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 771 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 772 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 773 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 774 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
01904826 | 775 | |
6ced10dd JB |
776 | if (regno == -1) |
777 | /* Since we're going to write out every register, the code below | |
778 | should store to every field of evrregs; if that doesn't happen, | |
779 | make it obvious by initializing it with suspicious values. */ | |
780 | memset (&evrregs, 42, sizeof (evrregs)); | |
781 | else | |
782 | /* We can only read and write the entire EVR register set at a | |
783 | time, so to write just a single register, we do a | |
784 | read-modify-write maneuver. */ | |
785 | get_spe_registers (tid, &evrregs); | |
786 | ||
787 | if (regno == -1) | |
01904826 | 788 | { |
6ced10dd JB |
789 | int i; |
790 | ||
791 | for (i = 0; i < ppc_num_gprs; i++) | |
56be3814 | 792 | regcache_raw_collect (regcache, |
6ced10dd JB |
793 | tdep->ppc_ev0_upper_regnum + i, |
794 | &evrregs.evr[i]); | |
01904826 | 795 | } |
6ced10dd JB |
796 | else if (tdep->ppc_ev0_upper_regnum <= regno |
797 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
56be3814 | 798 | regcache_raw_collect (regcache, regno, |
6ced10dd JB |
799 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
800 | ||
801 | if (regno == -1 | |
802 | || regno == tdep->ppc_acc_regnum) | |
56be3814 | 803 | regcache_raw_collect (regcache, |
6ced10dd JB |
804 | tdep->ppc_acc_regnum, |
805 | &evrregs.acc); | |
806 | ||
807 | if (regno == -1 | |
808 | || regno == tdep->ppc_spefscr_regnum) | |
56be3814 | 809 | regcache_raw_collect (regcache, |
6ced10dd JB |
810 | tdep->ppc_spefscr_regnum, |
811 | &evrregs.spefscr); | |
01904826 JB |
812 | |
813 | /* Write back the modified register set. */ | |
814 | set_spe_registers (tid, &evrregs); | |
815 | } | |
816 | ||
45229ea4 | 817 | static void |
56be3814 | 818 | store_register (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 819 | { |
40a6adc1 MD |
820 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
821 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
45229ea4 | 822 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 823 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
52f0bd74 | 824 | int i; |
4a19ea35 | 825 | size_t bytes_to_transfer; |
d9d9c31f | 826 | char buf[MAX_REGISTER_SIZE]; |
45229ea4 | 827 | |
be8626e0 | 828 | if (altivec_register_p (gdbarch, regno)) |
45229ea4 | 829 | { |
56be3814 | 830 | store_altivec_register (regcache, tid, regno); |
45229ea4 EZ |
831 | return; |
832 | } | |
604c2f83 LM |
833 | if (vsx_register_p (gdbarch, regno)) |
834 | { | |
835 | store_vsx_register (regcache, tid, regno); | |
836 | return; | |
837 | } | |
be8626e0 | 838 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 839 | { |
56be3814 | 840 | store_spe_register (regcache, tid, regno); |
01904826 JB |
841 | return; |
842 | } | |
45229ea4 | 843 | |
9abe5450 EZ |
844 | if (regaddr == -1) |
845 | return; | |
846 | ||
4a19ea35 JB |
847 | /* First collect the register. Keep in mind that the regcache's |
848 | idea of the register's size may not be a multiple of sizeof | |
411cb3f9 | 849 | (long). */ |
56d0d96a | 850 | memset (buf, 0, sizeof buf); |
40a6adc1 MD |
851 | bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); |
852 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) | |
4a19ea35 JB |
853 | { |
854 | /* Little-endian values always sit at the left end of the buffer. */ | |
56be3814 | 855 | regcache_raw_collect (regcache, regno, buf); |
4a19ea35 | 856 | } |
40a6adc1 | 857 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
858 | { |
859 | /* Big-endian values sit at the right end of the buffer. */ | |
40a6adc1 | 860 | size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); |
56be3814 | 861 | regcache_raw_collect (regcache, regno, buf + padding); |
4a19ea35 JB |
862 | } |
863 | ||
411cb3f9 | 864 | for (i = 0; i < bytes_to_transfer; i += sizeof (long)) |
45229ea4 EZ |
865 | { |
866 | errno = 0; | |
411cb3f9 PG |
867 | ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, |
868 | *(long *) &buf[i]); | |
869 | regaddr += sizeof (long); | |
e3f36dbd KB |
870 | |
871 | if (errno == EIO | |
7284e1be UW |
872 | && (regno == tdep->ppc_fpscr_regnum |
873 | || regno == PPC_ORIG_R3_REGNUM | |
874 | || regno == PPC_TRAP_REGNUM)) | |
e3f36dbd | 875 | { |
7284e1be UW |
876 | /* Some older kernel versions don't allow fpscr, orig_r3 |
877 | or trap to be written. */ | |
e3f36dbd KB |
878 | continue; |
879 | } | |
880 | ||
45229ea4 EZ |
881 | if (errno != 0) |
882 | { | |
bc97b3ba JB |
883 | char message[128]; |
884 | sprintf (message, "writing register %s (#%d)", | |
40a6adc1 | 885 | gdbarch_register_name (gdbarch, regno), regno); |
bc97b3ba | 886 | perror_with_name (message); |
45229ea4 EZ |
887 | } |
888 | } | |
889 | } | |
890 | ||
604c2f83 LM |
891 | static void |
892 | fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) | |
893 | { | |
894 | int i; | |
895 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
896 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
897 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
898 | ||
899 | for (i = 0; i < ppc_num_vshrs; i++) | |
900 | regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i, | |
901 | *vsxregsetp + i * vsxregsize); | |
902 | } | |
903 | ||
9abe5450 | 904 | static void |
56be3814 | 905 | fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
9abe5450 EZ |
906 | { |
907 | int i; | |
40a6adc1 MD |
908 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
909 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9abe5450 | 910 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; |
40a6adc1 MD |
911 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
912 | int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
913 | |
914 | for (i = 0; i < num_of_vrregs; i++) | |
915 | { | |
916 | /* The last 2 registers of this set are only 32 bit long, not | |
917 | 128, but only VSCR is fetched as a 16 bytes quantity. */ | |
918 | if (i == (num_of_vrregs - 2)) | |
56be3814 | 919 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
822c9732 | 920 | *vrregsetp + i * vrregsize + offset); |
9abe5450 | 921 | else |
56be3814 | 922 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
822c9732 | 923 | *vrregsetp + i * vrregsize); |
9abe5450 EZ |
924 | } |
925 | } | |
926 | ||
604c2f83 LM |
927 | static void |
928 | store_vsx_registers (const struct regcache *regcache, int tid) | |
929 | { | |
930 | int ret; | |
931 | gdb_vsxregset_t regs; | |
932 | ||
933 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
934 | if (ret < 0) | |
935 | { | |
936 | if (errno == EIO) | |
937 | { | |
938 | have_ptrace_getsetvsxregs = 0; | |
939 | return; | |
940 | } | |
941 | perror_with_name (_("Couldn't get VSX registers")); | |
942 | } | |
943 | ||
944 | fill_vsxregset (regcache, ®s); | |
945 | ||
946 | if (ptrace (PTRACE_SETVSXREGS, tid, 0, ®s) < 0) | |
947 | perror_with_name (_("Couldn't write VSX registers")); | |
948 | } | |
949 | ||
9abe5450 | 950 | static void |
56be3814 | 951 | store_altivec_registers (const struct regcache *regcache, int tid) |
9abe5450 EZ |
952 | { |
953 | int ret; | |
954 | gdb_vrregset_t regs; | |
955 | ||
0897f59b | 956 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); |
9abe5450 EZ |
957 | if (ret < 0) |
958 | { | |
959 | if (errno == EIO) | |
960 | { | |
961 | have_ptrace_getvrregs = 0; | |
962 | return; | |
963 | } | |
e2e0b3e5 | 964 | perror_with_name (_("Couldn't get AltiVec registers")); |
9abe5450 EZ |
965 | } |
966 | ||
56be3814 | 967 | fill_vrregset (regcache, ®s); |
9abe5450 | 968 | |
0897f59b | 969 | if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0) |
e2e0b3e5 | 970 | perror_with_name (_("Couldn't write AltiVec registers")); |
9abe5450 EZ |
971 | } |
972 | ||
45229ea4 | 973 | static void |
56be3814 | 974 | store_ppc_registers (const struct regcache *regcache, int tid) |
45229ea4 EZ |
975 | { |
976 | int i; | |
40a6adc1 MD |
977 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
978 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
45229ea4 | 979 | |
6ced10dd | 980 | for (i = 0; i < ppc_num_gprs; i++) |
56be3814 | 981 | store_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
32b99774 JB |
982 | if (tdep->ppc_fp0_regnum >= 0) |
983 | for (i = 0; i < ppc_num_fprs; i++) | |
56be3814 | 984 | store_register (regcache, tid, tdep->ppc_fp0_regnum + i); |
40a6adc1 | 985 | store_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 986 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 987 | store_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 988 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 989 | store_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 990 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 991 | store_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 992 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 993 | store_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 994 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 995 | store_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 996 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 997 | store_register (regcache, tid, tdep->ppc_mq_regnum); |
32b99774 | 998 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 999 | store_register (regcache, tid, tdep->ppc_fpscr_regnum); |
7284e1be UW |
1000 | if (ppc_linux_trap_reg_p (gdbarch)) |
1001 | { | |
1002 | store_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
1003 | store_register (regcache, tid, PPC_TRAP_REGNUM); | |
1004 | } | |
9abe5450 EZ |
1005 | if (have_ptrace_getvrregs) |
1006 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
56be3814 | 1007 | store_altivec_registers (regcache, tid); |
604c2f83 LM |
1008 | if (have_ptrace_getsetvsxregs) |
1009 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
1010 | store_vsx_registers (regcache, tid); | |
6ced10dd | 1011 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 1012 | store_spe_register (regcache, tid, -1); |
45229ea4 EZ |
1013 | } |
1014 | ||
e0d24f8d WZ |
1015 | static int |
1016 | ppc_linux_check_watch_resources (int type, int cnt, int ot) | |
1017 | { | |
1018 | int tid; | |
1019 | ptid_t ptid = inferior_ptid; | |
1020 | ||
1021 | /* DABR (data address breakpoint register) is optional for PPC variants. | |
1022 | Some variants have one DABR, others have none. So CNT can't be larger | |
1023 | than 1. */ | |
1024 | if (cnt > 1) | |
1025 | return 0; | |
1026 | ||
1027 | /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG and whether | |
1028 | the target has DABR. If either answer is no, the ptrace call will | |
1029 | return -1. Fail in that case. */ | |
1030 | tid = TIDGET (ptid); | |
1031 | if (tid == 0) | |
1032 | tid = PIDGET (ptid); | |
1033 | ||
1034 | if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1) | |
1035 | return 0; | |
1036 | return 1; | |
1037 | } | |
1038 | ||
b7622095 LM |
1039 | /* Fetch the AT_HWCAP entry from the aux vector. */ |
1040 | unsigned long ppc_linux_get_hwcap (void) | |
1041 | { | |
1042 | CORE_ADDR field; | |
1043 | ||
fcb09a75 | 1044 | if (target_auxv_search (¤t_target, AT_HWCAP, &field)) |
b7622095 LM |
1045 | return (unsigned long) field; |
1046 | ||
1047 | return 0; | |
1048 | } | |
1049 | ||
e0d24f8d WZ |
1050 | static int |
1051 | ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
1052 | { | |
1053 | /* Handle sub-8-byte quantities. */ | |
1054 | if (len <= 0) | |
1055 | return 0; | |
1056 | ||
b7622095 LM |
1057 | /* addr+len must fall in the 8 byte watchable region for DABR-based |
1058 | processors. DAC-based processors, like the PowerPC 440, will use | |
1059 | addresses aligned to 4-bytes due to the way the read/write flags are | |
1060 | passed at the moment. */ | |
1061 | if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
1062 | && (addr + len) > (addr & ~3) + 4) | |
1063 | || (addr + len) > (addr & ~7) + 8) | |
e0d24f8d WZ |
1064 | return 0; |
1065 | ||
1066 | return 1; | |
1067 | } | |
1068 | ||
9f0bdab8 DJ |
1069 | /* The cached DABR value, to install in new threads. */ |
1070 | static long saved_dabr_value; | |
1071 | ||
e0d24f8d | 1072 | /* Set a watchpoint of type TYPE at address ADDR. */ |
2c387241 | 1073 | static int |
e0d24f8d WZ |
1074 | ppc_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw) |
1075 | { | |
9f0bdab8 DJ |
1076 | struct lwp_info *lp; |
1077 | ptid_t ptid; | |
e0d24f8d | 1078 | long dabr_value; |
b7622095 LM |
1079 | long read_mode, write_mode; |
1080 | ||
1081 | if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
1082 | { | |
1083 | /* PowerPC 440 requires only the read/write flags to be passed | |
1084 | to the kernel. */ | |
1085 | read_mode = 1; | |
1086 | write_mode = 2; | |
1087 | } | |
1088 | else | |
1089 | { | |
1090 | /* PowerPC 970 and other DABR-based processors are required to pass | |
1091 | the Breakpoint Translation bit together with the flags. */ | |
1092 | read_mode = 5; | |
1093 | write_mode = 6; | |
1094 | } | |
1095 | ||
1096 | dabr_value = addr & ~(read_mode | write_mode); | |
e0d24f8d WZ |
1097 | switch (rw) |
1098 | { | |
1099 | case hw_read: | |
1100 | /* Set read and translate bits. */ | |
b7622095 | 1101 | dabr_value |= read_mode; |
e0d24f8d WZ |
1102 | break; |
1103 | case hw_write: | |
1104 | /* Set write and translate bits. */ | |
b7622095 | 1105 | dabr_value |= write_mode; |
e0d24f8d WZ |
1106 | break; |
1107 | case hw_access: | |
1108 | /* Set read, write and translate bits. */ | |
b7622095 | 1109 | dabr_value |= read_mode | write_mode; |
e0d24f8d WZ |
1110 | break; |
1111 | } | |
1112 | ||
1c86e440 LM |
1113 | saved_dabr_value = dabr_value; |
1114 | ||
9f0bdab8 DJ |
1115 | ALL_LWPS (lp, ptid) |
1116 | if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value) < 0) | |
1117 | return -1; | |
1c86e440 | 1118 | |
9f0bdab8 | 1119 | return 0; |
e0d24f8d WZ |
1120 | } |
1121 | ||
2c387241 AM |
1122 | static int |
1123 | ppc_linux_remove_watchpoint (CORE_ADDR addr, int len, int rw) | |
e0d24f8d | 1124 | { |
9f0bdab8 DJ |
1125 | struct lwp_info *lp; |
1126 | ptid_t ptid; | |
1127 | long dabr_value = 0; | |
1128 | ||
1129 | saved_dabr_value = 0; | |
1130 | ALL_LWPS (lp, ptid) | |
1131 | if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value) < 0) | |
1132 | return -1; | |
1133 | return 0; | |
e0d24f8d WZ |
1134 | } |
1135 | ||
9f0bdab8 DJ |
1136 | static void |
1137 | ppc_linux_new_thread (ptid_t ptid) | |
e0d24f8d | 1138 | { |
9f0bdab8 | 1139 | ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value); |
e0d24f8d WZ |
1140 | } |
1141 | ||
1142 | static int | |
9f0bdab8 | 1143 | ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p) |
e0d24f8d | 1144 | { |
9f0bdab8 | 1145 | struct siginfo *siginfo_p; |
e0d24f8d | 1146 | |
9f0bdab8 | 1147 | siginfo_p = linux_nat_get_siginfo (inferior_ptid); |
e0d24f8d | 1148 | |
9f0bdab8 DJ |
1149 | if (siginfo_p->si_signo != SIGTRAP |
1150 | || (siginfo_p->si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
e0d24f8d WZ |
1151 | return 0; |
1152 | ||
407f1a2e | 1153 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo_p->si_addr; |
e0d24f8d WZ |
1154 | return 1; |
1155 | } | |
1156 | ||
9f0bdab8 DJ |
1157 | static int |
1158 | ppc_linux_stopped_by_watchpoint (void) | |
1159 | { | |
1160 | CORE_ADDR addr; | |
1161 | return ppc_linux_stopped_data_address (¤t_target, &addr); | |
1162 | } | |
1163 | ||
5009afc5 AS |
1164 | static int |
1165 | ppc_linux_watchpoint_addr_within_range (struct target_ops *target, | |
1166 | CORE_ADDR addr, | |
1167 | CORE_ADDR start, int length) | |
1168 | { | |
b7622095 LM |
1169 | int mask; |
1170 | ||
1171 | if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
1172 | mask = 3; | |
1173 | else | |
1174 | mask = 7; | |
1175 | ||
1176 | addr &= ~mask; | |
1177 | ||
1178 | /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */ | |
1179 | return start <= addr + mask && start + length - 1 >= addr; | |
5009afc5 AS |
1180 | } |
1181 | ||
10d6c8cd | 1182 | static void |
28439f5e PA |
1183 | ppc_linux_store_inferior_registers (struct target_ops *ops, |
1184 | struct regcache *regcache, int regno) | |
45229ea4 | 1185 | { |
05f13b9c EZ |
1186 | /* Overload thread id onto process id */ |
1187 | int tid = TIDGET (inferior_ptid); | |
1188 | ||
1189 | /* No thread id, just use process id */ | |
1190 | if (tid == 0) | |
1191 | tid = PIDGET (inferior_ptid); | |
1192 | ||
45229ea4 | 1193 | if (regno >= 0) |
56be3814 | 1194 | store_register (regcache, tid, regno); |
45229ea4 | 1195 | else |
56be3814 | 1196 | store_ppc_registers (regcache, tid); |
45229ea4 EZ |
1197 | } |
1198 | ||
f2db237a AM |
1199 | /* Functions for transferring registers between a gregset_t or fpregset_t |
1200 | (see sys/ucontext.h) and gdb's regcache. The word size is that used | |
1201 | by the ptrace interface, not the current program's ABI. eg. If a | |
1202 | powerpc64-linux gdb is being used to debug a powerpc32-linux app, we | |
1203 | read or write 64-bit gregsets. This is to suit the host libthread_db. */ | |
1204 | ||
50c9bd31 | 1205 | void |
7f7fe91e | 1206 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
c877c8e6 | 1207 | { |
f2db237a | 1208 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 1209 | |
f2db237a | 1210 | ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp)); |
c877c8e6 KB |
1211 | } |
1212 | ||
fdb28ac4 | 1213 | void |
7f7fe91e UW |
1214 | fill_gregset (const struct regcache *regcache, |
1215 | gdb_gregset_t *gregsetp, int regno) | |
fdb28ac4 | 1216 | { |
f2db237a | 1217 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 1218 | |
f2db237a AM |
1219 | if (regno == -1) |
1220 | memset (gregsetp, 0, sizeof (*gregsetp)); | |
1221 | ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp)); | |
fdb28ac4 KB |
1222 | } |
1223 | ||
50c9bd31 | 1224 | void |
7f7fe91e | 1225 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp) |
c877c8e6 | 1226 | { |
f2db237a AM |
1227 | const struct regset *regset = ppc_linux_fpregset (); |
1228 | ||
1229 | ppc_supply_fpregset (regset, regcache, -1, | |
1230 | fpregsetp, sizeof (*fpregsetp)); | |
c877c8e6 | 1231 | } |
fdb28ac4 | 1232 | |
fdb28ac4 | 1233 | void |
7f7fe91e UW |
1234 | fill_fpregset (const struct regcache *regcache, |
1235 | gdb_fpregset_t *fpregsetp, int regno) | |
fdb28ac4 | 1236 | { |
f2db237a AM |
1237 | const struct regset *regset = ppc_linux_fpregset (); |
1238 | ||
1239 | ppc_collect_fpregset (regset, regcache, regno, | |
1240 | fpregsetp, sizeof (*fpregsetp)); | |
fdb28ac4 | 1241 | } |
10d6c8cd | 1242 | |
409c383c UW |
1243 | static int |
1244 | ppc_linux_target_wordsize (void) | |
1245 | { | |
1246 | int wordsize = 4; | |
1247 | ||
1248 | /* Check for 64-bit inferior process. This is the case when the host is | |
1249 | 64-bit, and in addition the top bit of the MSR register is set. */ | |
1250 | #ifdef __powerpc64__ | |
1251 | long msr; | |
1252 | ||
1253 | int tid = TIDGET (inferior_ptid); | |
1254 | if (tid == 0) | |
1255 | tid = PIDGET (inferior_ptid); | |
1256 | ||
1257 | errno = 0; | |
1258 | msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0); | |
1259 | if (errno == 0 && msr < 0) | |
1260 | wordsize = 8; | |
1261 | #endif | |
1262 | ||
1263 | return wordsize; | |
1264 | } | |
1265 | ||
1266 | static int | |
1267 | ppc_linux_auxv_parse (struct target_ops *ops, gdb_byte **readptr, | |
1268 | gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp) | |
1269 | { | |
1270 | int sizeof_auxv_field = ppc_linux_target_wordsize (); | |
1271 | gdb_byte *ptr = *readptr; | |
1272 | ||
1273 | if (endptr == ptr) | |
1274 | return 0; | |
1275 | ||
1276 | if (endptr - ptr < sizeof_auxv_field * 2) | |
1277 | return -1; | |
1278 | ||
1279 | *typep = extract_unsigned_integer (ptr, sizeof_auxv_field); | |
1280 | ptr += sizeof_auxv_field; | |
1281 | *valp = extract_unsigned_integer (ptr, sizeof_auxv_field); | |
1282 | ptr += sizeof_auxv_field; | |
1283 | ||
1284 | *readptr = ptr; | |
1285 | return 1; | |
1286 | } | |
1287 | ||
310a98e1 DJ |
1288 | static const struct target_desc * |
1289 | ppc_linux_read_description (struct target_ops *ops) | |
1290 | { | |
7284e1be | 1291 | int altivec = 0; |
604c2f83 | 1292 | int vsx = 0; |
69abc51c | 1293 | int isa205 = 0; |
7284e1be UW |
1294 | |
1295 | int tid = TIDGET (inferior_ptid); | |
1296 | if (tid == 0) | |
1297 | tid = PIDGET (inferior_ptid); | |
1298 | ||
310a98e1 DJ |
1299 | if (have_ptrace_getsetevrregs) |
1300 | { | |
1301 | struct gdb_evrregset_t evrregset; | |
310a98e1 DJ |
1302 | |
1303 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0) | |
7284e1be UW |
1304 | return tdesc_powerpc_e500l; |
1305 | ||
1306 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported. | |
1307 | Anything else needs to be reported. */ | |
1308 | else if (errno != EIO) | |
1309 | perror_with_name (_("Unable to fetch SPE registers")); | |
1310 | } | |
1311 | ||
604c2f83 LM |
1312 | if (have_ptrace_getsetvsxregs) |
1313 | { | |
1314 | gdb_vsxregset_t vsxregset; | |
1315 | ||
1316 | if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0) | |
1317 | vsx = 1; | |
1318 | ||
1319 | /* EIO means that the PTRACE_GETVSXREGS request isn't supported. | |
1320 | Anything else needs to be reported. */ | |
1321 | else if (errno != EIO) | |
1322 | perror_with_name (_("Unable to fetch VSX registers")); | |
1323 | } | |
1324 | ||
7284e1be UW |
1325 | if (have_ptrace_getvrregs) |
1326 | { | |
1327 | gdb_vrregset_t vrregset; | |
1328 | ||
1329 | if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0) | |
1330 | altivec = 1; | |
1331 | ||
1332 | /* EIO means that the PTRACE_GETVRREGS request isn't supported. | |
1333 | Anything else needs to be reported. */ | |
1334 | else if (errno != EIO) | |
1335 | perror_with_name (_("Unable to fetch AltiVec registers")); | |
310a98e1 DJ |
1336 | } |
1337 | ||
f04c6d38 TJB |
1338 | /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases |
1339 | the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this | |
1340 | ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only | |
1341 | PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher | |
1342 | half of the register are for Decimal Floating Point, we check if that | |
1343 | feature is available to decide the size of the FPSCR. */ | |
1344 | if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP) | |
69abc51c TJB |
1345 | isa205 = 1; |
1346 | ||
409c383c UW |
1347 | if (ppc_linux_target_wordsize () == 8) |
1348 | { | |
1349 | if (vsx) | |
1350 | return isa205? tdesc_powerpc_isa205_vsx64l : tdesc_powerpc_vsx64l; | |
1351 | else if (altivec) | |
1352 | return isa205? tdesc_powerpc_isa205_altivec64l : tdesc_powerpc_altivec64l; | |
1353 | ||
1354 | return isa205? tdesc_powerpc_isa205_64l : tdesc_powerpc_64l; | |
1355 | } | |
7284e1be | 1356 | |
604c2f83 | 1357 | if (vsx) |
69abc51c | 1358 | return isa205? tdesc_powerpc_isa205_vsx32l : tdesc_powerpc_vsx32l; |
604c2f83 | 1359 | else if (altivec) |
69abc51c | 1360 | return isa205? tdesc_powerpc_isa205_altivec32l : tdesc_powerpc_altivec32l; |
604c2f83 | 1361 | |
69abc51c | 1362 | return isa205? tdesc_powerpc_isa205_32l : tdesc_powerpc_32l; |
310a98e1 DJ |
1363 | } |
1364 | ||
10d6c8cd DJ |
1365 | void _initialize_ppc_linux_nat (void); |
1366 | ||
1367 | void | |
1368 | _initialize_ppc_linux_nat (void) | |
1369 | { | |
1370 | struct target_ops *t; | |
1371 | ||
1372 | /* Fill in the generic GNU/Linux methods. */ | |
1373 | t = linux_target (); | |
1374 | ||
1375 | /* Add our register access methods. */ | |
1376 | t->to_fetch_registers = ppc_linux_fetch_inferior_registers; | |
1377 | t->to_store_registers = ppc_linux_store_inferior_registers; | |
1378 | ||
e0d24f8d WZ |
1379 | /* Add our watchpoint methods. */ |
1380 | t->to_can_use_hw_breakpoint = ppc_linux_check_watch_resources; | |
1381 | t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint; | |
1382 | t->to_insert_watchpoint = ppc_linux_insert_watchpoint; | |
1383 | t->to_remove_watchpoint = ppc_linux_remove_watchpoint; | |
1384 | t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint; | |
1385 | t->to_stopped_data_address = ppc_linux_stopped_data_address; | |
5009afc5 | 1386 | t->to_watchpoint_addr_within_range = ppc_linux_watchpoint_addr_within_range; |
e0d24f8d | 1387 | |
310a98e1 | 1388 | t->to_read_description = ppc_linux_read_description; |
409c383c | 1389 | t->to_auxv_parse = ppc_linux_auxv_parse; |
310a98e1 | 1390 | |
10d6c8cd | 1391 | /* Register the target. */ |
f973ed9c | 1392 | linux_nat_add_target (t); |
9f0bdab8 | 1393 | linux_nat_set_new_thread (t, ppc_linux_new_thread); |
10d6c8cd | 1394 | } |