merge from gcc
[deliverable/binutils-gdb.git] / gdb / ppc-linux-nat.c
CommitLineData
9abe5450 1/* PPC GNU/Linux native support.
2555fe1a 2
197e01b6 3 Copyright (C) 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002,
c9dd6fef 4 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
c877c8e6
KB
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
197e01b6
EZ
20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
c877c8e6
KB
22
23#include "defs.h"
e162d11b 24#include "gdb_string.h"
c877c8e6
KB
25#include "frame.h"
26#include "inferior.h"
27#include "gdbcore.h"
4e052eda 28#include "regcache.h"
383f0f5b 29#include "gdb_assert.h"
10d6c8cd
DJ
30#include "target.h"
31#include "linux-nat.h"
c877c8e6
KB
32
33#include <sys/types.h>
34#include <sys/param.h>
35#include <signal.h>
36#include <sys/user.h>
37#include <sys/ioctl.h>
2555fe1a 38#include "gdb_wait.h"
c877c8e6
KB
39#include <fcntl.h>
40#include <sys/procfs.h>
45229ea4 41#include <sys/ptrace.h>
c877c8e6 42
c60c0f5f
MS
43/* Prototypes for supply_gregset etc. */
44#include "gregset.h"
16333c4f 45#include "ppc-tdep.h"
c60c0f5f 46
45229ea4
EZ
47#ifndef PT_READ_U
48#define PT_READ_U PTRACE_PEEKUSR
49#endif
50#ifndef PT_WRITE_U
51#define PT_WRITE_U PTRACE_POKEUSR
52#endif
53
54/* Default the type of the ptrace transfer to int. */
55#ifndef PTRACE_XFER_TYPE
56#define PTRACE_XFER_TYPE int
57#endif
58
9abe5450
EZ
59/* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
60 configure time check. Some older glibc's (for instance 2.2.1)
61 don't have a specific powerpc version of ptrace.h, and fall back on
62 a generic one. In such cases, sys/ptrace.h defines
63 PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that
64 ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and
65 PTRACE_SETVRREGS to be. This also makes a configury check pretty
66 much useless. */
67
68/* These definitions should really come from the glibc header files,
69 but Glibc doesn't know about the vrregs yet. */
70#ifndef PTRACE_GETVRREGS
71#define PTRACE_GETVRREGS 18
72#define PTRACE_SETVRREGS 19
73#endif
74
01904826
JB
75
76/* Similarly for the ptrace requests for getting / setting the SPE
77 registers (ev0 -- ev31, acc, and spefscr). See the description of
78 gdb_evrregset_t for details. */
79#ifndef PTRACE_GETEVRREGS
80#define PTRACE_GETEVRREGS 20
81#define PTRACE_SETEVRREGS 21
82#endif
83
e0d24f8d
WZ
84/* Similarly for the hardware watchpoint support. */
85#ifndef PTRACE_GET_DEBUGREG
86#define PTRACE_GET_DEBUGREG 25
87#endif
88#ifndef PTRACE_SET_DEBUGREG
89#define PTRACE_SET_DEBUGREG 26
90#endif
91#ifndef PTRACE_GETSIGINFO
92#define PTRACE_GETSIGINFO 0x4202
93#endif
01904826 94
9abe5450
EZ
95/* This oddity is because the Linux kernel defines elf_vrregset_t as
96 an array of 33 16 bytes long elements. I.e. it leaves out vrsave.
97 However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
98 the vrsave as an extra 4 bytes at the end. I opted for creating a
99 flat array of chars, so that it is easier to manipulate for gdb.
100
101 There are 32 vector registers 16 bytes longs, plus a VSCR register
102 which is only 4 bytes long, but is fetched as a 16 bytes
103 quantity. Up to here we have the elf_vrregset_t structure.
104 Appended to this there is space for the VRSAVE register: 4 bytes.
105 Even though this vrsave register is not included in the regset
106 typedef, it is handled by the ptrace requests.
107
108 Note that GNU/Linux doesn't support little endian PPC hardware,
109 therefore the offset at which the real value of the VSCR register
110 is located will be always 12 bytes.
111
112 The layout is like this (where x is the actual value of the vscr reg): */
113
114/* *INDENT-OFF* */
115/*
116 |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
117 <-------> <-------><-------><->
118 VR0 VR31 VSCR VRSAVE
119*/
120/* *INDENT-ON* */
121
122#define SIZEOF_VRREGS 33*16+4
123
124typedef char gdb_vrregset_t[SIZEOF_VRREGS];
125
01904826
JB
126
127/* On PPC processors that support the the Signal Processing Extension
128 (SPE) APU, the general-purpose registers are 64 bits long.
9cbc6ef0
AC
129 However, the ordinary Linux kernel PTRACE_PEEKUSR / PTRACE_POKEUSR
130 / PT_READ_U / PT_WRITE_U ptrace calls only access the lower half of
01904826
JB
131 each register, to allow them to behave the same way they do on
132 non-SPE systems. There's a separate pair of calls,
133 PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that read and write the top
134 halves of all the general-purpose registers at once, along with
135 some SPE-specific registers.
136
137 GDB itself continues to claim the general-purpose registers are 32
6ced10dd
JB
138 bits long. It has unnamed raw registers that hold the upper halves
139 of the gprs, and the the full 64-bit SIMD views of the registers,
140 'ev0' -- 'ev31', are pseudo-registers that splice the top and
141 bottom halves together.
01904826
JB
142
143 This is the structure filled in by PTRACE_GETEVRREGS and written to
144 the inferior's registers by PTRACE_SETEVRREGS. */
145struct gdb_evrregset_t
146{
147 unsigned long evr[32];
148 unsigned long long acc;
149 unsigned long spefscr;
150};
151
152
153/* Non-zero if our kernel may support the PTRACE_GETVRREGS and
154 PTRACE_SETVRREGS requests, for reading and writing the Altivec
155 registers. Zero if we've tried one of them and gotten an
156 error. */
9abe5450
EZ
157int have_ptrace_getvrregs = 1;
158
e0d24f8d 159static CORE_ADDR last_stopped_data_address = 0;
01904826
JB
160
161/* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
162 PTRACE_SETEVRREGS requests, for reading and writing the SPE
163 registers. Zero if we've tried one of them and gotten an
164 error. */
165int have_ptrace_getsetevrregs = 1;
166
c877c8e6 167int
fba45db2 168kernel_u_size (void)
c877c8e6
KB
169{
170 return (sizeof (struct user));
171}
172
16333c4f
EZ
173/* *INDENT-OFF* */
174/* registers layout, as presented by the ptrace interface:
175PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
176PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
177PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
178PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
179PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
180PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
181PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
182PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
183PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
184/* *INDENT_ON * */
c877c8e6 185
45229ea4
EZ
186static int
187ppc_register_u_addr (int regno)
c877c8e6 188{
16333c4f 189 int u_addr = -1;
dc5cfeb6 190 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
56d0d96a
AC
191 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
192 interface, and not the wordsize of the program's ABI. */
193 int wordsize = sizeof (PTRACE_XFER_TYPE);
16333c4f
EZ
194
195 /* General purpose registers occupy 1 slot each in the buffer */
8bf659e8
JB
196 if (regno >= tdep->ppc_gp0_regnum
197 && regno < tdep->ppc_gp0_regnum + ppc_num_gprs)
26e75e5c 198 u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize);
16333c4f 199
49ff75ad
JB
200 /* Floating point regs: eight bytes each in both 32- and 64-bit
201 ptrace interfaces. Thus, two slots each in 32-bit interface, one
202 slot each in 64-bit interface. */
383f0f5b
JB
203 if (tdep->ppc_fp0_regnum >= 0
204 && regno >= tdep->ppc_fp0_regnum
366f009f
JB
205 && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)
206 u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8);
16333c4f
EZ
207
208 /* UISA special purpose registers: 1 slot each */
209 if (regno == PC_REGNUM)
49ff75ad 210 u_addr = PT_NIP * wordsize;
dc5cfeb6 211 if (regno == tdep->ppc_lr_regnum)
49ff75ad 212 u_addr = PT_LNK * wordsize;
dc5cfeb6 213 if (regno == tdep->ppc_cr_regnum)
49ff75ad 214 u_addr = PT_CCR * wordsize;
dc5cfeb6 215 if (regno == tdep->ppc_xer_regnum)
49ff75ad 216 u_addr = PT_XER * wordsize;
dc5cfeb6 217 if (regno == tdep->ppc_ctr_regnum)
49ff75ad 218 u_addr = PT_CTR * wordsize;
f8c59253 219#ifdef PT_MQ
dc5cfeb6 220 if (regno == tdep->ppc_mq_regnum)
49ff75ad 221 u_addr = PT_MQ * wordsize;
f8c59253 222#endif
dc5cfeb6 223 if (regno == tdep->ppc_ps_regnum)
49ff75ad 224 u_addr = PT_MSR * wordsize;
383f0f5b
JB
225 if (tdep->ppc_fpscr_regnum >= 0
226 && regno == tdep->ppc_fpscr_regnum)
8f135812
AC
227 {
228 /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
229 kernel headers incorrectly contained the 32-bit definition of
230 PT_FPSCR. For the 32-bit definition, floating-point
231 registers occupy two 32-bit "slots", and the FPSCR lives in
232 the secondhalf of such a slot-pair (hence +1). For 64-bit,
233 the FPSCR instead occupies the full 64-bit 2-word-slot and
234 hence no adjustment is necessary. Hack around this. */
235 if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1))
236 u_addr = (48 + 32) * wordsize;
237 else
238 u_addr = PT_FPSCR * wordsize;
239 }
16333c4f 240 return u_addr;
c877c8e6
KB
241}
242
9abe5450
EZ
243/* The Linux kernel ptrace interface for AltiVec registers uses the
244 registers set mechanism, as opposed to the interface for all the
245 other registers, that stores/fetches each register individually. */
246static void
247fetch_altivec_register (int tid, int regno)
248{
249 int ret;
250 int offset = 0;
251 gdb_vrregset_t regs;
252 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3acba339 253 int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum);
9abe5450
EZ
254
255 ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
256 if (ret < 0)
257 {
258 if (errno == EIO)
259 {
260 have_ptrace_getvrregs = 0;
261 return;
262 }
e2e0b3e5 263 perror_with_name (_("Unable to fetch AltiVec register"));
9abe5450
EZ
264 }
265
266 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
267 long on the hardware. We deal only with the lower 4 bytes of the
268 vector. VRSAVE is at the end of the array in a 4 bytes slot, so
269 there is no need to define an offset for it. */
270 if (regno == (tdep->ppc_vrsave_regnum - 1))
3acba339 271 offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum);
9abe5450 272
23a6d369
AC
273 regcache_raw_supply (current_regcache, regno,
274 regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset);
9abe5450
EZ
275}
276
01904826
JB
277/* Fetch the top 32 bits of TID's general-purpose registers and the
278 SPE-specific registers, and place the results in EVRREGSET. If we
279 don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
280 zeros.
281
282 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
283 PTRACE_SETEVRREGS requests are supported is isolated here, and in
284 set_spe_registers. */
285static void
286get_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
287{
288 if (have_ptrace_getsetevrregs)
289 {
290 if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0)
291 return;
292 else
293 {
294 /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
295 we just return zeros. */
296 if (errno == EIO)
297 have_ptrace_getsetevrregs = 0;
298 else
299 /* Anything else needs to be reported. */
e2e0b3e5 300 perror_with_name (_("Unable to fetch SPE registers"));
01904826
JB
301 }
302 }
303
304 memset (evrregset, 0, sizeof (*evrregset));
305}
306
6ced10dd
JB
307/* Supply values from TID for SPE-specific raw registers: the upper
308 halves of the GPRs, the accumulator, and the spefscr. REGNO must
309 be the number of an upper half register, acc, spefscr, or -1 to
310 supply the values of all registers. */
01904826
JB
311static void
312fetch_spe_register (int tid, int regno)
313{
314 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
315 struct gdb_evrregset_t evrregs;
316
6ced10dd
JB
317 gdb_assert (sizeof (evrregs.evr[0])
318 == register_size (current_gdbarch, tdep->ppc_ev0_upper_regnum));
319 gdb_assert (sizeof (evrregs.acc)
320 == register_size (current_gdbarch, tdep->ppc_acc_regnum));
321 gdb_assert (sizeof (evrregs.spefscr)
322 == register_size (current_gdbarch, tdep->ppc_spefscr_regnum));
323
01904826
JB
324 get_spe_registers (tid, &evrregs);
325
6ced10dd 326 if (regno == -1)
01904826 327 {
6ced10dd
JB
328 int i;
329
330 for (i = 0; i < ppc_num_gprs; i++)
331 regcache_raw_supply (current_regcache, tdep->ppc_ev0_upper_regnum + i,
332 &evrregs.evr[i]);
01904826 333 }
6ced10dd
JB
334 else if (tdep->ppc_ev0_upper_regnum <= regno
335 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
336 regcache_raw_supply (current_regcache, regno,
337 &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
338
339 if (regno == -1
340 || regno == tdep->ppc_acc_regnum)
341 regcache_raw_supply (current_regcache, tdep->ppc_acc_regnum, &evrregs.acc);
342
343 if (regno == -1
344 || regno == tdep->ppc_spefscr_regnum)
345 regcache_raw_supply (current_regcache, tdep->ppc_spefscr_regnum,
346 &evrregs.spefscr);
01904826
JB
347}
348
45229ea4 349static void
05f13b9c 350fetch_register (int tid, int regno)
45229ea4 351{
366f009f 352 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
45229ea4 353 /* This isn't really an address. But ptrace thinks of it as one. */
0397dee1 354 CORE_ADDR regaddr = ppc_register_u_addr (regno);
4a19ea35 355 int bytes_transferred;
45229ea4 356 unsigned int offset; /* Offset of registers within the u area. */
d9d9c31f 357 char buf[MAX_REGISTER_SIZE];
45229ea4 358
9abe5450
EZ
359 if (altivec_register_p (regno))
360 {
361 /* If this is the first time through, or if it is not the first
362 time through, and we have comfirmed that there is kernel
363 support for such a ptrace request, then go and fetch the
364 register. */
365 if (have_ptrace_getvrregs)
366 {
367 fetch_altivec_register (tid, regno);
368 return;
369 }
370 /* If we have discovered that there is no ptrace support for
371 AltiVec registers, fall through and return zeroes, because
372 regaddr will be -1 in this case. */
373 }
01904826
JB
374 else if (spe_register_p (regno))
375 {
376 fetch_spe_register (tid, regno);
377 return;
378 }
9abe5450 379
45229ea4
EZ
380 if (regaddr == -1)
381 {
3acba339 382 memset (buf, '\0', register_size (current_gdbarch, regno)); /* Supply zeroes */
23a6d369 383 regcache_raw_supply (current_regcache, regno, buf);
45229ea4
EZ
384 return;
385 }
386
56d0d96a
AC
387 /* Read the raw register using PTRACE_XFER_TYPE sized chunks. On a
388 32-bit platform, 64-bit floating-point registers will require two
389 transfers. */
4a19ea35 390 for (bytes_transferred = 0;
8327ccee 391 bytes_transferred < register_size (current_gdbarch, regno);
4a19ea35 392 bytes_transferred += sizeof (PTRACE_XFER_TYPE))
45229ea4
EZ
393 {
394 errno = 0;
4a19ea35
JB
395 *(PTRACE_XFER_TYPE *) & buf[bytes_transferred]
396 = ptrace (PT_READ_U, tid, (PTRACE_ARG3_TYPE) regaddr, 0);
45229ea4
EZ
397 regaddr += sizeof (PTRACE_XFER_TYPE);
398 if (errno != 0)
399 {
bc97b3ba
JB
400 char message[128];
401 sprintf (message, "reading register %s (#%d)",
45229ea4 402 REGISTER_NAME (regno), regno);
bc97b3ba 403 perror_with_name (message);
45229ea4
EZ
404 }
405 }
56d0d96a 406
4a19ea35
JB
407 /* Now supply the register. Keep in mind that the regcache's idea
408 of the register's size may not be a multiple of sizeof
409 (PTRACE_XFER_TYPE). */
410 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
411 {
412 /* Little-endian values are always found at the left end of the
413 bytes transferred. */
414 regcache_raw_supply (current_regcache, regno, buf);
415 }
416 else if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
417 {
418 /* Big-endian values are found at the right end of the bytes
419 transferred. */
420 size_t padding = (bytes_transferred
421 - register_size (current_gdbarch, regno));
422 regcache_raw_supply (current_regcache, regno, buf + padding);
423 }
424 else
a44bddec 425 internal_error (__FILE__, __LINE__,
e2e0b3e5 426 _("fetch_register: unexpected byte order: %d"),
a44bddec 427 gdbarch_byte_order (current_gdbarch));
45229ea4
EZ
428}
429
9abe5450
EZ
430static void
431supply_vrregset (gdb_vrregset_t *vrregsetp)
432{
433 int i;
434 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
435 int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
3acba339
AC
436 int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum);
437 int offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum);
9abe5450
EZ
438
439 for (i = 0; i < num_of_vrregs; i++)
440 {
441 /* The last 2 registers of this set are only 32 bit long, not
442 128. However an offset is necessary only for VSCR because it
443 occupies a whole vector, while VRSAVE occupies a full 4 bytes
444 slot. */
445 if (i == (num_of_vrregs - 2))
23a6d369
AC
446 regcache_raw_supply (current_regcache, tdep->ppc_vr0_regnum + i,
447 *vrregsetp + i * vrregsize + offset);
9abe5450 448 else
23a6d369
AC
449 regcache_raw_supply (current_regcache, tdep->ppc_vr0_regnum + i,
450 *vrregsetp + i * vrregsize);
9abe5450
EZ
451 }
452}
453
454static void
455fetch_altivec_registers (int tid)
456{
457 int ret;
458 gdb_vrregset_t regs;
459
460 ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
461 if (ret < 0)
462 {
463 if (errno == EIO)
464 {
465 have_ptrace_getvrregs = 0;
466 return;
467 }
e2e0b3e5 468 perror_with_name (_("Unable to fetch AltiVec registers"));
9abe5450
EZ
469 }
470 supply_vrregset (&regs);
471}
472
45229ea4 473static void
05f13b9c 474fetch_ppc_registers (int tid)
45229ea4
EZ
475{
476 int i;
9abe5450
EZ
477 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
478
6ced10dd
JB
479 for (i = 0; i < ppc_num_gprs; i++)
480 fetch_register (tid, tdep->ppc_gp0_regnum + i);
32b99774
JB
481 if (tdep->ppc_fp0_regnum >= 0)
482 for (i = 0; i < ppc_num_fprs; i++)
483 fetch_register (tid, tdep->ppc_fp0_regnum + i);
484 fetch_register (tid, PC_REGNUM);
485 if (tdep->ppc_ps_regnum != -1)
486 fetch_register (tid, tdep->ppc_ps_regnum);
487 if (tdep->ppc_cr_regnum != -1)
488 fetch_register (tid, tdep->ppc_cr_regnum);
489 if (tdep->ppc_lr_regnum != -1)
490 fetch_register (tid, tdep->ppc_lr_regnum);
491 if (tdep->ppc_ctr_regnum != -1)
492 fetch_register (tid, tdep->ppc_ctr_regnum);
493 if (tdep->ppc_xer_regnum != -1)
494 fetch_register (tid, tdep->ppc_xer_regnum);
e3f36dbd
KB
495 if (tdep->ppc_mq_regnum != -1)
496 fetch_register (tid, tdep->ppc_mq_regnum);
32b99774
JB
497 if (tdep->ppc_fpscr_regnum != -1)
498 fetch_register (tid, tdep->ppc_fpscr_regnum);
9abe5450
EZ
499 if (have_ptrace_getvrregs)
500 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
501 fetch_altivec_registers (tid);
6ced10dd
JB
502 if (tdep->ppc_ev0_upper_regnum >= 0)
503 fetch_spe_register (tid, -1);
45229ea4
EZ
504}
505
506/* Fetch registers from the child process. Fetch all registers if
507 regno == -1, otherwise fetch all general registers or all floating
508 point registers depending upon the value of regno. */
10d6c8cd
DJ
509static void
510ppc_linux_fetch_inferior_registers (int regno)
45229ea4 511{
9abe5450 512 /* Overload thread id onto process id */
05f13b9c
EZ
513 int tid = TIDGET (inferior_ptid);
514
515 /* No thread id, just use process id */
516 if (tid == 0)
517 tid = PIDGET (inferior_ptid);
518
9abe5450 519 if (regno == -1)
05f13b9c 520 fetch_ppc_registers (tid);
45229ea4 521 else
05f13b9c 522 fetch_register (tid, regno);
45229ea4
EZ
523}
524
525/* Store one register. */
9abe5450
EZ
526static void
527store_altivec_register (int tid, int regno)
528{
529 int ret;
530 int offset = 0;
531 gdb_vrregset_t regs;
532 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3acba339 533 int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum);
9abe5450
EZ
534
535 ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
536 if (ret < 0)
537 {
538 if (errno == EIO)
539 {
540 have_ptrace_getvrregs = 0;
541 return;
542 }
e2e0b3e5 543 perror_with_name (_("Unable to fetch AltiVec register"));
9abe5450
EZ
544 }
545
546 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
547 long on the hardware. */
548 if (regno == (tdep->ppc_vrsave_regnum - 1))
3acba339 549 offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum);
9abe5450 550
822c9732
AC
551 regcache_raw_collect (current_regcache, regno,
552 regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset);
9abe5450
EZ
553
554 ret = ptrace (PTRACE_SETVRREGS, tid, 0, &regs);
555 if (ret < 0)
e2e0b3e5 556 perror_with_name (_("Unable to store AltiVec register"));
9abe5450
EZ
557}
558
01904826
JB
559/* Assuming TID referrs to an SPE process, set the top halves of TID's
560 general-purpose registers and its SPE-specific registers to the
561 values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do
562 nothing.
563
564 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
565 PTRACE_SETEVRREGS requests are supported is isolated here, and in
566 get_spe_registers. */
567static void
568set_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
569{
570 if (have_ptrace_getsetevrregs)
571 {
572 if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0)
573 return;
574 else
575 {
576 /* EIO means that the PTRACE_SETEVRREGS request isn't
577 supported; we fail silently, and don't try the call
578 again. */
579 if (errno == EIO)
580 have_ptrace_getsetevrregs = 0;
581 else
582 /* Anything else needs to be reported. */
e2e0b3e5 583 perror_with_name (_("Unable to set SPE registers"));
01904826
JB
584 }
585 }
586}
587
6ced10dd
JB
588/* Write GDB's value for the SPE-specific raw register REGNO to TID.
589 If REGNO is -1, write the values of all the SPE-specific
590 registers. */
01904826
JB
591static void
592store_spe_register (int tid, int regno)
593{
594 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
595 struct gdb_evrregset_t evrregs;
596
6ced10dd
JB
597 gdb_assert (sizeof (evrregs.evr[0])
598 == register_size (current_gdbarch, tdep->ppc_ev0_upper_regnum));
599 gdb_assert (sizeof (evrregs.acc)
600 == register_size (current_gdbarch, tdep->ppc_acc_regnum));
601 gdb_assert (sizeof (evrregs.spefscr)
602 == register_size (current_gdbarch, tdep->ppc_spefscr_regnum));
01904826 603
6ced10dd
JB
604 if (regno == -1)
605 /* Since we're going to write out every register, the code below
606 should store to every field of evrregs; if that doesn't happen,
607 make it obvious by initializing it with suspicious values. */
608 memset (&evrregs, 42, sizeof (evrregs));
609 else
610 /* We can only read and write the entire EVR register set at a
611 time, so to write just a single register, we do a
612 read-modify-write maneuver. */
613 get_spe_registers (tid, &evrregs);
614
615 if (regno == -1)
01904826 616 {
6ced10dd
JB
617 int i;
618
619 for (i = 0; i < ppc_num_gprs; i++)
620 regcache_raw_collect (current_regcache,
621 tdep->ppc_ev0_upper_regnum + i,
622 &evrregs.evr[i]);
01904826 623 }
6ced10dd
JB
624 else if (tdep->ppc_ev0_upper_regnum <= regno
625 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
626 regcache_raw_collect (current_regcache, regno,
627 &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
628
629 if (regno == -1
630 || regno == tdep->ppc_acc_regnum)
631 regcache_raw_collect (current_regcache,
632 tdep->ppc_acc_regnum,
633 &evrregs.acc);
634
635 if (regno == -1
636 || regno == tdep->ppc_spefscr_regnum)
637 regcache_raw_collect (current_regcache,
638 tdep->ppc_spefscr_regnum,
639 &evrregs.spefscr);
01904826
JB
640
641 /* Write back the modified register set. */
642 set_spe_registers (tid, &evrregs);
643}
644
45229ea4 645static void
05f13b9c 646store_register (int tid, int regno)
45229ea4 647{
366f009f 648 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
45229ea4
EZ
649 /* This isn't really an address. But ptrace thinks of it as one. */
650 CORE_ADDR regaddr = ppc_register_u_addr (regno);
52f0bd74 651 int i;
4a19ea35 652 size_t bytes_to_transfer;
d9d9c31f 653 char buf[MAX_REGISTER_SIZE];
45229ea4 654
9abe5450 655 if (altivec_register_p (regno))
45229ea4 656 {
9abe5450 657 store_altivec_register (tid, regno);
45229ea4
EZ
658 return;
659 }
01904826
JB
660 else if (spe_register_p (regno))
661 {
662 store_spe_register (tid, regno);
663 return;
664 }
45229ea4 665
9abe5450
EZ
666 if (regaddr == -1)
667 return;
668
4a19ea35
JB
669 /* First collect the register. Keep in mind that the regcache's
670 idea of the register's size may not be a multiple of sizeof
671 (PTRACE_XFER_TYPE). */
56d0d96a 672 memset (buf, 0, sizeof buf);
4a19ea35
JB
673 bytes_to_transfer = align_up (register_size (current_gdbarch, regno),
674 sizeof (PTRACE_XFER_TYPE));
675 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
676 {
677 /* Little-endian values always sit at the left end of the buffer. */
678 regcache_raw_collect (current_regcache, regno, buf);
679 }
680 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
681 {
682 /* Big-endian values sit at the right end of the buffer. */
683 size_t padding = (bytes_to_transfer
684 - register_size (current_gdbarch, regno));
685 regcache_raw_collect (current_regcache, regno, buf + padding);
686 }
687
688 for (i = 0; i < bytes_to_transfer; i += sizeof (PTRACE_XFER_TYPE))
45229ea4
EZ
689 {
690 errno = 0;
691 ptrace (PT_WRITE_U, tid, (PTRACE_ARG3_TYPE) regaddr,
692 *(PTRACE_XFER_TYPE *) & buf[i]);
693 regaddr += sizeof (PTRACE_XFER_TYPE);
e3f36dbd
KB
694
695 if (errno == EIO
383f0f5b 696 && regno == tdep->ppc_fpscr_regnum)
e3f36dbd
KB
697 {
698 /* Some older kernel versions don't allow fpscr to be written. */
699 continue;
700 }
701
45229ea4
EZ
702 if (errno != 0)
703 {
bc97b3ba
JB
704 char message[128];
705 sprintf (message, "writing register %s (#%d)",
45229ea4 706 REGISTER_NAME (regno), regno);
bc97b3ba 707 perror_with_name (message);
45229ea4
EZ
708 }
709 }
710}
711
9abe5450
EZ
712static void
713fill_vrregset (gdb_vrregset_t *vrregsetp)
714{
715 int i;
716 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
717 int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
3acba339
AC
718 int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum);
719 int offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum);
9abe5450
EZ
720
721 for (i = 0; i < num_of_vrregs; i++)
722 {
723 /* The last 2 registers of this set are only 32 bit long, not
724 128, but only VSCR is fetched as a 16 bytes quantity. */
725 if (i == (num_of_vrregs - 2))
822c9732
AC
726 regcache_raw_collect (current_regcache, tdep->ppc_vr0_regnum + i,
727 *vrregsetp + i * vrregsize + offset);
9abe5450 728 else
822c9732
AC
729 regcache_raw_collect (current_regcache, tdep->ppc_vr0_regnum + i,
730 *vrregsetp + i * vrregsize);
9abe5450
EZ
731 }
732}
733
734static void
735store_altivec_registers (int tid)
736{
737 int ret;
738 gdb_vrregset_t regs;
739
0897f59b 740 ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
9abe5450
EZ
741 if (ret < 0)
742 {
743 if (errno == EIO)
744 {
745 have_ptrace_getvrregs = 0;
746 return;
747 }
e2e0b3e5 748 perror_with_name (_("Couldn't get AltiVec registers"));
9abe5450
EZ
749 }
750
751 fill_vrregset (&regs);
752
0897f59b 753 if (ptrace (PTRACE_SETVRREGS, tid, 0, &regs) < 0)
e2e0b3e5 754 perror_with_name (_("Couldn't write AltiVec registers"));
9abe5450
EZ
755}
756
45229ea4 757static void
05f13b9c 758store_ppc_registers (int tid)
45229ea4
EZ
759{
760 int i;
9abe5450 761 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
45229ea4 762
6ced10dd
JB
763 for (i = 0; i < ppc_num_gprs; i++)
764 store_register (tid, tdep->ppc_gp0_regnum + i);
32b99774
JB
765 if (tdep->ppc_fp0_regnum >= 0)
766 for (i = 0; i < ppc_num_fprs; i++)
767 store_register (tid, tdep->ppc_fp0_regnum + i);
768 store_register (tid, PC_REGNUM);
769 if (tdep->ppc_ps_regnum != -1)
770 store_register (tid, tdep->ppc_ps_regnum);
771 if (tdep->ppc_cr_regnum != -1)
772 store_register (tid, tdep->ppc_cr_regnum);
773 if (tdep->ppc_lr_regnum != -1)
774 store_register (tid, tdep->ppc_lr_regnum);
775 if (tdep->ppc_ctr_regnum != -1)
776 store_register (tid, tdep->ppc_ctr_regnum);
777 if (tdep->ppc_xer_regnum != -1)
778 store_register (tid, tdep->ppc_xer_regnum);
e3f36dbd
KB
779 if (tdep->ppc_mq_regnum != -1)
780 store_register (tid, tdep->ppc_mq_regnum);
32b99774
JB
781 if (tdep->ppc_fpscr_regnum != -1)
782 store_register (tid, tdep->ppc_fpscr_regnum);
9abe5450
EZ
783 if (have_ptrace_getvrregs)
784 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
785 store_altivec_registers (tid);
6ced10dd
JB
786 if (tdep->ppc_ev0_upper_regnum >= 0)
787 store_spe_register (tid, -1);
45229ea4
EZ
788}
789
e0d24f8d
WZ
790static int
791ppc_linux_check_watch_resources (int type, int cnt, int ot)
792{
793 int tid;
794 ptid_t ptid = inferior_ptid;
795
796 /* DABR (data address breakpoint register) is optional for PPC variants.
797 Some variants have one DABR, others have none. So CNT can't be larger
798 than 1. */
799 if (cnt > 1)
800 return 0;
801
802 /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG and whether
803 the target has DABR. If either answer is no, the ptrace call will
804 return -1. Fail in that case. */
805 tid = TIDGET (ptid);
806 if (tid == 0)
807 tid = PIDGET (ptid);
808
809 if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1)
810 return 0;
811 return 1;
812}
813
814static int
815ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len)
816{
817 /* Handle sub-8-byte quantities. */
818 if (len <= 0)
819 return 0;
820
821 /* addr+len must fall in the 8 byte watchable region. */
822 if ((addr + len) > (addr & ~7) + 8)
823 return 0;
824
825 return 1;
826}
827
828/* Set a watchpoint of type TYPE at address ADDR. */
2c387241 829static int
e0d24f8d
WZ
830ppc_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw)
831{
832 int tid;
833 long dabr_value;
834 ptid_t ptid = inferior_ptid;
835
836 dabr_value = addr & ~7;
837 switch (rw)
838 {
839 case hw_read:
840 /* Set read and translate bits. */
841 dabr_value |= 5;
842 break;
843 case hw_write:
844 /* Set write and translate bits. */
845 dabr_value |= 6;
846 break;
847 case hw_access:
848 /* Set read, write and translate bits. */
849 dabr_value |= 7;
850 break;
851 }
852
853 tid = TIDGET (ptid);
854 if (tid == 0)
855 tid = PIDGET (ptid);
856
857 return ptrace (PTRACE_SET_DEBUGREG, tid, 0, dabr_value);
858}
859
2c387241
AM
860static int
861ppc_linux_remove_watchpoint (CORE_ADDR addr, int len, int rw)
e0d24f8d
WZ
862{
863 int tid;
864 ptid_t ptid = inferior_ptid;
865
866 tid = TIDGET (ptid);
867 if (tid == 0)
868 tid = PIDGET (ptid);
869
870 return ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0);
871}
872
873static int
874ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p)
875{
876 if (last_stopped_data_address)
877 {
878 *addr_p = last_stopped_data_address;
879 last_stopped_data_address = 0;
880 return 1;
881 }
882 return 0;
883}
884
885static int
886ppc_linux_stopped_by_watchpoint (void)
887{
888 int tid;
889 struct siginfo siginfo;
890 ptid_t ptid = inferior_ptid;
891 CORE_ADDR *addr_p;
892
893 tid = TIDGET(ptid);
894 if (tid == 0)
895 tid = PIDGET (ptid);
896
897 errno = 0;
898 ptrace (PTRACE_GETSIGINFO, tid, (PTRACE_TYPE_ARG3) 0, &siginfo);
899
900 if (errno != 0 || siginfo.si_signo != SIGTRAP ||
901 (siginfo.si_code & 0xffff) != 0x0004)
902 return 0;
903
904 last_stopped_data_address = (CORE_ADDR) siginfo.si_addr;
905 return 1;
906}
907
10d6c8cd
DJ
908static void
909ppc_linux_store_inferior_registers (int regno)
45229ea4 910{
05f13b9c
EZ
911 /* Overload thread id onto process id */
912 int tid = TIDGET (inferior_ptid);
913
914 /* No thread id, just use process id */
915 if (tid == 0)
916 tid = PIDGET (inferior_ptid);
917
45229ea4 918 if (regno >= 0)
05f13b9c 919 store_register (tid, regno);
45229ea4 920 else
05f13b9c 921 store_ppc_registers (tid);
45229ea4
EZ
922}
923
50c9bd31 924void
8ae45c11 925supply_gregset (gdb_gregset_t *gregsetp)
c877c8e6 926{
f9be684a
AC
927 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
928 interface, and not the wordsize of the program's ABI. */
929 int wordsize = sizeof (PTRACE_XFER_TYPE);
930 ppc_linux_supply_gregset (current_regcache, -1, gregsetp,
931 sizeof (gdb_gregset_t), wordsize);
932}
933
934static void
935right_fill_reg (int regnum, void *reg)
936{
937 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
938 interface, and not the wordsize of the program's ABI. */
939 int wordsize = sizeof (PTRACE_XFER_TYPE);
940 /* Right fill the register. */
941 regcache_raw_collect (current_regcache, regnum,
942 ((bfd_byte *) reg
943 + wordsize
944 - register_size (current_gdbarch, regnum)));
c877c8e6
KB
945}
946
fdb28ac4 947void
8ae45c11 948fill_gregset (gdb_gregset_t *gregsetp, int regno)
fdb28ac4
KB
949{
950 int regi;
2ac44c70 951 elf_greg_t *regp = (elf_greg_t *) gregsetp;
dc5cfeb6 952 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
f9be684a
AC
953 const int elf_ngreg = 48;
954
955
956 /* Start with zeros. */
957 memset (regp, 0, elf_ngreg * sizeof (*regp));
fdb28ac4 958
063715bf 959 for (regi = 0; regi < ppc_num_gprs; regi++)
fdb28ac4 960 {
cdf2c5f5
JB
961 if ((regno == -1) || regno == tdep->ppc_gp0_regnum + regi)
962 right_fill_reg (tdep->ppc_gp0_regnum + regi, (regp + PT_R0 + regi));
fdb28ac4
KB
963 }
964
16333c4f 965 if ((regno == -1) || regno == PC_REGNUM)
f9be684a 966 right_fill_reg (PC_REGNUM, regp + PT_NIP);
05f13b9c 967 if ((regno == -1) || regno == tdep->ppc_lr_regnum)
f9be684a 968 right_fill_reg (tdep->ppc_lr_regnum, regp + PT_LNK);
05f13b9c 969 if ((regno == -1) || regno == tdep->ppc_cr_regnum)
822c9732
AC
970 regcache_raw_collect (current_regcache, tdep->ppc_cr_regnum,
971 regp + PT_CCR);
05f13b9c 972 if ((regno == -1) || regno == tdep->ppc_xer_regnum)
822c9732
AC
973 regcache_raw_collect (current_regcache, tdep->ppc_xer_regnum,
974 regp + PT_XER);
05f13b9c 975 if ((regno == -1) || regno == tdep->ppc_ctr_regnum)
f9be684a 976 right_fill_reg (tdep->ppc_ctr_regnum, regp + PT_CTR);
f8c59253 977#ifdef PT_MQ
e3f36dbd
KB
978 if (((regno == -1) || regno == tdep->ppc_mq_regnum)
979 && (tdep->ppc_mq_regnum != -1))
f9be684a 980 right_fill_reg (tdep->ppc_mq_regnum, regp + PT_MQ);
f8c59253 981#endif
05f13b9c 982 if ((regno == -1) || regno == tdep->ppc_ps_regnum)
f9be684a 983 right_fill_reg (tdep->ppc_ps_regnum, regp + PT_MSR);
fdb28ac4
KB
984}
985
50c9bd31 986void
8ae45c11 987supply_fpregset (gdb_fpregset_t * fpregsetp)
c877c8e6 988{
f9be684a
AC
989 ppc_linux_supply_fpregset (NULL, current_regcache, -1, fpregsetp,
990 sizeof (gdb_fpregset_t));
c877c8e6 991}
fdb28ac4 992
9abe5450
EZ
993/* Given a pointer to a floating point register set in /proc format
994 (fpregset_t *), update the register specified by REGNO from gdb's
995 idea of the current floating point register set. If REGNO is -1,
996 update them all. */
fdb28ac4 997void
8ae45c11 998fill_fpregset (gdb_fpregset_t *fpregsetp, int regno)
fdb28ac4
KB
999{
1000 int regi;
e3f36dbd 1001 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
f9be684a 1002 bfd_byte *fpp = (void *) fpregsetp;
fdb28ac4 1003
383f0f5b 1004 if (ppc_floating_point_unit_p (current_gdbarch))
fdb28ac4 1005 {
383f0f5b
JB
1006 for (regi = 0; regi < ppc_num_fprs; regi++)
1007 {
1008 if ((regno == -1) || (regno == tdep->ppc_fp0_regnum + regi))
822c9732
AC
1009 regcache_raw_collect (current_regcache, tdep->ppc_fp0_regnum + regi,
1010 fpp + 8 * regi);
383f0f5b
JB
1011 }
1012 if (regno == -1 || regno == tdep->ppc_fpscr_regnum)
1013 right_fill_reg (tdep->ppc_fpscr_regnum, (fpp + 8 * 32));
fdb28ac4
KB
1014 }
1015}
10d6c8cd
DJ
1016
1017void _initialize_ppc_linux_nat (void);
1018
1019void
1020_initialize_ppc_linux_nat (void)
1021{
1022 struct target_ops *t;
1023
1024 /* Fill in the generic GNU/Linux methods. */
1025 t = linux_target ();
1026
1027 /* Add our register access methods. */
1028 t->to_fetch_registers = ppc_linux_fetch_inferior_registers;
1029 t->to_store_registers = ppc_linux_store_inferior_registers;
1030
e0d24f8d
WZ
1031 /* Add our watchpoint methods. */
1032 t->to_can_use_hw_breakpoint = ppc_linux_check_watch_resources;
1033 t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint;
1034 t->to_insert_watchpoint = ppc_linux_insert_watchpoint;
1035 t->to_remove_watchpoint = ppc_linux_remove_watchpoint;
1036 t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint;
1037 t->to_stopped_data_address = ppc_linux_stopped_data_address;
1038
10d6c8cd
DJ
1039 /* Register the target. */
1040 add_target (t);
1041}
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