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9abe5450 | 1 | /* PPC GNU/Linux native support. |
2555fe1a | 2 | |
e2882c85 | 3 | Copyright (C) 1988-2018 Free Software Foundation, Inc. |
c877c8e6 KB |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c877c8e6 KB |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c877c8e6 KB |
19 | |
20 | #include "defs.h" | |
76727919 | 21 | #include "observable.h" |
c877c8e6 KB |
22 | #include "frame.h" |
23 | #include "inferior.h" | |
6ffbb7ab | 24 | #include "gdbthread.h" |
c877c8e6 | 25 | #include "gdbcore.h" |
4e052eda | 26 | #include "regcache.h" |
1d75a658 | 27 | #include "regset.h" |
10d6c8cd DJ |
28 | #include "target.h" |
29 | #include "linux-nat.h" | |
c877c8e6 | 30 | #include <sys/types.h> |
c877c8e6 KB |
31 | #include <signal.h> |
32 | #include <sys/user.h> | |
33 | #include <sys/ioctl.h> | |
7ca18ed6 | 34 | #include <sys/uio.h> |
2555fe1a | 35 | #include "gdb_wait.h" |
c877c8e6 KB |
36 | #include <fcntl.h> |
37 | #include <sys/procfs.h> | |
5826e159 | 38 | #include "nat/gdb_ptrace.h" |
bcc0c096 | 39 | #include "inf-ptrace.h" |
c877c8e6 | 40 | |
0df8b418 | 41 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f | 42 | #include "gregset.h" |
16333c4f | 43 | #include "ppc-tdep.h" |
7284e1be UW |
44 | #include "ppc-linux-tdep.h" |
45 | ||
b7622095 LM |
46 | /* Required when using the AUXV. */ |
47 | #include "elf/common.h" | |
48 | #include "auxv.h" | |
49 | ||
bd64614e PFC |
50 | #include "arch/ppc-linux-common.h" |
51 | #include "arch/ppc-linux-tdesc.h" | |
514c5338 | 52 | #include "nat/ppc-linux.h" |
01904826 | 53 | |
6ffbb7ab | 54 | /* Similarly for the hardware watchpoint support. These requests are used |
926bf92d | 55 | when the PowerPC HWDEBUG ptrace interface is not available. */ |
e0d24f8d WZ |
56 | #ifndef PTRACE_GET_DEBUGREG |
57 | #define PTRACE_GET_DEBUGREG 25 | |
58 | #endif | |
59 | #ifndef PTRACE_SET_DEBUGREG | |
60 | #define PTRACE_SET_DEBUGREG 26 | |
61 | #endif | |
62 | #ifndef PTRACE_GETSIGINFO | |
63 | #define PTRACE_GETSIGINFO 0x4202 | |
64 | #endif | |
01904826 | 65 | |
926bf92d UW |
66 | /* These requests are used when the PowerPC HWDEBUG ptrace interface is |
67 | available. It exposes the debug facilities of PowerPC processors, as well | |
68 | as additional features of BookE processors, such as ranged breakpoints and | |
69 | watchpoints and hardware-accelerated condition evaluation. */ | |
6ffbb7ab TJB |
70 | #ifndef PPC_PTRACE_GETHWDBGINFO |
71 | ||
926bf92d UW |
72 | /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the PowerPC HWDEBUG |
73 | ptrace interface is not present in ptrace.h, so we'll have to pretty much | |
74 | include it all here so that the code at least compiles on older systems. */ | |
6ffbb7ab TJB |
75 | #define PPC_PTRACE_GETHWDBGINFO 0x89 |
76 | #define PPC_PTRACE_SETHWDEBUG 0x88 | |
77 | #define PPC_PTRACE_DELHWDEBUG 0x87 | |
78 | ||
79 | struct ppc_debug_info | |
80 | { | |
0df8b418 | 81 | uint32_t version; /* Only version 1 exists to date. */ |
6ffbb7ab TJB |
82 | uint32_t num_instruction_bps; |
83 | uint32_t num_data_bps; | |
84 | uint32_t num_condition_regs; | |
85 | uint32_t data_bp_alignment; | |
0df8b418 | 86 | uint32_t sizeof_condition; /* size of the DVC register. */ |
6ffbb7ab TJB |
87 | uint64_t features; |
88 | }; | |
89 | ||
90 | /* Features will have bits indicating whether there is support for: */ | |
91 | #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1 | |
92 | #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2 | |
93 | #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4 | |
94 | #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8 | |
95 | ||
96 | struct ppc_hw_breakpoint | |
97 | { | |
98 | uint32_t version; /* currently, version must be 1 */ | |
99 | uint32_t trigger_type; /* only some combinations allowed */ | |
100 | uint32_t addr_mode; /* address match mode */ | |
101 | uint32_t condition_mode; /* break/watchpoint condition flags */ | |
102 | uint64_t addr; /* break/watchpoint address */ | |
103 | uint64_t addr2; /* range end or mask */ | |
104 | uint64_t condition_value; /* contents of the DVC register */ | |
105 | }; | |
106 | ||
107 | /* Trigger type. */ | |
108 | #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1 | |
109 | #define PPC_BREAKPOINT_TRIGGER_READ 0x2 | |
110 | #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4 | |
111 | #define PPC_BREAKPOINT_TRIGGER_RW 0x6 | |
112 | ||
113 | /* Address mode. */ | |
114 | #define PPC_BREAKPOINT_MODE_EXACT 0x0 | |
115 | #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1 | |
116 | #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2 | |
117 | #define PPC_BREAKPOINT_MODE_MASK 0x3 | |
118 | ||
119 | /* Condition mode. */ | |
120 | #define PPC_BREAKPOINT_CONDITION_NONE 0x0 | |
121 | #define PPC_BREAKPOINT_CONDITION_AND 0x1 | |
122 | #define PPC_BREAKPOINT_CONDITION_EXACT 0x1 | |
123 | #define PPC_BREAKPOINT_CONDITION_OR 0x2 | |
124 | #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3 | |
125 | #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 | |
126 | #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16 | |
127 | #define PPC_BREAKPOINT_CONDITION_BE(n) \ | |
128 | (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT)) | |
129 | #endif /* PPC_PTRACE_GETHWDBGINFO */ | |
130 | ||
e23b9d6e UW |
131 | /* Feature defined on Linux kernel v3.9: DAWR interface, that enables wider |
132 | watchpoint (up to 512 bytes). */ | |
133 | #ifndef PPC_DEBUG_FEATURE_DATA_BP_DAWR | |
134 | #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10 | |
135 | #endif /* PPC_DEBUG_FEATURE_DATA_BP_DAWR */ | |
6ffbb7ab | 136 | |
1dfe79e8 SDJ |
137 | /* Similarly for the general-purpose (gp0 -- gp31) |
138 | and floating-point registers (fp0 -- fp31). */ | |
139 | #ifndef PTRACE_GETREGS | |
140 | #define PTRACE_GETREGS 12 | |
141 | #endif | |
142 | #ifndef PTRACE_SETREGS | |
143 | #define PTRACE_SETREGS 13 | |
144 | #endif | |
145 | #ifndef PTRACE_GETFPREGS | |
146 | #define PTRACE_GETFPREGS 14 | |
147 | #endif | |
148 | #ifndef PTRACE_SETFPREGS | |
149 | #define PTRACE_SETFPREGS 15 | |
150 | #endif | |
151 | ||
9abe5450 EZ |
152 | /* This oddity is because the Linux kernel defines elf_vrregset_t as |
153 | an array of 33 16 bytes long elements. I.e. it leaves out vrsave. | |
154 | However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return | |
155 | the vrsave as an extra 4 bytes at the end. I opted for creating a | |
156 | flat array of chars, so that it is easier to manipulate for gdb. | |
157 | ||
158 | There are 32 vector registers 16 bytes longs, plus a VSCR register | |
159 | which is only 4 bytes long, but is fetched as a 16 bytes | |
0df8b418 | 160 | quantity. Up to here we have the elf_vrregset_t structure. |
9abe5450 EZ |
161 | Appended to this there is space for the VRSAVE register: 4 bytes. |
162 | Even though this vrsave register is not included in the regset | |
163 | typedef, it is handled by the ptrace requests. | |
164 | ||
9abe5450 EZ |
165 | The layout is like this (where x is the actual value of the vscr reg): */ |
166 | ||
167 | /* *INDENT-OFF* */ | |
168 | /* | |
1d75a658 | 169 | Big-Endian: |
9abe5450 EZ |
170 | |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| |
171 | <-------> <-------><-------><-> | |
172 | VR0 VR31 VSCR VRSAVE | |
1d75a658 PFC |
173 | Little-Endian: |
174 | |.|.|.|.|.....|.|.|.|.||X|.|.|.||.| | |
175 | <-------> <-------><-------><-> | |
176 | VR0 VR31 VSCR VRSAVE | |
9abe5450 EZ |
177 | */ |
178 | /* *INDENT-ON* */ | |
179 | ||
d078308a | 180 | typedef char gdb_vrregset_t[PPC_LINUX_SIZEOF_VRREGSET]; |
9abe5450 | 181 | |
604c2f83 LM |
182 | /* This is the layout of the POWER7 VSX registers and the way they overlap |
183 | with the existing FPR and VMX registers. | |
184 | ||
185 | VSR doubleword 0 VSR doubleword 1 | |
186 | ---------------------------------------------------------------- | |
187 | VSR[0] | FPR[0] | | | |
188 | ---------------------------------------------------------------- | |
189 | VSR[1] | FPR[1] | | | |
190 | ---------------------------------------------------------------- | |
191 | | ... | | | |
192 | | ... | | | |
193 | ---------------------------------------------------------------- | |
194 | VSR[30] | FPR[30] | | | |
195 | ---------------------------------------------------------------- | |
196 | VSR[31] | FPR[31] | | | |
197 | ---------------------------------------------------------------- | |
198 | VSR[32] | VR[0] | | |
199 | ---------------------------------------------------------------- | |
200 | VSR[33] | VR[1] | | |
201 | ---------------------------------------------------------------- | |
202 | | ... | | |
203 | | ... | | |
204 | ---------------------------------------------------------------- | |
205 | VSR[62] | VR[30] | | |
206 | ---------------------------------------------------------------- | |
207 | VSR[63] | VR[31] | | |
208 | ---------------------------------------------------------------- | |
209 | ||
210 | VSX has 64 128bit registers. The first 32 registers overlap with | |
211 | the FP registers (doubleword 0) and hence extend them with additional | |
212 | 64 bits (doubleword 1). The other 32 regs overlap with the VMX | |
213 | registers. */ | |
d078308a | 214 | typedef char gdb_vsxregset_t[PPC_LINUX_SIZEOF_VSXREGSET]; |
01904826 | 215 | |
b021a221 | 216 | /* On PPC processors that support the Signal Processing Extension |
01904826 | 217 | (SPE) APU, the general-purpose registers are 64 bits long. |
411cb3f9 PG |
218 | However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER |
219 | ptrace calls only access the lower half of each register, to allow | |
220 | them to behave the same way they do on non-SPE systems. There's a | |
221 | separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that | |
222 | read and write the top halves of all the general-purpose registers | |
223 | at once, along with some SPE-specific registers. | |
01904826 JB |
224 | |
225 | GDB itself continues to claim the general-purpose registers are 32 | |
6ced10dd | 226 | bits long. It has unnamed raw registers that hold the upper halves |
b021a221 | 227 | of the gprs, and the full 64-bit SIMD views of the registers, |
6ced10dd JB |
228 | 'ev0' -- 'ev31', are pseudo-registers that splice the top and |
229 | bottom halves together. | |
01904826 JB |
230 | |
231 | This is the structure filled in by PTRACE_GETEVRREGS and written to | |
232 | the inferior's registers by PTRACE_SETEVRREGS. */ | |
233 | struct gdb_evrregset_t | |
234 | { | |
235 | unsigned long evr[32]; | |
236 | unsigned long long acc; | |
237 | unsigned long spefscr; | |
238 | }; | |
239 | ||
604c2f83 LM |
240 | /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and |
241 | PTRACE_SETVSXREGS requests, for reading and writing the VSX | |
242 | POWER7 registers 0 through 31. Zero if we've tried one of them and | |
243 | gotten an error. Note that VSX registers 32 through 63 overlap | |
244 | with VR registers 0 through 31. */ | |
245 | int have_ptrace_getsetvsxregs = 1; | |
01904826 JB |
246 | |
247 | /* Non-zero if our kernel may support the PTRACE_GETVRREGS and | |
248 | PTRACE_SETVRREGS requests, for reading and writing the Altivec | |
249 | registers. Zero if we've tried one of them and gotten an | |
250 | error. */ | |
9abe5450 EZ |
251 | int have_ptrace_getvrregs = 1; |
252 | ||
01904826 JB |
253 | /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and |
254 | PTRACE_SETEVRREGS requests, for reading and writing the SPE | |
255 | registers. Zero if we've tried one of them and gotten an | |
256 | error. */ | |
257 | int have_ptrace_getsetevrregs = 1; | |
258 | ||
1dfe79e8 SDJ |
259 | /* Non-zero if our kernel may support the PTRACE_GETREGS and |
260 | PTRACE_SETREGS requests, for reading and writing the | |
261 | general-purpose registers. Zero if we've tried one of | |
262 | them and gotten an error. */ | |
263 | int have_ptrace_getsetregs = 1; | |
264 | ||
265 | /* Non-zero if our kernel may support the PTRACE_GETFPREGS and | |
266 | PTRACE_SETFPREGS requests, for reading and writing the | |
267 | floating-pointers registers. Zero if we've tried one of | |
268 | them and gotten an error. */ | |
269 | int have_ptrace_getsetfpregs = 1; | |
270 | ||
f6ac5f3d PA |
271 | struct ppc_linux_nat_target final : public linux_nat_target |
272 | { | |
273 | /* Add our register access methods. */ | |
274 | void fetch_registers (struct regcache *, int) override; | |
275 | void store_registers (struct regcache *, int) override; | |
276 | ||
277 | /* Add our breakpoint/watchpoint methods. */ | |
278 | int can_use_hw_breakpoint (enum bptype, int, int) override; | |
279 | ||
280 | int insert_hw_breakpoint (struct gdbarch *, struct bp_target_info *) | |
281 | override; | |
282 | ||
283 | int remove_hw_breakpoint (struct gdbarch *, struct bp_target_info *) | |
284 | override; | |
285 | ||
286 | int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; | |
287 | ||
288 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
289 | struct expression *) override; | |
290 | ||
291 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
292 | struct expression *) override; | |
293 | ||
294 | int insert_mask_watchpoint (CORE_ADDR, CORE_ADDR, enum target_hw_bp_type) | |
295 | override; | |
296 | ||
297 | int remove_mask_watchpoint (CORE_ADDR, CORE_ADDR, enum target_hw_bp_type) | |
298 | override; | |
299 | ||
57810aa7 | 300 | bool stopped_by_watchpoint () override; |
f6ac5f3d | 301 | |
57810aa7 | 302 | bool stopped_data_address (CORE_ADDR *) override; |
f6ac5f3d | 303 | |
57810aa7 | 304 | bool watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override; |
f6ac5f3d | 305 | |
57810aa7 | 306 | bool can_accel_watchpoint_condition (CORE_ADDR, int, int, struct expression *) |
f6ac5f3d PA |
307 | override; |
308 | ||
309 | int masked_watch_num_registers (CORE_ADDR, CORE_ADDR) override; | |
310 | ||
311 | int ranged_break_num_registers () override; | |
312 | ||
313 | const struct target_desc *read_description () override; | |
314 | ||
315 | int auxv_parse (gdb_byte **readptr, | |
316 | gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp) | |
317 | override; | |
135340af PA |
318 | |
319 | /* Override linux_nat_target low methods. */ | |
320 | void low_new_thread (struct lwp_info *lp) override; | |
f6ac5f3d PA |
321 | }; |
322 | ||
323 | static ppc_linux_nat_target the_ppc_linux_nat_target; | |
324 | ||
16333c4f EZ |
325 | /* *INDENT-OFF* */ |
326 | /* registers layout, as presented by the ptrace interface: | |
327 | PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, | |
328 | PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15, | |
329 | PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23, | |
330 | PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31, | |
0df8b418 MS |
331 | PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, |
332 | PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14, | |
333 | PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, | |
334 | PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30, | |
335 | PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, | |
336 | PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46, | |
337 | PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, | |
338 | PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62, | |
16333c4f EZ |
339 | PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */ |
340 | /* *INDENT_ON * */ | |
c877c8e6 | 341 | |
45229ea4 | 342 | static int |
e101270f | 343 | ppc_register_u_addr (struct gdbarch *gdbarch, int regno) |
c877c8e6 | 344 | { |
16333c4f | 345 | int u_addr = -1; |
e101270f | 346 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
56d0d96a AC |
347 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
348 | interface, and not the wordsize of the program's ABI. */ | |
411cb3f9 | 349 | int wordsize = sizeof (long); |
16333c4f | 350 | |
0df8b418 | 351 | /* General purpose registers occupy 1 slot each in the buffer. */ |
8bf659e8 JB |
352 | if (regno >= tdep->ppc_gp0_regnum |
353 | && regno < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
26e75e5c | 354 | u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize); |
16333c4f | 355 | |
49ff75ad JB |
356 | /* Floating point regs: eight bytes each in both 32- and 64-bit |
357 | ptrace interfaces. Thus, two slots each in 32-bit interface, one | |
358 | slot each in 64-bit interface. */ | |
383f0f5b JB |
359 | if (tdep->ppc_fp0_regnum >= 0 |
360 | && regno >= tdep->ppc_fp0_regnum | |
366f009f JB |
361 | && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) |
362 | u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8); | |
16333c4f | 363 | |
0df8b418 | 364 | /* UISA special purpose registers: 1 slot each. */ |
e101270f | 365 | if (regno == gdbarch_pc_regnum (gdbarch)) |
49ff75ad | 366 | u_addr = PT_NIP * wordsize; |
dc5cfeb6 | 367 | if (regno == tdep->ppc_lr_regnum) |
49ff75ad | 368 | u_addr = PT_LNK * wordsize; |
dc5cfeb6 | 369 | if (regno == tdep->ppc_cr_regnum) |
49ff75ad | 370 | u_addr = PT_CCR * wordsize; |
dc5cfeb6 | 371 | if (regno == tdep->ppc_xer_regnum) |
49ff75ad | 372 | u_addr = PT_XER * wordsize; |
dc5cfeb6 | 373 | if (regno == tdep->ppc_ctr_regnum) |
49ff75ad | 374 | u_addr = PT_CTR * wordsize; |
f8c59253 | 375 | #ifdef PT_MQ |
dc5cfeb6 | 376 | if (regno == tdep->ppc_mq_regnum) |
49ff75ad | 377 | u_addr = PT_MQ * wordsize; |
f8c59253 | 378 | #endif |
dc5cfeb6 | 379 | if (regno == tdep->ppc_ps_regnum) |
49ff75ad | 380 | u_addr = PT_MSR * wordsize; |
7284e1be UW |
381 | if (regno == PPC_ORIG_R3_REGNUM) |
382 | u_addr = PT_ORIG_R3 * wordsize; | |
383 | if (regno == PPC_TRAP_REGNUM) | |
384 | u_addr = PT_TRAP * wordsize; | |
383f0f5b JB |
385 | if (tdep->ppc_fpscr_regnum >= 0 |
386 | && regno == tdep->ppc_fpscr_regnum) | |
8f135812 AC |
387 | { |
388 | /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the | |
389 | kernel headers incorrectly contained the 32-bit definition of | |
390 | PT_FPSCR. For the 32-bit definition, floating-point | |
391 | registers occupy two 32-bit "slots", and the FPSCR lives in | |
69abc51c | 392 | the second half of such a slot-pair (hence +1). For 64-bit, |
8f135812 AC |
393 | the FPSCR instead occupies the full 64-bit 2-word-slot and |
394 | hence no adjustment is necessary. Hack around this. */ | |
395 | if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1)) | |
396 | u_addr = (48 + 32) * wordsize; | |
69abc51c TJB |
397 | /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit |
398 | slot and not just its second word. The PT_FPSCR supplied when | |
399 | GDB is compiled as a 32-bit app doesn't reflect this. */ | |
400 | else if (wordsize == 4 && register_size (gdbarch, regno) == 8 | |
401 | && PT_FPSCR == (48 + 2*32 + 1)) | |
402 | u_addr = (48 + 2*32) * wordsize; | |
8f135812 AC |
403 | else |
404 | u_addr = PT_FPSCR * wordsize; | |
405 | } | |
16333c4f | 406 | return u_addr; |
c877c8e6 KB |
407 | } |
408 | ||
604c2f83 LM |
409 | /* The Linux kernel ptrace interface for POWER7 VSX registers uses the |
410 | registers set mechanism, as opposed to the interface for all the | |
411 | other registers, that stores/fetches each register individually. */ | |
412 | static void | |
2c3305f6 | 413 | fetch_vsx_registers (struct regcache *regcache, int tid, int regno) |
604c2f83 LM |
414 | { |
415 | int ret; | |
416 | gdb_vsxregset_t regs; | |
2c3305f6 | 417 | const struct regset *vsxregset = ppc_linux_vsxregset (); |
604c2f83 LM |
418 | |
419 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
420 | if (ret < 0) | |
421 | { | |
422 | if (errno == EIO) | |
423 | { | |
424 | have_ptrace_getsetvsxregs = 0; | |
425 | return; | |
426 | } | |
2c3305f6 | 427 | perror_with_name (_("Unable to fetch VSX registers")); |
604c2f83 LM |
428 | } |
429 | ||
2c3305f6 PFC |
430 | vsxregset->supply_regset (vsxregset, regcache, regno, ®s, |
431 | PPC_LINUX_SIZEOF_VSXREGSET); | |
604c2f83 LM |
432 | } |
433 | ||
9abe5450 EZ |
434 | /* The Linux kernel ptrace interface for AltiVec registers uses the |
435 | registers set mechanism, as opposed to the interface for all the | |
436 | other registers, that stores/fetches each register individually. */ | |
437 | static void | |
1d75a658 PFC |
438 | fetch_altivec_registers (struct regcache *regcache, int tid, |
439 | int regno) | |
9abe5450 EZ |
440 | { |
441 | int ret; | |
9abe5450 | 442 | gdb_vrregset_t regs; |
ac7936df | 443 | struct gdbarch *gdbarch = regcache->arch (); |
1d75a658 | 444 | const struct regset *vrregset = ppc_linux_vrregset (gdbarch); |
9abe5450 EZ |
445 | |
446 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
447 | if (ret < 0) | |
448 | { | |
449 | if (errno == EIO) | |
450 | { | |
451 | have_ptrace_getvrregs = 0; | |
452 | return; | |
453 | } | |
1d75a658 | 454 | perror_with_name (_("Unable to fetch AltiVec registers")); |
9abe5450 | 455 | } |
1d75a658 PFC |
456 | |
457 | vrregset->supply_regset (vrregset, regcache, regno, ®s, | |
458 | PPC_LINUX_SIZEOF_VRREGSET); | |
9abe5450 EZ |
459 | } |
460 | ||
01904826 JB |
461 | /* Fetch the top 32 bits of TID's general-purpose registers and the |
462 | SPE-specific registers, and place the results in EVRREGSET. If we | |
463 | don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with | |
464 | zeros. | |
465 | ||
466 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
467 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
468 | set_spe_registers. */ | |
469 | static void | |
470 | get_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
471 | { | |
472 | if (have_ptrace_getsetevrregs) | |
473 | { | |
474 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0) | |
475 | return; | |
476 | else | |
477 | { | |
478 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported; | |
479 | we just return zeros. */ | |
480 | if (errno == EIO) | |
481 | have_ptrace_getsetevrregs = 0; | |
482 | else | |
483 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 484 | perror_with_name (_("Unable to fetch SPE registers")); |
01904826 JB |
485 | } |
486 | } | |
487 | ||
488 | memset (evrregset, 0, sizeof (*evrregset)); | |
489 | } | |
490 | ||
6ced10dd JB |
491 | /* Supply values from TID for SPE-specific raw registers: the upper |
492 | halves of the GPRs, the accumulator, and the spefscr. REGNO must | |
493 | be the number of an upper half register, acc, spefscr, or -1 to | |
494 | supply the values of all registers. */ | |
01904826 | 495 | static void |
56be3814 | 496 | fetch_spe_register (struct regcache *regcache, int tid, int regno) |
01904826 | 497 | { |
ac7936df | 498 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 499 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
01904826 JB |
500 | struct gdb_evrregset_t evrregs; |
501 | ||
6ced10dd | 502 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 503 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 504 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 505 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 506 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 507 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
6ced10dd | 508 | |
01904826 JB |
509 | get_spe_registers (tid, &evrregs); |
510 | ||
6ced10dd | 511 | if (regno == -1) |
01904826 | 512 | { |
6ced10dd JB |
513 | int i; |
514 | ||
515 | for (i = 0; i < ppc_num_gprs; i++) | |
73e1c03f | 516 | regcache->raw_supply (tdep->ppc_ev0_upper_regnum + i, &evrregs.evr[i]); |
01904826 | 517 | } |
6ced10dd JB |
518 | else if (tdep->ppc_ev0_upper_regnum <= regno |
519 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
73e1c03f SM |
520 | regcache->raw_supply (regno, |
521 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); | |
6ced10dd JB |
522 | |
523 | if (regno == -1 | |
524 | || regno == tdep->ppc_acc_regnum) | |
73e1c03f | 525 | regcache->raw_supply (tdep->ppc_acc_regnum, &evrregs.acc); |
6ced10dd JB |
526 | |
527 | if (regno == -1 | |
528 | || regno == tdep->ppc_spefscr_regnum) | |
73e1c03f | 529 | regcache->raw_supply (tdep->ppc_spefscr_regnum, &evrregs.spefscr); |
01904826 JB |
530 | } |
531 | ||
7ca18ed6 EBM |
532 | /* Use ptrace to fetch all registers from the register set with note |
533 | type REGSET_ID, size REGSIZE, and layout described by REGSET, from | |
534 | process/thread TID and supply their values to REGCACHE. If ptrace | |
535 | returns ENODATA to indicate the regset is unavailable, mark the | |
536 | registers as unavailable in REGCACHE. */ | |
537 | ||
538 | static void | |
539 | fetch_regset (struct regcache *regcache, int tid, | |
540 | int regset_id, int regsetsize, const struct regset *regset) | |
541 | { | |
542 | void *buf = alloca (regsetsize); | |
543 | struct iovec iov; | |
544 | ||
545 | iov.iov_base = buf; | |
546 | iov.iov_len = regsetsize; | |
547 | ||
548 | if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) < 0) | |
549 | { | |
550 | if (errno == ENODATA) | |
551 | regset->supply_regset (regset, regcache, -1, NULL, regsetsize); | |
552 | else | |
553 | perror_with_name (_("Couldn't get register set")); | |
554 | } | |
555 | else | |
556 | regset->supply_regset (regset, regcache, -1, buf, regsetsize); | |
557 | } | |
558 | ||
559 | /* Use ptrace to store register REGNUM of the regset with note type | |
560 | REGSET_ID, size REGSETSIZE, and layout described by REGSET, from | |
561 | REGCACHE back to process/thread TID. If REGNUM is -1 all registers | |
562 | in the set are collected and stored. */ | |
563 | ||
564 | static void | |
565 | store_regset (const struct regcache *regcache, int tid, int regnum, | |
566 | int regset_id, int regsetsize, const struct regset *regset) | |
567 | { | |
568 | void *buf = alloca (regsetsize); | |
569 | struct iovec iov; | |
570 | ||
571 | iov.iov_base = buf; | |
572 | iov.iov_len = regsetsize; | |
573 | ||
574 | /* Make sure that the buffer that will be stored has up to date values | |
575 | for the registers that won't be collected. */ | |
576 | if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) < 0) | |
577 | perror_with_name (_("Couldn't get register set")); | |
578 | ||
579 | regset->collect_regset (regset, regcache, regnum, buf, regsetsize); | |
580 | ||
581 | if (ptrace (PTRACE_SETREGSET, tid, regset_id, &iov) < 0) | |
582 | perror_with_name (_("Couldn't set register set")); | |
583 | } | |
584 | ||
585 | /* Check whether the kernel provides a register set with number | |
586 | REGSET_ID of size REGSETSIZE for process/thread TID. */ | |
587 | ||
588 | static bool | |
589 | check_regset (int tid, int regset_id, int regsetsize) | |
590 | { | |
591 | void *buf = alloca (regsetsize); | |
592 | struct iovec iov; | |
593 | ||
594 | iov.iov_base = buf; | |
595 | iov.iov_len = regsetsize; | |
596 | ||
597 | if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) >= 0 | |
598 | || errno == ENODATA) | |
599 | return true; | |
600 | else | |
601 | return false; | |
602 | } | |
603 | ||
45229ea4 | 604 | static void |
56be3814 | 605 | fetch_register (struct regcache *regcache, int tid, int regno) |
45229ea4 | 606 | { |
ac7936df | 607 | struct gdbarch *gdbarch = regcache->arch (); |
7ca18ed6 | 608 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
45229ea4 | 609 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 610 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
4a19ea35 | 611 | int bytes_transferred; |
0f068fb5 | 612 | gdb_byte buf[PPC_MAX_REGISTER_SIZE]; |
45229ea4 | 613 | |
be8626e0 | 614 | if (altivec_register_p (gdbarch, regno)) |
9abe5450 EZ |
615 | { |
616 | /* If this is the first time through, or if it is not the first | |
617 | time through, and we have comfirmed that there is kernel | |
618 | support for such a ptrace request, then go and fetch the | |
619 | register. */ | |
620 | if (have_ptrace_getvrregs) | |
621 | { | |
1d75a658 | 622 | fetch_altivec_registers (regcache, tid, regno); |
9abe5450 EZ |
623 | return; |
624 | } | |
625 | /* If we have discovered that there is no ptrace support for | |
626 | AltiVec registers, fall through and return zeroes, because | |
627 | regaddr will be -1 in this case. */ | |
628 | } | |
3d907528 | 629 | else if (vsx_register_p (gdbarch, regno)) |
604c2f83 LM |
630 | { |
631 | if (have_ptrace_getsetvsxregs) | |
632 | { | |
2c3305f6 | 633 | fetch_vsx_registers (regcache, tid, regno); |
604c2f83 LM |
634 | return; |
635 | } | |
636 | } | |
be8626e0 | 637 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 638 | { |
56be3814 | 639 | fetch_spe_register (regcache, tid, regno); |
01904826 JB |
640 | return; |
641 | } | |
7ca18ed6 EBM |
642 | else if (regno == PPC_DSCR_REGNUM) |
643 | { | |
644 | gdb_assert (tdep->ppc_dscr_regnum != -1); | |
645 | ||
646 | fetch_regset (regcache, tid, NT_PPC_DSCR, | |
647 | PPC_LINUX_SIZEOF_DSCRREGSET, | |
648 | &ppc32_linux_dscrregset); | |
649 | return; | |
650 | } | |
651 | else if (regno == PPC_PPR_REGNUM) | |
652 | { | |
653 | gdb_assert (tdep->ppc_ppr_regnum != -1); | |
654 | ||
655 | fetch_regset (regcache, tid, NT_PPC_PPR, | |
656 | PPC_LINUX_SIZEOF_PPRREGSET, | |
657 | &ppc32_linux_pprregset); | |
658 | return; | |
659 | } | |
f2cf6173 EBM |
660 | else if (regno == PPC_TAR_REGNUM) |
661 | { | |
662 | gdb_assert (tdep->ppc_tar_regnum != -1); | |
663 | ||
664 | fetch_regset (regcache, tid, NT_PPC_TAR, | |
665 | PPC_LINUX_SIZEOF_TARREGSET, | |
666 | &ppc32_linux_tarregset); | |
667 | return; | |
668 | } | |
232bfb86 EBM |
669 | else if (PPC_IS_EBB_REGNUM (regno)) |
670 | { | |
671 | gdb_assert (tdep->have_ebb); | |
672 | ||
673 | fetch_regset (regcache, tid, NT_PPC_EBB, | |
674 | PPC_LINUX_SIZEOF_EBBREGSET, | |
675 | &ppc32_linux_ebbregset); | |
676 | return; | |
677 | } | |
678 | else if (PPC_IS_PMU_REGNUM (regno)) | |
679 | { | |
680 | gdb_assert (tdep->ppc_mmcr0_regnum != -1); | |
681 | ||
682 | fetch_regset (regcache, tid, NT_PPC_PMU, | |
683 | PPC_LINUX_SIZEOF_PMUREGSET, | |
684 | &ppc32_linux_pmuregset); | |
685 | return; | |
686 | } | |
9abe5450 | 687 | |
45229ea4 EZ |
688 | if (regaddr == -1) |
689 | { | |
40a6adc1 | 690 | memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ |
73e1c03f | 691 | regcache->raw_supply (regno, buf); |
45229ea4 EZ |
692 | return; |
693 | } | |
694 | ||
411cb3f9 | 695 | /* Read the raw register using sizeof(long) sized chunks. On a |
56d0d96a AC |
696 | 32-bit platform, 64-bit floating-point registers will require two |
697 | transfers. */ | |
4a19ea35 | 698 | for (bytes_transferred = 0; |
40a6adc1 | 699 | bytes_transferred < register_size (gdbarch, regno); |
411cb3f9 | 700 | bytes_transferred += sizeof (long)) |
45229ea4 | 701 | { |
11fde611 JK |
702 | long l; |
703 | ||
45229ea4 | 704 | errno = 0; |
11fde611 | 705 | l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); |
411cb3f9 | 706 | regaddr += sizeof (long); |
45229ea4 EZ |
707 | if (errno != 0) |
708 | { | |
bc97b3ba | 709 | char message[128]; |
8c042590 PM |
710 | xsnprintf (message, sizeof (message), "reading register %s (#%d)", |
711 | gdbarch_register_name (gdbarch, regno), regno); | |
bc97b3ba | 712 | perror_with_name (message); |
45229ea4 | 713 | } |
11fde611 | 714 | memcpy (&buf[bytes_transferred], &l, sizeof (l)); |
45229ea4 | 715 | } |
56d0d96a | 716 | |
4a19ea35 JB |
717 | /* Now supply the register. Keep in mind that the regcache's idea |
718 | of the register's size may not be a multiple of sizeof | |
411cb3f9 | 719 | (long). */ |
40a6adc1 | 720 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
4a19ea35 JB |
721 | { |
722 | /* Little-endian values are always found at the left end of the | |
723 | bytes transferred. */ | |
73e1c03f | 724 | regcache->raw_supply (regno, buf); |
4a19ea35 | 725 | } |
40a6adc1 | 726 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
727 | { |
728 | /* Big-endian values are found at the right end of the bytes | |
729 | transferred. */ | |
40a6adc1 | 730 | size_t padding = (bytes_transferred - register_size (gdbarch, regno)); |
73e1c03f | 731 | regcache->raw_supply (regno, buf + padding); |
4a19ea35 JB |
732 | } |
733 | else | |
a44bddec | 734 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 735 | _("fetch_register: unexpected byte order: %d"), |
40a6adc1 | 736 | gdbarch_byte_order (gdbarch)); |
45229ea4 EZ |
737 | } |
738 | ||
1dfe79e8 SDJ |
739 | /* This function actually issues the request to ptrace, telling |
740 | it to get all general-purpose registers and put them into the | |
741 | specified regset. | |
742 | ||
743 | If the ptrace request does not exist, this function returns 0 | |
744 | and properly sets the have_ptrace_* flag. If the request fails, | |
745 | this function calls perror_with_name. Otherwise, if the request | |
746 | succeeds, then the regcache gets filled and 1 is returned. */ | |
747 | static int | |
748 | fetch_all_gp_regs (struct regcache *regcache, int tid) | |
749 | { | |
1dfe79e8 SDJ |
750 | gdb_gregset_t gregset; |
751 | ||
752 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
753 | { | |
754 | if (errno == EIO) | |
755 | { | |
756 | have_ptrace_getsetregs = 0; | |
757 | return 0; | |
758 | } | |
759 | perror_with_name (_("Couldn't get general-purpose registers.")); | |
760 | } | |
761 | ||
762 | supply_gregset (regcache, (const gdb_gregset_t *) &gregset); | |
763 | ||
764 | return 1; | |
765 | } | |
766 | ||
767 | /* This is a wrapper for the fetch_all_gp_regs function. It is | |
768 | responsible for verifying if this target has the ptrace request | |
769 | that can be used to fetch all general-purpose registers at one | |
770 | shot. If it doesn't, then we should fetch them using the | |
771 | old-fashioned way, which is to iterate over the registers and | |
772 | request them one by one. */ | |
773 | static void | |
774 | fetch_gp_regs (struct regcache *regcache, int tid) | |
775 | { | |
ac7936df | 776 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
777 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
778 | int i; | |
779 | ||
780 | if (have_ptrace_getsetregs) | |
781 | if (fetch_all_gp_regs (regcache, tid)) | |
782 | return; | |
783 | ||
784 | /* If we've hit this point, it doesn't really matter which | |
785 | architecture we are using. We just need to read the | |
786 | registers in the "old-fashioned way". */ | |
787 | for (i = 0; i < ppc_num_gprs; i++) | |
788 | fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i); | |
789 | } | |
790 | ||
791 | /* This function actually issues the request to ptrace, telling | |
792 | it to get all floating-point registers and put them into the | |
793 | specified regset. | |
794 | ||
795 | If the ptrace request does not exist, this function returns 0 | |
796 | and properly sets the have_ptrace_* flag. If the request fails, | |
797 | this function calls perror_with_name. Otherwise, if the request | |
798 | succeeds, then the regcache gets filled and 1 is returned. */ | |
799 | static int | |
800 | fetch_all_fp_regs (struct regcache *regcache, int tid) | |
801 | { | |
802 | gdb_fpregset_t fpregs; | |
803 | ||
804 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
805 | { | |
806 | if (errno == EIO) | |
807 | { | |
808 | have_ptrace_getsetfpregs = 0; | |
809 | return 0; | |
810 | } | |
811 | perror_with_name (_("Couldn't get floating-point registers.")); | |
812 | } | |
813 | ||
814 | supply_fpregset (regcache, (const gdb_fpregset_t *) &fpregs); | |
815 | ||
816 | return 1; | |
817 | } | |
818 | ||
819 | /* This is a wrapper for the fetch_all_fp_regs function. It is | |
820 | responsible for verifying if this target has the ptrace request | |
821 | that can be used to fetch all floating-point registers at one | |
822 | shot. If it doesn't, then we should fetch them using the | |
823 | old-fashioned way, which is to iterate over the registers and | |
824 | request them one by one. */ | |
825 | static void | |
826 | fetch_fp_regs (struct regcache *regcache, int tid) | |
827 | { | |
ac7936df | 828 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
829 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
830 | int i; | |
831 | ||
832 | if (have_ptrace_getsetfpregs) | |
833 | if (fetch_all_fp_regs (regcache, tid)) | |
834 | return; | |
835 | ||
836 | /* If we've hit this point, it doesn't really matter which | |
837 | architecture we are using. We just need to read the | |
838 | registers in the "old-fashioned way". */ | |
839 | for (i = 0; i < ppc_num_fprs; i++) | |
840 | fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
841 | } | |
842 | ||
45229ea4 | 843 | static void |
56be3814 | 844 | fetch_ppc_registers (struct regcache *regcache, int tid) |
45229ea4 | 845 | { |
ac7936df | 846 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 847 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9abe5450 | 848 | |
1dfe79e8 | 849 | fetch_gp_regs (regcache, tid); |
32b99774 | 850 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 851 | fetch_fp_regs (regcache, tid); |
40a6adc1 | 852 | fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 853 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 854 | fetch_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 855 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 856 | fetch_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 857 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 858 | fetch_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 859 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 860 | fetch_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 861 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 862 | fetch_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 863 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 864 | fetch_register (regcache, tid, tdep->ppc_mq_regnum); |
7284e1be UW |
865 | if (ppc_linux_trap_reg_p (gdbarch)) |
866 | { | |
867 | fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
868 | fetch_register (regcache, tid, PPC_TRAP_REGNUM); | |
869 | } | |
32b99774 | 870 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 871 | fetch_register (regcache, tid, tdep->ppc_fpscr_regnum); |
9abe5450 EZ |
872 | if (have_ptrace_getvrregs) |
873 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
1d75a658 | 874 | fetch_altivec_registers (regcache, tid, -1); |
604c2f83 LM |
875 | if (have_ptrace_getsetvsxregs) |
876 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
2c3305f6 | 877 | fetch_vsx_registers (regcache, tid, -1); |
6ced10dd | 878 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 879 | fetch_spe_register (regcache, tid, -1); |
7ca18ed6 EBM |
880 | if (tdep->ppc_ppr_regnum != -1) |
881 | fetch_regset (regcache, tid, NT_PPC_PPR, | |
882 | PPC_LINUX_SIZEOF_PPRREGSET, | |
883 | &ppc32_linux_pprregset); | |
884 | if (tdep->ppc_dscr_regnum != -1) | |
885 | fetch_regset (regcache, tid, NT_PPC_DSCR, | |
886 | PPC_LINUX_SIZEOF_DSCRREGSET, | |
887 | &ppc32_linux_dscrregset); | |
f2cf6173 EBM |
888 | if (tdep->ppc_tar_regnum != -1) |
889 | fetch_regset (regcache, tid, NT_PPC_TAR, | |
890 | PPC_LINUX_SIZEOF_TARREGSET, | |
891 | &ppc32_linux_tarregset); | |
232bfb86 EBM |
892 | if (tdep->have_ebb) |
893 | fetch_regset (regcache, tid, NT_PPC_EBB, | |
894 | PPC_LINUX_SIZEOF_EBBREGSET, | |
895 | &ppc32_linux_ebbregset); | |
896 | if (tdep->ppc_mmcr0_regnum != -1) | |
897 | fetch_regset (regcache, tid, NT_PPC_PMU, | |
898 | PPC_LINUX_SIZEOF_PMUREGSET, | |
899 | &ppc32_linux_pmuregset); | |
45229ea4 EZ |
900 | } |
901 | ||
902 | /* Fetch registers from the child process. Fetch all registers if | |
903 | regno == -1, otherwise fetch all general registers or all floating | |
904 | point registers depending upon the value of regno. */ | |
f6ac5f3d PA |
905 | void |
906 | ppc_linux_nat_target::fetch_registers (struct regcache *regcache, int regno) | |
45229ea4 | 907 | { |
222312d3 | 908 | pid_t tid = get_ptrace_pid (regcache->ptid ()); |
05f13b9c | 909 | |
9abe5450 | 910 | if (regno == -1) |
56be3814 | 911 | fetch_ppc_registers (regcache, tid); |
45229ea4 | 912 | else |
56be3814 | 913 | fetch_register (regcache, tid, regno); |
45229ea4 EZ |
914 | } |
915 | ||
604c2f83 | 916 | static void |
2c3305f6 | 917 | store_vsx_registers (const struct regcache *regcache, int tid, int regno) |
604c2f83 LM |
918 | { |
919 | int ret; | |
920 | gdb_vsxregset_t regs; | |
2c3305f6 | 921 | const struct regset *vsxregset = ppc_linux_vsxregset (); |
604c2f83 | 922 | |
9fe70b4f | 923 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); |
604c2f83 LM |
924 | if (ret < 0) |
925 | { | |
926 | if (errno == EIO) | |
927 | { | |
928 | have_ptrace_getsetvsxregs = 0; | |
929 | return; | |
930 | } | |
2c3305f6 | 931 | perror_with_name (_("Unable to fetch VSX registers")); |
604c2f83 LM |
932 | } |
933 | ||
2c3305f6 PFC |
934 | vsxregset->collect_regset (vsxregset, regcache, regno, ®s, |
935 | PPC_LINUX_SIZEOF_VSXREGSET); | |
604c2f83 LM |
936 | |
937 | ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); | |
938 | if (ret < 0) | |
2c3305f6 | 939 | perror_with_name (_("Unable to store VSX registers")); |
604c2f83 LM |
940 | } |
941 | ||
9abe5450 | 942 | static void |
1d75a658 PFC |
943 | store_altivec_registers (const struct regcache *regcache, int tid, |
944 | int regno) | |
9abe5450 EZ |
945 | { |
946 | int ret; | |
9abe5450 | 947 | gdb_vrregset_t regs; |
ac7936df | 948 | struct gdbarch *gdbarch = regcache->arch (); |
1d75a658 | 949 | const struct regset *vrregset = ppc_linux_vrregset (gdbarch); |
9abe5450 EZ |
950 | |
951 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
952 | if (ret < 0) | |
953 | { | |
954 | if (errno == EIO) | |
955 | { | |
956 | have_ptrace_getvrregs = 0; | |
957 | return; | |
958 | } | |
1d75a658 | 959 | perror_with_name (_("Unable to fetch AltiVec registers")); |
9abe5450 EZ |
960 | } |
961 | ||
1d75a658 PFC |
962 | vrregset->collect_regset (vrregset, regcache, regno, ®s, |
963 | PPC_LINUX_SIZEOF_VRREGSET); | |
9abe5450 EZ |
964 | |
965 | ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); | |
966 | if (ret < 0) | |
1d75a658 | 967 | perror_with_name (_("Unable to store AltiVec registers")); |
9abe5450 EZ |
968 | } |
969 | ||
01904826 JB |
970 | /* Assuming TID referrs to an SPE process, set the top halves of TID's |
971 | general-purpose registers and its SPE-specific registers to the | |
972 | values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do | |
973 | nothing. | |
974 | ||
975 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
976 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
977 | get_spe_registers. */ | |
978 | static void | |
979 | set_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
980 | { | |
981 | if (have_ptrace_getsetevrregs) | |
982 | { | |
983 | if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0) | |
984 | return; | |
985 | else | |
986 | { | |
987 | /* EIO means that the PTRACE_SETEVRREGS request isn't | |
988 | supported; we fail silently, and don't try the call | |
989 | again. */ | |
990 | if (errno == EIO) | |
991 | have_ptrace_getsetevrregs = 0; | |
992 | else | |
993 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 994 | perror_with_name (_("Unable to set SPE registers")); |
01904826 JB |
995 | } |
996 | } | |
997 | } | |
998 | ||
6ced10dd JB |
999 | /* Write GDB's value for the SPE-specific raw register REGNO to TID. |
1000 | If REGNO is -1, write the values of all the SPE-specific | |
1001 | registers. */ | |
01904826 | 1002 | static void |
56be3814 | 1003 | store_spe_register (const struct regcache *regcache, int tid, int regno) |
01904826 | 1004 | { |
ac7936df | 1005 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 1006 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
01904826 JB |
1007 | struct gdb_evrregset_t evrregs; |
1008 | ||
6ced10dd | 1009 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 1010 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 1011 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 1012 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 1013 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 1014 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
01904826 | 1015 | |
6ced10dd JB |
1016 | if (regno == -1) |
1017 | /* Since we're going to write out every register, the code below | |
1018 | should store to every field of evrregs; if that doesn't happen, | |
1019 | make it obvious by initializing it with suspicious values. */ | |
1020 | memset (&evrregs, 42, sizeof (evrregs)); | |
1021 | else | |
1022 | /* We can only read and write the entire EVR register set at a | |
1023 | time, so to write just a single register, we do a | |
1024 | read-modify-write maneuver. */ | |
1025 | get_spe_registers (tid, &evrregs); | |
1026 | ||
1027 | if (regno == -1) | |
01904826 | 1028 | { |
6ced10dd JB |
1029 | int i; |
1030 | ||
1031 | for (i = 0; i < ppc_num_gprs; i++) | |
34a79281 SM |
1032 | regcache->raw_collect (tdep->ppc_ev0_upper_regnum + i, |
1033 | &evrregs.evr[i]); | |
01904826 | 1034 | } |
6ced10dd JB |
1035 | else if (tdep->ppc_ev0_upper_regnum <= regno |
1036 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
34a79281 SM |
1037 | regcache->raw_collect (regno, |
1038 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); | |
6ced10dd JB |
1039 | |
1040 | if (regno == -1 | |
1041 | || regno == tdep->ppc_acc_regnum) | |
34a79281 SM |
1042 | regcache->raw_collect (tdep->ppc_acc_regnum, |
1043 | &evrregs.acc); | |
6ced10dd JB |
1044 | |
1045 | if (regno == -1 | |
1046 | || regno == tdep->ppc_spefscr_regnum) | |
34a79281 SM |
1047 | regcache->raw_collect (tdep->ppc_spefscr_regnum, |
1048 | &evrregs.spefscr); | |
01904826 JB |
1049 | |
1050 | /* Write back the modified register set. */ | |
1051 | set_spe_registers (tid, &evrregs); | |
1052 | } | |
1053 | ||
45229ea4 | 1054 | static void |
56be3814 | 1055 | store_register (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 1056 | { |
ac7936df | 1057 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 1058 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
45229ea4 | 1059 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 1060 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
52f0bd74 | 1061 | int i; |
4a19ea35 | 1062 | size_t bytes_to_transfer; |
0f068fb5 | 1063 | gdb_byte buf[PPC_MAX_REGISTER_SIZE]; |
45229ea4 | 1064 | |
be8626e0 | 1065 | if (altivec_register_p (gdbarch, regno)) |
45229ea4 | 1066 | { |
1d75a658 | 1067 | store_altivec_registers (regcache, tid, regno); |
45229ea4 EZ |
1068 | return; |
1069 | } | |
3d907528 | 1070 | else if (vsx_register_p (gdbarch, regno)) |
604c2f83 | 1071 | { |
2c3305f6 | 1072 | store_vsx_registers (regcache, tid, regno); |
604c2f83 LM |
1073 | return; |
1074 | } | |
be8626e0 | 1075 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 1076 | { |
56be3814 | 1077 | store_spe_register (regcache, tid, regno); |
01904826 JB |
1078 | return; |
1079 | } | |
7ca18ed6 EBM |
1080 | else if (regno == PPC_DSCR_REGNUM) |
1081 | { | |
1082 | gdb_assert (tdep->ppc_dscr_regnum != -1); | |
1083 | ||
1084 | store_regset (regcache, tid, regno, NT_PPC_DSCR, | |
1085 | PPC_LINUX_SIZEOF_DSCRREGSET, | |
1086 | &ppc32_linux_dscrregset); | |
1087 | return; | |
1088 | } | |
1089 | else if (regno == PPC_PPR_REGNUM) | |
1090 | { | |
1091 | gdb_assert (tdep->ppc_ppr_regnum != -1); | |
1092 | ||
1093 | store_regset (regcache, tid, regno, NT_PPC_PPR, | |
1094 | PPC_LINUX_SIZEOF_PPRREGSET, | |
1095 | &ppc32_linux_pprregset); | |
1096 | return; | |
1097 | } | |
f2cf6173 EBM |
1098 | else if (regno == PPC_TAR_REGNUM) |
1099 | { | |
1100 | gdb_assert (tdep->ppc_tar_regnum != -1); | |
1101 | ||
1102 | store_regset (regcache, tid, regno, NT_PPC_TAR, | |
1103 | PPC_LINUX_SIZEOF_TARREGSET, | |
1104 | &ppc32_linux_tarregset); | |
1105 | return; | |
1106 | } | |
232bfb86 EBM |
1107 | else if (PPC_IS_EBB_REGNUM (regno)) |
1108 | { | |
1109 | gdb_assert (tdep->have_ebb); | |
1110 | ||
1111 | store_regset (regcache, tid, regno, NT_PPC_EBB, | |
1112 | PPC_LINUX_SIZEOF_EBBREGSET, | |
1113 | &ppc32_linux_ebbregset); | |
1114 | return; | |
1115 | } | |
1116 | else if (PPC_IS_PMU_REGNUM (regno)) | |
1117 | { | |
1118 | gdb_assert (tdep->ppc_mmcr0_regnum != -1); | |
1119 | ||
1120 | store_regset (regcache, tid, regno, NT_PPC_PMU, | |
1121 | PPC_LINUX_SIZEOF_PMUREGSET, | |
1122 | &ppc32_linux_pmuregset); | |
1123 | return; | |
1124 | } | |
45229ea4 | 1125 | |
9abe5450 EZ |
1126 | if (regaddr == -1) |
1127 | return; | |
1128 | ||
4a19ea35 JB |
1129 | /* First collect the register. Keep in mind that the regcache's |
1130 | idea of the register's size may not be a multiple of sizeof | |
411cb3f9 | 1131 | (long). */ |
56d0d96a | 1132 | memset (buf, 0, sizeof buf); |
40a6adc1 MD |
1133 | bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); |
1134 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) | |
4a19ea35 JB |
1135 | { |
1136 | /* Little-endian values always sit at the left end of the buffer. */ | |
34a79281 | 1137 | regcache->raw_collect (regno, buf); |
4a19ea35 | 1138 | } |
40a6adc1 | 1139 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
1140 | { |
1141 | /* Big-endian values sit at the right end of the buffer. */ | |
40a6adc1 | 1142 | size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); |
34a79281 | 1143 | regcache->raw_collect (regno, buf + padding); |
4a19ea35 JB |
1144 | } |
1145 | ||
411cb3f9 | 1146 | for (i = 0; i < bytes_to_transfer; i += sizeof (long)) |
45229ea4 | 1147 | { |
11fde611 JK |
1148 | long l; |
1149 | ||
1150 | memcpy (&l, &buf[i], sizeof (l)); | |
45229ea4 | 1151 | errno = 0; |
11fde611 | 1152 | ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l); |
411cb3f9 | 1153 | regaddr += sizeof (long); |
e3f36dbd KB |
1154 | |
1155 | if (errno == EIO | |
7284e1be UW |
1156 | && (regno == tdep->ppc_fpscr_regnum |
1157 | || regno == PPC_ORIG_R3_REGNUM | |
1158 | || regno == PPC_TRAP_REGNUM)) | |
e3f36dbd | 1159 | { |
7284e1be UW |
1160 | /* Some older kernel versions don't allow fpscr, orig_r3 |
1161 | or trap to be written. */ | |
e3f36dbd KB |
1162 | continue; |
1163 | } | |
1164 | ||
45229ea4 EZ |
1165 | if (errno != 0) |
1166 | { | |
bc97b3ba | 1167 | char message[128]; |
8c042590 PM |
1168 | xsnprintf (message, sizeof (message), "writing register %s (#%d)", |
1169 | gdbarch_register_name (gdbarch, regno), regno); | |
bc97b3ba | 1170 | perror_with_name (message); |
45229ea4 EZ |
1171 | } |
1172 | } | |
1173 | } | |
1174 | ||
1dfe79e8 SDJ |
1175 | /* This function actually issues the request to ptrace, telling |
1176 | it to store all general-purpose registers present in the specified | |
1177 | regset. | |
1178 | ||
1179 | If the ptrace request does not exist, this function returns 0 | |
1180 | and properly sets the have_ptrace_* flag. If the request fails, | |
1181 | this function calls perror_with_name. Otherwise, if the request | |
1182 | succeeds, then the regcache is stored and 1 is returned. */ | |
1183 | static int | |
1184 | store_all_gp_regs (const struct regcache *regcache, int tid, int regno) | |
1185 | { | |
1dfe79e8 SDJ |
1186 | gdb_gregset_t gregset; |
1187 | ||
1188 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
1189 | { | |
1190 | if (errno == EIO) | |
1191 | { | |
1192 | have_ptrace_getsetregs = 0; | |
1193 | return 0; | |
1194 | } | |
1195 | perror_with_name (_("Couldn't get general-purpose registers.")); | |
1196 | } | |
1197 | ||
1198 | fill_gregset (regcache, &gregset, regno); | |
1199 | ||
1200 | if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0) | |
1201 | { | |
1202 | if (errno == EIO) | |
1203 | { | |
1204 | have_ptrace_getsetregs = 0; | |
1205 | return 0; | |
1206 | } | |
1207 | perror_with_name (_("Couldn't set general-purpose registers.")); | |
1208 | } | |
1209 | ||
1210 | return 1; | |
1211 | } | |
1212 | ||
1213 | /* This is a wrapper for the store_all_gp_regs function. It is | |
1214 | responsible for verifying if this target has the ptrace request | |
1215 | that can be used to store all general-purpose registers at one | |
1216 | shot. If it doesn't, then we should store them using the | |
1217 | old-fashioned way, which is to iterate over the registers and | |
1218 | store them one by one. */ | |
45229ea4 | 1219 | static void |
1dfe79e8 | 1220 | store_gp_regs (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 1221 | { |
ac7936df | 1222 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 1223 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1dfe79e8 SDJ |
1224 | int i; |
1225 | ||
1226 | if (have_ptrace_getsetregs) | |
1227 | if (store_all_gp_regs (regcache, tid, regno)) | |
1228 | return; | |
1229 | ||
1230 | /* If we hit this point, it doesn't really matter which | |
1231 | architecture we are using. We just need to store the | |
1232 | registers in the "old-fashioned way". */ | |
6ced10dd | 1233 | for (i = 0; i < ppc_num_gprs; i++) |
56be3814 | 1234 | store_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
1dfe79e8 SDJ |
1235 | } |
1236 | ||
1237 | /* This function actually issues the request to ptrace, telling | |
1238 | it to store all floating-point registers present in the specified | |
1239 | regset. | |
1240 | ||
1241 | If the ptrace request does not exist, this function returns 0 | |
1242 | and properly sets the have_ptrace_* flag. If the request fails, | |
1243 | this function calls perror_with_name. Otherwise, if the request | |
1244 | succeeds, then the regcache is stored and 1 is returned. */ | |
1245 | static int | |
1246 | store_all_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1247 | { | |
1248 | gdb_fpregset_t fpregs; | |
1249 | ||
1250 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1251 | { | |
1252 | if (errno == EIO) | |
1253 | { | |
1254 | have_ptrace_getsetfpregs = 0; | |
1255 | return 0; | |
1256 | } | |
1257 | perror_with_name (_("Couldn't get floating-point registers.")); | |
1258 | } | |
1259 | ||
1260 | fill_fpregset (regcache, &fpregs, regno); | |
1261 | ||
1262 | if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1263 | { | |
1264 | if (errno == EIO) | |
1265 | { | |
1266 | have_ptrace_getsetfpregs = 0; | |
1267 | return 0; | |
1268 | } | |
1269 | perror_with_name (_("Couldn't set floating-point registers.")); | |
1270 | } | |
1271 | ||
1272 | return 1; | |
1273 | } | |
1274 | ||
1275 | /* This is a wrapper for the store_all_fp_regs function. It is | |
1276 | responsible for verifying if this target has the ptrace request | |
1277 | that can be used to store all floating-point registers at one | |
1278 | shot. If it doesn't, then we should store them using the | |
1279 | old-fashioned way, which is to iterate over the registers and | |
1280 | store them one by one. */ | |
1281 | static void | |
1282 | store_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1283 | { | |
ac7936df | 1284 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
1285 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1286 | int i; | |
1287 | ||
1288 | if (have_ptrace_getsetfpregs) | |
1289 | if (store_all_fp_regs (regcache, tid, regno)) | |
1290 | return; | |
1291 | ||
1292 | /* If we hit this point, it doesn't really matter which | |
1293 | architecture we are using. We just need to store the | |
1294 | registers in the "old-fashioned way". */ | |
1295 | for (i = 0; i < ppc_num_fprs; i++) | |
1296 | store_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
1297 | } | |
1298 | ||
1299 | static void | |
1300 | store_ppc_registers (const struct regcache *regcache, int tid) | |
1301 | { | |
ac7936df | 1302 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
1303 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1304 | ||
1305 | store_gp_regs (regcache, tid, -1); | |
32b99774 | 1306 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 1307 | store_fp_regs (regcache, tid, -1); |
40a6adc1 | 1308 | store_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 1309 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 1310 | store_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 1311 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 1312 | store_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 1313 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 1314 | store_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 1315 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 1316 | store_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 1317 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 1318 | store_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 1319 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 1320 | store_register (regcache, tid, tdep->ppc_mq_regnum); |
32b99774 | 1321 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 1322 | store_register (regcache, tid, tdep->ppc_fpscr_regnum); |
7284e1be UW |
1323 | if (ppc_linux_trap_reg_p (gdbarch)) |
1324 | { | |
1325 | store_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
1326 | store_register (regcache, tid, PPC_TRAP_REGNUM); | |
1327 | } | |
9abe5450 EZ |
1328 | if (have_ptrace_getvrregs) |
1329 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
1d75a658 | 1330 | store_altivec_registers (regcache, tid, -1); |
604c2f83 LM |
1331 | if (have_ptrace_getsetvsxregs) |
1332 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
2c3305f6 | 1333 | store_vsx_registers (regcache, tid, -1); |
6ced10dd | 1334 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 1335 | store_spe_register (regcache, tid, -1); |
7ca18ed6 EBM |
1336 | if (tdep->ppc_ppr_regnum != -1) |
1337 | store_regset (regcache, tid, -1, NT_PPC_PPR, | |
1338 | PPC_LINUX_SIZEOF_PPRREGSET, | |
1339 | &ppc32_linux_pprregset); | |
1340 | if (tdep->ppc_dscr_regnum != -1) | |
1341 | store_regset (regcache, tid, -1, NT_PPC_DSCR, | |
1342 | PPC_LINUX_SIZEOF_DSCRREGSET, | |
1343 | &ppc32_linux_dscrregset); | |
f2cf6173 EBM |
1344 | if (tdep->ppc_tar_regnum != -1) |
1345 | store_regset (regcache, tid, -1, NT_PPC_TAR, | |
1346 | PPC_LINUX_SIZEOF_TARREGSET, | |
1347 | &ppc32_linux_tarregset); | |
232bfb86 EBM |
1348 | |
1349 | if (tdep->ppc_mmcr0_regnum != -1) | |
1350 | store_regset (regcache, tid, -1, NT_PPC_PMU, | |
1351 | PPC_LINUX_SIZEOF_PMUREGSET, | |
1352 | &ppc32_linux_pmuregset); | |
1353 | ||
1354 | /* Because the EBB registers can be unavailable, attempts to store | |
1355 | them here would cause this function to fail most of the time, so | |
1356 | we ignore them. */ | |
45229ea4 EZ |
1357 | } |
1358 | ||
6ffbb7ab | 1359 | /* Fetch the AT_HWCAP entry from the aux vector. */ |
0ec848ad | 1360 | static CORE_ADDR |
b261e0c5 | 1361 | ppc_linux_get_hwcap (void) |
6ffbb7ab TJB |
1362 | { |
1363 | CORE_ADDR field; | |
1364 | ||
8b88a78e | 1365 | if (target_auxv_search (current_top_target (), AT_HWCAP, &field) != 1) |
0ec848ad | 1366 | return 0; |
6ffbb7ab | 1367 | |
0ec848ad | 1368 | return field; |
6ffbb7ab TJB |
1369 | } |
1370 | ||
7ca18ed6 EBM |
1371 | /* Fetch the AT_HWCAP2 entry from the aux vector. */ |
1372 | ||
1373 | static CORE_ADDR | |
1374 | ppc_linux_get_hwcap2 (void) | |
1375 | { | |
1376 | CORE_ADDR field; | |
1377 | ||
1378 | if (target_auxv_search (current_top_target (), AT_HWCAP2, &field) != 1) | |
1379 | return 0; | |
1380 | ||
1381 | return field; | |
1382 | } | |
1383 | ||
6ffbb7ab | 1384 | /* The cached DABR value, to install in new threads. |
926bf92d UW |
1385 | This variable is used when the PowerPC HWDEBUG ptrace |
1386 | interface is not available. */ | |
6ffbb7ab TJB |
1387 | static long saved_dabr_value; |
1388 | ||
1389 | /* Global structure that will store information about the available | |
926bf92d UW |
1390 | features provided by the PowerPC HWDEBUG ptrace interface. */ |
1391 | static struct ppc_debug_info hwdebug_info; | |
6ffbb7ab TJB |
1392 | |
1393 | /* Global variable that holds the maximum number of slots that the | |
926bf92d UW |
1394 | kernel will use. This is only used when PowerPC HWDEBUG ptrace interface |
1395 | is available. */ | |
6ffbb7ab TJB |
1396 | static size_t max_slots_number = 0; |
1397 | ||
1398 | struct hw_break_tuple | |
1399 | { | |
1400 | long slot; | |
1401 | struct ppc_hw_breakpoint *hw_break; | |
1402 | }; | |
1403 | ||
1404 | /* This is an internal VEC created to store information about *points inserted | |
926bf92d UW |
1405 | for each thread. This is used when PowerPC HWDEBUG ptrace interface is |
1406 | available. */ | |
6ffbb7ab TJB |
1407 | typedef struct thread_points |
1408 | { | |
1409 | /* The TID to which this *point relates. */ | |
1410 | int tid; | |
1411 | /* Information about the *point, such as its address, type, etc. | |
1412 | ||
1413 | Each element inside this vector corresponds to a hardware | |
1414 | breakpoint or watchpoint in the thread represented by TID. The maximum | |
1415 | size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of | |
1416 | the tuple is NULL, then the position in the vector is free. */ | |
1417 | struct hw_break_tuple *hw_breaks; | |
1418 | } *thread_points_p; | |
1419 | DEF_VEC_P (thread_points_p); | |
1420 | ||
1421 | VEC(thread_points_p) *ppc_threads = NULL; | |
1422 | ||
926bf92d UW |
1423 | /* The version of the PowerPC HWDEBUG kernel interface that we will use, if |
1424 | available. */ | |
6ffbb7ab TJB |
1425 | #define PPC_DEBUG_CURRENT_VERSION 1 |
1426 | ||
926bf92d | 1427 | /* Returns non-zero if we support the PowerPC HWDEBUG ptrace interface. */ |
e0d24f8d | 1428 | static int |
926bf92d | 1429 | have_ptrace_hwdebug_interface (void) |
e0d24f8d | 1430 | { |
926bf92d | 1431 | static int have_ptrace_hwdebug_interface = -1; |
e0d24f8d | 1432 | |
926bf92d | 1433 | if (have_ptrace_hwdebug_interface == -1) |
6ffbb7ab TJB |
1434 | { |
1435 | int tid; | |
e0d24f8d | 1436 | |
e38504b3 | 1437 | tid = inferior_ptid.lwp (); |
6ffbb7ab | 1438 | if (tid == 0) |
e99b03dc | 1439 | tid = inferior_ptid.pid (); |
e0d24f8d | 1440 | |
926bf92d UW |
1441 | /* Check for kernel support for PowerPC HWDEBUG ptrace interface. */ |
1442 | if (ptrace (PPC_PTRACE_GETHWDBGINFO, tid, 0, &hwdebug_info) >= 0) | |
6ffbb7ab | 1443 | { |
926bf92d | 1444 | /* Check whether PowerPC HWDEBUG ptrace interface is functional and |
0c56f59b | 1445 | provides any supported feature. */ |
926bf92d | 1446 | if (hwdebug_info.features != 0) |
0c56f59b | 1447 | { |
926bf92d UW |
1448 | have_ptrace_hwdebug_interface = 1; |
1449 | max_slots_number = hwdebug_info.num_instruction_bps | |
1450 | + hwdebug_info.num_data_bps | |
1451 | + hwdebug_info.num_condition_regs; | |
1452 | return have_ptrace_hwdebug_interface; | |
0c56f59b | 1453 | } |
6ffbb7ab | 1454 | } |
926bf92d UW |
1455 | /* Old school interface and no PowerPC HWDEBUG ptrace support. */ |
1456 | have_ptrace_hwdebug_interface = 0; | |
1457 | memset (&hwdebug_info, 0, sizeof (struct ppc_debug_info)); | |
6ffbb7ab TJB |
1458 | } |
1459 | ||
926bf92d | 1460 | return have_ptrace_hwdebug_interface; |
e0d24f8d WZ |
1461 | } |
1462 | ||
f6ac5f3d PA |
1463 | int |
1464 | ppc_linux_nat_target::can_use_hw_breakpoint (enum bptype type, int cnt, int ot) | |
b7622095 | 1465 | { |
6ffbb7ab | 1466 | int total_hw_wp, total_hw_bp; |
b7622095 | 1467 | |
926bf92d | 1468 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab | 1469 | { |
926bf92d UW |
1470 | /* When PowerPC HWDEBUG ptrace interface is available, the number of |
1471 | available hardware watchpoints and breakpoints is stored at the | |
1472 | hwdebug_info struct. */ | |
1473 | total_hw_bp = hwdebug_info.num_instruction_bps; | |
1474 | total_hw_wp = hwdebug_info.num_data_bps; | |
6ffbb7ab TJB |
1475 | } |
1476 | else | |
1477 | { | |
926bf92d UW |
1478 | /* When we do not have PowerPC HWDEBUG ptrace interface, we should |
1479 | consider having 1 hardware watchpoint and no hardware breakpoints. */ | |
6ffbb7ab TJB |
1480 | total_hw_bp = 0; |
1481 | total_hw_wp = 1; | |
1482 | } | |
b7622095 | 1483 | |
6ffbb7ab TJB |
1484 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint |
1485 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
1486 | { | |
bb08bdbd | 1487 | if (cnt + ot > total_hw_wp) |
6ffbb7ab TJB |
1488 | return -1; |
1489 | } | |
1490 | else if (type == bp_hardware_breakpoint) | |
1491 | { | |
572f6555 EBM |
1492 | if (total_hw_bp == 0) |
1493 | { | |
1494 | /* No hardware breakpoint support. */ | |
1495 | return 0; | |
1496 | } | |
6ffbb7ab TJB |
1497 | if (cnt > total_hw_bp) |
1498 | return -1; | |
1499 | } | |
1500 | ||
926bf92d | 1501 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1502 | { |
1503 | int tid; | |
1504 | ptid_t ptid = inferior_ptid; | |
1505 | ||
0df8b418 MS |
1506 | /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG |
1507 | and whether the target has DABR. If either answer is no, the | |
1508 | ptrace call will return -1. Fail in that case. */ | |
e38504b3 | 1509 | tid = ptid.lwp (); |
6ffbb7ab | 1510 | if (tid == 0) |
e99b03dc | 1511 | tid = ptid.pid (); |
6ffbb7ab TJB |
1512 | |
1513 | if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1) | |
1514 | return 0; | |
1515 | } | |
1516 | ||
1517 | return 1; | |
b7622095 LM |
1518 | } |
1519 | ||
f6ac5f3d PA |
1520 | int |
1521 | ppc_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
e0d24f8d WZ |
1522 | { |
1523 | /* Handle sub-8-byte quantities. */ | |
1524 | if (len <= 0) | |
1525 | return 0; | |
1526 | ||
926bf92d UW |
1527 | /* The PowerPC HWDEBUG ptrace interface tells if there are alignment |
1528 | restrictions for watchpoints in the processors. In that case, we use that | |
1529 | information to determine the hardcoded watchable region for | |
1530 | watchpoints. */ | |
1531 | if (have_ptrace_hwdebug_interface ()) | |
6ffbb7ab | 1532 | { |
e23b9d6e | 1533 | int region_size; |
4feebbdd EBM |
1534 | /* Embedded DAC-based processors, like the PowerPC 440 have ranged |
1535 | watchpoints and can watch any access within an arbitrary memory | |
1536 | region. This is useful to watch arrays and structs, for instance. It | |
1537 | takes two hardware watchpoints though. */ | |
e09342b5 | 1538 | if (len > 1 |
926bf92d | 1539 | && hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE |
4feebbdd | 1540 | && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
e09342b5 | 1541 | return 2; |
e23b9d6e UW |
1542 | /* Check if the processor provides DAWR interface. */ |
1543 | if (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_DAWR) | |
1544 | /* DAWR interface allows to watch up to 512 byte wide ranges which | |
1545 | can't cross a 512 byte boundary. */ | |
1546 | region_size = 512; | |
1547 | else | |
1548 | region_size = hwdebug_info.data_bp_alignment; | |
4feebbdd EBM |
1549 | /* Server processors provide one hardware watchpoint and addr+len should |
1550 | fall in the watchable region provided by the ptrace interface. */ | |
e23b9d6e UW |
1551 | if (region_size |
1552 | && (addr + len > (addr & ~(region_size - 1)) + region_size)) | |
0cf6dd15 | 1553 | return 0; |
6ffbb7ab | 1554 | } |
b7622095 | 1555 | /* addr+len must fall in the 8 byte watchable region for DABR-based |
926bf92d UW |
1556 | processors (i.e., server processors). Without the new PowerPC HWDEBUG |
1557 | ptrace interface, DAC-based processors (i.e., embedded processors) will | |
1558 | use addresses aligned to 4-bytes due to the way the read/write flags are | |
6ffbb7ab TJB |
1559 | passed in the old ptrace interface. */ |
1560 | else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
1561 | && (addr + len) > (addr & ~3) + 4) | |
1562 | || (addr + len) > (addr & ~7) + 8) | |
e0d24f8d WZ |
1563 | return 0; |
1564 | ||
1565 | return 1; | |
1566 | } | |
1567 | ||
6ffbb7ab | 1568 | /* This function compares two ppc_hw_breakpoint structs field-by-field. */ |
e4166a49 | 1569 | static int |
926bf92d | 1570 | hwdebug_point_cmp (struct ppc_hw_breakpoint *a, struct ppc_hw_breakpoint *b) |
6ffbb7ab | 1571 | { |
ad422571 TJB |
1572 | return (a->trigger_type == b->trigger_type |
1573 | && a->addr_mode == b->addr_mode | |
1574 | && a->condition_mode == b->condition_mode | |
1575 | && a->addr == b->addr | |
1576 | && a->addr2 == b->addr2 | |
6ffbb7ab TJB |
1577 | && a->condition_value == b->condition_value); |
1578 | } | |
1579 | ||
1580 | /* This function can be used to retrieve a thread_points by the TID of the | |
1581 | related process/thread. If nothing has been found, and ALLOC_NEW is 0, | |
1582 | it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the | |
1583 | provided TID will be created and returned. */ | |
1584 | static struct thread_points * | |
926bf92d | 1585 | hwdebug_find_thread_points_by_tid (int tid, int alloc_new) |
6ffbb7ab TJB |
1586 | { |
1587 | int i; | |
1588 | struct thread_points *t; | |
1589 | ||
1590 | for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, t); i++) | |
1591 | if (t->tid == tid) | |
1592 | return t; | |
1593 | ||
1594 | t = NULL; | |
1595 | ||
1596 | /* Do we need to allocate a new point_item | |
1597 | if the wanted one does not exist? */ | |
1598 | if (alloc_new) | |
1599 | { | |
8d749320 SM |
1600 | t = XNEW (struct thread_points); |
1601 | t->hw_breaks = XCNEWVEC (struct hw_break_tuple, max_slots_number); | |
6ffbb7ab TJB |
1602 | t->tid = tid; |
1603 | VEC_safe_push (thread_points_p, ppc_threads, t); | |
1604 | } | |
1605 | ||
1606 | return t; | |
1607 | } | |
1608 | ||
1609 | /* This function is a generic wrapper that is responsible for inserting a | |
1610 | *point (i.e., calling `ptrace' in order to issue the request to the | |
1611 | kernel) and registering it internally in GDB. */ | |
1612 | static void | |
926bf92d | 1613 | hwdebug_insert_point (struct ppc_hw_breakpoint *b, int tid) |
6ffbb7ab TJB |
1614 | { |
1615 | int i; | |
1616 | long slot; | |
a90ecff8 | 1617 | gdb::unique_xmalloc_ptr<ppc_hw_breakpoint> p (XDUP (ppc_hw_breakpoint, b)); |
6ffbb7ab | 1618 | struct hw_break_tuple *hw_breaks; |
6ffbb7ab | 1619 | struct thread_points *t; |
6ffbb7ab | 1620 | |
6ffbb7ab | 1621 | errno = 0; |
a90ecff8 | 1622 | slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p.get ()); |
6ffbb7ab TJB |
1623 | if (slot < 0) |
1624 | perror_with_name (_("Unexpected error setting breakpoint or watchpoint")); | |
1625 | ||
1626 | /* Everything went fine, so we have to register this *point. */ | |
926bf92d | 1627 | t = hwdebug_find_thread_points_by_tid (tid, 1); |
6ffbb7ab TJB |
1628 | gdb_assert (t != NULL); |
1629 | hw_breaks = t->hw_breaks; | |
1630 | ||
1631 | /* Find a free element in the hw_breaks vector. */ | |
1632 | for (i = 0; i < max_slots_number; i++) | |
1633 | if (hw_breaks[i].hw_break == NULL) | |
1634 | { | |
1635 | hw_breaks[i].slot = slot; | |
a90ecff8 | 1636 | hw_breaks[i].hw_break = p.release (); |
6ffbb7ab TJB |
1637 | break; |
1638 | } | |
1639 | ||
1640 | gdb_assert (i != max_slots_number); | |
6ffbb7ab TJB |
1641 | } |
1642 | ||
1643 | /* This function is a generic wrapper that is responsible for removing a | |
1644 | *point (i.e., calling `ptrace' in order to issue the request to the | |
1645 | kernel), and unregistering it internally at GDB. */ | |
1646 | static void | |
926bf92d | 1647 | hwdebug_remove_point (struct ppc_hw_breakpoint *b, int tid) |
6ffbb7ab TJB |
1648 | { |
1649 | int i; | |
1650 | struct hw_break_tuple *hw_breaks; | |
1651 | struct thread_points *t; | |
1652 | ||
926bf92d | 1653 | t = hwdebug_find_thread_points_by_tid (tid, 0); |
6ffbb7ab TJB |
1654 | gdb_assert (t != NULL); |
1655 | hw_breaks = t->hw_breaks; | |
1656 | ||
1657 | for (i = 0; i < max_slots_number; i++) | |
926bf92d | 1658 | if (hw_breaks[i].hw_break && hwdebug_point_cmp (hw_breaks[i].hw_break, b)) |
6ffbb7ab TJB |
1659 | break; |
1660 | ||
1661 | gdb_assert (i != max_slots_number); | |
1662 | ||
1663 | /* We have to ignore ENOENT errors because the kernel implements hardware | |
1664 | breakpoints/watchpoints as "one-shot", that is, they are automatically | |
1665 | deleted when hit. */ | |
1666 | errno = 0; | |
1667 | if (ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot) < 0) | |
1668 | if (errno != ENOENT) | |
0df8b418 MS |
1669 | perror_with_name (_("Unexpected error deleting " |
1670 | "breakpoint or watchpoint")); | |
6ffbb7ab TJB |
1671 | |
1672 | xfree (hw_breaks[i].hw_break); | |
1673 | hw_breaks[i].hw_break = NULL; | |
1674 | } | |
9f0bdab8 | 1675 | |
f1310107 TJB |
1676 | /* Return the number of registers needed for a ranged breakpoint. */ |
1677 | ||
f6ac5f3d PA |
1678 | int |
1679 | ppc_linux_nat_target::ranged_break_num_registers () | |
f1310107 | 1680 | { |
926bf92d UW |
1681 | return ((have_ptrace_hwdebug_interface () |
1682 | && hwdebug_info.features & PPC_DEBUG_FEATURE_INSN_BP_RANGE)? | |
f1310107 TJB |
1683 | 2 : -1); |
1684 | } | |
1685 | ||
1686 | /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for | |
1687 | success, 1 if hardware breakpoints are not supported or -1 for failure. */ | |
1688 | ||
f6ac5f3d PA |
1689 | int |
1690 | ppc_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, | |
1691 | struct bp_target_info *bp_tgt) | |
e0d24f8d | 1692 | { |
9f0bdab8 | 1693 | struct lwp_info *lp; |
6ffbb7ab TJB |
1694 | struct ppc_hw_breakpoint p; |
1695 | ||
926bf92d | 1696 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1697 | return -1; |
1698 | ||
ad422571 TJB |
1699 | p.version = PPC_DEBUG_CURRENT_VERSION; |
1700 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | |
ad422571 | 1701 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
0d5ed153 | 1702 | p.addr = (uint64_t) (bp_tgt->placed_address = bp_tgt->reqstd_address); |
6ffbb7ab TJB |
1703 | p.condition_value = 0; |
1704 | ||
f1310107 TJB |
1705 | if (bp_tgt->length) |
1706 | { | |
1707 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
1708 | ||
1709 | /* The breakpoint will trigger if the address of the instruction is | |
1710 | within the defined range, as follows: p.addr <= address < p.addr2. */ | |
1711 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; | |
1712 | } | |
1713 | else | |
1714 | { | |
1715 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
1716 | p.addr2 = 0; | |
1717 | } | |
1718 | ||
4c38200f | 1719 | ALL_LWPS (lp) |
e38504b3 | 1720 | hwdebug_insert_point (&p, lp->ptid.lwp ()); |
6ffbb7ab TJB |
1721 | |
1722 | return 0; | |
1723 | } | |
1724 | ||
f6ac5f3d PA |
1725 | int |
1726 | ppc_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, | |
1727 | struct bp_target_info *bp_tgt) | |
6ffbb7ab | 1728 | { |
6ffbb7ab TJB |
1729 | struct lwp_info *lp; |
1730 | struct ppc_hw_breakpoint p; | |
b7622095 | 1731 | |
926bf92d | 1732 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1733 | return -1; |
1734 | ||
ad422571 TJB |
1735 | p.version = PPC_DEBUG_CURRENT_VERSION; |
1736 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | |
ad422571 TJB |
1737 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
1738 | p.addr = (uint64_t) bp_tgt->placed_address; | |
6ffbb7ab TJB |
1739 | p.condition_value = 0; |
1740 | ||
f1310107 TJB |
1741 | if (bp_tgt->length) |
1742 | { | |
1743 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
1744 | ||
1745 | /* The breakpoint will trigger if the address of the instruction is within | |
1746 | the defined range, as follows: p.addr <= address < p.addr2. */ | |
1747 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; | |
1748 | } | |
1749 | else | |
1750 | { | |
1751 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
1752 | p.addr2 = 0; | |
1753 | } | |
1754 | ||
4c38200f | 1755 | ALL_LWPS (lp) |
e38504b3 | 1756 | hwdebug_remove_point (&p, lp->ptid.lwp ()); |
6ffbb7ab TJB |
1757 | |
1758 | return 0; | |
1759 | } | |
1760 | ||
1761 | static int | |
e76460db | 1762 | get_trigger_type (enum target_hw_bp_type type) |
6ffbb7ab TJB |
1763 | { |
1764 | int t; | |
1765 | ||
e76460db | 1766 | if (type == hw_read) |
6ffbb7ab | 1767 | t = PPC_BREAKPOINT_TRIGGER_READ; |
e76460db | 1768 | else if (type == hw_write) |
6ffbb7ab | 1769 | t = PPC_BREAKPOINT_TRIGGER_WRITE; |
b7622095 | 1770 | else |
6ffbb7ab TJB |
1771 | t = PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE; |
1772 | ||
1773 | return t; | |
1774 | } | |
1775 | ||
9c06b0b4 TJB |
1776 | /* Insert a new masked watchpoint at ADDR using the mask MASK. |
1777 | RW may be hw_read for a read watchpoint, hw_write for a write watchpoint | |
1778 | or hw_access for an access watchpoint. Returns 0 on success and throws | |
1779 | an error on failure. */ | |
1780 | ||
f6ac5f3d PA |
1781 | int |
1782 | ppc_linux_nat_target::insert_mask_watchpoint (CORE_ADDR addr, CORE_ADDR mask, | |
1783 | target_hw_bp_type rw) | |
9c06b0b4 | 1784 | { |
9c06b0b4 TJB |
1785 | struct lwp_info *lp; |
1786 | struct ppc_hw_breakpoint p; | |
1787 | ||
926bf92d | 1788 | gdb_assert (have_ptrace_hwdebug_interface ()); |
9c06b0b4 TJB |
1789 | |
1790 | p.version = PPC_DEBUG_CURRENT_VERSION; | |
1791 | p.trigger_type = get_trigger_type (rw); | |
1792 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; | |
1793 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
1794 | p.addr = addr; | |
1795 | p.addr2 = mask; | |
1796 | p.condition_value = 0; | |
1797 | ||
4c38200f | 1798 | ALL_LWPS (lp) |
e38504b3 | 1799 | hwdebug_insert_point (&p, lp->ptid.lwp ()); |
9c06b0b4 TJB |
1800 | |
1801 | return 0; | |
1802 | } | |
1803 | ||
1804 | /* Remove a masked watchpoint at ADDR with the mask MASK. | |
1805 | RW may be hw_read for a read watchpoint, hw_write for a write watchpoint | |
1806 | or hw_access for an access watchpoint. Returns 0 on success and throws | |
1807 | an error on failure. */ | |
1808 | ||
f6ac5f3d PA |
1809 | int |
1810 | ppc_linux_nat_target::remove_mask_watchpoint (CORE_ADDR addr, CORE_ADDR mask, | |
1811 | target_hw_bp_type rw) | |
9c06b0b4 | 1812 | { |
9c06b0b4 TJB |
1813 | struct lwp_info *lp; |
1814 | struct ppc_hw_breakpoint p; | |
1815 | ||
926bf92d | 1816 | gdb_assert (have_ptrace_hwdebug_interface ()); |
9c06b0b4 TJB |
1817 | |
1818 | p.version = PPC_DEBUG_CURRENT_VERSION; | |
1819 | p.trigger_type = get_trigger_type (rw); | |
1820 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; | |
1821 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
1822 | p.addr = addr; | |
1823 | p.addr2 = mask; | |
1824 | p.condition_value = 0; | |
1825 | ||
4c38200f | 1826 | ALL_LWPS (lp) |
e38504b3 | 1827 | hwdebug_remove_point (&p, lp->ptid.lwp ()); |
9c06b0b4 TJB |
1828 | |
1829 | return 0; | |
1830 | } | |
1831 | ||
0cf6dd15 TJB |
1832 | /* Check whether we have at least one free DVC register. */ |
1833 | static int | |
1834 | can_use_watchpoint_cond_accel (void) | |
1835 | { | |
1836 | struct thread_points *p; | |
e38504b3 | 1837 | int tid = inferior_ptid.lwp (); |
926bf92d | 1838 | int cnt = hwdebug_info.num_condition_regs, i; |
0cf6dd15 | 1839 | |
926bf92d | 1840 | if (!have_ptrace_hwdebug_interface () || cnt == 0) |
0cf6dd15 TJB |
1841 | return 0; |
1842 | ||
926bf92d | 1843 | p = hwdebug_find_thread_points_by_tid (tid, 0); |
0cf6dd15 TJB |
1844 | |
1845 | if (p) | |
1846 | { | |
1847 | for (i = 0; i < max_slots_number; i++) | |
1848 | if (p->hw_breaks[i].hw_break != NULL | |
1849 | && (p->hw_breaks[i].hw_break->condition_mode | |
1850 | != PPC_BREAKPOINT_CONDITION_NONE)) | |
1851 | cnt--; | |
1852 | ||
1853 | /* There are no available slots now. */ | |
1854 | if (cnt <= 0) | |
1855 | return 0; | |
1856 | } | |
1857 | ||
1858 | return 1; | |
1859 | } | |
1860 | ||
1861 | /* Calculate the enable bits and the contents of the Data Value Compare | |
1862 | debug register present in BookE processors. | |
1863 | ||
1864 | ADDR is the address to be watched, LEN is the length of watched data | |
1865 | and DATA_VALUE is the value which will trigger the watchpoint. | |
1866 | On exit, CONDITION_MODE will hold the enable bits for the DVC, and | |
1867 | CONDITION_VALUE will hold the value which should be put in the | |
1868 | DVC register. */ | |
1869 | static void | |
1870 | calculate_dvc (CORE_ADDR addr, int len, CORE_ADDR data_value, | |
1871 | uint32_t *condition_mode, uint64_t *condition_value) | |
1872 | { | |
1873 | int i, num_byte_enable, align_offset, num_bytes_off_dvc, | |
1874 | rightmost_enabled_byte; | |
1875 | CORE_ADDR addr_end_data, addr_end_dvc; | |
1876 | ||
1877 | /* The DVC register compares bytes within fixed-length windows which | |
1878 | are word-aligned, with length equal to that of the DVC register. | |
1879 | We need to calculate where our watch region is relative to that | |
1880 | window and enable comparison of the bytes which fall within it. */ | |
1881 | ||
926bf92d | 1882 | align_offset = addr % hwdebug_info.sizeof_condition; |
0cf6dd15 TJB |
1883 | addr_end_data = addr + len; |
1884 | addr_end_dvc = (addr - align_offset | |
926bf92d | 1885 | + hwdebug_info.sizeof_condition); |
0cf6dd15 TJB |
1886 | num_bytes_off_dvc = (addr_end_data > addr_end_dvc)? |
1887 | addr_end_data - addr_end_dvc : 0; | |
1888 | num_byte_enable = len - num_bytes_off_dvc; | |
1889 | /* Here, bytes are numbered from right to left. */ | |
1890 | rightmost_enabled_byte = (addr_end_data < addr_end_dvc)? | |
1891 | addr_end_dvc - addr_end_data : 0; | |
1892 | ||
1893 | *condition_mode = PPC_BREAKPOINT_CONDITION_AND; | |
1894 | for (i = 0; i < num_byte_enable; i++) | |
0df8b418 MS |
1895 | *condition_mode |
1896 | |= PPC_BREAKPOINT_CONDITION_BE (i + rightmost_enabled_byte); | |
0cf6dd15 TJB |
1897 | |
1898 | /* Now we need to match the position within the DVC of the comparison | |
1899 | value with where the watch region is relative to the window | |
1900 | (i.e., the ALIGN_OFFSET). */ | |
1901 | ||
1902 | *condition_value = ((uint64_t) data_value >> num_bytes_off_dvc * 8 | |
1903 | << rightmost_enabled_byte * 8); | |
1904 | } | |
1905 | ||
1906 | /* Return the number of memory locations that need to be accessed to | |
1907 | evaluate the expression which generated the given value chain. | |
1908 | Returns -1 if there's any register access involved, or if there are | |
1909 | other kinds of values which are not acceptable in a condition | |
1910 | expression (e.g., lval_computed or lval_internalvar). */ | |
1911 | static int | |
a6535de1 | 1912 | num_memory_accesses (const std::vector<value_ref_ptr> &chain) |
0cf6dd15 TJB |
1913 | { |
1914 | int found_memory_cnt = 0; | |
0cf6dd15 TJB |
1915 | |
1916 | /* The idea here is that evaluating an expression generates a series | |
1917 | of values, one holding the value of every subexpression. (The | |
1918 | expression a*b+c has five subexpressions: a, b, a*b, c, and | |
1919 | a*b+c.) GDB's values hold almost enough information to establish | |
1920 | the criteria given above --- they identify memory lvalues, | |
1921 | register lvalues, computed values, etcetera. So we can evaluate | |
1922 | the expression, and then scan the chain of values that leaves | |
1923 | behind to determine the memory locations involved in the evaluation | |
1924 | of an expression. | |
1925 | ||
1926 | However, I don't think that the values returned by inferior | |
1927 | function calls are special in any way. So this function may not | |
1928 | notice that an expression contains an inferior function call. | |
1929 | FIXME. */ | |
1930 | ||
a6535de1 | 1931 | for (const value_ref_ptr &iter : chain) |
0cf6dd15 | 1932 | { |
a6535de1 TT |
1933 | struct value *v = iter.get (); |
1934 | ||
0cf6dd15 TJB |
1935 | /* Constants and values from the history are fine. */ |
1936 | if (VALUE_LVAL (v) == not_lval || deprecated_value_modifiable (v) == 0) | |
1937 | continue; | |
1938 | else if (VALUE_LVAL (v) == lval_memory) | |
1939 | { | |
1940 | /* A lazy memory lvalue is one that GDB never needed to fetch; | |
1941 | we either just used its address (e.g., `a' in `a.b') or | |
1942 | we never needed it at all (e.g., `a' in `a,b'). */ | |
1943 | if (!value_lazy (v)) | |
1944 | found_memory_cnt++; | |
1945 | } | |
0df8b418 | 1946 | /* Other kinds of values are not fine. */ |
0cf6dd15 TJB |
1947 | else |
1948 | return -1; | |
1949 | } | |
1950 | ||
1951 | return found_memory_cnt; | |
1952 | } | |
1953 | ||
1954 | /* Verifies whether the expression COND can be implemented using the | |
1955 | DVC (Data Value Compare) register in BookE processors. The expression | |
1956 | must test the watch value for equality with a constant expression. | |
1957 | If the function returns 1, DATA_VALUE will contain the constant against | |
e7db58ea TJB |
1958 | which the watch value should be compared and LEN will contain the size |
1959 | of the constant. */ | |
0cf6dd15 TJB |
1960 | static int |
1961 | check_condition (CORE_ADDR watch_addr, struct expression *cond, | |
e7db58ea | 1962 | CORE_ADDR *data_value, int *len) |
0cf6dd15 TJB |
1963 | { |
1964 | int pc = 1, num_accesses_left, num_accesses_right; | |
a6535de1 TT |
1965 | struct value *left_val, *right_val; |
1966 | std::vector<value_ref_ptr> left_chain, right_chain; | |
0cf6dd15 TJB |
1967 | |
1968 | if (cond->elts[0].opcode != BINOP_EQUAL) | |
1969 | return 0; | |
1970 | ||
3a1115a0 | 1971 | fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain, 0); |
0cf6dd15 TJB |
1972 | num_accesses_left = num_memory_accesses (left_chain); |
1973 | ||
1974 | if (left_val == NULL || num_accesses_left < 0) | |
a6535de1 | 1975 | return 0; |
0cf6dd15 | 1976 | |
3a1115a0 | 1977 | fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain, 0); |
0cf6dd15 TJB |
1978 | num_accesses_right = num_memory_accesses (right_chain); |
1979 | ||
1980 | if (right_val == NULL || num_accesses_right < 0) | |
a6535de1 | 1981 | return 0; |
0cf6dd15 TJB |
1982 | |
1983 | if (num_accesses_left == 1 && num_accesses_right == 0 | |
1984 | && VALUE_LVAL (left_val) == lval_memory | |
1985 | && value_address (left_val) == watch_addr) | |
e7db58ea TJB |
1986 | { |
1987 | *data_value = value_as_long (right_val); | |
1988 | ||
1989 | /* DATA_VALUE is the constant in RIGHT_VAL, but actually has | |
1990 | the same type as the memory region referenced by LEFT_VAL. */ | |
1991 | *len = TYPE_LENGTH (check_typedef (value_type (left_val))); | |
1992 | } | |
0cf6dd15 TJB |
1993 | else if (num_accesses_left == 0 && num_accesses_right == 1 |
1994 | && VALUE_LVAL (right_val) == lval_memory | |
1995 | && value_address (right_val) == watch_addr) | |
e7db58ea TJB |
1996 | { |
1997 | *data_value = value_as_long (left_val); | |
1998 | ||
1999 | /* DATA_VALUE is the constant in LEFT_VAL, but actually has | |
2000 | the same type as the memory region referenced by RIGHT_VAL. */ | |
2001 | *len = TYPE_LENGTH (check_typedef (value_type (right_val))); | |
2002 | } | |
0cf6dd15 | 2003 | else |
a6535de1 | 2004 | return 0; |
0cf6dd15 TJB |
2005 | |
2006 | return 1; | |
2007 | } | |
2008 | ||
2009 | /* Return non-zero if the target is capable of using hardware to evaluate | |
2010 | the condition expression, thus only triggering the watchpoint when it is | |
2011 | true. */ | |
57810aa7 | 2012 | bool |
f6ac5f3d PA |
2013 | ppc_linux_nat_target::can_accel_watchpoint_condition (CORE_ADDR addr, int len, |
2014 | int rw, | |
2015 | struct expression *cond) | |
0cf6dd15 TJB |
2016 | { |
2017 | CORE_ADDR data_value; | |
2018 | ||
926bf92d UW |
2019 | return (have_ptrace_hwdebug_interface () |
2020 | && hwdebug_info.num_condition_regs > 0 | |
e7db58ea | 2021 | && check_condition (addr, cond, &data_value, &len)); |
0cf6dd15 TJB |
2022 | } |
2023 | ||
e09342b5 TJB |
2024 | /* Set up P with the parameters necessary to request a watchpoint covering |
2025 | LEN bytes starting at ADDR and if possible with condition expression COND | |
2026 | evaluated by hardware. INSERT tells if we are creating a request for | |
2027 | inserting or removing the watchpoint. */ | |
2028 | ||
2029 | static void | |
2030 | create_watchpoint_request (struct ppc_hw_breakpoint *p, CORE_ADDR addr, | |
e76460db PA |
2031 | int len, enum target_hw_bp_type type, |
2032 | struct expression *cond, int insert) | |
e09342b5 | 2033 | { |
f16c4e8b | 2034 | if (len == 1 |
926bf92d | 2035 | || !(hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE)) |
e09342b5 TJB |
2036 | { |
2037 | int use_condition; | |
2038 | CORE_ADDR data_value; | |
2039 | ||
2040 | use_condition = (insert? can_use_watchpoint_cond_accel () | |
926bf92d | 2041 | : hwdebug_info.num_condition_regs > 0); |
e7db58ea TJB |
2042 | if (cond && use_condition && check_condition (addr, cond, |
2043 | &data_value, &len)) | |
e09342b5 TJB |
2044 | calculate_dvc (addr, len, data_value, &p->condition_mode, |
2045 | &p->condition_value); | |
2046 | else | |
2047 | { | |
2048 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
2049 | p->condition_value = 0; | |
2050 | } | |
2051 | ||
2052 | p->addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
2053 | p->addr2 = 0; | |
2054 | } | |
2055 | else | |
2056 | { | |
2057 | p->addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
2058 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
2059 | p->condition_value = 0; | |
2060 | ||
2061 | /* The watchpoint will trigger if the address of the memory access is | |
2062 | within the defined range, as follows: p->addr <= address < p->addr2. | |
2063 | ||
2064 | Note that the above sentence just documents how ptrace interprets | |
2065 | its arguments; the watchpoint is set to watch the range defined by | |
2066 | the user _inclusively_, as specified by the user interface. */ | |
2067 | p->addr2 = (uint64_t) addr + len; | |
2068 | } | |
2069 | ||
2070 | p->version = PPC_DEBUG_CURRENT_VERSION; | |
e76460db | 2071 | p->trigger_type = get_trigger_type (type); |
e09342b5 TJB |
2072 | p->addr = (uint64_t) addr; |
2073 | } | |
2074 | ||
f6ac5f3d PA |
2075 | int |
2076 | ppc_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, | |
2077 | enum target_hw_bp_type type, | |
2078 | struct expression *cond) | |
6ffbb7ab TJB |
2079 | { |
2080 | struct lwp_info *lp; | |
6ffbb7ab TJB |
2081 | int ret = -1; |
2082 | ||
926bf92d | 2083 | if (have_ptrace_hwdebug_interface ()) |
e0d24f8d | 2084 | { |
6ffbb7ab TJB |
2085 | struct ppc_hw_breakpoint p; |
2086 | ||
e76460db | 2087 | create_watchpoint_request (&p, addr, len, type, cond, 1); |
6ffbb7ab | 2088 | |
4c38200f | 2089 | ALL_LWPS (lp) |
e38504b3 | 2090 | hwdebug_insert_point (&p, lp->ptid.lwp ()); |
6ffbb7ab TJB |
2091 | |
2092 | ret = 0; | |
e0d24f8d | 2093 | } |
6ffbb7ab TJB |
2094 | else |
2095 | { | |
2096 | long dabr_value; | |
2097 | long read_mode, write_mode; | |
e0d24f8d | 2098 | |
6ffbb7ab TJB |
2099 | if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
2100 | { | |
2101 | /* PowerPC 440 requires only the read/write flags to be passed | |
2102 | to the kernel. */ | |
ad422571 | 2103 | read_mode = 1; |
6ffbb7ab TJB |
2104 | write_mode = 2; |
2105 | } | |
2106 | else | |
2107 | { | |
2108 | /* PowerPC 970 and other DABR-based processors are required to pass | |
2109 | the Breakpoint Translation bit together with the flags. */ | |
ad422571 | 2110 | read_mode = 5; |
6ffbb7ab TJB |
2111 | write_mode = 6; |
2112 | } | |
1c86e440 | 2113 | |
6ffbb7ab | 2114 | dabr_value = addr & ~(read_mode | write_mode); |
e76460db | 2115 | switch (type) |
6ffbb7ab TJB |
2116 | { |
2117 | case hw_read: | |
2118 | /* Set read and translate bits. */ | |
2119 | dabr_value |= read_mode; | |
2120 | break; | |
2121 | case hw_write: | |
2122 | /* Set write and translate bits. */ | |
2123 | dabr_value |= write_mode; | |
2124 | break; | |
2125 | case hw_access: | |
2126 | /* Set read, write and translate bits. */ | |
2127 | dabr_value |= read_mode | write_mode; | |
2128 | break; | |
2129 | } | |
1c86e440 | 2130 | |
6ffbb7ab TJB |
2131 | saved_dabr_value = dabr_value; |
2132 | ||
4c38200f | 2133 | ALL_LWPS (lp) |
e38504b3 | 2134 | if (ptrace (PTRACE_SET_DEBUGREG, lp->ptid.lwp (), 0, |
0cf6dd15 | 2135 | saved_dabr_value) < 0) |
6ffbb7ab TJB |
2136 | return -1; |
2137 | ||
2138 | ret = 0; | |
2139 | } | |
2140 | ||
2141 | return ret; | |
e0d24f8d WZ |
2142 | } |
2143 | ||
f6ac5f3d PA |
2144 | int |
2145 | ppc_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, | |
2146 | enum target_hw_bp_type type, | |
2147 | struct expression *cond) | |
e0d24f8d | 2148 | { |
9f0bdab8 | 2149 | struct lwp_info *lp; |
6ffbb7ab | 2150 | int ret = -1; |
9f0bdab8 | 2151 | |
926bf92d | 2152 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2153 | { |
2154 | struct ppc_hw_breakpoint p; | |
2155 | ||
e76460db | 2156 | create_watchpoint_request (&p, addr, len, type, cond, 0); |
6ffbb7ab | 2157 | |
4c38200f | 2158 | ALL_LWPS (lp) |
e38504b3 | 2159 | hwdebug_remove_point (&p, lp->ptid.lwp ()); |
6ffbb7ab TJB |
2160 | |
2161 | ret = 0; | |
2162 | } | |
2163 | else | |
2164 | { | |
2165 | saved_dabr_value = 0; | |
4c38200f | 2166 | ALL_LWPS (lp) |
e38504b3 | 2167 | if (ptrace (PTRACE_SET_DEBUGREG, lp->ptid.lwp (), 0, |
0cf6dd15 | 2168 | saved_dabr_value) < 0) |
6ffbb7ab TJB |
2169 | return -1; |
2170 | ||
2171 | ret = 0; | |
2172 | } | |
2173 | ||
2174 | return ret; | |
e0d24f8d WZ |
2175 | } |
2176 | ||
135340af PA |
2177 | void |
2178 | ppc_linux_nat_target::low_new_thread (struct lwp_info *lp) | |
e0d24f8d | 2179 | { |
e38504b3 | 2180 | int tid = lp->ptid.lwp (); |
6ffbb7ab | 2181 | |
926bf92d | 2182 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2183 | { |
2184 | int i; | |
2185 | struct thread_points *p; | |
2186 | struct hw_break_tuple *hw_breaks; | |
2187 | ||
2188 | if (VEC_empty (thread_points_p, ppc_threads)) | |
2189 | return; | |
2190 | ||
0df8b418 | 2191 | /* Get a list of breakpoints from any thread. */ |
6ffbb7ab TJB |
2192 | p = VEC_last (thread_points_p, ppc_threads); |
2193 | hw_breaks = p->hw_breaks; | |
2194 | ||
0df8b418 | 2195 | /* Copy that thread's breakpoints and watchpoints to the new thread. */ |
6ffbb7ab TJB |
2196 | for (i = 0; i < max_slots_number; i++) |
2197 | if (hw_breaks[i].hw_break) | |
aacbb8a5 LM |
2198 | { |
2199 | /* Older kernels did not make new threads inherit their parent | |
2200 | thread's debug state, so we always clear the slot and replicate | |
2201 | the debug state ourselves, ensuring compatibility with all | |
2202 | kernels. */ | |
2203 | ||
2204 | /* The ppc debug resource accounting is done through "slots". | |
2205 | Ask the kernel the deallocate this specific *point's slot. */ | |
2206 | ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot); | |
2207 | ||
926bf92d | 2208 | hwdebug_insert_point (hw_breaks[i].hw_break, tid); |
aacbb8a5 | 2209 | } |
6ffbb7ab TJB |
2210 | } |
2211 | else | |
2212 | ptrace (PTRACE_SET_DEBUGREG, tid, 0, saved_dabr_value); | |
2213 | } | |
2214 | ||
2215 | static void | |
2216 | ppc_linux_thread_exit (struct thread_info *tp, int silent) | |
2217 | { | |
2218 | int i; | |
e38504b3 | 2219 | int tid = tp->ptid.lwp (); |
6ffbb7ab TJB |
2220 | struct hw_break_tuple *hw_breaks; |
2221 | struct thread_points *t = NULL, *p; | |
2222 | ||
926bf92d | 2223 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2224 | return; |
2225 | ||
2226 | for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, p); i++) | |
2227 | if (p->tid == tid) | |
2228 | { | |
2229 | t = p; | |
2230 | break; | |
2231 | } | |
2232 | ||
2233 | if (t == NULL) | |
2234 | return; | |
2235 | ||
2236 | VEC_unordered_remove (thread_points_p, ppc_threads, i); | |
2237 | ||
2238 | hw_breaks = t->hw_breaks; | |
2239 | ||
2240 | for (i = 0; i < max_slots_number; i++) | |
2241 | if (hw_breaks[i].hw_break) | |
2242 | xfree (hw_breaks[i].hw_break); | |
2243 | ||
2244 | xfree (t->hw_breaks); | |
2245 | xfree (t); | |
e0d24f8d WZ |
2246 | } |
2247 | ||
57810aa7 | 2248 | bool |
f6ac5f3d | 2249 | ppc_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) |
e0d24f8d | 2250 | { |
f865ee35 | 2251 | siginfo_t siginfo; |
e0d24f8d | 2252 | |
f865ee35 | 2253 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) |
57810aa7 | 2254 | return false; |
e0d24f8d | 2255 | |
f865ee35 JK |
2256 | if (siginfo.si_signo != SIGTRAP |
2257 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
57810aa7 | 2258 | return false; |
e0d24f8d | 2259 | |
926bf92d | 2260 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2261 | { |
2262 | int i; | |
2263 | struct thread_points *t; | |
2264 | struct hw_break_tuple *hw_breaks; | |
2265 | /* The index (or slot) of the *point is passed in the si_errno field. */ | |
f865ee35 | 2266 | int slot = siginfo.si_errno; |
6ffbb7ab | 2267 | |
e38504b3 | 2268 | t = hwdebug_find_thread_points_by_tid (inferior_ptid.lwp (), 0); |
6ffbb7ab TJB |
2269 | |
2270 | /* Find out if this *point is a hardware breakpoint. | |
2271 | If so, we should return 0. */ | |
2272 | if (t) | |
2273 | { | |
2274 | hw_breaks = t->hw_breaks; | |
2275 | for (i = 0; i < max_slots_number; i++) | |
2276 | if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot | |
2277 | && hw_breaks[i].hw_break->trigger_type | |
2278 | == PPC_BREAKPOINT_TRIGGER_EXECUTE) | |
57810aa7 | 2279 | return false; |
6ffbb7ab TJB |
2280 | } |
2281 | } | |
2282 | ||
f865ee35 | 2283 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
57810aa7 | 2284 | return true; |
e0d24f8d WZ |
2285 | } |
2286 | ||
57810aa7 | 2287 | bool |
f6ac5f3d | 2288 | ppc_linux_nat_target::stopped_by_watchpoint () |
9f0bdab8 DJ |
2289 | { |
2290 | CORE_ADDR addr; | |
f6ac5f3d | 2291 | return stopped_data_address (&addr); |
9f0bdab8 DJ |
2292 | } |
2293 | ||
57810aa7 | 2294 | bool |
f6ac5f3d PA |
2295 | ppc_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr, |
2296 | CORE_ADDR start, | |
2297 | int length) | |
5009afc5 | 2298 | { |
b7622095 LM |
2299 | int mask; |
2300 | ||
926bf92d | 2301 | if (have_ptrace_hwdebug_interface () |
6ffbb7ab TJB |
2302 | && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
2303 | return start <= addr && start + length >= addr; | |
2304 | else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
b7622095 LM |
2305 | mask = 3; |
2306 | else | |
2307 | mask = 7; | |
2308 | ||
2309 | addr &= ~mask; | |
2310 | ||
0df8b418 | 2311 | /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */ |
b7622095 | 2312 | return start <= addr + mask && start + length - 1 >= addr; |
5009afc5 AS |
2313 | } |
2314 | ||
9c06b0b4 TJB |
2315 | /* Return the number of registers needed for a masked hardware watchpoint. */ |
2316 | ||
f6ac5f3d PA |
2317 | int |
2318 | ppc_linux_nat_target::masked_watch_num_registers (CORE_ADDR addr, CORE_ADDR mask) | |
9c06b0b4 | 2319 | { |
926bf92d UW |
2320 | if (!have_ptrace_hwdebug_interface () |
2321 | || (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_MASK) == 0) | |
9c06b0b4 TJB |
2322 | return -1; |
2323 | else if ((mask & 0xC0000000) != 0xC0000000) | |
2324 | { | |
2325 | warning (_("The given mask covers kernel address space " | |
2326 | "and cannot be used.\n")); | |
2327 | ||
2328 | return -2; | |
2329 | } | |
2330 | else | |
2331 | return 2; | |
2332 | } | |
2333 | ||
f6ac5f3d PA |
2334 | void |
2335 | ppc_linux_nat_target::store_registers (struct regcache *regcache, int regno) | |
45229ea4 | 2336 | { |
222312d3 | 2337 | pid_t tid = get_ptrace_pid (regcache->ptid ()); |
05f13b9c | 2338 | |
45229ea4 | 2339 | if (regno >= 0) |
56be3814 | 2340 | store_register (regcache, tid, regno); |
45229ea4 | 2341 | else |
56be3814 | 2342 | store_ppc_registers (regcache, tid); |
45229ea4 EZ |
2343 | } |
2344 | ||
f2db237a AM |
2345 | /* Functions for transferring registers between a gregset_t or fpregset_t |
2346 | (see sys/ucontext.h) and gdb's regcache. The word size is that used | |
0df8b418 | 2347 | by the ptrace interface, not the current program's ABI. Eg. if a |
f2db237a AM |
2348 | powerpc64-linux gdb is being used to debug a powerpc32-linux app, we |
2349 | read or write 64-bit gregsets. This is to suit the host libthread_db. */ | |
2350 | ||
50c9bd31 | 2351 | void |
7f7fe91e | 2352 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
c877c8e6 | 2353 | { |
f2db237a | 2354 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 2355 | |
f2db237a | 2356 | ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp)); |
c877c8e6 KB |
2357 | } |
2358 | ||
fdb28ac4 | 2359 | void |
7f7fe91e UW |
2360 | fill_gregset (const struct regcache *regcache, |
2361 | gdb_gregset_t *gregsetp, int regno) | |
fdb28ac4 | 2362 | { |
f2db237a | 2363 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 2364 | |
f2db237a AM |
2365 | if (regno == -1) |
2366 | memset (gregsetp, 0, sizeof (*gregsetp)); | |
2367 | ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp)); | |
fdb28ac4 KB |
2368 | } |
2369 | ||
50c9bd31 | 2370 | void |
7f7fe91e | 2371 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp) |
c877c8e6 | 2372 | { |
f2db237a AM |
2373 | const struct regset *regset = ppc_linux_fpregset (); |
2374 | ||
2375 | ppc_supply_fpregset (regset, regcache, -1, | |
2376 | fpregsetp, sizeof (*fpregsetp)); | |
c877c8e6 | 2377 | } |
fdb28ac4 | 2378 | |
fdb28ac4 | 2379 | void |
7f7fe91e UW |
2380 | fill_fpregset (const struct regcache *regcache, |
2381 | gdb_fpregset_t *fpregsetp, int regno) | |
fdb28ac4 | 2382 | { |
f2db237a AM |
2383 | const struct regset *regset = ppc_linux_fpregset (); |
2384 | ||
2385 | ppc_collect_fpregset (regset, regcache, regno, | |
2386 | fpregsetp, sizeof (*fpregsetp)); | |
fdb28ac4 | 2387 | } |
10d6c8cd | 2388 | |
2e077f5e PFC |
2389 | int |
2390 | ppc_linux_nat_target::auxv_parse (gdb_byte **readptr, | |
2391 | gdb_byte *endptr, CORE_ADDR *typep, | |
2392 | CORE_ADDR *valp) | |
409c383c | 2393 | { |
e38504b3 | 2394 | int tid = inferior_ptid.lwp (); |
409c383c | 2395 | if (tid == 0) |
e99b03dc | 2396 | tid = inferior_ptid.pid (); |
409c383c | 2397 | |
2e077f5e | 2398 | int sizeof_auxv_field = ppc_linux_target_wordsize (tid); |
409c383c | 2399 | |
f5656ead | 2400 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); |
409c383c UW |
2401 | gdb_byte *ptr = *readptr; |
2402 | ||
2403 | if (endptr == ptr) | |
2404 | return 0; | |
2405 | ||
2406 | if (endptr - ptr < sizeof_auxv_field * 2) | |
2407 | return -1; | |
2408 | ||
e17a4113 | 2409 | *typep = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); |
409c383c | 2410 | ptr += sizeof_auxv_field; |
e17a4113 | 2411 | *valp = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); |
409c383c UW |
2412 | ptr += sizeof_auxv_field; |
2413 | ||
2414 | *readptr = ptr; | |
2415 | return 1; | |
2416 | } | |
2417 | ||
f6ac5f3d PA |
2418 | const struct target_desc * |
2419 | ppc_linux_nat_target::read_description () | |
310a98e1 | 2420 | { |
e38504b3 | 2421 | int tid = inferior_ptid.lwp (); |
7284e1be | 2422 | if (tid == 0) |
e99b03dc | 2423 | tid = inferior_ptid.pid (); |
7284e1be | 2424 | |
310a98e1 DJ |
2425 | if (have_ptrace_getsetevrregs) |
2426 | { | |
2427 | struct gdb_evrregset_t evrregset; | |
310a98e1 DJ |
2428 | |
2429 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0) | |
7284e1be UW |
2430 | return tdesc_powerpc_e500l; |
2431 | ||
2432 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported. | |
2433 | Anything else needs to be reported. */ | |
2434 | else if (errno != EIO) | |
2435 | perror_with_name (_("Unable to fetch SPE registers")); | |
2436 | } | |
2437 | ||
bd64614e PFC |
2438 | struct ppc_linux_features features = ppc_linux_no_features; |
2439 | ||
2e077f5e | 2440 | features.wordsize = ppc_linux_target_wordsize (tid); |
bd64614e | 2441 | |
0ec848ad | 2442 | CORE_ADDR hwcap = ppc_linux_get_hwcap (); |
7ca18ed6 | 2443 | CORE_ADDR hwcap2 = ppc_linux_get_hwcap2 (); |
bd64614e | 2444 | |
0154d990 | 2445 | if (have_ptrace_getsetvsxregs |
bd64614e | 2446 | && (hwcap & PPC_FEATURE_HAS_VSX)) |
604c2f83 LM |
2447 | { |
2448 | gdb_vsxregset_t vsxregset; | |
2449 | ||
2450 | if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0) | |
bd64614e | 2451 | features.vsx = true; |
604c2f83 LM |
2452 | |
2453 | /* EIO means that the PTRACE_GETVSXREGS request isn't supported. | |
2454 | Anything else needs to be reported. */ | |
2455 | else if (errno != EIO) | |
2456 | perror_with_name (_("Unable to fetch VSX registers")); | |
2457 | } | |
2458 | ||
0154d990 | 2459 | if (have_ptrace_getvrregs |
bd64614e | 2460 | && (hwcap & PPC_FEATURE_HAS_ALTIVEC)) |
7284e1be UW |
2461 | { |
2462 | gdb_vrregset_t vrregset; | |
2463 | ||
2464 | if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0) | |
bd64614e | 2465 | features.altivec = true; |
7284e1be UW |
2466 | |
2467 | /* EIO means that the PTRACE_GETVRREGS request isn't supported. | |
2468 | Anything else needs to be reported. */ | |
2469 | else if (errno != EIO) | |
2470 | perror_with_name (_("Unable to fetch AltiVec registers")); | |
310a98e1 DJ |
2471 | } |
2472 | ||
bd64614e PFC |
2473 | if (hwcap & PPC_FEATURE_CELL) |
2474 | features.cell = true; | |
7284e1be | 2475 | |
bd64614e | 2476 | features.isa205 = ppc_linux_has_isa205 (hwcap); |
604c2f83 | 2477 | |
7ca18ed6 EBM |
2478 | if ((hwcap2 & PPC_FEATURE2_DSCR) |
2479 | && check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET) | |
2480 | && check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET)) | |
f2cf6173 EBM |
2481 | { |
2482 | features.ppr_dscr = true; | |
2483 | if ((hwcap2 & PPC_FEATURE2_ARCH_2_07) | |
2484 | && (hwcap2 & PPC_FEATURE2_TAR) | |
232bfb86 EBM |
2485 | && (hwcap2 & PPC_FEATURE2_EBB) |
2486 | && check_regset (tid, NT_PPC_TAR, PPC_LINUX_SIZEOF_TARREGSET) | |
2487 | && check_regset (tid, NT_PPC_EBB, PPC_LINUX_SIZEOF_EBBREGSET) | |
2488 | && check_regset (tid, NT_PPC_PMU, PPC_LINUX_SIZEOF_PMUREGSET)) | |
f2cf6173 EBM |
2489 | features.isa207 = true; |
2490 | } | |
7ca18ed6 | 2491 | |
bd64614e | 2492 | return ppc_linux_match_description (features); |
310a98e1 DJ |
2493 | } |
2494 | ||
10d6c8cd DJ |
2495 | void |
2496 | _initialize_ppc_linux_nat (void) | |
2497 | { | |
f6ac5f3d | 2498 | linux_target = &the_ppc_linux_nat_target; |
310a98e1 | 2499 | |
76727919 | 2500 | gdb::observers::thread_exit.attach (ppc_linux_thread_exit); |
6ffbb7ab | 2501 | |
10d6c8cd | 2502 | /* Register the target. */ |
d9f719f1 | 2503 | add_inf_child_target (linux_target); |
10d6c8cd | 2504 | } |