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9abe5450 | 1 | /* PPC GNU/Linux native support. |
2555fe1a | 2 | |
28e7fd62 | 3 | Copyright (C) 1988-2013 Free Software Foundation, Inc. |
c877c8e6 KB |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c877c8e6 KB |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c877c8e6 KB |
19 | |
20 | #include "defs.h" | |
e162d11b | 21 | #include "gdb_string.h" |
6ffbb7ab | 22 | #include "observer.h" |
c877c8e6 KB |
23 | #include "frame.h" |
24 | #include "inferior.h" | |
6ffbb7ab | 25 | #include "gdbthread.h" |
c877c8e6 | 26 | #include "gdbcore.h" |
4e052eda | 27 | #include "regcache.h" |
383f0f5b | 28 | #include "gdb_assert.h" |
10d6c8cd DJ |
29 | #include "target.h" |
30 | #include "linux-nat.h" | |
c877c8e6 | 31 | |
411cb3f9 | 32 | #include <stdint.h> |
c877c8e6 | 33 | #include <sys/types.h> |
c877c8e6 KB |
34 | #include <signal.h> |
35 | #include <sys/user.h> | |
36 | #include <sys/ioctl.h> | |
2555fe1a | 37 | #include "gdb_wait.h" |
c877c8e6 KB |
38 | #include <fcntl.h> |
39 | #include <sys/procfs.h> | |
45229ea4 | 40 | #include <sys/ptrace.h> |
c877c8e6 | 41 | |
0df8b418 | 42 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f | 43 | #include "gregset.h" |
16333c4f | 44 | #include "ppc-tdep.h" |
7284e1be UW |
45 | #include "ppc-linux-tdep.h" |
46 | ||
b7622095 LM |
47 | /* Required when using the AUXV. */ |
48 | #include "elf/common.h" | |
49 | #include "auxv.h" | |
50 | ||
7284e1be UW |
51 | /* This sometimes isn't defined. */ |
52 | #ifndef PT_ORIG_R3 | |
53 | #define PT_ORIG_R3 34 | |
54 | #endif | |
55 | #ifndef PT_TRAP | |
56 | #define PT_TRAP 40 | |
57 | #endif | |
c60c0f5f | 58 | |
69abc51c TJB |
59 | /* The PPC_FEATURE_* defines should be provided by <asm/cputable.h>. |
60 | If they aren't, we can provide them ourselves (their values are fixed | |
61 | because they are part of the kernel ABI). They are used in the AT_HWCAP | |
62 | entry of the AUXV. */ | |
f4d9bade UW |
63 | #ifndef PPC_FEATURE_CELL |
64 | #define PPC_FEATURE_CELL 0x00010000 | |
65 | #endif | |
b7622095 LM |
66 | #ifndef PPC_FEATURE_BOOKE |
67 | #define PPC_FEATURE_BOOKE 0x00008000 | |
68 | #endif | |
f04c6d38 TJB |
69 | #ifndef PPC_FEATURE_HAS_DFP |
70 | #define PPC_FEATURE_HAS_DFP 0x00000400 /* Decimal Floating Point. */ | |
69abc51c | 71 | #endif |
b7622095 | 72 | |
9abe5450 EZ |
73 | /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a |
74 | configure time check. Some older glibc's (for instance 2.2.1) | |
75 | don't have a specific powerpc version of ptrace.h, and fall back on | |
76 | a generic one. In such cases, sys/ptrace.h defines | |
77 | PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that | |
78 | ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and | |
79 | PTRACE_SETVRREGS to be. This also makes a configury check pretty | |
80 | much useless. */ | |
81 | ||
82 | /* These definitions should really come from the glibc header files, | |
83 | but Glibc doesn't know about the vrregs yet. */ | |
84 | #ifndef PTRACE_GETVRREGS | |
85 | #define PTRACE_GETVRREGS 18 | |
86 | #define PTRACE_SETVRREGS 19 | |
87 | #endif | |
88 | ||
604c2f83 LM |
89 | /* PTRACE requests for POWER7 VSX registers. */ |
90 | #ifndef PTRACE_GETVSXREGS | |
91 | #define PTRACE_GETVSXREGS 27 | |
92 | #define PTRACE_SETVSXREGS 28 | |
93 | #endif | |
01904826 JB |
94 | |
95 | /* Similarly for the ptrace requests for getting / setting the SPE | |
96 | registers (ev0 -- ev31, acc, and spefscr). See the description of | |
97 | gdb_evrregset_t for details. */ | |
98 | #ifndef PTRACE_GETEVRREGS | |
99 | #define PTRACE_GETEVRREGS 20 | |
100 | #define PTRACE_SETEVRREGS 21 | |
101 | #endif | |
102 | ||
6ffbb7ab TJB |
103 | /* Similarly for the hardware watchpoint support. These requests are used |
104 | when the BookE kernel interface is not available. */ | |
e0d24f8d WZ |
105 | #ifndef PTRACE_GET_DEBUGREG |
106 | #define PTRACE_GET_DEBUGREG 25 | |
107 | #endif | |
108 | #ifndef PTRACE_SET_DEBUGREG | |
109 | #define PTRACE_SET_DEBUGREG 26 | |
110 | #endif | |
111 | #ifndef PTRACE_GETSIGINFO | |
112 | #define PTRACE_GETSIGINFO 0x4202 | |
113 | #endif | |
01904826 | 114 | |
6ffbb7ab TJB |
115 | /* These requests are used when the BookE kernel interface is available. |
116 | It exposes the additional debug features of BookE processors, such as | |
117 | ranged breakpoints and watchpoints and hardware-accelerated condition | |
118 | evaluation. */ | |
119 | #ifndef PPC_PTRACE_GETHWDBGINFO | |
120 | ||
121 | /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the new BookE | |
122 | interface is not present in ptrace.h, so we'll have to pretty much include | |
123 | it all here so that the code at least compiles on older systems. */ | |
124 | #define PPC_PTRACE_GETHWDBGINFO 0x89 | |
125 | #define PPC_PTRACE_SETHWDEBUG 0x88 | |
126 | #define PPC_PTRACE_DELHWDEBUG 0x87 | |
127 | ||
128 | struct ppc_debug_info | |
129 | { | |
0df8b418 | 130 | uint32_t version; /* Only version 1 exists to date. */ |
6ffbb7ab TJB |
131 | uint32_t num_instruction_bps; |
132 | uint32_t num_data_bps; | |
133 | uint32_t num_condition_regs; | |
134 | uint32_t data_bp_alignment; | |
0df8b418 | 135 | uint32_t sizeof_condition; /* size of the DVC register. */ |
6ffbb7ab TJB |
136 | uint64_t features; |
137 | }; | |
138 | ||
139 | /* Features will have bits indicating whether there is support for: */ | |
140 | #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1 | |
141 | #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2 | |
142 | #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4 | |
143 | #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8 | |
144 | ||
145 | struct ppc_hw_breakpoint | |
146 | { | |
147 | uint32_t version; /* currently, version must be 1 */ | |
148 | uint32_t trigger_type; /* only some combinations allowed */ | |
149 | uint32_t addr_mode; /* address match mode */ | |
150 | uint32_t condition_mode; /* break/watchpoint condition flags */ | |
151 | uint64_t addr; /* break/watchpoint address */ | |
152 | uint64_t addr2; /* range end or mask */ | |
153 | uint64_t condition_value; /* contents of the DVC register */ | |
154 | }; | |
155 | ||
156 | /* Trigger type. */ | |
157 | #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1 | |
158 | #define PPC_BREAKPOINT_TRIGGER_READ 0x2 | |
159 | #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4 | |
160 | #define PPC_BREAKPOINT_TRIGGER_RW 0x6 | |
161 | ||
162 | /* Address mode. */ | |
163 | #define PPC_BREAKPOINT_MODE_EXACT 0x0 | |
164 | #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1 | |
165 | #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2 | |
166 | #define PPC_BREAKPOINT_MODE_MASK 0x3 | |
167 | ||
168 | /* Condition mode. */ | |
169 | #define PPC_BREAKPOINT_CONDITION_NONE 0x0 | |
170 | #define PPC_BREAKPOINT_CONDITION_AND 0x1 | |
171 | #define PPC_BREAKPOINT_CONDITION_EXACT 0x1 | |
172 | #define PPC_BREAKPOINT_CONDITION_OR 0x2 | |
173 | #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3 | |
174 | #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 | |
175 | #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16 | |
176 | #define PPC_BREAKPOINT_CONDITION_BE(n) \ | |
177 | (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT)) | |
178 | #endif /* PPC_PTRACE_GETHWDBGINFO */ | |
179 | ||
180 | ||
181 | ||
1dfe79e8 SDJ |
182 | /* Similarly for the general-purpose (gp0 -- gp31) |
183 | and floating-point registers (fp0 -- fp31). */ | |
184 | #ifndef PTRACE_GETREGS | |
185 | #define PTRACE_GETREGS 12 | |
186 | #endif | |
187 | #ifndef PTRACE_SETREGS | |
188 | #define PTRACE_SETREGS 13 | |
189 | #endif | |
190 | #ifndef PTRACE_GETFPREGS | |
191 | #define PTRACE_GETFPREGS 14 | |
192 | #endif | |
193 | #ifndef PTRACE_SETFPREGS | |
194 | #define PTRACE_SETFPREGS 15 | |
195 | #endif | |
196 | ||
9abe5450 EZ |
197 | /* This oddity is because the Linux kernel defines elf_vrregset_t as |
198 | an array of 33 16 bytes long elements. I.e. it leaves out vrsave. | |
199 | However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return | |
200 | the vrsave as an extra 4 bytes at the end. I opted for creating a | |
201 | flat array of chars, so that it is easier to manipulate for gdb. | |
202 | ||
203 | There are 32 vector registers 16 bytes longs, plus a VSCR register | |
204 | which is only 4 bytes long, but is fetched as a 16 bytes | |
0df8b418 | 205 | quantity. Up to here we have the elf_vrregset_t structure. |
9abe5450 EZ |
206 | Appended to this there is space for the VRSAVE register: 4 bytes. |
207 | Even though this vrsave register is not included in the regset | |
208 | typedef, it is handled by the ptrace requests. | |
209 | ||
210 | Note that GNU/Linux doesn't support little endian PPC hardware, | |
211 | therefore the offset at which the real value of the VSCR register | |
212 | is located will be always 12 bytes. | |
213 | ||
214 | The layout is like this (where x is the actual value of the vscr reg): */ | |
215 | ||
216 | /* *INDENT-OFF* */ | |
217 | /* | |
218 | |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| | |
219 | <-------> <-------><-------><-> | |
220 | VR0 VR31 VSCR VRSAVE | |
221 | */ | |
222 | /* *INDENT-ON* */ | |
223 | ||
224 | #define SIZEOF_VRREGS 33*16+4 | |
225 | ||
226 | typedef char gdb_vrregset_t[SIZEOF_VRREGS]; | |
227 | ||
604c2f83 LM |
228 | /* This is the layout of the POWER7 VSX registers and the way they overlap |
229 | with the existing FPR and VMX registers. | |
230 | ||
231 | VSR doubleword 0 VSR doubleword 1 | |
232 | ---------------------------------------------------------------- | |
233 | VSR[0] | FPR[0] | | | |
234 | ---------------------------------------------------------------- | |
235 | VSR[1] | FPR[1] | | | |
236 | ---------------------------------------------------------------- | |
237 | | ... | | | |
238 | | ... | | | |
239 | ---------------------------------------------------------------- | |
240 | VSR[30] | FPR[30] | | | |
241 | ---------------------------------------------------------------- | |
242 | VSR[31] | FPR[31] | | | |
243 | ---------------------------------------------------------------- | |
244 | VSR[32] | VR[0] | | |
245 | ---------------------------------------------------------------- | |
246 | VSR[33] | VR[1] | | |
247 | ---------------------------------------------------------------- | |
248 | | ... | | |
249 | | ... | | |
250 | ---------------------------------------------------------------- | |
251 | VSR[62] | VR[30] | | |
252 | ---------------------------------------------------------------- | |
253 | VSR[63] | VR[31] | | |
254 | ---------------------------------------------------------------- | |
255 | ||
256 | VSX has 64 128bit registers. The first 32 registers overlap with | |
257 | the FP registers (doubleword 0) and hence extend them with additional | |
258 | 64 bits (doubleword 1). The other 32 regs overlap with the VMX | |
259 | registers. */ | |
260 | #define SIZEOF_VSXREGS 32*8 | |
261 | ||
262 | typedef char gdb_vsxregset_t[SIZEOF_VSXREGS]; | |
01904826 | 263 | |
b021a221 | 264 | /* On PPC processors that support the Signal Processing Extension |
01904826 | 265 | (SPE) APU, the general-purpose registers are 64 bits long. |
411cb3f9 PG |
266 | However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER |
267 | ptrace calls only access the lower half of each register, to allow | |
268 | them to behave the same way they do on non-SPE systems. There's a | |
269 | separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that | |
270 | read and write the top halves of all the general-purpose registers | |
271 | at once, along with some SPE-specific registers. | |
01904826 JB |
272 | |
273 | GDB itself continues to claim the general-purpose registers are 32 | |
6ced10dd | 274 | bits long. It has unnamed raw registers that hold the upper halves |
b021a221 | 275 | of the gprs, and the full 64-bit SIMD views of the registers, |
6ced10dd JB |
276 | 'ev0' -- 'ev31', are pseudo-registers that splice the top and |
277 | bottom halves together. | |
01904826 JB |
278 | |
279 | This is the structure filled in by PTRACE_GETEVRREGS and written to | |
280 | the inferior's registers by PTRACE_SETEVRREGS. */ | |
281 | struct gdb_evrregset_t | |
282 | { | |
283 | unsigned long evr[32]; | |
284 | unsigned long long acc; | |
285 | unsigned long spefscr; | |
286 | }; | |
287 | ||
604c2f83 LM |
288 | /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and |
289 | PTRACE_SETVSXREGS requests, for reading and writing the VSX | |
290 | POWER7 registers 0 through 31. Zero if we've tried one of them and | |
291 | gotten an error. Note that VSX registers 32 through 63 overlap | |
292 | with VR registers 0 through 31. */ | |
293 | int have_ptrace_getsetvsxregs = 1; | |
01904826 JB |
294 | |
295 | /* Non-zero if our kernel may support the PTRACE_GETVRREGS and | |
296 | PTRACE_SETVRREGS requests, for reading and writing the Altivec | |
297 | registers. Zero if we've tried one of them and gotten an | |
298 | error. */ | |
9abe5450 EZ |
299 | int have_ptrace_getvrregs = 1; |
300 | ||
01904826 JB |
301 | /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and |
302 | PTRACE_SETEVRREGS requests, for reading and writing the SPE | |
303 | registers. Zero if we've tried one of them and gotten an | |
304 | error. */ | |
305 | int have_ptrace_getsetevrregs = 1; | |
306 | ||
1dfe79e8 SDJ |
307 | /* Non-zero if our kernel may support the PTRACE_GETREGS and |
308 | PTRACE_SETREGS requests, for reading and writing the | |
309 | general-purpose registers. Zero if we've tried one of | |
310 | them and gotten an error. */ | |
311 | int have_ptrace_getsetregs = 1; | |
312 | ||
313 | /* Non-zero if our kernel may support the PTRACE_GETFPREGS and | |
314 | PTRACE_SETFPREGS requests, for reading and writing the | |
315 | floating-pointers registers. Zero if we've tried one of | |
316 | them and gotten an error. */ | |
317 | int have_ptrace_getsetfpregs = 1; | |
318 | ||
16333c4f EZ |
319 | /* *INDENT-OFF* */ |
320 | /* registers layout, as presented by the ptrace interface: | |
321 | PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, | |
322 | PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15, | |
323 | PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23, | |
324 | PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31, | |
0df8b418 MS |
325 | PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, |
326 | PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14, | |
327 | PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, | |
328 | PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30, | |
329 | PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, | |
330 | PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46, | |
331 | PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, | |
332 | PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62, | |
16333c4f EZ |
333 | PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */ |
334 | /* *INDENT_ON * */ | |
c877c8e6 | 335 | |
45229ea4 | 336 | static int |
e101270f | 337 | ppc_register_u_addr (struct gdbarch *gdbarch, int regno) |
c877c8e6 | 338 | { |
16333c4f | 339 | int u_addr = -1; |
e101270f | 340 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
56d0d96a AC |
341 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
342 | interface, and not the wordsize of the program's ABI. */ | |
411cb3f9 | 343 | int wordsize = sizeof (long); |
16333c4f | 344 | |
0df8b418 | 345 | /* General purpose registers occupy 1 slot each in the buffer. */ |
8bf659e8 JB |
346 | if (regno >= tdep->ppc_gp0_regnum |
347 | && regno < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
26e75e5c | 348 | u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize); |
16333c4f | 349 | |
49ff75ad JB |
350 | /* Floating point regs: eight bytes each in both 32- and 64-bit |
351 | ptrace interfaces. Thus, two slots each in 32-bit interface, one | |
352 | slot each in 64-bit interface. */ | |
383f0f5b JB |
353 | if (tdep->ppc_fp0_regnum >= 0 |
354 | && regno >= tdep->ppc_fp0_regnum | |
366f009f JB |
355 | && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) |
356 | u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8); | |
16333c4f | 357 | |
0df8b418 | 358 | /* UISA special purpose registers: 1 slot each. */ |
e101270f | 359 | if (regno == gdbarch_pc_regnum (gdbarch)) |
49ff75ad | 360 | u_addr = PT_NIP * wordsize; |
dc5cfeb6 | 361 | if (regno == tdep->ppc_lr_regnum) |
49ff75ad | 362 | u_addr = PT_LNK * wordsize; |
dc5cfeb6 | 363 | if (regno == tdep->ppc_cr_regnum) |
49ff75ad | 364 | u_addr = PT_CCR * wordsize; |
dc5cfeb6 | 365 | if (regno == tdep->ppc_xer_regnum) |
49ff75ad | 366 | u_addr = PT_XER * wordsize; |
dc5cfeb6 | 367 | if (regno == tdep->ppc_ctr_regnum) |
49ff75ad | 368 | u_addr = PT_CTR * wordsize; |
f8c59253 | 369 | #ifdef PT_MQ |
dc5cfeb6 | 370 | if (regno == tdep->ppc_mq_regnum) |
49ff75ad | 371 | u_addr = PT_MQ * wordsize; |
f8c59253 | 372 | #endif |
dc5cfeb6 | 373 | if (regno == tdep->ppc_ps_regnum) |
49ff75ad | 374 | u_addr = PT_MSR * wordsize; |
7284e1be UW |
375 | if (regno == PPC_ORIG_R3_REGNUM) |
376 | u_addr = PT_ORIG_R3 * wordsize; | |
377 | if (regno == PPC_TRAP_REGNUM) | |
378 | u_addr = PT_TRAP * wordsize; | |
383f0f5b JB |
379 | if (tdep->ppc_fpscr_regnum >= 0 |
380 | && regno == tdep->ppc_fpscr_regnum) | |
8f135812 AC |
381 | { |
382 | /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the | |
383 | kernel headers incorrectly contained the 32-bit definition of | |
384 | PT_FPSCR. For the 32-bit definition, floating-point | |
385 | registers occupy two 32-bit "slots", and the FPSCR lives in | |
69abc51c | 386 | the second half of such a slot-pair (hence +1). For 64-bit, |
8f135812 AC |
387 | the FPSCR instead occupies the full 64-bit 2-word-slot and |
388 | hence no adjustment is necessary. Hack around this. */ | |
389 | if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1)) | |
390 | u_addr = (48 + 32) * wordsize; | |
69abc51c TJB |
391 | /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit |
392 | slot and not just its second word. The PT_FPSCR supplied when | |
393 | GDB is compiled as a 32-bit app doesn't reflect this. */ | |
394 | else if (wordsize == 4 && register_size (gdbarch, regno) == 8 | |
395 | && PT_FPSCR == (48 + 2*32 + 1)) | |
396 | u_addr = (48 + 2*32) * wordsize; | |
8f135812 AC |
397 | else |
398 | u_addr = PT_FPSCR * wordsize; | |
399 | } | |
16333c4f | 400 | return u_addr; |
c877c8e6 KB |
401 | } |
402 | ||
604c2f83 LM |
403 | /* The Linux kernel ptrace interface for POWER7 VSX registers uses the |
404 | registers set mechanism, as opposed to the interface for all the | |
405 | other registers, that stores/fetches each register individually. */ | |
406 | static void | |
407 | fetch_vsx_register (struct regcache *regcache, int tid, int regno) | |
408 | { | |
409 | int ret; | |
410 | gdb_vsxregset_t regs; | |
411 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
412 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
413 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
414 | ||
415 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
416 | if (ret < 0) | |
417 | { | |
418 | if (errno == EIO) | |
419 | { | |
420 | have_ptrace_getsetvsxregs = 0; | |
421 | return; | |
422 | } | |
423 | perror_with_name (_("Unable to fetch VSX register")); | |
424 | } | |
425 | ||
426 | regcache_raw_supply (regcache, regno, | |
427 | regs + (regno - tdep->ppc_vsr0_upper_regnum) | |
428 | * vsxregsize); | |
429 | } | |
430 | ||
9abe5450 EZ |
431 | /* The Linux kernel ptrace interface for AltiVec registers uses the |
432 | registers set mechanism, as opposed to the interface for all the | |
433 | other registers, that stores/fetches each register individually. */ | |
434 | static void | |
56be3814 | 435 | fetch_altivec_register (struct regcache *regcache, int tid, int regno) |
9abe5450 EZ |
436 | { |
437 | int ret; | |
438 | int offset = 0; | |
439 | gdb_vrregset_t regs; | |
40a6adc1 MD |
440 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
441 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
442 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); | |
9abe5450 EZ |
443 | |
444 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
445 | if (ret < 0) | |
446 | { | |
447 | if (errno == EIO) | |
448 | { | |
449 | have_ptrace_getvrregs = 0; | |
450 | return; | |
451 | } | |
e2e0b3e5 | 452 | perror_with_name (_("Unable to fetch AltiVec register")); |
9abe5450 EZ |
453 | } |
454 | ||
455 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
456 | long on the hardware. We deal only with the lower 4 bytes of the | |
457 | vector. VRSAVE is at the end of the array in a 4 bytes slot, so | |
458 | there is no need to define an offset for it. */ | |
459 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
40a6adc1 | 460 | offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
9abe5450 | 461 | |
56be3814 | 462 | regcache_raw_supply (regcache, regno, |
0df8b418 MS |
463 | regs + (regno |
464 | - tdep->ppc_vr0_regnum) * vrregsize + offset); | |
9abe5450 EZ |
465 | } |
466 | ||
01904826 JB |
467 | /* Fetch the top 32 bits of TID's general-purpose registers and the |
468 | SPE-specific registers, and place the results in EVRREGSET. If we | |
469 | don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with | |
470 | zeros. | |
471 | ||
472 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
473 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
474 | set_spe_registers. */ | |
475 | static void | |
476 | get_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
477 | { | |
478 | if (have_ptrace_getsetevrregs) | |
479 | { | |
480 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0) | |
481 | return; | |
482 | else | |
483 | { | |
484 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported; | |
485 | we just return zeros. */ | |
486 | if (errno == EIO) | |
487 | have_ptrace_getsetevrregs = 0; | |
488 | else | |
489 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 490 | perror_with_name (_("Unable to fetch SPE registers")); |
01904826 JB |
491 | } |
492 | } | |
493 | ||
494 | memset (evrregset, 0, sizeof (*evrregset)); | |
495 | } | |
496 | ||
6ced10dd JB |
497 | /* Supply values from TID for SPE-specific raw registers: the upper |
498 | halves of the GPRs, the accumulator, and the spefscr. REGNO must | |
499 | be the number of an upper half register, acc, spefscr, or -1 to | |
500 | supply the values of all registers. */ | |
01904826 | 501 | static void |
56be3814 | 502 | fetch_spe_register (struct regcache *regcache, int tid, int regno) |
01904826 | 503 | { |
40a6adc1 MD |
504 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
505 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
01904826 JB |
506 | struct gdb_evrregset_t evrregs; |
507 | ||
6ced10dd | 508 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 509 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 510 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 511 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 512 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 513 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
6ced10dd | 514 | |
01904826 JB |
515 | get_spe_registers (tid, &evrregs); |
516 | ||
6ced10dd | 517 | if (regno == -1) |
01904826 | 518 | { |
6ced10dd JB |
519 | int i; |
520 | ||
521 | for (i = 0; i < ppc_num_gprs; i++) | |
56be3814 | 522 | regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i, |
6ced10dd | 523 | &evrregs.evr[i]); |
01904826 | 524 | } |
6ced10dd JB |
525 | else if (tdep->ppc_ev0_upper_regnum <= regno |
526 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
56be3814 | 527 | regcache_raw_supply (regcache, regno, |
6ced10dd JB |
528 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
529 | ||
530 | if (regno == -1 | |
531 | || regno == tdep->ppc_acc_regnum) | |
56be3814 | 532 | regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc); |
6ced10dd JB |
533 | |
534 | if (regno == -1 | |
535 | || regno == tdep->ppc_spefscr_regnum) | |
56be3814 | 536 | regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum, |
6ced10dd | 537 | &evrregs.spefscr); |
01904826 JB |
538 | } |
539 | ||
45229ea4 | 540 | static void |
56be3814 | 541 | fetch_register (struct regcache *regcache, int tid, int regno) |
45229ea4 | 542 | { |
40a6adc1 MD |
543 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
544 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
45229ea4 | 545 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 546 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
4a19ea35 | 547 | int bytes_transferred; |
0df8b418 | 548 | unsigned int offset; /* Offset of registers within the u area. */ |
e362b510 | 549 | gdb_byte buf[MAX_REGISTER_SIZE]; |
45229ea4 | 550 | |
be8626e0 | 551 | if (altivec_register_p (gdbarch, regno)) |
9abe5450 EZ |
552 | { |
553 | /* If this is the first time through, or if it is not the first | |
554 | time through, and we have comfirmed that there is kernel | |
555 | support for such a ptrace request, then go and fetch the | |
556 | register. */ | |
557 | if (have_ptrace_getvrregs) | |
558 | { | |
56be3814 | 559 | fetch_altivec_register (regcache, tid, regno); |
9abe5450 EZ |
560 | return; |
561 | } | |
562 | /* If we have discovered that there is no ptrace support for | |
563 | AltiVec registers, fall through and return zeroes, because | |
564 | regaddr will be -1 in this case. */ | |
565 | } | |
604c2f83 LM |
566 | if (vsx_register_p (gdbarch, regno)) |
567 | { | |
568 | if (have_ptrace_getsetvsxregs) | |
569 | { | |
570 | fetch_vsx_register (regcache, tid, regno); | |
571 | return; | |
572 | } | |
573 | } | |
be8626e0 | 574 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 575 | { |
56be3814 | 576 | fetch_spe_register (regcache, tid, regno); |
01904826 JB |
577 | return; |
578 | } | |
9abe5450 | 579 | |
45229ea4 EZ |
580 | if (regaddr == -1) |
581 | { | |
40a6adc1 | 582 | memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ |
56be3814 | 583 | regcache_raw_supply (regcache, regno, buf); |
45229ea4 EZ |
584 | return; |
585 | } | |
586 | ||
411cb3f9 | 587 | /* Read the raw register using sizeof(long) sized chunks. On a |
56d0d96a AC |
588 | 32-bit platform, 64-bit floating-point registers will require two |
589 | transfers. */ | |
4a19ea35 | 590 | for (bytes_transferred = 0; |
40a6adc1 | 591 | bytes_transferred < register_size (gdbarch, regno); |
411cb3f9 | 592 | bytes_transferred += sizeof (long)) |
45229ea4 | 593 | { |
11fde611 JK |
594 | long l; |
595 | ||
45229ea4 | 596 | errno = 0; |
11fde611 | 597 | l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); |
411cb3f9 | 598 | regaddr += sizeof (long); |
45229ea4 EZ |
599 | if (errno != 0) |
600 | { | |
bc97b3ba | 601 | char message[128]; |
8c042590 PM |
602 | xsnprintf (message, sizeof (message), "reading register %s (#%d)", |
603 | gdbarch_register_name (gdbarch, regno), regno); | |
bc97b3ba | 604 | perror_with_name (message); |
45229ea4 | 605 | } |
11fde611 | 606 | memcpy (&buf[bytes_transferred], &l, sizeof (l)); |
45229ea4 | 607 | } |
56d0d96a | 608 | |
4a19ea35 JB |
609 | /* Now supply the register. Keep in mind that the regcache's idea |
610 | of the register's size may not be a multiple of sizeof | |
411cb3f9 | 611 | (long). */ |
40a6adc1 | 612 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
4a19ea35 JB |
613 | { |
614 | /* Little-endian values are always found at the left end of the | |
615 | bytes transferred. */ | |
56be3814 | 616 | regcache_raw_supply (regcache, regno, buf); |
4a19ea35 | 617 | } |
40a6adc1 | 618 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
619 | { |
620 | /* Big-endian values are found at the right end of the bytes | |
621 | transferred. */ | |
40a6adc1 | 622 | size_t padding = (bytes_transferred - register_size (gdbarch, regno)); |
56be3814 | 623 | regcache_raw_supply (regcache, regno, buf + padding); |
4a19ea35 JB |
624 | } |
625 | else | |
a44bddec | 626 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 627 | _("fetch_register: unexpected byte order: %d"), |
40a6adc1 | 628 | gdbarch_byte_order (gdbarch)); |
45229ea4 EZ |
629 | } |
630 | ||
604c2f83 LM |
631 | static void |
632 | supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) | |
633 | { | |
634 | int i; | |
635 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
636 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
637 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
638 | ||
639 | for (i = 0; i < ppc_num_vshrs; i++) | |
640 | { | |
641 | regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i, | |
642 | *vsxregsetp + i * vsxregsize); | |
643 | } | |
644 | } | |
645 | ||
9abe5450 | 646 | static void |
56be3814 | 647 | supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
9abe5450 EZ |
648 | { |
649 | int i; | |
40a6adc1 MD |
650 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
651 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9abe5450 | 652 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; |
40a6adc1 MD |
653 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
654 | int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
655 | |
656 | for (i = 0; i < num_of_vrregs; i++) | |
657 | { | |
658 | /* The last 2 registers of this set are only 32 bit long, not | |
659 | 128. However an offset is necessary only for VSCR because it | |
660 | occupies a whole vector, while VRSAVE occupies a full 4 bytes | |
661 | slot. */ | |
662 | if (i == (num_of_vrregs - 2)) | |
56be3814 | 663 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
23a6d369 | 664 | *vrregsetp + i * vrregsize + offset); |
9abe5450 | 665 | else |
56be3814 | 666 | regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, |
23a6d369 | 667 | *vrregsetp + i * vrregsize); |
9abe5450 EZ |
668 | } |
669 | } | |
670 | ||
604c2f83 LM |
671 | static void |
672 | fetch_vsx_registers (struct regcache *regcache, int tid) | |
673 | { | |
674 | int ret; | |
675 | gdb_vsxregset_t regs; | |
676 | ||
677 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
678 | if (ret < 0) | |
679 | { | |
680 | if (errno == EIO) | |
681 | { | |
682 | have_ptrace_getsetvsxregs = 0; | |
683 | return; | |
684 | } | |
685 | perror_with_name (_("Unable to fetch VSX registers")); | |
686 | } | |
687 | supply_vsxregset (regcache, ®s); | |
688 | } | |
689 | ||
9abe5450 | 690 | static void |
56be3814 | 691 | fetch_altivec_registers (struct regcache *regcache, int tid) |
9abe5450 EZ |
692 | { |
693 | int ret; | |
694 | gdb_vrregset_t regs; | |
695 | ||
696 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
697 | if (ret < 0) | |
698 | { | |
699 | if (errno == EIO) | |
700 | { | |
701 | have_ptrace_getvrregs = 0; | |
702 | return; | |
703 | } | |
e2e0b3e5 | 704 | perror_with_name (_("Unable to fetch AltiVec registers")); |
9abe5450 | 705 | } |
56be3814 | 706 | supply_vrregset (regcache, ®s); |
9abe5450 EZ |
707 | } |
708 | ||
1dfe79e8 SDJ |
709 | /* This function actually issues the request to ptrace, telling |
710 | it to get all general-purpose registers and put them into the | |
711 | specified regset. | |
712 | ||
713 | If the ptrace request does not exist, this function returns 0 | |
714 | and properly sets the have_ptrace_* flag. If the request fails, | |
715 | this function calls perror_with_name. Otherwise, if the request | |
716 | succeeds, then the regcache gets filled and 1 is returned. */ | |
717 | static int | |
718 | fetch_all_gp_regs (struct regcache *regcache, int tid) | |
719 | { | |
720 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
721 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
722 | gdb_gregset_t gregset; | |
723 | ||
724 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
725 | { | |
726 | if (errno == EIO) | |
727 | { | |
728 | have_ptrace_getsetregs = 0; | |
729 | return 0; | |
730 | } | |
731 | perror_with_name (_("Couldn't get general-purpose registers.")); | |
732 | } | |
733 | ||
734 | supply_gregset (regcache, (const gdb_gregset_t *) &gregset); | |
735 | ||
736 | return 1; | |
737 | } | |
738 | ||
739 | /* This is a wrapper for the fetch_all_gp_regs function. It is | |
740 | responsible for verifying if this target has the ptrace request | |
741 | that can be used to fetch all general-purpose registers at one | |
742 | shot. If it doesn't, then we should fetch them using the | |
743 | old-fashioned way, which is to iterate over the registers and | |
744 | request them one by one. */ | |
745 | static void | |
746 | fetch_gp_regs (struct regcache *regcache, int tid) | |
747 | { | |
748 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
749 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
750 | int i; | |
751 | ||
752 | if (have_ptrace_getsetregs) | |
753 | if (fetch_all_gp_regs (regcache, tid)) | |
754 | return; | |
755 | ||
756 | /* If we've hit this point, it doesn't really matter which | |
757 | architecture we are using. We just need to read the | |
758 | registers in the "old-fashioned way". */ | |
759 | for (i = 0; i < ppc_num_gprs; i++) | |
760 | fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i); | |
761 | } | |
762 | ||
763 | /* This function actually issues the request to ptrace, telling | |
764 | it to get all floating-point registers and put them into the | |
765 | specified regset. | |
766 | ||
767 | If the ptrace request does not exist, this function returns 0 | |
768 | and properly sets the have_ptrace_* flag. If the request fails, | |
769 | this function calls perror_with_name. Otherwise, if the request | |
770 | succeeds, then the regcache gets filled and 1 is returned. */ | |
771 | static int | |
772 | fetch_all_fp_regs (struct regcache *regcache, int tid) | |
773 | { | |
774 | gdb_fpregset_t fpregs; | |
775 | ||
776 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
777 | { | |
778 | if (errno == EIO) | |
779 | { | |
780 | have_ptrace_getsetfpregs = 0; | |
781 | return 0; | |
782 | } | |
783 | perror_with_name (_("Couldn't get floating-point registers.")); | |
784 | } | |
785 | ||
786 | supply_fpregset (regcache, (const gdb_fpregset_t *) &fpregs); | |
787 | ||
788 | return 1; | |
789 | } | |
790 | ||
791 | /* This is a wrapper for the fetch_all_fp_regs function. It is | |
792 | responsible for verifying if this target has the ptrace request | |
793 | that can be used to fetch all floating-point registers at one | |
794 | shot. If it doesn't, then we should fetch them using the | |
795 | old-fashioned way, which is to iterate over the registers and | |
796 | request them one by one. */ | |
797 | static void | |
798 | fetch_fp_regs (struct regcache *regcache, int tid) | |
799 | { | |
800 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
801 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
802 | int i; | |
803 | ||
804 | if (have_ptrace_getsetfpregs) | |
805 | if (fetch_all_fp_regs (regcache, tid)) | |
806 | return; | |
807 | ||
808 | /* If we've hit this point, it doesn't really matter which | |
809 | architecture we are using. We just need to read the | |
810 | registers in the "old-fashioned way". */ | |
811 | for (i = 0; i < ppc_num_fprs; i++) | |
812 | fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
813 | } | |
814 | ||
45229ea4 | 815 | static void |
56be3814 | 816 | fetch_ppc_registers (struct regcache *regcache, int tid) |
45229ea4 EZ |
817 | { |
818 | int i; | |
40a6adc1 MD |
819 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
820 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9abe5450 | 821 | |
1dfe79e8 | 822 | fetch_gp_regs (regcache, tid); |
32b99774 | 823 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 824 | fetch_fp_regs (regcache, tid); |
40a6adc1 | 825 | fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 826 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 827 | fetch_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 828 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 829 | fetch_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 830 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 831 | fetch_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 832 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 833 | fetch_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 834 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 835 | fetch_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 836 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 837 | fetch_register (regcache, tid, tdep->ppc_mq_regnum); |
7284e1be UW |
838 | if (ppc_linux_trap_reg_p (gdbarch)) |
839 | { | |
840 | fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
841 | fetch_register (regcache, tid, PPC_TRAP_REGNUM); | |
842 | } | |
32b99774 | 843 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 844 | fetch_register (regcache, tid, tdep->ppc_fpscr_regnum); |
9abe5450 EZ |
845 | if (have_ptrace_getvrregs) |
846 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
56be3814 | 847 | fetch_altivec_registers (regcache, tid); |
604c2f83 LM |
848 | if (have_ptrace_getsetvsxregs) |
849 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
850 | fetch_vsx_registers (regcache, tid); | |
6ced10dd | 851 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 852 | fetch_spe_register (regcache, tid, -1); |
45229ea4 EZ |
853 | } |
854 | ||
855 | /* Fetch registers from the child process. Fetch all registers if | |
856 | regno == -1, otherwise fetch all general registers or all floating | |
857 | point registers depending upon the value of regno. */ | |
10d6c8cd | 858 | static void |
28439f5e PA |
859 | ppc_linux_fetch_inferior_registers (struct target_ops *ops, |
860 | struct regcache *regcache, int regno) | |
45229ea4 | 861 | { |
0df8b418 | 862 | /* Overload thread id onto process id. */ |
05f13b9c EZ |
863 | int tid = TIDGET (inferior_ptid); |
864 | ||
0df8b418 | 865 | /* No thread id, just use process id. */ |
05f13b9c EZ |
866 | if (tid == 0) |
867 | tid = PIDGET (inferior_ptid); | |
868 | ||
9abe5450 | 869 | if (regno == -1) |
56be3814 | 870 | fetch_ppc_registers (regcache, tid); |
45229ea4 | 871 | else |
56be3814 | 872 | fetch_register (regcache, tid, regno); |
45229ea4 EZ |
873 | } |
874 | ||
0df8b418 | 875 | /* Store one VSX register. */ |
604c2f83 LM |
876 | static void |
877 | store_vsx_register (const struct regcache *regcache, int tid, int regno) | |
878 | { | |
879 | int ret; | |
880 | gdb_vsxregset_t regs; | |
881 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
882 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
883 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
884 | ||
9fe70b4f | 885 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); |
604c2f83 LM |
886 | if (ret < 0) |
887 | { | |
888 | if (errno == EIO) | |
889 | { | |
890 | have_ptrace_getsetvsxregs = 0; | |
891 | return; | |
892 | } | |
893 | perror_with_name (_("Unable to fetch VSX register")); | |
894 | } | |
895 | ||
896 | regcache_raw_collect (regcache, regno, regs + | |
897 | (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize); | |
898 | ||
899 | ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); | |
900 | if (ret < 0) | |
901 | perror_with_name (_("Unable to store VSX register")); | |
902 | } | |
903 | ||
0df8b418 | 904 | /* Store one register. */ |
9abe5450 | 905 | static void |
56be3814 | 906 | store_altivec_register (const struct regcache *regcache, int tid, int regno) |
9abe5450 EZ |
907 | { |
908 | int ret; | |
909 | int offset = 0; | |
910 | gdb_vrregset_t regs; | |
40a6adc1 MD |
911 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
912 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
913 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); | |
9abe5450 EZ |
914 | |
915 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
916 | if (ret < 0) | |
917 | { | |
918 | if (errno == EIO) | |
919 | { | |
920 | have_ptrace_getvrregs = 0; | |
921 | return; | |
922 | } | |
e2e0b3e5 | 923 | perror_with_name (_("Unable to fetch AltiVec register")); |
9abe5450 EZ |
924 | } |
925 | ||
926 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
927 | long on the hardware. */ | |
928 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
40a6adc1 | 929 | offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); |
9abe5450 | 930 | |
56be3814 | 931 | regcache_raw_collect (regcache, regno, |
0df8b418 MS |
932 | regs + (regno |
933 | - tdep->ppc_vr0_regnum) * vrregsize + offset); | |
9abe5450 EZ |
934 | |
935 | ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); | |
936 | if (ret < 0) | |
e2e0b3e5 | 937 | perror_with_name (_("Unable to store AltiVec register")); |
9abe5450 EZ |
938 | } |
939 | ||
01904826 JB |
940 | /* Assuming TID referrs to an SPE process, set the top halves of TID's |
941 | general-purpose registers and its SPE-specific registers to the | |
942 | values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do | |
943 | nothing. | |
944 | ||
945 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
946 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
947 | get_spe_registers. */ | |
948 | static void | |
949 | set_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
950 | { | |
951 | if (have_ptrace_getsetevrregs) | |
952 | { | |
953 | if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0) | |
954 | return; | |
955 | else | |
956 | { | |
957 | /* EIO means that the PTRACE_SETEVRREGS request isn't | |
958 | supported; we fail silently, and don't try the call | |
959 | again. */ | |
960 | if (errno == EIO) | |
961 | have_ptrace_getsetevrregs = 0; | |
962 | else | |
963 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 964 | perror_with_name (_("Unable to set SPE registers")); |
01904826 JB |
965 | } |
966 | } | |
967 | } | |
968 | ||
6ced10dd JB |
969 | /* Write GDB's value for the SPE-specific raw register REGNO to TID. |
970 | If REGNO is -1, write the values of all the SPE-specific | |
971 | registers. */ | |
01904826 | 972 | static void |
56be3814 | 973 | store_spe_register (const struct regcache *regcache, int tid, int regno) |
01904826 | 974 | { |
40a6adc1 MD |
975 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
976 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
01904826 JB |
977 | struct gdb_evrregset_t evrregs; |
978 | ||
6ced10dd | 979 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 980 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 981 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 982 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 983 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 984 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
01904826 | 985 | |
6ced10dd JB |
986 | if (regno == -1) |
987 | /* Since we're going to write out every register, the code below | |
988 | should store to every field of evrregs; if that doesn't happen, | |
989 | make it obvious by initializing it with suspicious values. */ | |
990 | memset (&evrregs, 42, sizeof (evrregs)); | |
991 | else | |
992 | /* We can only read and write the entire EVR register set at a | |
993 | time, so to write just a single register, we do a | |
994 | read-modify-write maneuver. */ | |
995 | get_spe_registers (tid, &evrregs); | |
996 | ||
997 | if (regno == -1) | |
01904826 | 998 | { |
6ced10dd JB |
999 | int i; |
1000 | ||
1001 | for (i = 0; i < ppc_num_gprs; i++) | |
56be3814 | 1002 | regcache_raw_collect (regcache, |
6ced10dd JB |
1003 | tdep->ppc_ev0_upper_regnum + i, |
1004 | &evrregs.evr[i]); | |
01904826 | 1005 | } |
6ced10dd JB |
1006 | else if (tdep->ppc_ev0_upper_regnum <= regno |
1007 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
56be3814 | 1008 | regcache_raw_collect (regcache, regno, |
6ced10dd JB |
1009 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); |
1010 | ||
1011 | if (regno == -1 | |
1012 | || regno == tdep->ppc_acc_regnum) | |
56be3814 | 1013 | regcache_raw_collect (regcache, |
6ced10dd JB |
1014 | tdep->ppc_acc_regnum, |
1015 | &evrregs.acc); | |
1016 | ||
1017 | if (regno == -1 | |
1018 | || regno == tdep->ppc_spefscr_regnum) | |
56be3814 | 1019 | regcache_raw_collect (regcache, |
6ced10dd JB |
1020 | tdep->ppc_spefscr_regnum, |
1021 | &evrregs.spefscr); | |
01904826 JB |
1022 | |
1023 | /* Write back the modified register set. */ | |
1024 | set_spe_registers (tid, &evrregs); | |
1025 | } | |
1026 | ||
45229ea4 | 1027 | static void |
56be3814 | 1028 | store_register (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 1029 | { |
40a6adc1 MD |
1030 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1031 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
45229ea4 | 1032 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 1033 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
52f0bd74 | 1034 | int i; |
4a19ea35 | 1035 | size_t bytes_to_transfer; |
e362b510 | 1036 | gdb_byte buf[MAX_REGISTER_SIZE]; |
45229ea4 | 1037 | |
be8626e0 | 1038 | if (altivec_register_p (gdbarch, regno)) |
45229ea4 | 1039 | { |
56be3814 | 1040 | store_altivec_register (regcache, tid, regno); |
45229ea4 EZ |
1041 | return; |
1042 | } | |
604c2f83 LM |
1043 | if (vsx_register_p (gdbarch, regno)) |
1044 | { | |
1045 | store_vsx_register (regcache, tid, regno); | |
1046 | return; | |
1047 | } | |
be8626e0 | 1048 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 1049 | { |
56be3814 | 1050 | store_spe_register (regcache, tid, regno); |
01904826 JB |
1051 | return; |
1052 | } | |
45229ea4 | 1053 | |
9abe5450 EZ |
1054 | if (regaddr == -1) |
1055 | return; | |
1056 | ||
4a19ea35 JB |
1057 | /* First collect the register. Keep in mind that the regcache's |
1058 | idea of the register's size may not be a multiple of sizeof | |
411cb3f9 | 1059 | (long). */ |
56d0d96a | 1060 | memset (buf, 0, sizeof buf); |
40a6adc1 MD |
1061 | bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); |
1062 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) | |
4a19ea35 JB |
1063 | { |
1064 | /* Little-endian values always sit at the left end of the buffer. */ | |
56be3814 | 1065 | regcache_raw_collect (regcache, regno, buf); |
4a19ea35 | 1066 | } |
40a6adc1 | 1067 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
1068 | { |
1069 | /* Big-endian values sit at the right end of the buffer. */ | |
40a6adc1 | 1070 | size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); |
56be3814 | 1071 | regcache_raw_collect (regcache, regno, buf + padding); |
4a19ea35 JB |
1072 | } |
1073 | ||
411cb3f9 | 1074 | for (i = 0; i < bytes_to_transfer; i += sizeof (long)) |
45229ea4 | 1075 | { |
11fde611 JK |
1076 | long l; |
1077 | ||
1078 | memcpy (&l, &buf[i], sizeof (l)); | |
45229ea4 | 1079 | errno = 0; |
11fde611 | 1080 | ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l); |
411cb3f9 | 1081 | regaddr += sizeof (long); |
e3f36dbd KB |
1082 | |
1083 | if (errno == EIO | |
7284e1be UW |
1084 | && (regno == tdep->ppc_fpscr_regnum |
1085 | || regno == PPC_ORIG_R3_REGNUM | |
1086 | || regno == PPC_TRAP_REGNUM)) | |
e3f36dbd | 1087 | { |
7284e1be UW |
1088 | /* Some older kernel versions don't allow fpscr, orig_r3 |
1089 | or trap to be written. */ | |
e3f36dbd KB |
1090 | continue; |
1091 | } | |
1092 | ||
45229ea4 EZ |
1093 | if (errno != 0) |
1094 | { | |
bc97b3ba | 1095 | char message[128]; |
8c042590 PM |
1096 | xsnprintf (message, sizeof (message), "writing register %s (#%d)", |
1097 | gdbarch_register_name (gdbarch, regno), regno); | |
bc97b3ba | 1098 | perror_with_name (message); |
45229ea4 EZ |
1099 | } |
1100 | } | |
1101 | } | |
1102 | ||
604c2f83 LM |
1103 | static void |
1104 | fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) | |
1105 | { | |
1106 | int i; | |
1107 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
1108 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1109 | int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); | |
1110 | ||
1111 | for (i = 0; i < ppc_num_vshrs; i++) | |
1112 | regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i, | |
1113 | *vsxregsetp + i * vsxregsize); | |
1114 | } | |
1115 | ||
9abe5450 | 1116 | static void |
56be3814 | 1117 | fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp) |
9abe5450 EZ |
1118 | { |
1119 | int i; | |
40a6adc1 MD |
1120 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1121 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9abe5450 | 1122 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; |
40a6adc1 MD |
1123 | int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); |
1124 | int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
1125 | |
1126 | for (i = 0; i < num_of_vrregs; i++) | |
1127 | { | |
1128 | /* The last 2 registers of this set are only 32 bit long, not | |
1129 | 128, but only VSCR is fetched as a 16 bytes quantity. */ | |
1130 | if (i == (num_of_vrregs - 2)) | |
56be3814 | 1131 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
822c9732 | 1132 | *vrregsetp + i * vrregsize + offset); |
9abe5450 | 1133 | else |
56be3814 | 1134 | regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, |
822c9732 | 1135 | *vrregsetp + i * vrregsize); |
9abe5450 EZ |
1136 | } |
1137 | } | |
1138 | ||
604c2f83 LM |
1139 | static void |
1140 | store_vsx_registers (const struct regcache *regcache, int tid) | |
1141 | { | |
1142 | int ret; | |
1143 | gdb_vsxregset_t regs; | |
1144 | ||
1145 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
1146 | if (ret < 0) | |
1147 | { | |
1148 | if (errno == EIO) | |
1149 | { | |
1150 | have_ptrace_getsetvsxregs = 0; | |
1151 | return; | |
1152 | } | |
1153 | perror_with_name (_("Couldn't get VSX registers")); | |
1154 | } | |
1155 | ||
1156 | fill_vsxregset (regcache, ®s); | |
1157 | ||
1158 | if (ptrace (PTRACE_SETVSXREGS, tid, 0, ®s) < 0) | |
1159 | perror_with_name (_("Couldn't write VSX registers")); | |
1160 | } | |
1161 | ||
9abe5450 | 1162 | static void |
56be3814 | 1163 | store_altivec_registers (const struct regcache *regcache, int tid) |
9abe5450 EZ |
1164 | { |
1165 | int ret; | |
1166 | gdb_vrregset_t regs; | |
1167 | ||
0897f59b | 1168 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); |
9abe5450 EZ |
1169 | if (ret < 0) |
1170 | { | |
1171 | if (errno == EIO) | |
1172 | { | |
1173 | have_ptrace_getvrregs = 0; | |
1174 | return; | |
1175 | } | |
e2e0b3e5 | 1176 | perror_with_name (_("Couldn't get AltiVec registers")); |
9abe5450 EZ |
1177 | } |
1178 | ||
56be3814 | 1179 | fill_vrregset (regcache, ®s); |
9abe5450 | 1180 | |
0897f59b | 1181 | if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0) |
e2e0b3e5 | 1182 | perror_with_name (_("Couldn't write AltiVec registers")); |
9abe5450 EZ |
1183 | } |
1184 | ||
1dfe79e8 SDJ |
1185 | /* This function actually issues the request to ptrace, telling |
1186 | it to store all general-purpose registers present in the specified | |
1187 | regset. | |
1188 | ||
1189 | If the ptrace request does not exist, this function returns 0 | |
1190 | and properly sets the have_ptrace_* flag. If the request fails, | |
1191 | this function calls perror_with_name. Otherwise, if the request | |
1192 | succeeds, then the regcache is stored and 1 is returned. */ | |
1193 | static int | |
1194 | store_all_gp_regs (const struct regcache *regcache, int tid, int regno) | |
1195 | { | |
1196 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
1197 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1198 | gdb_gregset_t gregset; | |
1199 | ||
1200 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
1201 | { | |
1202 | if (errno == EIO) | |
1203 | { | |
1204 | have_ptrace_getsetregs = 0; | |
1205 | return 0; | |
1206 | } | |
1207 | perror_with_name (_("Couldn't get general-purpose registers.")); | |
1208 | } | |
1209 | ||
1210 | fill_gregset (regcache, &gregset, regno); | |
1211 | ||
1212 | if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0) | |
1213 | { | |
1214 | if (errno == EIO) | |
1215 | { | |
1216 | have_ptrace_getsetregs = 0; | |
1217 | return 0; | |
1218 | } | |
1219 | perror_with_name (_("Couldn't set general-purpose registers.")); | |
1220 | } | |
1221 | ||
1222 | return 1; | |
1223 | } | |
1224 | ||
1225 | /* This is a wrapper for the store_all_gp_regs function. It is | |
1226 | responsible for verifying if this target has the ptrace request | |
1227 | that can be used to store all general-purpose registers at one | |
1228 | shot. If it doesn't, then we should store them using the | |
1229 | old-fashioned way, which is to iterate over the registers and | |
1230 | store them one by one. */ | |
45229ea4 | 1231 | static void |
1dfe79e8 | 1232 | store_gp_regs (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 1233 | { |
40a6adc1 MD |
1234 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1235 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1dfe79e8 SDJ |
1236 | int i; |
1237 | ||
1238 | if (have_ptrace_getsetregs) | |
1239 | if (store_all_gp_regs (regcache, tid, regno)) | |
1240 | return; | |
1241 | ||
1242 | /* If we hit this point, it doesn't really matter which | |
1243 | architecture we are using. We just need to store the | |
1244 | registers in the "old-fashioned way". */ | |
6ced10dd | 1245 | for (i = 0; i < ppc_num_gprs; i++) |
56be3814 | 1246 | store_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
1dfe79e8 SDJ |
1247 | } |
1248 | ||
1249 | /* This function actually issues the request to ptrace, telling | |
1250 | it to store all floating-point registers present in the specified | |
1251 | regset. | |
1252 | ||
1253 | If the ptrace request does not exist, this function returns 0 | |
1254 | and properly sets the have_ptrace_* flag. If the request fails, | |
1255 | this function calls perror_with_name. Otherwise, if the request | |
1256 | succeeds, then the regcache is stored and 1 is returned. */ | |
1257 | static int | |
1258 | store_all_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1259 | { | |
1260 | gdb_fpregset_t fpregs; | |
1261 | ||
1262 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1263 | { | |
1264 | if (errno == EIO) | |
1265 | { | |
1266 | have_ptrace_getsetfpregs = 0; | |
1267 | return 0; | |
1268 | } | |
1269 | perror_with_name (_("Couldn't get floating-point registers.")); | |
1270 | } | |
1271 | ||
1272 | fill_fpregset (regcache, &fpregs, regno); | |
1273 | ||
1274 | if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1275 | { | |
1276 | if (errno == EIO) | |
1277 | { | |
1278 | have_ptrace_getsetfpregs = 0; | |
1279 | return 0; | |
1280 | } | |
1281 | perror_with_name (_("Couldn't set floating-point registers.")); | |
1282 | } | |
1283 | ||
1284 | return 1; | |
1285 | } | |
1286 | ||
1287 | /* This is a wrapper for the store_all_fp_regs function. It is | |
1288 | responsible for verifying if this target has the ptrace request | |
1289 | that can be used to store all floating-point registers at one | |
1290 | shot. If it doesn't, then we should store them using the | |
1291 | old-fashioned way, which is to iterate over the registers and | |
1292 | store them one by one. */ | |
1293 | static void | |
1294 | store_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1295 | { | |
1296 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
1297 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1298 | int i; | |
1299 | ||
1300 | if (have_ptrace_getsetfpregs) | |
1301 | if (store_all_fp_regs (regcache, tid, regno)) | |
1302 | return; | |
1303 | ||
1304 | /* If we hit this point, it doesn't really matter which | |
1305 | architecture we are using. We just need to store the | |
1306 | registers in the "old-fashioned way". */ | |
1307 | for (i = 0; i < ppc_num_fprs; i++) | |
1308 | store_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
1309 | } | |
1310 | ||
1311 | static void | |
1312 | store_ppc_registers (const struct regcache *regcache, int tid) | |
1313 | { | |
1314 | int i; | |
1315 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
1316 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1317 | ||
1318 | store_gp_regs (regcache, tid, -1); | |
32b99774 | 1319 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 1320 | store_fp_regs (regcache, tid, -1); |
40a6adc1 | 1321 | store_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 1322 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 1323 | store_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 1324 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 1325 | store_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 1326 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 1327 | store_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 1328 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 1329 | store_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 1330 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 1331 | store_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 1332 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 1333 | store_register (regcache, tid, tdep->ppc_mq_regnum); |
32b99774 | 1334 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 1335 | store_register (regcache, tid, tdep->ppc_fpscr_regnum); |
7284e1be UW |
1336 | if (ppc_linux_trap_reg_p (gdbarch)) |
1337 | { | |
1338 | store_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
1339 | store_register (regcache, tid, PPC_TRAP_REGNUM); | |
1340 | } | |
9abe5450 EZ |
1341 | if (have_ptrace_getvrregs) |
1342 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
56be3814 | 1343 | store_altivec_registers (regcache, tid); |
604c2f83 LM |
1344 | if (have_ptrace_getsetvsxregs) |
1345 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
1346 | store_vsx_registers (regcache, tid); | |
6ced10dd | 1347 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 1348 | store_spe_register (regcache, tid, -1); |
45229ea4 EZ |
1349 | } |
1350 | ||
6ffbb7ab | 1351 | /* Fetch the AT_HWCAP entry from the aux vector. */ |
b261e0c5 UW |
1352 | static unsigned long |
1353 | ppc_linux_get_hwcap (void) | |
6ffbb7ab TJB |
1354 | { |
1355 | CORE_ADDR field; | |
1356 | ||
1357 | if (target_auxv_search (¤t_target, AT_HWCAP, &field)) | |
1358 | return (unsigned long) field; | |
1359 | ||
1360 | return 0; | |
1361 | } | |
1362 | ||
1363 | /* The cached DABR value, to install in new threads. | |
1364 | This variable is used when we are dealing with non-BookE | |
1365 | processors. */ | |
1366 | static long saved_dabr_value; | |
1367 | ||
1368 | /* Global structure that will store information about the available | |
1369 | features on this BookE processor. */ | |
1370 | static struct ppc_debug_info booke_debug_info; | |
1371 | ||
1372 | /* Global variable that holds the maximum number of slots that the | |
1373 | kernel will use. This is only used when the processor is BookE. */ | |
1374 | static size_t max_slots_number = 0; | |
1375 | ||
1376 | struct hw_break_tuple | |
1377 | { | |
1378 | long slot; | |
1379 | struct ppc_hw_breakpoint *hw_break; | |
1380 | }; | |
1381 | ||
1382 | /* This is an internal VEC created to store information about *points inserted | |
1383 | for each thread. This is used for BookE processors. */ | |
1384 | typedef struct thread_points | |
1385 | { | |
1386 | /* The TID to which this *point relates. */ | |
1387 | int tid; | |
1388 | /* Information about the *point, such as its address, type, etc. | |
1389 | ||
1390 | Each element inside this vector corresponds to a hardware | |
1391 | breakpoint or watchpoint in the thread represented by TID. The maximum | |
1392 | size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of | |
1393 | the tuple is NULL, then the position in the vector is free. */ | |
1394 | struct hw_break_tuple *hw_breaks; | |
1395 | } *thread_points_p; | |
1396 | DEF_VEC_P (thread_points_p); | |
1397 | ||
1398 | VEC(thread_points_p) *ppc_threads = NULL; | |
1399 | ||
1400 | /* The version of the kernel interface that we will use if the processor is | |
1401 | BookE. */ | |
1402 | #define PPC_DEBUG_CURRENT_VERSION 1 | |
1403 | ||
1404 | /* Returns non-zero if we support the ptrace interface which enables | |
1405 | booke debugging resources. */ | |
e0d24f8d | 1406 | static int |
6ffbb7ab | 1407 | have_ptrace_booke_interface (void) |
e0d24f8d | 1408 | { |
6ffbb7ab | 1409 | static int have_ptrace_booke_interface = -1; |
e0d24f8d | 1410 | |
6ffbb7ab TJB |
1411 | if (have_ptrace_booke_interface == -1) |
1412 | { | |
1413 | int tid; | |
e0d24f8d | 1414 | |
6ffbb7ab TJB |
1415 | tid = TIDGET (inferior_ptid); |
1416 | if (tid == 0) | |
1417 | tid = PIDGET (inferior_ptid); | |
e0d24f8d | 1418 | |
6ffbb7ab TJB |
1419 | /* Check for kernel support for BOOKE debug registers. */ |
1420 | if (ptrace (PPC_PTRACE_GETHWDBGINFO, tid, 0, &booke_debug_info) >= 0) | |
1421 | { | |
0c56f59b EBM |
1422 | /* Check whether ptrace BOOKE interface is functional and |
1423 | provides any supported feature. */ | |
1424 | if (booke_debug_info.features != 0) | |
1425 | { | |
1426 | have_ptrace_booke_interface = 1; | |
1427 | max_slots_number = booke_debug_info.num_instruction_bps | |
1428 | + booke_debug_info.num_data_bps | |
1429 | + booke_debug_info.num_condition_regs; | |
1430 | return have_ptrace_booke_interface; | |
1431 | } | |
6ffbb7ab | 1432 | } |
0c56f59b EBM |
1433 | /* Old school interface and no BOOKE debug registers support. */ |
1434 | have_ptrace_booke_interface = 0; | |
1435 | memset (&booke_debug_info, 0, sizeof (struct ppc_debug_info)); | |
6ffbb7ab TJB |
1436 | } |
1437 | ||
1438 | return have_ptrace_booke_interface; | |
e0d24f8d WZ |
1439 | } |
1440 | ||
6ffbb7ab TJB |
1441 | static int |
1442 | ppc_linux_can_use_hw_breakpoint (int type, int cnt, int ot) | |
b7622095 | 1443 | { |
6ffbb7ab | 1444 | int total_hw_wp, total_hw_bp; |
b7622095 | 1445 | |
6ffbb7ab TJB |
1446 | if (have_ptrace_booke_interface ()) |
1447 | { | |
1448 | /* For PPC BookE processors, the number of available hardware | |
1449 | watchpoints and breakpoints is stored at the booke_debug_info | |
1450 | struct. */ | |
1451 | total_hw_bp = booke_debug_info.num_instruction_bps; | |
1452 | total_hw_wp = booke_debug_info.num_data_bps; | |
1453 | } | |
1454 | else | |
1455 | { | |
1456 | /* For PPC server processors, we accept 1 hardware watchpoint and 0 | |
1457 | hardware breakpoints. */ | |
1458 | total_hw_bp = 0; | |
1459 | total_hw_wp = 1; | |
1460 | } | |
b7622095 | 1461 | |
6ffbb7ab TJB |
1462 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint |
1463 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
1464 | { | |
bb08bdbd | 1465 | if (cnt + ot > total_hw_wp) |
6ffbb7ab TJB |
1466 | return -1; |
1467 | } | |
1468 | else if (type == bp_hardware_breakpoint) | |
1469 | { | |
1470 | if (cnt > total_hw_bp) | |
1471 | return -1; | |
1472 | } | |
1473 | ||
1474 | if (!have_ptrace_booke_interface ()) | |
1475 | { | |
1476 | int tid; | |
1477 | ptid_t ptid = inferior_ptid; | |
1478 | ||
0df8b418 MS |
1479 | /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG |
1480 | and whether the target has DABR. If either answer is no, the | |
1481 | ptrace call will return -1. Fail in that case. */ | |
6ffbb7ab TJB |
1482 | tid = TIDGET (ptid); |
1483 | if (tid == 0) | |
1484 | tid = PIDGET (ptid); | |
1485 | ||
1486 | if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1) | |
1487 | return 0; | |
1488 | } | |
1489 | ||
1490 | return 1; | |
b7622095 LM |
1491 | } |
1492 | ||
e0d24f8d WZ |
1493 | static int |
1494 | ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
1495 | { | |
1496 | /* Handle sub-8-byte quantities. */ | |
1497 | if (len <= 0) | |
1498 | return 0; | |
1499 | ||
6ffbb7ab TJB |
1500 | /* The new BookE ptrace interface tells if there are alignment restrictions |
1501 | for watchpoints in the processors. In that case, we use that information | |
1502 | to determine the hardcoded watchable region for watchpoints. */ | |
1503 | if (have_ptrace_booke_interface ()) | |
1504 | { | |
4feebbdd EBM |
1505 | /* Embedded DAC-based processors, like the PowerPC 440 have ranged |
1506 | watchpoints and can watch any access within an arbitrary memory | |
1507 | region. This is useful to watch arrays and structs, for instance. It | |
1508 | takes two hardware watchpoints though. */ | |
e09342b5 | 1509 | if (len > 1 |
4feebbdd EBM |
1510 | && booke_debug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE |
1511 | && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
e09342b5 | 1512 | return 2; |
4feebbdd EBM |
1513 | /* Server processors provide one hardware watchpoint and addr+len should |
1514 | fall in the watchable region provided by the ptrace interface. */ | |
1515 | if (booke_debug_info.data_bp_alignment | |
1516 | && (addr + len > (addr & ~(booke_debug_info.data_bp_alignment - 1)) | |
1517 | + booke_debug_info.data_bp_alignment)) | |
0cf6dd15 | 1518 | return 0; |
6ffbb7ab | 1519 | } |
b7622095 | 1520 | /* addr+len must fall in the 8 byte watchable region for DABR-based |
6ffbb7ab TJB |
1521 | processors (i.e., server processors). Without the new BookE ptrace |
1522 | interface, DAC-based processors (i.e., embedded processors) will use | |
b7622095 | 1523 | addresses aligned to 4-bytes due to the way the read/write flags are |
6ffbb7ab TJB |
1524 | passed in the old ptrace interface. */ |
1525 | else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
1526 | && (addr + len) > (addr & ~3) + 4) | |
1527 | || (addr + len) > (addr & ~7) + 8) | |
e0d24f8d WZ |
1528 | return 0; |
1529 | ||
1530 | return 1; | |
1531 | } | |
1532 | ||
6ffbb7ab | 1533 | /* This function compares two ppc_hw_breakpoint structs field-by-field. */ |
e4166a49 | 1534 | static int |
6ffbb7ab TJB |
1535 | booke_cmp_hw_point (struct ppc_hw_breakpoint *a, struct ppc_hw_breakpoint *b) |
1536 | { | |
ad422571 TJB |
1537 | return (a->trigger_type == b->trigger_type |
1538 | && a->addr_mode == b->addr_mode | |
1539 | && a->condition_mode == b->condition_mode | |
1540 | && a->addr == b->addr | |
1541 | && a->addr2 == b->addr2 | |
6ffbb7ab TJB |
1542 | && a->condition_value == b->condition_value); |
1543 | } | |
1544 | ||
1545 | /* This function can be used to retrieve a thread_points by the TID of the | |
1546 | related process/thread. If nothing has been found, and ALLOC_NEW is 0, | |
1547 | it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the | |
1548 | provided TID will be created and returned. */ | |
1549 | static struct thread_points * | |
1550 | booke_find_thread_points_by_tid (int tid, int alloc_new) | |
1551 | { | |
1552 | int i; | |
1553 | struct thread_points *t; | |
1554 | ||
1555 | for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, t); i++) | |
1556 | if (t->tid == tid) | |
1557 | return t; | |
1558 | ||
1559 | t = NULL; | |
1560 | ||
1561 | /* Do we need to allocate a new point_item | |
1562 | if the wanted one does not exist? */ | |
1563 | if (alloc_new) | |
1564 | { | |
1565 | t = xmalloc (sizeof (struct thread_points)); | |
0df8b418 MS |
1566 | t->hw_breaks |
1567 | = xzalloc (max_slots_number * sizeof (struct hw_break_tuple)); | |
6ffbb7ab TJB |
1568 | t->tid = tid; |
1569 | VEC_safe_push (thread_points_p, ppc_threads, t); | |
1570 | } | |
1571 | ||
1572 | return t; | |
1573 | } | |
1574 | ||
1575 | /* This function is a generic wrapper that is responsible for inserting a | |
1576 | *point (i.e., calling `ptrace' in order to issue the request to the | |
1577 | kernel) and registering it internally in GDB. */ | |
1578 | static void | |
1579 | booke_insert_point (struct ppc_hw_breakpoint *b, int tid) | |
1580 | { | |
1581 | int i; | |
1582 | long slot; | |
1583 | struct ppc_hw_breakpoint *p = xmalloc (sizeof (struct ppc_hw_breakpoint)); | |
1584 | struct hw_break_tuple *hw_breaks; | |
1585 | struct cleanup *c = make_cleanup (xfree, p); | |
1586 | struct thread_points *t; | |
1587 | struct hw_break_tuple *tuple; | |
1588 | ||
1589 | memcpy (p, b, sizeof (struct ppc_hw_breakpoint)); | |
1590 | ||
1591 | errno = 0; | |
1592 | slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p); | |
1593 | if (slot < 0) | |
1594 | perror_with_name (_("Unexpected error setting breakpoint or watchpoint")); | |
1595 | ||
1596 | /* Everything went fine, so we have to register this *point. */ | |
1597 | t = booke_find_thread_points_by_tid (tid, 1); | |
1598 | gdb_assert (t != NULL); | |
1599 | hw_breaks = t->hw_breaks; | |
1600 | ||
1601 | /* Find a free element in the hw_breaks vector. */ | |
1602 | for (i = 0; i < max_slots_number; i++) | |
1603 | if (hw_breaks[i].hw_break == NULL) | |
1604 | { | |
1605 | hw_breaks[i].slot = slot; | |
1606 | hw_breaks[i].hw_break = p; | |
1607 | break; | |
1608 | } | |
1609 | ||
1610 | gdb_assert (i != max_slots_number); | |
1611 | ||
1612 | discard_cleanups (c); | |
1613 | } | |
1614 | ||
1615 | /* This function is a generic wrapper that is responsible for removing a | |
1616 | *point (i.e., calling `ptrace' in order to issue the request to the | |
1617 | kernel), and unregistering it internally at GDB. */ | |
1618 | static void | |
1619 | booke_remove_point (struct ppc_hw_breakpoint *b, int tid) | |
1620 | { | |
1621 | int i; | |
1622 | struct hw_break_tuple *hw_breaks; | |
1623 | struct thread_points *t; | |
1624 | ||
1625 | t = booke_find_thread_points_by_tid (tid, 0); | |
1626 | gdb_assert (t != NULL); | |
1627 | hw_breaks = t->hw_breaks; | |
1628 | ||
1629 | for (i = 0; i < max_slots_number; i++) | |
1630 | if (hw_breaks[i].hw_break && booke_cmp_hw_point (hw_breaks[i].hw_break, b)) | |
1631 | break; | |
1632 | ||
1633 | gdb_assert (i != max_slots_number); | |
1634 | ||
1635 | /* We have to ignore ENOENT errors because the kernel implements hardware | |
1636 | breakpoints/watchpoints as "one-shot", that is, they are automatically | |
1637 | deleted when hit. */ | |
1638 | errno = 0; | |
1639 | if (ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot) < 0) | |
1640 | if (errno != ENOENT) | |
0df8b418 MS |
1641 | perror_with_name (_("Unexpected error deleting " |
1642 | "breakpoint or watchpoint")); | |
6ffbb7ab TJB |
1643 | |
1644 | xfree (hw_breaks[i].hw_break); | |
1645 | hw_breaks[i].hw_break = NULL; | |
1646 | } | |
9f0bdab8 | 1647 | |
f1310107 TJB |
1648 | /* Return the number of registers needed for a ranged breakpoint. */ |
1649 | ||
1650 | static int | |
1651 | ppc_linux_ranged_break_num_registers (struct target_ops *target) | |
1652 | { | |
1653 | return ((have_ptrace_booke_interface () | |
1654 | && booke_debug_info.features & PPC_DEBUG_FEATURE_INSN_BP_RANGE)? | |
1655 | 2 : -1); | |
1656 | } | |
1657 | ||
1658 | /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for | |
1659 | success, 1 if hardware breakpoints are not supported or -1 for failure. */ | |
1660 | ||
2c387241 | 1661 | static int |
6ffbb7ab TJB |
1662 | ppc_linux_insert_hw_breakpoint (struct gdbarch *gdbarch, |
1663 | struct bp_target_info *bp_tgt) | |
e0d24f8d | 1664 | { |
9f0bdab8 | 1665 | struct lwp_info *lp; |
6ffbb7ab TJB |
1666 | struct ppc_hw_breakpoint p; |
1667 | ||
1668 | if (!have_ptrace_booke_interface ()) | |
1669 | return -1; | |
1670 | ||
ad422571 TJB |
1671 | p.version = PPC_DEBUG_CURRENT_VERSION; |
1672 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | |
ad422571 TJB |
1673 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
1674 | p.addr = (uint64_t) bp_tgt->placed_address; | |
6ffbb7ab TJB |
1675 | p.condition_value = 0; |
1676 | ||
f1310107 TJB |
1677 | if (bp_tgt->length) |
1678 | { | |
1679 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
1680 | ||
1681 | /* The breakpoint will trigger if the address of the instruction is | |
1682 | within the defined range, as follows: p.addr <= address < p.addr2. */ | |
1683 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; | |
1684 | } | |
1685 | else | |
1686 | { | |
1687 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
1688 | p.addr2 = 0; | |
1689 | } | |
1690 | ||
4c38200f PA |
1691 | ALL_LWPS (lp) |
1692 | booke_insert_point (&p, TIDGET (lp->ptid)); | |
6ffbb7ab TJB |
1693 | |
1694 | return 0; | |
1695 | } | |
1696 | ||
1697 | static int | |
1698 | ppc_linux_remove_hw_breakpoint (struct gdbarch *gdbarch, | |
1699 | struct bp_target_info *bp_tgt) | |
1700 | { | |
6ffbb7ab TJB |
1701 | struct lwp_info *lp; |
1702 | struct ppc_hw_breakpoint p; | |
b7622095 | 1703 | |
6ffbb7ab TJB |
1704 | if (!have_ptrace_booke_interface ()) |
1705 | return -1; | |
1706 | ||
ad422571 TJB |
1707 | p.version = PPC_DEBUG_CURRENT_VERSION; |
1708 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | |
ad422571 TJB |
1709 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
1710 | p.addr = (uint64_t) bp_tgt->placed_address; | |
6ffbb7ab TJB |
1711 | p.condition_value = 0; |
1712 | ||
f1310107 TJB |
1713 | if (bp_tgt->length) |
1714 | { | |
1715 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
1716 | ||
1717 | /* The breakpoint will trigger if the address of the instruction is within | |
1718 | the defined range, as follows: p.addr <= address < p.addr2. */ | |
1719 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; | |
1720 | } | |
1721 | else | |
1722 | { | |
1723 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
1724 | p.addr2 = 0; | |
1725 | } | |
1726 | ||
4c38200f PA |
1727 | ALL_LWPS (lp) |
1728 | booke_remove_point (&p, TIDGET (lp->ptid)); | |
6ffbb7ab TJB |
1729 | |
1730 | return 0; | |
1731 | } | |
1732 | ||
1733 | static int | |
1734 | get_trigger_type (int rw) | |
1735 | { | |
1736 | int t; | |
1737 | ||
1738 | if (rw == hw_read) | |
1739 | t = PPC_BREAKPOINT_TRIGGER_READ; | |
1740 | else if (rw == hw_write) | |
1741 | t = PPC_BREAKPOINT_TRIGGER_WRITE; | |
b7622095 | 1742 | else |
6ffbb7ab TJB |
1743 | t = PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE; |
1744 | ||
1745 | return t; | |
1746 | } | |
1747 | ||
9c06b0b4 TJB |
1748 | /* Insert a new masked watchpoint at ADDR using the mask MASK. |
1749 | RW may be hw_read for a read watchpoint, hw_write for a write watchpoint | |
1750 | or hw_access for an access watchpoint. Returns 0 on success and throws | |
1751 | an error on failure. */ | |
1752 | ||
1753 | static int | |
1754 | ppc_linux_insert_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr, | |
1755 | CORE_ADDR mask, int rw) | |
1756 | { | |
9c06b0b4 TJB |
1757 | struct lwp_info *lp; |
1758 | struct ppc_hw_breakpoint p; | |
1759 | ||
1760 | gdb_assert (have_ptrace_booke_interface ()); | |
1761 | ||
1762 | p.version = PPC_DEBUG_CURRENT_VERSION; | |
1763 | p.trigger_type = get_trigger_type (rw); | |
1764 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; | |
1765 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
1766 | p.addr = addr; | |
1767 | p.addr2 = mask; | |
1768 | p.condition_value = 0; | |
1769 | ||
4c38200f PA |
1770 | ALL_LWPS (lp) |
1771 | booke_insert_point (&p, TIDGET (lp->ptid)); | |
9c06b0b4 TJB |
1772 | |
1773 | return 0; | |
1774 | } | |
1775 | ||
1776 | /* Remove a masked watchpoint at ADDR with the mask MASK. | |
1777 | RW may be hw_read for a read watchpoint, hw_write for a write watchpoint | |
1778 | or hw_access for an access watchpoint. Returns 0 on success and throws | |
1779 | an error on failure. */ | |
1780 | ||
1781 | static int | |
1782 | ppc_linux_remove_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr, | |
1783 | CORE_ADDR mask, int rw) | |
1784 | { | |
9c06b0b4 TJB |
1785 | struct lwp_info *lp; |
1786 | struct ppc_hw_breakpoint p; | |
1787 | ||
1788 | gdb_assert (have_ptrace_booke_interface ()); | |
1789 | ||
1790 | p.version = PPC_DEBUG_CURRENT_VERSION; | |
1791 | p.trigger_type = get_trigger_type (rw); | |
1792 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; | |
1793 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
1794 | p.addr = addr; | |
1795 | p.addr2 = mask; | |
1796 | p.condition_value = 0; | |
1797 | ||
4c38200f PA |
1798 | ALL_LWPS (lp) |
1799 | booke_remove_point (&p, TIDGET (lp->ptid)); | |
9c06b0b4 TJB |
1800 | |
1801 | return 0; | |
1802 | } | |
1803 | ||
0cf6dd15 TJB |
1804 | /* Check whether we have at least one free DVC register. */ |
1805 | static int | |
1806 | can_use_watchpoint_cond_accel (void) | |
1807 | { | |
1808 | struct thread_points *p; | |
1809 | int tid = TIDGET (inferior_ptid); | |
1810 | int cnt = booke_debug_info.num_condition_regs, i; | |
1811 | CORE_ADDR tmp_value; | |
1812 | ||
1813 | if (!have_ptrace_booke_interface () || cnt == 0) | |
1814 | return 0; | |
1815 | ||
1816 | p = booke_find_thread_points_by_tid (tid, 0); | |
1817 | ||
1818 | if (p) | |
1819 | { | |
1820 | for (i = 0; i < max_slots_number; i++) | |
1821 | if (p->hw_breaks[i].hw_break != NULL | |
1822 | && (p->hw_breaks[i].hw_break->condition_mode | |
1823 | != PPC_BREAKPOINT_CONDITION_NONE)) | |
1824 | cnt--; | |
1825 | ||
1826 | /* There are no available slots now. */ | |
1827 | if (cnt <= 0) | |
1828 | return 0; | |
1829 | } | |
1830 | ||
1831 | return 1; | |
1832 | } | |
1833 | ||
1834 | /* Calculate the enable bits and the contents of the Data Value Compare | |
1835 | debug register present in BookE processors. | |
1836 | ||
1837 | ADDR is the address to be watched, LEN is the length of watched data | |
1838 | and DATA_VALUE is the value which will trigger the watchpoint. | |
1839 | On exit, CONDITION_MODE will hold the enable bits for the DVC, and | |
1840 | CONDITION_VALUE will hold the value which should be put in the | |
1841 | DVC register. */ | |
1842 | static void | |
1843 | calculate_dvc (CORE_ADDR addr, int len, CORE_ADDR data_value, | |
1844 | uint32_t *condition_mode, uint64_t *condition_value) | |
1845 | { | |
1846 | int i, num_byte_enable, align_offset, num_bytes_off_dvc, | |
1847 | rightmost_enabled_byte; | |
1848 | CORE_ADDR addr_end_data, addr_end_dvc; | |
1849 | ||
1850 | /* The DVC register compares bytes within fixed-length windows which | |
1851 | are word-aligned, with length equal to that of the DVC register. | |
1852 | We need to calculate where our watch region is relative to that | |
1853 | window and enable comparison of the bytes which fall within it. */ | |
1854 | ||
1855 | align_offset = addr % booke_debug_info.sizeof_condition; | |
1856 | addr_end_data = addr + len; | |
1857 | addr_end_dvc = (addr - align_offset | |
1858 | + booke_debug_info.sizeof_condition); | |
1859 | num_bytes_off_dvc = (addr_end_data > addr_end_dvc)? | |
1860 | addr_end_data - addr_end_dvc : 0; | |
1861 | num_byte_enable = len - num_bytes_off_dvc; | |
1862 | /* Here, bytes are numbered from right to left. */ | |
1863 | rightmost_enabled_byte = (addr_end_data < addr_end_dvc)? | |
1864 | addr_end_dvc - addr_end_data : 0; | |
1865 | ||
1866 | *condition_mode = PPC_BREAKPOINT_CONDITION_AND; | |
1867 | for (i = 0; i < num_byte_enable; i++) | |
0df8b418 MS |
1868 | *condition_mode |
1869 | |= PPC_BREAKPOINT_CONDITION_BE (i + rightmost_enabled_byte); | |
0cf6dd15 TJB |
1870 | |
1871 | /* Now we need to match the position within the DVC of the comparison | |
1872 | value with where the watch region is relative to the window | |
1873 | (i.e., the ALIGN_OFFSET). */ | |
1874 | ||
1875 | *condition_value = ((uint64_t) data_value >> num_bytes_off_dvc * 8 | |
1876 | << rightmost_enabled_byte * 8); | |
1877 | } | |
1878 | ||
1879 | /* Return the number of memory locations that need to be accessed to | |
1880 | evaluate the expression which generated the given value chain. | |
1881 | Returns -1 if there's any register access involved, or if there are | |
1882 | other kinds of values which are not acceptable in a condition | |
1883 | expression (e.g., lval_computed or lval_internalvar). */ | |
1884 | static int | |
1885 | num_memory_accesses (struct value *v) | |
1886 | { | |
1887 | int found_memory_cnt = 0; | |
1888 | struct value *head = v; | |
1889 | ||
1890 | /* The idea here is that evaluating an expression generates a series | |
1891 | of values, one holding the value of every subexpression. (The | |
1892 | expression a*b+c has five subexpressions: a, b, a*b, c, and | |
1893 | a*b+c.) GDB's values hold almost enough information to establish | |
1894 | the criteria given above --- they identify memory lvalues, | |
1895 | register lvalues, computed values, etcetera. So we can evaluate | |
1896 | the expression, and then scan the chain of values that leaves | |
1897 | behind to determine the memory locations involved in the evaluation | |
1898 | of an expression. | |
1899 | ||
1900 | However, I don't think that the values returned by inferior | |
1901 | function calls are special in any way. So this function may not | |
1902 | notice that an expression contains an inferior function call. | |
1903 | FIXME. */ | |
1904 | ||
1905 | for (; v; v = value_next (v)) | |
1906 | { | |
1907 | /* Constants and values from the history are fine. */ | |
1908 | if (VALUE_LVAL (v) == not_lval || deprecated_value_modifiable (v) == 0) | |
1909 | continue; | |
1910 | else if (VALUE_LVAL (v) == lval_memory) | |
1911 | { | |
1912 | /* A lazy memory lvalue is one that GDB never needed to fetch; | |
1913 | we either just used its address (e.g., `a' in `a.b') or | |
1914 | we never needed it at all (e.g., `a' in `a,b'). */ | |
1915 | if (!value_lazy (v)) | |
1916 | found_memory_cnt++; | |
1917 | } | |
0df8b418 | 1918 | /* Other kinds of values are not fine. */ |
0cf6dd15 TJB |
1919 | else |
1920 | return -1; | |
1921 | } | |
1922 | ||
1923 | return found_memory_cnt; | |
1924 | } | |
1925 | ||
1926 | /* Verifies whether the expression COND can be implemented using the | |
1927 | DVC (Data Value Compare) register in BookE processors. The expression | |
1928 | must test the watch value for equality with a constant expression. | |
1929 | If the function returns 1, DATA_VALUE will contain the constant against | |
e7db58ea TJB |
1930 | which the watch value should be compared and LEN will contain the size |
1931 | of the constant. */ | |
0cf6dd15 TJB |
1932 | static int |
1933 | check_condition (CORE_ADDR watch_addr, struct expression *cond, | |
e7db58ea | 1934 | CORE_ADDR *data_value, int *len) |
0cf6dd15 TJB |
1935 | { |
1936 | int pc = 1, num_accesses_left, num_accesses_right; | |
1937 | struct value *left_val, *right_val, *left_chain, *right_chain; | |
1938 | ||
1939 | if (cond->elts[0].opcode != BINOP_EQUAL) | |
1940 | return 0; | |
1941 | ||
1942 | fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain); | |
1943 | num_accesses_left = num_memory_accesses (left_chain); | |
1944 | ||
1945 | if (left_val == NULL || num_accesses_left < 0) | |
1946 | { | |
1947 | free_value_chain (left_chain); | |
1948 | ||
1949 | return 0; | |
1950 | } | |
1951 | ||
1952 | fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain); | |
1953 | num_accesses_right = num_memory_accesses (right_chain); | |
1954 | ||
1955 | if (right_val == NULL || num_accesses_right < 0) | |
1956 | { | |
1957 | free_value_chain (left_chain); | |
1958 | free_value_chain (right_chain); | |
1959 | ||
1960 | return 0; | |
1961 | } | |
1962 | ||
1963 | if (num_accesses_left == 1 && num_accesses_right == 0 | |
1964 | && VALUE_LVAL (left_val) == lval_memory | |
1965 | && value_address (left_val) == watch_addr) | |
e7db58ea TJB |
1966 | { |
1967 | *data_value = value_as_long (right_val); | |
1968 | ||
1969 | /* DATA_VALUE is the constant in RIGHT_VAL, but actually has | |
1970 | the same type as the memory region referenced by LEFT_VAL. */ | |
1971 | *len = TYPE_LENGTH (check_typedef (value_type (left_val))); | |
1972 | } | |
0cf6dd15 TJB |
1973 | else if (num_accesses_left == 0 && num_accesses_right == 1 |
1974 | && VALUE_LVAL (right_val) == lval_memory | |
1975 | && value_address (right_val) == watch_addr) | |
e7db58ea TJB |
1976 | { |
1977 | *data_value = value_as_long (left_val); | |
1978 | ||
1979 | /* DATA_VALUE is the constant in LEFT_VAL, but actually has | |
1980 | the same type as the memory region referenced by RIGHT_VAL. */ | |
1981 | *len = TYPE_LENGTH (check_typedef (value_type (right_val))); | |
1982 | } | |
0cf6dd15 TJB |
1983 | else |
1984 | { | |
1985 | free_value_chain (left_chain); | |
1986 | free_value_chain (right_chain); | |
1987 | ||
1988 | return 0; | |
1989 | } | |
1990 | ||
1991 | free_value_chain (left_chain); | |
1992 | free_value_chain (right_chain); | |
1993 | ||
1994 | return 1; | |
1995 | } | |
1996 | ||
1997 | /* Return non-zero if the target is capable of using hardware to evaluate | |
1998 | the condition expression, thus only triggering the watchpoint when it is | |
1999 | true. */ | |
2000 | static int | |
2001 | ppc_linux_can_accel_watchpoint_condition (CORE_ADDR addr, int len, int rw, | |
2002 | struct expression *cond) | |
2003 | { | |
2004 | CORE_ADDR data_value; | |
2005 | ||
2006 | return (have_ptrace_booke_interface () | |
2007 | && booke_debug_info.num_condition_regs > 0 | |
e7db58ea | 2008 | && check_condition (addr, cond, &data_value, &len)); |
0cf6dd15 TJB |
2009 | } |
2010 | ||
e09342b5 TJB |
2011 | /* Set up P with the parameters necessary to request a watchpoint covering |
2012 | LEN bytes starting at ADDR and if possible with condition expression COND | |
2013 | evaluated by hardware. INSERT tells if we are creating a request for | |
2014 | inserting or removing the watchpoint. */ | |
2015 | ||
2016 | static void | |
2017 | create_watchpoint_request (struct ppc_hw_breakpoint *p, CORE_ADDR addr, | |
2018 | int len, int rw, struct expression *cond, | |
2019 | int insert) | |
2020 | { | |
f16c4e8b AS |
2021 | if (len == 1 |
2022 | || !(booke_debug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE)) | |
e09342b5 TJB |
2023 | { |
2024 | int use_condition; | |
2025 | CORE_ADDR data_value; | |
2026 | ||
2027 | use_condition = (insert? can_use_watchpoint_cond_accel () | |
2028 | : booke_debug_info.num_condition_regs > 0); | |
e7db58ea TJB |
2029 | if (cond && use_condition && check_condition (addr, cond, |
2030 | &data_value, &len)) | |
e09342b5 TJB |
2031 | calculate_dvc (addr, len, data_value, &p->condition_mode, |
2032 | &p->condition_value); | |
2033 | else | |
2034 | { | |
2035 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
2036 | p->condition_value = 0; | |
2037 | } | |
2038 | ||
2039 | p->addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
2040 | p->addr2 = 0; | |
2041 | } | |
2042 | else | |
2043 | { | |
2044 | p->addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
2045 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
2046 | p->condition_value = 0; | |
2047 | ||
2048 | /* The watchpoint will trigger if the address of the memory access is | |
2049 | within the defined range, as follows: p->addr <= address < p->addr2. | |
2050 | ||
2051 | Note that the above sentence just documents how ptrace interprets | |
2052 | its arguments; the watchpoint is set to watch the range defined by | |
2053 | the user _inclusively_, as specified by the user interface. */ | |
2054 | p->addr2 = (uint64_t) addr + len; | |
2055 | } | |
2056 | ||
2057 | p->version = PPC_DEBUG_CURRENT_VERSION; | |
2058 | p->trigger_type = get_trigger_type (rw); | |
2059 | p->addr = (uint64_t) addr; | |
2060 | } | |
2061 | ||
6ffbb7ab | 2062 | static int |
0cf6dd15 TJB |
2063 | ppc_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw, |
2064 | struct expression *cond) | |
6ffbb7ab TJB |
2065 | { |
2066 | struct lwp_info *lp; | |
6ffbb7ab TJB |
2067 | int ret = -1; |
2068 | ||
2069 | if (have_ptrace_booke_interface ()) | |
e0d24f8d | 2070 | { |
6ffbb7ab TJB |
2071 | struct ppc_hw_breakpoint p; |
2072 | ||
e09342b5 | 2073 | create_watchpoint_request (&p, addr, len, rw, cond, 1); |
6ffbb7ab | 2074 | |
4c38200f PA |
2075 | ALL_LWPS (lp) |
2076 | booke_insert_point (&p, TIDGET (lp->ptid)); | |
6ffbb7ab TJB |
2077 | |
2078 | ret = 0; | |
e0d24f8d | 2079 | } |
6ffbb7ab TJB |
2080 | else |
2081 | { | |
2082 | long dabr_value; | |
2083 | long read_mode, write_mode; | |
e0d24f8d | 2084 | |
6ffbb7ab TJB |
2085 | if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
2086 | { | |
2087 | /* PowerPC 440 requires only the read/write flags to be passed | |
2088 | to the kernel. */ | |
ad422571 | 2089 | read_mode = 1; |
6ffbb7ab TJB |
2090 | write_mode = 2; |
2091 | } | |
2092 | else | |
2093 | { | |
2094 | /* PowerPC 970 and other DABR-based processors are required to pass | |
2095 | the Breakpoint Translation bit together with the flags. */ | |
ad422571 | 2096 | read_mode = 5; |
6ffbb7ab TJB |
2097 | write_mode = 6; |
2098 | } | |
1c86e440 | 2099 | |
6ffbb7ab TJB |
2100 | dabr_value = addr & ~(read_mode | write_mode); |
2101 | switch (rw) | |
2102 | { | |
2103 | case hw_read: | |
2104 | /* Set read and translate bits. */ | |
2105 | dabr_value |= read_mode; | |
2106 | break; | |
2107 | case hw_write: | |
2108 | /* Set write and translate bits. */ | |
2109 | dabr_value |= write_mode; | |
2110 | break; | |
2111 | case hw_access: | |
2112 | /* Set read, write and translate bits. */ | |
2113 | dabr_value |= read_mode | write_mode; | |
2114 | break; | |
2115 | } | |
1c86e440 | 2116 | |
6ffbb7ab TJB |
2117 | saved_dabr_value = dabr_value; |
2118 | ||
4c38200f PA |
2119 | ALL_LWPS (lp) |
2120 | if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (lp->ptid), 0, | |
0cf6dd15 | 2121 | saved_dabr_value) < 0) |
6ffbb7ab TJB |
2122 | return -1; |
2123 | ||
2124 | ret = 0; | |
2125 | } | |
2126 | ||
2127 | return ret; | |
e0d24f8d WZ |
2128 | } |
2129 | ||
2c387241 | 2130 | static int |
0cf6dd15 TJB |
2131 | ppc_linux_remove_watchpoint (CORE_ADDR addr, int len, int rw, |
2132 | struct expression *cond) | |
e0d24f8d | 2133 | { |
9f0bdab8 | 2134 | struct lwp_info *lp; |
6ffbb7ab | 2135 | int ret = -1; |
9f0bdab8 | 2136 | |
6ffbb7ab TJB |
2137 | if (have_ptrace_booke_interface ()) |
2138 | { | |
2139 | struct ppc_hw_breakpoint p; | |
2140 | ||
e09342b5 | 2141 | create_watchpoint_request (&p, addr, len, rw, cond, 0); |
6ffbb7ab | 2142 | |
4c38200f PA |
2143 | ALL_LWPS (lp) |
2144 | booke_remove_point (&p, TIDGET (lp->ptid)); | |
6ffbb7ab TJB |
2145 | |
2146 | ret = 0; | |
2147 | } | |
2148 | else | |
2149 | { | |
2150 | saved_dabr_value = 0; | |
4c38200f PA |
2151 | ALL_LWPS (lp) |
2152 | if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (lp->ptid), 0, | |
0cf6dd15 | 2153 | saved_dabr_value) < 0) |
6ffbb7ab TJB |
2154 | return -1; |
2155 | ||
2156 | ret = 0; | |
2157 | } | |
2158 | ||
2159 | return ret; | |
e0d24f8d WZ |
2160 | } |
2161 | ||
9f0bdab8 | 2162 | static void |
7b50312a | 2163 | ppc_linux_new_thread (struct lwp_info *lp) |
e0d24f8d | 2164 | { |
7b50312a | 2165 | int tid = TIDGET (lp->ptid); |
6ffbb7ab TJB |
2166 | |
2167 | if (have_ptrace_booke_interface ()) | |
2168 | { | |
2169 | int i; | |
2170 | struct thread_points *p; | |
2171 | struct hw_break_tuple *hw_breaks; | |
2172 | ||
2173 | if (VEC_empty (thread_points_p, ppc_threads)) | |
2174 | return; | |
2175 | ||
0df8b418 | 2176 | /* Get a list of breakpoints from any thread. */ |
6ffbb7ab TJB |
2177 | p = VEC_last (thread_points_p, ppc_threads); |
2178 | hw_breaks = p->hw_breaks; | |
2179 | ||
0df8b418 | 2180 | /* Copy that thread's breakpoints and watchpoints to the new thread. */ |
6ffbb7ab TJB |
2181 | for (i = 0; i < max_slots_number; i++) |
2182 | if (hw_breaks[i].hw_break) | |
aacbb8a5 LM |
2183 | { |
2184 | /* Older kernels did not make new threads inherit their parent | |
2185 | thread's debug state, so we always clear the slot and replicate | |
2186 | the debug state ourselves, ensuring compatibility with all | |
2187 | kernels. */ | |
2188 | ||
2189 | /* The ppc debug resource accounting is done through "slots". | |
2190 | Ask the kernel the deallocate this specific *point's slot. */ | |
2191 | ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot); | |
2192 | ||
2193 | booke_insert_point (hw_breaks[i].hw_break, tid); | |
2194 | } | |
6ffbb7ab TJB |
2195 | } |
2196 | else | |
2197 | ptrace (PTRACE_SET_DEBUGREG, tid, 0, saved_dabr_value); | |
2198 | } | |
2199 | ||
2200 | static void | |
2201 | ppc_linux_thread_exit (struct thread_info *tp, int silent) | |
2202 | { | |
2203 | int i; | |
2204 | int tid = TIDGET (tp->ptid); | |
2205 | struct hw_break_tuple *hw_breaks; | |
2206 | struct thread_points *t = NULL, *p; | |
2207 | ||
2208 | if (!have_ptrace_booke_interface ()) | |
2209 | return; | |
2210 | ||
2211 | for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, p); i++) | |
2212 | if (p->tid == tid) | |
2213 | { | |
2214 | t = p; | |
2215 | break; | |
2216 | } | |
2217 | ||
2218 | if (t == NULL) | |
2219 | return; | |
2220 | ||
2221 | VEC_unordered_remove (thread_points_p, ppc_threads, i); | |
2222 | ||
2223 | hw_breaks = t->hw_breaks; | |
2224 | ||
2225 | for (i = 0; i < max_slots_number; i++) | |
2226 | if (hw_breaks[i].hw_break) | |
2227 | xfree (hw_breaks[i].hw_break); | |
2228 | ||
2229 | xfree (t->hw_breaks); | |
2230 | xfree (t); | |
e0d24f8d WZ |
2231 | } |
2232 | ||
2233 | static int | |
9f0bdab8 | 2234 | ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p) |
e0d24f8d | 2235 | { |
f865ee35 | 2236 | siginfo_t siginfo; |
e0d24f8d | 2237 | |
f865ee35 JK |
2238 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) |
2239 | return 0; | |
e0d24f8d | 2240 | |
f865ee35 JK |
2241 | if (siginfo.si_signo != SIGTRAP |
2242 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
e0d24f8d WZ |
2243 | return 0; |
2244 | ||
6ffbb7ab TJB |
2245 | if (have_ptrace_booke_interface ()) |
2246 | { | |
2247 | int i; | |
2248 | struct thread_points *t; | |
2249 | struct hw_break_tuple *hw_breaks; | |
2250 | /* The index (or slot) of the *point is passed in the si_errno field. */ | |
f865ee35 | 2251 | int slot = siginfo.si_errno; |
6ffbb7ab TJB |
2252 | |
2253 | t = booke_find_thread_points_by_tid (TIDGET (inferior_ptid), 0); | |
2254 | ||
2255 | /* Find out if this *point is a hardware breakpoint. | |
2256 | If so, we should return 0. */ | |
2257 | if (t) | |
2258 | { | |
2259 | hw_breaks = t->hw_breaks; | |
2260 | for (i = 0; i < max_slots_number; i++) | |
2261 | if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot | |
2262 | && hw_breaks[i].hw_break->trigger_type | |
2263 | == PPC_BREAKPOINT_TRIGGER_EXECUTE) | |
2264 | return 0; | |
2265 | } | |
2266 | } | |
2267 | ||
f865ee35 | 2268 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
e0d24f8d WZ |
2269 | return 1; |
2270 | } | |
2271 | ||
9f0bdab8 DJ |
2272 | static int |
2273 | ppc_linux_stopped_by_watchpoint (void) | |
2274 | { | |
2275 | CORE_ADDR addr; | |
2276 | return ppc_linux_stopped_data_address (¤t_target, &addr); | |
2277 | } | |
2278 | ||
5009afc5 AS |
2279 | static int |
2280 | ppc_linux_watchpoint_addr_within_range (struct target_ops *target, | |
2281 | CORE_ADDR addr, | |
2282 | CORE_ADDR start, int length) | |
2283 | { | |
b7622095 LM |
2284 | int mask; |
2285 | ||
6ffbb7ab TJB |
2286 | if (have_ptrace_booke_interface () |
2287 | && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
2288 | return start <= addr && start + length >= addr; | |
2289 | else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
b7622095 LM |
2290 | mask = 3; |
2291 | else | |
2292 | mask = 7; | |
2293 | ||
2294 | addr &= ~mask; | |
2295 | ||
0df8b418 | 2296 | /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */ |
b7622095 | 2297 | return start <= addr + mask && start + length - 1 >= addr; |
5009afc5 AS |
2298 | } |
2299 | ||
9c06b0b4 TJB |
2300 | /* Return the number of registers needed for a masked hardware watchpoint. */ |
2301 | ||
2302 | static int | |
2303 | ppc_linux_masked_watch_num_registers (struct target_ops *target, | |
2304 | CORE_ADDR addr, CORE_ADDR mask) | |
2305 | { | |
2306 | if (!have_ptrace_booke_interface () | |
2307 | || (booke_debug_info.features & PPC_DEBUG_FEATURE_DATA_BP_MASK) == 0) | |
2308 | return -1; | |
2309 | else if ((mask & 0xC0000000) != 0xC0000000) | |
2310 | { | |
2311 | warning (_("The given mask covers kernel address space " | |
2312 | "and cannot be used.\n")); | |
2313 | ||
2314 | return -2; | |
2315 | } | |
2316 | else | |
2317 | return 2; | |
2318 | } | |
2319 | ||
10d6c8cd | 2320 | static void |
28439f5e PA |
2321 | ppc_linux_store_inferior_registers (struct target_ops *ops, |
2322 | struct regcache *regcache, int regno) | |
45229ea4 | 2323 | { |
0df8b418 | 2324 | /* Overload thread id onto process id. */ |
05f13b9c EZ |
2325 | int tid = TIDGET (inferior_ptid); |
2326 | ||
0df8b418 | 2327 | /* No thread id, just use process id. */ |
05f13b9c EZ |
2328 | if (tid == 0) |
2329 | tid = PIDGET (inferior_ptid); | |
2330 | ||
45229ea4 | 2331 | if (regno >= 0) |
56be3814 | 2332 | store_register (regcache, tid, regno); |
45229ea4 | 2333 | else |
56be3814 | 2334 | store_ppc_registers (regcache, tid); |
45229ea4 EZ |
2335 | } |
2336 | ||
f2db237a AM |
2337 | /* Functions for transferring registers between a gregset_t or fpregset_t |
2338 | (see sys/ucontext.h) and gdb's regcache. The word size is that used | |
0df8b418 | 2339 | by the ptrace interface, not the current program's ABI. Eg. if a |
f2db237a AM |
2340 | powerpc64-linux gdb is being used to debug a powerpc32-linux app, we |
2341 | read or write 64-bit gregsets. This is to suit the host libthread_db. */ | |
2342 | ||
50c9bd31 | 2343 | void |
7f7fe91e | 2344 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
c877c8e6 | 2345 | { |
f2db237a | 2346 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 2347 | |
f2db237a | 2348 | ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp)); |
c877c8e6 KB |
2349 | } |
2350 | ||
fdb28ac4 | 2351 | void |
7f7fe91e UW |
2352 | fill_gregset (const struct regcache *regcache, |
2353 | gdb_gregset_t *gregsetp, int regno) | |
fdb28ac4 | 2354 | { |
f2db237a | 2355 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 2356 | |
f2db237a AM |
2357 | if (regno == -1) |
2358 | memset (gregsetp, 0, sizeof (*gregsetp)); | |
2359 | ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp)); | |
fdb28ac4 KB |
2360 | } |
2361 | ||
50c9bd31 | 2362 | void |
7f7fe91e | 2363 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp) |
c877c8e6 | 2364 | { |
f2db237a AM |
2365 | const struct regset *regset = ppc_linux_fpregset (); |
2366 | ||
2367 | ppc_supply_fpregset (regset, regcache, -1, | |
2368 | fpregsetp, sizeof (*fpregsetp)); | |
c877c8e6 | 2369 | } |
fdb28ac4 | 2370 | |
fdb28ac4 | 2371 | void |
7f7fe91e UW |
2372 | fill_fpregset (const struct regcache *regcache, |
2373 | gdb_fpregset_t *fpregsetp, int regno) | |
fdb28ac4 | 2374 | { |
f2db237a AM |
2375 | const struct regset *regset = ppc_linux_fpregset (); |
2376 | ||
2377 | ppc_collect_fpregset (regset, regcache, regno, | |
2378 | fpregsetp, sizeof (*fpregsetp)); | |
fdb28ac4 | 2379 | } |
10d6c8cd | 2380 | |
409c383c UW |
2381 | static int |
2382 | ppc_linux_target_wordsize (void) | |
2383 | { | |
2384 | int wordsize = 4; | |
2385 | ||
2386 | /* Check for 64-bit inferior process. This is the case when the host is | |
2387 | 64-bit, and in addition the top bit of the MSR register is set. */ | |
2388 | #ifdef __powerpc64__ | |
2389 | long msr; | |
2390 | ||
2391 | int tid = TIDGET (inferior_ptid); | |
2392 | if (tid == 0) | |
2393 | tid = PIDGET (inferior_ptid); | |
2394 | ||
2395 | errno = 0; | |
2396 | msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0); | |
2397 | if (errno == 0 && msr < 0) | |
2398 | wordsize = 8; | |
2399 | #endif | |
2400 | ||
2401 | return wordsize; | |
2402 | } | |
2403 | ||
2404 | static int | |
2405 | ppc_linux_auxv_parse (struct target_ops *ops, gdb_byte **readptr, | |
2406 | gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp) | |
2407 | { | |
2408 | int sizeof_auxv_field = ppc_linux_target_wordsize (); | |
f5656ead | 2409 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); |
409c383c UW |
2410 | gdb_byte *ptr = *readptr; |
2411 | ||
2412 | if (endptr == ptr) | |
2413 | return 0; | |
2414 | ||
2415 | if (endptr - ptr < sizeof_auxv_field * 2) | |
2416 | return -1; | |
2417 | ||
e17a4113 | 2418 | *typep = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); |
409c383c | 2419 | ptr += sizeof_auxv_field; |
e17a4113 | 2420 | *valp = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); |
409c383c UW |
2421 | ptr += sizeof_auxv_field; |
2422 | ||
2423 | *readptr = ptr; | |
2424 | return 1; | |
2425 | } | |
2426 | ||
310a98e1 DJ |
2427 | static const struct target_desc * |
2428 | ppc_linux_read_description (struct target_ops *ops) | |
2429 | { | |
7284e1be | 2430 | int altivec = 0; |
604c2f83 | 2431 | int vsx = 0; |
69abc51c | 2432 | int isa205 = 0; |
f4d9bade | 2433 | int cell = 0; |
7284e1be UW |
2434 | |
2435 | int tid = TIDGET (inferior_ptid); | |
2436 | if (tid == 0) | |
2437 | tid = PIDGET (inferior_ptid); | |
2438 | ||
310a98e1 DJ |
2439 | if (have_ptrace_getsetevrregs) |
2440 | { | |
2441 | struct gdb_evrregset_t evrregset; | |
310a98e1 DJ |
2442 | |
2443 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0) | |
7284e1be UW |
2444 | return tdesc_powerpc_e500l; |
2445 | ||
2446 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported. | |
2447 | Anything else needs to be reported. */ | |
2448 | else if (errno != EIO) | |
2449 | perror_with_name (_("Unable to fetch SPE registers")); | |
2450 | } | |
2451 | ||
604c2f83 LM |
2452 | if (have_ptrace_getsetvsxregs) |
2453 | { | |
2454 | gdb_vsxregset_t vsxregset; | |
2455 | ||
2456 | if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0) | |
2457 | vsx = 1; | |
2458 | ||
2459 | /* EIO means that the PTRACE_GETVSXREGS request isn't supported. | |
2460 | Anything else needs to be reported. */ | |
2461 | else if (errno != EIO) | |
2462 | perror_with_name (_("Unable to fetch VSX registers")); | |
2463 | } | |
2464 | ||
7284e1be UW |
2465 | if (have_ptrace_getvrregs) |
2466 | { | |
2467 | gdb_vrregset_t vrregset; | |
2468 | ||
2469 | if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0) | |
2470 | altivec = 1; | |
2471 | ||
2472 | /* EIO means that the PTRACE_GETVRREGS request isn't supported. | |
2473 | Anything else needs to be reported. */ | |
2474 | else if (errno != EIO) | |
2475 | perror_with_name (_("Unable to fetch AltiVec registers")); | |
310a98e1 DJ |
2476 | } |
2477 | ||
f04c6d38 | 2478 | /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases |
0df8b418 | 2479 | the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this |
f04c6d38 TJB |
2480 | ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only |
2481 | PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher | |
2482 | half of the register are for Decimal Floating Point, we check if that | |
2483 | feature is available to decide the size of the FPSCR. */ | |
2484 | if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP) | |
69abc51c TJB |
2485 | isa205 = 1; |
2486 | ||
f4d9bade UW |
2487 | if (ppc_linux_get_hwcap () & PPC_FEATURE_CELL) |
2488 | cell = 1; | |
2489 | ||
409c383c UW |
2490 | if (ppc_linux_target_wordsize () == 8) |
2491 | { | |
f4d9bade UW |
2492 | if (cell) |
2493 | return tdesc_powerpc_cell64l; | |
2494 | else if (vsx) | |
409c383c UW |
2495 | return isa205? tdesc_powerpc_isa205_vsx64l : tdesc_powerpc_vsx64l; |
2496 | else if (altivec) | |
0df8b418 MS |
2497 | return isa205 |
2498 | ? tdesc_powerpc_isa205_altivec64l : tdesc_powerpc_altivec64l; | |
409c383c UW |
2499 | |
2500 | return isa205? tdesc_powerpc_isa205_64l : tdesc_powerpc_64l; | |
2501 | } | |
7284e1be | 2502 | |
f4d9bade UW |
2503 | if (cell) |
2504 | return tdesc_powerpc_cell32l; | |
2505 | else if (vsx) | |
69abc51c | 2506 | return isa205? tdesc_powerpc_isa205_vsx32l : tdesc_powerpc_vsx32l; |
604c2f83 | 2507 | else if (altivec) |
69abc51c | 2508 | return isa205? tdesc_powerpc_isa205_altivec32l : tdesc_powerpc_altivec32l; |
604c2f83 | 2509 | |
69abc51c | 2510 | return isa205? tdesc_powerpc_isa205_32l : tdesc_powerpc_32l; |
310a98e1 DJ |
2511 | } |
2512 | ||
10d6c8cd DJ |
2513 | void _initialize_ppc_linux_nat (void); |
2514 | ||
2515 | void | |
2516 | _initialize_ppc_linux_nat (void) | |
2517 | { | |
2518 | struct target_ops *t; | |
2519 | ||
2520 | /* Fill in the generic GNU/Linux methods. */ | |
2521 | t = linux_target (); | |
2522 | ||
2523 | /* Add our register access methods. */ | |
2524 | t->to_fetch_registers = ppc_linux_fetch_inferior_registers; | |
2525 | t->to_store_registers = ppc_linux_store_inferior_registers; | |
2526 | ||
6ffbb7ab TJB |
2527 | /* Add our breakpoint/watchpoint methods. */ |
2528 | t->to_can_use_hw_breakpoint = ppc_linux_can_use_hw_breakpoint; | |
2529 | t->to_insert_hw_breakpoint = ppc_linux_insert_hw_breakpoint; | |
2530 | t->to_remove_hw_breakpoint = ppc_linux_remove_hw_breakpoint; | |
e0d24f8d WZ |
2531 | t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint; |
2532 | t->to_insert_watchpoint = ppc_linux_insert_watchpoint; | |
2533 | t->to_remove_watchpoint = ppc_linux_remove_watchpoint; | |
9c06b0b4 TJB |
2534 | t->to_insert_mask_watchpoint = ppc_linux_insert_mask_watchpoint; |
2535 | t->to_remove_mask_watchpoint = ppc_linux_remove_mask_watchpoint; | |
e0d24f8d WZ |
2536 | t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint; |
2537 | t->to_stopped_data_address = ppc_linux_stopped_data_address; | |
5009afc5 | 2538 | t->to_watchpoint_addr_within_range = ppc_linux_watchpoint_addr_within_range; |
0df8b418 MS |
2539 | t->to_can_accel_watchpoint_condition |
2540 | = ppc_linux_can_accel_watchpoint_condition; | |
9c06b0b4 | 2541 | t->to_masked_watch_num_registers = ppc_linux_masked_watch_num_registers; |
f1310107 | 2542 | t->to_ranged_break_num_registers = ppc_linux_ranged_break_num_registers; |
e0d24f8d | 2543 | |
310a98e1 | 2544 | t->to_read_description = ppc_linux_read_description; |
409c383c | 2545 | t->to_auxv_parse = ppc_linux_auxv_parse; |
310a98e1 | 2546 | |
6ffbb7ab TJB |
2547 | observer_attach_thread_exit (ppc_linux_thread_exit); |
2548 | ||
10d6c8cd | 2549 | /* Register the target. */ |
f973ed9c | 2550 | linux_nat_add_target (t); |
9f0bdab8 | 2551 | linux_nat_set_new_thread (t, ppc_linux_new_thread); |
10d6c8cd | 2552 | } |