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9abe5450 | 1 | /* PPC GNU/Linux native support. |
2555fe1a | 2 | |
e2882c85 | 3 | Copyright (C) 1988-2018 Free Software Foundation, Inc. |
c877c8e6 KB |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c877c8e6 KB |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c877c8e6 KB |
19 | |
20 | #include "defs.h" | |
76727919 | 21 | #include "observable.h" |
c877c8e6 KB |
22 | #include "frame.h" |
23 | #include "inferior.h" | |
6ffbb7ab | 24 | #include "gdbthread.h" |
c877c8e6 | 25 | #include "gdbcore.h" |
4e052eda | 26 | #include "regcache.h" |
1d75a658 | 27 | #include "regset.h" |
10d6c8cd DJ |
28 | #include "target.h" |
29 | #include "linux-nat.h" | |
c877c8e6 | 30 | #include <sys/types.h> |
c877c8e6 KB |
31 | #include <signal.h> |
32 | #include <sys/user.h> | |
33 | #include <sys/ioctl.h> | |
7ca18ed6 | 34 | #include <sys/uio.h> |
2555fe1a | 35 | #include "gdb_wait.h" |
c877c8e6 KB |
36 | #include <fcntl.h> |
37 | #include <sys/procfs.h> | |
5826e159 | 38 | #include "nat/gdb_ptrace.h" |
bcc0c096 | 39 | #include "inf-ptrace.h" |
c877c8e6 | 40 | |
0df8b418 | 41 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f | 42 | #include "gregset.h" |
16333c4f | 43 | #include "ppc-tdep.h" |
7284e1be UW |
44 | #include "ppc-linux-tdep.h" |
45 | ||
b7622095 LM |
46 | /* Required when using the AUXV. */ |
47 | #include "elf/common.h" | |
48 | #include "auxv.h" | |
49 | ||
bd64614e PFC |
50 | #include "arch/ppc-linux-common.h" |
51 | #include "arch/ppc-linux-tdesc.h" | |
514c5338 | 52 | #include "nat/ppc-linux.h" |
01904826 | 53 | |
6ffbb7ab | 54 | /* Similarly for the hardware watchpoint support. These requests are used |
926bf92d | 55 | when the PowerPC HWDEBUG ptrace interface is not available. */ |
e0d24f8d WZ |
56 | #ifndef PTRACE_GET_DEBUGREG |
57 | #define PTRACE_GET_DEBUGREG 25 | |
58 | #endif | |
59 | #ifndef PTRACE_SET_DEBUGREG | |
60 | #define PTRACE_SET_DEBUGREG 26 | |
61 | #endif | |
62 | #ifndef PTRACE_GETSIGINFO | |
63 | #define PTRACE_GETSIGINFO 0x4202 | |
64 | #endif | |
01904826 | 65 | |
926bf92d UW |
66 | /* These requests are used when the PowerPC HWDEBUG ptrace interface is |
67 | available. It exposes the debug facilities of PowerPC processors, as well | |
68 | as additional features of BookE processors, such as ranged breakpoints and | |
69 | watchpoints and hardware-accelerated condition evaluation. */ | |
6ffbb7ab TJB |
70 | #ifndef PPC_PTRACE_GETHWDBGINFO |
71 | ||
926bf92d UW |
72 | /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the PowerPC HWDEBUG |
73 | ptrace interface is not present in ptrace.h, so we'll have to pretty much | |
74 | include it all here so that the code at least compiles on older systems. */ | |
6ffbb7ab TJB |
75 | #define PPC_PTRACE_GETHWDBGINFO 0x89 |
76 | #define PPC_PTRACE_SETHWDEBUG 0x88 | |
77 | #define PPC_PTRACE_DELHWDEBUG 0x87 | |
78 | ||
79 | struct ppc_debug_info | |
80 | { | |
0df8b418 | 81 | uint32_t version; /* Only version 1 exists to date. */ |
6ffbb7ab TJB |
82 | uint32_t num_instruction_bps; |
83 | uint32_t num_data_bps; | |
84 | uint32_t num_condition_regs; | |
85 | uint32_t data_bp_alignment; | |
0df8b418 | 86 | uint32_t sizeof_condition; /* size of the DVC register. */ |
6ffbb7ab TJB |
87 | uint64_t features; |
88 | }; | |
89 | ||
90 | /* Features will have bits indicating whether there is support for: */ | |
91 | #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1 | |
92 | #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2 | |
93 | #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4 | |
94 | #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8 | |
95 | ||
96 | struct ppc_hw_breakpoint | |
97 | { | |
98 | uint32_t version; /* currently, version must be 1 */ | |
99 | uint32_t trigger_type; /* only some combinations allowed */ | |
100 | uint32_t addr_mode; /* address match mode */ | |
101 | uint32_t condition_mode; /* break/watchpoint condition flags */ | |
102 | uint64_t addr; /* break/watchpoint address */ | |
103 | uint64_t addr2; /* range end or mask */ | |
104 | uint64_t condition_value; /* contents of the DVC register */ | |
105 | }; | |
106 | ||
107 | /* Trigger type. */ | |
108 | #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1 | |
109 | #define PPC_BREAKPOINT_TRIGGER_READ 0x2 | |
110 | #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4 | |
111 | #define PPC_BREAKPOINT_TRIGGER_RW 0x6 | |
112 | ||
113 | /* Address mode. */ | |
114 | #define PPC_BREAKPOINT_MODE_EXACT 0x0 | |
115 | #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1 | |
116 | #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2 | |
117 | #define PPC_BREAKPOINT_MODE_MASK 0x3 | |
118 | ||
119 | /* Condition mode. */ | |
120 | #define PPC_BREAKPOINT_CONDITION_NONE 0x0 | |
121 | #define PPC_BREAKPOINT_CONDITION_AND 0x1 | |
122 | #define PPC_BREAKPOINT_CONDITION_EXACT 0x1 | |
123 | #define PPC_BREAKPOINT_CONDITION_OR 0x2 | |
124 | #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3 | |
125 | #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 | |
126 | #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16 | |
127 | #define PPC_BREAKPOINT_CONDITION_BE(n) \ | |
128 | (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT)) | |
129 | #endif /* PPC_PTRACE_GETHWDBGINFO */ | |
130 | ||
e23b9d6e UW |
131 | /* Feature defined on Linux kernel v3.9: DAWR interface, that enables wider |
132 | watchpoint (up to 512 bytes). */ | |
133 | #ifndef PPC_DEBUG_FEATURE_DATA_BP_DAWR | |
134 | #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10 | |
135 | #endif /* PPC_DEBUG_FEATURE_DATA_BP_DAWR */ | |
6ffbb7ab | 136 | |
1dfe79e8 SDJ |
137 | /* Similarly for the general-purpose (gp0 -- gp31) |
138 | and floating-point registers (fp0 -- fp31). */ | |
139 | #ifndef PTRACE_GETREGS | |
140 | #define PTRACE_GETREGS 12 | |
141 | #endif | |
142 | #ifndef PTRACE_SETREGS | |
143 | #define PTRACE_SETREGS 13 | |
144 | #endif | |
145 | #ifndef PTRACE_GETFPREGS | |
146 | #define PTRACE_GETFPREGS 14 | |
147 | #endif | |
148 | #ifndef PTRACE_SETFPREGS | |
149 | #define PTRACE_SETFPREGS 15 | |
150 | #endif | |
151 | ||
9abe5450 EZ |
152 | /* This oddity is because the Linux kernel defines elf_vrregset_t as |
153 | an array of 33 16 bytes long elements. I.e. it leaves out vrsave. | |
154 | However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return | |
155 | the vrsave as an extra 4 bytes at the end. I opted for creating a | |
156 | flat array of chars, so that it is easier to manipulate for gdb. | |
157 | ||
158 | There are 32 vector registers 16 bytes longs, plus a VSCR register | |
159 | which is only 4 bytes long, but is fetched as a 16 bytes | |
0df8b418 | 160 | quantity. Up to here we have the elf_vrregset_t structure. |
9abe5450 EZ |
161 | Appended to this there is space for the VRSAVE register: 4 bytes. |
162 | Even though this vrsave register is not included in the regset | |
163 | typedef, it is handled by the ptrace requests. | |
164 | ||
9abe5450 EZ |
165 | The layout is like this (where x is the actual value of the vscr reg): */ |
166 | ||
167 | /* *INDENT-OFF* */ | |
168 | /* | |
1d75a658 | 169 | Big-Endian: |
9abe5450 EZ |
170 | |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| |
171 | <-------> <-------><-------><-> | |
172 | VR0 VR31 VSCR VRSAVE | |
1d75a658 PFC |
173 | Little-Endian: |
174 | |.|.|.|.|.....|.|.|.|.||X|.|.|.||.| | |
175 | <-------> <-------><-------><-> | |
176 | VR0 VR31 VSCR VRSAVE | |
9abe5450 EZ |
177 | */ |
178 | /* *INDENT-ON* */ | |
179 | ||
d078308a | 180 | typedef char gdb_vrregset_t[PPC_LINUX_SIZEOF_VRREGSET]; |
9abe5450 | 181 | |
604c2f83 LM |
182 | /* This is the layout of the POWER7 VSX registers and the way they overlap |
183 | with the existing FPR and VMX registers. | |
184 | ||
185 | VSR doubleword 0 VSR doubleword 1 | |
186 | ---------------------------------------------------------------- | |
187 | VSR[0] | FPR[0] | | | |
188 | ---------------------------------------------------------------- | |
189 | VSR[1] | FPR[1] | | | |
190 | ---------------------------------------------------------------- | |
191 | | ... | | | |
192 | | ... | | | |
193 | ---------------------------------------------------------------- | |
194 | VSR[30] | FPR[30] | | | |
195 | ---------------------------------------------------------------- | |
196 | VSR[31] | FPR[31] | | | |
197 | ---------------------------------------------------------------- | |
198 | VSR[32] | VR[0] | | |
199 | ---------------------------------------------------------------- | |
200 | VSR[33] | VR[1] | | |
201 | ---------------------------------------------------------------- | |
202 | | ... | | |
203 | | ... | | |
204 | ---------------------------------------------------------------- | |
205 | VSR[62] | VR[30] | | |
206 | ---------------------------------------------------------------- | |
207 | VSR[63] | VR[31] | | |
208 | ---------------------------------------------------------------- | |
209 | ||
210 | VSX has 64 128bit registers. The first 32 registers overlap with | |
211 | the FP registers (doubleword 0) and hence extend them with additional | |
212 | 64 bits (doubleword 1). The other 32 regs overlap with the VMX | |
213 | registers. */ | |
d078308a | 214 | typedef char gdb_vsxregset_t[PPC_LINUX_SIZEOF_VSXREGSET]; |
01904826 | 215 | |
b021a221 | 216 | /* On PPC processors that support the Signal Processing Extension |
01904826 | 217 | (SPE) APU, the general-purpose registers are 64 bits long. |
411cb3f9 PG |
218 | However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER |
219 | ptrace calls only access the lower half of each register, to allow | |
220 | them to behave the same way they do on non-SPE systems. There's a | |
221 | separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that | |
222 | read and write the top halves of all the general-purpose registers | |
223 | at once, along with some SPE-specific registers. | |
01904826 JB |
224 | |
225 | GDB itself continues to claim the general-purpose registers are 32 | |
6ced10dd | 226 | bits long. It has unnamed raw registers that hold the upper halves |
b021a221 | 227 | of the gprs, and the full 64-bit SIMD views of the registers, |
6ced10dd JB |
228 | 'ev0' -- 'ev31', are pseudo-registers that splice the top and |
229 | bottom halves together. | |
01904826 JB |
230 | |
231 | This is the structure filled in by PTRACE_GETEVRREGS and written to | |
232 | the inferior's registers by PTRACE_SETEVRREGS. */ | |
233 | struct gdb_evrregset_t | |
234 | { | |
235 | unsigned long evr[32]; | |
236 | unsigned long long acc; | |
237 | unsigned long spefscr; | |
238 | }; | |
239 | ||
604c2f83 LM |
240 | /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and |
241 | PTRACE_SETVSXREGS requests, for reading and writing the VSX | |
242 | POWER7 registers 0 through 31. Zero if we've tried one of them and | |
243 | gotten an error. Note that VSX registers 32 through 63 overlap | |
244 | with VR registers 0 through 31. */ | |
245 | int have_ptrace_getsetvsxregs = 1; | |
01904826 JB |
246 | |
247 | /* Non-zero if our kernel may support the PTRACE_GETVRREGS and | |
248 | PTRACE_SETVRREGS requests, for reading and writing the Altivec | |
249 | registers. Zero if we've tried one of them and gotten an | |
250 | error. */ | |
9abe5450 EZ |
251 | int have_ptrace_getvrregs = 1; |
252 | ||
01904826 JB |
253 | /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and |
254 | PTRACE_SETEVRREGS requests, for reading and writing the SPE | |
255 | registers. Zero if we've tried one of them and gotten an | |
256 | error. */ | |
257 | int have_ptrace_getsetevrregs = 1; | |
258 | ||
1dfe79e8 SDJ |
259 | /* Non-zero if our kernel may support the PTRACE_GETREGS and |
260 | PTRACE_SETREGS requests, for reading and writing the | |
261 | general-purpose registers. Zero if we've tried one of | |
262 | them and gotten an error. */ | |
263 | int have_ptrace_getsetregs = 1; | |
264 | ||
265 | /* Non-zero if our kernel may support the PTRACE_GETFPREGS and | |
266 | PTRACE_SETFPREGS requests, for reading and writing the | |
267 | floating-pointers registers. Zero if we've tried one of | |
268 | them and gotten an error. */ | |
269 | int have_ptrace_getsetfpregs = 1; | |
270 | ||
f6ac5f3d PA |
271 | struct ppc_linux_nat_target final : public linux_nat_target |
272 | { | |
273 | /* Add our register access methods. */ | |
274 | void fetch_registers (struct regcache *, int) override; | |
275 | void store_registers (struct regcache *, int) override; | |
276 | ||
277 | /* Add our breakpoint/watchpoint methods. */ | |
278 | int can_use_hw_breakpoint (enum bptype, int, int) override; | |
279 | ||
280 | int insert_hw_breakpoint (struct gdbarch *, struct bp_target_info *) | |
281 | override; | |
282 | ||
283 | int remove_hw_breakpoint (struct gdbarch *, struct bp_target_info *) | |
284 | override; | |
285 | ||
286 | int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; | |
287 | ||
288 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
289 | struct expression *) override; | |
290 | ||
291 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
292 | struct expression *) override; | |
293 | ||
294 | int insert_mask_watchpoint (CORE_ADDR, CORE_ADDR, enum target_hw_bp_type) | |
295 | override; | |
296 | ||
297 | int remove_mask_watchpoint (CORE_ADDR, CORE_ADDR, enum target_hw_bp_type) | |
298 | override; | |
299 | ||
57810aa7 | 300 | bool stopped_by_watchpoint () override; |
f6ac5f3d | 301 | |
57810aa7 | 302 | bool stopped_data_address (CORE_ADDR *) override; |
f6ac5f3d | 303 | |
57810aa7 | 304 | bool watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override; |
f6ac5f3d | 305 | |
57810aa7 | 306 | bool can_accel_watchpoint_condition (CORE_ADDR, int, int, struct expression *) |
f6ac5f3d PA |
307 | override; |
308 | ||
309 | int masked_watch_num_registers (CORE_ADDR, CORE_ADDR) override; | |
310 | ||
311 | int ranged_break_num_registers () override; | |
312 | ||
313 | const struct target_desc *read_description () override; | |
314 | ||
315 | int auxv_parse (gdb_byte **readptr, | |
316 | gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp) | |
317 | override; | |
135340af PA |
318 | |
319 | /* Override linux_nat_target low methods. */ | |
320 | void low_new_thread (struct lwp_info *lp) override; | |
f6ac5f3d PA |
321 | }; |
322 | ||
323 | static ppc_linux_nat_target the_ppc_linux_nat_target; | |
324 | ||
16333c4f EZ |
325 | /* *INDENT-OFF* */ |
326 | /* registers layout, as presented by the ptrace interface: | |
327 | PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, | |
328 | PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15, | |
329 | PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23, | |
330 | PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31, | |
0df8b418 MS |
331 | PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, |
332 | PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14, | |
333 | PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, | |
334 | PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30, | |
335 | PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, | |
336 | PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46, | |
337 | PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, | |
338 | PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62, | |
16333c4f EZ |
339 | PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */ |
340 | /* *INDENT_ON * */ | |
c877c8e6 | 341 | |
45229ea4 | 342 | static int |
e101270f | 343 | ppc_register_u_addr (struct gdbarch *gdbarch, int regno) |
c877c8e6 | 344 | { |
16333c4f | 345 | int u_addr = -1; |
e101270f | 346 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
56d0d96a AC |
347 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
348 | interface, and not the wordsize of the program's ABI. */ | |
411cb3f9 | 349 | int wordsize = sizeof (long); |
16333c4f | 350 | |
0df8b418 | 351 | /* General purpose registers occupy 1 slot each in the buffer. */ |
8bf659e8 JB |
352 | if (regno >= tdep->ppc_gp0_regnum |
353 | && regno < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
26e75e5c | 354 | u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize); |
16333c4f | 355 | |
49ff75ad JB |
356 | /* Floating point regs: eight bytes each in both 32- and 64-bit |
357 | ptrace interfaces. Thus, two slots each in 32-bit interface, one | |
358 | slot each in 64-bit interface. */ | |
383f0f5b JB |
359 | if (tdep->ppc_fp0_regnum >= 0 |
360 | && regno >= tdep->ppc_fp0_regnum | |
366f009f JB |
361 | && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) |
362 | u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8); | |
16333c4f | 363 | |
0df8b418 | 364 | /* UISA special purpose registers: 1 slot each. */ |
e101270f | 365 | if (regno == gdbarch_pc_regnum (gdbarch)) |
49ff75ad | 366 | u_addr = PT_NIP * wordsize; |
dc5cfeb6 | 367 | if (regno == tdep->ppc_lr_regnum) |
49ff75ad | 368 | u_addr = PT_LNK * wordsize; |
dc5cfeb6 | 369 | if (regno == tdep->ppc_cr_regnum) |
49ff75ad | 370 | u_addr = PT_CCR * wordsize; |
dc5cfeb6 | 371 | if (regno == tdep->ppc_xer_regnum) |
49ff75ad | 372 | u_addr = PT_XER * wordsize; |
dc5cfeb6 | 373 | if (regno == tdep->ppc_ctr_regnum) |
49ff75ad | 374 | u_addr = PT_CTR * wordsize; |
f8c59253 | 375 | #ifdef PT_MQ |
dc5cfeb6 | 376 | if (regno == tdep->ppc_mq_regnum) |
49ff75ad | 377 | u_addr = PT_MQ * wordsize; |
f8c59253 | 378 | #endif |
dc5cfeb6 | 379 | if (regno == tdep->ppc_ps_regnum) |
49ff75ad | 380 | u_addr = PT_MSR * wordsize; |
7284e1be UW |
381 | if (regno == PPC_ORIG_R3_REGNUM) |
382 | u_addr = PT_ORIG_R3 * wordsize; | |
383 | if (regno == PPC_TRAP_REGNUM) | |
384 | u_addr = PT_TRAP * wordsize; | |
383f0f5b JB |
385 | if (tdep->ppc_fpscr_regnum >= 0 |
386 | && regno == tdep->ppc_fpscr_regnum) | |
8f135812 AC |
387 | { |
388 | /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the | |
389 | kernel headers incorrectly contained the 32-bit definition of | |
390 | PT_FPSCR. For the 32-bit definition, floating-point | |
391 | registers occupy two 32-bit "slots", and the FPSCR lives in | |
69abc51c | 392 | the second half of such a slot-pair (hence +1). For 64-bit, |
8f135812 AC |
393 | the FPSCR instead occupies the full 64-bit 2-word-slot and |
394 | hence no adjustment is necessary. Hack around this. */ | |
395 | if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1)) | |
396 | u_addr = (48 + 32) * wordsize; | |
69abc51c TJB |
397 | /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit |
398 | slot and not just its second word. The PT_FPSCR supplied when | |
399 | GDB is compiled as a 32-bit app doesn't reflect this. */ | |
400 | else if (wordsize == 4 && register_size (gdbarch, regno) == 8 | |
401 | && PT_FPSCR == (48 + 2*32 + 1)) | |
402 | u_addr = (48 + 2*32) * wordsize; | |
8f135812 AC |
403 | else |
404 | u_addr = PT_FPSCR * wordsize; | |
405 | } | |
16333c4f | 406 | return u_addr; |
c877c8e6 KB |
407 | } |
408 | ||
604c2f83 LM |
409 | /* The Linux kernel ptrace interface for POWER7 VSX registers uses the |
410 | registers set mechanism, as opposed to the interface for all the | |
411 | other registers, that stores/fetches each register individually. */ | |
412 | static void | |
2c3305f6 | 413 | fetch_vsx_registers (struct regcache *regcache, int tid, int regno) |
604c2f83 LM |
414 | { |
415 | int ret; | |
416 | gdb_vsxregset_t regs; | |
2c3305f6 | 417 | const struct regset *vsxregset = ppc_linux_vsxregset (); |
604c2f83 LM |
418 | |
419 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
420 | if (ret < 0) | |
421 | { | |
422 | if (errno == EIO) | |
423 | { | |
424 | have_ptrace_getsetvsxregs = 0; | |
425 | return; | |
426 | } | |
2c3305f6 | 427 | perror_with_name (_("Unable to fetch VSX registers")); |
604c2f83 LM |
428 | } |
429 | ||
2c3305f6 PFC |
430 | vsxregset->supply_regset (vsxregset, regcache, regno, ®s, |
431 | PPC_LINUX_SIZEOF_VSXREGSET); | |
604c2f83 LM |
432 | } |
433 | ||
9abe5450 EZ |
434 | /* The Linux kernel ptrace interface for AltiVec registers uses the |
435 | registers set mechanism, as opposed to the interface for all the | |
436 | other registers, that stores/fetches each register individually. */ | |
437 | static void | |
1d75a658 PFC |
438 | fetch_altivec_registers (struct regcache *regcache, int tid, |
439 | int regno) | |
9abe5450 EZ |
440 | { |
441 | int ret; | |
9abe5450 | 442 | gdb_vrregset_t regs; |
ac7936df | 443 | struct gdbarch *gdbarch = regcache->arch (); |
1d75a658 | 444 | const struct regset *vrregset = ppc_linux_vrregset (gdbarch); |
9abe5450 EZ |
445 | |
446 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
447 | if (ret < 0) | |
448 | { | |
449 | if (errno == EIO) | |
450 | { | |
451 | have_ptrace_getvrregs = 0; | |
452 | return; | |
453 | } | |
1d75a658 | 454 | perror_with_name (_("Unable to fetch AltiVec registers")); |
9abe5450 | 455 | } |
1d75a658 PFC |
456 | |
457 | vrregset->supply_regset (vrregset, regcache, regno, ®s, | |
458 | PPC_LINUX_SIZEOF_VRREGSET); | |
9abe5450 EZ |
459 | } |
460 | ||
01904826 JB |
461 | /* Fetch the top 32 bits of TID's general-purpose registers and the |
462 | SPE-specific registers, and place the results in EVRREGSET. If we | |
463 | don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with | |
464 | zeros. | |
465 | ||
466 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
467 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
468 | set_spe_registers. */ | |
469 | static void | |
470 | get_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
471 | { | |
472 | if (have_ptrace_getsetevrregs) | |
473 | { | |
474 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0) | |
475 | return; | |
476 | else | |
477 | { | |
478 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported; | |
479 | we just return zeros. */ | |
480 | if (errno == EIO) | |
481 | have_ptrace_getsetevrregs = 0; | |
482 | else | |
483 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 484 | perror_with_name (_("Unable to fetch SPE registers")); |
01904826 JB |
485 | } |
486 | } | |
487 | ||
488 | memset (evrregset, 0, sizeof (*evrregset)); | |
489 | } | |
490 | ||
6ced10dd JB |
491 | /* Supply values from TID for SPE-specific raw registers: the upper |
492 | halves of the GPRs, the accumulator, and the spefscr. REGNO must | |
493 | be the number of an upper half register, acc, spefscr, or -1 to | |
494 | supply the values of all registers. */ | |
01904826 | 495 | static void |
56be3814 | 496 | fetch_spe_register (struct regcache *regcache, int tid, int regno) |
01904826 | 497 | { |
ac7936df | 498 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 499 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
01904826 JB |
500 | struct gdb_evrregset_t evrregs; |
501 | ||
6ced10dd | 502 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 503 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 504 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 505 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 506 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 507 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
6ced10dd | 508 | |
01904826 JB |
509 | get_spe_registers (tid, &evrregs); |
510 | ||
6ced10dd | 511 | if (regno == -1) |
01904826 | 512 | { |
6ced10dd JB |
513 | int i; |
514 | ||
515 | for (i = 0; i < ppc_num_gprs; i++) | |
73e1c03f | 516 | regcache->raw_supply (tdep->ppc_ev0_upper_regnum + i, &evrregs.evr[i]); |
01904826 | 517 | } |
6ced10dd JB |
518 | else if (tdep->ppc_ev0_upper_regnum <= regno |
519 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
73e1c03f SM |
520 | regcache->raw_supply (regno, |
521 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); | |
6ced10dd JB |
522 | |
523 | if (regno == -1 | |
524 | || regno == tdep->ppc_acc_regnum) | |
73e1c03f | 525 | regcache->raw_supply (tdep->ppc_acc_regnum, &evrregs.acc); |
6ced10dd JB |
526 | |
527 | if (regno == -1 | |
528 | || regno == tdep->ppc_spefscr_regnum) | |
73e1c03f | 529 | regcache->raw_supply (tdep->ppc_spefscr_regnum, &evrregs.spefscr); |
01904826 JB |
530 | } |
531 | ||
7ca18ed6 EBM |
532 | /* Use ptrace to fetch all registers from the register set with note |
533 | type REGSET_ID, size REGSIZE, and layout described by REGSET, from | |
534 | process/thread TID and supply their values to REGCACHE. If ptrace | |
535 | returns ENODATA to indicate the regset is unavailable, mark the | |
536 | registers as unavailable in REGCACHE. */ | |
537 | ||
538 | static void | |
539 | fetch_regset (struct regcache *regcache, int tid, | |
540 | int regset_id, int regsetsize, const struct regset *regset) | |
541 | { | |
542 | void *buf = alloca (regsetsize); | |
543 | struct iovec iov; | |
544 | ||
545 | iov.iov_base = buf; | |
546 | iov.iov_len = regsetsize; | |
547 | ||
548 | if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) < 0) | |
549 | { | |
550 | if (errno == ENODATA) | |
551 | regset->supply_regset (regset, regcache, -1, NULL, regsetsize); | |
552 | else | |
553 | perror_with_name (_("Couldn't get register set")); | |
554 | } | |
555 | else | |
556 | regset->supply_regset (regset, regcache, -1, buf, regsetsize); | |
557 | } | |
558 | ||
559 | /* Use ptrace to store register REGNUM of the regset with note type | |
560 | REGSET_ID, size REGSETSIZE, and layout described by REGSET, from | |
561 | REGCACHE back to process/thread TID. If REGNUM is -1 all registers | |
562 | in the set are collected and stored. */ | |
563 | ||
564 | static void | |
565 | store_regset (const struct regcache *regcache, int tid, int regnum, | |
566 | int regset_id, int regsetsize, const struct regset *regset) | |
567 | { | |
568 | void *buf = alloca (regsetsize); | |
569 | struct iovec iov; | |
570 | ||
571 | iov.iov_base = buf; | |
572 | iov.iov_len = regsetsize; | |
573 | ||
574 | /* Make sure that the buffer that will be stored has up to date values | |
575 | for the registers that won't be collected. */ | |
576 | if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) < 0) | |
577 | perror_with_name (_("Couldn't get register set")); | |
578 | ||
579 | regset->collect_regset (regset, regcache, regnum, buf, regsetsize); | |
580 | ||
581 | if (ptrace (PTRACE_SETREGSET, tid, regset_id, &iov) < 0) | |
582 | perror_with_name (_("Couldn't set register set")); | |
583 | } | |
584 | ||
585 | /* Check whether the kernel provides a register set with number | |
586 | REGSET_ID of size REGSETSIZE for process/thread TID. */ | |
587 | ||
588 | static bool | |
589 | check_regset (int tid, int regset_id, int regsetsize) | |
590 | { | |
591 | void *buf = alloca (regsetsize); | |
592 | struct iovec iov; | |
593 | ||
594 | iov.iov_base = buf; | |
595 | iov.iov_len = regsetsize; | |
596 | ||
597 | if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) >= 0 | |
598 | || errno == ENODATA) | |
599 | return true; | |
600 | else | |
601 | return false; | |
602 | } | |
603 | ||
45229ea4 | 604 | static void |
56be3814 | 605 | fetch_register (struct regcache *regcache, int tid, int regno) |
45229ea4 | 606 | { |
ac7936df | 607 | struct gdbarch *gdbarch = regcache->arch (); |
7ca18ed6 | 608 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
45229ea4 | 609 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 610 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
4a19ea35 | 611 | int bytes_transferred; |
0f068fb5 | 612 | gdb_byte buf[PPC_MAX_REGISTER_SIZE]; |
45229ea4 | 613 | |
be8626e0 | 614 | if (altivec_register_p (gdbarch, regno)) |
9abe5450 EZ |
615 | { |
616 | /* If this is the first time through, or if it is not the first | |
617 | time through, and we have comfirmed that there is kernel | |
618 | support for such a ptrace request, then go and fetch the | |
619 | register. */ | |
620 | if (have_ptrace_getvrregs) | |
621 | { | |
1d75a658 | 622 | fetch_altivec_registers (regcache, tid, regno); |
9abe5450 EZ |
623 | return; |
624 | } | |
625 | /* If we have discovered that there is no ptrace support for | |
626 | AltiVec registers, fall through and return zeroes, because | |
627 | regaddr will be -1 in this case. */ | |
628 | } | |
3d907528 | 629 | else if (vsx_register_p (gdbarch, regno)) |
604c2f83 LM |
630 | { |
631 | if (have_ptrace_getsetvsxregs) | |
632 | { | |
2c3305f6 | 633 | fetch_vsx_registers (regcache, tid, regno); |
604c2f83 LM |
634 | return; |
635 | } | |
636 | } | |
be8626e0 | 637 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 638 | { |
56be3814 | 639 | fetch_spe_register (regcache, tid, regno); |
01904826 JB |
640 | return; |
641 | } | |
7ca18ed6 EBM |
642 | else if (regno == PPC_DSCR_REGNUM) |
643 | { | |
644 | gdb_assert (tdep->ppc_dscr_regnum != -1); | |
645 | ||
646 | fetch_regset (regcache, tid, NT_PPC_DSCR, | |
647 | PPC_LINUX_SIZEOF_DSCRREGSET, | |
648 | &ppc32_linux_dscrregset); | |
649 | return; | |
650 | } | |
651 | else if (regno == PPC_PPR_REGNUM) | |
652 | { | |
653 | gdb_assert (tdep->ppc_ppr_regnum != -1); | |
654 | ||
655 | fetch_regset (regcache, tid, NT_PPC_PPR, | |
656 | PPC_LINUX_SIZEOF_PPRREGSET, | |
657 | &ppc32_linux_pprregset); | |
658 | return; | |
659 | } | |
f2cf6173 EBM |
660 | else if (regno == PPC_TAR_REGNUM) |
661 | { | |
662 | gdb_assert (tdep->ppc_tar_regnum != -1); | |
663 | ||
664 | fetch_regset (regcache, tid, NT_PPC_TAR, | |
665 | PPC_LINUX_SIZEOF_TARREGSET, | |
666 | &ppc32_linux_tarregset); | |
667 | return; | |
668 | } | |
9abe5450 | 669 | |
45229ea4 EZ |
670 | if (regaddr == -1) |
671 | { | |
40a6adc1 | 672 | memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ |
73e1c03f | 673 | regcache->raw_supply (regno, buf); |
45229ea4 EZ |
674 | return; |
675 | } | |
676 | ||
411cb3f9 | 677 | /* Read the raw register using sizeof(long) sized chunks. On a |
56d0d96a AC |
678 | 32-bit platform, 64-bit floating-point registers will require two |
679 | transfers. */ | |
4a19ea35 | 680 | for (bytes_transferred = 0; |
40a6adc1 | 681 | bytes_transferred < register_size (gdbarch, regno); |
411cb3f9 | 682 | bytes_transferred += sizeof (long)) |
45229ea4 | 683 | { |
11fde611 JK |
684 | long l; |
685 | ||
45229ea4 | 686 | errno = 0; |
11fde611 | 687 | l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); |
411cb3f9 | 688 | regaddr += sizeof (long); |
45229ea4 EZ |
689 | if (errno != 0) |
690 | { | |
bc97b3ba | 691 | char message[128]; |
8c042590 PM |
692 | xsnprintf (message, sizeof (message), "reading register %s (#%d)", |
693 | gdbarch_register_name (gdbarch, regno), regno); | |
bc97b3ba | 694 | perror_with_name (message); |
45229ea4 | 695 | } |
11fde611 | 696 | memcpy (&buf[bytes_transferred], &l, sizeof (l)); |
45229ea4 | 697 | } |
56d0d96a | 698 | |
4a19ea35 JB |
699 | /* Now supply the register. Keep in mind that the regcache's idea |
700 | of the register's size may not be a multiple of sizeof | |
411cb3f9 | 701 | (long). */ |
40a6adc1 | 702 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
4a19ea35 JB |
703 | { |
704 | /* Little-endian values are always found at the left end of the | |
705 | bytes transferred. */ | |
73e1c03f | 706 | regcache->raw_supply (regno, buf); |
4a19ea35 | 707 | } |
40a6adc1 | 708 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
709 | { |
710 | /* Big-endian values are found at the right end of the bytes | |
711 | transferred. */ | |
40a6adc1 | 712 | size_t padding = (bytes_transferred - register_size (gdbarch, regno)); |
73e1c03f | 713 | regcache->raw_supply (regno, buf + padding); |
4a19ea35 JB |
714 | } |
715 | else | |
a44bddec | 716 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 717 | _("fetch_register: unexpected byte order: %d"), |
40a6adc1 | 718 | gdbarch_byte_order (gdbarch)); |
45229ea4 EZ |
719 | } |
720 | ||
1dfe79e8 SDJ |
721 | /* This function actually issues the request to ptrace, telling |
722 | it to get all general-purpose registers and put them into the | |
723 | specified regset. | |
724 | ||
725 | If the ptrace request does not exist, this function returns 0 | |
726 | and properly sets the have_ptrace_* flag. If the request fails, | |
727 | this function calls perror_with_name. Otherwise, if the request | |
728 | succeeds, then the regcache gets filled and 1 is returned. */ | |
729 | static int | |
730 | fetch_all_gp_regs (struct regcache *regcache, int tid) | |
731 | { | |
1dfe79e8 SDJ |
732 | gdb_gregset_t gregset; |
733 | ||
734 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
735 | { | |
736 | if (errno == EIO) | |
737 | { | |
738 | have_ptrace_getsetregs = 0; | |
739 | return 0; | |
740 | } | |
741 | perror_with_name (_("Couldn't get general-purpose registers.")); | |
742 | } | |
743 | ||
744 | supply_gregset (regcache, (const gdb_gregset_t *) &gregset); | |
745 | ||
746 | return 1; | |
747 | } | |
748 | ||
749 | /* This is a wrapper for the fetch_all_gp_regs function. It is | |
750 | responsible for verifying if this target has the ptrace request | |
751 | that can be used to fetch all general-purpose registers at one | |
752 | shot. If it doesn't, then we should fetch them using the | |
753 | old-fashioned way, which is to iterate over the registers and | |
754 | request them one by one. */ | |
755 | static void | |
756 | fetch_gp_regs (struct regcache *regcache, int tid) | |
757 | { | |
ac7936df | 758 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
759 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
760 | int i; | |
761 | ||
762 | if (have_ptrace_getsetregs) | |
763 | if (fetch_all_gp_regs (regcache, tid)) | |
764 | return; | |
765 | ||
766 | /* If we've hit this point, it doesn't really matter which | |
767 | architecture we are using. We just need to read the | |
768 | registers in the "old-fashioned way". */ | |
769 | for (i = 0; i < ppc_num_gprs; i++) | |
770 | fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i); | |
771 | } | |
772 | ||
773 | /* This function actually issues the request to ptrace, telling | |
774 | it to get all floating-point registers and put them into the | |
775 | specified regset. | |
776 | ||
777 | If the ptrace request does not exist, this function returns 0 | |
778 | and properly sets the have_ptrace_* flag. If the request fails, | |
779 | this function calls perror_with_name. Otherwise, if the request | |
780 | succeeds, then the regcache gets filled and 1 is returned. */ | |
781 | static int | |
782 | fetch_all_fp_regs (struct regcache *regcache, int tid) | |
783 | { | |
784 | gdb_fpregset_t fpregs; | |
785 | ||
786 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
787 | { | |
788 | if (errno == EIO) | |
789 | { | |
790 | have_ptrace_getsetfpregs = 0; | |
791 | return 0; | |
792 | } | |
793 | perror_with_name (_("Couldn't get floating-point registers.")); | |
794 | } | |
795 | ||
796 | supply_fpregset (regcache, (const gdb_fpregset_t *) &fpregs); | |
797 | ||
798 | return 1; | |
799 | } | |
800 | ||
801 | /* This is a wrapper for the fetch_all_fp_regs function. It is | |
802 | responsible for verifying if this target has the ptrace request | |
803 | that can be used to fetch all floating-point registers at one | |
804 | shot. If it doesn't, then we should fetch them using the | |
805 | old-fashioned way, which is to iterate over the registers and | |
806 | request them one by one. */ | |
807 | static void | |
808 | fetch_fp_regs (struct regcache *regcache, int tid) | |
809 | { | |
ac7936df | 810 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
811 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
812 | int i; | |
813 | ||
814 | if (have_ptrace_getsetfpregs) | |
815 | if (fetch_all_fp_regs (regcache, tid)) | |
816 | return; | |
817 | ||
818 | /* If we've hit this point, it doesn't really matter which | |
819 | architecture we are using. We just need to read the | |
820 | registers in the "old-fashioned way". */ | |
821 | for (i = 0; i < ppc_num_fprs; i++) | |
822 | fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
823 | } | |
824 | ||
45229ea4 | 825 | static void |
56be3814 | 826 | fetch_ppc_registers (struct regcache *regcache, int tid) |
45229ea4 | 827 | { |
ac7936df | 828 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 829 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9abe5450 | 830 | |
1dfe79e8 | 831 | fetch_gp_regs (regcache, tid); |
32b99774 | 832 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 833 | fetch_fp_regs (regcache, tid); |
40a6adc1 | 834 | fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 835 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 836 | fetch_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 837 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 838 | fetch_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 839 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 840 | fetch_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 841 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 842 | fetch_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 843 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 844 | fetch_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 845 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 846 | fetch_register (regcache, tid, tdep->ppc_mq_regnum); |
7284e1be UW |
847 | if (ppc_linux_trap_reg_p (gdbarch)) |
848 | { | |
849 | fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
850 | fetch_register (regcache, tid, PPC_TRAP_REGNUM); | |
851 | } | |
32b99774 | 852 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 853 | fetch_register (regcache, tid, tdep->ppc_fpscr_regnum); |
9abe5450 EZ |
854 | if (have_ptrace_getvrregs) |
855 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
1d75a658 | 856 | fetch_altivec_registers (regcache, tid, -1); |
604c2f83 LM |
857 | if (have_ptrace_getsetvsxregs) |
858 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
2c3305f6 | 859 | fetch_vsx_registers (regcache, tid, -1); |
6ced10dd | 860 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 861 | fetch_spe_register (regcache, tid, -1); |
7ca18ed6 EBM |
862 | if (tdep->ppc_ppr_regnum != -1) |
863 | fetch_regset (regcache, tid, NT_PPC_PPR, | |
864 | PPC_LINUX_SIZEOF_PPRREGSET, | |
865 | &ppc32_linux_pprregset); | |
866 | if (tdep->ppc_dscr_regnum != -1) | |
867 | fetch_regset (regcache, tid, NT_PPC_DSCR, | |
868 | PPC_LINUX_SIZEOF_DSCRREGSET, | |
869 | &ppc32_linux_dscrregset); | |
f2cf6173 EBM |
870 | if (tdep->ppc_tar_regnum != -1) |
871 | fetch_regset (regcache, tid, NT_PPC_TAR, | |
872 | PPC_LINUX_SIZEOF_TARREGSET, | |
873 | &ppc32_linux_tarregset); | |
45229ea4 EZ |
874 | } |
875 | ||
876 | /* Fetch registers from the child process. Fetch all registers if | |
877 | regno == -1, otherwise fetch all general registers or all floating | |
878 | point registers depending upon the value of regno. */ | |
f6ac5f3d PA |
879 | void |
880 | ppc_linux_nat_target::fetch_registers (struct regcache *regcache, int regno) | |
45229ea4 | 881 | { |
222312d3 | 882 | pid_t tid = get_ptrace_pid (regcache->ptid ()); |
05f13b9c | 883 | |
9abe5450 | 884 | if (regno == -1) |
56be3814 | 885 | fetch_ppc_registers (regcache, tid); |
45229ea4 | 886 | else |
56be3814 | 887 | fetch_register (regcache, tid, regno); |
45229ea4 EZ |
888 | } |
889 | ||
604c2f83 | 890 | static void |
2c3305f6 | 891 | store_vsx_registers (const struct regcache *regcache, int tid, int regno) |
604c2f83 LM |
892 | { |
893 | int ret; | |
894 | gdb_vsxregset_t regs; | |
2c3305f6 | 895 | const struct regset *vsxregset = ppc_linux_vsxregset (); |
604c2f83 | 896 | |
9fe70b4f | 897 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); |
604c2f83 LM |
898 | if (ret < 0) |
899 | { | |
900 | if (errno == EIO) | |
901 | { | |
902 | have_ptrace_getsetvsxregs = 0; | |
903 | return; | |
904 | } | |
2c3305f6 | 905 | perror_with_name (_("Unable to fetch VSX registers")); |
604c2f83 LM |
906 | } |
907 | ||
2c3305f6 PFC |
908 | vsxregset->collect_regset (vsxregset, regcache, regno, ®s, |
909 | PPC_LINUX_SIZEOF_VSXREGSET); | |
604c2f83 LM |
910 | |
911 | ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); | |
912 | if (ret < 0) | |
2c3305f6 | 913 | perror_with_name (_("Unable to store VSX registers")); |
604c2f83 LM |
914 | } |
915 | ||
9abe5450 | 916 | static void |
1d75a658 PFC |
917 | store_altivec_registers (const struct regcache *regcache, int tid, |
918 | int regno) | |
9abe5450 EZ |
919 | { |
920 | int ret; | |
9abe5450 | 921 | gdb_vrregset_t regs; |
ac7936df | 922 | struct gdbarch *gdbarch = regcache->arch (); |
1d75a658 | 923 | const struct regset *vrregset = ppc_linux_vrregset (gdbarch); |
9abe5450 EZ |
924 | |
925 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
926 | if (ret < 0) | |
927 | { | |
928 | if (errno == EIO) | |
929 | { | |
930 | have_ptrace_getvrregs = 0; | |
931 | return; | |
932 | } | |
1d75a658 | 933 | perror_with_name (_("Unable to fetch AltiVec registers")); |
9abe5450 EZ |
934 | } |
935 | ||
1d75a658 PFC |
936 | vrregset->collect_regset (vrregset, regcache, regno, ®s, |
937 | PPC_LINUX_SIZEOF_VRREGSET); | |
9abe5450 EZ |
938 | |
939 | ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); | |
940 | if (ret < 0) | |
1d75a658 | 941 | perror_with_name (_("Unable to store AltiVec registers")); |
9abe5450 EZ |
942 | } |
943 | ||
01904826 JB |
944 | /* Assuming TID referrs to an SPE process, set the top halves of TID's |
945 | general-purpose registers and its SPE-specific registers to the | |
946 | values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do | |
947 | nothing. | |
948 | ||
949 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
950 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
951 | get_spe_registers. */ | |
952 | static void | |
953 | set_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
954 | { | |
955 | if (have_ptrace_getsetevrregs) | |
956 | { | |
957 | if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0) | |
958 | return; | |
959 | else | |
960 | { | |
961 | /* EIO means that the PTRACE_SETEVRREGS request isn't | |
962 | supported; we fail silently, and don't try the call | |
963 | again. */ | |
964 | if (errno == EIO) | |
965 | have_ptrace_getsetevrregs = 0; | |
966 | else | |
967 | /* Anything else needs to be reported. */ | |
e2e0b3e5 | 968 | perror_with_name (_("Unable to set SPE registers")); |
01904826 JB |
969 | } |
970 | } | |
971 | } | |
972 | ||
6ced10dd JB |
973 | /* Write GDB's value for the SPE-specific raw register REGNO to TID. |
974 | If REGNO is -1, write the values of all the SPE-specific | |
975 | registers. */ | |
01904826 | 976 | static void |
56be3814 | 977 | store_spe_register (const struct regcache *regcache, int tid, int regno) |
01904826 | 978 | { |
ac7936df | 979 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 980 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
01904826 JB |
981 | struct gdb_evrregset_t evrregs; |
982 | ||
6ced10dd | 983 | gdb_assert (sizeof (evrregs.evr[0]) |
40a6adc1 | 984 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 985 | gdb_assert (sizeof (evrregs.acc) |
40a6adc1 | 986 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 987 | gdb_assert (sizeof (evrregs.spefscr) |
40a6adc1 | 988 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
01904826 | 989 | |
6ced10dd JB |
990 | if (regno == -1) |
991 | /* Since we're going to write out every register, the code below | |
992 | should store to every field of evrregs; if that doesn't happen, | |
993 | make it obvious by initializing it with suspicious values. */ | |
994 | memset (&evrregs, 42, sizeof (evrregs)); | |
995 | else | |
996 | /* We can only read and write the entire EVR register set at a | |
997 | time, so to write just a single register, we do a | |
998 | read-modify-write maneuver. */ | |
999 | get_spe_registers (tid, &evrregs); | |
1000 | ||
1001 | if (regno == -1) | |
01904826 | 1002 | { |
6ced10dd JB |
1003 | int i; |
1004 | ||
1005 | for (i = 0; i < ppc_num_gprs; i++) | |
34a79281 SM |
1006 | regcache->raw_collect (tdep->ppc_ev0_upper_regnum + i, |
1007 | &evrregs.evr[i]); | |
01904826 | 1008 | } |
6ced10dd JB |
1009 | else if (tdep->ppc_ev0_upper_regnum <= regno |
1010 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
34a79281 SM |
1011 | regcache->raw_collect (regno, |
1012 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); | |
6ced10dd JB |
1013 | |
1014 | if (regno == -1 | |
1015 | || regno == tdep->ppc_acc_regnum) | |
34a79281 SM |
1016 | regcache->raw_collect (tdep->ppc_acc_regnum, |
1017 | &evrregs.acc); | |
6ced10dd JB |
1018 | |
1019 | if (regno == -1 | |
1020 | || regno == tdep->ppc_spefscr_regnum) | |
34a79281 SM |
1021 | regcache->raw_collect (tdep->ppc_spefscr_regnum, |
1022 | &evrregs.spefscr); | |
01904826 JB |
1023 | |
1024 | /* Write back the modified register set. */ | |
1025 | set_spe_registers (tid, &evrregs); | |
1026 | } | |
1027 | ||
45229ea4 | 1028 | static void |
56be3814 | 1029 | store_register (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 1030 | { |
ac7936df | 1031 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 1032 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
45229ea4 | 1033 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 1034 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
52f0bd74 | 1035 | int i; |
4a19ea35 | 1036 | size_t bytes_to_transfer; |
0f068fb5 | 1037 | gdb_byte buf[PPC_MAX_REGISTER_SIZE]; |
45229ea4 | 1038 | |
be8626e0 | 1039 | if (altivec_register_p (gdbarch, regno)) |
45229ea4 | 1040 | { |
1d75a658 | 1041 | store_altivec_registers (regcache, tid, regno); |
45229ea4 EZ |
1042 | return; |
1043 | } | |
3d907528 | 1044 | else if (vsx_register_p (gdbarch, regno)) |
604c2f83 | 1045 | { |
2c3305f6 | 1046 | store_vsx_registers (regcache, tid, regno); |
604c2f83 LM |
1047 | return; |
1048 | } | |
be8626e0 | 1049 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 1050 | { |
56be3814 | 1051 | store_spe_register (regcache, tid, regno); |
01904826 JB |
1052 | return; |
1053 | } | |
7ca18ed6 EBM |
1054 | else if (regno == PPC_DSCR_REGNUM) |
1055 | { | |
1056 | gdb_assert (tdep->ppc_dscr_regnum != -1); | |
1057 | ||
1058 | store_regset (regcache, tid, regno, NT_PPC_DSCR, | |
1059 | PPC_LINUX_SIZEOF_DSCRREGSET, | |
1060 | &ppc32_linux_dscrregset); | |
1061 | return; | |
1062 | } | |
1063 | else if (regno == PPC_PPR_REGNUM) | |
1064 | { | |
1065 | gdb_assert (tdep->ppc_ppr_regnum != -1); | |
1066 | ||
1067 | store_regset (regcache, tid, regno, NT_PPC_PPR, | |
1068 | PPC_LINUX_SIZEOF_PPRREGSET, | |
1069 | &ppc32_linux_pprregset); | |
1070 | return; | |
1071 | } | |
f2cf6173 EBM |
1072 | else if (regno == PPC_TAR_REGNUM) |
1073 | { | |
1074 | gdb_assert (tdep->ppc_tar_regnum != -1); | |
1075 | ||
1076 | store_regset (regcache, tid, regno, NT_PPC_TAR, | |
1077 | PPC_LINUX_SIZEOF_TARREGSET, | |
1078 | &ppc32_linux_tarregset); | |
1079 | return; | |
1080 | } | |
45229ea4 | 1081 | |
9abe5450 EZ |
1082 | if (regaddr == -1) |
1083 | return; | |
1084 | ||
4a19ea35 JB |
1085 | /* First collect the register. Keep in mind that the regcache's |
1086 | idea of the register's size may not be a multiple of sizeof | |
411cb3f9 | 1087 | (long). */ |
56d0d96a | 1088 | memset (buf, 0, sizeof buf); |
40a6adc1 MD |
1089 | bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); |
1090 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) | |
4a19ea35 JB |
1091 | { |
1092 | /* Little-endian values always sit at the left end of the buffer. */ | |
34a79281 | 1093 | regcache->raw_collect (regno, buf); |
4a19ea35 | 1094 | } |
40a6adc1 | 1095 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
1096 | { |
1097 | /* Big-endian values sit at the right end of the buffer. */ | |
40a6adc1 | 1098 | size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); |
34a79281 | 1099 | regcache->raw_collect (regno, buf + padding); |
4a19ea35 JB |
1100 | } |
1101 | ||
411cb3f9 | 1102 | for (i = 0; i < bytes_to_transfer; i += sizeof (long)) |
45229ea4 | 1103 | { |
11fde611 JK |
1104 | long l; |
1105 | ||
1106 | memcpy (&l, &buf[i], sizeof (l)); | |
45229ea4 | 1107 | errno = 0; |
11fde611 | 1108 | ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l); |
411cb3f9 | 1109 | regaddr += sizeof (long); |
e3f36dbd KB |
1110 | |
1111 | if (errno == EIO | |
7284e1be UW |
1112 | && (regno == tdep->ppc_fpscr_regnum |
1113 | || regno == PPC_ORIG_R3_REGNUM | |
1114 | || regno == PPC_TRAP_REGNUM)) | |
e3f36dbd | 1115 | { |
7284e1be UW |
1116 | /* Some older kernel versions don't allow fpscr, orig_r3 |
1117 | or trap to be written. */ | |
e3f36dbd KB |
1118 | continue; |
1119 | } | |
1120 | ||
45229ea4 EZ |
1121 | if (errno != 0) |
1122 | { | |
bc97b3ba | 1123 | char message[128]; |
8c042590 PM |
1124 | xsnprintf (message, sizeof (message), "writing register %s (#%d)", |
1125 | gdbarch_register_name (gdbarch, regno), regno); | |
bc97b3ba | 1126 | perror_with_name (message); |
45229ea4 EZ |
1127 | } |
1128 | } | |
1129 | } | |
1130 | ||
1dfe79e8 SDJ |
1131 | /* This function actually issues the request to ptrace, telling |
1132 | it to store all general-purpose registers present in the specified | |
1133 | regset. | |
1134 | ||
1135 | If the ptrace request does not exist, this function returns 0 | |
1136 | and properly sets the have_ptrace_* flag. If the request fails, | |
1137 | this function calls perror_with_name. Otherwise, if the request | |
1138 | succeeds, then the regcache is stored and 1 is returned. */ | |
1139 | static int | |
1140 | store_all_gp_regs (const struct regcache *regcache, int tid, int regno) | |
1141 | { | |
1dfe79e8 SDJ |
1142 | gdb_gregset_t gregset; |
1143 | ||
1144 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
1145 | { | |
1146 | if (errno == EIO) | |
1147 | { | |
1148 | have_ptrace_getsetregs = 0; | |
1149 | return 0; | |
1150 | } | |
1151 | perror_with_name (_("Couldn't get general-purpose registers.")); | |
1152 | } | |
1153 | ||
1154 | fill_gregset (regcache, &gregset, regno); | |
1155 | ||
1156 | if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0) | |
1157 | { | |
1158 | if (errno == EIO) | |
1159 | { | |
1160 | have_ptrace_getsetregs = 0; | |
1161 | return 0; | |
1162 | } | |
1163 | perror_with_name (_("Couldn't set general-purpose registers.")); | |
1164 | } | |
1165 | ||
1166 | return 1; | |
1167 | } | |
1168 | ||
1169 | /* This is a wrapper for the store_all_gp_regs function. It is | |
1170 | responsible for verifying if this target has the ptrace request | |
1171 | that can be used to store all general-purpose registers at one | |
1172 | shot. If it doesn't, then we should store them using the | |
1173 | old-fashioned way, which is to iterate over the registers and | |
1174 | store them one by one. */ | |
45229ea4 | 1175 | static void |
1dfe79e8 | 1176 | store_gp_regs (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 1177 | { |
ac7936df | 1178 | struct gdbarch *gdbarch = regcache->arch (); |
40a6adc1 | 1179 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1dfe79e8 SDJ |
1180 | int i; |
1181 | ||
1182 | if (have_ptrace_getsetregs) | |
1183 | if (store_all_gp_regs (regcache, tid, regno)) | |
1184 | return; | |
1185 | ||
1186 | /* If we hit this point, it doesn't really matter which | |
1187 | architecture we are using. We just need to store the | |
1188 | registers in the "old-fashioned way". */ | |
6ced10dd | 1189 | for (i = 0; i < ppc_num_gprs; i++) |
56be3814 | 1190 | store_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
1dfe79e8 SDJ |
1191 | } |
1192 | ||
1193 | /* This function actually issues the request to ptrace, telling | |
1194 | it to store all floating-point registers present in the specified | |
1195 | regset. | |
1196 | ||
1197 | If the ptrace request does not exist, this function returns 0 | |
1198 | and properly sets the have_ptrace_* flag. If the request fails, | |
1199 | this function calls perror_with_name. Otherwise, if the request | |
1200 | succeeds, then the regcache is stored and 1 is returned. */ | |
1201 | static int | |
1202 | store_all_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1203 | { | |
1204 | gdb_fpregset_t fpregs; | |
1205 | ||
1206 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1207 | { | |
1208 | if (errno == EIO) | |
1209 | { | |
1210 | have_ptrace_getsetfpregs = 0; | |
1211 | return 0; | |
1212 | } | |
1213 | perror_with_name (_("Couldn't get floating-point registers.")); | |
1214 | } | |
1215 | ||
1216 | fill_fpregset (regcache, &fpregs, regno); | |
1217 | ||
1218 | if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1219 | { | |
1220 | if (errno == EIO) | |
1221 | { | |
1222 | have_ptrace_getsetfpregs = 0; | |
1223 | return 0; | |
1224 | } | |
1225 | perror_with_name (_("Couldn't set floating-point registers.")); | |
1226 | } | |
1227 | ||
1228 | return 1; | |
1229 | } | |
1230 | ||
1231 | /* This is a wrapper for the store_all_fp_regs function. It is | |
1232 | responsible for verifying if this target has the ptrace request | |
1233 | that can be used to store all floating-point registers at one | |
1234 | shot. If it doesn't, then we should store them using the | |
1235 | old-fashioned way, which is to iterate over the registers and | |
1236 | store them one by one. */ | |
1237 | static void | |
1238 | store_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1239 | { | |
ac7936df | 1240 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
1241 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1242 | int i; | |
1243 | ||
1244 | if (have_ptrace_getsetfpregs) | |
1245 | if (store_all_fp_regs (regcache, tid, regno)) | |
1246 | return; | |
1247 | ||
1248 | /* If we hit this point, it doesn't really matter which | |
1249 | architecture we are using. We just need to store the | |
1250 | registers in the "old-fashioned way". */ | |
1251 | for (i = 0; i < ppc_num_fprs; i++) | |
1252 | store_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
1253 | } | |
1254 | ||
1255 | static void | |
1256 | store_ppc_registers (const struct regcache *regcache, int tid) | |
1257 | { | |
ac7936df | 1258 | struct gdbarch *gdbarch = regcache->arch (); |
1dfe79e8 SDJ |
1259 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1260 | ||
1261 | store_gp_regs (regcache, tid, -1); | |
32b99774 | 1262 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 1263 | store_fp_regs (regcache, tid, -1); |
40a6adc1 | 1264 | store_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 1265 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 1266 | store_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 1267 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 1268 | store_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 1269 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 1270 | store_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 1271 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 1272 | store_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 1273 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 1274 | store_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 1275 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 1276 | store_register (regcache, tid, tdep->ppc_mq_regnum); |
32b99774 | 1277 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 1278 | store_register (regcache, tid, tdep->ppc_fpscr_regnum); |
7284e1be UW |
1279 | if (ppc_linux_trap_reg_p (gdbarch)) |
1280 | { | |
1281 | store_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
1282 | store_register (regcache, tid, PPC_TRAP_REGNUM); | |
1283 | } | |
9abe5450 EZ |
1284 | if (have_ptrace_getvrregs) |
1285 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
1d75a658 | 1286 | store_altivec_registers (regcache, tid, -1); |
604c2f83 LM |
1287 | if (have_ptrace_getsetvsxregs) |
1288 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
2c3305f6 | 1289 | store_vsx_registers (regcache, tid, -1); |
6ced10dd | 1290 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 1291 | store_spe_register (regcache, tid, -1); |
7ca18ed6 EBM |
1292 | if (tdep->ppc_ppr_regnum != -1) |
1293 | store_regset (regcache, tid, -1, NT_PPC_PPR, | |
1294 | PPC_LINUX_SIZEOF_PPRREGSET, | |
1295 | &ppc32_linux_pprregset); | |
1296 | if (tdep->ppc_dscr_regnum != -1) | |
1297 | store_regset (regcache, tid, -1, NT_PPC_DSCR, | |
1298 | PPC_LINUX_SIZEOF_DSCRREGSET, | |
1299 | &ppc32_linux_dscrregset); | |
f2cf6173 EBM |
1300 | if (tdep->ppc_tar_regnum != -1) |
1301 | store_regset (regcache, tid, -1, NT_PPC_TAR, | |
1302 | PPC_LINUX_SIZEOF_TARREGSET, | |
1303 | &ppc32_linux_tarregset); | |
45229ea4 EZ |
1304 | } |
1305 | ||
6ffbb7ab | 1306 | /* Fetch the AT_HWCAP entry from the aux vector. */ |
0ec848ad | 1307 | static CORE_ADDR |
b261e0c5 | 1308 | ppc_linux_get_hwcap (void) |
6ffbb7ab TJB |
1309 | { |
1310 | CORE_ADDR field; | |
1311 | ||
8b88a78e | 1312 | if (target_auxv_search (current_top_target (), AT_HWCAP, &field) != 1) |
0ec848ad | 1313 | return 0; |
6ffbb7ab | 1314 | |
0ec848ad | 1315 | return field; |
6ffbb7ab TJB |
1316 | } |
1317 | ||
7ca18ed6 EBM |
1318 | /* Fetch the AT_HWCAP2 entry from the aux vector. */ |
1319 | ||
1320 | static CORE_ADDR | |
1321 | ppc_linux_get_hwcap2 (void) | |
1322 | { | |
1323 | CORE_ADDR field; | |
1324 | ||
1325 | if (target_auxv_search (current_top_target (), AT_HWCAP2, &field) != 1) | |
1326 | return 0; | |
1327 | ||
1328 | return field; | |
1329 | } | |
1330 | ||
6ffbb7ab | 1331 | /* The cached DABR value, to install in new threads. |
926bf92d UW |
1332 | This variable is used when the PowerPC HWDEBUG ptrace |
1333 | interface is not available. */ | |
6ffbb7ab TJB |
1334 | static long saved_dabr_value; |
1335 | ||
1336 | /* Global structure that will store information about the available | |
926bf92d UW |
1337 | features provided by the PowerPC HWDEBUG ptrace interface. */ |
1338 | static struct ppc_debug_info hwdebug_info; | |
6ffbb7ab TJB |
1339 | |
1340 | /* Global variable that holds the maximum number of slots that the | |
926bf92d UW |
1341 | kernel will use. This is only used when PowerPC HWDEBUG ptrace interface |
1342 | is available. */ | |
6ffbb7ab TJB |
1343 | static size_t max_slots_number = 0; |
1344 | ||
1345 | struct hw_break_tuple | |
1346 | { | |
1347 | long slot; | |
1348 | struct ppc_hw_breakpoint *hw_break; | |
1349 | }; | |
1350 | ||
1351 | /* This is an internal VEC created to store information about *points inserted | |
926bf92d UW |
1352 | for each thread. This is used when PowerPC HWDEBUG ptrace interface is |
1353 | available. */ | |
6ffbb7ab TJB |
1354 | typedef struct thread_points |
1355 | { | |
1356 | /* The TID to which this *point relates. */ | |
1357 | int tid; | |
1358 | /* Information about the *point, such as its address, type, etc. | |
1359 | ||
1360 | Each element inside this vector corresponds to a hardware | |
1361 | breakpoint or watchpoint in the thread represented by TID. The maximum | |
1362 | size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of | |
1363 | the tuple is NULL, then the position in the vector is free. */ | |
1364 | struct hw_break_tuple *hw_breaks; | |
1365 | } *thread_points_p; | |
1366 | DEF_VEC_P (thread_points_p); | |
1367 | ||
1368 | VEC(thread_points_p) *ppc_threads = NULL; | |
1369 | ||
926bf92d UW |
1370 | /* The version of the PowerPC HWDEBUG kernel interface that we will use, if |
1371 | available. */ | |
6ffbb7ab TJB |
1372 | #define PPC_DEBUG_CURRENT_VERSION 1 |
1373 | ||
926bf92d | 1374 | /* Returns non-zero if we support the PowerPC HWDEBUG ptrace interface. */ |
e0d24f8d | 1375 | static int |
926bf92d | 1376 | have_ptrace_hwdebug_interface (void) |
e0d24f8d | 1377 | { |
926bf92d | 1378 | static int have_ptrace_hwdebug_interface = -1; |
e0d24f8d | 1379 | |
926bf92d | 1380 | if (have_ptrace_hwdebug_interface == -1) |
6ffbb7ab TJB |
1381 | { |
1382 | int tid; | |
e0d24f8d | 1383 | |
e38504b3 | 1384 | tid = inferior_ptid.lwp (); |
6ffbb7ab | 1385 | if (tid == 0) |
e99b03dc | 1386 | tid = inferior_ptid.pid (); |
e0d24f8d | 1387 | |
926bf92d UW |
1388 | /* Check for kernel support for PowerPC HWDEBUG ptrace interface. */ |
1389 | if (ptrace (PPC_PTRACE_GETHWDBGINFO, tid, 0, &hwdebug_info) >= 0) | |
6ffbb7ab | 1390 | { |
926bf92d | 1391 | /* Check whether PowerPC HWDEBUG ptrace interface is functional and |
0c56f59b | 1392 | provides any supported feature. */ |
926bf92d | 1393 | if (hwdebug_info.features != 0) |
0c56f59b | 1394 | { |
926bf92d UW |
1395 | have_ptrace_hwdebug_interface = 1; |
1396 | max_slots_number = hwdebug_info.num_instruction_bps | |
1397 | + hwdebug_info.num_data_bps | |
1398 | + hwdebug_info.num_condition_regs; | |
1399 | return have_ptrace_hwdebug_interface; | |
0c56f59b | 1400 | } |
6ffbb7ab | 1401 | } |
926bf92d UW |
1402 | /* Old school interface and no PowerPC HWDEBUG ptrace support. */ |
1403 | have_ptrace_hwdebug_interface = 0; | |
1404 | memset (&hwdebug_info, 0, sizeof (struct ppc_debug_info)); | |
6ffbb7ab TJB |
1405 | } |
1406 | ||
926bf92d | 1407 | return have_ptrace_hwdebug_interface; |
e0d24f8d WZ |
1408 | } |
1409 | ||
f6ac5f3d PA |
1410 | int |
1411 | ppc_linux_nat_target::can_use_hw_breakpoint (enum bptype type, int cnt, int ot) | |
b7622095 | 1412 | { |
6ffbb7ab | 1413 | int total_hw_wp, total_hw_bp; |
b7622095 | 1414 | |
926bf92d | 1415 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab | 1416 | { |
926bf92d UW |
1417 | /* When PowerPC HWDEBUG ptrace interface is available, the number of |
1418 | available hardware watchpoints and breakpoints is stored at the | |
1419 | hwdebug_info struct. */ | |
1420 | total_hw_bp = hwdebug_info.num_instruction_bps; | |
1421 | total_hw_wp = hwdebug_info.num_data_bps; | |
6ffbb7ab TJB |
1422 | } |
1423 | else | |
1424 | { | |
926bf92d UW |
1425 | /* When we do not have PowerPC HWDEBUG ptrace interface, we should |
1426 | consider having 1 hardware watchpoint and no hardware breakpoints. */ | |
6ffbb7ab TJB |
1427 | total_hw_bp = 0; |
1428 | total_hw_wp = 1; | |
1429 | } | |
b7622095 | 1430 | |
6ffbb7ab TJB |
1431 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint |
1432 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
1433 | { | |
bb08bdbd | 1434 | if (cnt + ot > total_hw_wp) |
6ffbb7ab TJB |
1435 | return -1; |
1436 | } | |
1437 | else if (type == bp_hardware_breakpoint) | |
1438 | { | |
572f6555 EBM |
1439 | if (total_hw_bp == 0) |
1440 | { | |
1441 | /* No hardware breakpoint support. */ | |
1442 | return 0; | |
1443 | } | |
6ffbb7ab TJB |
1444 | if (cnt > total_hw_bp) |
1445 | return -1; | |
1446 | } | |
1447 | ||
926bf92d | 1448 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1449 | { |
1450 | int tid; | |
1451 | ptid_t ptid = inferior_ptid; | |
1452 | ||
0df8b418 MS |
1453 | /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG |
1454 | and whether the target has DABR. If either answer is no, the | |
1455 | ptrace call will return -1. Fail in that case. */ | |
e38504b3 | 1456 | tid = ptid.lwp (); |
6ffbb7ab | 1457 | if (tid == 0) |
e99b03dc | 1458 | tid = ptid.pid (); |
6ffbb7ab TJB |
1459 | |
1460 | if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1) | |
1461 | return 0; | |
1462 | } | |
1463 | ||
1464 | return 1; | |
b7622095 LM |
1465 | } |
1466 | ||
f6ac5f3d PA |
1467 | int |
1468 | ppc_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
e0d24f8d WZ |
1469 | { |
1470 | /* Handle sub-8-byte quantities. */ | |
1471 | if (len <= 0) | |
1472 | return 0; | |
1473 | ||
926bf92d UW |
1474 | /* The PowerPC HWDEBUG ptrace interface tells if there are alignment |
1475 | restrictions for watchpoints in the processors. In that case, we use that | |
1476 | information to determine the hardcoded watchable region for | |
1477 | watchpoints. */ | |
1478 | if (have_ptrace_hwdebug_interface ()) | |
6ffbb7ab | 1479 | { |
e23b9d6e | 1480 | int region_size; |
4feebbdd EBM |
1481 | /* Embedded DAC-based processors, like the PowerPC 440 have ranged |
1482 | watchpoints and can watch any access within an arbitrary memory | |
1483 | region. This is useful to watch arrays and structs, for instance. It | |
1484 | takes two hardware watchpoints though. */ | |
e09342b5 | 1485 | if (len > 1 |
926bf92d | 1486 | && hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE |
4feebbdd | 1487 | && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
e09342b5 | 1488 | return 2; |
e23b9d6e UW |
1489 | /* Check if the processor provides DAWR interface. */ |
1490 | if (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_DAWR) | |
1491 | /* DAWR interface allows to watch up to 512 byte wide ranges which | |
1492 | can't cross a 512 byte boundary. */ | |
1493 | region_size = 512; | |
1494 | else | |
1495 | region_size = hwdebug_info.data_bp_alignment; | |
4feebbdd EBM |
1496 | /* Server processors provide one hardware watchpoint and addr+len should |
1497 | fall in the watchable region provided by the ptrace interface. */ | |
e23b9d6e UW |
1498 | if (region_size |
1499 | && (addr + len > (addr & ~(region_size - 1)) + region_size)) | |
0cf6dd15 | 1500 | return 0; |
6ffbb7ab | 1501 | } |
b7622095 | 1502 | /* addr+len must fall in the 8 byte watchable region for DABR-based |
926bf92d UW |
1503 | processors (i.e., server processors). Without the new PowerPC HWDEBUG |
1504 | ptrace interface, DAC-based processors (i.e., embedded processors) will | |
1505 | use addresses aligned to 4-bytes due to the way the read/write flags are | |
6ffbb7ab TJB |
1506 | passed in the old ptrace interface. */ |
1507 | else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
1508 | && (addr + len) > (addr & ~3) + 4) | |
1509 | || (addr + len) > (addr & ~7) + 8) | |
e0d24f8d WZ |
1510 | return 0; |
1511 | ||
1512 | return 1; | |
1513 | } | |
1514 | ||
6ffbb7ab | 1515 | /* This function compares two ppc_hw_breakpoint structs field-by-field. */ |
e4166a49 | 1516 | static int |
926bf92d | 1517 | hwdebug_point_cmp (struct ppc_hw_breakpoint *a, struct ppc_hw_breakpoint *b) |
6ffbb7ab | 1518 | { |
ad422571 TJB |
1519 | return (a->trigger_type == b->trigger_type |
1520 | && a->addr_mode == b->addr_mode | |
1521 | && a->condition_mode == b->condition_mode | |
1522 | && a->addr == b->addr | |
1523 | && a->addr2 == b->addr2 | |
6ffbb7ab TJB |
1524 | && a->condition_value == b->condition_value); |
1525 | } | |
1526 | ||
1527 | /* This function can be used to retrieve a thread_points by the TID of the | |
1528 | related process/thread. If nothing has been found, and ALLOC_NEW is 0, | |
1529 | it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the | |
1530 | provided TID will be created and returned. */ | |
1531 | static struct thread_points * | |
926bf92d | 1532 | hwdebug_find_thread_points_by_tid (int tid, int alloc_new) |
6ffbb7ab TJB |
1533 | { |
1534 | int i; | |
1535 | struct thread_points *t; | |
1536 | ||
1537 | for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, t); i++) | |
1538 | if (t->tid == tid) | |
1539 | return t; | |
1540 | ||
1541 | t = NULL; | |
1542 | ||
1543 | /* Do we need to allocate a new point_item | |
1544 | if the wanted one does not exist? */ | |
1545 | if (alloc_new) | |
1546 | { | |
8d749320 SM |
1547 | t = XNEW (struct thread_points); |
1548 | t->hw_breaks = XCNEWVEC (struct hw_break_tuple, max_slots_number); | |
6ffbb7ab TJB |
1549 | t->tid = tid; |
1550 | VEC_safe_push (thread_points_p, ppc_threads, t); | |
1551 | } | |
1552 | ||
1553 | return t; | |
1554 | } | |
1555 | ||
1556 | /* This function is a generic wrapper that is responsible for inserting a | |
1557 | *point (i.e., calling `ptrace' in order to issue the request to the | |
1558 | kernel) and registering it internally in GDB. */ | |
1559 | static void | |
926bf92d | 1560 | hwdebug_insert_point (struct ppc_hw_breakpoint *b, int tid) |
6ffbb7ab TJB |
1561 | { |
1562 | int i; | |
1563 | long slot; | |
a90ecff8 | 1564 | gdb::unique_xmalloc_ptr<ppc_hw_breakpoint> p (XDUP (ppc_hw_breakpoint, b)); |
6ffbb7ab | 1565 | struct hw_break_tuple *hw_breaks; |
6ffbb7ab | 1566 | struct thread_points *t; |
6ffbb7ab | 1567 | |
6ffbb7ab | 1568 | errno = 0; |
a90ecff8 | 1569 | slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p.get ()); |
6ffbb7ab TJB |
1570 | if (slot < 0) |
1571 | perror_with_name (_("Unexpected error setting breakpoint or watchpoint")); | |
1572 | ||
1573 | /* Everything went fine, so we have to register this *point. */ | |
926bf92d | 1574 | t = hwdebug_find_thread_points_by_tid (tid, 1); |
6ffbb7ab TJB |
1575 | gdb_assert (t != NULL); |
1576 | hw_breaks = t->hw_breaks; | |
1577 | ||
1578 | /* Find a free element in the hw_breaks vector. */ | |
1579 | for (i = 0; i < max_slots_number; i++) | |
1580 | if (hw_breaks[i].hw_break == NULL) | |
1581 | { | |
1582 | hw_breaks[i].slot = slot; | |
a90ecff8 | 1583 | hw_breaks[i].hw_break = p.release (); |
6ffbb7ab TJB |
1584 | break; |
1585 | } | |
1586 | ||
1587 | gdb_assert (i != max_slots_number); | |
6ffbb7ab TJB |
1588 | } |
1589 | ||
1590 | /* This function is a generic wrapper that is responsible for removing a | |
1591 | *point (i.e., calling `ptrace' in order to issue the request to the | |
1592 | kernel), and unregistering it internally at GDB. */ | |
1593 | static void | |
926bf92d | 1594 | hwdebug_remove_point (struct ppc_hw_breakpoint *b, int tid) |
6ffbb7ab TJB |
1595 | { |
1596 | int i; | |
1597 | struct hw_break_tuple *hw_breaks; | |
1598 | struct thread_points *t; | |
1599 | ||
926bf92d | 1600 | t = hwdebug_find_thread_points_by_tid (tid, 0); |
6ffbb7ab TJB |
1601 | gdb_assert (t != NULL); |
1602 | hw_breaks = t->hw_breaks; | |
1603 | ||
1604 | for (i = 0; i < max_slots_number; i++) | |
926bf92d | 1605 | if (hw_breaks[i].hw_break && hwdebug_point_cmp (hw_breaks[i].hw_break, b)) |
6ffbb7ab TJB |
1606 | break; |
1607 | ||
1608 | gdb_assert (i != max_slots_number); | |
1609 | ||
1610 | /* We have to ignore ENOENT errors because the kernel implements hardware | |
1611 | breakpoints/watchpoints as "one-shot", that is, they are automatically | |
1612 | deleted when hit. */ | |
1613 | errno = 0; | |
1614 | if (ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot) < 0) | |
1615 | if (errno != ENOENT) | |
0df8b418 MS |
1616 | perror_with_name (_("Unexpected error deleting " |
1617 | "breakpoint or watchpoint")); | |
6ffbb7ab TJB |
1618 | |
1619 | xfree (hw_breaks[i].hw_break); | |
1620 | hw_breaks[i].hw_break = NULL; | |
1621 | } | |
9f0bdab8 | 1622 | |
f1310107 TJB |
1623 | /* Return the number of registers needed for a ranged breakpoint. */ |
1624 | ||
f6ac5f3d PA |
1625 | int |
1626 | ppc_linux_nat_target::ranged_break_num_registers () | |
f1310107 | 1627 | { |
926bf92d UW |
1628 | return ((have_ptrace_hwdebug_interface () |
1629 | && hwdebug_info.features & PPC_DEBUG_FEATURE_INSN_BP_RANGE)? | |
f1310107 TJB |
1630 | 2 : -1); |
1631 | } | |
1632 | ||
1633 | /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for | |
1634 | success, 1 if hardware breakpoints are not supported or -1 for failure. */ | |
1635 | ||
f6ac5f3d PA |
1636 | int |
1637 | ppc_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, | |
1638 | struct bp_target_info *bp_tgt) | |
e0d24f8d | 1639 | { |
9f0bdab8 | 1640 | struct lwp_info *lp; |
6ffbb7ab TJB |
1641 | struct ppc_hw_breakpoint p; |
1642 | ||
926bf92d | 1643 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1644 | return -1; |
1645 | ||
ad422571 TJB |
1646 | p.version = PPC_DEBUG_CURRENT_VERSION; |
1647 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | |
ad422571 | 1648 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
0d5ed153 | 1649 | p.addr = (uint64_t) (bp_tgt->placed_address = bp_tgt->reqstd_address); |
6ffbb7ab TJB |
1650 | p.condition_value = 0; |
1651 | ||
f1310107 TJB |
1652 | if (bp_tgt->length) |
1653 | { | |
1654 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
1655 | ||
1656 | /* The breakpoint will trigger if the address of the instruction is | |
1657 | within the defined range, as follows: p.addr <= address < p.addr2. */ | |
1658 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; | |
1659 | } | |
1660 | else | |
1661 | { | |
1662 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
1663 | p.addr2 = 0; | |
1664 | } | |
1665 | ||
4c38200f | 1666 | ALL_LWPS (lp) |
e38504b3 | 1667 | hwdebug_insert_point (&p, lp->ptid.lwp ()); |
6ffbb7ab TJB |
1668 | |
1669 | return 0; | |
1670 | } | |
1671 | ||
f6ac5f3d PA |
1672 | int |
1673 | ppc_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, | |
1674 | struct bp_target_info *bp_tgt) | |
6ffbb7ab | 1675 | { |
6ffbb7ab TJB |
1676 | struct lwp_info *lp; |
1677 | struct ppc_hw_breakpoint p; | |
b7622095 | 1678 | |
926bf92d | 1679 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
1680 | return -1; |
1681 | ||
ad422571 TJB |
1682 | p.version = PPC_DEBUG_CURRENT_VERSION; |
1683 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | |
ad422571 TJB |
1684 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
1685 | p.addr = (uint64_t) bp_tgt->placed_address; | |
6ffbb7ab TJB |
1686 | p.condition_value = 0; |
1687 | ||
f1310107 TJB |
1688 | if (bp_tgt->length) |
1689 | { | |
1690 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
1691 | ||
1692 | /* The breakpoint will trigger if the address of the instruction is within | |
1693 | the defined range, as follows: p.addr <= address < p.addr2. */ | |
1694 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; | |
1695 | } | |
1696 | else | |
1697 | { | |
1698 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
1699 | p.addr2 = 0; | |
1700 | } | |
1701 | ||
4c38200f | 1702 | ALL_LWPS (lp) |
e38504b3 | 1703 | hwdebug_remove_point (&p, lp->ptid.lwp ()); |
6ffbb7ab TJB |
1704 | |
1705 | return 0; | |
1706 | } | |
1707 | ||
1708 | static int | |
e76460db | 1709 | get_trigger_type (enum target_hw_bp_type type) |
6ffbb7ab TJB |
1710 | { |
1711 | int t; | |
1712 | ||
e76460db | 1713 | if (type == hw_read) |
6ffbb7ab | 1714 | t = PPC_BREAKPOINT_TRIGGER_READ; |
e76460db | 1715 | else if (type == hw_write) |
6ffbb7ab | 1716 | t = PPC_BREAKPOINT_TRIGGER_WRITE; |
b7622095 | 1717 | else |
6ffbb7ab TJB |
1718 | t = PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE; |
1719 | ||
1720 | return t; | |
1721 | } | |
1722 | ||
9c06b0b4 TJB |
1723 | /* Insert a new masked watchpoint at ADDR using the mask MASK. |
1724 | RW may be hw_read for a read watchpoint, hw_write for a write watchpoint | |
1725 | or hw_access for an access watchpoint. Returns 0 on success and throws | |
1726 | an error on failure. */ | |
1727 | ||
f6ac5f3d PA |
1728 | int |
1729 | ppc_linux_nat_target::insert_mask_watchpoint (CORE_ADDR addr, CORE_ADDR mask, | |
1730 | target_hw_bp_type rw) | |
9c06b0b4 | 1731 | { |
9c06b0b4 TJB |
1732 | struct lwp_info *lp; |
1733 | struct ppc_hw_breakpoint p; | |
1734 | ||
926bf92d | 1735 | gdb_assert (have_ptrace_hwdebug_interface ()); |
9c06b0b4 TJB |
1736 | |
1737 | p.version = PPC_DEBUG_CURRENT_VERSION; | |
1738 | p.trigger_type = get_trigger_type (rw); | |
1739 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; | |
1740 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
1741 | p.addr = addr; | |
1742 | p.addr2 = mask; | |
1743 | p.condition_value = 0; | |
1744 | ||
4c38200f | 1745 | ALL_LWPS (lp) |
e38504b3 | 1746 | hwdebug_insert_point (&p, lp->ptid.lwp ()); |
9c06b0b4 TJB |
1747 | |
1748 | return 0; | |
1749 | } | |
1750 | ||
1751 | /* Remove a masked watchpoint at ADDR with the mask MASK. | |
1752 | RW may be hw_read for a read watchpoint, hw_write for a write watchpoint | |
1753 | or hw_access for an access watchpoint. Returns 0 on success and throws | |
1754 | an error on failure. */ | |
1755 | ||
f6ac5f3d PA |
1756 | int |
1757 | ppc_linux_nat_target::remove_mask_watchpoint (CORE_ADDR addr, CORE_ADDR mask, | |
1758 | target_hw_bp_type rw) | |
9c06b0b4 | 1759 | { |
9c06b0b4 TJB |
1760 | struct lwp_info *lp; |
1761 | struct ppc_hw_breakpoint p; | |
1762 | ||
926bf92d | 1763 | gdb_assert (have_ptrace_hwdebug_interface ()); |
9c06b0b4 TJB |
1764 | |
1765 | p.version = PPC_DEBUG_CURRENT_VERSION; | |
1766 | p.trigger_type = get_trigger_type (rw); | |
1767 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; | |
1768 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
1769 | p.addr = addr; | |
1770 | p.addr2 = mask; | |
1771 | p.condition_value = 0; | |
1772 | ||
4c38200f | 1773 | ALL_LWPS (lp) |
e38504b3 | 1774 | hwdebug_remove_point (&p, lp->ptid.lwp ()); |
9c06b0b4 TJB |
1775 | |
1776 | return 0; | |
1777 | } | |
1778 | ||
0cf6dd15 TJB |
1779 | /* Check whether we have at least one free DVC register. */ |
1780 | static int | |
1781 | can_use_watchpoint_cond_accel (void) | |
1782 | { | |
1783 | struct thread_points *p; | |
e38504b3 | 1784 | int tid = inferior_ptid.lwp (); |
926bf92d | 1785 | int cnt = hwdebug_info.num_condition_regs, i; |
0cf6dd15 | 1786 | |
926bf92d | 1787 | if (!have_ptrace_hwdebug_interface () || cnt == 0) |
0cf6dd15 TJB |
1788 | return 0; |
1789 | ||
926bf92d | 1790 | p = hwdebug_find_thread_points_by_tid (tid, 0); |
0cf6dd15 TJB |
1791 | |
1792 | if (p) | |
1793 | { | |
1794 | for (i = 0; i < max_slots_number; i++) | |
1795 | if (p->hw_breaks[i].hw_break != NULL | |
1796 | && (p->hw_breaks[i].hw_break->condition_mode | |
1797 | != PPC_BREAKPOINT_CONDITION_NONE)) | |
1798 | cnt--; | |
1799 | ||
1800 | /* There are no available slots now. */ | |
1801 | if (cnt <= 0) | |
1802 | return 0; | |
1803 | } | |
1804 | ||
1805 | return 1; | |
1806 | } | |
1807 | ||
1808 | /* Calculate the enable bits and the contents of the Data Value Compare | |
1809 | debug register present in BookE processors. | |
1810 | ||
1811 | ADDR is the address to be watched, LEN is the length of watched data | |
1812 | and DATA_VALUE is the value which will trigger the watchpoint. | |
1813 | On exit, CONDITION_MODE will hold the enable bits for the DVC, and | |
1814 | CONDITION_VALUE will hold the value which should be put in the | |
1815 | DVC register. */ | |
1816 | static void | |
1817 | calculate_dvc (CORE_ADDR addr, int len, CORE_ADDR data_value, | |
1818 | uint32_t *condition_mode, uint64_t *condition_value) | |
1819 | { | |
1820 | int i, num_byte_enable, align_offset, num_bytes_off_dvc, | |
1821 | rightmost_enabled_byte; | |
1822 | CORE_ADDR addr_end_data, addr_end_dvc; | |
1823 | ||
1824 | /* The DVC register compares bytes within fixed-length windows which | |
1825 | are word-aligned, with length equal to that of the DVC register. | |
1826 | We need to calculate where our watch region is relative to that | |
1827 | window and enable comparison of the bytes which fall within it. */ | |
1828 | ||
926bf92d | 1829 | align_offset = addr % hwdebug_info.sizeof_condition; |
0cf6dd15 TJB |
1830 | addr_end_data = addr + len; |
1831 | addr_end_dvc = (addr - align_offset | |
926bf92d | 1832 | + hwdebug_info.sizeof_condition); |
0cf6dd15 TJB |
1833 | num_bytes_off_dvc = (addr_end_data > addr_end_dvc)? |
1834 | addr_end_data - addr_end_dvc : 0; | |
1835 | num_byte_enable = len - num_bytes_off_dvc; | |
1836 | /* Here, bytes are numbered from right to left. */ | |
1837 | rightmost_enabled_byte = (addr_end_data < addr_end_dvc)? | |
1838 | addr_end_dvc - addr_end_data : 0; | |
1839 | ||
1840 | *condition_mode = PPC_BREAKPOINT_CONDITION_AND; | |
1841 | for (i = 0; i < num_byte_enable; i++) | |
0df8b418 MS |
1842 | *condition_mode |
1843 | |= PPC_BREAKPOINT_CONDITION_BE (i + rightmost_enabled_byte); | |
0cf6dd15 TJB |
1844 | |
1845 | /* Now we need to match the position within the DVC of the comparison | |
1846 | value with where the watch region is relative to the window | |
1847 | (i.e., the ALIGN_OFFSET). */ | |
1848 | ||
1849 | *condition_value = ((uint64_t) data_value >> num_bytes_off_dvc * 8 | |
1850 | << rightmost_enabled_byte * 8); | |
1851 | } | |
1852 | ||
1853 | /* Return the number of memory locations that need to be accessed to | |
1854 | evaluate the expression which generated the given value chain. | |
1855 | Returns -1 if there's any register access involved, or if there are | |
1856 | other kinds of values which are not acceptable in a condition | |
1857 | expression (e.g., lval_computed or lval_internalvar). */ | |
1858 | static int | |
a6535de1 | 1859 | num_memory_accesses (const std::vector<value_ref_ptr> &chain) |
0cf6dd15 TJB |
1860 | { |
1861 | int found_memory_cnt = 0; | |
0cf6dd15 TJB |
1862 | |
1863 | /* The idea here is that evaluating an expression generates a series | |
1864 | of values, one holding the value of every subexpression. (The | |
1865 | expression a*b+c has five subexpressions: a, b, a*b, c, and | |
1866 | a*b+c.) GDB's values hold almost enough information to establish | |
1867 | the criteria given above --- they identify memory lvalues, | |
1868 | register lvalues, computed values, etcetera. So we can evaluate | |
1869 | the expression, and then scan the chain of values that leaves | |
1870 | behind to determine the memory locations involved in the evaluation | |
1871 | of an expression. | |
1872 | ||
1873 | However, I don't think that the values returned by inferior | |
1874 | function calls are special in any way. So this function may not | |
1875 | notice that an expression contains an inferior function call. | |
1876 | FIXME. */ | |
1877 | ||
a6535de1 | 1878 | for (const value_ref_ptr &iter : chain) |
0cf6dd15 | 1879 | { |
a6535de1 TT |
1880 | struct value *v = iter.get (); |
1881 | ||
0cf6dd15 TJB |
1882 | /* Constants and values from the history are fine. */ |
1883 | if (VALUE_LVAL (v) == not_lval || deprecated_value_modifiable (v) == 0) | |
1884 | continue; | |
1885 | else if (VALUE_LVAL (v) == lval_memory) | |
1886 | { | |
1887 | /* A lazy memory lvalue is one that GDB never needed to fetch; | |
1888 | we either just used its address (e.g., `a' in `a.b') or | |
1889 | we never needed it at all (e.g., `a' in `a,b'). */ | |
1890 | if (!value_lazy (v)) | |
1891 | found_memory_cnt++; | |
1892 | } | |
0df8b418 | 1893 | /* Other kinds of values are not fine. */ |
0cf6dd15 TJB |
1894 | else |
1895 | return -1; | |
1896 | } | |
1897 | ||
1898 | return found_memory_cnt; | |
1899 | } | |
1900 | ||
1901 | /* Verifies whether the expression COND can be implemented using the | |
1902 | DVC (Data Value Compare) register in BookE processors. The expression | |
1903 | must test the watch value for equality with a constant expression. | |
1904 | If the function returns 1, DATA_VALUE will contain the constant against | |
e7db58ea TJB |
1905 | which the watch value should be compared and LEN will contain the size |
1906 | of the constant. */ | |
0cf6dd15 TJB |
1907 | static int |
1908 | check_condition (CORE_ADDR watch_addr, struct expression *cond, | |
e7db58ea | 1909 | CORE_ADDR *data_value, int *len) |
0cf6dd15 TJB |
1910 | { |
1911 | int pc = 1, num_accesses_left, num_accesses_right; | |
a6535de1 TT |
1912 | struct value *left_val, *right_val; |
1913 | std::vector<value_ref_ptr> left_chain, right_chain; | |
0cf6dd15 TJB |
1914 | |
1915 | if (cond->elts[0].opcode != BINOP_EQUAL) | |
1916 | return 0; | |
1917 | ||
3a1115a0 | 1918 | fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain, 0); |
0cf6dd15 TJB |
1919 | num_accesses_left = num_memory_accesses (left_chain); |
1920 | ||
1921 | if (left_val == NULL || num_accesses_left < 0) | |
a6535de1 | 1922 | return 0; |
0cf6dd15 | 1923 | |
3a1115a0 | 1924 | fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain, 0); |
0cf6dd15 TJB |
1925 | num_accesses_right = num_memory_accesses (right_chain); |
1926 | ||
1927 | if (right_val == NULL || num_accesses_right < 0) | |
a6535de1 | 1928 | return 0; |
0cf6dd15 TJB |
1929 | |
1930 | if (num_accesses_left == 1 && num_accesses_right == 0 | |
1931 | && VALUE_LVAL (left_val) == lval_memory | |
1932 | && value_address (left_val) == watch_addr) | |
e7db58ea TJB |
1933 | { |
1934 | *data_value = value_as_long (right_val); | |
1935 | ||
1936 | /* DATA_VALUE is the constant in RIGHT_VAL, but actually has | |
1937 | the same type as the memory region referenced by LEFT_VAL. */ | |
1938 | *len = TYPE_LENGTH (check_typedef (value_type (left_val))); | |
1939 | } | |
0cf6dd15 TJB |
1940 | else if (num_accesses_left == 0 && num_accesses_right == 1 |
1941 | && VALUE_LVAL (right_val) == lval_memory | |
1942 | && value_address (right_val) == watch_addr) | |
e7db58ea TJB |
1943 | { |
1944 | *data_value = value_as_long (left_val); | |
1945 | ||
1946 | /* DATA_VALUE is the constant in LEFT_VAL, but actually has | |
1947 | the same type as the memory region referenced by RIGHT_VAL. */ | |
1948 | *len = TYPE_LENGTH (check_typedef (value_type (right_val))); | |
1949 | } | |
0cf6dd15 | 1950 | else |
a6535de1 | 1951 | return 0; |
0cf6dd15 TJB |
1952 | |
1953 | return 1; | |
1954 | } | |
1955 | ||
1956 | /* Return non-zero if the target is capable of using hardware to evaluate | |
1957 | the condition expression, thus only triggering the watchpoint when it is | |
1958 | true. */ | |
57810aa7 | 1959 | bool |
f6ac5f3d PA |
1960 | ppc_linux_nat_target::can_accel_watchpoint_condition (CORE_ADDR addr, int len, |
1961 | int rw, | |
1962 | struct expression *cond) | |
0cf6dd15 TJB |
1963 | { |
1964 | CORE_ADDR data_value; | |
1965 | ||
926bf92d UW |
1966 | return (have_ptrace_hwdebug_interface () |
1967 | && hwdebug_info.num_condition_regs > 0 | |
e7db58ea | 1968 | && check_condition (addr, cond, &data_value, &len)); |
0cf6dd15 TJB |
1969 | } |
1970 | ||
e09342b5 TJB |
1971 | /* Set up P with the parameters necessary to request a watchpoint covering |
1972 | LEN bytes starting at ADDR and if possible with condition expression COND | |
1973 | evaluated by hardware. INSERT tells if we are creating a request for | |
1974 | inserting or removing the watchpoint. */ | |
1975 | ||
1976 | static void | |
1977 | create_watchpoint_request (struct ppc_hw_breakpoint *p, CORE_ADDR addr, | |
e76460db PA |
1978 | int len, enum target_hw_bp_type type, |
1979 | struct expression *cond, int insert) | |
e09342b5 | 1980 | { |
f16c4e8b | 1981 | if (len == 1 |
926bf92d | 1982 | || !(hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE)) |
e09342b5 TJB |
1983 | { |
1984 | int use_condition; | |
1985 | CORE_ADDR data_value; | |
1986 | ||
1987 | use_condition = (insert? can_use_watchpoint_cond_accel () | |
926bf92d | 1988 | : hwdebug_info.num_condition_regs > 0); |
e7db58ea TJB |
1989 | if (cond && use_condition && check_condition (addr, cond, |
1990 | &data_value, &len)) | |
e09342b5 TJB |
1991 | calculate_dvc (addr, len, data_value, &p->condition_mode, |
1992 | &p->condition_value); | |
1993 | else | |
1994 | { | |
1995 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
1996 | p->condition_value = 0; | |
1997 | } | |
1998 | ||
1999 | p->addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
2000 | p->addr2 = 0; | |
2001 | } | |
2002 | else | |
2003 | { | |
2004 | p->addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
2005 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
2006 | p->condition_value = 0; | |
2007 | ||
2008 | /* The watchpoint will trigger if the address of the memory access is | |
2009 | within the defined range, as follows: p->addr <= address < p->addr2. | |
2010 | ||
2011 | Note that the above sentence just documents how ptrace interprets | |
2012 | its arguments; the watchpoint is set to watch the range defined by | |
2013 | the user _inclusively_, as specified by the user interface. */ | |
2014 | p->addr2 = (uint64_t) addr + len; | |
2015 | } | |
2016 | ||
2017 | p->version = PPC_DEBUG_CURRENT_VERSION; | |
e76460db | 2018 | p->trigger_type = get_trigger_type (type); |
e09342b5 TJB |
2019 | p->addr = (uint64_t) addr; |
2020 | } | |
2021 | ||
f6ac5f3d PA |
2022 | int |
2023 | ppc_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, | |
2024 | enum target_hw_bp_type type, | |
2025 | struct expression *cond) | |
6ffbb7ab TJB |
2026 | { |
2027 | struct lwp_info *lp; | |
6ffbb7ab TJB |
2028 | int ret = -1; |
2029 | ||
926bf92d | 2030 | if (have_ptrace_hwdebug_interface ()) |
e0d24f8d | 2031 | { |
6ffbb7ab TJB |
2032 | struct ppc_hw_breakpoint p; |
2033 | ||
e76460db | 2034 | create_watchpoint_request (&p, addr, len, type, cond, 1); |
6ffbb7ab | 2035 | |
4c38200f | 2036 | ALL_LWPS (lp) |
e38504b3 | 2037 | hwdebug_insert_point (&p, lp->ptid.lwp ()); |
6ffbb7ab TJB |
2038 | |
2039 | ret = 0; | |
e0d24f8d | 2040 | } |
6ffbb7ab TJB |
2041 | else |
2042 | { | |
2043 | long dabr_value; | |
2044 | long read_mode, write_mode; | |
e0d24f8d | 2045 | |
6ffbb7ab TJB |
2046 | if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
2047 | { | |
2048 | /* PowerPC 440 requires only the read/write flags to be passed | |
2049 | to the kernel. */ | |
ad422571 | 2050 | read_mode = 1; |
6ffbb7ab TJB |
2051 | write_mode = 2; |
2052 | } | |
2053 | else | |
2054 | { | |
2055 | /* PowerPC 970 and other DABR-based processors are required to pass | |
2056 | the Breakpoint Translation bit together with the flags. */ | |
ad422571 | 2057 | read_mode = 5; |
6ffbb7ab TJB |
2058 | write_mode = 6; |
2059 | } | |
1c86e440 | 2060 | |
6ffbb7ab | 2061 | dabr_value = addr & ~(read_mode | write_mode); |
e76460db | 2062 | switch (type) |
6ffbb7ab TJB |
2063 | { |
2064 | case hw_read: | |
2065 | /* Set read and translate bits. */ | |
2066 | dabr_value |= read_mode; | |
2067 | break; | |
2068 | case hw_write: | |
2069 | /* Set write and translate bits. */ | |
2070 | dabr_value |= write_mode; | |
2071 | break; | |
2072 | case hw_access: | |
2073 | /* Set read, write and translate bits. */ | |
2074 | dabr_value |= read_mode | write_mode; | |
2075 | break; | |
2076 | } | |
1c86e440 | 2077 | |
6ffbb7ab TJB |
2078 | saved_dabr_value = dabr_value; |
2079 | ||
4c38200f | 2080 | ALL_LWPS (lp) |
e38504b3 | 2081 | if (ptrace (PTRACE_SET_DEBUGREG, lp->ptid.lwp (), 0, |
0cf6dd15 | 2082 | saved_dabr_value) < 0) |
6ffbb7ab TJB |
2083 | return -1; |
2084 | ||
2085 | ret = 0; | |
2086 | } | |
2087 | ||
2088 | return ret; | |
e0d24f8d WZ |
2089 | } |
2090 | ||
f6ac5f3d PA |
2091 | int |
2092 | ppc_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, | |
2093 | enum target_hw_bp_type type, | |
2094 | struct expression *cond) | |
e0d24f8d | 2095 | { |
9f0bdab8 | 2096 | struct lwp_info *lp; |
6ffbb7ab | 2097 | int ret = -1; |
9f0bdab8 | 2098 | |
926bf92d | 2099 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2100 | { |
2101 | struct ppc_hw_breakpoint p; | |
2102 | ||
e76460db | 2103 | create_watchpoint_request (&p, addr, len, type, cond, 0); |
6ffbb7ab | 2104 | |
4c38200f | 2105 | ALL_LWPS (lp) |
e38504b3 | 2106 | hwdebug_remove_point (&p, lp->ptid.lwp ()); |
6ffbb7ab TJB |
2107 | |
2108 | ret = 0; | |
2109 | } | |
2110 | else | |
2111 | { | |
2112 | saved_dabr_value = 0; | |
4c38200f | 2113 | ALL_LWPS (lp) |
e38504b3 | 2114 | if (ptrace (PTRACE_SET_DEBUGREG, lp->ptid.lwp (), 0, |
0cf6dd15 | 2115 | saved_dabr_value) < 0) |
6ffbb7ab TJB |
2116 | return -1; |
2117 | ||
2118 | ret = 0; | |
2119 | } | |
2120 | ||
2121 | return ret; | |
e0d24f8d WZ |
2122 | } |
2123 | ||
135340af PA |
2124 | void |
2125 | ppc_linux_nat_target::low_new_thread (struct lwp_info *lp) | |
e0d24f8d | 2126 | { |
e38504b3 | 2127 | int tid = lp->ptid.lwp (); |
6ffbb7ab | 2128 | |
926bf92d | 2129 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2130 | { |
2131 | int i; | |
2132 | struct thread_points *p; | |
2133 | struct hw_break_tuple *hw_breaks; | |
2134 | ||
2135 | if (VEC_empty (thread_points_p, ppc_threads)) | |
2136 | return; | |
2137 | ||
0df8b418 | 2138 | /* Get a list of breakpoints from any thread. */ |
6ffbb7ab TJB |
2139 | p = VEC_last (thread_points_p, ppc_threads); |
2140 | hw_breaks = p->hw_breaks; | |
2141 | ||
0df8b418 | 2142 | /* Copy that thread's breakpoints and watchpoints to the new thread. */ |
6ffbb7ab TJB |
2143 | for (i = 0; i < max_slots_number; i++) |
2144 | if (hw_breaks[i].hw_break) | |
aacbb8a5 LM |
2145 | { |
2146 | /* Older kernels did not make new threads inherit their parent | |
2147 | thread's debug state, so we always clear the slot and replicate | |
2148 | the debug state ourselves, ensuring compatibility with all | |
2149 | kernels. */ | |
2150 | ||
2151 | /* The ppc debug resource accounting is done through "slots". | |
2152 | Ask the kernel the deallocate this specific *point's slot. */ | |
2153 | ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot); | |
2154 | ||
926bf92d | 2155 | hwdebug_insert_point (hw_breaks[i].hw_break, tid); |
aacbb8a5 | 2156 | } |
6ffbb7ab TJB |
2157 | } |
2158 | else | |
2159 | ptrace (PTRACE_SET_DEBUGREG, tid, 0, saved_dabr_value); | |
2160 | } | |
2161 | ||
2162 | static void | |
2163 | ppc_linux_thread_exit (struct thread_info *tp, int silent) | |
2164 | { | |
2165 | int i; | |
e38504b3 | 2166 | int tid = tp->ptid.lwp (); |
6ffbb7ab TJB |
2167 | struct hw_break_tuple *hw_breaks; |
2168 | struct thread_points *t = NULL, *p; | |
2169 | ||
926bf92d | 2170 | if (!have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2171 | return; |
2172 | ||
2173 | for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, p); i++) | |
2174 | if (p->tid == tid) | |
2175 | { | |
2176 | t = p; | |
2177 | break; | |
2178 | } | |
2179 | ||
2180 | if (t == NULL) | |
2181 | return; | |
2182 | ||
2183 | VEC_unordered_remove (thread_points_p, ppc_threads, i); | |
2184 | ||
2185 | hw_breaks = t->hw_breaks; | |
2186 | ||
2187 | for (i = 0; i < max_slots_number; i++) | |
2188 | if (hw_breaks[i].hw_break) | |
2189 | xfree (hw_breaks[i].hw_break); | |
2190 | ||
2191 | xfree (t->hw_breaks); | |
2192 | xfree (t); | |
e0d24f8d WZ |
2193 | } |
2194 | ||
57810aa7 | 2195 | bool |
f6ac5f3d | 2196 | ppc_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) |
e0d24f8d | 2197 | { |
f865ee35 | 2198 | siginfo_t siginfo; |
e0d24f8d | 2199 | |
f865ee35 | 2200 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) |
57810aa7 | 2201 | return false; |
e0d24f8d | 2202 | |
f865ee35 JK |
2203 | if (siginfo.si_signo != SIGTRAP |
2204 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
57810aa7 | 2205 | return false; |
e0d24f8d | 2206 | |
926bf92d | 2207 | if (have_ptrace_hwdebug_interface ()) |
6ffbb7ab TJB |
2208 | { |
2209 | int i; | |
2210 | struct thread_points *t; | |
2211 | struct hw_break_tuple *hw_breaks; | |
2212 | /* The index (or slot) of the *point is passed in the si_errno field. */ | |
f865ee35 | 2213 | int slot = siginfo.si_errno; |
6ffbb7ab | 2214 | |
e38504b3 | 2215 | t = hwdebug_find_thread_points_by_tid (inferior_ptid.lwp (), 0); |
6ffbb7ab TJB |
2216 | |
2217 | /* Find out if this *point is a hardware breakpoint. | |
2218 | If so, we should return 0. */ | |
2219 | if (t) | |
2220 | { | |
2221 | hw_breaks = t->hw_breaks; | |
2222 | for (i = 0; i < max_slots_number; i++) | |
2223 | if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot | |
2224 | && hw_breaks[i].hw_break->trigger_type | |
2225 | == PPC_BREAKPOINT_TRIGGER_EXECUTE) | |
57810aa7 | 2226 | return false; |
6ffbb7ab TJB |
2227 | } |
2228 | } | |
2229 | ||
f865ee35 | 2230 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
57810aa7 | 2231 | return true; |
e0d24f8d WZ |
2232 | } |
2233 | ||
57810aa7 | 2234 | bool |
f6ac5f3d | 2235 | ppc_linux_nat_target::stopped_by_watchpoint () |
9f0bdab8 DJ |
2236 | { |
2237 | CORE_ADDR addr; | |
f6ac5f3d | 2238 | return stopped_data_address (&addr); |
9f0bdab8 DJ |
2239 | } |
2240 | ||
57810aa7 | 2241 | bool |
f6ac5f3d PA |
2242 | ppc_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr, |
2243 | CORE_ADDR start, | |
2244 | int length) | |
5009afc5 | 2245 | { |
b7622095 LM |
2246 | int mask; |
2247 | ||
926bf92d | 2248 | if (have_ptrace_hwdebug_interface () |
6ffbb7ab TJB |
2249 | && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) |
2250 | return start <= addr && start + length >= addr; | |
2251 | else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) | |
b7622095 LM |
2252 | mask = 3; |
2253 | else | |
2254 | mask = 7; | |
2255 | ||
2256 | addr &= ~mask; | |
2257 | ||
0df8b418 | 2258 | /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */ |
b7622095 | 2259 | return start <= addr + mask && start + length - 1 >= addr; |
5009afc5 AS |
2260 | } |
2261 | ||
9c06b0b4 TJB |
2262 | /* Return the number of registers needed for a masked hardware watchpoint. */ |
2263 | ||
f6ac5f3d PA |
2264 | int |
2265 | ppc_linux_nat_target::masked_watch_num_registers (CORE_ADDR addr, CORE_ADDR mask) | |
9c06b0b4 | 2266 | { |
926bf92d UW |
2267 | if (!have_ptrace_hwdebug_interface () |
2268 | || (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_MASK) == 0) | |
9c06b0b4 TJB |
2269 | return -1; |
2270 | else if ((mask & 0xC0000000) != 0xC0000000) | |
2271 | { | |
2272 | warning (_("The given mask covers kernel address space " | |
2273 | "and cannot be used.\n")); | |
2274 | ||
2275 | return -2; | |
2276 | } | |
2277 | else | |
2278 | return 2; | |
2279 | } | |
2280 | ||
f6ac5f3d PA |
2281 | void |
2282 | ppc_linux_nat_target::store_registers (struct regcache *regcache, int regno) | |
45229ea4 | 2283 | { |
222312d3 | 2284 | pid_t tid = get_ptrace_pid (regcache->ptid ()); |
05f13b9c | 2285 | |
45229ea4 | 2286 | if (regno >= 0) |
56be3814 | 2287 | store_register (regcache, tid, regno); |
45229ea4 | 2288 | else |
56be3814 | 2289 | store_ppc_registers (regcache, tid); |
45229ea4 EZ |
2290 | } |
2291 | ||
f2db237a AM |
2292 | /* Functions for transferring registers between a gregset_t or fpregset_t |
2293 | (see sys/ucontext.h) and gdb's regcache. The word size is that used | |
0df8b418 | 2294 | by the ptrace interface, not the current program's ABI. Eg. if a |
f2db237a AM |
2295 | powerpc64-linux gdb is being used to debug a powerpc32-linux app, we |
2296 | read or write 64-bit gregsets. This is to suit the host libthread_db. */ | |
2297 | ||
50c9bd31 | 2298 | void |
7f7fe91e | 2299 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
c877c8e6 | 2300 | { |
f2db237a | 2301 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 2302 | |
f2db237a | 2303 | ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp)); |
c877c8e6 KB |
2304 | } |
2305 | ||
fdb28ac4 | 2306 | void |
7f7fe91e UW |
2307 | fill_gregset (const struct regcache *regcache, |
2308 | gdb_gregset_t *gregsetp, int regno) | |
fdb28ac4 | 2309 | { |
f2db237a | 2310 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); |
f9be684a | 2311 | |
f2db237a AM |
2312 | if (regno == -1) |
2313 | memset (gregsetp, 0, sizeof (*gregsetp)); | |
2314 | ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp)); | |
fdb28ac4 KB |
2315 | } |
2316 | ||
50c9bd31 | 2317 | void |
7f7fe91e | 2318 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp) |
c877c8e6 | 2319 | { |
f2db237a AM |
2320 | const struct regset *regset = ppc_linux_fpregset (); |
2321 | ||
2322 | ppc_supply_fpregset (regset, regcache, -1, | |
2323 | fpregsetp, sizeof (*fpregsetp)); | |
c877c8e6 | 2324 | } |
fdb28ac4 | 2325 | |
fdb28ac4 | 2326 | void |
7f7fe91e UW |
2327 | fill_fpregset (const struct regcache *regcache, |
2328 | gdb_fpregset_t *fpregsetp, int regno) | |
fdb28ac4 | 2329 | { |
f2db237a AM |
2330 | const struct regset *regset = ppc_linux_fpregset (); |
2331 | ||
2332 | ppc_collect_fpregset (regset, regcache, regno, | |
2333 | fpregsetp, sizeof (*fpregsetp)); | |
fdb28ac4 | 2334 | } |
10d6c8cd | 2335 | |
2e077f5e PFC |
2336 | int |
2337 | ppc_linux_nat_target::auxv_parse (gdb_byte **readptr, | |
2338 | gdb_byte *endptr, CORE_ADDR *typep, | |
2339 | CORE_ADDR *valp) | |
409c383c | 2340 | { |
e38504b3 | 2341 | int tid = inferior_ptid.lwp (); |
409c383c | 2342 | if (tid == 0) |
e99b03dc | 2343 | tid = inferior_ptid.pid (); |
409c383c | 2344 | |
2e077f5e | 2345 | int sizeof_auxv_field = ppc_linux_target_wordsize (tid); |
409c383c | 2346 | |
f5656ead | 2347 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); |
409c383c UW |
2348 | gdb_byte *ptr = *readptr; |
2349 | ||
2350 | if (endptr == ptr) | |
2351 | return 0; | |
2352 | ||
2353 | if (endptr - ptr < sizeof_auxv_field * 2) | |
2354 | return -1; | |
2355 | ||
e17a4113 | 2356 | *typep = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); |
409c383c | 2357 | ptr += sizeof_auxv_field; |
e17a4113 | 2358 | *valp = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); |
409c383c UW |
2359 | ptr += sizeof_auxv_field; |
2360 | ||
2361 | *readptr = ptr; | |
2362 | return 1; | |
2363 | } | |
2364 | ||
f6ac5f3d PA |
2365 | const struct target_desc * |
2366 | ppc_linux_nat_target::read_description () | |
310a98e1 | 2367 | { |
e38504b3 | 2368 | int tid = inferior_ptid.lwp (); |
7284e1be | 2369 | if (tid == 0) |
e99b03dc | 2370 | tid = inferior_ptid.pid (); |
7284e1be | 2371 | |
310a98e1 DJ |
2372 | if (have_ptrace_getsetevrregs) |
2373 | { | |
2374 | struct gdb_evrregset_t evrregset; | |
310a98e1 DJ |
2375 | |
2376 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0) | |
7284e1be UW |
2377 | return tdesc_powerpc_e500l; |
2378 | ||
2379 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported. | |
2380 | Anything else needs to be reported. */ | |
2381 | else if (errno != EIO) | |
2382 | perror_with_name (_("Unable to fetch SPE registers")); | |
2383 | } | |
2384 | ||
bd64614e PFC |
2385 | struct ppc_linux_features features = ppc_linux_no_features; |
2386 | ||
2e077f5e | 2387 | features.wordsize = ppc_linux_target_wordsize (tid); |
bd64614e | 2388 | |
0ec848ad | 2389 | CORE_ADDR hwcap = ppc_linux_get_hwcap (); |
7ca18ed6 | 2390 | CORE_ADDR hwcap2 = ppc_linux_get_hwcap2 (); |
bd64614e | 2391 | |
0154d990 | 2392 | if (have_ptrace_getsetvsxregs |
bd64614e | 2393 | && (hwcap & PPC_FEATURE_HAS_VSX)) |
604c2f83 LM |
2394 | { |
2395 | gdb_vsxregset_t vsxregset; | |
2396 | ||
2397 | if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0) | |
bd64614e | 2398 | features.vsx = true; |
604c2f83 LM |
2399 | |
2400 | /* EIO means that the PTRACE_GETVSXREGS request isn't supported. | |
2401 | Anything else needs to be reported. */ | |
2402 | else if (errno != EIO) | |
2403 | perror_with_name (_("Unable to fetch VSX registers")); | |
2404 | } | |
2405 | ||
0154d990 | 2406 | if (have_ptrace_getvrregs |
bd64614e | 2407 | && (hwcap & PPC_FEATURE_HAS_ALTIVEC)) |
7284e1be UW |
2408 | { |
2409 | gdb_vrregset_t vrregset; | |
2410 | ||
2411 | if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0) | |
bd64614e | 2412 | features.altivec = true; |
7284e1be UW |
2413 | |
2414 | /* EIO means that the PTRACE_GETVRREGS request isn't supported. | |
2415 | Anything else needs to be reported. */ | |
2416 | else if (errno != EIO) | |
2417 | perror_with_name (_("Unable to fetch AltiVec registers")); | |
310a98e1 DJ |
2418 | } |
2419 | ||
bd64614e PFC |
2420 | if (hwcap & PPC_FEATURE_CELL) |
2421 | features.cell = true; | |
7284e1be | 2422 | |
bd64614e | 2423 | features.isa205 = ppc_linux_has_isa205 (hwcap); |
604c2f83 | 2424 | |
7ca18ed6 EBM |
2425 | if ((hwcap2 & PPC_FEATURE2_DSCR) |
2426 | && check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET) | |
2427 | && check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET)) | |
f2cf6173 EBM |
2428 | { |
2429 | features.ppr_dscr = true; | |
2430 | if ((hwcap2 & PPC_FEATURE2_ARCH_2_07) | |
2431 | && (hwcap2 & PPC_FEATURE2_TAR) | |
2432 | && check_regset (tid, NT_PPC_TAR, PPC_LINUX_SIZEOF_TARREGSET)) | |
2433 | features.isa207 = true; | |
2434 | } | |
7ca18ed6 | 2435 | |
bd64614e | 2436 | return ppc_linux_match_description (features); |
310a98e1 DJ |
2437 | } |
2438 | ||
10d6c8cd DJ |
2439 | void |
2440 | _initialize_ppc_linux_nat (void) | |
2441 | { | |
f6ac5f3d | 2442 | linux_target = &the_ppc_linux_nat_target; |
310a98e1 | 2443 | |
76727919 | 2444 | gdb::observers::thread_exit.attach (ppc_linux_thread_exit); |
6ffbb7ab | 2445 | |
10d6c8cd | 2446 | /* Register the target. */ |
d9f719f1 | 2447 | add_inf_child_target (linux_target); |
10d6c8cd | 2448 | } |