[deliverable/binutils-gdb.git] / gdb / ppc-tdep.h

/* Target-dependent code for GDB, the GNU debugger.

   Copyright (C) 2000-2014 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef PPC_TDEP_H
#define PPC_TDEP_H

struct gdbarch;
struct frame_info;
struct value;
struct regcache;
struct type;

/* From ppc-sysv-tdep.c ...  */
enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
							struct value *function,
							struct type *valtype,
							struct regcache *regcache,
							gdb_byte *readbuf,
							const gdb_byte *writebuf);
enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
							       struct value *function,
							       struct type *valtype,
							       struct regcache *regcache,
							       gdb_byte *readbuf,
							       const gdb_byte *writebuf);
CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
					struct value *function,
					struct regcache *regcache,
					CORE_ADDR bp_addr, int nargs,
					struct value **args, CORE_ADDR sp,
					int struct_return,
					CORE_ADDR struct_addr);
CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
					  struct value *function,
					  struct regcache *regcache,
					  CORE_ADDR bp_addr, int nargs,
					  struct value **args, CORE_ADDR sp,
					  int struct_return,
					  CORE_ADDR struct_addr);
enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
							  struct value *function,
							  struct type *valtype,
							  struct regcache *regcache,
							  gdb_byte *readbuf,
							  const gdb_byte *writebuf);

/* From rs6000-tdep.c...  */
int altivec_register_p (struct gdbarch *gdbarch, int regno);
int vsx_register_p (struct gdbarch *gdbarch, int regno);
int spe_register_p (struct gdbarch *gdbarch, int regno);

/* Return non-zero if the architecture described by GDBARCH has
   floating-point registers (f0 --- f31 and fpscr).  */
int ppc_floating_point_unit_p (struct gdbarch *gdbarch);

/* Return non-zero if the architecture described by GDBARCH has
   Altivec registers (vr0 --- vr31, vrsave and vscr).  */
int ppc_altivec_support_p (struct gdbarch *gdbarch);

/* Return non-zero if the architecture described by GDBARCH has
   VSX registers (vsr0 --- vsr63).  */
int vsx_support_p (struct gdbarch *gdbarch);
int ppc_deal_with_atomic_sequence (struct frame_info *frame);


/* Register set description.  */

struct ppc_reg_offsets
{
  /* General-purpose registers.  */
  int r0_offset;
  int gpr_size; /* size for r0-31, pc, ps, lr, ctr.  */
  int xr_size;  /* size for cr, xer, mq.  */
  int pc_offset;
  int ps_offset;
  int cr_offset;
  int lr_offset;
  int ctr_offset;
  int xer_offset;
  int mq_offset;

  /* Floating-point registers.  */
  int f0_offset;
  int fpscr_offset;
  int fpscr_size;

  /* AltiVec registers.  */
  int vr0_offset;
  int vscr_offset;
  int vrsave_offset;
};

extern void ppc_supply_reg (struct regcache *regcache, int regnum,
			    const gdb_byte *regs, size_t offset, int regsize);

extern void ppc_collect_reg (const struct regcache *regcache, int regnum,
			     gdb_byte *regs, size_t offset, int regsize);

/* Supply register REGNUM in the general-purpose register set REGSET
   from the buffer specified by GREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_gregset (const struct regset *regset,
				struct regcache *regcache,
				int regnum, const void *gregs, size_t len);

/* Supply register REGNUM in the floating-point register set REGSET
   from the buffer specified by FPREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_fpregset (const struct regset *regset,
				 struct regcache *regcache,
				 int regnum, const void *fpregs, size_t len);

/* Supply register REGNUM in the Altivec register set REGSET
   from the buffer specified by VRREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_vrregset (const struct regset *regset,
				 struct regcache *regcache,
				 int regnum, const void *vrregs, size_t len);

/* Supply register REGNUM in the VSX register set REGSET
   from the buffer specified by VSXREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_vsxregset (const struct regset *regset,
				 struct regcache *regcache,
				 int regnum, const void *vsxregs, size_t len);

/* Collect register REGNUM in the general-purpose register set
   REGSET, from register cache REGCACHE into the buffer specified by
   GREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_gregset (const struct regset *regset,
				 const struct regcache *regcache,
				 int regnum, void *gregs, size_t len);

/* Collect register REGNUM in the floating-point register set
   REGSET, from register cache REGCACHE into the buffer specified by
   FPREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_fpregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *fpregs, size_t len);

/* Collect register REGNUM in the Altivec register set
   REGSET from register cache REGCACHE into the buffer specified by
   VRREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_vrregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *vrregs, size_t len);

/* Collect register REGNUM in the VSX register set
   REGSET from register cache REGCACHE into the buffer specified by
   VSXREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_vsxregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *vsxregs, size_t len);

/* Private data that this module attaches to struct gdbarch.  */

/* ELF ABI version used by the inferior.  */
enum powerpc_elf_abi
{
  POWERPC_ELF_AUTO,
  POWERPC_ELF_V1,
  POWERPC_ELF_V2,
  POWERPC_ELF_LAST
};

/* Vector ABI used by the inferior.  */
enum powerpc_vector_abi
{
  POWERPC_VEC_AUTO,
  POWERPC_VEC_GENERIC,
  POWERPC_VEC_ALTIVEC,
  POWERPC_VEC_SPE,
  POWERPC_VEC_LAST
};

struct gdbarch_tdep
  {
    int wordsize;		/* Size in bytes of fixed-point word.  */
    int soft_float;		/* Avoid FP registers for arguments?  */

    enum powerpc_elf_abi elf_abi;	/* ELF ABI version.  */

    /* How to pass vector arguments.  Never set to AUTO or LAST.  */
    enum powerpc_vector_abi vector_abi;

    int ppc_gp0_regnum;		/* GPR register 0 */
    int ppc_toc_regnum;		/* TOC register */
    int ppc_ps_regnum;	        /* Processor (or machine) status (%msr) */
    int ppc_cr_regnum;		/* Condition register */
    int ppc_lr_regnum;		/* Link register */
    int ppc_ctr_regnum;		/* Count register */
    int ppc_xer_regnum;		/* Integer exception register */

    /* Not all PPC and RS6000 variants will have the registers
       represented below.  A -1 is used to indicate that the register
       is not present in this variant.  */

    /* Floating-point registers.  */
    int ppc_fp0_regnum;         /* Floating-point register 0.  */
    int ppc_fpscr_regnum;	/* fp status and condition register.  */

    /* Multiplier-Quotient Register (older POWER architectures only).  */
    int ppc_mq_regnum;

    /* POWER7 VSX registers.  */
    int ppc_vsr0_regnum;	/* First VSX register.  */
    int ppc_vsr0_upper_regnum;  /* First right most dword vsx register.  */
    int ppc_efpr0_regnum;	/* First Extended FP register.  */

    /* Altivec registers.  */
    int ppc_vr0_regnum;		/* First AltiVec register.  */
    int ppc_vrsave_regnum;	/* Last AltiVec register.  */

    /* SPE registers.  */
    int ppc_ev0_upper_regnum;   /* First GPR upper half register.  */
    int ppc_ev0_regnum;         /* First ev register.  */
    int ppc_acc_regnum;         /* SPE 'acc' register.  */
    int ppc_spefscr_regnum;     /* SPE 'spefscr' register.  */

    /* Decimal 128 registers.  */
    int ppc_dl0_regnum;		/* First Decimal128 argument register pair.  */

    /* Offset to ABI specific location where link register is saved.  */
    int lr_frame_offset;	

    /* An array of integers, such that sim_regno[I] is the simulator
       register number for GDB register number I, or -1 if the
       simulator does not implement that register.  */
    int *sim_regno;

    /* ISA-specific types.  */
    struct type *ppc_builtin_type_vec64;
    struct type *ppc_builtin_type_vec128;
};


/* Constants for register set sizes.  */
enum
  {
    ppc_num_gprs = 32,		/* 32 general-purpose registers.  */
    ppc_num_fprs = 32,		/* 32 floating-point registers.  */
    ppc_num_srs = 16,		/* 16 segment registers.  */
    ppc_num_vrs = 32,		/* 32 Altivec vector registers.  */
    ppc_num_vshrs = 32,		/* 32 doublewords (dword 1 of vs0~vs31).  */
    ppc_num_vsrs = 64,		/* 64 VSX vector registers.  */
    ppc_num_efprs = 32		/* 32 Extended FP registers.  */
  };


/* Register number constants.  These are GDB internal register
   numbers; they are not used for the simulator or remote targets.
   Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given
   numbers above PPC_NUM_REGS.  So are segment registers and other
   target-defined registers.  */
enum {
  PPC_R0_REGNUM = 0,
  PPC_F0_REGNUM = 32,
  PPC_PC_REGNUM = 64,
  PPC_MSR_REGNUM = 65,
  PPC_CR_REGNUM = 66,
  PPC_LR_REGNUM = 67,
  PPC_CTR_REGNUM = 68,
  PPC_XER_REGNUM = 69,
  PPC_FPSCR_REGNUM = 70,
  PPC_MQ_REGNUM = 71,
  PPC_SPE_UPPER_GP0_REGNUM = 72,
  PPC_SPE_ACC_REGNUM = 104,
  PPC_SPE_FSCR_REGNUM = 105,
  PPC_VR0_REGNUM = 106,
  PPC_VSCR_REGNUM = 138,
  PPC_VRSAVE_REGNUM = 139,
  PPC_VSR0_UPPER_REGNUM = 140,
  PPC_VSR31_UPPER_REGNUM = 171,
  PPC_NUM_REGS
};

/* An instruction to match.  */

struct ppc_insn_pattern
{
  unsigned int mask;            /* mask the insn with this...  */
  unsigned int data;            /* ...and see if it matches this.  */
  int optional;                 /* If non-zero, this insn may be absent.  */
};

extern int ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc,
				    struct ppc_insn_pattern *pattern,
				    unsigned int *insns);
extern CORE_ADDR ppc_insn_d_field (unsigned int insn);

extern CORE_ADDR ppc_insn_ds_field (unsigned int insn);

/* Instruction size.  */
#define PPC_INSN_SIZE 4

/* Estimate for the maximum number of instrctions in a function epilogue.  */
#define PPC_MAX_EPILOGUE_INSTRUCTIONS  52

#endif /* ppc-tdep.h */
Commit	Line	Data
9aa1e687	1	/* Target-dependent code for GDB, the GNU debugger.
f9be684a	2
ecd75fc8	3	Copyright (C) 2000-2014 Free Software Foundation, Inc.
9aa1e687 KB	4
	5	This file is part of GDB.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
a9762ec7	9	the Free Software Foundation; either version 3 of the License, or
9aa1e687 KB	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
a9762ec7	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
9aa1e687	19
3a1c5313 AC	20	#ifndef PPC_TDEP_H
	21	#define PPC_TDEP_H
	22
da3331ec	23	struct gdbarch;
3a1c5313 AC	24	struct frame_info;
3a1c5313 AC	25	struct value;
4a4b3fed	26	struct regcache;
221c12ff	27	struct type;
3a1c5313	28
0df8b418	29	/* From ppc-sysv-tdep.c ... */
05580c65	30	enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
6a3a010b	31	struct value *function,
05580c65 AC	32	struct type *valtype,
05580c65 AC	33	struct regcache *regcache,
50fd1280 AC	34	gdb_byte *readbuf,
50fd1280 AC	35	const gdb_byte *writebuf);
05580c65	36	enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
6a3a010b	37	struct value *function,
05580c65 AC	38	struct type *valtype,
05580c65 AC	39	struct regcache *regcache,
50fd1280 AC	40	gdb_byte *readbuf,
50fd1280 AC	41	const gdb_byte *writebuf);
77b2b6d4	42	CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
7d9b040b	43	struct value *function,
77b2b6d4 AC	44	struct regcache *regcache,
	45	CORE_ADDR bp_addr, int nargs,
	46	struct value **args, CORE_ADDR sp,
	47	int struct_return,
	48	CORE_ADDR struct_addr);
8be9034a	49	CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
7d9b040b	50	struct value *function,
8be9034a AC	51	struct regcache *regcache,
	52	CORE_ADDR bp_addr, int nargs,
	53	struct value **args, CORE_ADDR sp,
	54	int struct_return,
	55	CORE_ADDR struct_addr);
05580c65	56	enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
6a3a010b	57	struct value *function,
05580c65 AC	58	struct type *valtype,
05580c65 AC	59	struct regcache *regcache,
50fd1280 AC	60	gdb_byte *readbuf,
50fd1280 AC	61	const gdb_byte *writebuf);
9aa1e687	62
0df8b418	63	/* From rs6000-tdep.c... */
be8626e0	64	int altivec_register_p (struct gdbarch *gdbarch, int regno);
604c2f83	65	int vsx_register_p (struct gdbarch *gdbarch, int regno);
be8626e0	66	int spe_register_p (struct gdbarch *gdbarch, int regno);
9aa1e687	67
383f0f5b JB	68	/* Return non-zero if the architecture described by GDBARCH has
383f0f5b JB	69	floating-point registers (f0 --- f31 and fpscr). */
0a613259 AC	70	int ppc_floating_point_unit_p (struct gdbarch *gdbarch);
0a613259 AC	71
06caf7d2 CES	72	/* Return non-zero if the architecture described by GDBARCH has
	73	Altivec registers (vr0 --- vr31, vrsave and vscr). */
	74	int ppc_altivec_support_p (struct gdbarch *gdbarch);
	75
604c2f83 LM	76	/* Return non-zero if the architecture described by GDBARCH has
	77	VSX registers (vsr0 --- vsr63). */
	78	int vsx_support_p (struct gdbarch *gdbarch);
4a7622d1 UW	79	int ppc_deal_with_atomic_sequence (struct frame_info *frame);
	80
	81
d195bc9f MK	82	/* Register set description. */
	83
	84	struct ppc_reg_offsets
	85	{
	86	/* General-purpose registers. */
	87	int r0_offset;
f2db237a AM	88	int gpr_size; /* size for r0-31, pc, ps, lr, ctr. */
f2db237a AM	89	int xr_size; /* size for cr, xer, mq. */
d195bc9f MK	90	int pc_offset;
	91	int ps_offset;
	92	int cr_offset;
	93	int lr_offset;
	94	int ctr_offset;
	95	int xer_offset;
	96	int mq_offset;
	97
	98	/* Floating-point registers. */
	99	int f0_offset;
	100	int fpscr_offset;
f2db237a	101	int fpscr_size;
d195bc9f MK	102
	103	/* AltiVec registers. */
	104	int vr0_offset;
	105	int vscr_offset;
	106	int vrsave_offset;
	107	};
	108
7284e1be UW	109	extern void ppc_supply_reg (struct regcache *regcache, int regnum,
	110	const gdb_byte *regs, size_t offset, int regsize);
	111
	112	extern void ppc_collect_reg (const struct regcache *regcache, int regnum,
	113	gdb_byte *regs, size_t offset, int regsize);
	114
d195bc9f MK	115	/* Supply register REGNUM in the general-purpose register set REGSET
	116	from the buffer specified by GREGS and LEN to register cache
	117	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	118
	119	extern void ppc_supply_gregset (const struct regset *regset,
	120	struct regcache *regcache,
	121	int regnum, const void *gregs, size_t len);
	122
	123	/* Supply register REGNUM in the floating-point register set REGSET
	124	from the buffer specified by FPREGS and LEN to register cache
	125	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	126
	127	extern void ppc_supply_fpregset (const struct regset *regset,
	128	struct regcache *regcache,
	129	int regnum, const void *fpregs, size_t len);
	130
06caf7d2 CES	131	/* Supply register REGNUM in the Altivec register set REGSET
	132	from the buffer specified by VRREGS and LEN to register cache
	133	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	134
	135	extern void ppc_supply_vrregset (const struct regset *regset,
	136	struct regcache *regcache,
	137	int regnum, const void *vrregs, size_t len);
	138
604c2f83 LM	139	/* Supply register REGNUM in the VSX register set REGSET
	140	from the buffer specified by VSXREGS and LEN to register cache
	141	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	142
	143	extern void ppc_supply_vsxregset (const struct regset *regset,
	144	struct regcache *regcache,
	145	int regnum, const void *vsxregs, size_t len);
	146
d195bc9f	147	/* Collect register REGNUM in the general-purpose register set
0df8b418	148	REGSET, from register cache REGCACHE into the buffer specified by
d195bc9f MK	149	GREGS and LEN. If REGNUM is -1, do this for all registers in
	150	REGSET. */
	151
	152	extern void ppc_collect_gregset (const struct regset *regset,
	153	const struct regcache *regcache,
	154	int regnum, void *gregs, size_t len);
	155
	156	/* Collect register REGNUM in the floating-point register set
0df8b418	157	REGSET, from register cache REGCACHE into the buffer specified by
d195bc9f MK	158	FPREGS and LEN. If REGNUM is -1, do this for all registers in
	159	REGSET. */
	160
	161	extern void ppc_collect_fpregset (const struct regset *regset,
	162	const struct regcache *regcache,
	163	int regnum, void *fpregs, size_t len);
	164
06caf7d2 CES	165	/* Collect register REGNUM in the Altivec register set
	166	REGSET from register cache REGCACHE into the buffer specified by
	167	VRREGS and LEN. If REGNUM is -1, do this for all registers in
	168	REGSET. */
	169
	170	extern void ppc_collect_vrregset (const struct regset *regset,
	171	const struct regcache *regcache,
	172	int regnum, void *vrregs, size_t len);
	173
604c2f83 LM	174	/* Collect register REGNUM in the VSX register set
	175	REGSET from register cache REGCACHE into the buffer specified by
	176	VSXREGS and LEN. If REGNUM is -1, do this for all registers in
	177	REGSET. */
	178
	179	extern void ppc_collect_vsxregset (const struct regset *regset,
	180	const struct regcache *regcache,
	181	int regnum, void *vsxregs, size_t len);
	182
0df8b418	183	/* Private data that this module attaches to struct gdbarch. */
2188cbdd	184
cd453cd0 UW	185	/* ELF ABI version used by the inferior. */
	186	enum powerpc_elf_abi
	187	{
	188	POWERPC_ELF_AUTO,
	189	POWERPC_ELF_V1,
	190	POWERPC_ELF_V2,
	191	POWERPC_ELF_LAST
	192	};
	193
55eddb0f DJ	194	/* Vector ABI used by the inferior. */
	195	enum powerpc_vector_abi
	196	{
	197	POWERPC_VEC_AUTO,
	198	POWERPC_VEC_GENERIC,
	199	POWERPC_VEC_ALTIVEC,
	200	POWERPC_VEC_SPE,
	201	POWERPC_VEC_LAST
	202	};
	203
2188cbdd EZ	204	struct gdbarch_tdep
2188cbdd EZ	205	{
55eddb0f DJ	206	int wordsize; /* Size in bytes of fixed-point word. */
	207	int soft_float; /* Avoid FP registers for arguments? */
	208
cd453cd0 UW	209	enum powerpc_elf_abi elf_abi; /* ELF ABI version. */
cd453cd0 UW	210
55eddb0f DJ	211	/* How to pass vector arguments. Never set to AUTO or LAST. */
	212	enum powerpc_vector_abi vector_abi;
	213
2188cbdd	214	int ppc_gp0_regnum; /* GPR register 0 */
2188cbdd EZ	215	int ppc_toc_regnum; /* TOC register */
	216	int ppc_ps_regnum; /* Processor (or machine) status (%msr) */
	217	int ppc_cr_regnum; /* Condition register */
	218	int ppc_lr_regnum; /* Link register */
	219	int ppc_ctr_regnum; /* Count register */
	220	int ppc_xer_regnum; /* Integer exception register */
383f0f5b	221
826d5376 PG	222	/* Not all PPC and RS6000 variants will have the registers
	223	represented below. A -1 is used to indicate that the register
	224	is not present in this variant. */
	225
	226	/* Floating-point registers. */
0df8b418 MS	227	int ppc_fp0_regnum; /* Floating-point register 0. */
0df8b418 MS	228	int ppc_fpscr_regnum; /* fp status and condition register. */
826d5376	229
826d5376 PG	230	/* Multiplier-Quotient Register (older POWER architectures only). */
826d5376 PG	231	int ppc_mq_regnum;
f86a7158	232
604c2f83 LM	233	/* POWER7 VSX registers. */
	234	int ppc_vsr0_regnum; /* First VSX register. */
	235	int ppc_vsr0_upper_regnum; /* First right most dword vsx register. */
	236	int ppc_efpr0_regnum; /* First Extended FP register. */
	237
826d5376	238	/* Altivec registers. */
0df8b418 MS	239	int ppc_vr0_regnum; /* First AltiVec register. */
0df8b418 MS	240	int ppc_vrsave_regnum; /* Last AltiVec register. */
826d5376 PG	241
826d5376 PG	242	/* SPE registers. */
0df8b418 MS	243	int ppc_ev0_upper_regnum; /* First GPR upper half register. */
	244	int ppc_ev0_regnum; /* First ev register. */
	245	int ppc_acc_regnum; /* SPE 'acc' register. */
	246	int ppc_spefscr_regnum; /* SPE 'spefscr' register. */
826d5376	247
f949c649 TJB	248	/* Decimal 128 registers. */
	249	int ppc_dl0_regnum; /* First Decimal128 argument register pair. */
	250
826d5376 PG	251	/* Offset to ABI specific location where link register is saved. */
826d5376 PG	252	int lr_frame_offset;
9f643768 JB	253
	254	/* An array of integers, such that sim_regno[I] is the simulator
	255	register number for GDB register number I, or -1 if the
	256	simulator does not implement that register. */
	257	int *sim_regno;
6f7f3f0d	258
794ac428 UW	259	/* ISA-specific types. */
794ac428 UW	260	struct type *ppc_builtin_type_vec64;
604c2f83	261	struct type *ppc_builtin_type_vec128;
2188cbdd	262	};
3a1c5313	263
b967e06f JB	264
	265	/* Constants for register set sizes. */
	266	enum
	267	{
604c2f83 LM	268	ppc_num_gprs = 32, /* 32 general-purpose registers. */
	269	ppc_num_fprs = 32, /* 32 floating-point registers. */
	270	ppc_num_srs = 16, /* 16 segment registers. */
	271	ppc_num_vrs = 32, /* 32 Altivec vector registers. */
	272	ppc_num_vshrs = 32, /* 32 doublewords (dword 1 of vs0~vs31). */
	273	ppc_num_vsrs = 64, /* 64 VSX vector registers. */
	274	ppc_num_efprs = 32 /* 32 Extended FP registers. */
b967e06f JB	275	};
b967e06f JB	276
0ea0ec5f	277
7cc46491 DJ	278	/* Register number constants. These are GDB internal register
	279	numbers; they are not used for the simulator or remote targets.
	280	Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given
	281	numbers above PPC_NUM_REGS. So are segment registers and other
	282	target-defined registers. */
	283	enum {
	284	PPC_R0_REGNUM = 0,
	285	PPC_F0_REGNUM = 32,
	286	PPC_PC_REGNUM = 64,
	287	PPC_MSR_REGNUM = 65,
	288	PPC_CR_REGNUM = 66,
	289	PPC_LR_REGNUM = 67,
	290	PPC_CTR_REGNUM = 68,
	291	PPC_XER_REGNUM = 69,
	292	PPC_FPSCR_REGNUM = 70,
	293	PPC_MQ_REGNUM = 71,
	294	PPC_SPE_UPPER_GP0_REGNUM = 72,
	295	PPC_SPE_ACC_REGNUM = 104,
	296	PPC_SPE_FSCR_REGNUM = 105,
	297	PPC_VR0_REGNUM = 106,
	298	PPC_VSCR_REGNUM = 138,
	299	PPC_VRSAVE_REGNUM = 139,
604c2f83 LM	300	PPC_VSR0_UPPER_REGNUM = 140,
604c2f83 LM	301	PPC_VSR31_UPPER_REGNUM = 171,
7cc46491 DJ	302	PPC_NUM_REGS
7cc46491 DJ	303	};
0ea0ec5f	304
d78489bf AT	305	/* An instruction to match. */
	306
	307	struct ppc_insn_pattern
	308	{
	309	unsigned int mask; /* mask the insn with this... */
	310	unsigned int data; /* ...and see if it matches this. */
	311	int optional; /* If non-zero, this insn may be absent. */
	312	};
	313
845d4708	314	extern int ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc,
d78489bf	315	struct ppc_insn_pattern *pattern,
845d4708	316	unsigned int *insns);
d78489bf AT	317	extern CORE_ADDR ppc_insn_d_field (unsigned int insn);
	318
	319	extern CORE_ADDR ppc_insn_ds_field (unsigned int insn);
0ea0ec5f	320
a0c75879 MK	321	/* Instruction size. */
	322	#define PPC_INSN_SIZE 4
	323
0d1243d9 PG	324	/* Estimate for the maximum number of instrctions in a function epilogue. */
	325	#define PPC_MAX_EPILOGUE_INSTRUCTIONS 52
	326
a0c75879	327	#endif /* ppc-tdep.h */