[deliverable/binutils-gdb.git] / gdb / ppc-tdep.h

/* Target-dependent code for GDB, the GNU debugger.

   Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008
   Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef PPC_TDEP_H
#define PPC_TDEP_H

struct gdbarch;
struct frame_info;
struct value;
struct regcache;
struct type;

/* From ppc-linux-tdep.c... */
enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
							struct type *func_type,
							struct type *valtype,
							struct regcache *regcache,
							gdb_byte *readbuf,
							const gdb_byte *writebuf);
enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
							       struct type *func_type,
							       struct type *valtype,
							       struct regcache *regcache,
							       gdb_byte *readbuf,
							       const gdb_byte *writebuf);
CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
					struct value *function,
					struct regcache *regcache,
					CORE_ADDR bp_addr, int nargs,
					struct value **args, CORE_ADDR sp,
					int struct_return,
					CORE_ADDR struct_addr);
CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
					  struct value *function,
					  struct regcache *regcache,
					  CORE_ADDR bp_addr, int nargs,
					  struct value **args, CORE_ADDR sp,
					  int struct_return,
					  CORE_ADDR struct_addr);
CORE_ADDR ppc64_sysv_abi_adjust_breakpoint_address (struct gdbarch *gdbarch,
						    CORE_ADDR bpaddr);
int ppc_linux_memory_remove_breakpoint (struct gdbarch *, struct bp_target_info *);
struct link_map_offsets *ppc_linux_svr4_fetch_link_map_offsets (void);
const struct regset *ppc_linux_gregset (int);
const struct regset *ppc_linux_fpregset (void);

enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
							  struct type *func_type,
							  struct type *valtype,
							  struct regcache *regcache,
							  gdb_byte *readbuf,
							  const gdb_byte *writebuf);

/* From rs6000-tdep.c... */
int altivec_register_p (struct gdbarch *gdbarch, int regno);
int spe_register_p (struct gdbarch *gdbarch, int regno);

/* Return non-zero if the architecture described by GDBARCH has
   floating-point registers (f0 --- f31 and fpscr).  */
int ppc_floating_point_unit_p (struct gdbarch *gdbarch);

/* Return non-zero if the architecture described by GDBARCH has
   Altivec registers (vr0 --- vr31, vrsave and vscr).  */
int ppc_altivec_support_p (struct gdbarch *gdbarch);

/* Register set description.  */

struct ppc_reg_offsets
{
  /* General-purpose registers.  */
  int r0_offset;
  int gpr_size; /* size for r0-31, pc, ps, lr, ctr.  */
  int xr_size;  /* size for cr, xer, mq.  */
  int pc_offset;
  int ps_offset;
  int cr_offset;
  int lr_offset;
  int ctr_offset;
  int xer_offset;
  int mq_offset;

  /* Floating-point registers.  */
  int f0_offset;
  int fpscr_offset;
  int fpscr_size;

  /* AltiVec registers.  */
  int vr0_offset;
  int vscr_offset;
  int vrsave_offset;
};

/* Supply register REGNUM in the general-purpose register set REGSET
   from the buffer specified by GREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_gregset (const struct regset *regset,
				struct regcache *regcache,
				int regnum, const void *gregs, size_t len);

/* Supply register REGNUM in the floating-point register set REGSET
   from the buffer specified by FPREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_fpregset (const struct regset *regset,
				 struct regcache *regcache,
				 int regnum, const void *fpregs, size_t len);

/* Supply register REGNUM in the Altivec register set REGSET
   from the buffer specified by VRREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_vrregset (const struct regset *regset,
				 struct regcache *regcache,
				 int regnum, const void *vrregs, size_t len);

/* Collect register REGNUM in the general-purpose register set
   REGSET. from register cache REGCACHE into the buffer specified by
   GREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_gregset (const struct regset *regset,
				 const struct regcache *regcache,
				 int regnum, void *gregs, size_t len);

/* Collect register REGNUM in the floating-point register set
   REGSET. from register cache REGCACHE into the buffer specified by
   FPREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_fpregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *fpregs, size_t len);

/* Collect register REGNUM in the Altivec register set
   REGSET from register cache REGCACHE into the buffer specified by
   VRREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_vrregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *vrregs, size_t len);

/* Private data that this module attaches to struct gdbarch. */

/* Vector ABI used by the inferior.  */
enum powerpc_vector_abi
{
  POWERPC_VEC_AUTO,
  POWERPC_VEC_GENERIC,
  POWERPC_VEC_ALTIVEC,
  POWERPC_VEC_SPE,
  POWERPC_VEC_LAST
};

struct gdbarch_tdep
  {
    int wordsize;		/* Size in bytes of fixed-point word.  */
    int soft_float;		/* Avoid FP registers for arguments?  */

    /* How to pass vector arguments.  Never set to AUTO or LAST.  */
    enum powerpc_vector_abi vector_abi;

    int ppc_gp0_regnum;		/* GPR register 0 */
    int ppc_toc_regnum;		/* TOC register */
    int ppc_ps_regnum;	        /* Processor (or machine) status (%msr) */
    int ppc_cr_regnum;		/* Condition register */
    int ppc_lr_regnum;		/* Link register */
    int ppc_ctr_regnum;		/* Count register */
    int ppc_xer_regnum;		/* Integer exception register */

    /* Not all PPC and RS6000 variants will have the registers
       represented below.  A -1 is used to indicate that the register
       is not present in this variant.  */

    /* Floating-point registers.  */
    int ppc_fp0_regnum;         /* floating-point register 0 */
    int ppc_fpscr_regnum;	/* fp status and condition register */

    /* Multiplier-Quotient Register (older POWER architectures only).  */
    int ppc_mq_regnum;

    /* Altivec registers.  */
    int ppc_vr0_regnum;		/* First AltiVec register */
    int ppc_vrsave_regnum;	/* Last AltiVec register */

    /* SPE registers.  */
    int ppc_ev0_upper_regnum;   /* First GPR upper half register */
    int ppc_ev0_regnum;         /* First ev register */
    int ppc_acc_regnum;         /* SPE 'acc' register */
    int ppc_spefscr_regnum;     /* SPE 'spefscr' register */

    /* Decimal 128 registers.  */
    int ppc_dl0_regnum;		/* First Decimal128 argument register pair.  */

    /* Offset to ABI specific location where link register is saved.  */
    int lr_frame_offset;	

    /* An array of integers, such that sim_regno[I] is the simulator
       register number for GDB register number I, or -1 if the
       simulator does not implement that register.  */
    int *sim_regno;

    /* Minimum possible text address.  */
    CORE_ADDR text_segment_base;

    /* ISA-specific types.  */
    struct type *ppc_builtin_type_vec64;
};


/* Constants for register set sizes.  */
enum
  {
    ppc_num_gprs = 32,          /* 32 general-purpose registers */
    ppc_num_fprs = 32,          /* 32 floating-point registers */
    ppc_num_srs = 16,           /* 16 segment registers */
    ppc_num_vrs = 32            /* 32 Altivec vector registers */
  };


/* Register number constants.  These are GDB internal register
   numbers; they are not used for the simulator or remote targets.
   Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given
   numbers above PPC_NUM_REGS.  So are segment registers and other
   target-defined registers.  */
enum {
  PPC_R0_REGNUM = 0,
  PPC_F0_REGNUM = 32,
  PPC_PC_REGNUM = 64,
  PPC_MSR_REGNUM = 65,
  PPC_CR_REGNUM = 66,
  PPC_LR_REGNUM = 67,
  PPC_CTR_REGNUM = 68,
  PPC_XER_REGNUM = 69,
  PPC_FPSCR_REGNUM = 70,
  PPC_MQ_REGNUM = 71,
  PPC_SPE_UPPER_GP0_REGNUM = 72,
  PPC_SPE_ACC_REGNUM = 104,
  PPC_SPE_FSCR_REGNUM = 105,
  PPC_VR0_REGNUM = 106,
  PPC_VSCR_REGNUM = 138,
  PPC_VRSAVE_REGNUM = 139,
  PPC_NUM_REGS
};


/* Instruction size.  */
#define PPC_INSN_SIZE 4

/* Estimate for the maximum number of instrctions in a function epilogue.  */
#define PPC_MAX_EPILOGUE_INSTRUCTIONS  52

extern struct target_desc *tdesc_powerpc_e500;

#endif /* ppc-tdep.h */
Commit	Line	Data
9aa1e687	1	/* Target-dependent code for GDB, the GNU debugger.
f9be684a	2
9b254dd1	3	Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008
a0c75879	4	Free Software Foundation, Inc.
9aa1e687 KB	5
	6	This file is part of GDB.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
a9762ec7	10	the Free Software Foundation; either version 3 of the License, or
9aa1e687 KB	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
a9762ec7	19	along with this program. If not, see <http://www.gnu.org/licenses/>. */
9aa1e687	20
3a1c5313 AC	21	#ifndef PPC_TDEP_H
	22	#define PPC_TDEP_H
	23
da3331ec	24	struct gdbarch;
3a1c5313 AC	25	struct frame_info;
3a1c5313 AC	26	struct value;
4a4b3fed	27	struct regcache;
221c12ff	28	struct type;
3a1c5313	29
9aa1e687	30	/* From ppc-linux-tdep.c... */
05580c65	31	enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
c055b101	32	struct type *func_type,
05580c65 AC	33	struct type *valtype,
05580c65 AC	34	struct regcache *regcache,
50fd1280 AC	35	gdb_byte *readbuf,
50fd1280 AC	36	const gdb_byte *writebuf);
05580c65	37	enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
c055b101	38	struct type *func_type,
05580c65 AC	39	struct type *valtype,
05580c65 AC	40	struct regcache *regcache,
50fd1280 AC	41	gdb_byte *readbuf,
50fd1280 AC	42	const gdb_byte *writebuf);
77b2b6d4	43	CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
7d9b040b	44	struct value *function,
77b2b6d4 AC	45	struct regcache *regcache,
	46	CORE_ADDR bp_addr, int nargs,
	47	struct value **args, CORE_ADDR sp,
	48	int struct_return,
	49	CORE_ADDR struct_addr);
8be9034a	50	CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
7d9b040b	51	struct value *function,
8be9034a AC	52	struct regcache *regcache,
	53	CORE_ADDR bp_addr, int nargs,
	54	struct value **args, CORE_ADDR sp,
	55	int struct_return,
	56	CORE_ADDR struct_addr);
6066c3de AC	57	CORE_ADDR ppc64_sysv_abi_adjust_breakpoint_address (struct gdbarch *gdbarch,
6066c3de AC	58	CORE_ADDR bpaddr);
ae4b2284	59	int ppc_linux_memory_remove_breakpoint (struct gdbarch , struct bp_target_info );
6ded7999	60	struct link_map_offsets *ppc_linux_svr4_fetch_link_map_offsets (void);
f2db237a AM	61	const struct regset *ppc_linux_gregset (int);
f2db237a AM	62	const struct regset *ppc_linux_fpregset (void);
9aa1e687	63
05580c65	64	enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
c055b101	65	struct type *func_type,
05580c65 AC	66	struct type *valtype,
05580c65 AC	67	struct regcache *regcache,
50fd1280 AC	68	gdb_byte *readbuf,
50fd1280 AC	69	const gdb_byte *writebuf);
9aa1e687 KB	70
9aa1e687 KB	71	/* From rs6000-tdep.c... */
be8626e0 MD	72	int altivec_register_p (struct gdbarch *gdbarch, int regno);
be8626e0 MD	73	int spe_register_p (struct gdbarch *gdbarch, int regno);
9aa1e687	74
383f0f5b JB	75	/* Return non-zero if the architecture described by GDBARCH has
383f0f5b JB	76	floating-point registers (f0 --- f31 and fpscr). */
0a613259 AC	77	int ppc_floating_point_unit_p (struct gdbarch *gdbarch);
0a613259 AC	78
06caf7d2 CES	79	/* Return non-zero if the architecture described by GDBARCH has
	80	Altivec registers (vr0 --- vr31, vrsave and vscr). */
	81	int ppc_altivec_support_p (struct gdbarch *gdbarch);
	82
d195bc9f MK	83	/* Register set description. */
	84
	85	struct ppc_reg_offsets
	86	{
	87	/* General-purpose registers. */
	88	int r0_offset;
f2db237a AM	89	int gpr_size; /* size for r0-31, pc, ps, lr, ctr. */
f2db237a AM	90	int xr_size; /* size for cr, xer, mq. */
d195bc9f MK	91	int pc_offset;
	92	int ps_offset;
	93	int cr_offset;
	94	int lr_offset;
	95	int ctr_offset;
	96	int xer_offset;
	97	int mq_offset;
	98
	99	/* Floating-point registers. */
	100	int f0_offset;
	101	int fpscr_offset;
f2db237a	102	int fpscr_size;
d195bc9f MK	103
	104	/* AltiVec registers. */
	105	int vr0_offset;
	106	int vscr_offset;
	107	int vrsave_offset;
	108	};
	109
	110	/* Supply register REGNUM in the general-purpose register set REGSET
	111	from the buffer specified by GREGS and LEN to register cache
	112	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	113
	114	extern void ppc_supply_gregset (const struct regset *regset,
	115	struct regcache *regcache,
	116	int regnum, const void *gregs, size_t len);
	117
	118	/* Supply register REGNUM in the floating-point register set REGSET
	119	from the buffer specified by FPREGS and LEN to register cache
	120	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	121
	122	extern void ppc_supply_fpregset (const struct regset *regset,
	123	struct regcache *regcache,
	124	int regnum, const void *fpregs, size_t len);
	125
06caf7d2 CES	126	/* Supply register REGNUM in the Altivec register set REGSET
	127	from the buffer specified by VRREGS and LEN to register cache
	128	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	129
	130	extern void ppc_supply_vrregset (const struct regset *regset,
	131	struct regcache *regcache,
	132	int regnum, const void *vrregs, size_t len);
	133
d195bc9f MK	134	/* Collect register REGNUM in the general-purpose register set
	135	REGSET. from register cache REGCACHE into the buffer specified by
	136	GREGS and LEN. If REGNUM is -1, do this for all registers in
	137	REGSET. */
	138
	139	extern void ppc_collect_gregset (const struct regset *regset,
	140	const struct regcache *regcache,
	141	int regnum, void *gregs, size_t len);
	142
	143	/* Collect register REGNUM in the floating-point register set
	144	REGSET. from register cache REGCACHE into the buffer specified by
	145	FPREGS and LEN. If REGNUM is -1, do this for all registers in
	146	REGSET. */
	147
	148	extern void ppc_collect_fpregset (const struct regset *regset,
	149	const struct regcache *regcache,
	150	int regnum, void *fpregs, size_t len);
	151
06caf7d2 CES	152	/* Collect register REGNUM in the Altivec register set
	153	REGSET from register cache REGCACHE into the buffer specified by
	154	VRREGS and LEN. If REGNUM is -1, do this for all registers in
	155	REGSET. */
	156
	157	extern void ppc_collect_vrregset (const struct regset *regset,
	158	const struct regcache *regcache,
	159	int regnum, void *vrregs, size_t len);
	160
2188cbdd EZ	161	/* Private data that this module attaches to struct gdbarch. */
2188cbdd EZ	162
55eddb0f DJ	163	/* Vector ABI used by the inferior. */
	164	enum powerpc_vector_abi
	165	{
	166	POWERPC_VEC_AUTO,
	167	POWERPC_VEC_GENERIC,
	168	POWERPC_VEC_ALTIVEC,
	169	POWERPC_VEC_SPE,
	170	POWERPC_VEC_LAST
	171	};
	172
2188cbdd EZ	173	struct gdbarch_tdep
2188cbdd EZ	174	{
55eddb0f DJ	175	int wordsize; /* Size in bytes of fixed-point word. */
	176	int soft_float; /* Avoid FP registers for arguments? */
	177
	178	/* How to pass vector arguments. Never set to AUTO or LAST. */
	179	enum powerpc_vector_abi vector_abi;
	180
2188cbdd	181	int ppc_gp0_regnum; /* GPR register 0 */
2188cbdd EZ	182	int ppc_toc_regnum; /* TOC register */
	183	int ppc_ps_regnum; /* Processor (or machine) status (%msr) */
	184	int ppc_cr_regnum; /* Condition register */
	185	int ppc_lr_regnum; /* Link register */
	186	int ppc_ctr_regnum; /* Count register */
	187	int ppc_xer_regnum; /* Integer exception register */
383f0f5b	188
826d5376 PG	189	/* Not all PPC and RS6000 variants will have the registers
	190	represented below. A -1 is used to indicate that the register
	191	is not present in this variant. */
	192
	193	/* Floating-point registers. */
366f009f	194	int ppc_fp0_regnum; /* floating-point register 0 */
826d5376 PG	195	int ppc_fpscr_regnum; /* fp status and condition register */
826d5376 PG	196
826d5376 PG	197	/* Multiplier-Quotient Register (older POWER architectures only). */
826d5376 PG	198	int ppc_mq_regnum;
f86a7158	199
826d5376	200	/* Altivec registers. */
1fcc0bb8 EZ	201	int ppc_vr0_regnum; /* First AltiVec register */
1fcc0bb8 EZ	202	int ppc_vrsave_regnum; /* Last AltiVec register */
826d5376 PG	203
826d5376 PG	204	/* SPE registers. */
6ced10dd	205	int ppc_ev0_upper_regnum; /* First GPR upper half register */
c8001721	206	int ppc_ev0_regnum; /* First ev register */
867e2dc5 JB	207	int ppc_acc_regnum; /* SPE 'acc' register */
867e2dc5 JB	208	int ppc_spefscr_regnum; /* SPE 'spefscr' register */
826d5376	209
f949c649 TJB	210	/* Decimal 128 registers. */
	211	int ppc_dl0_regnum; /* First Decimal128 argument register pair. */
	212
826d5376 PG	213	/* Offset to ABI specific location where link register is saved. */
826d5376 PG	214	int lr_frame_offset;
9f643768 JB	215
	216	/* An array of integers, such that sim_regno[I] is the simulator
	217	register number for GDB register number I, or -1 if the
	218	simulator does not implement that register. */
	219	int *sim_regno;
6f7f3f0d UW	220
	221	/* Minimum possible text address. */
	222	CORE_ADDR text_segment_base;
794ac428 UW	223
	224	/* ISA-specific types. */
	225	struct type *ppc_builtin_type_vec64;
2188cbdd	226	};
3a1c5313	227
b967e06f JB	228
	229	/* Constants for register set sizes. */
	230	enum
	231	{
8bf659e8	232	ppc_num_gprs = 32, /* 32 general-purpose registers */
cc98b5cc	233	ppc_num_fprs = 32, /* 32 floating-point registers */
8f088af7	234	ppc_num_srs = 16, /* 16 segment registers */
cc98b5cc	235	ppc_num_vrs = 32 /* 32 Altivec vector registers */
b967e06f JB	236	};
b967e06f JB	237
0ea0ec5f	238
7cc46491 DJ	239	/* Register number constants. These are GDB internal register
	240	numbers; they are not used for the simulator or remote targets.
	241	Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given
	242	numbers above PPC_NUM_REGS. So are segment registers and other
	243	target-defined registers. */
	244	enum {
	245	PPC_R0_REGNUM = 0,
	246	PPC_F0_REGNUM = 32,
	247	PPC_PC_REGNUM = 64,
	248	PPC_MSR_REGNUM = 65,
	249	PPC_CR_REGNUM = 66,
	250	PPC_LR_REGNUM = 67,
	251	PPC_CTR_REGNUM = 68,
	252	PPC_XER_REGNUM = 69,
	253	PPC_FPSCR_REGNUM = 70,
	254	PPC_MQ_REGNUM = 71,
	255	PPC_SPE_UPPER_GP0_REGNUM = 72,
	256	PPC_SPE_ACC_REGNUM = 104,
	257	PPC_SPE_FSCR_REGNUM = 105,
	258	PPC_VR0_REGNUM = 106,
	259	PPC_VSCR_REGNUM = 138,
	260	PPC_VRSAVE_REGNUM = 139,
	261	PPC_NUM_REGS
	262	};
0ea0ec5f	263
0ea0ec5f	264
a0c75879 MK	265	/* Instruction size. */
	266	#define PPC_INSN_SIZE 4
	267
0d1243d9 PG	268	/* Estimate for the maximum number of instrctions in a function epilogue. */
	269	#define PPC_MAX_EPILOGUE_INSTRUCTIONS 52
	270
310a98e1 DJ	271	extern struct target_desc *tdesc_powerpc_e500;
310a98e1 DJ	272
a0c75879	273	#endif /* ppc-tdep.h */