[deliverable/binutils-gdb.git] / gdb / ppc-tdep.h

/* Target-dependent code for GDB, the GNU debugger.

   Copyright (C) 2000-2020 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef PPC_TDEP_H
#define PPC_TDEP_H

#include "gdbarch.h"

struct gdbarch;
struct frame_info;
struct value;
struct regcache;
struct type;

/* From ppc-sysv-tdep.c ...  */
enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
							struct value *function,
							struct type *valtype,
							struct regcache *regcache,
							gdb_byte *readbuf,
							const gdb_byte *writebuf);
enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
							       struct value *function,
							       struct type *valtype,
							       struct regcache *regcache,
							       gdb_byte *readbuf,
							       const gdb_byte *writebuf);

CORE_ADDR ppc_sysv_abi_push_dummy_call
  (struct gdbarch *gdbarch, struct value *function, struct regcache *regcache,
   CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp,
   function_call_return_method return_method, CORE_ADDR struct_addr);

CORE_ADDR ppc64_sysv_abi_push_dummy_call
  (struct gdbarch *gdbarch, struct value *function, struct regcache *regcache,
   CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp,
   function_call_return_method return_method, CORE_ADDR struct_addr);

enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
							  struct value *function,
							  struct type *valtype,
							  struct regcache *regcache,
							  gdb_byte *readbuf,
							  const gdb_byte *writebuf);

/* From rs6000-tdep.c...  */
int altivec_register_p (struct gdbarch *gdbarch, int regno);
int vsx_register_p (struct gdbarch *gdbarch, int regno);
int spe_register_p (struct gdbarch *gdbarch, int regno);

/* Return non-zero if the architecture described by GDBARCH has
   floating-point registers (f0 --- f31 and fpscr).  */
int ppc_floating_point_unit_p (struct gdbarch *gdbarch);

/* Return non-zero if the architecture described by GDBARCH has
   Altivec registers (vr0 --- vr31, vrsave and vscr).  */
int ppc_altivec_support_p (struct gdbarch *gdbarch);

/* Return non-zero if the architecture described by GDBARCH has
   VSX registers (vsr0 --- vsr63).  */
int vsx_support_p (struct gdbarch *gdbarch);
std::vector<CORE_ADDR> ppc_deal_with_atomic_sequence
  (struct regcache *regcache);


/* Register set description.  */

struct ppc_reg_offsets
{
  /* General-purpose registers.  */
  int r0_offset;
  int gpr_size; /* size for r0-31, pc, ps, lr, ctr.  */
  int xr_size;  /* size for cr, xer, mq.  */
  int pc_offset;
  int ps_offset;
  int cr_offset;
  int lr_offset;
  int ctr_offset;
  int xer_offset;
  int mq_offset;

  /* Floating-point registers.  */
  int f0_offset;
  int fpscr_offset;
  int fpscr_size;
};

extern void ppc_supply_reg (struct regcache *regcache, int regnum,
			    const gdb_byte *regs, size_t offset, int regsize);

extern void ppc_collect_reg (const struct regcache *regcache, int regnum,
			     gdb_byte *regs, size_t offset, int regsize);

/* Supply register REGNUM in the general-purpose register set REGSET
   from the buffer specified by GREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_gregset (const struct regset *regset,
				struct regcache *regcache,
				int regnum, const void *gregs, size_t len);

/* Supply register REGNUM in the floating-point register set REGSET
   from the buffer specified by FPREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_fpregset (const struct regset *regset,
				 struct regcache *regcache,
				 int regnum, const void *fpregs, size_t len);

/* Supply register REGNUM in the Altivec register set REGSET
   from the buffer specified by VRREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_vrregset (const struct regset *regset,
				 struct regcache *regcache,
				 int regnum, const void *vrregs, size_t len);

/* Supply register REGNUM in the VSX register set REGSET
   from the buffer specified by VSXREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_vsxregset (const struct regset *regset,
				 struct regcache *regcache,
				 int regnum, const void *vsxregs, size_t len);

/* Collect register REGNUM in the general-purpose register set
   REGSET, from register cache REGCACHE into the buffer specified by
   GREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_gregset (const struct regset *regset,
				 const struct regcache *regcache,
				 int regnum, void *gregs, size_t len);

/* Collect register REGNUM in the floating-point register set
   REGSET, from register cache REGCACHE into the buffer specified by
   FPREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_fpregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *fpregs, size_t len);

/* Collect register REGNUM in the Altivec register set
   REGSET from register cache REGCACHE into the buffer specified by
   VRREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_vrregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *vrregs, size_t len);

/* Collect register REGNUM in the VSX register set
   REGSET from register cache REGCACHE into the buffer specified by
   VSXREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_vsxregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *vsxregs, size_t len);

/* Private data that this module attaches to struct gdbarch.  */

/* ELF ABI version used by the inferior.  */
enum powerpc_elf_abi
{
  POWERPC_ELF_AUTO,
  POWERPC_ELF_V1,
  POWERPC_ELF_V2,
  POWERPC_ELF_LAST
};

/* Vector ABI used by the inferior.  */
enum powerpc_vector_abi
{
  POWERPC_VEC_AUTO,
  POWERPC_VEC_GENERIC,
  POWERPC_VEC_ALTIVEC,
  POWERPC_VEC_SPE,
  POWERPC_VEC_LAST
};

/* long double ABI version used by the inferior.  */
enum powerpc_long_double_abi
{
  POWERPC_LONG_DOUBLE_AUTO,
  POWERPC_LONG_DOUBLE_IBM128,
  POWERPC_LONG_DOUBLE_IEEE128,
  POWERPC_LONG_DOUBLE_LAST
};

struct gdbarch_tdep
  {
    int wordsize;		/* Size in bytes of fixed-point word.  */
    int soft_float;		/* Avoid FP registers for arguments?  */

    enum powerpc_elf_abi elf_abi;	/* ELF ABI version.  */

    /* Format to use for the "long double" data type.  */
    enum powerpc_long_double_abi long_double_abi;

    /* How to pass vector arguments.  Never set to AUTO or LAST.  */
    enum powerpc_vector_abi vector_abi;

    int ppc_gp0_regnum;		/* GPR register 0 */
    int ppc_toc_regnum;		/* TOC register */
    int ppc_ps_regnum;	        /* Processor (or machine) status (%msr) */
    int ppc_cr_regnum;		/* Condition register */
    int ppc_lr_regnum;		/* Link register */
    int ppc_ctr_regnum;		/* Count register */
    int ppc_xer_regnum;		/* Integer exception register */

    /* Not all PPC and RS6000 variants will have the registers
       represented below.  A -1 is used to indicate that the register
       is not present in this variant.  */

    /* Floating-point registers.  */
    int ppc_fp0_regnum;         /* Floating-point register 0.  */
    int ppc_fpscr_regnum;	/* fp status and condition register.  */

    /* Multiplier-Quotient Register (older POWER architectures only).  */
    int ppc_mq_regnum;

    /* POWER7 VSX registers.  */
    int ppc_vsr0_regnum;	/* First VSX register.  */
    int ppc_vsr0_upper_regnum;  /* First right most dword vsx register.  */
    int ppc_efpr0_regnum;	/* First Extended FP register.  */

    /* Altivec registers.  */
    int ppc_vr0_regnum;		/* First AltiVec register.  */
    int ppc_vrsave_regnum;	/* Last AltiVec register.  */

    /* Altivec pseudo-register vX aliases for the raw vrX
       registers.  */
    int ppc_v0_alias_regnum;

    /* SPE registers.  */
    int ppc_ev0_upper_regnum;   /* First GPR upper half register.  */
    int ppc_ev0_regnum;         /* First ev register.  */
    int ppc_acc_regnum;         /* SPE 'acc' register.  */
    int ppc_spefscr_regnum;     /* SPE 'spefscr' register.  */

    /* Program Priority Register.  */
    int ppc_ppr_regnum;

    /* Data Stream Control Register.  */
    int ppc_dscr_regnum;

    /* Target Address Register.  */
    int ppc_tar_regnum;

    /* Decimal 128 registers.  */
    int ppc_dl0_regnum;		/* First Decimal128 argument register pair.  */

    int have_ebb;

    /* PMU registers.  */
    int ppc_mmcr0_regnum;
    int ppc_mmcr2_regnum;
    int ppc_siar_regnum;
    int ppc_sdar_regnum;
    int ppc_sier_regnum;

    /* Hardware Transactional Memory registers.  */
    int have_htm_spr;
    int have_htm_core;
    int have_htm_fpu;
    int have_htm_altivec;
    int have_htm_vsx;
    int ppc_cppr_regnum;
    int ppc_cdscr_regnum;
    int ppc_ctar_regnum;

    /* HTM pseudo registers.  */
    int ppc_cdl0_regnum;
    int ppc_cvsr0_regnum;
    int ppc_cefpr0_regnum;

    /* Offset to ABI specific location where link register is saved.  */
    int lr_frame_offset;	

    /* An array of integers, such that sim_regno[I] is the simulator
       register number for GDB register number I, or -1 if the
       simulator does not implement that register.  */
    int *sim_regno;

    /* ISA-specific types.  */
    struct type *ppc_builtin_type_vec64;
    struct type *ppc_builtin_type_vec128;

    int (*ppc_syscall_record) (struct regcache *regcache);
};


/* Constants for register set sizes.  */
enum
  {
    ppc_num_gprs = 32,		/* 32 general-purpose registers.  */
    ppc_num_fprs = 32,		/* 32 floating-point registers.  */
    ppc_num_srs = 16,		/* 16 segment registers.  */
    ppc_num_vrs = 32,		/* 32 Altivec vector registers.  */
    ppc_num_vshrs = 32,		/* 32 doublewords (dword 1 of vs0~vs31).  */
    ppc_num_vsrs = 64,		/* 64 VSX vector registers.  */
    ppc_num_efprs = 32		/* 32 Extended FP registers.  */
  };


/* Register number constants.  These are GDB internal register
   numbers; they are not used for the simulator or remote targets.
   Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given
   numbers above PPC_NUM_REGS.  So are segment registers and other
   target-defined registers.  */
enum {
  PPC_R0_REGNUM = 0,
  PPC_F0_REGNUM = 32,
  PPC_PC_REGNUM = 64,
  PPC_MSR_REGNUM = 65,
  PPC_CR_REGNUM = 66,
  PPC_LR_REGNUM = 67,
  PPC_CTR_REGNUM = 68,
  PPC_XER_REGNUM = 69,
  PPC_FPSCR_REGNUM = 70,
  PPC_MQ_REGNUM = 71,
  PPC_SPE_UPPER_GP0_REGNUM = 72,
  PPC_SPE_ACC_REGNUM = 104,
  PPC_SPE_FSCR_REGNUM = 105,
  PPC_VR0_REGNUM = 106,
  PPC_VSCR_REGNUM = 138,
  PPC_VRSAVE_REGNUM = 139,
  PPC_VSR0_UPPER_REGNUM = 140,
  PPC_VSR31_UPPER_REGNUM = 171,
  PPC_PPR_REGNUM = 172,
  PPC_DSCR_REGNUM = 173,
  PPC_TAR_REGNUM = 174,

  /* EBB registers.  */
  PPC_BESCR_REGNUM = 175,
  PPC_EBBHR_REGNUM = 176,
  PPC_EBBRR_REGNUM = 177,

  /* PMU registers.  */
  PPC_MMCR0_REGNUM = 178,
  PPC_MMCR2_REGNUM = 179,
  PPC_SIAR_REGNUM = 180,
  PPC_SDAR_REGNUM = 181,
  PPC_SIER_REGNUM = 182,

  /* Hardware transactional memory registers.  */
  PPC_TFHAR_REGNUM = 183,
  PPC_TEXASR_REGNUM = 184,
  PPC_TFIAR_REGNUM = 185,

  PPC_CR0_REGNUM = 186,
  PPC_CCR_REGNUM = 218,
  PPC_CXER_REGNUM = 219,
  PPC_CLR_REGNUM = 220,
  PPC_CCTR_REGNUM = 221,

  PPC_CF0_REGNUM = 222,
  PPC_CFPSCR_REGNUM = 254,

  PPC_CVR0_REGNUM = 255,
  PPC_CVSCR_REGNUM = 287,
  PPC_CVRSAVE_REGNUM = 288,

  PPC_CVSR0_UPPER_REGNUM = 289,

  PPC_CPPR_REGNUM = 321,
  PPC_CDSCR_REGNUM = 322,
  PPC_CTAR_REGNUM = 323,
  PPC_NUM_REGS
};

/* Big enough to hold the size of the largest register in bytes.  */
#define PPC_MAX_REGISTER_SIZE	64

#define PPC_IS_EBB_REGNUM(i) \
	((i) >= PPC_BESCR_REGNUM && (i) <= PPC_EBBRR_REGNUM)

#define PPC_IS_PMU_REGNUM(i) \
	((i) >= PPC_MMCR0_REGNUM && (i) <= PPC_SIER_REGNUM)

#define PPC_IS_TMSPR_REGNUM(i) \
  ((i) >= PPC_TFHAR_REGNUM && (i) <= PPC_TFIAR_REGNUM)

#define PPC_IS_CKPTGP_REGNUM(i) \
  ((i) >= PPC_CR0_REGNUM && (i) <= PPC_CCTR_REGNUM)

#define PPC_IS_CKPTFP_REGNUM(i) \
  ((i) >= PPC_CF0_REGNUM && (i) <= PPC_CFPSCR_REGNUM)

#define PPC_IS_CKPTVMX_REGNUM(i) \
  ((i) >= PPC_CVR0_REGNUM && (i) <= PPC_CVRSAVE_REGNUM)

#define PPC_IS_CKPTVSX_REGNUM(i) \
  ((i) >= PPC_CVSR0_UPPER_REGNUM && (i) < (PPC_CVSR0_UPPER_REGNUM + 32))

/* An instruction to match.  */

struct ppc_insn_pattern
{
  unsigned int mask;            /* mask the insn with this...  */
  unsigned int data;            /* ...and see if it matches this.  */
  int optional;                 /* If non-zero, this insn may be absent.  */
};

extern int ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc,
				    const struct ppc_insn_pattern *pattern,
				    unsigned int *insns);
extern CORE_ADDR ppc_insn_d_field (unsigned int insn);

extern CORE_ADDR ppc_insn_ds_field (unsigned int insn);

extern int ppc_process_record (struct gdbarch *gdbarch,
			       struct regcache *regcache, CORE_ADDR addr);

/* Instruction size.  */
#define PPC_INSN_SIZE 4

/* Estimate for the maximum number of instructions in a function epilogue.  */
#define PPC_MAX_EPILOGUE_INSTRUCTIONS  52

#endif /* ppc-tdep.h */
Commit	Line	Data
9aa1e687	1	/* Target-dependent code for GDB, the GNU debugger.
f9be684a	2
11bc5fe4	3	Copyright (C) 2000-2020 Free Software Foundation, Inc.
9aa1e687 KB	4
	5	This file is part of GDB.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
a9762ec7	9	the Free Software Foundation; either version 3 of the License, or
9aa1e687 KB	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
a9762ec7	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
9aa1e687	19
3a1c5313 AC	20	#ifndef PPC_TDEP_H
	21	#define PPC_TDEP_H
	22
0d12e84c TT	23	#include "gdbarch.h"
0d12e84c TT	24
da3331ec	25	struct gdbarch;
3a1c5313 AC	26	struct frame_info;
3a1c5313 AC	27	struct value;
4a4b3fed	28	struct regcache;
221c12ff	29	struct type;
3a1c5313	30
0df8b418	31	/* From ppc-sysv-tdep.c ... */
05580c65	32	enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
6a3a010b	33	struct value *function,
05580c65 AC	34	struct type *valtype,
05580c65 AC	35	struct regcache *regcache,
50fd1280 AC	36	gdb_byte *readbuf,
50fd1280 AC	37	const gdb_byte *writebuf);
05580c65	38	enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
6a3a010b	39	struct value *function,
05580c65 AC	40	struct type *valtype,
05580c65 AC	41	struct regcache *regcache,
50fd1280 AC	42	gdb_byte *readbuf,
50fd1280 AC	43	const gdb_byte *writebuf);
cf84fa6b AH	44
	45	CORE_ADDR ppc_sysv_abi_push_dummy_call
	46	(struct gdbarch gdbarch, struct value function, struct regcache *regcache,
	47	CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp,
	48	function_call_return_method return_method, CORE_ADDR struct_addr);
	49
	50	CORE_ADDR ppc64_sysv_abi_push_dummy_call
	51	(struct gdbarch gdbarch, struct value function, struct regcache *regcache,
	52	CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp,
	53	function_call_return_method return_method, CORE_ADDR struct_addr);
	54
05580c65	55	enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
6a3a010b	56	struct value *function,
05580c65 AC	57	struct type *valtype,
05580c65 AC	58	struct regcache *regcache,
50fd1280 AC	59	gdb_byte *readbuf,
50fd1280 AC	60	const gdb_byte *writebuf);
9aa1e687	61
0df8b418	62	/* From rs6000-tdep.c... */
be8626e0	63	int altivec_register_p (struct gdbarch *gdbarch, int regno);
604c2f83	64	int vsx_register_p (struct gdbarch *gdbarch, int regno);
be8626e0	65	int spe_register_p (struct gdbarch *gdbarch, int regno);
9aa1e687	66
383f0f5b JB	67	/* Return non-zero if the architecture described by GDBARCH has
383f0f5b JB	68	floating-point registers (f0 --- f31 and fpscr). */
0a613259 AC	69	int ppc_floating_point_unit_p (struct gdbarch *gdbarch);
0a613259 AC	70
06caf7d2 CES	71	/* Return non-zero if the architecture described by GDBARCH has
	72	Altivec registers (vr0 --- vr31, vrsave and vscr). */
	73	int ppc_altivec_support_p (struct gdbarch *gdbarch);
	74
604c2f83 LM	75	/* Return non-zero if the architecture described by GDBARCH has
	76	VSX registers (vsr0 --- vsr63). */
	77	int vsx_support_p (struct gdbarch *gdbarch);
a0ff9e1a SM	78	std::vector<CORE_ADDR> ppc_deal_with_atomic_sequence
a0ff9e1a SM	79	(struct regcache *regcache);
4a7622d1 UW	80
4a7622d1 UW	81
d195bc9f MK	82	/* Register set description. */
	83
	84	struct ppc_reg_offsets
	85	{
	86	/* General-purpose registers. */
	87	int r0_offset;
f2db237a AM	88	int gpr_size; /* size for r0-31, pc, ps, lr, ctr. */
f2db237a AM	89	int xr_size; /* size for cr, xer, mq. */
d195bc9f MK	90	int pc_offset;
	91	int ps_offset;
	92	int cr_offset;
	93	int lr_offset;
	94	int ctr_offset;
	95	int xer_offset;
	96	int mq_offset;
	97
	98	/* Floating-point registers. */
	99	int f0_offset;
	100	int fpscr_offset;
f2db237a	101	int fpscr_size;
d195bc9f MK	102	};
d195bc9f MK	103
7284e1be UW	104	extern void ppc_supply_reg (struct regcache *regcache, int regnum,
	105	const gdb_byte *regs, size_t offset, int regsize);
	106
	107	extern void ppc_collect_reg (const struct regcache *regcache, int regnum,
	108	gdb_byte *regs, size_t offset, int regsize);
	109
d195bc9f MK	110	/* Supply register REGNUM in the general-purpose register set REGSET
	111	from the buffer specified by GREGS and LEN to register cache
	112	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	113
	114	extern void ppc_supply_gregset (const struct regset *regset,
	115	struct regcache *regcache,
	116	int regnum, const void *gregs, size_t len);
	117
	118	/* Supply register REGNUM in the floating-point register set REGSET
	119	from the buffer specified by FPREGS and LEN to register cache
	120	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	121
	122	extern void ppc_supply_fpregset (const struct regset *regset,
	123	struct regcache *regcache,
	124	int regnum, const void *fpregs, size_t len);
	125
06caf7d2 CES	126	/* Supply register REGNUM in the Altivec register set REGSET
	127	from the buffer specified by VRREGS and LEN to register cache
	128	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	129
	130	extern void ppc_supply_vrregset (const struct regset *regset,
	131	struct regcache *regcache,
	132	int regnum, const void *vrregs, size_t len);
	133
604c2f83 LM	134	/* Supply register REGNUM in the VSX register set REGSET
	135	from the buffer specified by VSXREGS and LEN to register cache
	136	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	137
	138	extern void ppc_supply_vsxregset (const struct regset *regset,
	139	struct regcache *regcache,
	140	int regnum, const void *vsxregs, size_t len);
	141
d195bc9f	142	/* Collect register REGNUM in the general-purpose register set
0df8b418	143	REGSET, from register cache REGCACHE into the buffer specified by
d195bc9f MK	144	GREGS and LEN. If REGNUM is -1, do this for all registers in
	145	REGSET. */
	146
	147	extern void ppc_collect_gregset (const struct regset *regset,
	148	const struct regcache *regcache,
	149	int regnum, void *gregs, size_t len);
	150
	151	/* Collect register REGNUM in the floating-point register set
0df8b418	152	REGSET, from register cache REGCACHE into the buffer specified by
d195bc9f MK	153	FPREGS and LEN. If REGNUM is -1, do this for all registers in
	154	REGSET. */
	155
	156	extern void ppc_collect_fpregset (const struct regset *regset,
	157	const struct regcache *regcache,
	158	int regnum, void *fpregs, size_t len);
	159
06caf7d2 CES	160	/* Collect register REGNUM in the Altivec register set
	161	REGSET from register cache REGCACHE into the buffer specified by
	162	VRREGS and LEN. If REGNUM is -1, do this for all registers in
	163	REGSET. */
	164
	165	extern void ppc_collect_vrregset (const struct regset *regset,
	166	const struct regcache *regcache,
	167	int regnum, void *vrregs, size_t len);
	168
604c2f83 LM	169	/* Collect register REGNUM in the VSX register set
	170	REGSET from register cache REGCACHE into the buffer specified by
	171	VSXREGS and LEN. If REGNUM is -1, do this for all registers in
	172	REGSET. */
	173
	174	extern void ppc_collect_vsxregset (const struct regset *regset,
	175	const struct regcache *regcache,
	176	int regnum, void *vsxregs, size_t len);
	177
0df8b418	178	/* Private data that this module attaches to struct gdbarch. */
2188cbdd	179
cd453cd0 UW	180	/* ELF ABI version used by the inferior. */
	181	enum powerpc_elf_abi
	182	{
	183	POWERPC_ELF_AUTO,
	184	POWERPC_ELF_V1,
	185	POWERPC_ELF_V2,
	186	POWERPC_ELF_LAST
	187	};
	188
55eddb0f DJ	189	/* Vector ABI used by the inferior. */
	190	enum powerpc_vector_abi
	191	{
	192	POWERPC_VEC_AUTO,
	193	POWERPC_VEC_GENERIC,
	194	POWERPC_VEC_ALTIVEC,
	195	POWERPC_VEC_SPE,
	196	POWERPC_VEC_LAST
	197	};
	198
ed0f4273 UW	199	/* long double ABI version used by the inferior. */
	200	enum powerpc_long_double_abi
	201	{
	202	POWERPC_LONG_DOUBLE_AUTO,
	203	POWERPC_LONG_DOUBLE_IBM128,
	204	POWERPC_LONG_DOUBLE_IEEE128,
	205	POWERPC_LONG_DOUBLE_LAST
	206	};
	207
2188cbdd EZ	208	struct gdbarch_tdep
2188cbdd EZ	209	{
55eddb0f DJ	210	int wordsize; /* Size in bytes of fixed-point word. */
	211	int soft_float; /* Avoid FP registers for arguments? */
	212
cd453cd0 UW	213	enum powerpc_elf_abi elf_abi; /* ELF ABI version. */
cd453cd0 UW	214
ed0f4273 UW	215	/* Format to use for the "long double" data type. */
	216	enum powerpc_long_double_abi long_double_abi;
	217
55eddb0f DJ	218	/* How to pass vector arguments. Never set to AUTO or LAST. */
	219	enum powerpc_vector_abi vector_abi;
	220
2188cbdd	221	int ppc_gp0_regnum; /* GPR register 0 */
2188cbdd EZ	222	int ppc_toc_regnum; /* TOC register */
	223	int ppc_ps_regnum; /* Processor (or machine) status (%msr) */
	224	int ppc_cr_regnum; /* Condition register */
	225	int ppc_lr_regnum; /* Link register */
	226	int ppc_ctr_regnum; /* Count register */
	227	int ppc_xer_regnum; /* Integer exception register */
383f0f5b	228
826d5376 PG	229	/* Not all PPC and RS6000 variants will have the registers
	230	represented below. A -1 is used to indicate that the register
	231	is not present in this variant. */
	232
	233	/* Floating-point registers. */
0df8b418 MS	234	int ppc_fp0_regnum; /* Floating-point register 0. */
0df8b418 MS	235	int ppc_fpscr_regnum; /* fp status and condition register. */
826d5376	236
826d5376 PG	237	/* Multiplier-Quotient Register (older POWER architectures only). */
826d5376 PG	238	int ppc_mq_regnum;
f86a7158	239
604c2f83 LM	240	/* POWER7 VSX registers. */
	241	int ppc_vsr0_regnum; /* First VSX register. */
	242	int ppc_vsr0_upper_regnum; /* First right most dword vsx register. */
	243	int ppc_efpr0_regnum; /* First Extended FP register. */
	244
826d5376	245	/* Altivec registers. */
0df8b418 MS	246	int ppc_vr0_regnum; /* First AltiVec register. */
0df8b418 MS	247	int ppc_vrsave_regnum; /* Last AltiVec register. */
826d5376	248
6f072a10 PFC	249	/* Altivec pseudo-register vX aliases for the raw vrX
	250	registers. */
	251	int ppc_v0_alias_regnum;
	252
826d5376	253	/* SPE registers. */
0df8b418 MS	254	int ppc_ev0_upper_regnum; /* First GPR upper half register. */
	255	int ppc_ev0_regnum; /* First ev register. */
	256	int ppc_acc_regnum; /* SPE 'acc' register. */
	257	int ppc_spefscr_regnum; /* SPE 'spefscr' register. */
826d5376	258
7ca18ed6 EBM	259	/* Program Priority Register. */
	260	int ppc_ppr_regnum;
	261
	262	/* Data Stream Control Register. */
	263	int ppc_dscr_regnum;
	264
f2cf6173 EBM	265	/* Target Address Register. */
	266	int ppc_tar_regnum;
	267
f949c649 TJB	268	/* Decimal 128 registers. */
	269	int ppc_dl0_regnum; /* First Decimal128 argument register pair. */
	270
232bfb86 EBM	271	int have_ebb;
	272
	273	/* PMU registers. */
	274	int ppc_mmcr0_regnum;
	275	int ppc_mmcr2_regnum;
	276	int ppc_siar_regnum;
	277	int ppc_sdar_regnum;
	278	int ppc_sier_regnum;
	279
8d619c01 EBM	280	/* Hardware Transactional Memory registers. */
	281	int have_htm_spr;
	282	int have_htm_core;
	283	int have_htm_fpu;
	284	int have_htm_altivec;
	285	int have_htm_vsx;
	286	int ppc_cppr_regnum;
	287	int ppc_cdscr_regnum;
	288	int ppc_ctar_regnum;
	289
	290	/* HTM pseudo registers. */
	291	int ppc_cdl0_regnum;
	292	int ppc_cvsr0_regnum;
	293	int ppc_cefpr0_regnum;
	294
826d5376 PG	295	/* Offset to ABI specific location where link register is saved. */
826d5376 PG	296	int lr_frame_offset;
9f643768 JB	297
	298	/* An array of integers, such that sim_regno[I] is the simulator
	299	register number for GDB register number I, or -1 if the
	300	simulator does not implement that register. */
	301	int *sim_regno;
6f7f3f0d	302
794ac428 UW	303	/* ISA-specific types. */
794ac428 UW	304	struct type *ppc_builtin_type_vec64;
604c2f83	305	struct type *ppc_builtin_type_vec128;
b4cdae6f WW	306
b4cdae6f WW	307	int (ppc_syscall_record) (struct regcache regcache);
2188cbdd	308	};
3a1c5313	309
b967e06f JB	310
	311	/* Constants for register set sizes. */
	312	enum
	313	{
604c2f83 LM	314	ppc_num_gprs = 32, /* 32 general-purpose registers. */
	315	ppc_num_fprs = 32, /* 32 floating-point registers. */
	316	ppc_num_srs = 16, /* 16 segment registers. */
	317	ppc_num_vrs = 32, /* 32 Altivec vector registers. */
	318	ppc_num_vshrs = 32, /* 32 doublewords (dword 1 of vs0~vs31). */
	319	ppc_num_vsrs = 64, /* 64 VSX vector registers. */
	320	ppc_num_efprs = 32 /* 32 Extended FP registers. */
b967e06f JB	321	};
b967e06f JB	322
0ea0ec5f	323
7cc46491 DJ	324	/* Register number constants. These are GDB internal register
	325	numbers; they are not used for the simulator or remote targets.
	326	Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given
	327	numbers above PPC_NUM_REGS. So are segment registers and other
	328	target-defined registers. */
	329	enum {
	330	PPC_R0_REGNUM = 0,
	331	PPC_F0_REGNUM = 32,
	332	PPC_PC_REGNUM = 64,
	333	PPC_MSR_REGNUM = 65,
	334	PPC_CR_REGNUM = 66,
	335	PPC_LR_REGNUM = 67,
	336	PPC_CTR_REGNUM = 68,
	337	PPC_XER_REGNUM = 69,
	338	PPC_FPSCR_REGNUM = 70,
	339	PPC_MQ_REGNUM = 71,
	340	PPC_SPE_UPPER_GP0_REGNUM = 72,
	341	PPC_SPE_ACC_REGNUM = 104,
	342	PPC_SPE_FSCR_REGNUM = 105,
	343	PPC_VR0_REGNUM = 106,
	344	PPC_VSCR_REGNUM = 138,
	345	PPC_VRSAVE_REGNUM = 139,
604c2f83 LM	346	PPC_VSR0_UPPER_REGNUM = 140,
604c2f83 LM	347	PPC_VSR31_UPPER_REGNUM = 171,
7ca18ed6 EBM	348	PPC_PPR_REGNUM = 172,
7ca18ed6 EBM	349	PPC_DSCR_REGNUM = 173,
f2cf6173	350	PPC_TAR_REGNUM = 174,
232bfb86 EBM	351
	352	/* EBB registers. */
	353	PPC_BESCR_REGNUM = 175,
	354	PPC_EBBHR_REGNUM = 176,
	355	PPC_EBBRR_REGNUM = 177,
	356
	357	/* PMU registers. */
	358	PPC_MMCR0_REGNUM = 178,
	359	PPC_MMCR2_REGNUM = 179,
	360	PPC_SIAR_REGNUM = 180,
	361	PPC_SDAR_REGNUM = 181,
	362	PPC_SIER_REGNUM = 182,
	363
8d619c01 EBM	364	/* Hardware transactional memory registers. */
	365	PPC_TFHAR_REGNUM = 183,
	366	PPC_TEXASR_REGNUM = 184,
	367	PPC_TFIAR_REGNUM = 185,
	368
	369	PPC_CR0_REGNUM = 186,
	370	PPC_CCR_REGNUM = 218,
	371	PPC_CXER_REGNUM = 219,
	372	PPC_CLR_REGNUM = 220,
	373	PPC_CCTR_REGNUM = 221,
	374
	375	PPC_CF0_REGNUM = 222,
	376	PPC_CFPSCR_REGNUM = 254,
	377
	378	PPC_CVR0_REGNUM = 255,
	379	PPC_CVSCR_REGNUM = 287,
	380	PPC_CVRSAVE_REGNUM = 288,
	381
	382	PPC_CVSR0_UPPER_REGNUM = 289,
	383
	384	PPC_CPPR_REGNUM = 321,
	385	PPC_CDSCR_REGNUM = 322,
	386	PPC_CTAR_REGNUM = 323,
7cc46491 DJ	387	PPC_NUM_REGS
7cc46491 DJ	388	};
0ea0ec5f	389
0f068fb5 AH	390	/* Big enough to hold the size of the largest register in bytes. */
	391	#define PPC_MAX_REGISTER_SIZE 64
	392
232bfb86 EBM	393	#define PPC_IS_EBB_REGNUM(i) \
	394	((i) >= PPC_BESCR_REGNUM && (i) <= PPC_EBBRR_REGNUM)
	395
	396	#define PPC_IS_PMU_REGNUM(i) \
	397	((i) >= PPC_MMCR0_REGNUM && (i) <= PPC_SIER_REGNUM)
	398
8d619c01 EBM	399	#define PPC_IS_TMSPR_REGNUM(i) \
	400	((i) >= PPC_TFHAR_REGNUM && (i) <= PPC_TFIAR_REGNUM)
	401
	402	#define PPC_IS_CKPTGP_REGNUM(i) \
	403	((i) >= PPC_CR0_REGNUM && (i) <= PPC_CCTR_REGNUM)
	404
	405	#define PPC_IS_CKPTFP_REGNUM(i) \
	406	((i) >= PPC_CF0_REGNUM && (i) <= PPC_CFPSCR_REGNUM)
	407
	408	#define PPC_IS_CKPTVMX_REGNUM(i) \
	409	((i) >= PPC_CVR0_REGNUM && (i) <= PPC_CVRSAVE_REGNUM)
	410
	411	#define PPC_IS_CKPTVSX_REGNUM(i) \
	412	((i) >= PPC_CVSR0_UPPER_REGNUM && (i) < (PPC_CVSR0_UPPER_REGNUM + 32))
	413
d78489bf AT	414	/* An instruction to match. */
	415
	416	struct ppc_insn_pattern
	417	{
	418	unsigned int mask; /* mask the insn with this... */
	419	unsigned int data; /* ...and see if it matches this. */
	420	int optional; /* If non-zero, this insn may be absent. */
	421	};
	422
845d4708	423	extern int ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc,
7433498b	424	const struct ppc_insn_pattern *pattern,
845d4708	425	unsigned int *insns);
d78489bf AT	426	extern CORE_ADDR ppc_insn_d_field (unsigned int insn);
	427
	428	extern CORE_ADDR ppc_insn_ds_field (unsigned int insn);
0ea0ec5f	429
b4cdae6f WW	430	extern int ppc_process_record (struct gdbarch *gdbarch,
	431	struct regcache *regcache, CORE_ADDR addr);
	432
a0c75879 MK	433	/* Instruction size. */
	434	#define PPC_INSN_SIZE 4
	435
30baf67b	436	/* Estimate for the maximum number of instructions in a function epilogue. */
0d1243d9 PG	437	#define PPC_MAX_EPILOGUE_INSTRUCTIONS 52
0d1243d9 PG	438
a0c75879	439	#endif /* ppc-tdep.h */