[deliverable/binutils-gdb.git] / gdb / ppcnbsd-tdep.c

/* Target-dependent code for PowerPC systems running NetBSD.

   Copyright 2002, 2003, 2004 Free Software Foundation, Inc.

   Contributed by Wasabi Systems, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place - Suite 330,
   Boston, MA 02111-1307, USA.  */

#include "defs.h"
#include "gdbcore.h"
#include "regcache.h"
#include "target.h"
#include "breakpoint.h"
#include "value.h"
#include "osabi.h"

#include "ppc-tdep.h"
#include "ppcnbsd-tdep.h"
#include "nbsd-tdep.h"
#include "tramp-frame.h"
#include "trad-frame.h"
#include "gdb_assert.h"
#include "solib-svr4.h"

#define REG_FIXREG_OFFSET(x)	((x) * 4)
#define REG_LR_OFFSET		(32 * 4)
#define REG_CR_OFFSET		(33 * 4)
#define REG_XER_OFFSET		(34 * 4)
#define REG_CTR_OFFSET		(35 * 4)
#define REG_PC_OFFSET		(36 * 4)
#define SIZEOF_STRUCT_REG	(37 * 4)

#define FPREG_FPR_OFFSET(x)	((x) * 8)
#define FPREG_FPSCR_OFFSET	(32 * 8)
#define SIZEOF_STRUCT_FPREG	(33 * 8)

void
ppcnbsd_supply_reg (char *regs, int regno)
{
  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
  int i;

  for (i = 0; i < ppc_num_gprs; i++)
    {
      if (regno == tdep->ppc_gp0_regnum + i || regno == -1)
	supply_register (tdep->ppc_gp0_regnum + i,
                         regs + REG_FIXREG_OFFSET (i));
    }

  if (regno == tdep->ppc_lr_regnum || regno == -1)
    supply_register (tdep->ppc_lr_regnum, regs + REG_LR_OFFSET);

  if (regno == tdep->ppc_cr_regnum || regno == -1)
    supply_register (tdep->ppc_cr_regnum, regs + REG_CR_OFFSET);

  if (regno == tdep->ppc_xer_regnum || regno == -1)
    supply_register (tdep->ppc_xer_regnum, regs + REG_XER_OFFSET);

  if (regno == tdep->ppc_ctr_regnum || regno == -1)
    supply_register (tdep->ppc_ctr_regnum, regs + REG_CTR_OFFSET);

  if (regno == PC_REGNUM || regno == -1)
    supply_register (PC_REGNUM, regs + REG_PC_OFFSET);
}

void
ppcnbsd_fill_reg (char *regs, int regno)
{
  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
  int i;

  for (i = 0; i < ppc_num_gprs; i++)
    {
      if (regno == tdep->ppc_gp0_regnum + i || regno == -1)
	regcache_collect (tdep->ppc_gp0_regnum + i,
                          regs + REG_FIXREG_OFFSET (i));
    }

  if (regno == tdep->ppc_lr_regnum || regno == -1)
    regcache_collect (tdep->ppc_lr_regnum, regs + REG_LR_OFFSET);

  if (regno == tdep->ppc_cr_regnum || regno == -1)
    regcache_collect (tdep->ppc_cr_regnum, regs + REG_CR_OFFSET);

  if (regno == tdep->ppc_xer_regnum || regno == -1)
    regcache_collect (tdep->ppc_xer_regnum, regs + REG_XER_OFFSET);

  if (regno == tdep->ppc_ctr_regnum || regno == -1)
    regcache_collect (tdep->ppc_ctr_regnum, regs + REG_CTR_OFFSET);

  if (regno == PC_REGNUM || regno == -1)
    regcache_collect (PC_REGNUM, regs + REG_PC_OFFSET);
}

void
ppcnbsd_supply_fpreg (char *fpregs, int regno)
{
  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
  int i;

  /* FIXME: jimb/2004-05-05: Some PPC variants don't have floating
     point registers.  Traditionally, GDB's register set has still
     listed the floating point registers for such machines, so this
     code is harmless.  However, the new E500 port actually omits the
     floating point registers entirely from the register set --- they
     don't even have register numbers assigned to them.

     It's not clear to me how best to update this code, so this assert
     will alert the first person to encounter the NetBSD/E500
     combination to the problem.  */
  gdb_assert (ppc_floating_point_unit_p (current_gdbarch));

  for (i = 0; i < ppc_num_fprs; i++)
    {
      if (regno == tdep->ppc_fp0_regnum + i || regno == -1)
	supply_register (tdep->ppc_fp0_regnum + i,
                         fpregs + FPREG_FPR_OFFSET (i));
    }

  if (regno == tdep->ppc_fpscr_regnum || regno == -1)
    supply_register (tdep->ppc_fpscr_regnum, fpregs + FPREG_FPSCR_OFFSET);
}

void
ppcnbsd_fill_fpreg (char *fpregs, int regno)
{
  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
  int i;

  /* FIXME: jimb/2004-05-05: Some PPC variants don't have floating
     point registers.  Traditionally, GDB's register set has still
     listed the floating point registers for such machines, so this
     code is harmless.  However, the new E500 port actually omits the
     floating point registers entirely from the register set --- they
     don't even have register numbers assigned to them.

     It's not clear to me how best to update this code, so this assert
     will alert the first person to encounter the NetBSD/E500
     combination to the problem.  */
  gdb_assert (ppc_floating_point_unit_p (current_gdbarch));

  for (i = 0; i < ppc_num_fprs; i++)
    {
      if (regno == tdep->ppc_fp0_regnum + i || regno == -1)
	regcache_collect (tdep->ppc_fp0_regnum + i,
                          fpregs + FPREG_FPR_OFFSET (i));
    }

  if (regno == tdep->ppc_fpscr_regnum || regno == -1)
    regcache_collect (tdep->ppc_fpscr_regnum, fpregs + FPREG_FPSCR_OFFSET);
}

static void
fetch_core_registers (char *core_reg_sect, unsigned core_reg_size, int which,
                      CORE_ADDR ignore)
{
  char *regs, *fpregs;

  /* We get everything from one section.  */
  if (which != 0)
    return;

  regs = core_reg_sect;
  fpregs = core_reg_sect + SIZEOF_STRUCT_REG;

  /* Integer registers.  */
  ppcnbsd_supply_reg (regs, -1);

  /* Floating point registers.  */
  ppcnbsd_supply_fpreg (fpregs, -1);
}

static void
fetch_elfcore_registers (char *core_reg_sect, unsigned core_reg_size, int which,
                         CORE_ADDR ignore)
{
  switch (which)
    {
    case 0:  /* Integer registers.  */
      if (core_reg_size != SIZEOF_STRUCT_REG)
	warning ("Wrong size register set in core file.");
      else
	ppcnbsd_supply_reg (core_reg_sect, -1);
      break;

    case 2:  /* Floating point registers.  */
      if (core_reg_size != SIZEOF_STRUCT_FPREG)
	warning ("Wrong size FP register set in core file.");
      else
	ppcnbsd_supply_fpreg (core_reg_sect, -1);
      break;

    default:
      /* Don't know what kind of register request this is; just ignore it.  */
      break;
    }
}

static struct core_fns ppcnbsd_core_fns =
{
  bfd_target_unknown_flavour,		/* core_flavour */
  default_check_format,			/* check_format */
  default_core_sniffer,			/* core_sniffer */
  fetch_core_registers,			/* core_read_registers */
  NULL					/* next */
};

static struct core_fns ppcnbsd_elfcore_fns =
{
  bfd_target_elf_flavour,		/* core_flavour */
  default_check_format,			/* check_format */
  default_core_sniffer,			/* core_sniffer */
  fetch_elfcore_registers,		/* core_read_registers */
  NULL					/* next */
};

/* NetBSD is confused.  It appears that 1.5 was using the correct SVr4
   convention but, 1.6 switched to the below broken convention.  For
   the moment use the broken convention.  Ulgh!.  */

static enum return_value_convention
ppcnbsd_return_value (struct gdbarch *gdbarch, struct type *valtype,
		      struct regcache *regcache, void *readbuf,
		      const void *writebuf)
{
  if ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
       || TYPE_CODE (valtype) == TYPE_CODE_UNION)
      && !((TYPE_LENGTH (valtype) == 16 || TYPE_LENGTH (valtype) == 8)
	    && TYPE_VECTOR (valtype))
      && !(TYPE_LENGTH (valtype) == 1
	   || TYPE_LENGTH (valtype) == 2
	   || TYPE_LENGTH (valtype) == 4
	   || TYPE_LENGTH (valtype) == 8))
    return RETURN_VALUE_STRUCT_CONVENTION;
  else
    return ppc_sysv_abi_broken_return_value (gdbarch, valtype, regcache,
					     readbuf, writebuf);
}

static void
ppcnbsd_sigtramp_cache_init (const struct tramp_frame *self,
			     struct frame_info *next_frame,
			     struct trad_frame_cache *this_cache,
			     CORE_ADDR func)
{
  CORE_ADDR base;
  CORE_ADDR offset;
  int i;
  struct gdbarch *gdbarch = get_frame_arch (next_frame);
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
  offset = base + 0x18 + 2 * tdep->wordsize;
  for (i = 0; i < ppc_num_gprs; i++)
    {
      int regnum = i + tdep->ppc_gp0_regnum;
      trad_frame_set_reg_addr (this_cache, regnum, offset);
      offset += tdep->wordsize;
    }
  trad_frame_set_reg_addr (this_cache, tdep->ppc_lr_regnum, offset);
  offset += tdep->wordsize;
  trad_frame_set_reg_addr (this_cache, tdep->ppc_cr_regnum, offset);
  offset += tdep->wordsize;
  trad_frame_set_reg_addr (this_cache, tdep->ppc_xer_regnum, offset);
  offset += tdep->wordsize;
  trad_frame_set_reg_addr (this_cache, tdep->ppc_ctr_regnum, offset);
  offset += tdep->wordsize;
  trad_frame_set_reg_addr (this_cache, PC_REGNUM, offset); /* SRR0? */
  offset += tdep->wordsize;

  /* Construct the frame ID using the function start.  */
  trad_frame_set_id (this_cache, frame_id_build (base, func));
}

/* Given the NEXT frame, examine the instructions at and around this
   frame's resume address (aka PC) to see of they look like a signal
   trampoline.  Return the address of the trampolines first
   instruction, or zero if it isn't a signal trampoline.  */

static const struct tramp_frame ppcnbsd_sigtramp = {
  SIGTRAMP_FRAME,
  4, /* insn size */
  { /* insn */
    { 0x38610018, -1 }, /* addi r3,r1,24 */
    { 0x38000127, -1 }, /* li r0,295 */
    { 0x44000002, -1 }, /* sc */
    { 0x38000001, -1 }, /* li r0,1 */
    { 0x44000002, -1 }, /* sc */
    { TRAMP_SENTINEL_INSN, -1 }
  },
  ppcnbsd_sigtramp_cache_init
};

static void
ppcnbsd_init_abi (struct gdbarch_info info,
                  struct gdbarch *gdbarch)
{
  /* For NetBSD, this is an on again, off again thing.  Some systems
     do use the broken struct convention, and some don't.  */
  set_gdbarch_return_value (gdbarch, ppcnbsd_return_value);
  set_solib_svr4_fetch_link_map_offsets (gdbarch,
                                nbsd_ilp32_solib_svr4_fetch_link_map_offsets);
  tramp_frame_prepend_unwinder (gdbarch, &ppcnbsd_sigtramp);
}

void
_initialize_ppcnbsd_tdep (void)
{
  gdbarch_register_osabi (bfd_arch_powerpc, 0, GDB_OSABI_NETBSD_ELF,
			  ppcnbsd_init_abi);

  deprecated_add_core_fns (&ppcnbsd_core_fns);
  deprecated_add_core_fns (&ppcnbsd_elfcore_fns);
}
Commit	Line	Data
485721b1	1	/* Target-dependent code for PowerPC systems running NetBSD.
476be15e AC	2
	3	Copyright 2002, 2003, 2004 Free Software Foundation, Inc.
	4
485721b1 JT	5	Contributed by Wasabi Systems, Inc.
	6
	7	This file is part of GDB.
	8
	9	This program is free software; you can redistribute it and/or modify
	10	it under the terms of the GNU General Public License as published by
	11	the Free Software Foundation; either version 2 of the License, or
	12	(at your option) any later version.
	13
	14	This program is distributed in the hope that it will be useful,
	15	but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	GNU General Public License for more details.
	18
	19	You should have received a copy of the GNU General Public License
	20	along with this program; if not, write to the Free Software
	21	Foundation, Inc., 59 Temple Place - Suite 330,
	22	Boston, MA 02111-1307, USA. */
	23
	24	#include "defs.h"
	25	#include "gdbcore.h"
	26	#include "regcache.h"
	27	#include "target.h"
	28	#include "breakpoint.h"
	29	#include "value.h"
4be87837	30	#include "osabi.h"
485721b1 JT	31
	32	#include "ppc-tdep.h"
	33	#include "ppcnbsd-tdep.h"
	34	#include "nbsd-tdep.h"
476be15e AC	35	#include "tramp-frame.h"
476be15e AC	36	#include "trad-frame.h"
d28b44a7	37	#include "gdb_assert.h"
485721b1 JT	38	#include "solib-svr4.h"
	39
	40	#define REG_FIXREG_OFFSET(x) ((x) * 4)
	41	#define REG_LR_OFFSET (32 * 4)
	42	#define REG_CR_OFFSET (33 * 4)
	43	#define REG_XER_OFFSET (34 * 4)
	44	#define REG_CTR_OFFSET (35 * 4)
	45	#define REG_PC_OFFSET (36 * 4)
	46	#define SIZEOF_STRUCT_REG (37 * 4)
	47
	48	#define FPREG_FPR_OFFSET(x) ((x) * 8)
	49	#define FPREG_FPSCR_OFFSET (32 * 8)
	50	#define SIZEOF_STRUCT_FPREG (33 * 8)
	51
	52	void
	53	ppcnbsd_supply_reg (char *regs, int regno)
	54	{
	55	struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
	56	int i;
	57
063715bf	58	for (i = 0; i < ppc_num_gprs; i++)
485721b1	59	{
cdf2c5f5 JB	60	if (regno == tdep->ppc_gp0_regnum + i \|\| regno == -1)
	61	supply_register (tdep->ppc_gp0_regnum + i,
	62	regs + REG_FIXREG_OFFSET (i));
485721b1 JT	63	}
	64
	65	if (regno == tdep->ppc_lr_regnum \|\| regno == -1)
	66	supply_register (tdep->ppc_lr_regnum, regs + REG_LR_OFFSET);
	67
	68	if (regno == tdep->ppc_cr_regnum \|\| regno == -1)
	69	supply_register (tdep->ppc_cr_regnum, regs + REG_CR_OFFSET);
	70
	71	if (regno == tdep->ppc_xer_regnum \|\| regno == -1)
	72	supply_register (tdep->ppc_xer_regnum, regs + REG_XER_OFFSET);
	73
	74	if (regno == tdep->ppc_ctr_regnum \|\| regno == -1)
	75	supply_register (tdep->ppc_ctr_regnum, regs + REG_CTR_OFFSET);
	76
	77	if (regno == PC_REGNUM \|\| regno == -1)
	78	supply_register (PC_REGNUM, regs + REG_PC_OFFSET);
	79	}
	80
	81	void
	82	ppcnbsd_fill_reg (char *regs, int regno)
	83	{
	84	struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
	85	int i;
	86
063715bf	87	for (i = 0; i < ppc_num_gprs; i++)
485721b1	88	{
cdf2c5f5 JB	89	if (regno == tdep->ppc_gp0_regnum + i \|\| regno == -1)
	90	regcache_collect (tdep->ppc_gp0_regnum + i,
	91	regs + REG_FIXREG_OFFSET (i));
485721b1 JT	92	}
	93
	94	if (regno == tdep->ppc_lr_regnum \|\| regno == -1)
	95	regcache_collect (tdep->ppc_lr_regnum, regs + REG_LR_OFFSET);
	96
	97	if (regno == tdep->ppc_cr_regnum \|\| regno == -1)
	98	regcache_collect (tdep->ppc_cr_regnum, regs + REG_CR_OFFSET);
	99
	100	if (regno == tdep->ppc_xer_regnum \|\| regno == -1)
	101	regcache_collect (tdep->ppc_xer_regnum, regs + REG_XER_OFFSET);
	102
	103	if (regno == tdep->ppc_ctr_regnum \|\| regno == -1)
	104	regcache_collect (tdep->ppc_ctr_regnum, regs + REG_CTR_OFFSET);
	105
	106	if (regno == PC_REGNUM \|\| regno == -1)
	107	regcache_collect (PC_REGNUM, regs + REG_PC_OFFSET);
	108	}
	109
	110	void
	111	ppcnbsd_supply_fpreg (char *fpregs, int regno)
	112	{
	113	struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
	114	int i;
	115
383f0f5b JB	116	/* FIXME: jimb/2004-05-05: Some PPC variants don't have floating
	117	point registers. Traditionally, GDB's register set has still
	118	listed the floating point registers for such machines, so this
	119	code is harmless. However, the new E500 port actually omits the
	120	floating point registers entirely from the register set --- they
	121	don't even have register numbers assigned to them.
	122
	123	It's not clear to me how best to update this code, so this assert
	124	will alert the first person to encounter the NetBSD/E500
	125	combination to the problem. */
	126	gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
	127
366f009f	128	for (i = 0; i < ppc_num_fprs; i++)
485721b1	129	{
366f009f JB	130	if (regno == tdep->ppc_fp0_regnum + i \|\| regno == -1)
	131	supply_register (tdep->ppc_fp0_regnum + i,
	132	fpregs + FPREG_FPR_OFFSET (i));
485721b1 JT	133	}
	134
	135	if (regno == tdep->ppc_fpscr_regnum \|\| regno == -1)
	136	supply_register (tdep->ppc_fpscr_regnum, fpregs + FPREG_FPSCR_OFFSET);
	137	}
	138
	139	void
	140	ppcnbsd_fill_fpreg (char *fpregs, int regno)
	141	{
	142	struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
	143	int i;
	144
383f0f5b JB	145	/* FIXME: jimb/2004-05-05: Some PPC variants don't have floating
	146	point registers. Traditionally, GDB's register set has still
	147	listed the floating point registers for such machines, so this
	148	code is harmless. However, the new E500 port actually omits the
	149	floating point registers entirely from the register set --- they
	150	don't even have register numbers assigned to them.
	151
	152	It's not clear to me how best to update this code, so this assert
	153	will alert the first person to encounter the NetBSD/E500
	154	combination to the problem. */
	155	gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
	156
366f009f	157	for (i = 0; i < ppc_num_fprs; i++)
485721b1	158	{
366f009f JB	159	if (regno == tdep->ppc_fp0_regnum + i \|\| regno == -1)
	160	regcache_collect (tdep->ppc_fp0_regnum + i,
	161	fpregs + FPREG_FPR_OFFSET (i));
485721b1 JT	162	}
	163
	164	if (regno == tdep->ppc_fpscr_regnum \|\| regno == -1)
	165	regcache_collect (tdep->ppc_fpscr_regnum, fpregs + FPREG_FPSCR_OFFSET);
	166	}
	167
	168	static void
	169	fetch_core_registers (char *core_reg_sect, unsigned core_reg_size, int which,
	170	CORE_ADDR ignore)
	171	{
	172	char regs, fpregs;
	173
	174	/* We get everything from one section. */
	175	if (which != 0)
	176	return;
	177
	178	regs = core_reg_sect;
	179	fpregs = core_reg_sect + SIZEOF_STRUCT_REG;
	180
	181	/* Integer registers. */
	182	ppcnbsd_supply_reg (regs, -1);
	183
	184	/* Floating point registers. */
	185	ppcnbsd_supply_fpreg (fpregs, -1);
	186	}
	187
	188	static void
	189	fetch_elfcore_registers (char *core_reg_sect, unsigned core_reg_size, int which,
	190	CORE_ADDR ignore)
	191	{
	192	switch (which)
	193	{
	194	case 0: /* Integer registers. */
	195	if (core_reg_size != SIZEOF_STRUCT_REG)
	196	warning ("Wrong size register set in core file.");
	197	else
	198	ppcnbsd_supply_reg (core_reg_sect, -1);
	199	break;
	200
	201	case 2: /* Floating point registers. */
	202	if (core_reg_size != SIZEOF_STRUCT_FPREG)
	203	warning ("Wrong size FP register set in core file.");
	204	else
	205	ppcnbsd_supply_fpreg (core_reg_sect, -1);
	206	break;
	207
	208	default:
	209	/* Don't know what kind of register request this is; just ignore it. */
	210	break;
	211	}
	212	}
	213
	214	static struct core_fns ppcnbsd_core_fns =
	215	{
	216	bfd_target_unknown_flavour, /* core_flavour */
	217	default_check_format, /* check_format */
	218	default_core_sniffer, /* core_sniffer */
	219	fetch_core_registers, /* core_read_registers */
	220	NULL /* next */
	221	};
	222
	223	static struct core_fns ppcnbsd_elfcore_fns =
	224	{
	225	bfd_target_elf_flavour, /* core_flavour */
226	default_check_format, /* check_format */
227	default_core_sniffer, /* core_sniffer */
228	fetch_elfcore_registers, /* core_read_registers */
229	NULL /* next */
230	};
231
957e27ac AC	232	/* NetBSD is confused. It appears that 1.5 was using the correct SVr4
	233	convention but, 1.6 switched to the below broken convention. For
	234	the moment use the broken convention. Ulgh!. */
	235
05580c65 AC	236	static enum return_value_convention
05580c65 AC	237	ppcnbsd_return_value (struct gdbarch gdbarch, struct type valtype,
963e2bb7 AC	238	struct regcache regcache, void readbuf,
963e2bb7 AC	239	const void *writebuf)
05580c65 AC	240	{
	241	if ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
	242	\|\| TYPE_CODE (valtype) == TYPE_CODE_UNION)
	243	&& !((TYPE_LENGTH (valtype) == 16 \|\| TYPE_LENGTH (valtype) == 8)
	244	&& TYPE_VECTOR (valtype))
	245	&& !(TYPE_LENGTH (valtype) == 1
	246	\|\| TYPE_LENGTH (valtype) == 2
	247	\|\| TYPE_LENGTH (valtype) == 4
	248	\|\| TYPE_LENGTH (valtype) == 8))
	249	return RETURN_VALUE_STRUCT_CONVENTION;
	250	else
	251	return ppc_sysv_abi_broken_return_value (gdbarch, valtype, regcache,
963e2bb7	252	readbuf, writebuf);
957e27ac AC	253	}
957e27ac AC	254
476be15e AC	255	static void
	256	ppcnbsd_sigtramp_cache_init (const struct tramp_frame *self,
	257	struct frame_info *next_frame,
	258	struct trad_frame_cache *this_cache,
	259	CORE_ADDR func)
	260	{
	261	CORE_ADDR base;
	262	CORE_ADDR offset;
	263	int i;
	264	struct gdbarch *gdbarch = get_frame_arch (next_frame);
	265	struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
	266
	267	base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
	268	offset = base + 0x18 + 2 * tdep->wordsize;
063715bf	269	for (i = 0; i < ppc_num_gprs; i++)
476be15e AC	270	{
	271	int regnum = i + tdep->ppc_gp0_regnum;
	272	trad_frame_set_reg_addr (this_cache, regnum, offset);
	273	offset += tdep->wordsize;
	274	}
	275	trad_frame_set_reg_addr (this_cache, tdep->ppc_lr_regnum, offset);
	276	offset += tdep->wordsize;
	277	trad_frame_set_reg_addr (this_cache, tdep->ppc_cr_regnum, offset);
	278	offset += tdep->wordsize;
	279	trad_frame_set_reg_addr (this_cache, tdep->ppc_xer_regnum, offset);
	280	offset += tdep->wordsize;
	281	trad_frame_set_reg_addr (this_cache, tdep->ppc_ctr_regnum, offset);
	282	offset += tdep->wordsize;
	283	trad_frame_set_reg_addr (this_cache, PC_REGNUM, offset); /* SRR0? */
	284	offset += tdep->wordsize;
	285
	286	/* Construct the frame ID using the function start. */
	287	trad_frame_set_id (this_cache, frame_id_build (base, func));
	288	}
	289
	290	/* Given the NEXT frame, examine the instructions at and around this
	291	frame's resume address (aka PC) to see of they look like a signal
	292	trampoline. Return the address of the trampolines first
	293	instruction, or zero if it isn't a signal trampoline. */
	294
	295	static const struct tramp_frame ppcnbsd_sigtramp = {
2cd8546d	296	SIGTRAMP_FRAME,
476be15e AC	297	4, /* insn size */
476be15e AC	298	{ /* insn */
2cd8546d AC	299	{ 0x38610018, -1 }, /* addi r3,r1,24 */
	300	{ 0x38000127, -1 }, /* li r0,295 */
	301	{ 0x44000002, -1 }, /* sc */
	302	{ 0x38000001, -1 }, /* li r0,1 */
	303	{ 0x44000002, -1 }, /* sc */
	304	{ TRAMP_SENTINEL_INSN, -1 }
476be15e AC	305	},
	306	ppcnbsd_sigtramp_cache_init
	307	};
	308
485721b1 JT	309	static void
	310	ppcnbsd_init_abi (struct gdbarch_info info,
	311	struct gdbarch *gdbarch)
	312	{
e754ae69 AC	313	/* For NetBSD, this is an on again, off again thing. Some systems
e754ae69 AC	314	do use the broken struct convention, and some don't. */
05580c65	315	set_gdbarch_return_value (gdbarch, ppcnbsd_return_value);
485721b1 JT	316	set_solib_svr4_fetch_link_map_offsets (gdbarch,
485721b1 JT	317	nbsd_ilp32_solib_svr4_fetch_link_map_offsets);
476be15e	318	tramp_frame_prepend_unwinder (gdbarch, &ppcnbsd_sigtramp);
485721b1 JT	319	}
	320
	321	void
	322	_initialize_ppcnbsd_tdep (void)
	323	{
05816f70	324	gdbarch_register_osabi (bfd_arch_powerpc, 0, GDB_OSABI_NETBSD_ELF,
485721b1 JT	325	ppcnbsd_init_abi);
485721b1 JT	326
00e32a35 AC	327	deprecated_add_core_fns (&ppcnbsd_core_fns);
00e32a35 AC	328	deprecated_add_core_fns (&ppcnbsd_elfcore_fns);
485721b1	329	}