[deliverable/binutils-gdb.git] / gdb / riscv-fbsd-tdep.c

/* Target-dependent code for FreeBSD on RISC-V processors.
   Copyright (C) 2018-2019 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#include "defs.h"
#include "fbsd-tdep.h"
#include "osabi.h"
#include "riscv-tdep.h"
#include "riscv-fbsd-tdep.h"
#include "solib-svr4.h"
#include "target.h"
#include "trad-frame.h"
#include "tramp-frame.h"

/* Register maps.  */

static const struct regcache_map_entry riscv_fbsd_gregmap[] =
  {
    { 1, RISCV_RA_REGNUM, 0 },
    { 1, RISCV_SP_REGNUM, 0 },
    { 1, RISCV_GP_REGNUM, 0 },
    { 1, RISCV_TP_REGNUM, 0 },
    { 3, 5, 0 },		/* t0 - t2 */
    { 4, 28, 0 },		/* t3 - t6 */
    { 2, RISCV_FP_REGNUM, 0 },	/* s0 - s1 */
    { 10, 18, 0 },		/* s2 - s11 */
    { 8, RISCV_A0_REGNUM, 0 },	/* a0 - a7 */
    { 1, RISCV_PC_REGNUM, 0 },
    { 1, RISCV_CSR_SSTATUS_REGNUM, 0 },
    { 0 }
  };

static const struct regcache_map_entry riscv_fbsd_fpregmap[] =
  {
    { 32, RISCV_FIRST_FP_REGNUM, 16 },
    { 1, RISCV_CSR_FCSR_REGNUM, 8 },
    { 0 }
  };

/* Supply the general-purpose registers stored in GREGS to REGCACHE.
   This function only exists to supply the always-zero x0 in addition
   to the registers in GREGS.  */

static void
riscv_fbsd_supply_gregset (const struct regset *regset,
			   struct regcache *regcache, int regnum,
			   const void *gregs, size_t len)
{
  regcache->supply_regset (&riscv_fbsd_gregset, regnum, gregs, len);
  if (regnum == -1 || regnum == RISCV_ZERO_REGNUM)
    regcache->raw_supply_zeroed (RISCV_ZERO_REGNUM);
}

/* Register set definitions.  */

const struct regset riscv_fbsd_gregset =
  {
    riscv_fbsd_gregmap,
    riscv_fbsd_supply_gregset, regcache_collect_regset
  };

const struct regset riscv_fbsd_fpregset =
  {
    riscv_fbsd_fpregmap,
    regcache_supply_regset, regcache_collect_regset
  };

/* Implement the "regset_from_core_section" gdbarch method.  */

static void
riscv_fbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
					 iterate_over_regset_sections_cb *cb,
					 void *cb_data,
					 const struct regcache *regcache)
{
  cb (".reg", RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch),
      RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch),
      &riscv_fbsd_gregset, NULL, cb_data);
  cb (".reg2", RISCV_FBSD_SIZEOF_FPREGSET, RISCV_FBSD_SIZEOF_FPREGSET,
      &riscv_fbsd_fpregset, NULL, cb_data);
}

/* In a signal frame, sp points to a 'struct sigframe' which is
   defined as:

   struct sigframe {
	   siginfo_t	sf_si;
	   ucontext_t	sf_uc;
   };

   ucontext_t is defined as:

   struct __ucontext {
	   sigset_t	uc_sigmask;
	   mcontext_t	uc_mcontext;
	   ...
   };

   The mcontext_t contains the general purpose register set followed
   by the floating point register set.  The floating point register
   set is only valid if the _MC_FP_VALID flag is set in mc_flags.  */

#define RISCV_SIGFRAME_UCONTEXT_OFFSET 		80
#define RISCV_UCONTEXT_MCONTEXT_OFFSET		16
#define RISCV_MCONTEXT_FLAG_FP_VALID		0x1

/* Implement the "init" method of struct tramp_frame.  */

static void
riscv_fbsd_sigframe_init (const struct tramp_frame *self,
			  struct frame_info *this_frame,
			  struct trad_frame_cache *this_cache,
			  CORE_ADDR func)
{
  struct gdbarch *gdbarch = get_frame_arch (this_frame);
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  CORE_ADDR sp = get_frame_register_unsigned (this_frame, RISCV_SP_REGNUM);
  CORE_ADDR mcontext_addr
    = (sp
       + RISCV_SIGFRAME_UCONTEXT_OFFSET
       + RISCV_UCONTEXT_MCONTEXT_OFFSET);
  gdb_byte buf[4];

  trad_frame_set_reg_regmap (this_cache, riscv_fbsd_gregmap, mcontext_addr,
			     RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch));

  CORE_ADDR fpregs_addr
    = mcontext_addr + RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch);
  CORE_ADDR fp_flags_addr
    = fpregs_addr + RISCV_FBSD_SIZEOF_FPREGSET;
  if (target_read_memory (fp_flags_addr, buf, 4) == 0
      && (extract_unsigned_integer (buf, 4, byte_order)
	  & RISCV_MCONTEXT_FLAG_FP_VALID))
    trad_frame_set_reg_regmap (this_cache, riscv_fbsd_fpregmap, fpregs_addr,
			       RISCV_FBSD_SIZEOF_FPREGSET);

  trad_frame_set_id (this_cache, frame_id_build (sp, func));
}

/* RISC-V supports 16-bit instructions ("C") as well as 32-bit
   instructions.  The signal trampoline on FreeBSD uses a mix of
   these, but tramp_frame assumes a fixed instruction size.  To cope,
   claim that all instructions are 16 bits and use two "slots" for
   32-bit instructions.  */

static const struct tramp_frame riscv_fbsd_sigframe =
{
  SIGTRAMP_FRAME,
  2,
  {
    {0x850a, ULONGEST_MAX},		/* mov  a0, sp  */
    {0x0513, ULONGEST_MAX},		/* addi a0, a0, #SF_UC  */
    {0x0505, ULONGEST_MAX},
    {0x0293, ULONGEST_MAX},		/* li   t0, #SYS_sigreturn  */
    {0x1a10, ULONGEST_MAX},
    {0x0073, ULONGEST_MAX},		/* ecall  */
    {0x0000, ULONGEST_MAX},
    {TRAMP_SENTINEL_INSN, ULONGEST_MAX}
  },
  riscv_fbsd_sigframe_init
};

/* Implement the "get_thread_local_address" gdbarch method.  */

static CORE_ADDR
riscv_fbsd_get_thread_local_address (struct gdbarch *gdbarch, ptid_t ptid,
				     CORE_ADDR lm_addr, CORE_ADDR offset)
{
  struct regcache *regcache;

  regcache = get_thread_arch_regcache (ptid, gdbarch);

  target_fetch_registers (regcache, RISCV_TP_REGNUM);

  ULONGEST tp;
  if (regcache->cooked_read (RISCV_TP_REGNUM, &tp) != REG_VALID)
    error (_("Unable to fetch %%tp"));

  /* %tp points to the end of the TCB which contains two pointers.
      The first pointer in the TCB points to the DTV array.  */
  CORE_ADDR dtv_addr = tp - (gdbarch_ptr_bit (gdbarch) / 8) * 2;
  return fbsd_get_thread_local_address (gdbarch, dtv_addr, lm_addr, offset);
}

/* Implement the 'init_osabi' method of struct gdb_osabi_handler.  */

static void
riscv_fbsd_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
{
  /* Generic FreeBSD support.  */
  fbsd_init_abi (info, gdbarch);

  set_gdbarch_software_single_step (gdbarch, riscv_software_single_step);

  set_solib_svr4_fetch_link_map_offsets (gdbarch,
					 (riscv_isa_xlen (gdbarch) == 4
					  ? svr4_ilp32_fetch_link_map_offsets
					  : svr4_lp64_fetch_link_map_offsets));

  tramp_frame_prepend_unwinder (gdbarch, &riscv_fbsd_sigframe);

  set_gdbarch_iterate_over_regset_sections
    (gdbarch, riscv_fbsd_iterate_over_regset_sections);

  set_gdbarch_fetch_tls_load_module_address (gdbarch,
					     svr4_fetch_objfile_link_map);
  set_gdbarch_get_thread_local_address (gdbarch,
					riscv_fbsd_get_thread_local_address);
}

void
_initialize_riscv_fbsd_tdep (void)
{
  gdbarch_register_osabi (bfd_arch_riscv, 0, GDB_OSABI_FREEBSD,
			  riscv_fbsd_init_abi);
}
Commit	Line	Data
ed65e20b	1	/* Target-dependent code for FreeBSD on RISC-V processors.
42a4f53d	2	Copyright (C) 2018-2019 Free Software Foundation, Inc.
ed65e20b JB	3
	4	This file is part of GDB.
	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 3 of the License, or
	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
	17	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	18
	19	#include "defs.h"
	20	#include "fbsd-tdep.h"
	21	#include "osabi.h"
	22	#include "riscv-tdep.h"
	23	#include "riscv-fbsd-tdep.h"
	24	#include "solib-svr4.h"
	25	#include "target.h"
	26	#include "trad-frame.h"
	27	#include "tramp-frame.h"
	28
	29	/* Register maps. */
	30
	31	static const struct regcache_map_entry riscv_fbsd_gregmap[] =
	32	{
	33	{ 1, RISCV_RA_REGNUM, 0 },
	34	{ 1, RISCV_SP_REGNUM, 0 },
	35	{ 1, RISCV_GP_REGNUM, 0 },
	36	{ 1, RISCV_TP_REGNUM, 0 },
	37	{ 3, 5, 0 }, /* t0 - t2 */
	38	{ 4, 28, 0 }, /* t3 - t6 */
	39	{ 2, RISCV_FP_REGNUM, 0 }, /* s0 - s1 */
	40	{ 10, 18, 0 }, /* s2 - s11 */
	41	{ 8, RISCV_A0_REGNUM, 0 }, /* a0 - a7 */
	42	{ 1, RISCV_PC_REGNUM, 0 },
	43	{ 1, RISCV_CSR_SSTATUS_REGNUM, 0 },
	44	{ 0 }
	45	};
	46
	47	static const struct regcache_map_entry riscv_fbsd_fpregmap[] =
	48	{
	49	{ 32, RISCV_FIRST_FP_REGNUM, 16 },
	50	{ 1, RISCV_CSR_FCSR_REGNUM, 8 },
	51	{ 0 }
	52	};
	53
	54	/* Supply the general-purpose registers stored in GREGS to REGCACHE.
	55	This function only exists to supply the always-zero x0 in addition
	56	to the registers in GREGS. */
	57
	58	static void
	59	riscv_fbsd_supply_gregset (const struct regset *regset,
	60	struct regcache *regcache, int regnum,
	61	const void *gregs, size_t len)
	62	{
	63	regcache->supply_regset (&riscv_fbsd_gregset, regnum, gregs, len);
	64	if (regnum == -1 \|\| regnum == RISCV_ZERO_REGNUM)
	65	regcache->raw_supply_zeroed (RISCV_ZERO_REGNUM);
	66	}
67
68	/* Register set definitions. */
69
70	const struct regset riscv_fbsd_gregset =
71	{
72	riscv_fbsd_gregmap,
73	riscv_fbsd_supply_gregset, regcache_collect_regset
74	};
75
76	const struct regset riscv_fbsd_fpregset =
77	{
78	riscv_fbsd_fpregmap,
79	regcache_supply_regset, regcache_collect_regset
80	};
81
82	/* Implement the "regset_from_core_section" gdbarch method. */
83
84	static void
85	riscv_fbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
86	iterate_over_regset_sections_cb *cb,
87	void *cb_data,
88	const struct regcache *regcache)
89	{
90	cb (".reg", RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch),
91	RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch),
92	&riscv_fbsd_gregset, NULL, cb_data);
93	cb (".reg2", RISCV_FBSD_SIZEOF_FPREGSET, RISCV_FBSD_SIZEOF_FPREGSET,
94	&riscv_fbsd_fpregset, NULL, cb_data);
95	}
96
97	/* In a signal frame, sp points to a 'struct sigframe' which is
98	defined as:
99
100	struct sigframe {
101	siginfo_t sf_si;
102	ucontext_t sf_uc;
103	};
104
105	ucontext_t is defined as:
106
107	struct __ucontext {
108	sigset_t uc_sigmask;
109	mcontext_t uc_mcontext;
110	...
111	};
112
113	The mcontext_t contains the general purpose register set followed
114	by the floating point register set. The floating point register
115	set is only valid if the _MC_FP_VALID flag is set in mc_flags. */
116
117	#define RISCV_SIGFRAME_UCONTEXT_OFFSET 80
118	#define RISCV_UCONTEXT_MCONTEXT_OFFSET 16
119	#define RISCV_MCONTEXT_FLAG_FP_VALID 0x1
120
121	/* Implement the "init" method of struct tramp_frame. */
122
123	static void
124	riscv_fbsd_sigframe_init (const struct tramp_frame *self,
125	struct frame_info *this_frame,
126	struct trad_frame_cache *this_cache,
127	CORE_ADDR func)
128	{
129	struct gdbarch *gdbarch = get_frame_arch (this_frame);
130	enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
131	CORE_ADDR sp = get_frame_register_unsigned (this_frame, RISCV_SP_REGNUM);
132	CORE_ADDR mcontext_addr
133	= (sp
134	+ RISCV_SIGFRAME_UCONTEXT_OFFSET
135	+ RISCV_UCONTEXT_MCONTEXT_OFFSET);
136	gdb_byte buf[4];
ed65e20b JB	137
	138	trad_frame_set_reg_regmap (this_cache, riscv_fbsd_gregmap, mcontext_addr,
	139	RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch));
	140
	141	CORE_ADDR fpregs_addr
	142	= mcontext_addr + RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch);
	143	CORE_ADDR fp_flags_addr
	144	= fpregs_addr + RISCV_FBSD_SIZEOF_FPREGSET;
	145	if (target_read_memory (fp_flags_addr, buf, 4) == 0
	146	&& (extract_unsigned_integer (buf, 4, byte_order)
	147	& RISCV_MCONTEXT_FLAG_FP_VALID))
	148	trad_frame_set_reg_regmap (this_cache, riscv_fbsd_fpregmap, fpregs_addr,
	149	RISCV_FBSD_SIZEOF_FPREGSET);
	150
	151	trad_frame_set_id (this_cache, frame_id_build (sp, func));
	152	}
	153
	154	/* RISC-V supports 16-bit instructions ("C") as well as 32-bit
	155	instructions. The signal trampoline on FreeBSD uses a mix of
	156	these, but tramp_frame assumes a fixed instruction size. To cope,
	157	claim that all instructions are 16 bits and use two "slots" for
	158	32-bit instructions. */
	159
	160	static const struct tramp_frame riscv_fbsd_sigframe =
	161	{
	162	SIGTRAMP_FRAME,
	163	2,
	164	{
	165	{0x850a, ULONGEST_MAX}, /* mov a0, sp */
	166	{0x0513, ULONGEST_MAX}, /* addi a0, a0, #SF_UC */
	167	{0x0505, ULONGEST_MAX},
	168	{0x0293, ULONGEST_MAX}, /* li t0, #SYS_sigreturn */
	169	{0x1a10, ULONGEST_MAX},
	170	{0x0073, ULONGEST_MAX}, /* ecall */
	171	{0x0000, ULONGEST_MAX},
	172	{TRAMP_SENTINEL_INSN, ULONGEST_MAX}
	173	},
	174	riscv_fbsd_sigframe_init
	175	};
	176
b0f87ed0 JB	177	/* Implement the "get_thread_local_address" gdbarch method. */
	178
	179	static CORE_ADDR
	180	riscv_fbsd_get_thread_local_address (struct gdbarch *gdbarch, ptid_t ptid,
	181	CORE_ADDR lm_addr, CORE_ADDR offset)
	182	{
	183	struct regcache *regcache;
	184
	185	regcache = get_thread_arch_regcache (ptid, gdbarch);
	186
	187	target_fetch_registers (regcache, RISCV_TP_REGNUM);
	188
	189	ULONGEST tp;
	190	if (regcache->cooked_read (RISCV_TP_REGNUM, &tp) != REG_VALID)
	191	error (_("Unable to fetch %%tp"));
	192
	193	/* %tp points to the end of the TCB which contains two pointers.
	194	The first pointer in the TCB points to the DTV array. */
	195	CORE_ADDR dtv_addr = tp - (gdbarch_ptr_bit (gdbarch) / 8) * 2;
	196	return fbsd_get_thread_local_address (gdbarch, dtv_addr, lm_addr, offset);
	197	}
	198
ed65e20b JB	199	/* Implement the 'init_osabi' method of struct gdb_osabi_handler. */
	200
	201	static void
	202	riscv_fbsd_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
	203	{
ed65e20b JB	204	/* Generic FreeBSD support. */
	205	fbsd_init_abi (info, gdbarch);
	206
	207	set_gdbarch_software_single_step (gdbarch, riscv_software_single_step);
	208
	209	set_solib_svr4_fetch_link_map_offsets (gdbarch,
	210	(riscv_isa_xlen (gdbarch) == 4
	211	? svr4_ilp32_fetch_link_map_offsets
	212	: svr4_lp64_fetch_link_map_offsets));
	213
	214	tramp_frame_prepend_unwinder (gdbarch, &riscv_fbsd_sigframe);
	215
	216	set_gdbarch_iterate_over_regset_sections
	217	(gdbarch, riscv_fbsd_iterate_over_regset_sections);
b0f87ed0 JB	218
	219	set_gdbarch_fetch_tls_load_module_address (gdbarch,
	220	svr4_fetch_objfile_link_map);
	221	set_gdbarch_get_thread_local_address (gdbarch,
	222	riscv_fbsd_get_thread_local_address);
ed65e20b JB	223	}
	224
	225	void
	226	_initialize_riscv_fbsd_tdep (void)
	227	{
	228	gdbarch_register_osabi (bfd_arch_riscv, 0, GDB_OSABI_FREEBSD,
	229	riscv_fbsd_init_abi);
	230	}