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dbbb1059 AB |
1 | /* Target-dependent code for the RISC-V architecture, for GDB. |
2 | ||
3 | Copyright (C) 2018 Free Software Foundation, Inc. | |
4 | ||
dbbb1059 AB |
5 | This file is part of GDB. |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "inferior.h" | |
23 | #include "symtab.h" | |
24 | #include "value.h" | |
25 | #include "gdbcmd.h" | |
26 | #include "language.h" | |
27 | #include "gdbcore.h" | |
28 | #include "symfile.h" | |
29 | #include "objfiles.h" | |
30 | #include "gdbtypes.h" | |
31 | #include "target.h" | |
32 | #include "arch-utils.h" | |
33 | #include "regcache.h" | |
34 | #include "osabi.h" | |
35 | #include "riscv-tdep.h" | |
36 | #include "block.h" | |
37 | #include "reggroups.h" | |
38 | #include "opcode/riscv.h" | |
39 | #include "elf/riscv.h" | |
40 | #include "elf-bfd.h" | |
41 | #include "symcat.h" | |
42 | #include "dis-asm.h" | |
43 | #include "frame-unwind.h" | |
44 | #include "frame-base.h" | |
45 | #include "trad-frame.h" | |
46 | #include "infcall.h" | |
47 | #include "floatformat.h" | |
48 | #include "remote.h" | |
49 | #include "target-descriptions.h" | |
50 | #include "dwarf2-frame.h" | |
51 | #include "user-regs.h" | |
52 | #include "valprint.h" | |
53 | #include "common-defs.h" | |
54 | #include "opcode/riscv-opc.h" | |
55 | #include "cli/cli-decode.h" | |
76727919 | 56 | #include "observable.h" |
78a3b0fa | 57 | #include "prologue-value.h" |
dbbb1059 AB |
58 | |
59 | /* The stack must be 16-byte aligned. */ | |
60 | #define SP_ALIGNMENT 16 | |
61 | ||
62 | /* Forward declarations. */ | |
63 | static bool riscv_has_feature (struct gdbarch *gdbarch, char feature); | |
dbbb1059 AB |
64 | |
65 | /* Define a series of is_XXX_insn functions to check if the value INSN | |
66 | is an instance of instruction XXX. */ | |
67 | #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \ | |
68 | static inline bool is_ ## INSN_NAME ## _insn (long insn) \ | |
69 | { \ | |
70 | return (insn & INSN_MASK) == INSN_MATCH; \ | |
71 | } | |
72 | #include "opcode/riscv-opc.h" | |
73 | #undef DECLARE_INSN | |
74 | ||
78a3b0fa AB |
75 | /* Cached information about a frame. */ |
76 | ||
77 | struct riscv_unwind_cache | |
78 | { | |
79 | /* The register from which we can calculate the frame base. This is | |
80 | usually $sp or $fp. */ | |
81 | int frame_base_reg; | |
82 | ||
83 | /* The offset from the current value in register FRAME_BASE_REG to the | |
84 | actual frame base address. */ | |
85 | int frame_base_offset; | |
86 | ||
87 | /* Information about previous register values. */ | |
88 | struct trad_frame_saved_reg *regs; | |
89 | ||
90 | /* The id for this frame. */ | |
91 | struct frame_id this_id; | |
92 | ||
93 | /* The base (stack) address for this frame. This is the stack pointer | |
94 | value on entry to this frame before any adjustments are made. */ | |
95 | CORE_ADDR frame_base; | |
96 | }; | |
97 | ||
0dbfcfff AB |
98 | /* The preferred register names for all the general purpose and floating |
99 | point registers. These are what GDB will use when referencing a | |
100 | register. */ | |
dbbb1059 AB |
101 | |
102 | static const char * const riscv_gdb_reg_names[RISCV_LAST_FP_REGNUM + 1] = | |
103 | { | |
0dbfcfff AB |
104 | "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1", |
105 | "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", | |
106 | "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", | |
107 | "pc", | |
108 | "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1", | |
109 | "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", "fs2", "fs3", | |
110 | "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", | |
111 | "ft10", "ft11", | |
dbbb1059 AB |
112 | }; |
113 | ||
0dbfcfff | 114 | /* Map alternative register names onto their GDB register number. */ |
dbbb1059 | 115 | |
0dbfcfff | 116 | struct riscv_register_alias |
dbbb1059 AB |
117 | { |
118 | /* The register alias. Usually more descriptive than the | |
119 | architectural name of the register. */ | |
120 | const char *name; | |
121 | ||
122 | /* The GDB register number. */ | |
123 | int regnum; | |
124 | }; | |
125 | ||
126 | /* Table of register aliases. */ | |
127 | ||
0dbfcfff | 128 | static const struct riscv_register_alias riscv_register_aliases[] = |
dbbb1059 | 129 | { |
0dbfcfff AB |
130 | /* Aliases for general purpose registers. These are the architectural |
131 | names, as GDB uses the more user friendly names by default. */ | |
132 | { "x0", (RISCV_ZERO_REGNUM + 0) }, | |
133 | { "x1", (RISCV_ZERO_REGNUM + 1) }, | |
134 | { "x2", (RISCV_ZERO_REGNUM + 2) }, | |
135 | { "x3", (RISCV_ZERO_REGNUM + 3) }, | |
136 | { "x4", (RISCV_ZERO_REGNUM + 4) }, | |
137 | { "x5", (RISCV_ZERO_REGNUM + 5) }, | |
138 | { "x6", (RISCV_ZERO_REGNUM + 6) }, | |
139 | { "x7", (RISCV_ZERO_REGNUM + 7) }, | |
140 | { "x8", (RISCV_ZERO_REGNUM + 8) }, | |
141 | { "s0", (RISCV_ZERO_REGNUM + 8) }, /* fp, s0, and x8 are all aliases. */ | |
142 | { "x9", (RISCV_ZERO_REGNUM + 9) }, | |
143 | { "x10", (RISCV_ZERO_REGNUM + 10) }, | |
144 | { "x11", (RISCV_ZERO_REGNUM + 11) }, | |
145 | { "x12", (RISCV_ZERO_REGNUM + 12) }, | |
146 | { "x13", (RISCV_ZERO_REGNUM + 13) }, | |
147 | { "x14", (RISCV_ZERO_REGNUM + 14) }, | |
148 | { "x15", (RISCV_ZERO_REGNUM + 15) }, | |
149 | { "x16", (RISCV_ZERO_REGNUM + 16) }, | |
150 | { "x17", (RISCV_ZERO_REGNUM + 17) }, | |
151 | { "x18", (RISCV_ZERO_REGNUM + 18) }, | |
152 | { "x19", (RISCV_ZERO_REGNUM + 19) }, | |
153 | { "x20", (RISCV_ZERO_REGNUM + 20) }, | |
154 | { "x21", (RISCV_ZERO_REGNUM + 21) }, | |
155 | { "x22", (RISCV_ZERO_REGNUM + 22) }, | |
156 | { "x23", (RISCV_ZERO_REGNUM + 23) }, | |
157 | { "x24", (RISCV_ZERO_REGNUM + 24) }, | |
158 | { "x25", (RISCV_ZERO_REGNUM + 25) }, | |
159 | { "x26", (RISCV_ZERO_REGNUM + 26) }, | |
160 | { "x27", (RISCV_ZERO_REGNUM + 27) }, | |
161 | { "x28", (RISCV_ZERO_REGNUM + 28) }, | |
162 | { "x29", (RISCV_ZERO_REGNUM + 29) }, | |
163 | { "x30", (RISCV_ZERO_REGNUM + 30) }, | |
164 | { "x31", (RISCV_ZERO_REGNUM + 31) }, | |
165 | ||
166 | /* Aliases for the floating-point registers. These are the architectural | |
167 | names as GDB uses the more user friendly names by default. */ | |
168 | { "f0", (RISCV_FIRST_FP_REGNUM + 0) }, | |
169 | { "f1", (RISCV_FIRST_FP_REGNUM + 1) }, | |
170 | { "f2", (RISCV_FIRST_FP_REGNUM + 2) }, | |
171 | { "f3", (RISCV_FIRST_FP_REGNUM + 3) }, | |
172 | { "f4", (RISCV_FIRST_FP_REGNUM + 4) }, | |
173 | { "f5", (RISCV_FIRST_FP_REGNUM + 5) }, | |
174 | { "f6", (RISCV_FIRST_FP_REGNUM + 6) }, | |
175 | { "f7", (RISCV_FIRST_FP_REGNUM + 7) }, | |
176 | { "f8", (RISCV_FIRST_FP_REGNUM + 8) }, | |
177 | { "f9", (RISCV_FIRST_FP_REGNUM + 9) }, | |
178 | { "f10", (RISCV_FIRST_FP_REGNUM + 10) }, | |
179 | { "f11", (RISCV_FIRST_FP_REGNUM + 11) }, | |
180 | { "f12", (RISCV_FIRST_FP_REGNUM + 12) }, | |
181 | { "f13", (RISCV_FIRST_FP_REGNUM + 13) }, | |
182 | { "f14", (RISCV_FIRST_FP_REGNUM + 14) }, | |
183 | { "f15", (RISCV_FIRST_FP_REGNUM + 15) }, | |
184 | { "f16", (RISCV_FIRST_FP_REGNUM + 16) }, | |
185 | { "f17", (RISCV_FIRST_FP_REGNUM + 17) }, | |
186 | { "f18", (RISCV_FIRST_FP_REGNUM + 18) }, | |
187 | { "f19", (RISCV_FIRST_FP_REGNUM + 19) }, | |
188 | { "f20", (RISCV_FIRST_FP_REGNUM + 20) }, | |
189 | { "f21", (RISCV_FIRST_FP_REGNUM + 21) }, | |
190 | { "f22", (RISCV_FIRST_FP_REGNUM + 22) }, | |
191 | { "f23", (RISCV_FIRST_FP_REGNUM + 23) }, | |
192 | { "f24", (RISCV_FIRST_FP_REGNUM + 24) }, | |
193 | { "f25", (RISCV_FIRST_FP_REGNUM + 25) }, | |
194 | { "f26", (RISCV_FIRST_FP_REGNUM + 26) }, | |
195 | { "f27", (RISCV_FIRST_FP_REGNUM + 27) }, | |
196 | { "f28", (RISCV_FIRST_FP_REGNUM + 28) }, | |
197 | { "f29", (RISCV_FIRST_FP_REGNUM + 29) }, | |
198 | { "f30", (RISCV_FIRST_FP_REGNUM + 30) }, | |
199 | { "f31", (RISCV_FIRST_FP_REGNUM + 31) }, | |
dbbb1059 AB |
200 | }; |
201 | ||
202 | /* Controls whether we place compressed breakpoints or not. When in auto | |
203 | mode GDB tries to determine if the target supports compressed | |
204 | breakpoints, and uses them if it does. */ | |
205 | ||
206 | static enum auto_boolean use_compressed_breakpoints; | |
207 | ||
208 | /* The show callback for 'show riscv use-compressed-breakpoints'. */ | |
209 | ||
210 | static void | |
211 | show_use_compressed_breakpoints (struct ui_file *file, int from_tty, | |
212 | struct cmd_list_element *c, | |
213 | const char *value) | |
214 | { | |
dbbb1059 AB |
215 | fprintf_filtered (file, |
216 | _("Debugger's use of compressed breakpoints is set " | |
f37bc8b1 | 217 | "to %s.\n"), value); |
dbbb1059 AB |
218 | } |
219 | ||
220 | /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */ | |
221 | ||
222 | static struct cmd_list_element *setriscvcmdlist = NULL; | |
223 | static struct cmd_list_element *showriscvcmdlist = NULL; | |
224 | ||
225 | /* The show callback for the 'show riscv' prefix command. */ | |
226 | ||
227 | static void | |
228 | show_riscv_command (const char *args, int from_tty) | |
229 | { | |
230 | help_list (showriscvcmdlist, "show riscv ", all_commands, gdb_stdout); | |
231 | } | |
232 | ||
233 | /* The set callback for the 'set riscv' prefix command. */ | |
234 | ||
235 | static void | |
236 | set_riscv_command (const char *args, int from_tty) | |
237 | { | |
238 | printf_unfiltered | |
239 | (_("\"set riscv\" must be followed by an appropriate subcommand.\n")); | |
240 | help_list (setriscvcmdlist, "set riscv ", all_commands, gdb_stdout); | |
241 | } | |
242 | ||
243 | /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */ | |
244 | ||
245 | static struct cmd_list_element *setdebugriscvcmdlist = NULL; | |
246 | static struct cmd_list_element *showdebugriscvcmdlist = NULL; | |
247 | ||
248 | /* The show callback for the 'show debug riscv' prefix command. */ | |
249 | ||
250 | static void | |
251 | show_debug_riscv_command (const char *args, int from_tty) | |
252 | { | |
253 | help_list (showdebugriscvcmdlist, "show debug riscv ", all_commands, gdb_stdout); | |
254 | } | |
255 | ||
256 | /* The set callback for the 'set debug riscv' prefix command. */ | |
257 | ||
258 | static void | |
259 | set_debug_riscv_command (const char *args, int from_tty) | |
260 | { | |
261 | printf_unfiltered | |
262 | (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n")); | |
263 | help_list (setdebugriscvcmdlist, "set debug riscv ", all_commands, gdb_stdout); | |
264 | } | |
265 | ||
266 | /* The show callback for all 'show debug riscv VARNAME' variables. */ | |
267 | ||
268 | static void | |
269 | show_riscv_debug_variable (struct ui_file *file, int from_tty, | |
270 | struct cmd_list_element *c, | |
271 | const char *value) | |
272 | { | |
273 | fprintf_filtered (file, | |
274 | _("RiscV debug variable `%s' is set to: %s\n"), | |
275 | c->name, value); | |
276 | } | |
277 | ||
f37bc8b1 JB |
278 | /* When this is set to non-zero debugging information about breakpoint |
279 | kinds will be printed. */ | |
280 | ||
281 | static unsigned int riscv_debug_breakpoints = 0; | |
282 | ||
dbbb1059 AB |
283 | /* When this is set to non-zero debugging information about inferior calls |
284 | will be printed. */ | |
285 | ||
286 | static unsigned int riscv_debug_infcall = 0; | |
287 | ||
78a3b0fa AB |
288 | /* When this is set to non-zero debugging information about stack unwinding |
289 | will be printed. */ | |
290 | ||
291 | static unsigned int riscv_debug_unwinder = 0; | |
292 | ||
0b0eff8b AB |
293 | /* Read the MISA register from the target. There are a couple of locations |
294 | that the register might be found, these are all tried. If the MISA | |
295 | register can't be found at all then the default value of 0 is returned, | |
296 | this is inline with the RISC-V specification. */ | |
dbbb1059 AB |
297 | |
298 | static uint32_t | |
0b0eff8b | 299 | riscv_read_misa_reg () |
dbbb1059 | 300 | { |
0b3f9efc | 301 | uint32_t value = 0; |
dbbb1059 | 302 | |
0b3f9efc | 303 | if (target_has_registers) |
dbbb1059 | 304 | { |
0b0eff8b AB |
305 | /* Old cores might have MISA located at a different offset. */ |
306 | static int misa_regs[] = | |
307 | { RISCV_CSR_MISA_REGNUM, RISCV_CSR_LEGACY_MISA_REGNUM }; | |
308 | ||
dbbb1059 AB |
309 | struct frame_info *frame = get_current_frame (); |
310 | ||
0b0eff8b | 311 | for (int i = 0; i < ARRAY_SIZE (misa_regs); ++i) |
dbbb1059 | 312 | { |
0b0eff8b AB |
313 | bool success = false; |
314 | ||
315 | TRY | |
316 | { | |
317 | value = get_frame_register_unsigned (frame, misa_regs[i]); | |
318 | success = true; | |
319 | } | |
320 | CATCH (ex, RETURN_MASK_ERROR) | |
321 | { | |
322 | /* Ignore errors, it is acceptable for a target to not | |
323 | provide a MISA register, in which case the default value | |
324 | of 0 should be used. */ | |
325 | } | |
326 | END_CATCH | |
327 | ||
328 | if (success) | |
329 | break; | |
dbbb1059 | 330 | } |
dbbb1059 AB |
331 | } |
332 | ||
0b3f9efc | 333 | return value; |
dbbb1059 AB |
334 | } |
335 | ||
336 | /* Return true if FEATURE is available for the architecture GDBARCH. The | |
337 | FEATURE should be one of the single character feature codes described in | |
338 | the RiscV ISA manual, these are between 'A' and 'Z'. */ | |
339 | ||
340 | static bool | |
341 | riscv_has_feature (struct gdbarch *gdbarch, char feature) | |
342 | { | |
dbbb1059 AB |
343 | gdb_assert (feature >= 'A' && feature <= 'Z'); |
344 | ||
0b0eff8b AB |
345 | uint32_t misa = riscv_read_misa_reg (); |
346 | if (misa == 0) | |
dbbb1059 AB |
347 | misa = gdbarch_tdep (gdbarch)->core_features; |
348 | ||
349 | return (misa & (1 << (feature - 'A'))) != 0; | |
350 | } | |
351 | ||
8a613826 | 352 | /* See riscv-tdep.h. */ |
dbbb1059 | 353 | |
411baa47 | 354 | int |
dbbb1059 AB |
355 | riscv_isa_xlen (struct gdbarch *gdbarch) |
356 | { | |
357 | switch (gdbarch_tdep (gdbarch)->abi.fields.base_len) | |
358 | { | |
359 | default: | |
360 | warning (_("unknown xlen size, assuming 4 bytes")); | |
565e0eda | 361 | /* Fall through. */ |
dbbb1059 AB |
362 | case 1: |
363 | return 4; | |
364 | case 2: | |
365 | return 8; | |
366 | case 3: | |
367 | return 16; | |
368 | } | |
369 | } | |
370 | ||
8a613826 | 371 | /* See riscv-tdep.h. */ |
dbbb1059 | 372 | |
8a613826 | 373 | int |
dbbb1059 AB |
374 | riscv_isa_flen (struct gdbarch *gdbarch) |
375 | { | |
376 | if (riscv_has_feature (gdbarch, 'Q')) | |
377 | return 16; | |
378 | else if (riscv_has_feature (gdbarch, 'D')) | |
379 | return 8; | |
380 | else if (riscv_has_feature (gdbarch, 'F')) | |
381 | return 4; | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
386 | /* Return true if the target for GDBARCH has floating point hardware. */ | |
387 | ||
388 | static bool | |
389 | riscv_has_fp_regs (struct gdbarch *gdbarch) | |
390 | { | |
391 | return (riscv_isa_flen (gdbarch) > 0); | |
392 | } | |
393 | ||
394 | /* Return true if GDBARCH is using any of the floating point hardware ABIs. */ | |
395 | ||
396 | static bool | |
397 | riscv_has_fp_abi (struct gdbarch *gdbarch) | |
398 | { | |
399 | return (gdbarch_tdep (gdbarch)->abi.fields.float_abi != 0); | |
400 | } | |
401 | ||
8c49aa89 AB |
402 | /* Return true if REGNO is a floating pointer register. */ |
403 | ||
404 | static bool | |
405 | riscv_is_fp_regno_p (int regno) | |
406 | { | |
407 | return (regno >= RISCV_FIRST_FP_REGNUM | |
408 | && regno <= RISCV_LAST_FP_REGNUM); | |
409 | } | |
410 | ||
dbbb1059 AB |
411 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
412 | ||
413 | static int | |
414 | riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
415 | { | |
416 | if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO) | |
417 | { | |
3ba2ee38 | 418 | bool unaligned_p = false; |
f37bc8b1 JB |
419 | gdb_byte buf[1]; |
420 | ||
3ba2ee38 JW |
421 | /* Some targets don't support unaligned reads. The address can only |
422 | be unaligned if the C extension is supported. So it is safe to | |
423 | use a compressed breakpoint in this case. */ | |
424 | if (*pcptr & 0x2) | |
425 | unaligned_p = true; | |
426 | else | |
427 | { | |
428 | /* Read the opcode byte to determine the instruction length. */ | |
429 | read_code (*pcptr, buf, 1); | |
430 | } | |
f37bc8b1 JB |
431 | |
432 | if (riscv_debug_breakpoints) | |
3ba2ee38 JW |
433 | { |
434 | const char *bp = (unaligned_p || riscv_insn_length (buf[0]) == 2 | |
435 | ? "C.EBREAK" : "EBREAK"); | |
436 | ||
437 | fprintf_unfiltered (gdb_stdlog, "Using %s for breakpoint at %s ", | |
438 | bp, paddress (gdbarch, *pcptr)); | |
439 | if (unaligned_p) | |
440 | fprintf_unfiltered (gdb_stdlog, "(unaligned address)\n"); | |
441 | else | |
442 | fprintf_unfiltered (gdb_stdlog, "(instruction length %d)\n", | |
443 | riscv_insn_length (buf[0])); | |
444 | } | |
445 | if (unaligned_p || riscv_insn_length (buf[0]) == 2) | |
dbbb1059 AB |
446 | return 2; |
447 | else | |
448 | return 4; | |
449 | } | |
450 | else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE) | |
451 | return 2; | |
452 | else | |
453 | return 4; | |
454 | } | |
455 | ||
456 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ | |
457 | ||
458 | static const gdb_byte * | |
459 | riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
460 | { | |
461 | static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, }; | |
462 | static const gdb_byte c_ebreak[] = { 0x02, 0x90 }; | |
463 | ||
464 | *size = kind; | |
465 | switch (kind) | |
466 | { | |
467 | case 2: | |
468 | return c_ebreak; | |
469 | case 4: | |
470 | return ebreak; | |
471 | default: | |
89a3b63e | 472 | gdb_assert_not_reached (_("unhandled breakpoint kind")); |
dbbb1059 AB |
473 | } |
474 | } | |
475 | ||
476 | /* Callback function for user_reg_add. */ | |
477 | ||
478 | static struct value * | |
479 | value_of_riscv_user_reg (struct frame_info *frame, const void *baton) | |
480 | { | |
481 | const int *reg_p = (const int *) baton; | |
482 | return value_of_register (*reg_p, frame); | |
483 | } | |
484 | ||
485 | /* Implement the register_name gdbarch method. */ | |
486 | ||
487 | static const char * | |
488 | riscv_register_name (struct gdbarch *gdbarch, int regnum) | |
489 | { | |
dbbb1059 | 490 | /* Prefer to use the alias. */ |
0dbfcfff | 491 | if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_FP_REGNUM) |
dbbb1059 | 492 | { |
0dbfcfff AB |
493 | gdb_assert (regnum < ARRAY_SIZE (riscv_gdb_reg_names)); |
494 | return riscv_gdb_reg_names[regnum]; | |
dbbb1059 AB |
495 | } |
496 | ||
0dbfcfff AB |
497 | /* Check that there's no gap between the set of registers handled above, |
498 | and the set of registers handled next. */ | |
499 | gdb_assert ((RISCV_LAST_FP_REGNUM + 1) == RISCV_FIRST_CSR_REGNUM); | |
dbbb1059 AB |
500 | |
501 | if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM) | |
502 | { | |
420ecd9c AB |
503 | #define DECLARE_CSR(NAME,VALUE) \ |
504 | case RISCV_ ## VALUE ## _REGNUM: return # NAME; | |
dbbb1059 | 505 | |
420ecd9c AB |
506 | switch (regnum) |
507 | { | |
508 | #include "opcode/riscv-opc.h" | |
509 | default: | |
510 | { | |
511 | static char buf[20]; | |
512 | ||
513 | xsnprintf (buf, sizeof (buf), "csr%d", | |
514 | regnum - RISCV_FIRST_CSR_REGNUM); | |
515 | return buf; | |
516 | } | |
517 | } | |
518 | #undef DECLARE_CSR | |
dbbb1059 AB |
519 | } |
520 | ||
521 | if (regnum == RISCV_PRIV_REGNUM) | |
522 | return "priv"; | |
523 | ||
524 | return NULL; | |
525 | } | |
526 | ||
270b9329 JW |
527 | /* Construct a type for 64-bit FP registers. */ |
528 | ||
529 | static struct type * | |
530 | riscv_fpreg_d_type (struct gdbarch *gdbarch) | |
531 | { | |
532 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
533 | ||
534 | if (tdep->riscv_fpreg_d_type == nullptr) | |
535 | { | |
536 | const struct builtin_type *bt = builtin_type (gdbarch); | |
537 | ||
538 | /* The type we're building is this: */ | |
539 | #if 0 | |
540 | union __gdb_builtin_type_fpreg_d | |
541 | { | |
542 | float f; | |
543 | double d; | |
544 | }; | |
545 | #endif | |
546 | ||
547 | struct type *t; | |
548 | ||
549 | t = arch_composite_type (gdbarch, | |
550 | "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION); | |
551 | append_composite_type_field (t, "float", bt->builtin_float); | |
552 | append_composite_type_field (t, "double", bt->builtin_double); | |
553 | TYPE_VECTOR (t) = 1; | |
554 | TYPE_NAME (t) = "builtin_type_fpreg_d"; | |
555 | tdep->riscv_fpreg_d_type = t; | |
556 | } | |
557 | ||
558 | return tdep->riscv_fpreg_d_type; | |
559 | } | |
560 | ||
561 | /* Construct a type for 128-bit FP registers. */ | |
562 | ||
563 | static struct type * | |
564 | riscv_fpreg_q_type (struct gdbarch *gdbarch) | |
565 | { | |
566 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
567 | ||
568 | if (tdep->riscv_fpreg_q_type == nullptr) | |
569 | { | |
570 | const struct builtin_type *bt = builtin_type (gdbarch); | |
571 | ||
572 | /* The type we're building is this: */ | |
573 | #if 0 | |
574 | union __gdb_builtin_type_fpreg_d | |
575 | { | |
576 | float f; | |
577 | double d; | |
578 | long double ld; | |
579 | }; | |
580 | #endif | |
581 | ||
582 | struct type *t; | |
583 | ||
584 | t = arch_composite_type (gdbarch, | |
585 | "__gdb_builtin_type_fpreg_q", TYPE_CODE_UNION); | |
586 | append_composite_type_field (t, "float", bt->builtin_float); | |
587 | append_composite_type_field (t, "double", bt->builtin_double); | |
588 | append_composite_type_field (t, "long double", bt->builtin_long_double); | |
589 | TYPE_VECTOR (t) = 1; | |
590 | TYPE_NAME (t) = "builtin_type_fpreg_q"; | |
591 | tdep->riscv_fpreg_q_type = t; | |
592 | } | |
593 | ||
594 | return tdep->riscv_fpreg_q_type; | |
595 | } | |
596 | ||
dbbb1059 AB |
597 | /* Implement the register_type gdbarch method. */ |
598 | ||
599 | static struct type * | |
600 | riscv_register_type (struct gdbarch *gdbarch, int regnum) | |
601 | { | |
602 | int regsize; | |
603 | ||
604 | if (regnum < RISCV_FIRST_FP_REGNUM) | |
605 | { | |
606 | if (regnum == gdbarch_pc_regnum (gdbarch) | |
607 | || regnum == RISCV_RA_REGNUM) | |
608 | return builtin_type (gdbarch)->builtin_func_ptr; | |
609 | ||
610 | if (regnum == RISCV_FP_REGNUM | |
611 | || regnum == RISCV_SP_REGNUM | |
612 | || regnum == RISCV_GP_REGNUM | |
613 | || regnum == RISCV_TP_REGNUM) | |
614 | return builtin_type (gdbarch)->builtin_data_ptr; | |
615 | ||
616 | /* Remaining GPRs vary in size based on the current ISA. */ | |
617 | regsize = riscv_isa_xlen (gdbarch); | |
618 | switch (regsize) | |
619 | { | |
620 | case 4: | |
621 | return builtin_type (gdbarch)->builtin_uint32; | |
622 | case 8: | |
623 | return builtin_type (gdbarch)->builtin_uint64; | |
624 | case 16: | |
625 | return builtin_type (gdbarch)->builtin_uint128; | |
626 | default: | |
627 | internal_error (__FILE__, __LINE__, | |
628 | _("unknown isa regsize %i"), regsize); | |
629 | } | |
630 | } | |
631 | else if (regnum <= RISCV_LAST_FP_REGNUM) | |
632 | { | |
633 | regsize = riscv_isa_xlen (gdbarch); | |
634 | switch (regsize) | |
635 | { | |
636 | case 4: | |
637 | return builtin_type (gdbarch)->builtin_float; | |
638 | case 8: | |
270b9329 | 639 | return riscv_fpreg_d_type (gdbarch); |
dbbb1059 | 640 | case 16: |
270b9329 | 641 | return riscv_fpreg_q_type (gdbarch); |
dbbb1059 AB |
642 | default: |
643 | internal_error (__FILE__, __LINE__, | |
644 | _("unknown isa regsize %i"), regsize); | |
645 | } | |
646 | } | |
647 | else if (regnum == RISCV_PRIV_REGNUM) | |
648 | return builtin_type (gdbarch)->builtin_int8; | |
649 | else | |
650 | { | |
651 | if (regnum == RISCV_CSR_FFLAGS_REGNUM | |
652 | || regnum == RISCV_CSR_FRM_REGNUM | |
653 | || regnum == RISCV_CSR_FCSR_REGNUM) | |
654 | return builtin_type (gdbarch)->builtin_int32; | |
655 | ||
656 | regsize = riscv_isa_xlen (gdbarch); | |
657 | switch (regsize) | |
658 | { | |
659 | case 4: | |
660 | return builtin_type (gdbarch)->builtin_int32; | |
661 | case 8: | |
662 | return builtin_type (gdbarch)->builtin_int64; | |
663 | case 16: | |
664 | return builtin_type (gdbarch)->builtin_int128; | |
665 | default: | |
666 | internal_error (__FILE__, __LINE__, | |
667 | _("unknown isa regsize %i"), regsize); | |
668 | } | |
669 | } | |
670 | } | |
671 | ||
672 | /* Helper for riscv_print_registers_info, prints info for a single register | |
673 | REGNUM. */ | |
674 | ||
675 | static void | |
676 | riscv_print_one_register_info (struct gdbarch *gdbarch, | |
677 | struct ui_file *file, | |
678 | struct frame_info *frame, | |
679 | int regnum) | |
680 | { | |
681 | const char *name = gdbarch_register_name (gdbarch, regnum); | |
682 | struct value *val = value_of_register (regnum, frame); | |
683 | struct type *regtype = value_type (val); | |
684 | int print_raw_format; | |
685 | enum tab_stops { value_column_1 = 15 }; | |
686 | ||
687 | fputs_filtered (name, file); | |
688 | print_spaces_filtered (value_column_1 - strlen (name), file); | |
689 | ||
690 | print_raw_format = (value_entirely_available (val) | |
691 | && !value_optimized_out (val)); | |
692 | ||
270b9329 JW |
693 | if (TYPE_CODE (regtype) == TYPE_CODE_FLT |
694 | || (TYPE_CODE (regtype) == TYPE_CODE_UNION | |
695 | && TYPE_NFIELDS (regtype) == 2 | |
696 | && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT | |
697 | && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT) | |
698 | || (TYPE_CODE (regtype) == TYPE_CODE_UNION | |
699 | && TYPE_NFIELDS (regtype) == 3 | |
700 | && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT | |
701 | && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT | |
702 | && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 2)) == TYPE_CODE_FLT)) | |
dbbb1059 AB |
703 | { |
704 | struct value_print_options opts; | |
705 | const gdb_byte *valaddr = value_contents_for_printing (val); | |
706 | enum bfd_endian byte_order = gdbarch_byte_order (get_type_arch (regtype)); | |
707 | ||
708 | get_user_print_options (&opts); | |
709 | opts.deref_ref = 1; | |
710 | ||
711 | val_print (regtype, | |
712 | value_embedded_offset (val), 0, | |
713 | file, 0, val, &opts, current_language); | |
714 | ||
715 | if (print_raw_format) | |
716 | { | |
717 | fprintf_filtered (file, "\t(raw "); | |
718 | print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order, | |
719 | true); | |
720 | fprintf_filtered (file, ")"); | |
721 | } | |
722 | } | |
723 | else | |
724 | { | |
725 | struct value_print_options opts; | |
726 | ||
727 | /* Print the register in hex. */ | |
728 | get_formatted_print_options (&opts, 'x'); | |
729 | opts.deref_ref = 1; | |
730 | val_print (regtype, | |
731 | value_embedded_offset (val), 0, | |
732 | file, 0, val, &opts, current_language); | |
733 | ||
734 | if (print_raw_format) | |
735 | { | |
736 | if (regnum == RISCV_CSR_MSTATUS_REGNUM) | |
737 | { | |
738 | LONGEST d; | |
739 | int size = register_size (gdbarch, regnum); | |
740 | unsigned xlen; | |
741 | ||
742 | d = value_as_long (val); | |
743 | xlen = size * 4; | |
744 | fprintf_filtered (file, | |
745 | "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X " | |
746 | "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X " | |
747 | "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X", | |
748 | (int) ((d >> (xlen - 1)) & 0x1), | |
749 | (int) ((d >> 24) & 0x1f), | |
750 | (int) ((d >> 19) & 0x1), | |
751 | (int) ((d >> 18) & 0x1), | |
752 | (int) ((d >> 17) & 0x1), | |
753 | (int) ((d >> 15) & 0x3), | |
754 | (int) ((d >> 13) & 0x3), | |
755 | (int) ((d >> 11) & 0x3), | |
756 | (int) ((d >> 9) & 0x3), | |
757 | (int) ((d >> 8) & 0x1), | |
758 | (int) ((d >> 7) & 0x1), | |
759 | (int) ((d >> 6) & 0x1), | |
760 | (int) ((d >> 5) & 0x1), | |
761 | (int) ((d >> 4) & 0x1), | |
762 | (int) ((d >> 3) & 0x1), | |
763 | (int) ((d >> 2) & 0x1), | |
764 | (int) ((d >> 1) & 0x1), | |
765 | (int) ((d >> 0) & 0x1)); | |
766 | } | |
767 | else if (regnum == RISCV_CSR_MISA_REGNUM) | |
768 | { | |
769 | int base; | |
770 | unsigned xlen, i; | |
771 | LONGEST d; | |
772 | ||
773 | d = value_as_long (val); | |
774 | base = d >> 30; | |
775 | xlen = 16; | |
776 | ||
777 | for (; base > 0; base--) | |
778 | xlen *= 2; | |
779 | fprintf_filtered (file, "\tRV%d", xlen); | |
780 | ||
781 | for (i = 0; i < 26; i++) | |
782 | { | |
783 | if (d & (1 << i)) | |
784 | fprintf_filtered (file, "%c", 'A' + i); | |
785 | } | |
786 | } | |
787 | else if (regnum == RISCV_CSR_FCSR_REGNUM | |
788 | || regnum == RISCV_CSR_FFLAGS_REGNUM | |
789 | || regnum == RISCV_CSR_FRM_REGNUM) | |
790 | { | |
791 | LONGEST d; | |
792 | ||
793 | d = value_as_long (val); | |
794 | ||
795 | fprintf_filtered (file, "\t"); | |
796 | if (regnum != RISCV_CSR_FRM_REGNUM) | |
797 | fprintf_filtered (file, | |
798 | "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d", | |
799 | (int) ((d >> 5) & 0x7), | |
800 | (int) ((d >> 4) & 0x1), | |
801 | (int) ((d >> 3) & 0x1), | |
802 | (int) ((d >> 2) & 0x1), | |
803 | (int) ((d >> 1) & 0x1), | |
804 | (int) ((d >> 0) & 0x1)); | |
805 | ||
806 | if (regnum != RISCV_CSR_FFLAGS_REGNUM) | |
807 | { | |
808 | static const char * const sfrm[] = | |
809 | { | |
810 | "RNE (round to nearest; ties to even)", | |
811 | "RTZ (Round towards zero)", | |
812 | "RDN (Round down towards -INF)", | |
813 | "RUP (Round up towards +INF)", | |
814 | "RMM (Round to nearest; ties to max magnitude)", | |
815 | "INVALID[5]", | |
816 | "INVALID[6]", | |
817 | "dynamic rounding mode", | |
818 | }; | |
819 | int frm = ((regnum == RISCV_CSR_FCSR_REGNUM) | |
820 | ? (d >> 5) : d) & 0x3; | |
821 | ||
822 | fprintf_filtered (file, "%sFRM:%i [%s]", | |
823 | (regnum == RISCV_CSR_FCSR_REGNUM | |
824 | ? " " : ""), | |
825 | frm, sfrm[frm]); | |
826 | } | |
827 | } | |
828 | else if (regnum == RISCV_PRIV_REGNUM) | |
829 | { | |
830 | LONGEST d; | |
831 | uint8_t priv; | |
832 | ||
833 | d = value_as_long (val); | |
834 | priv = d & 0xff; | |
835 | ||
836 | if (priv < 4) | |
837 | { | |
838 | static const char * const sprv[] = | |
839 | { | |
840 | "User/Application", | |
841 | "Supervisor", | |
842 | "Hypervisor", | |
843 | "Machine" | |
844 | }; | |
845 | fprintf_filtered (file, "\tprv:%d [%s]", | |
846 | priv, sprv[priv]); | |
847 | } | |
848 | else | |
849 | fprintf_filtered (file, "\tprv:%d [INVALID]", priv); | |
850 | } | |
851 | else | |
852 | { | |
853 | /* If not a vector register, print it also according to its | |
854 | natural format. */ | |
855 | if (TYPE_VECTOR (regtype) == 0) | |
856 | { | |
857 | get_user_print_options (&opts); | |
858 | opts.deref_ref = 1; | |
859 | fprintf_filtered (file, "\t"); | |
860 | val_print (regtype, | |
861 | value_embedded_offset (val), 0, | |
862 | file, 0, val, &opts, current_language); | |
863 | } | |
864 | } | |
865 | } | |
866 | } | |
867 | fprintf_filtered (file, "\n"); | |
868 | } | |
869 | ||
0dbfcfff AB |
870 | /* Return true if REGNUM is a valid CSR register. The CSR register space |
871 | is sparsely populated, so not every number is a named CSR. */ | |
872 | ||
873 | static bool | |
874 | riscv_is_regnum_a_named_csr (int regnum) | |
875 | { | |
876 | gdb_assert (regnum >= RISCV_FIRST_CSR_REGNUM | |
877 | && regnum <= RISCV_LAST_CSR_REGNUM); | |
878 | ||
879 | switch (regnum) | |
880 | { | |
881 | #define DECLARE_CSR(name, num) case RISCV_ ## num ## _REGNUM: | |
882 | #include "opcode/riscv-opc.h" | |
883 | #undef DECLARE_CSR | |
884 | return true; | |
885 | ||
886 | default: | |
887 | return false; | |
888 | } | |
889 | } | |
890 | ||
dbbb1059 AB |
891 | /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member |
892 | of REGGROUP? */ | |
893 | ||
894 | static int | |
895 | riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
896 | struct reggroup *reggroup) | |
897 | { | |
dbbb1059 AB |
898 | /* Used by 'info registers' and 'info registers <groupname>'. */ |
899 | ||
900 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
901 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
902 | return 0; | |
903 | ||
904 | if (reggroup == all_reggroup) | |
905 | { | |
906 | if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM) | |
907 | return 1; | |
0dbfcfff AB |
908 | if (riscv_is_regnum_a_named_csr (regnum)) |
909 | return 1; | |
dbbb1059 AB |
910 | return 0; |
911 | } | |
912 | else if (reggroup == float_reggroup) | |
8c49aa89 AB |
913 | return (riscv_is_fp_regno_p (regnum) |
914 | || regnum == RISCV_CSR_FCSR_REGNUM | |
915 | || regnum == RISCV_CSR_FFLAGS_REGNUM | |
916 | || regnum == RISCV_CSR_FRM_REGNUM); | |
dbbb1059 AB |
917 | else if (reggroup == general_reggroup) |
918 | return regnum < RISCV_FIRST_FP_REGNUM; | |
919 | else if (reggroup == restore_reggroup || reggroup == save_reggroup) | |
920 | { | |
921 | if (riscv_has_fp_regs (gdbarch)) | |
922 | return regnum <= RISCV_LAST_FP_REGNUM; | |
923 | else | |
924 | return regnum < RISCV_FIRST_FP_REGNUM; | |
925 | } | |
926 | else if (reggroup == system_reggroup) | |
927 | { | |
928 | if (regnum == RISCV_PRIV_REGNUM) | |
929 | return 1; | |
930 | if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM) | |
931 | return 0; | |
0dbfcfff AB |
932 | if (riscv_is_regnum_a_named_csr (regnum)) |
933 | return 1; | |
dbbb1059 AB |
934 | return 0; |
935 | } | |
936 | else if (reggroup == vector_reggroup) | |
937 | return 0; | |
938 | else | |
939 | return 0; | |
940 | } | |
941 | ||
942 | /* Implement the print_registers_info gdbarch method. This is used by | |
943 | 'info registers' and 'info all-registers'. */ | |
944 | ||
945 | static void | |
946 | riscv_print_registers_info (struct gdbarch *gdbarch, | |
947 | struct ui_file *file, | |
948 | struct frame_info *frame, | |
949 | int regnum, int print_all) | |
950 | { | |
951 | if (regnum != -1) | |
952 | { | |
953 | /* Print one specified register. */ | |
954 | gdb_assert (regnum <= RISCV_LAST_REGNUM); | |
955 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
956 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
957 | error (_("Not a valid register for the current processor type")); | |
958 | riscv_print_one_register_info (gdbarch, file, frame, regnum); | |
959 | } | |
960 | else | |
961 | { | |
962 | struct reggroup *reggroup; | |
963 | ||
964 | if (print_all) | |
965 | reggroup = all_reggroup; | |
966 | else | |
967 | reggroup = general_reggroup; | |
968 | ||
969 | for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum) | |
970 | { | |
971 | /* Zero never changes, so might as well hide by default. */ | |
972 | if (regnum == RISCV_ZERO_REGNUM && !print_all) | |
973 | continue; | |
974 | ||
975 | /* Registers with no name are not valid on this ISA. */ | |
976 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
977 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
978 | continue; | |
979 | ||
980 | /* Is the register in the group we're interested in? */ | |
981 | if (!riscv_register_reggroup_p (gdbarch, regnum, reggroup)) | |
982 | continue; | |
983 | ||
984 | riscv_print_one_register_info (gdbarch, file, frame, regnum); | |
985 | } | |
986 | } | |
987 | } | |
988 | ||
989 | /* Class that handles one decoded RiscV instruction. */ | |
990 | ||
991 | class riscv_insn | |
992 | { | |
993 | public: | |
994 | ||
995 | /* Enum of all the opcodes that GDB cares about during the prologue scan. */ | |
996 | enum opcode | |
997 | { | |
998 | /* Unknown value is used at initialisation time. */ | |
999 | UNKNOWN = 0, | |
1000 | ||
1001 | /* These instructions are all the ones we are interested in during the | |
1002 | prologue scan. */ | |
1003 | ADD, | |
1004 | ADDI, | |
1005 | ADDIW, | |
1006 | ADDW, | |
1007 | AUIPC, | |
1008 | LUI, | |
1009 | SD, | |
1010 | SW, | |
5c720ed8 JW |
1011 | /* These are needed for software breakopint support. */ |
1012 | JAL, | |
1013 | JALR, | |
1014 | BEQ, | |
1015 | BNE, | |
1016 | BLT, | |
1017 | BGE, | |
1018 | BLTU, | |
1019 | BGEU, | |
1020 | /* These are needed for stepping over atomic sequences. */ | |
1021 | LR, | |
1022 | SC, | |
dbbb1059 AB |
1023 | |
1024 | /* Other instructions are not interesting during the prologue scan, and | |
1025 | are ignored. */ | |
1026 | OTHER | |
1027 | }; | |
1028 | ||
1029 | riscv_insn () | |
1030 | : m_length (0), | |
1031 | m_opcode (OTHER), | |
1032 | m_rd (0), | |
1033 | m_rs1 (0), | |
1034 | m_rs2 (0) | |
1035 | { | |
1036 | /* Nothing. */ | |
1037 | } | |
1038 | ||
1039 | void decode (struct gdbarch *gdbarch, CORE_ADDR pc); | |
1040 | ||
1041 | /* Get the length of the instruction in bytes. */ | |
1042 | int length () const | |
1043 | { return m_length; } | |
1044 | ||
1045 | /* Get the opcode for this instruction. */ | |
1046 | enum opcode opcode () const | |
1047 | { return m_opcode; } | |
1048 | ||
1049 | /* Get destination register field for this instruction. This is only | |
1050 | valid if the OPCODE implies there is such a field for this | |
1051 | instruction. */ | |
1052 | int rd () const | |
1053 | { return m_rd; } | |
1054 | ||
1055 | /* Get the RS1 register field for this instruction. This is only valid | |
1056 | if the OPCODE implies there is such a field for this instruction. */ | |
1057 | int rs1 () const | |
1058 | { return m_rs1; } | |
1059 | ||
1060 | /* Get the RS2 register field for this instruction. This is only valid | |
1061 | if the OPCODE implies there is such a field for this instruction. */ | |
1062 | int rs2 () const | |
1063 | { return m_rs2; } | |
1064 | ||
1065 | /* Get the immediate for this instruction in signed form. This is only | |
1066 | valid if the OPCODE implies there is such a field for this | |
1067 | instruction. */ | |
1068 | int imm_signed () const | |
1069 | { return m_imm.s; } | |
1070 | ||
1071 | private: | |
1072 | ||
1073 | /* Extract 5 bit register field at OFFSET from instruction OPCODE. */ | |
1074 | int decode_register_index (unsigned long opcode, int offset) | |
1075 | { | |
1076 | return (opcode >> offset) & 0x1F; | |
1077 | } | |
1078 | ||
5c720ed8 JW |
1079 | /* Extract 5 bit register field at OFFSET from instruction OPCODE. */ |
1080 | int decode_register_index_short (unsigned long opcode, int offset) | |
1081 | { | |
1082 | return ((opcode >> offset) & 0x7) + 8; | |
1083 | } | |
1084 | ||
dbbb1059 AB |
1085 | /* Helper for DECODE, decode 32-bit R-type instruction. */ |
1086 | void decode_r_type_insn (enum opcode opcode, ULONGEST ival) | |
1087 | { | |
1088 | m_opcode = opcode; | |
1089 | m_rd = decode_register_index (ival, OP_SH_RD); | |
1090 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
1091 | m_rs2 = decode_register_index (ival, OP_SH_RS2); | |
1092 | } | |
1093 | ||
1094 | /* Helper for DECODE, decode 16-bit compressed R-type instruction. */ | |
1095 | void decode_cr_type_insn (enum opcode opcode, ULONGEST ival) | |
1096 | { | |
1097 | m_opcode = opcode; | |
1098 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S); | |
1099 | m_rs2 = decode_register_index (ival, OP_SH_CRS2); | |
1100 | } | |
1101 | ||
1102 | /* Helper for DECODE, decode 32-bit I-type instruction. */ | |
1103 | void decode_i_type_insn (enum opcode opcode, ULONGEST ival) | |
1104 | { | |
1105 | m_opcode = opcode; | |
1106 | m_rd = decode_register_index (ival, OP_SH_RD); | |
1107 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
1108 | m_imm.s = EXTRACT_ITYPE_IMM (ival); | |
1109 | } | |
1110 | ||
1111 | /* Helper for DECODE, decode 16-bit compressed I-type instruction. */ | |
1112 | void decode_ci_type_insn (enum opcode opcode, ULONGEST ival) | |
1113 | { | |
1114 | m_opcode = opcode; | |
1115 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S); | |
1116 | m_imm.s = EXTRACT_RVC_IMM (ival); | |
1117 | } | |
1118 | ||
1119 | /* Helper for DECODE, decode 32-bit S-type instruction. */ | |
1120 | void decode_s_type_insn (enum opcode opcode, ULONGEST ival) | |
1121 | { | |
1122 | m_opcode = opcode; | |
1123 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
1124 | m_rs2 = decode_register_index (ival, OP_SH_RS2); | |
1125 | m_imm.s = EXTRACT_STYPE_IMM (ival); | |
1126 | } | |
1127 | ||
ff3a05b3 AB |
1128 | /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate |
1129 | encoding is different for each CS format instruction, so extracting | |
1130 | the immediate is left up to the caller, who should pass the extracted | |
1131 | immediate value through in IMM. */ | |
1132 | void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm) | |
1133 | { | |
1134 | m_opcode = opcode; | |
1135 | m_imm.s = imm; | |
1136 | m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S); | |
1137 | m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S); | |
1138 | } | |
1139 | ||
1140 | /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate | |
1141 | encoding is different for each CSS format instruction, so extracting | |
1142 | the immediate is left up to the caller, who should pass the extracted | |
1143 | immediate value through in IMM. */ | |
1144 | void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm) | |
1145 | { | |
1146 | m_opcode = opcode; | |
1147 | m_imm.s = imm; | |
1148 | m_rs1 = RISCV_SP_REGNUM; | |
1149 | /* Not a compressed register number in this case. */ | |
1150 | m_rs2 = decode_register_index (ival, OP_SH_CRS2); | |
1151 | } | |
1152 | ||
dbbb1059 AB |
1153 | /* Helper for DECODE, decode 32-bit U-type instruction. */ |
1154 | void decode_u_type_insn (enum opcode opcode, ULONGEST ival) | |
1155 | { | |
1156 | m_opcode = opcode; | |
1157 | m_rd = decode_register_index (ival, OP_SH_RD); | |
1158 | m_imm.s = EXTRACT_UTYPE_IMM (ival); | |
1159 | } | |
1160 | ||
5c720ed8 JW |
1161 | /* Helper for DECODE, decode 32-bit J-type instruction. */ |
1162 | void decode_j_type_insn (enum opcode opcode, ULONGEST ival) | |
1163 | { | |
1164 | m_opcode = opcode; | |
1165 | m_rd = decode_register_index (ival, OP_SH_RD); | |
1166 | m_imm.s = EXTRACT_UJTYPE_IMM (ival); | |
1167 | } | |
1168 | ||
1169 | /* Helper for DECODE, decode 32-bit J-type instruction. */ | |
1170 | void decode_cj_type_insn (enum opcode opcode, ULONGEST ival) | |
1171 | { | |
1172 | m_opcode = opcode; | |
1173 | m_imm.s = EXTRACT_RVC_J_IMM (ival); | |
1174 | } | |
1175 | ||
1176 | void decode_b_type_insn (enum opcode opcode, ULONGEST ival) | |
1177 | { | |
1178 | m_opcode = opcode; | |
1179 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
1180 | m_rs2 = decode_register_index (ival, OP_SH_RS2); | |
1181 | m_imm.s = EXTRACT_SBTYPE_IMM (ival); | |
1182 | } | |
1183 | ||
1184 | void decode_cb_type_insn (enum opcode opcode, ULONGEST ival) | |
1185 | { | |
1186 | m_opcode = opcode; | |
1187 | m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S); | |
1188 | m_imm.s = EXTRACT_RVC_B_IMM (ival); | |
1189 | } | |
1190 | ||
dbbb1059 AB |
1191 | /* Fetch instruction from target memory at ADDR, return the content of |
1192 | the instruction, and update LEN with the instruction length. */ | |
1193 | static ULONGEST fetch_instruction (struct gdbarch *gdbarch, | |
1194 | CORE_ADDR addr, int *len); | |
1195 | ||
1196 | /* The length of the instruction in bytes. Should be 2 or 4. */ | |
1197 | int m_length; | |
1198 | ||
1199 | /* The instruction opcode. */ | |
1200 | enum opcode m_opcode; | |
1201 | ||
1202 | /* The three possible registers an instruction might reference. Not | |
1203 | every instruction fills in all of these registers. Which fields are | |
1204 | valid depends on the opcode. The naming of these fields matches the | |
1205 | naming in the riscv isa manual. */ | |
1206 | int m_rd; | |
1207 | int m_rs1; | |
1208 | int m_rs2; | |
1209 | ||
1210 | /* Possible instruction immediate. This is only valid if the instruction | |
1211 | format contains an immediate, not all instruction, whether this is | |
1212 | valid depends on the opcode. Despite only having one format for now | |
1213 | the immediate is packed into a union, later instructions might require | |
1214 | an unsigned formatted immediate, having the union in place now will | |
1215 | reduce the need for code churn later. */ | |
1216 | union riscv_insn_immediate | |
1217 | { | |
1218 | riscv_insn_immediate () | |
1219 | : s (0) | |
1220 | { | |
1221 | /* Nothing. */ | |
1222 | } | |
1223 | ||
1224 | int s; | |
1225 | } m_imm; | |
1226 | }; | |
1227 | ||
1228 | /* Fetch instruction from target memory at ADDR, return the content of the | |
1229 | instruction, and update LEN with the instruction length. */ | |
1230 | ||
1231 | ULONGEST | |
1232 | riscv_insn::fetch_instruction (struct gdbarch *gdbarch, | |
1233 | CORE_ADDR addr, int *len) | |
1234 | { | |
1235 | enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch); | |
1236 | gdb_byte buf[8]; | |
1237 | int instlen, status; | |
1238 | ||
1239 | /* All insns are at least 16 bits. */ | |
1240 | status = target_read_memory (addr, buf, 2); | |
1241 | if (status) | |
1242 | memory_error (TARGET_XFER_E_IO, addr); | |
1243 | ||
1244 | /* If we need more, grab it now. */ | |
1245 | instlen = riscv_insn_length (buf[0]); | |
89a3b63e | 1246 | gdb_assert (instlen <= sizeof (buf)); |
dbbb1059 | 1247 | *len = instlen; |
89a3b63e AB |
1248 | |
1249 | if (instlen > 2) | |
dbbb1059 AB |
1250 | { |
1251 | status = target_read_memory (addr + 2, buf + 2, instlen - 2); | |
1252 | if (status) | |
1253 | memory_error (TARGET_XFER_E_IO, addr + 2); | |
1254 | } | |
1255 | ||
1256 | return extract_unsigned_integer (buf, instlen, byte_order); | |
1257 | } | |
1258 | ||
17cf2897 AB |
1259 | /* Fetch from target memory an instruction at PC and decode it. This can |
1260 | throw an error if the memory access fails, callers are responsible for | |
1261 | handling this error if that is appropriate. */ | |
dbbb1059 AB |
1262 | |
1263 | void | |
1264 | riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1265 | { | |
1266 | ULONGEST ival; | |
1267 | ||
1268 | /* Fetch the instruction, and the instructions length. */ | |
1269 | ival = fetch_instruction (gdbarch, pc, &m_length); | |
1270 | ||
1271 | if (m_length == 4) | |
1272 | { | |
1273 | if (is_add_insn (ival)) | |
1274 | decode_r_type_insn (ADD, ival); | |
1275 | else if (is_addw_insn (ival)) | |
1276 | decode_r_type_insn (ADDW, ival); | |
1277 | else if (is_addi_insn (ival)) | |
1278 | decode_i_type_insn (ADDI, ival); | |
1279 | else if (is_addiw_insn (ival)) | |
1280 | decode_i_type_insn (ADDIW, ival); | |
1281 | else if (is_auipc_insn (ival)) | |
1282 | decode_u_type_insn (AUIPC, ival); | |
1283 | else if (is_lui_insn (ival)) | |
1284 | decode_u_type_insn (LUI, ival); | |
1285 | else if (is_sd_insn (ival)) | |
1286 | decode_s_type_insn (SD, ival); | |
1287 | else if (is_sw_insn (ival)) | |
1288 | decode_s_type_insn (SW, ival); | |
5c720ed8 JW |
1289 | else if (is_jal_insn (ival)) |
1290 | decode_j_type_insn (JAL, ival); | |
1291 | else if (is_jalr_insn (ival)) | |
1292 | decode_i_type_insn (JALR, ival); | |
1293 | else if (is_beq_insn (ival)) | |
1294 | decode_b_type_insn (BEQ, ival); | |
1295 | else if (is_bne_insn (ival)) | |
1296 | decode_b_type_insn (BNE, ival); | |
1297 | else if (is_blt_insn (ival)) | |
1298 | decode_b_type_insn (BLT, ival); | |
1299 | else if (is_bge_insn (ival)) | |
1300 | decode_b_type_insn (BGE, ival); | |
1301 | else if (is_bltu_insn (ival)) | |
1302 | decode_b_type_insn (BLTU, ival); | |
1303 | else if (is_bgeu_insn (ival)) | |
1304 | decode_b_type_insn (BGEU, ival); | |
1305 | else if (is_lr_w_insn (ival)) | |
1306 | decode_r_type_insn (LR, ival); | |
1307 | else if (is_lr_d_insn (ival)) | |
1308 | decode_r_type_insn (LR, ival); | |
1309 | else if (is_sc_w_insn (ival)) | |
1310 | decode_r_type_insn (SC, ival); | |
1311 | else if (is_sc_d_insn (ival)) | |
1312 | decode_r_type_insn (SC, ival); | |
dbbb1059 AB |
1313 | else |
1314 | /* None of the other fields are valid in this case. */ | |
1315 | m_opcode = OTHER; | |
1316 | } | |
1317 | else if (m_length == 2) | |
1318 | { | |
5c720ed8 JW |
1319 | int xlen = riscv_isa_xlen (gdbarch); |
1320 | ||
1321 | /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a | |
1322 | C_JALR. So must try to match C_JALR first as it has more bits in | |
1323 | mask. */ | |
1324 | if (is_c_jalr_insn (ival)) | |
1325 | decode_cr_type_insn (JALR, ival); | |
1326 | else if (is_c_add_insn (ival)) | |
dbbb1059 | 1327 | decode_cr_type_insn (ADD, ival); |
5c720ed8 JW |
1328 | /* C_ADDW is RV64 and RV128 only. */ |
1329 | else if (xlen != 4 && is_c_addw_insn (ival)) | |
dbbb1059 AB |
1330 | decode_cr_type_insn (ADDW, ival); |
1331 | else if (is_c_addi_insn (ival)) | |
1332 | decode_ci_type_insn (ADDI, ival); | |
5c720ed8 JW |
1333 | /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128 |
1334 | only and C_JAL is RV32 only. */ | |
1335 | else if (xlen != 4 && is_c_addiw_insn (ival)) | |
dbbb1059 | 1336 | decode_ci_type_insn (ADDIW, ival); |
5c720ed8 JW |
1337 | else if (xlen == 4 && is_c_jal_insn (ival)) |
1338 | decode_cj_type_insn (JAL, ival); | |
1339 | /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a | |
1340 | C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits | |
1341 | in mask. */ | |
dbbb1059 AB |
1342 | else if (is_c_addi16sp_insn (ival)) |
1343 | { | |
1344 | m_opcode = ADDI; | |
1345 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD); | |
1346 | m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival); | |
1347 | } | |
ff3a05b3 AB |
1348 | else if (is_c_addi4spn_insn (ival)) |
1349 | { | |
1350 | m_opcode = ADDI; | |
1351 | m_rd = decode_register_index_short (ival, OP_SH_CRS2S); | |
1352 | m_rs1 = RISCV_SP_REGNUM; | |
1353 | m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival); | |
1354 | } | |
5c720ed8 | 1355 | else if (is_c_lui_insn (ival)) |
d354055e AB |
1356 | { |
1357 | m_opcode = LUI; | |
1358 | m_rd = decode_register_index (ival, OP_SH_CRS1S); | |
1359 | m_imm.s = EXTRACT_RVC_LUI_IMM (ival); | |
1360 | } | |
5c720ed8 JW |
1361 | /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only, |
1362 | and C_FSW is RV32 only. */ | |
1363 | else if (xlen != 4 && is_c_sd_insn (ival)) | |
ff3a05b3 | 1364 | decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival)); |
5c720ed8 | 1365 | else if (is_c_sw_insn (ival)) |
ff3a05b3 AB |
1366 | decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival)); |
1367 | else if (is_c_swsp_insn (ival)) | |
1368 | decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival)); | |
1369 | else if (xlen != 4 && is_c_sdsp_insn (ival)) | |
1370 | decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival)); | |
5c720ed8 JW |
1371 | /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR. |
1372 | So must try to match C_JR first as it ahs more bits in mask. */ | |
1373 | else if (is_c_jr_insn (ival)) | |
1374 | decode_cr_type_insn (JALR, ival); | |
1375 | else if (is_c_j_insn (ival)) | |
1376 | decode_cj_type_insn (JAL, ival); | |
1377 | else if (is_c_beqz_insn (ival)) | |
1378 | decode_cb_type_insn (BEQ, ival); | |
1379 | else if (is_c_bnez_insn (ival)) | |
1380 | decode_cb_type_insn (BNE, ival); | |
dbbb1059 AB |
1381 | else |
1382 | /* None of the other fields of INSN are valid in this case. */ | |
1383 | m_opcode = OTHER; | |
1384 | } | |
1385 | else | |
1386 | internal_error (__FILE__, __LINE__, | |
1387 | _("unable to decode %d byte instructions in " | |
1388 | "prologue at %s"), m_length, | |
1389 | core_addr_to_string (pc)); | |
1390 | } | |
1391 | ||
1392 | /* The prologue scanner. This is currently only used for skipping the | |
1393 | prologue of a function when the DWARF information is not sufficient. | |
1394 | However, it is written with filling of the frame cache in mind, which | |
1395 | is why different groups of stack setup instructions are split apart | |
1396 | during the core of the inner loop. In the future, the intention is to | |
1397 | extend this function to fully support building up a frame cache that | |
1398 | can unwind register values when there is no DWARF information. */ | |
1399 | ||
1400 | static CORE_ADDR | |
1401 | riscv_scan_prologue (struct gdbarch *gdbarch, | |
78a3b0fa AB |
1402 | CORE_ADDR start_pc, CORE_ADDR end_pc, |
1403 | struct riscv_unwind_cache *cache) | |
dbbb1059 | 1404 | { |
78a3b0fa | 1405 | CORE_ADDR cur_pc, next_pc, after_prologue_pc; |
dbbb1059 AB |
1406 | CORE_ADDR end_prologue_addr = 0; |
1407 | ||
78a3b0fa AB |
1408 | /* Find an upper limit on the function prologue using the debug |
1409 | information. If the debug information could not be used to provide | |
1410 | that bound, then use an arbitrary large number as the upper bound. */ | |
1411 | after_prologue_pc = skip_prologue_using_sal (gdbarch, start_pc); | |
1412 | if (after_prologue_pc == 0) | |
1413 | after_prologue_pc = start_pc + 100; /* Arbitrary large number. */ | |
1414 | if (after_prologue_pc < end_pc) | |
1415 | end_pc = after_prologue_pc; | |
1416 | ||
1417 | pv_t regs[RISCV_NUM_INTEGER_REGS]; /* Number of GPR. */ | |
1418 | for (int regno = 0; regno < RISCV_NUM_INTEGER_REGS; regno++) | |
1419 | regs[regno] = pv_register (regno, 0); | |
1420 | pv_area stack (RISCV_SP_REGNUM, gdbarch_addr_bit (gdbarch)); | |
1421 | ||
1422 | if (riscv_debug_unwinder) | |
1423 | fprintf_unfiltered | |
1424 | (gdb_stdlog, | |
1425 | "Prologue scan for function starting at %s (limit %s)\n", | |
1426 | core_addr_to_string (start_pc), | |
1427 | core_addr_to_string (end_pc)); | |
1428 | ||
1429 | for (next_pc = cur_pc = start_pc; cur_pc < end_pc; cur_pc = next_pc) | |
dbbb1059 AB |
1430 | { |
1431 | struct riscv_insn insn; | |
1432 | ||
1433 | /* Decode the current instruction, and decide where the next | |
1434 | instruction lives based on the size of this instruction. */ | |
1435 | insn.decode (gdbarch, cur_pc); | |
1436 | gdb_assert (insn.length () > 0); | |
1437 | next_pc = cur_pc + insn.length (); | |
1438 | ||
1439 | /* Look for common stack adjustment insns. */ | |
1440 | if ((insn.opcode () == riscv_insn::ADDI | |
1441 | || insn.opcode () == riscv_insn::ADDIW) | |
1442 | && insn.rd () == RISCV_SP_REGNUM | |
1443 | && insn.rs1 () == RISCV_SP_REGNUM) | |
1444 | { | |
1445 | /* Handle: addi sp, sp, -i | |
1446 | or: addiw sp, sp, -i */ | |
78a3b0fa AB |
1447 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
1448 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1449 | regs[insn.rd ()] | |
1450 | = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()); | |
dbbb1059 AB |
1451 | } |
1452 | else if ((insn.opcode () == riscv_insn::SW | |
1453 | || insn.opcode () == riscv_insn::SD) | |
1454 | && (insn.rs1 () == RISCV_SP_REGNUM | |
1455 | || insn.rs1 () == RISCV_FP_REGNUM)) | |
1456 | { | |
1457 | /* Handle: sw reg, offset(sp) | |
1458 | or: sd reg, offset(sp) | |
1459 | or: sw reg, offset(s0) | |
1460 | or: sd reg, offset(s0) */ | |
1461 | /* Instruction storing a register onto the stack. */ | |
78a3b0fa AB |
1462 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); |
1463 | gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS); | |
1464 | stack.store (pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()), | |
1465 | (insn.opcode () == riscv_insn::SW ? 4 : 8), | |
1466 | regs[insn.rs2 ()]); | |
dbbb1059 AB |
1467 | } |
1468 | else if (insn.opcode () == riscv_insn::ADDI | |
1469 | && insn.rd () == RISCV_FP_REGNUM | |
1470 | && insn.rs1 () == RISCV_SP_REGNUM) | |
1471 | { | |
1472 | /* Handle: addi s0, sp, size */ | |
1473 | /* Instructions setting up the frame pointer. */ | |
78a3b0fa AB |
1474 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
1475 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1476 | regs[insn.rd ()] | |
1477 | = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()); | |
dbbb1059 AB |
1478 | } |
1479 | else if ((insn.opcode () == riscv_insn::ADD | |
1480 | || insn.opcode () == riscv_insn::ADDW) | |
1481 | && insn.rd () == RISCV_FP_REGNUM | |
1482 | && insn.rs1 () == RISCV_SP_REGNUM | |
1483 | && insn.rs2 () == RISCV_ZERO_REGNUM) | |
1484 | { | |
1485 | /* Handle: add s0, sp, 0 | |
1486 | or: addw s0, sp, 0 */ | |
1487 | /* Instructions setting up the frame pointer. */ | |
78a3b0fa AB |
1488 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
1489 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1490 | regs[insn.rd ()] = pv_add_constant (regs[insn.rs1 ()], 0); | |
dbbb1059 | 1491 | } |
d354055e AB |
1492 | else if ((insn.opcode () == riscv_insn::ADDI |
1493 | && insn.rd () == RISCV_ZERO_REGNUM | |
1494 | && insn.rs1 () == RISCV_ZERO_REGNUM | |
1495 | && insn.imm_signed () == 0)) | |
dbbb1059 | 1496 | { |
d354055e | 1497 | /* Handle: add x0, x0, 0 (NOP) */ |
dbbb1059 | 1498 | } |
d354055e AB |
1499 | else if (insn.opcode () == riscv_insn::AUIPC) |
1500 | { | |
1501 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); | |
1502 | regs[insn.rd ()] = pv_constant (cur_pc + insn.imm_signed ()); | |
1503 | } | |
1504 | else if (insn.opcode () == riscv_insn::LUI) | |
1505 | { | |
1506 | /* Handle: lui REG, n | |
1507 | Where REG is not gp register. */ | |
1508 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); | |
1509 | regs[insn.rd ()] = pv_constant (insn.imm_signed ()); | |
1510 | } | |
1511 | else if (insn.opcode () == riscv_insn::ADDI) | |
1512 | { | |
1513 | /* Handle: addi REG1, REG2, IMM */ | |
1514 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); | |
1515 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1516 | regs[insn.rd ()] | |
1517 | = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()); | |
1518 | } | |
1519 | else if (insn.opcode () == riscv_insn::ADD) | |
1520 | { | |
1521 | /* Handle: addi REG1, REG2, IMM */ | |
1522 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); | |
1523 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1524 | gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS); | |
1525 | regs[insn.rd ()] = pv_add (regs[insn.rs1 ()], regs[insn.rs2 ()]); | |
1526 | } | |
dbbb1059 AB |
1527 | else |
1528 | { | |
78a3b0fa AB |
1529 | end_prologue_addr = cur_pc; |
1530 | break; | |
dbbb1059 AB |
1531 | } |
1532 | } | |
1533 | ||
1534 | if (end_prologue_addr == 0) | |
1535 | end_prologue_addr = cur_pc; | |
1536 | ||
78a3b0fa AB |
1537 | if (riscv_debug_unwinder) |
1538 | fprintf_unfiltered (gdb_stdlog, "End of prologue at %s\n", | |
1539 | core_addr_to_string (end_prologue_addr)); | |
1540 | ||
1541 | if (cache != NULL) | |
1542 | { | |
1543 | /* Figure out if it is a frame pointer or just a stack pointer. Also | |
1544 | the offset held in the pv_t is from the original register value to | |
1545 | the current value, which for a grows down stack means a negative | |
1546 | value. The FRAME_BASE_OFFSET is the negation of this, how to get | |
1547 | from the current value to the original value. */ | |
1548 | if (pv_is_register (regs[RISCV_FP_REGNUM], RISCV_SP_REGNUM)) | |
1549 | { | |
1550 | cache->frame_base_reg = RISCV_FP_REGNUM; | |
1551 | cache->frame_base_offset = -regs[RISCV_FP_REGNUM].k; | |
1552 | } | |
1553 | else | |
1554 | { | |
1555 | cache->frame_base_reg = RISCV_SP_REGNUM; | |
1556 | cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k; | |
1557 | } | |
1558 | ||
1559 | /* Assign offset from old SP to all saved registers. As we don't | |
1560 | have the previous value for the frame base register at this | |
1561 | point, we store the offset as the address in the trad_frame, and | |
1562 | then convert this to an actual address later. */ | |
1563 | for (int i = 0; i <= RISCV_NUM_INTEGER_REGS; i++) | |
1564 | { | |
1565 | CORE_ADDR offset; | |
1566 | if (stack.find_reg (gdbarch, i, &offset)) | |
1567 | { | |
1568 | if (riscv_debug_unwinder) | |
1569 | fprintf_unfiltered (gdb_stdlog, | |
1570 | "Register $%s at stack offset %ld\n", | |
1571 | gdbarch_register_name (gdbarch, i), | |
1572 | offset); | |
1573 | trad_frame_set_addr (cache->regs, i, offset); | |
1574 | } | |
1575 | } | |
1576 | } | |
1577 | ||
dbbb1059 AB |
1578 | return end_prologue_addr; |
1579 | } | |
1580 | ||
1581 | /* Implement the riscv_skip_prologue gdbarch method. */ | |
1582 | ||
1583 | static CORE_ADDR | |
78a3b0fa | 1584 | riscv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
dbbb1059 | 1585 | { |
dbbb1059 AB |
1586 | CORE_ADDR func_addr; |
1587 | ||
1588 | /* See if we can determine the end of the prologue via the symbol | |
1589 | table. If so, then return either PC, or the PC after the | |
1590 | prologue, whichever is greater. */ | |
1591 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
1592 | { | |
1593 | CORE_ADDR post_prologue_pc | |
1594 | = skip_prologue_using_sal (gdbarch, func_addr); | |
1595 | ||
1596 | if (post_prologue_pc != 0) | |
1597 | return std::max (pc, post_prologue_pc); | |
1598 | } | |
1599 | ||
1600 | /* Can't determine prologue from the symbol table, need to examine | |
78a3b0fa AB |
1601 | instructions. Pass -1 for the end address to indicate the prologue |
1602 | scanner can scan as far as it needs to find the end of the prologue. */ | |
1603 | return riscv_scan_prologue (gdbarch, pc, ((CORE_ADDR) -1), NULL); | |
dbbb1059 AB |
1604 | } |
1605 | ||
1606 | /* Implement the gdbarch push dummy code callback. */ | |
1607 | ||
1608 | static CORE_ADDR | |
1609 | riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
1610 | CORE_ADDR funaddr, struct value **args, int nargs, | |
1611 | struct type *value_type, CORE_ADDR *real_pc, | |
1612 | CORE_ADDR *bp_addr, struct regcache *regcache) | |
1613 | { | |
1614 | /* Allocate space for a breakpoint, and keep the stack correctly | |
1615 | aligned. */ | |
1616 | sp -= 16; | |
1617 | *bp_addr = sp; | |
1618 | *real_pc = funaddr; | |
1619 | return sp; | |
1620 | } | |
1621 | ||
1622 | /* Compute the alignment of the type T. Used while setting up the | |
1623 | arguments for a dummy call. */ | |
1624 | ||
1625 | static int | |
1626 | riscv_type_alignment (struct type *t) | |
1627 | { | |
1628 | t = check_typedef (t); | |
1629 | switch (TYPE_CODE (t)) | |
1630 | { | |
1631 | default: | |
1632 | error (_("Could not compute alignment of type")); | |
1633 | ||
1634 | case TYPE_CODE_RVALUE_REF: | |
1635 | case TYPE_CODE_PTR: | |
1636 | case TYPE_CODE_ENUM: | |
1637 | case TYPE_CODE_INT: | |
1638 | case TYPE_CODE_FLT: | |
1639 | case TYPE_CODE_REF: | |
1640 | case TYPE_CODE_CHAR: | |
1641 | case TYPE_CODE_BOOL: | |
1642 | return TYPE_LENGTH (t); | |
1643 | ||
1644 | case TYPE_CODE_ARRAY: | |
1645 | case TYPE_CODE_COMPLEX: | |
1646 | return riscv_type_alignment (TYPE_TARGET_TYPE (t)); | |
1647 | ||
1648 | case TYPE_CODE_STRUCT: | |
1649 | case TYPE_CODE_UNION: | |
1650 | { | |
1651 | int i; | |
1652 | int align = 1; | |
1653 | ||
1654 | for (i = 0; i < TYPE_NFIELDS (t); ++i) | |
1655 | { | |
1656 | if (TYPE_FIELD_LOC_KIND (t, i) == FIELD_LOC_KIND_BITPOS) | |
1657 | { | |
1658 | int a = riscv_type_alignment (TYPE_FIELD_TYPE (t, i)); | |
1659 | if (a > align) | |
1660 | align = a; | |
1661 | } | |
1662 | } | |
1663 | return align; | |
1664 | } | |
1665 | } | |
1666 | } | |
1667 | ||
1668 | /* Holds information about a single argument either being passed to an | |
1669 | inferior function, or returned from an inferior function. This includes | |
1670 | information about the size, type, etc of the argument, and also | |
1671 | information about how the argument will be passed (or returned). */ | |
1672 | ||
1673 | struct riscv_arg_info | |
1674 | { | |
1675 | /* Contents of the argument. */ | |
1676 | const gdb_byte *contents; | |
1677 | ||
1678 | /* Length of argument. */ | |
1679 | int length; | |
1680 | ||
1681 | /* Alignment required for an argument of this type. */ | |
1682 | int align; | |
1683 | ||
1684 | /* The type for this argument. */ | |
1685 | struct type *type; | |
1686 | ||
1687 | /* Each argument can have either 1 or 2 locations assigned to it. Each | |
1688 | location describes where part of the argument will be placed. The | |
1689 | second location is valid based on the LOC_TYPE and C_LENGTH fields | |
1690 | of the first location (which is always valid). */ | |
1691 | struct location | |
1692 | { | |
1693 | /* What type of location this is. */ | |
1694 | enum location_type | |
1695 | { | |
1696 | /* Argument passed in a register. */ | |
1697 | in_reg, | |
1698 | ||
1699 | /* Argument passed as an on stack argument. */ | |
1700 | on_stack, | |
1701 | ||
1702 | /* Argument passed by reference. The second location is always | |
1703 | valid for a BY_REF argument, and describes where the address | |
1704 | of the BY_REF argument should be placed. */ | |
1705 | by_ref | |
1706 | } loc_type; | |
1707 | ||
1708 | /* Information that depends on the location type. */ | |
1709 | union | |
1710 | { | |
1711 | /* Which register number to use. */ | |
1712 | int regno; | |
1713 | ||
1714 | /* The offset into the stack region. */ | |
1715 | int offset; | |
1716 | } loc_data; | |
1717 | ||
1718 | /* The length of contents covered by this location. If this is less | |
1719 | than the total length of the argument, then the second location | |
1720 | will be valid, and will describe where the rest of the argument | |
1721 | will go. */ | |
1722 | int c_length; | |
1723 | ||
1724 | /* The offset within CONTENTS for this part of the argument. Will | |
1725 | always be 0 for the first part. For the second part of the | |
1726 | argument, this might be the C_LENGTH value of the first part, | |
1727 | however, if we are passing a structure in two registers, and there's | |
1728 | is padding between the first and second field, then this offset | |
1729 | might be greater than the length of the first argument part. When | |
1730 | the second argument location is not holding part of the argument | |
1731 | value, but is instead holding the address of a reference argument, | |
1732 | then this offset will be set to 0. */ | |
1733 | int c_offset; | |
1734 | } argloc[2]; | |
1735 | }; | |
1736 | ||
1737 | /* Information about a set of registers being used for passing arguments as | |
1738 | part of a function call. The register set must be numerically | |
1739 | sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be | |
1740 | disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */ | |
1741 | ||
1742 | struct riscv_arg_reg | |
1743 | { | |
1744 | riscv_arg_reg (int first, int last) | |
1745 | : next_regnum (first), | |
1746 | last_regnum (last) | |
1747 | { | |
1748 | /* Nothing. */ | |
1749 | } | |
1750 | ||
1751 | /* The GDB register number to use in this set. */ | |
1752 | int next_regnum; | |
1753 | ||
1754 | /* The last GDB register number to use in this set. */ | |
1755 | int last_regnum; | |
1756 | }; | |
1757 | ||
1758 | /* Arguments can be passed as on stack arguments, or by reference. The | |
1759 | on stack arguments must be in a continuous region starting from $sp, | |
1760 | while the by reference arguments can be anywhere, but we'll put them | |
1761 | on the stack after (at higher address) the on stack arguments. | |
1762 | ||
1763 | This might not be the right approach to take. The ABI is clear that | |
1764 | an argument passed by reference can be modified by the callee, which | |
1765 | us placing the argument (temporarily) onto the stack will not achieve | |
1766 | (changes will be lost). There's also the possibility that very large | |
1767 | arguments could overflow the stack. | |
1768 | ||
1769 | This struct is used to track offset into these two areas for where | |
1770 | arguments are to be placed. */ | |
1771 | struct riscv_memory_offsets | |
1772 | { | |
1773 | riscv_memory_offsets () | |
1774 | : arg_offset (0), | |
1775 | ref_offset (0) | |
1776 | { | |
1777 | /* Nothing. */ | |
1778 | } | |
1779 | ||
1780 | /* Offset into on stack argument area. */ | |
1781 | int arg_offset; | |
1782 | ||
1783 | /* Offset into the pass by reference area. */ | |
1784 | int ref_offset; | |
1785 | }; | |
1786 | ||
1787 | /* Holds information about where arguments to a call will be placed. This | |
1788 | is updated as arguments are added onto the call, and can be used to | |
1789 | figure out where the next argument should be placed. */ | |
1790 | ||
1791 | struct riscv_call_info | |
1792 | { | |
1793 | riscv_call_info (struct gdbarch *gdbarch) | |
1794 | : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7), | |
1795 | float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7) | |
1796 | { | |
1797 | xlen = riscv_isa_xlen (gdbarch); | |
1798 | flen = riscv_isa_flen (gdbarch); | |
1799 | ||
1800 | /* Disable use of floating point registers if needed. */ | |
1801 | if (!riscv_has_fp_abi (gdbarch)) | |
1802 | float_regs.next_regnum = float_regs.last_regnum + 1; | |
1803 | } | |
1804 | ||
1805 | /* Track the memory areas used for holding in-memory arguments to a | |
1806 | call. */ | |
1807 | struct riscv_memory_offsets memory; | |
1808 | ||
1809 | /* Holds information about the next integer register to use for passing | |
1810 | an argument. */ | |
1811 | struct riscv_arg_reg int_regs; | |
1812 | ||
1813 | /* Holds information about the next floating point register to use for | |
1814 | passing an argument. */ | |
1815 | struct riscv_arg_reg float_regs; | |
1816 | ||
1817 | /* The XLEN and FLEN are copied in to this structure for convenience, and | |
1818 | are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */ | |
1819 | int xlen; | |
1820 | int flen; | |
1821 | }; | |
1822 | ||
1823 | /* Return the number of registers available for use as parameters in the | |
1824 | register set REG. Returned value can be 0 or more. */ | |
1825 | ||
1826 | static int | |
1827 | riscv_arg_regs_available (struct riscv_arg_reg *reg) | |
1828 | { | |
1829 | if (reg->next_regnum > reg->last_regnum) | |
1830 | return 0; | |
1831 | ||
1832 | return (reg->last_regnum - reg->next_regnum + 1); | |
1833 | } | |
1834 | ||
1835 | /* If there is at least one register available in the register set REG then | |
1836 | the next register from REG is assigned to LOC and the length field of | |
1837 | LOC is updated to LENGTH. The register set REG is updated to indicate | |
1838 | that the assigned register is no longer available and the function | |
1839 | returns true. | |
1840 | ||
1841 | If there are no registers available in REG then the function returns | |
1842 | false, and LOC and REG are unchanged. */ | |
1843 | ||
1844 | static bool | |
1845 | riscv_assign_reg_location (struct riscv_arg_info::location *loc, | |
1846 | struct riscv_arg_reg *reg, | |
1847 | int length, int offset) | |
1848 | { | |
1849 | if (reg->next_regnum <= reg->last_regnum) | |
1850 | { | |
1851 | loc->loc_type = riscv_arg_info::location::in_reg; | |
1852 | loc->loc_data.regno = reg->next_regnum; | |
1853 | reg->next_regnum++; | |
1854 | loc->c_length = length; | |
1855 | loc->c_offset = offset; | |
1856 | return true; | |
1857 | } | |
1858 | ||
1859 | return false; | |
1860 | } | |
1861 | ||
1862 | /* Assign LOC a location as the next stack parameter, and update MEMORY to | |
1863 | record that an area of stack has been used to hold the parameter | |
1864 | described by LOC. | |
1865 | ||
1866 | The length field of LOC is updated to LENGTH, the length of the | |
1867 | parameter being stored, and ALIGN is the alignment required by the | |
1868 | parameter, which will affect how memory is allocated out of MEMORY. */ | |
1869 | ||
1870 | static void | |
1871 | riscv_assign_stack_location (struct riscv_arg_info::location *loc, | |
1872 | struct riscv_memory_offsets *memory, | |
1873 | int length, int align) | |
1874 | { | |
1875 | loc->loc_type = riscv_arg_info::location::on_stack; | |
1876 | memory->arg_offset | |
1877 | = align_up (memory->arg_offset, align); | |
1878 | loc->loc_data.offset = memory->arg_offset; | |
1879 | memory->arg_offset += length; | |
1880 | loc->c_length = length; | |
1881 | ||
1882 | /* Offset is always 0, either we're the first location part, in which | |
1883 | case we're reading content from the start of the argument, or we're | |
1884 | passing the address of a reference argument, so 0. */ | |
1885 | loc->c_offset = 0; | |
1886 | } | |
1887 | ||
1888 | /* Update AINFO, which describes an argument that should be passed or | |
1889 | returned using the integer ABI. The argloc fields within AINFO are | |
1890 | updated to describe the location in which the argument will be passed to | |
1891 | a function, or returned from a function. | |
1892 | ||
1893 | The CINFO structure contains the ongoing call information, the holds | |
1894 | information such as which argument registers are remaining to be | |
1895 | assigned to parameter, and how much memory has been used by parameters | |
1896 | so far. | |
1897 | ||
1898 | By examining the state of CINFO a suitable location can be selected, | |
1899 | and assigned to AINFO. */ | |
1900 | ||
1901 | static void | |
1902 | riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo, | |
1903 | struct riscv_call_info *cinfo) | |
1904 | { | |
1905 | if (ainfo->length > (2 * cinfo->xlen)) | |
1906 | { | |
1907 | /* Argument is going to be passed by reference. */ | |
1908 | ainfo->argloc[0].loc_type | |
1909 | = riscv_arg_info::location::by_ref; | |
1910 | cinfo->memory.ref_offset | |
1911 | = align_up (cinfo->memory.ref_offset, ainfo->align); | |
1912 | ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset; | |
1913 | cinfo->memory.ref_offset += ainfo->length; | |
1914 | ainfo->argloc[0].c_length = ainfo->length; | |
1915 | ||
1916 | /* The second location for this argument is given over to holding the | |
1917 | address of the by-reference data. Pass 0 for the offset as this | |
1918 | is not part of the actual argument value. */ | |
1919 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
1920 | &cinfo->int_regs, | |
1921 | cinfo->xlen, 0)) | |
1922 | riscv_assign_stack_location (&ainfo->argloc[1], | |
1923 | &cinfo->memory, cinfo->xlen, | |
1924 | cinfo->xlen); | |
1925 | } | |
1926 | else | |
1927 | { | |
1928 | int len = (ainfo->length > cinfo->xlen) ? cinfo->xlen : ainfo->length; | |
1929 | ||
1930 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
1931 | &cinfo->int_regs, len, 0)) | |
1932 | riscv_assign_stack_location (&ainfo->argloc[0], | |
1933 | &cinfo->memory, len, ainfo->align); | |
1934 | ||
1935 | if (len < ainfo->length) | |
1936 | { | |
1937 | len = ainfo->length - len; | |
1938 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
1939 | &cinfo->int_regs, len, | |
1940 | cinfo->xlen)) | |
1941 | riscv_assign_stack_location (&ainfo->argloc[1], | |
1942 | &cinfo->memory, len, cinfo->xlen); | |
1943 | } | |
1944 | } | |
1945 | } | |
1946 | ||
1947 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO | |
1948 | is being passed with the floating point ABI. */ | |
1949 | ||
1950 | static void | |
1951 | riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo, | |
1952 | struct riscv_call_info *cinfo) | |
1953 | { | |
1954 | if (ainfo->length > cinfo->flen) | |
1955 | return riscv_call_arg_scalar_int (ainfo, cinfo); | |
1956 | else | |
1957 | { | |
1958 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
1959 | &cinfo->float_regs, | |
1960 | ainfo->length, 0)) | |
1961 | return riscv_call_arg_scalar_int (ainfo, cinfo); | |
1962 | } | |
1963 | } | |
1964 | ||
1965 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO | |
1966 | is a complex floating point argument, and is therefore handled | |
1967 | differently to other argument types. */ | |
1968 | ||
1969 | static void | |
1970 | riscv_call_arg_complex_float (struct riscv_arg_info *ainfo, | |
1971 | struct riscv_call_info *cinfo) | |
1972 | { | |
1973 | if (ainfo->length <= (2 * cinfo->flen) | |
1974 | && riscv_arg_regs_available (&cinfo->float_regs) >= 2) | |
1975 | { | |
1976 | bool result; | |
1977 | int len = ainfo->length / 2; | |
1978 | ||
1979 | result = riscv_assign_reg_location (&ainfo->argloc[0], | |
1980 | &cinfo->float_regs, len, len); | |
1981 | gdb_assert (result); | |
1982 | ||
1983 | result = riscv_assign_reg_location (&ainfo->argloc[1], | |
1984 | &cinfo->float_regs, len, len); | |
1985 | gdb_assert (result); | |
1986 | } | |
1987 | else | |
1988 | return riscv_call_arg_scalar_int (ainfo, cinfo); | |
1989 | } | |
1990 | ||
1991 | /* A structure used for holding information about a structure type within | |
1992 | the inferior program. The RiscV ABI has special rules for handling some | |
1993 | structures with a single field or with two fields. The counting of | |
1994 | fields here is done after flattening out all nested structures. */ | |
1995 | ||
1996 | class riscv_struct_info | |
1997 | { | |
1998 | public: | |
1999 | riscv_struct_info () | |
2000 | : m_number_of_fields (0), | |
2001 | m_types { nullptr, nullptr } | |
2002 | { | |
2003 | /* Nothing. */ | |
2004 | } | |
2005 | ||
2006 | /* Analyse TYPE descending into nested structures, count the number of | |
2007 | scalar fields and record the types of the first two fields found. */ | |
2008 | void analyse (struct type *type); | |
2009 | ||
2010 | /* The number of scalar fields found in the analysed type. This is | |
2011 | currently only accurate if the value returned is 0, 1, or 2 as the | |
2012 | analysis stops counting when the number of fields is 3. This is | |
2013 | because the RiscV ABI only has special cases for 1 or 2 fields, | |
2014 | anything else we just don't care about. */ | |
2015 | int number_of_fields () const | |
2016 | { return m_number_of_fields; } | |
2017 | ||
2018 | /* Return the type for scalar field INDEX within the analysed type. Will | |
2019 | return nullptr if there is no field at that index. Only INDEX values | |
2020 | 0 and 1 can be requested as the RiscV ABI only has special cases for | |
2021 | structures with 1 or 2 fields. */ | |
2022 | struct type *field_type (int index) const | |
2023 | { | |
2024 | gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0]))); | |
2025 | return m_types[index]; | |
2026 | } | |
2027 | ||
2028 | private: | |
2029 | /* The number of scalar fields found within the structure after recursing | |
2030 | into nested structures. */ | |
2031 | int m_number_of_fields; | |
2032 | ||
2033 | /* The types of the first two scalar fields found within the structure | |
2034 | after recursing into nested structures. */ | |
2035 | struct type *m_types[2]; | |
2036 | }; | |
2037 | ||
2038 | /* Analyse TYPE descending into nested structures, count the number of | |
2039 | scalar fields and record the types of the first two fields found. */ | |
2040 | ||
2041 | void | |
2042 | riscv_struct_info::analyse (struct type *type) | |
2043 | { | |
2044 | unsigned int count = TYPE_NFIELDS (type); | |
2045 | unsigned int i; | |
2046 | ||
2047 | for (i = 0; i < count; ++i) | |
2048 | { | |
2049 | if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS) | |
2050 | continue; | |
2051 | ||
2052 | struct type *field_type = TYPE_FIELD_TYPE (type, i); | |
2053 | field_type = check_typedef (field_type); | |
2054 | ||
2055 | switch (TYPE_CODE (field_type)) | |
2056 | { | |
2057 | case TYPE_CODE_STRUCT: | |
2058 | analyse (field_type); | |
2059 | break; | |
2060 | ||
2061 | default: | |
2062 | /* RiscV only flattens out structures. Anything else does not | |
2063 | need to be flattened, we just record the type, and when we | |
2064 | look at the analysis results we'll realise this is not a | |
2065 | structure we can special case, and pass the structure in | |
2066 | memory. */ | |
2067 | if (m_number_of_fields < 2) | |
2068 | m_types[m_number_of_fields] = field_type; | |
2069 | m_number_of_fields++; | |
2070 | break; | |
2071 | } | |
2072 | ||
2073 | /* RiscV only has special handling for structures with 1 or 2 scalar | |
2074 | fields, any more than that and the structure is just passed in | |
2075 | memory. We can safely drop out early when we find 3 or more | |
2076 | fields then. */ | |
2077 | ||
2078 | if (m_number_of_fields > 2) | |
2079 | return; | |
2080 | } | |
2081 | } | |
2082 | ||
2083 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO | |
2084 | is a structure. Small structures on RiscV have some special case | |
2085 | handling in order that the structure might be passed in register. | |
2086 | Larger structures are passed in memory. After assigning location | |
2087 | information to AINFO, CINFO will have been updated. */ | |
2088 | ||
2089 | static void | |
2090 | riscv_call_arg_struct (struct riscv_arg_info *ainfo, | |
2091 | struct riscv_call_info *cinfo) | |
2092 | { | |
2093 | if (riscv_arg_regs_available (&cinfo->float_regs) >= 1) | |
2094 | { | |
2095 | struct riscv_struct_info sinfo; | |
2096 | ||
2097 | sinfo.analyse (ainfo->type); | |
2098 | if (sinfo.number_of_fields () == 1 | |
2099 | && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_COMPLEX) | |
2100 | { | |
2101 | gdb_assert (TYPE_LENGTH (ainfo->type) | |
2102 | == TYPE_LENGTH (sinfo.field_type (0))); | |
2103 | return riscv_call_arg_complex_float (ainfo, cinfo); | |
2104 | } | |
2105 | ||
2106 | if (sinfo.number_of_fields () == 1 | |
2107 | && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT) | |
2108 | { | |
2109 | gdb_assert (TYPE_LENGTH (ainfo->type) | |
2110 | == TYPE_LENGTH (sinfo.field_type (0))); | |
2111 | return riscv_call_arg_scalar_float (ainfo, cinfo); | |
2112 | } | |
2113 | ||
2114 | if (sinfo.number_of_fields () == 2 | |
2115 | && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT | |
2116 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen | |
2117 | && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT | |
2118 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen | |
2119 | && riscv_arg_regs_available (&cinfo->float_regs) >= 2) | |
2120 | { | |
2121 | int len0, len1, offset; | |
2122 | ||
2123 | gdb_assert (TYPE_LENGTH (ainfo->type) <= (2 * cinfo->flen)); | |
2124 | ||
2125 | len0 = TYPE_LENGTH (sinfo.field_type (0)); | |
2126 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
2127 | &cinfo->float_regs, len0, 0)) | |
2128 | error (_("failed during argument setup")); | |
2129 | ||
2130 | len1 = TYPE_LENGTH (sinfo.field_type (1)); | |
2131 | offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1))); | |
2132 | gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type) | |
2133 | - TYPE_LENGTH (sinfo.field_type (0)))); | |
2134 | ||
2135 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
2136 | &cinfo->float_regs, | |
2137 | len1, offset)) | |
2138 | error (_("failed during argument setup")); | |
2139 | return; | |
2140 | } | |
2141 | ||
2142 | if (sinfo.number_of_fields () == 2 | |
2143 | && riscv_arg_regs_available (&cinfo->int_regs) >= 1 | |
2144 | && (TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT | |
2145 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen | |
2146 | && is_integral_type (sinfo.field_type (1)) | |
2147 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen)) | |
2148 | { | |
2149 | int len0, len1, offset; | |
2150 | ||
2151 | gdb_assert (TYPE_LENGTH (ainfo->type) | |
2152 | <= (cinfo->flen + cinfo->xlen)); | |
2153 | ||
2154 | len0 = TYPE_LENGTH (sinfo.field_type (0)); | |
2155 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
2156 | &cinfo->float_regs, len0, 0)) | |
2157 | error (_("failed during argument setup")); | |
2158 | ||
2159 | len1 = TYPE_LENGTH (sinfo.field_type (1)); | |
2160 | offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1))); | |
2161 | gdb_assert (len1 <= cinfo->xlen); | |
2162 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
2163 | &cinfo->int_regs, len1, offset)) | |
2164 | error (_("failed during argument setup")); | |
2165 | return; | |
2166 | } | |
2167 | ||
2168 | if (sinfo.number_of_fields () == 2 | |
2169 | && riscv_arg_regs_available (&cinfo->int_regs) >= 1 | |
2170 | && (is_integral_type (sinfo.field_type (0)) | |
2171 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen | |
2172 | && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT | |
2173 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen)) | |
2174 | { | |
2175 | int len0, len1, offset; | |
2176 | ||
2177 | gdb_assert (TYPE_LENGTH (ainfo->type) | |
2178 | <= (cinfo->flen + cinfo->xlen)); | |
2179 | ||
2180 | len0 = TYPE_LENGTH (sinfo.field_type (0)); | |
2181 | len1 = TYPE_LENGTH (sinfo.field_type (1)); | |
2182 | offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1))); | |
2183 | ||
2184 | gdb_assert (len0 <= cinfo->xlen); | |
2185 | gdb_assert (len1 <= cinfo->flen); | |
2186 | ||
2187 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
2188 | &cinfo->int_regs, len0, 0)) | |
2189 | error (_("failed during argument setup")); | |
2190 | ||
2191 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
2192 | &cinfo->float_regs, | |
2193 | len1, offset)) | |
2194 | error (_("failed during argument setup")); | |
2195 | ||
2196 | return; | |
2197 | } | |
2198 | } | |
2199 | ||
2200 | /* Non of the structure flattening cases apply, so we just pass using | |
2201 | the integer ABI. */ | |
2202 | ainfo->length = align_up (ainfo->length, cinfo->xlen); | |
2203 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
2204 | } | |
2205 | ||
2206 | /* Assign a location to call (or return) argument AINFO, the location is | |
2207 | selected from CINFO which holds information about what call argument | |
2208 | locations are available for use next. The TYPE is the type of the | |
2209 | argument being passed, this information is recorded into AINFO (along | |
2210 | with some additional information derived from the type). | |
2211 | ||
2212 | After assigning a location to AINFO, CINFO will have been updated. */ | |
2213 | ||
2214 | static void | |
2215 | riscv_arg_location (struct gdbarch *gdbarch, | |
2216 | struct riscv_arg_info *ainfo, | |
2217 | struct riscv_call_info *cinfo, | |
2218 | struct type *type) | |
2219 | { | |
2220 | ainfo->type = type; | |
2221 | ainfo->length = TYPE_LENGTH (ainfo->type); | |
2222 | ainfo->align = riscv_type_alignment (ainfo->type); | |
2223 | ainfo->contents = nullptr; | |
2224 | ||
2225 | switch (TYPE_CODE (ainfo->type)) | |
2226 | { | |
2227 | case TYPE_CODE_INT: | |
2228 | case TYPE_CODE_BOOL: | |
2229 | case TYPE_CODE_CHAR: | |
2230 | case TYPE_CODE_RANGE: | |
2231 | case TYPE_CODE_ENUM: | |
2232 | case TYPE_CODE_PTR: | |
2233 | if (ainfo->length <= cinfo->xlen) | |
2234 | { | |
2235 | ainfo->type = builtin_type (gdbarch)->builtin_long; | |
2236 | ainfo->length = cinfo->xlen; | |
2237 | } | |
2238 | else if (ainfo->length <= (2 * cinfo->xlen)) | |
2239 | { | |
2240 | ainfo->type = builtin_type (gdbarch)->builtin_long_long; | |
2241 | ainfo->length = 2 * cinfo->xlen; | |
2242 | } | |
2243 | ||
2244 | /* Recalculate the alignment requirement. */ | |
2245 | ainfo->align = riscv_type_alignment (ainfo->type); | |
2246 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
2247 | break; | |
2248 | ||
2249 | case TYPE_CODE_FLT: | |
2250 | riscv_call_arg_scalar_float (ainfo, cinfo); | |
2251 | break; | |
2252 | ||
2253 | case TYPE_CODE_COMPLEX: | |
2254 | riscv_call_arg_complex_float (ainfo, cinfo); | |
2255 | break; | |
2256 | ||
2257 | case TYPE_CODE_STRUCT: | |
2258 | riscv_call_arg_struct (ainfo, cinfo); | |
2259 | break; | |
2260 | ||
2261 | default: | |
2262 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
2263 | break; | |
2264 | } | |
2265 | } | |
2266 | ||
cab5bb9d AB |
2267 | /* Used for printing debug information about the call argument location in |
2268 | INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base | |
2269 | addresses for the location of pass-by-reference and | |
2270 | arguments-on-the-stack memory areas. */ | |
2271 | ||
dbbb1059 | 2272 | static void |
cab5bb9d | 2273 | riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch, |
dbbb1059 AB |
2274 | struct riscv_arg_info *info, |
2275 | CORE_ADDR sp_refs, CORE_ADDR sp_args) | |
2276 | { | |
cab5bb9d | 2277 | fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x", |
42ecac17 | 2278 | TYPE_SAFE_NAME (info->type), info->length, info->align); |
dbbb1059 AB |
2279 | switch (info->argloc[0].loc_type) |
2280 | { | |
2281 | case riscv_arg_info::location::in_reg: | |
cab5bb9d AB |
2282 | fprintf_unfiltered |
2283 | (stream, ", register %s", | |
2284 | gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno)); | |
dbbb1059 AB |
2285 | if (info->argloc[0].c_length < info->length) |
2286 | { | |
2287 | switch (info->argloc[1].loc_type) | |
2288 | { | |
2289 | case riscv_arg_info::location::in_reg: | |
cab5bb9d AB |
2290 | fprintf_unfiltered |
2291 | (stream, ", register %s", | |
2292 | gdbarch_register_name (gdbarch, | |
2293 | info->argloc[1].loc_data.regno)); | |
dbbb1059 AB |
2294 | break; |
2295 | ||
2296 | case riscv_arg_info::location::on_stack: | |
cab5bb9d AB |
2297 | fprintf_unfiltered (stream, ", on stack at offset 0x%x", |
2298 | info->argloc[1].loc_data.offset); | |
dbbb1059 AB |
2299 | break; |
2300 | ||
2301 | case riscv_arg_info::location::by_ref: | |
2302 | default: | |
2303 | /* The second location should never be a reference, any | |
2304 | argument being passed by reference just places its address | |
2305 | in the first location and is done. */ | |
2306 | error (_("invalid argument location")); | |
2307 | break; | |
2308 | } | |
2309 | ||
2310 | if (info->argloc[1].c_offset > info->argloc[0].c_length) | |
cab5bb9d AB |
2311 | fprintf_unfiltered (stream, " (offset 0x%x)", |
2312 | info->argloc[1].c_offset); | |
dbbb1059 AB |
2313 | } |
2314 | break; | |
2315 | ||
2316 | case riscv_arg_info::location::on_stack: | |
cab5bb9d AB |
2317 | fprintf_unfiltered (stream, ", on stack at offset 0x%x", |
2318 | info->argloc[0].loc_data.offset); | |
dbbb1059 AB |
2319 | break; |
2320 | ||
2321 | case riscv_arg_info::location::by_ref: | |
cab5bb9d AB |
2322 | fprintf_unfiltered |
2323 | (stream, ", by reference, data at offset 0x%x (%s)", | |
2324 | info->argloc[0].loc_data.offset, | |
2325 | core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset)); | |
dbbb1059 AB |
2326 | if (info->argloc[1].loc_type |
2327 | == riscv_arg_info::location::in_reg) | |
cab5bb9d AB |
2328 | fprintf_unfiltered |
2329 | (stream, ", address in register %s", | |
2330 | gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno)); | |
dbbb1059 AB |
2331 | else |
2332 | { | |
2333 | gdb_assert (info->argloc[1].loc_type | |
2334 | == riscv_arg_info::location::on_stack); | |
cab5bb9d AB |
2335 | fprintf_unfiltered |
2336 | (stream, ", address on stack at offset 0x%x (%s)", | |
2337 | info->argloc[1].loc_data.offset, | |
2338 | core_addr_to_string (sp_args + info->argloc[1].loc_data.offset)); | |
dbbb1059 AB |
2339 | } |
2340 | break; | |
2341 | ||
2342 | default: | |
89a3b63e | 2343 | gdb_assert_not_reached (_("unknown argument location type")); |
dbbb1059 AB |
2344 | } |
2345 | } | |
2346 | ||
2347 | /* Implement the push dummy call gdbarch callback. */ | |
2348 | ||
2349 | static CORE_ADDR | |
2350 | riscv_push_dummy_call (struct gdbarch *gdbarch, | |
2351 | struct value *function, | |
2352 | struct regcache *regcache, | |
2353 | CORE_ADDR bp_addr, | |
2354 | int nargs, | |
2355 | struct value **args, | |
2356 | CORE_ADDR sp, | |
2357 | int struct_return, | |
2358 | CORE_ADDR struct_addr) | |
2359 | { | |
2360 | int i; | |
2361 | CORE_ADDR sp_args, sp_refs; | |
2362 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
dbbb1059 AB |
2363 | |
2364 | struct riscv_arg_info *arg_info = | |
2365 | (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info)); | |
dbbb1059 AB |
2366 | |
2367 | struct riscv_call_info call_info (gdbarch); | |
2368 | ||
2369 | CORE_ADDR osp = sp; | |
2370 | ||
2371 | /* We'll use register $a0 if we're returning a struct. */ | |
2372 | if (struct_return) | |
2373 | ++call_info.int_regs.next_regnum; | |
2374 | ||
b926417a | 2375 | for (i = 0; i < nargs; ++i) |
dbbb1059 AB |
2376 | { |
2377 | struct value *arg_value; | |
2378 | struct type *arg_type; | |
b926417a | 2379 | struct riscv_arg_info *info = &arg_info[i]; |
dbbb1059 AB |
2380 | |
2381 | arg_value = args[i]; | |
2382 | arg_type = check_typedef (value_type (arg_value)); | |
2383 | ||
2384 | riscv_arg_location (gdbarch, info, &call_info, arg_type); | |
2385 | ||
2386 | if (info->type != arg_type) | |
2387 | arg_value = value_cast (info->type, arg_value); | |
2388 | info->contents = value_contents (arg_value); | |
2389 | } | |
2390 | ||
2391 | /* Adjust the stack pointer and align it. */ | |
2392 | sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT); | |
2393 | sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT); | |
2394 | ||
2395 | if (riscv_debug_infcall > 0) | |
2396 | { | |
2397 | fprintf_unfiltered (gdb_stdlog, "dummy call args:\n"); | |
2398 | fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n", | |
2399 | (riscv_has_fp_abi (gdbarch) ? "is" : "is not")); | |
2400 | fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n", | |
2401 | call_info.xlen, call_info.flen); | |
2402 | if (struct_return) | |
2403 | fprintf_unfiltered (gdb_stdlog, | |
2404 | "[*] struct return pointer in register $A0\n"); | |
2405 | for (i = 0; i < nargs; ++i) | |
2406 | { | |
2407 | struct riscv_arg_info *info = &arg_info [i]; | |
2408 | ||
2409 | fprintf_unfiltered (gdb_stdlog, "[%2d] ", i); | |
cab5bb9d | 2410 | riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args); |
dbbb1059 AB |
2411 | fprintf_unfiltered (gdb_stdlog, "\n"); |
2412 | } | |
2413 | if (call_info.memory.arg_offset > 0 | |
2414 | || call_info.memory.ref_offset > 0) | |
2415 | { | |
cab5bb9d AB |
2416 | fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n", |
2417 | core_addr_to_string (osp)); | |
dbbb1059 | 2418 | fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n", |
cab5bb9d | 2419 | call_info.memory.arg_offset); |
dbbb1059 | 2420 | fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n", |
cab5bb9d | 2421 | call_info.memory.ref_offset); |
fb294655 AB |
2422 | fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n", |
2423 | core_addr_to_string_nz (osp - sp)); | |
dbbb1059 AB |
2424 | } |
2425 | } | |
2426 | ||
2427 | /* Now load the argument into registers, or onto the stack. */ | |
2428 | ||
2429 | if (struct_return) | |
2430 | { | |
2431 | gdb_byte buf[sizeof (LONGEST)]; | |
2432 | ||
2433 | store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr); | |
b66f5587 | 2434 | regcache->cooked_write (RISCV_A0_REGNUM, buf); |
dbbb1059 AB |
2435 | } |
2436 | ||
2437 | for (i = 0; i < nargs; ++i) | |
2438 | { | |
2439 | CORE_ADDR dst; | |
2440 | int second_arg_length = 0; | |
2441 | const gdb_byte *second_arg_data; | |
2442 | struct riscv_arg_info *info = &arg_info [i]; | |
2443 | ||
2444 | gdb_assert (info->length > 0); | |
2445 | ||
2446 | switch (info->argloc[0].loc_type) | |
2447 | { | |
2448 | case riscv_arg_info::location::in_reg: | |
2449 | { | |
2450 | gdb_byte tmp [sizeof (ULONGEST)]; | |
2451 | ||
2452 | gdb_assert (info->argloc[0].c_length <= info->length); | |
3399f1b3 JW |
2453 | /* FP values in FP registers must be NaN-boxed. */ |
2454 | if (riscv_is_fp_regno_p (info->argloc[0].loc_data.regno) | |
2455 | && info->argloc[0].c_length < call_info.flen) | |
2456 | memset (tmp, -1, sizeof (tmp)); | |
2457 | else | |
2458 | memset (tmp, 0, sizeof (tmp)); | |
dbbb1059 | 2459 | memcpy (tmp, info->contents, info->argloc[0].c_length); |
b66f5587 | 2460 | regcache->cooked_write (info->argloc[0].loc_data.regno, tmp); |
dbbb1059 AB |
2461 | second_arg_length = |
2462 | ((info->argloc[0].c_length < info->length) | |
2463 | ? info->argloc[1].c_length : 0); | |
2464 | second_arg_data = info->contents + info->argloc[1].c_offset; | |
2465 | } | |
2466 | break; | |
2467 | ||
2468 | case riscv_arg_info::location::on_stack: | |
2469 | dst = sp_args + info->argloc[0].loc_data.offset; | |
2470 | write_memory (dst, info->contents, info->length); | |
2471 | second_arg_length = 0; | |
2472 | break; | |
2473 | ||
2474 | case riscv_arg_info::location::by_ref: | |
2475 | dst = sp_refs + info->argloc[0].loc_data.offset; | |
2476 | write_memory (dst, info->contents, info->length); | |
2477 | ||
2478 | second_arg_length = call_info.xlen; | |
2479 | second_arg_data = (gdb_byte *) &dst; | |
2480 | break; | |
2481 | ||
2482 | default: | |
89a3b63e | 2483 | gdb_assert_not_reached (_("unknown argument location type")); |
dbbb1059 AB |
2484 | } |
2485 | ||
2486 | if (second_arg_length > 0) | |
2487 | { | |
2488 | switch (info->argloc[1].loc_type) | |
2489 | { | |
2490 | case riscv_arg_info::location::in_reg: | |
2491 | { | |
2492 | gdb_byte tmp [sizeof (ULONGEST)]; | |
2493 | ||
8c49aa89 AB |
2494 | gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno) |
2495 | && second_arg_length <= call_info.flen) | |
2496 | || second_arg_length <= call_info.xlen); | |
3399f1b3 JW |
2497 | /* FP values in FP registers must be NaN-boxed. */ |
2498 | if (riscv_is_fp_regno_p (info->argloc[1].loc_data.regno) | |
2499 | && second_arg_length < call_info.flen) | |
2500 | memset (tmp, -1, sizeof (tmp)); | |
2501 | else | |
2502 | memset (tmp, 0, sizeof (tmp)); | |
dbbb1059 | 2503 | memcpy (tmp, second_arg_data, second_arg_length); |
b66f5587 | 2504 | regcache->cooked_write (info->argloc[1].loc_data.regno, tmp); |
dbbb1059 AB |
2505 | } |
2506 | break; | |
2507 | ||
2508 | case riscv_arg_info::location::on_stack: | |
2509 | { | |
2510 | CORE_ADDR arg_addr; | |
2511 | ||
2512 | arg_addr = sp_args + info->argloc[1].loc_data.offset; | |
2513 | write_memory (arg_addr, second_arg_data, second_arg_length); | |
2514 | break; | |
2515 | } | |
2516 | ||
2517 | case riscv_arg_info::location::by_ref: | |
2518 | default: | |
2519 | /* The second location should never be a reference, any | |
2520 | argument being passed by reference just places its address | |
2521 | in the first location and is done. */ | |
2522 | error (_("invalid argument location")); | |
2523 | break; | |
2524 | } | |
2525 | } | |
2526 | } | |
2527 | ||
2528 | /* Set the dummy return value to bp_addr. | |
2529 | A dummy breakpoint will be setup to execute the call. */ | |
2530 | ||
2531 | if (riscv_debug_infcall > 0) | |
cab5bb9d AB |
2532 | fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n", |
2533 | core_addr_to_string (bp_addr)); | |
dbbb1059 AB |
2534 | regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr); |
2535 | ||
2536 | /* Finally, update the stack pointer. */ | |
2537 | ||
2538 | if (riscv_debug_infcall > 0) | |
cab5bb9d AB |
2539 | fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n", |
2540 | core_addr_to_string (sp)); | |
dbbb1059 AB |
2541 | regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp); |
2542 | ||
2543 | return sp; | |
2544 | } | |
2545 | ||
2546 | /* Implement the return_value gdbarch method. */ | |
2547 | ||
2548 | static enum return_value_convention | |
2549 | riscv_return_value (struct gdbarch *gdbarch, | |
2550 | struct value *function, | |
2551 | struct type *type, | |
2552 | struct regcache *regcache, | |
2553 | gdb_byte *readbuf, | |
2554 | const gdb_byte *writebuf) | |
2555 | { | |
dbbb1059 AB |
2556 | struct riscv_call_info call_info (gdbarch); |
2557 | struct riscv_arg_info info; | |
2558 | struct type *arg_type; | |
2559 | ||
2560 | arg_type = check_typedef (type); | |
2561 | riscv_arg_location (gdbarch, &info, &call_info, arg_type); | |
2562 | ||
2563 | if (riscv_debug_infcall > 0) | |
2564 | { | |
2565 | fprintf_unfiltered (gdb_stdlog, "riscv return value:\n"); | |
2566 | fprintf_unfiltered (gdb_stdlog, "[R] "); | |
cab5bb9d | 2567 | riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0); |
dbbb1059 AB |
2568 | fprintf_unfiltered (gdb_stdlog, "\n"); |
2569 | } | |
2570 | ||
2571 | if (readbuf != nullptr || writebuf != nullptr) | |
2572 | { | |
2573 | int regnum; | |
2574 | ||
2575 | switch (info.argloc[0].loc_type) | |
2576 | { | |
2577 | /* Return value in register(s). */ | |
2578 | case riscv_arg_info::location::in_reg: | |
2579 | { | |
2580 | regnum = info.argloc[0].loc_data.regno; | |
2581 | ||
2582 | if (readbuf) | |
dca08e1f | 2583 | regcache->cooked_read (regnum, readbuf); |
dbbb1059 AB |
2584 | |
2585 | if (writebuf) | |
b66f5587 | 2586 | regcache->cooked_write (regnum, writebuf); |
dbbb1059 AB |
2587 | |
2588 | /* A return value in register can have a second part in a | |
2589 | second register. */ | |
2590 | if (info.argloc[0].c_length < info.length) | |
2591 | { | |
2592 | switch (info.argloc[1].loc_type) | |
2593 | { | |
2594 | case riscv_arg_info::location::in_reg: | |
2595 | regnum = info.argloc[1].loc_data.regno; | |
2596 | ||
2597 | if (readbuf) | |
2598 | { | |
2599 | readbuf += info.argloc[1].c_offset; | |
dca08e1f | 2600 | regcache->cooked_read (regnum, readbuf); |
dbbb1059 AB |
2601 | } |
2602 | ||
2603 | if (writebuf) | |
2604 | { | |
2605 | writebuf += info.argloc[1].c_offset; | |
b66f5587 | 2606 | regcache->cooked_write (regnum, writebuf); |
dbbb1059 AB |
2607 | } |
2608 | break; | |
2609 | ||
2610 | case riscv_arg_info::location::by_ref: | |
2611 | case riscv_arg_info::location::on_stack: | |
2612 | default: | |
2613 | error (_("invalid argument location")); | |
2614 | break; | |
2615 | } | |
2616 | } | |
2617 | } | |
2618 | break; | |
2619 | ||
2620 | /* Return value by reference will have its address in A0. */ | |
2621 | case riscv_arg_info::location::by_ref: | |
2622 | { | |
b2970c23 | 2623 | ULONGEST addr; |
dbbb1059 AB |
2624 | |
2625 | regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM, | |
2626 | &addr); | |
2627 | if (readbuf != nullptr) | |
2628 | read_memory (addr, readbuf, info.length); | |
2629 | if (writebuf != nullptr) | |
2630 | write_memory (addr, writebuf, info.length); | |
2631 | } | |
2632 | break; | |
2633 | ||
2634 | case riscv_arg_info::location::on_stack: | |
2635 | default: | |
2636 | error (_("invalid argument location")); | |
2637 | break; | |
2638 | } | |
2639 | } | |
2640 | ||
2641 | switch (info.argloc[0].loc_type) | |
2642 | { | |
2643 | case riscv_arg_info::location::in_reg: | |
2644 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2645 | case riscv_arg_info::location::by_ref: | |
2646 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2647 | case riscv_arg_info::location::on_stack: | |
2648 | default: | |
2649 | error (_("invalid argument location")); | |
2650 | } | |
2651 | } | |
2652 | ||
2653 | /* Implement the frame_align gdbarch method. */ | |
2654 | ||
2655 | static CORE_ADDR | |
2656 | riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2657 | { | |
2658 | return align_down (addr, 16); | |
2659 | } | |
2660 | ||
2661 | /* Implement the unwind_pc gdbarch method. */ | |
2662 | ||
2663 | static CORE_ADDR | |
2664 | riscv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2665 | { | |
2666 | return frame_unwind_register_unsigned (next_frame, RISCV_PC_REGNUM); | |
2667 | } | |
2668 | ||
2669 | /* Implement the unwind_sp gdbarch method. */ | |
2670 | ||
2671 | static CORE_ADDR | |
2672 | riscv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2673 | { | |
2674 | return frame_unwind_register_unsigned (next_frame, RISCV_SP_REGNUM); | |
2675 | } | |
2676 | ||
2677 | /* Implement the dummy_id gdbarch method. */ | |
2678 | ||
2679 | static struct frame_id | |
2680 | riscv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
2681 | { | |
2682 | return frame_id_build (get_frame_register_signed (this_frame, RISCV_SP_REGNUM), | |
2683 | get_frame_pc (this_frame)); | |
2684 | } | |
2685 | ||
2686 | /* Generate, or return the cached frame cache for the RiscV frame | |
2687 | unwinder. */ | |
2688 | ||
78a3b0fa | 2689 | static struct riscv_unwind_cache * |
dbbb1059 AB |
2690 | riscv_frame_cache (struct frame_info *this_frame, void **this_cache) |
2691 | { | |
78a3b0fa AB |
2692 | CORE_ADDR pc, start_addr; |
2693 | struct riscv_unwind_cache *cache; | |
dbbb1059 | 2694 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
78a3b0fa | 2695 | int numregs, regno; |
dbbb1059 AB |
2696 | |
2697 | if ((*this_cache) != NULL) | |
78a3b0fa | 2698 | return (struct riscv_unwind_cache *) *this_cache; |
dbbb1059 | 2699 | |
78a3b0fa AB |
2700 | cache = FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache); |
2701 | cache->regs = trad_frame_alloc_saved_regs (this_frame); | |
2702 | (*this_cache) = cache; | |
dbbb1059 | 2703 | |
78a3b0fa AB |
2704 | /* Scan the prologue, filling in the cache. */ |
2705 | start_addr = get_frame_func (this_frame); | |
dbbb1059 | 2706 | pc = get_frame_pc (this_frame); |
78a3b0fa AB |
2707 | riscv_scan_prologue (gdbarch, start_addr, pc, cache); |
2708 | ||
2709 | /* We can now calculate the frame base address. */ | |
2710 | cache->frame_base | |
6c9d681b AB |
2711 | = (get_frame_register_signed (this_frame, cache->frame_base_reg) |
2712 | + cache->frame_base_offset); | |
78a3b0fa AB |
2713 | if (riscv_debug_unwinder) |
2714 | fprintf_unfiltered (gdb_stdlog, "Frame base is %s ($%s + 0x%x)\n", | |
2715 | core_addr_to_string (cache->frame_base), | |
2716 | gdbarch_register_name (gdbarch, | |
2717 | cache->frame_base_reg), | |
2718 | cache->frame_base_offset); | |
2719 | ||
2720 | /* The prologue scanner sets the address of registers stored to the stack | |
2721 | as the offset of that register from the frame base. The prologue | |
2722 | scanner doesn't know the actual frame base value, and so is unable to | |
2723 | compute the exact address. We do now know the frame base value, so | |
2724 | update the address of registers stored to the stack. */ | |
2725 | numregs = gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); | |
2726 | for (regno = 0; regno < numregs; ++regno) | |
2727 | { | |
2728 | if (trad_frame_addr_p (cache->regs, regno)) | |
2729 | cache->regs[regno].addr += cache->frame_base; | |
2730 | } | |
2731 | ||
2732 | /* The previous $pc can be found wherever the $ra value can be found. | |
2733 | The previous $ra value is gone, this would have been stored be the | |
2734 | previous frame if required. */ | |
2735 | cache->regs[gdbarch_pc_regnum (gdbarch)] = cache->regs[RISCV_RA_REGNUM]; | |
2736 | trad_frame_set_unknown (cache->regs, RISCV_RA_REGNUM); | |
2737 | ||
2738 | /* Build the frame id. */ | |
2739 | cache->this_id = frame_id_build (cache->frame_base, start_addr); | |
dbbb1059 | 2740 | |
78a3b0fa AB |
2741 | /* The previous $sp value is the frame base value. */ |
2742 | trad_frame_set_value (cache->regs, gdbarch_sp_regnum (gdbarch), | |
2743 | cache->frame_base); | |
dbbb1059 | 2744 | |
78a3b0fa | 2745 | return cache; |
dbbb1059 AB |
2746 | } |
2747 | ||
2748 | /* Implement the this_id callback for RiscV frame unwinder. */ | |
2749 | ||
2750 | static void | |
2751 | riscv_frame_this_id (struct frame_info *this_frame, | |
2752 | void **prologue_cache, | |
2753 | struct frame_id *this_id) | |
2754 | { | |
78a3b0fa | 2755 | struct riscv_unwind_cache *cache; |
dbbb1059 | 2756 | |
17cf2897 AB |
2757 | TRY |
2758 | { | |
2759 | cache = riscv_frame_cache (this_frame, prologue_cache); | |
2760 | *this_id = cache->this_id; | |
2761 | } | |
2762 | CATCH (ex, RETURN_MASK_ERROR) | |
2763 | { | |
2764 | /* Ignore errors, this leaves the frame id as the predefined outer | |
2765 | frame id which terminates the backtrace at this point. */ | |
2766 | } | |
2767 | END_CATCH | |
dbbb1059 AB |
2768 | } |
2769 | ||
2770 | /* Implement the prev_register callback for RiscV frame unwinder. */ | |
2771 | ||
2772 | static struct value * | |
2773 | riscv_frame_prev_register (struct frame_info *this_frame, | |
2774 | void **prologue_cache, | |
2775 | int regnum) | |
2776 | { | |
78a3b0fa | 2777 | struct riscv_unwind_cache *cache; |
dbbb1059 | 2778 | |
78a3b0fa AB |
2779 | cache = riscv_frame_cache (this_frame, prologue_cache); |
2780 | return trad_frame_get_prev_register (this_frame, cache->regs, regnum); | |
dbbb1059 AB |
2781 | } |
2782 | ||
2783 | /* Structure defining the RiscV normal frame unwind functions. Since we | |
2784 | are the fallback unwinder (DWARF unwinder is used first), we use the | |
2785 | default frame sniffer, which always accepts the frame. */ | |
2786 | ||
2787 | static const struct frame_unwind riscv_frame_unwind = | |
2788 | { | |
2789 | /*.type =*/ NORMAL_FRAME, | |
2790 | /*.stop_reason =*/ default_frame_unwind_stop_reason, | |
2791 | /*.this_id =*/ riscv_frame_this_id, | |
2792 | /*.prev_register =*/ riscv_frame_prev_register, | |
2793 | /*.unwind_data =*/ NULL, | |
2794 | /*.sniffer =*/ default_frame_sniffer, | |
2795 | /*.dealloc_cache =*/ NULL, | |
2796 | /*.prev_arch =*/ NULL, | |
2797 | }; | |
2798 | ||
2799 | /* Initialize the current architecture based on INFO. If possible, | |
2800 | re-use an architecture from ARCHES, which is a list of | |
2801 | architectures already created during this debugging session. | |
2802 | ||
2803 | Called e.g. at program startup, when reading a core file, and when | |
2804 | reading a binary file. */ | |
2805 | ||
2806 | static struct gdbarch * | |
2807 | riscv_gdbarch_init (struct gdbarch_info info, | |
2808 | struct gdbarch_list *arches) | |
2809 | { | |
2810 | struct gdbarch *gdbarch; | |
2811 | struct gdbarch_tdep *tdep; | |
2812 | struct gdbarch_tdep tmp_tdep; | |
dbbb1059 AB |
2813 | int i; |
2814 | ||
2815 | /* Ideally, we'd like to get as much information from the target for | |
2816 | things like register size, and whether the target has floating point | |
2817 | hardware. However, there are some things that the target can't tell | |
2818 | us, like, what ABI is being used. | |
2819 | ||
2820 | So, for now, we take as much information as possible from the ELF, | |
2821 | including things like register size, and FP hardware support, along | |
2822 | with information about the ABI. | |
2823 | ||
2824 | Information about this target is built up in TMP_TDEP, and then we | |
2825 | look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no | |
2826 | match is found we'll create a new gdbarch and copy TMP_TDEP over. */ | |
2827 | memset (&tmp_tdep, 0, sizeof (tmp_tdep)); | |
2828 | ||
2829 | if (info.abfd != NULL | |
2830 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
2831 | { | |
2832 | unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS]; | |
2833 | int e_flags = elf_elfheader (info.abfd)->e_flags; | |
2834 | ||
2835 | if (eclass == ELFCLASS32) | |
2836 | tmp_tdep.abi.fields.base_len = 1; | |
2837 | else if (eclass == ELFCLASS64) | |
2838 | tmp_tdep.abi.fields.base_len = 2; | |
2839 | else | |
2840 | internal_error (__FILE__, __LINE__, | |
2841 | _("unknown ELF header class %d"), eclass); | |
2842 | ||
2843 | if (e_flags & EF_RISCV_RVC) | |
27724bad | 2844 | tmp_tdep.core_features |= (1 << ('C' - 'A')); |
dbbb1059 AB |
2845 | |
2846 | if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE) | |
2847 | { | |
2848 | tmp_tdep.abi.fields.float_abi = 2; | |
2849 | tmp_tdep.core_features |= (1 << ('D' - 'A')); | |
2850 | tmp_tdep.core_features |= (1 << ('F' - 'A')); | |
2851 | } | |
2852 | else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE) | |
2853 | { | |
2854 | tmp_tdep.abi.fields.float_abi = 1; | |
2855 | tmp_tdep.core_features |= (1 << ('F' - 'A')); | |
2856 | } | |
2857 | } | |
2858 | else | |
2859 | { | |
2860 | const struct bfd_arch_info *binfo = info.bfd_arch_info; | |
2861 | ||
2862 | if (binfo->bits_per_word == 32) | |
2863 | tmp_tdep.abi.fields.base_len = 1; | |
2864 | else if (binfo->bits_per_word == 64) | |
2865 | tmp_tdep.abi.fields.base_len = 2; | |
2866 | else | |
2867 | internal_error (__FILE__, __LINE__, _("unknown bits_per_word %d"), | |
2868 | binfo->bits_per_word); | |
2869 | } | |
2870 | ||
2871 | /* Find a candidate among the list of pre-declared architectures. */ | |
2872 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
2873 | arches != NULL; | |
2874 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
2875 | if (gdbarch_tdep (arches->gdbarch)->abi.value == tmp_tdep.abi.value) | |
2876 | return arches->gdbarch; | |
2877 | ||
2878 | /* None found, so create a new architecture from the information provided. */ | |
2879 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof *tdep); | |
2880 | gdbarch = gdbarch_alloc (&info, tdep); | |
2881 | memcpy (tdep, &tmp_tdep, sizeof (tmp_tdep)); | |
2882 | ||
2883 | /* Target data types. */ | |
2884 | set_gdbarch_short_bit (gdbarch, 16); | |
2885 | set_gdbarch_int_bit (gdbarch, 32); | |
2886 | set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8); | |
2887 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2888 | set_gdbarch_float_bit (gdbarch, 32); | |
2889 | set_gdbarch_double_bit (gdbarch, 64); | |
2890 | set_gdbarch_long_double_bit (gdbarch, 128); | |
2891 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); | |
2892 | set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8); | |
2893 | set_gdbarch_char_signed (gdbarch, 0); | |
2894 | ||
2895 | /* Information about the target architecture. */ | |
2896 | set_gdbarch_return_value (gdbarch, riscv_return_value); | |
2897 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc); | |
2898 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind); | |
5a77b1b4 | 2899 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
dbbb1059 AB |
2900 | |
2901 | /* Register architecture. */ | |
dbbb1059 | 2902 | set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1); |
dbbb1059 AB |
2903 | set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM); |
2904 | set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM); | |
2905 | set_gdbarch_ps_regnum (gdbarch, RISCV_FP_REGNUM); | |
2906 | set_gdbarch_deprecated_fp_regnum (gdbarch, RISCV_FP_REGNUM); | |
2907 | ||
2908 | /* Functions to supply register information. */ | |
2909 | set_gdbarch_register_name (gdbarch, riscv_register_name); | |
2910 | set_gdbarch_register_type (gdbarch, riscv_register_type); | |
2911 | set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info); | |
2912 | set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p); | |
2913 | ||
2914 | /* Functions to analyze frames. */ | |
dbbb1059 AB |
2915 | set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue); |
2916 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2917 | set_gdbarch_frame_align (gdbarch, riscv_frame_align); | |
2918 | ||
2919 | /* Functions to access frame data. */ | |
2920 | set_gdbarch_unwind_pc (gdbarch, riscv_unwind_pc); | |
2921 | set_gdbarch_unwind_sp (gdbarch, riscv_unwind_sp); | |
2922 | ||
2923 | /* Functions handling dummy frames. */ | |
2924 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
2925 | set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code); | |
2926 | set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call); | |
2927 | set_gdbarch_dummy_id (gdbarch, riscv_dummy_id); | |
2928 | ||
2929 | /* Frame unwinders. Use DWARF debug info if available, otherwise use our own | |
2930 | unwinder. */ | |
2931 | dwarf2_append_unwinders (gdbarch); | |
2932 | frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind); | |
2933 | ||
dbbb1059 AB |
2934 | for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) |
2935 | user_reg_add (gdbarch, riscv_register_aliases[i].name, | |
2936 | value_of_riscv_user_reg, &riscv_register_aliases[i].regnum); | |
2937 | ||
117a0e99 JW |
2938 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
2939 | gdbarch_init_osabi (info, gdbarch); | |
2940 | ||
dbbb1059 AB |
2941 | return gdbarch; |
2942 | } | |
2943 | ||
5c720ed8 JW |
2944 | /* This decodes the current instruction and determines the address of the |
2945 | next instruction. */ | |
2946 | ||
2947 | static CORE_ADDR | |
2948 | riscv_next_pc (struct regcache *regcache, CORE_ADDR pc) | |
2949 | { | |
2950 | struct gdbarch *gdbarch = regcache->arch (); | |
2951 | struct riscv_insn insn; | |
2952 | CORE_ADDR next_pc; | |
2953 | ||
2954 | insn.decode (gdbarch, pc); | |
2955 | next_pc = pc + insn.length (); | |
2956 | ||
2957 | if (insn.opcode () == riscv_insn::JAL) | |
2958 | next_pc = pc + insn.imm_signed (); | |
2959 | else if (insn.opcode () == riscv_insn::JALR) | |
2960 | { | |
2961 | LONGEST source; | |
2962 | regcache->cooked_read (insn.rs1 (), &source); | |
2963 | next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR) 0x1; | |
2964 | } | |
2965 | else if (insn.opcode () == riscv_insn::BEQ) | |
2966 | { | |
2967 | LONGEST src1, src2; | |
2968 | regcache->cooked_read (insn.rs1 (), &src1); | |
2969 | regcache->cooked_read (insn.rs2 (), &src2); | |
2970 | if (src1 == src2) | |
2971 | next_pc = pc + insn.imm_signed (); | |
2972 | } | |
2973 | else if (insn.opcode () == riscv_insn::BNE) | |
2974 | { | |
2975 | LONGEST src1, src2; | |
2976 | regcache->cooked_read (insn.rs1 (), &src1); | |
2977 | regcache->cooked_read (insn.rs2 (), &src2); | |
2978 | if (src1 != src2) | |
2979 | next_pc = pc + insn.imm_signed (); | |
2980 | } | |
2981 | else if (insn.opcode () == riscv_insn::BLT) | |
2982 | { | |
2983 | LONGEST src1, src2; | |
2984 | regcache->cooked_read (insn.rs1 (), &src1); | |
2985 | regcache->cooked_read (insn.rs2 (), &src2); | |
2986 | if (src1 < src2) | |
2987 | next_pc = pc + insn.imm_signed (); | |
2988 | } | |
2989 | else if (insn.opcode () == riscv_insn::BGE) | |
2990 | { | |
2991 | LONGEST src1, src2; | |
2992 | regcache->cooked_read (insn.rs1 (), &src1); | |
2993 | regcache->cooked_read (insn.rs2 (), &src2); | |
2994 | if (src1 >= src2) | |
2995 | next_pc = pc + insn.imm_signed (); | |
2996 | } | |
2997 | else if (insn.opcode () == riscv_insn::BLTU) | |
2998 | { | |
2999 | ULONGEST src1, src2; | |
3000 | regcache->cooked_read (insn.rs1 (), &src1); | |
3001 | regcache->cooked_read (insn.rs2 (), &src2); | |
3002 | if (src1 < src2) | |
3003 | next_pc = pc + insn.imm_signed (); | |
3004 | } | |
3005 | else if (insn.opcode () == riscv_insn::BGEU) | |
3006 | { | |
3007 | ULONGEST src1, src2; | |
3008 | regcache->cooked_read (insn.rs1 (), &src1); | |
3009 | regcache->cooked_read (insn.rs2 (), &src2); | |
3010 | if (src1 >= src2) | |
3011 | next_pc = pc + insn.imm_signed (); | |
3012 | } | |
3013 | ||
3014 | return next_pc; | |
3015 | } | |
3016 | ||
3017 | /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look | |
3018 | for the end of the sequence and put the breakpoint there. */ | |
3019 | ||
3020 | static bool | |
3021 | riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc, | |
3022 | CORE_ADDR *next_pc) | |
3023 | { | |
3024 | struct gdbarch *gdbarch = regcache->arch (); | |
3025 | struct riscv_insn insn; | |
3026 | CORE_ADDR cur_step_pc = pc; | |
3027 | CORE_ADDR last_addr = 0; | |
3028 | ||
3029 | /* First instruction has to be a load reserved. */ | |
3030 | insn.decode (gdbarch, cur_step_pc); | |
3031 | if (insn.opcode () != riscv_insn::LR) | |
3032 | return false; | |
3033 | cur_step_pc = cur_step_pc + insn.length (); | |
3034 | ||
3035 | /* Next instruction should be branch to exit. */ | |
3036 | insn.decode (gdbarch, cur_step_pc); | |
3037 | if (insn.opcode () != riscv_insn::BNE) | |
3038 | return false; | |
3039 | last_addr = cur_step_pc + insn.imm_signed (); | |
3040 | cur_step_pc = cur_step_pc + insn.length (); | |
3041 | ||
3042 | /* Next instruction should be store conditional. */ | |
3043 | insn.decode (gdbarch, cur_step_pc); | |
3044 | if (insn.opcode () != riscv_insn::SC) | |
3045 | return false; | |
3046 | cur_step_pc = cur_step_pc + insn.length (); | |
3047 | ||
3048 | /* Next instruction should be branch to start. */ | |
3049 | insn.decode (gdbarch, cur_step_pc); | |
3050 | if (insn.opcode () != riscv_insn::BNE) | |
3051 | return false; | |
3052 | if (pc != (cur_step_pc + insn.imm_signed ())) | |
3053 | return false; | |
3054 | cur_step_pc = cur_step_pc + insn.length (); | |
3055 | ||
3056 | /* We should now be at the end of the sequence. */ | |
3057 | if (cur_step_pc != last_addr) | |
3058 | return false; | |
3059 | ||
3060 | *next_pc = cur_step_pc; | |
3061 | return true; | |
3062 | } | |
3063 | ||
3064 | /* This is called just before we want to resume the inferior, if we want to | |
3065 | single-step it but there is no hardware or kernel single-step support. We | |
3066 | find the target of the coming instruction and breakpoint it. */ | |
3067 | ||
3068 | std::vector<CORE_ADDR> | |
3069 | riscv_software_single_step (struct regcache *regcache) | |
3070 | { | |
3071 | CORE_ADDR pc, next_pc; | |
3072 | ||
3073 | pc = regcache_read_pc (regcache); | |
3074 | ||
3075 | if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc)) | |
3076 | return {next_pc}; | |
3077 | ||
3078 | next_pc = riscv_next_pc (regcache, pc); | |
3079 | ||
3080 | return {next_pc}; | |
3081 | } | |
3082 | ||
dbbb1059 AB |
3083 | void |
3084 | _initialize_riscv_tdep (void) | |
3085 | { | |
3086 | gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL); | |
3087 | ||
dbbb1059 AB |
3088 | /* Add root prefix command for all "set debug riscv" and "show debug |
3089 | riscv" commands. */ | |
3090 | add_prefix_cmd ("riscv", no_class, set_debug_riscv_command, | |
3091 | _("RISC-V specific debug commands."), | |
3092 | &setdebugriscvcmdlist, "set debug riscv ", 0, | |
3093 | &setdebuglist); | |
3094 | ||
3095 | add_prefix_cmd ("riscv", no_class, show_debug_riscv_command, | |
3096 | _("RISC-V specific debug commands."), | |
3097 | &showdebugriscvcmdlist, "show debug riscv ", 0, | |
3098 | &showdebuglist); | |
3099 | ||
f37bc8b1 JB |
3100 | add_setshow_zuinteger_cmd ("breakpoints", class_maintenance, |
3101 | &riscv_debug_breakpoints, _("\ | |
3102 | Set riscv breakpoint debugging."), _("\ | |
3103 | Show riscv breakpoint debugging."), _("\ | |
3104 | When non-zero, print debugging information for the riscv specific parts\n\ | |
3105 | of the breakpoint mechanism."), | |
3106 | NULL, | |
3107 | show_riscv_debug_variable, | |
3108 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); | |
3109 | ||
dbbb1059 AB |
3110 | add_setshow_zuinteger_cmd ("infcall", class_maintenance, |
3111 | &riscv_debug_infcall, _("\ | |
3112 | Set riscv inferior call debugging."), _("\ | |
3113 | Show riscv inferior call debugging."), _("\ | |
3114 | When non-zero, print debugging information for the riscv specific parts\n\ | |
3115 | of the inferior call mechanism."), | |
3116 | NULL, | |
3117 | show_riscv_debug_variable, | |
3118 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); | |
78a3b0fa AB |
3119 | |
3120 | add_setshow_zuinteger_cmd ("unwinder", class_maintenance, | |
3121 | &riscv_debug_unwinder, _("\ | |
3122 | Set riscv stack unwinding debugging."), _("\ | |
3123 | Show riscv stack unwinding debugging."), _("\ | |
3124 | When non-zero, print debugging information for the riscv specific parts\n\ | |
3125 | of the stack unwinding mechanism."), | |
3126 | NULL, | |
3127 | show_riscv_debug_variable, | |
3128 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); | |
dbbb1059 AB |
3129 | |
3130 | /* Add root prefix command for all "set riscv" and "show riscv" commands. */ | |
3131 | add_prefix_cmd ("riscv", no_class, set_riscv_command, | |
3132 | _("RISC-V specific commands."), | |
3133 | &setriscvcmdlist, "set riscv ", 0, &setlist); | |
3134 | ||
3135 | add_prefix_cmd ("riscv", no_class, show_riscv_command, | |
3136 | _("RISC-V specific commands."), | |
3137 | &showriscvcmdlist, "show riscv ", 0, &showlist); | |
3138 | ||
3139 | ||
3140 | use_compressed_breakpoints = AUTO_BOOLEAN_AUTO; | |
3141 | add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class, | |
3142 | &use_compressed_breakpoints, | |
3143 | _("\ | |
3144 | Set debugger's use of compressed breakpoints."), _(" \ | |
3145 | Show debugger's use of compressed breakpoints."), _("\ | |
f37bc8b1 JB |
3146 | Debugging compressed code requires compressed breakpoints to be used. If\n\ |
3147 | left to 'auto' then gdb will use them if the existing instruction is a\n\ | |
3148 | compressed instruction. If that doesn't give the correct behavior, then\n\ | |
3149 | this option can be used."), | |
dbbb1059 AB |
3150 | NULL, |
3151 | show_use_compressed_breakpoints, | |
3152 | &setriscvcmdlist, | |
3153 | &showriscvcmdlist); | |
3154 | } |