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[deliverable/binutils-gdb.git] / gdb / riscv-tdep.c
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dbbb1059
AB		 1/* Target-dependent code for the RISC-V architecture, for GDB.
2
3 Copyright (C) 2018 Free Software Foundation, Inc.
4
dbbb1059
AB		 5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20#include "defs.h"
21#include "frame.h"
22#include "inferior.h"
23#include "symtab.h"
24#include "value.h"
25#include "gdbcmd.h"
26#include "language.h"
27#include "gdbcore.h"
28#include "symfile.h"
29#include "objfiles.h"
30#include "gdbtypes.h"
31#include "target.h"
32#include "arch-utils.h"
33#include "regcache.h"
34#include "osabi.h"
35#include "riscv-tdep.h"
36#include "block.h"
37#include "reggroups.h"
38#include "opcode/riscv.h"
39#include "elf/riscv.h"
40#include "elf-bfd.h"
41#include "symcat.h"
42#include "dis-asm.h"
43#include "frame-unwind.h"
44#include "frame-base.h"
45#include "trad-frame.h"
46#include "infcall.h"
47#include "floatformat.h"
48#include "remote.h"
49#include "target-descriptions.h"
50#include "dwarf2-frame.h"
51#include "user-regs.h"
52#include "valprint.h"
53#include "common-defs.h"
54#include "opcode/riscv-opc.h"
55#include "cli/cli-decode.h"
76727919 56#include "observable.h"
78a3b0fa 57#include "prologue-value.h"
dbbb1059
AB		 58
59/* The stack must be 16-byte aligned. */
60#define SP_ALIGNMENT 16
61
62/* Forward declarations. */
63static bool riscv_has_feature (struct gdbarch *gdbarch, char feature);
dbbb1059
AB		 64
65/* Define a series of is_XXX_insn functions to check if the value INSN
66 is an instance of instruction XXX. */
67#define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
68static inline bool is_ ## INSN_NAME ## _insn (long insn) \
69{ \
70 return (insn & INSN_MASK) == INSN_MATCH; \
71}
72#include "opcode/riscv-opc.h"
73#undef DECLARE_INSN
74
78a3b0fa
AB		 75/* Cached information about a frame. */
76
77struct riscv_unwind_cache
78{
79 /* The register from which we can calculate the frame base. This is
80 usually $sp or $fp. */
81 int frame_base_reg;
82
83 /* The offset from the current value in register FRAME_BASE_REG to the
84 actual frame base address. */
85 int frame_base_offset;
86
87 /* Information about previous register values. */
88 struct trad_frame_saved_reg *regs;
89
90 /* The id for this frame. */
91 struct frame_id this_id;
92
93 /* The base (stack) address for this frame. This is the stack pointer
94 value on entry to this frame before any adjustments are made. */
95 CORE_ADDR frame_base;
96};
97
dbbb1059
AB		 98/* Architectural name for core registers. */
99
100static const char * const riscv_gdb_reg_names[RISCV_LAST_FP_REGNUM + 1] =
101{
102 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
103 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
104 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
105 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
106 "pc",
107 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
108 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
109 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
110 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
111};
112
113/* Maps "pretty" register names onto their GDB register number. */
114
115struct register_alias
116{
117 /* The register alias. Usually more descriptive than the
118 architectural name of the register. */
119 const char *name;
120
121 /* The GDB register number. */
122 int regnum;
123};
124
125/* Table of register aliases. */
126
127static const struct register_alias riscv_register_aliases[] =
128{
129 { "zero", 0 },
130 { "ra", 1 },
131 { "sp", 2 },
132 { "gp", 3 },
133 { "tp", 4 },
134 { "t0", 5 },
135 { "t1", 6 },
136 { "t2", 7 },
dbbb1059 137 { "s0", 8 },
41823f29 138 { "fp", 8 },
dbbb1059
AB		 139 { "s1", 9 },
140 { "a0", 10 },
141 { "a1", 11 },
142 { "a2", 12 },
143 { "a3", 13 },
144 { "a4", 14 },
145 { "a5", 15 },
146 { "a6", 16 },
147 { "a7", 17 },
148 { "s2", 18 },
149 { "s3", 19 },
150 { "s4", 20 },
151 { "s5", 21 },
152 { "s6", 22 },
153 { "s7", 23 },
154 { "s8", 24 },
155 { "s9", 25 },
156 { "s10", 26 },
157 { "s11", 27 },
158 { "t3", 28 },
159 { "t4", 29 },
160 { "t5", 30 },
161 { "t6", 31 },
162 /* pc is 32. */
163 { "ft0", 33 },
164 { "ft1", 34 },
165 { "ft2", 35 },
166 { "ft3", 36 },
167 { "ft4", 37 },
168 { "ft5", 38 },
169 { "ft6", 39 },
170 { "ft7", 40 },
171 { "fs0", 41 },
172 { "fs1", 42 },
173 { "fa0", 43 },
174 { "fa1", 44 },
175 { "fa2", 45 },
176 { "fa3", 46 },
177 { "fa4", 47 },
178 { "fa5", 48 },
179 { "fa6", 49 },
180 { "fa7", 50 },
181 { "fs2", 51 },
182 { "fs3", 52 },
183 { "fs4", 53 },
184 { "fs5", 54 },
185 { "fs6", 55 },
186 { "fs7", 56 },
187 { "fs8", 57 },
188 { "fs9", 58 },
189 { "fs10", 59 },
190 { "fs11", 60 },
191 { "ft8", 61 },
192 { "ft9", 62 },
193 { "ft10", 63 },
194 { "ft11", 64 },
195#define DECLARE_CSR(name, num) { #name, (num) + 65 },
196#include "opcode/riscv-opc.h"
197#undef DECLARE_CSR
198};
199
200/* Controls whether we place compressed breakpoints or not. When in auto
201 mode GDB tries to determine if the target supports compressed
202 breakpoints, and uses them if it does. */
203
204static enum auto_boolean use_compressed_breakpoints;
205
206/* The show callback for 'show riscv use-compressed-breakpoints'. */
207
208static void
209show_use_compressed_breakpoints (struct ui_file *file, int from_tty,
210 struct cmd_list_element *c,
211 const char *value)
212{
213 const char *additional_info;
214 struct gdbarch *gdbarch = target_gdbarch ();
215
216 if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO)
217 if (riscv_has_feature (gdbarch, 'C'))
218 additional_info = _(" (currently on)");
219 else
220 additional_info = _(" (currently off)");
221 else
222 additional_info = "";
223
224 fprintf_filtered (file,
225 _("Debugger's use of compressed breakpoints is set "
226 "to %s%s.\n"), value, additional_info);
227}
228
229/* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
230
231static struct cmd_list_element *setriscvcmdlist = NULL;
232static struct cmd_list_element *showriscvcmdlist = NULL;
233
234/* The show callback for the 'show riscv' prefix command. */
235
236static void
237show_riscv_command (const char *args, int from_tty)
238{
239 help_list (showriscvcmdlist, "show riscv ", all_commands, gdb_stdout);
240}
241
242/* The set callback for the 'set riscv' prefix command. */
243
244static void
245set_riscv_command (const char *args, int from_tty)
246{
247 printf_unfiltered
248 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
249 help_list (setriscvcmdlist, "set riscv ", all_commands, gdb_stdout);
250}
251
252/* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
253
254static struct cmd_list_element *setdebugriscvcmdlist = NULL;
255static struct cmd_list_element *showdebugriscvcmdlist = NULL;
256
257/* The show callback for the 'show debug riscv' prefix command. */
258
259static void
260show_debug_riscv_command (const char *args, int from_tty)
261{
262 help_list (showdebugriscvcmdlist, "show debug riscv ", all_commands, gdb_stdout);
263}
264
265/* The set callback for the 'set debug riscv' prefix command. */
266
267static void
268set_debug_riscv_command (const char *args, int from_tty)
269{
270 printf_unfiltered
271 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
272 help_list (setdebugriscvcmdlist, "set debug riscv ", all_commands, gdb_stdout);
273}
274
275/* The show callback for all 'show debug riscv VARNAME' variables. */
276
277static void
278show_riscv_debug_variable (struct ui_file *file, int from_tty,
279 struct cmd_list_element *c,
280 const char *value)
281{
282 fprintf_filtered (file,
283 _("RiscV debug variable `%s' is set to: %s\n"),
284 c->name, value);
285}
286
287/* When this is set to non-zero debugging information about inferior calls
288 will be printed. */
289
290static unsigned int riscv_debug_infcall = 0;
291
78a3b0fa
AB		 292/* When this is set to non-zero debugging information about stack unwinding
293 will be printed. */
294
295static unsigned int riscv_debug_unwinder = 0;
296
dbbb1059
AB		 297/* Read the MISA register from the target. The register will only be read
298 once, and the value read will be cached. If the register can't be read
299 from the target then a default value (0) will be returned. If the
300 pointer READ_P is not null, then the bool pointed to is updated to
301 indicate if the value returned was read from the target (true) or is the
302 default (false). */
303
304static uint32_t
305riscv_read_misa_reg (bool *read_p)
306{
0b3f9efc 307 uint32_t value = 0;
dbbb1059 308
0b3f9efc 309 if (target_has_registers)
dbbb1059 310 {
dbbb1059
AB		 311 struct frame_info *frame = get_current_frame ();
312
313 TRY
314 {
0b3f9efc
AB		 315 value = get_frame_register_unsigned (frame,
316 RISCV_CSR_MISA_REGNUM);
dbbb1059
AB		 317 }
318 CATCH (ex, RETURN_MASK_ERROR)
319 {
320 /* Old cores might have MISA located at a different offset. */
321 value = get_frame_register_unsigned (frame,
322 RISCV_CSR_LEGACY_MISA_REGNUM);
323 }
324 END_CATCH
dbbb1059
AB		 325 }
326
0b3f9efc 327 return value;
dbbb1059
AB		 328}
329
330/* Return true if FEATURE is available for the architecture GDBARCH. The
331 FEATURE should be one of the single character feature codes described in
332 the RiscV ISA manual, these are between 'A' and 'Z'. */
333
334static bool
335riscv_has_feature (struct gdbarch *gdbarch, char feature)
336{
337 bool have_read_misa = false;
338 uint32_t misa;
339
340 gdb_assert (feature >= 'A' && feature <= 'Z');
341
27724bad 342 misa = riscv_read_misa_reg (&have_read_misa);
dbbb1059
AB		 343 if (!have_read_misa || misa == 0)
344 misa = gdbarch_tdep (gdbarch)->core_features;
345
346 return (misa & (1 << (feature - 'A'))) != 0;
347}
348
349/* Return the width in bytes of the general purpose registers for GDBARCH.
350 Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
351 RV128. */
352
411baa47 353int
dbbb1059
AB		 354riscv_isa_xlen (struct gdbarch *gdbarch)
355{
356 switch (gdbarch_tdep (gdbarch)->abi.fields.base_len)
357 {
358 default:
359 warning (_("unknown xlen size, assuming 4 bytes"));
565e0eda 360 /* Fall through. */
dbbb1059
AB		 361 case 1:
362 return 4;
363 case 2:
364 return 8;
365 case 3:
366 return 16;
367 }
368}
369
370/* Return the width in bytes of the floating point registers for GDBARCH.
371 If this architecture has no floating point registers, then return 0.
372 Possible values are 4, 8, or 16 for depending on which of single, double
373 or quad floating point support is available. */
374
375static int
376riscv_isa_flen (struct gdbarch *gdbarch)
377{
378 if (riscv_has_feature (gdbarch, 'Q'))
379 return 16;
380 else if (riscv_has_feature (gdbarch, 'D'))
381 return 8;
382 else if (riscv_has_feature (gdbarch, 'F'))
383 return 4;
384
385 return 0;
386}
387
388/* Return true if the target for GDBARCH has floating point hardware. */
389
390static bool
391riscv_has_fp_regs (struct gdbarch *gdbarch)
392{
393 return (riscv_isa_flen (gdbarch) > 0);
394}
395
396/* Return true if GDBARCH is using any of the floating point hardware ABIs. */
397
398static bool
399riscv_has_fp_abi (struct gdbarch *gdbarch)
400{
401 return (gdbarch_tdep (gdbarch)->abi.fields.float_abi != 0);
402}
403
8c49aa89
AB		 404/* Return true if REGNO is a floating pointer register. */
405
406static bool
407riscv_is_fp_regno_p (int regno)
408{
409 return (regno >= RISCV_FIRST_FP_REGNUM
410 && regno <= RISCV_LAST_FP_REGNUM);
411}
412
dbbb1059
AB		 413/* Implement the breakpoint_kind_from_pc gdbarch method. */
414
415static int
416riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
417{
418 if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO)
419 {
420 if (riscv_has_feature (gdbarch, 'C'))
421 return 2;
422 else
423 return 4;
424 }
425 else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE)
426 return 2;
427 else
428 return 4;
429}
430
431/* Implement the sw_breakpoint_from_kind gdbarch method. */
432
433static const gdb_byte *
434riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
435{
436 static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, };
437 static const gdb_byte c_ebreak[] = { 0x02, 0x90 };
438
439 *size = kind;
440 switch (kind)
441 {
442 case 2:
443 return c_ebreak;
444 case 4:
445 return ebreak;
446 default:
89a3b63e 447 gdb_assert_not_reached (_("unhandled breakpoint kind"));
dbbb1059
AB		 448 }
449}
450
451/* Callback function for user_reg_add. */
452
453static struct value *
454value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
455{
456 const int *reg_p = (const int *) baton;
457 return value_of_register (*reg_p, frame);
458}
459
460/* Implement the register_name gdbarch method. */
461
462static const char *
463riscv_register_name (struct gdbarch *gdbarch, int regnum)
464{
dbbb1059
AB		 465 /* Prefer to use the alias. */
466 if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_REGNUM)
467 {
468 int i;
469
470 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
471 if (regnum == riscv_register_aliases[i].regnum)
472 return riscv_register_aliases[i].name;
473 }
474
475 if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
476 return riscv_gdb_reg_names[regnum];
477
478 if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
479 {
480 static char buf[20];
481
89a3b63e
AB		 482 xsnprintf (buf, sizeof (buf), "csr%d",
483 regnum - RISCV_FIRST_CSR_REGNUM);
dbbb1059
AB		 484 return buf;
485 }
486
487 if (regnum == RISCV_PRIV_REGNUM)
488 return "priv";
489
490 return NULL;
491}
492
dbbb1059
AB		 493/* Implement the register_type gdbarch method. */
494
495static struct type *
496riscv_register_type (struct gdbarch *gdbarch, int regnum)
497{
498 int regsize;
499
500 if (regnum < RISCV_FIRST_FP_REGNUM)
501 {
502 if (regnum == gdbarch_pc_regnum (gdbarch)
503 || regnum == RISCV_RA_REGNUM)
504 return builtin_type (gdbarch)->builtin_func_ptr;
505
506 if (regnum == RISCV_FP_REGNUM
507 || regnum == RISCV_SP_REGNUM
508 || regnum == RISCV_GP_REGNUM
509 || regnum == RISCV_TP_REGNUM)
510 return builtin_type (gdbarch)->builtin_data_ptr;
511
512 /* Remaining GPRs vary in size based on the current ISA. */
513 regsize = riscv_isa_xlen (gdbarch);
514 switch (regsize)
515 {
516 case 4:
517 return builtin_type (gdbarch)->builtin_uint32;
518 case 8:
519 return builtin_type (gdbarch)->builtin_uint64;
520 case 16:
521 return builtin_type (gdbarch)->builtin_uint128;
522 default:
523 internal_error (__FILE__, __LINE__,
524 _("unknown isa regsize %i"), regsize);
525 }
526 }
527 else if (regnum <= RISCV_LAST_FP_REGNUM)
528 {
529 regsize = riscv_isa_xlen (gdbarch);
530 switch (regsize)
531 {
532 case 4:
533 return builtin_type (gdbarch)->builtin_float;
534 case 8:
535 return builtin_type (gdbarch)->builtin_double;
536 case 16:
537 return builtin_type (gdbarch)->builtin_long_double;
538 default:
539 internal_error (__FILE__, __LINE__,
540 _("unknown isa regsize %i"), regsize);
541 }
542 }
543 else if (regnum == RISCV_PRIV_REGNUM)
544 return builtin_type (gdbarch)->builtin_int8;
545 else
546 {
547 if (regnum == RISCV_CSR_FFLAGS_REGNUM
548 || regnum == RISCV_CSR_FRM_REGNUM
549 || regnum == RISCV_CSR_FCSR_REGNUM)
550 return builtin_type (gdbarch)->builtin_int32;
551
552 regsize = riscv_isa_xlen (gdbarch);
553 switch (regsize)
554 {
555 case 4:
556 return builtin_type (gdbarch)->builtin_int32;
557 case 8:
558 return builtin_type (gdbarch)->builtin_int64;
559 case 16:
560 return builtin_type (gdbarch)->builtin_int128;
561 default:
562 internal_error (__FILE__, __LINE__,
563 _("unknown isa regsize %i"), regsize);
564 }
565 }
566}
567
568/* Helper for riscv_print_registers_info, prints info for a single register
569 REGNUM. */
570
571static void
572riscv_print_one_register_info (struct gdbarch *gdbarch,
573 struct ui_file *file,
574 struct frame_info *frame,
575 int regnum)
576{
577 const char *name = gdbarch_register_name (gdbarch, regnum);
578 struct value *val = value_of_register (regnum, frame);
579 struct type *regtype = value_type (val);
580 int print_raw_format;
581 enum tab_stops { value_column_1 = 15 };
582
583 fputs_filtered (name, file);
584 print_spaces_filtered (value_column_1 - strlen (name), file);
585
586 print_raw_format = (value_entirely_available (val)
587 && !value_optimized_out (val));
588
589 if (TYPE_CODE (regtype) == TYPE_CODE_FLT)
590 {
591 struct value_print_options opts;
592 const gdb_byte *valaddr = value_contents_for_printing (val);
593 enum bfd_endian byte_order = gdbarch_byte_order (get_type_arch (regtype));
594
595 get_user_print_options (&opts);
596 opts.deref_ref = 1;
597
598 val_print (regtype,
599 value_embedded_offset (val), 0,
600 file, 0, val, &opts, current_language);
601
602 if (print_raw_format)
603 {
604 fprintf_filtered (file, "\t(raw ");
605 print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order,
606 true);
607 fprintf_filtered (file, ")");
608 }
609 }
610 else
611 {
612 struct value_print_options opts;
613
614 /* Print the register in hex. */
615 get_formatted_print_options (&opts, 'x');
616 opts.deref_ref = 1;
617 val_print (regtype,
618 value_embedded_offset (val), 0,
619 file, 0, val, &opts, current_language);
620
621 if (print_raw_format)
622 {
623 if (regnum == RISCV_CSR_MSTATUS_REGNUM)
624 {
625 LONGEST d;
626 int size = register_size (gdbarch, regnum);
627 unsigned xlen;
628
629 d = value_as_long (val);
630 xlen = size * 4;
631 fprintf_filtered (file,
632 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
633 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
634 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
635 (int) ((d >> (xlen - 1)) & 0x1),
636 (int) ((d >> 24) & 0x1f),
637 (int) ((d >> 19) & 0x1),
638 (int) ((d >> 18) & 0x1),
639 (int) ((d >> 17) & 0x1),
640 (int) ((d >> 15) & 0x3),
641 (int) ((d >> 13) & 0x3),
642 (int) ((d >> 11) & 0x3),
643 (int) ((d >> 9) & 0x3),
644 (int) ((d >> 8) & 0x1),
645 (int) ((d >> 7) & 0x1),
646 (int) ((d >> 6) & 0x1),
647 (int) ((d >> 5) & 0x1),
648 (int) ((d >> 4) & 0x1),
649 (int) ((d >> 3) & 0x1),
650 (int) ((d >> 2) & 0x1),
651 (int) ((d >> 1) & 0x1),
652 (int) ((d >> 0) & 0x1));
653 }
654 else if (regnum == RISCV_CSR_MISA_REGNUM)
655 {
656 int base;
657 unsigned xlen, i;
658 LONGEST d;
659
660 d = value_as_long (val);
661 base = d >> 30;
662 xlen = 16;
663
664 for (; base > 0; base--)
665 xlen *= 2;
666 fprintf_filtered (file, "\tRV%d", xlen);
667
668 for (i = 0; i < 26; i++)
669 {
670 if (d & (1 << i))
671 fprintf_filtered (file, "%c", 'A' + i);
672 }
673 }
674 else if (regnum == RISCV_CSR_FCSR_REGNUM
675 || regnum == RISCV_CSR_FFLAGS_REGNUM
676 || regnum == RISCV_CSR_FRM_REGNUM)
677 {
678 LONGEST d;
679
680 d = value_as_long (val);
681
682 fprintf_filtered (file, "\t");
683 if (regnum != RISCV_CSR_FRM_REGNUM)
684 fprintf_filtered (file,
685 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
686 (int) ((d >> 5) & 0x7),
687 (int) ((d >> 4) & 0x1),
688 (int) ((d >> 3) & 0x1),
689 (int) ((d >> 2) & 0x1),
690 (int) ((d >> 1) & 0x1),
691 (int) ((d >> 0) & 0x1));
692
693 if (regnum != RISCV_CSR_FFLAGS_REGNUM)
694 {
695 static const char * const sfrm[] =
696 {
697 "RNE (round to nearest; ties to even)",
698 "RTZ (Round towards zero)",
699 "RDN (Round down towards -INF)",
700 "RUP (Round up towards +INF)",
701 "RMM (Round to nearest; ties to max magnitude)",
702 "INVALID[5]",
703 "INVALID[6]",
704 "dynamic rounding mode",
705 };
706 int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
707 ? (d >> 5) : d) & 0x3;
708
709 fprintf_filtered (file, "%sFRM:%i [%s]",
710 (regnum == RISCV_CSR_FCSR_REGNUM
711 ? " " : ""),
712 frm, sfrm[frm]);
713 }
714 }
715 else if (regnum == RISCV_PRIV_REGNUM)
716 {
717 LONGEST d;
718 uint8_t priv;
719
720 d = value_as_long (val);
721 priv = d & 0xff;
722
723 if (priv < 4)
724 {
725 static const char * const sprv[] =
726 {
727 "User/Application",
728 "Supervisor",
729 "Hypervisor",
730 "Machine"
731 };
732 fprintf_filtered (file, "\tprv:%d [%s]",
733 priv, sprv[priv]);
734 }
735 else
736 fprintf_filtered (file, "\tprv:%d [INVALID]", priv);
737 }
738 else
739 {
740 /* If not a vector register, print it also according to its
741 natural format. */
742 if (TYPE_VECTOR (regtype) == 0)
743 {
744 get_user_print_options (&opts);
745 opts.deref_ref = 1;
746 fprintf_filtered (file, "\t");
747 val_print (regtype,
748 value_embedded_offset (val), 0,
749 file, 0, val, &opts, current_language);
750 }
751 }
752 }
753 }
754 fprintf_filtered (file, "\n");
755}
756
757/* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
758 of REGGROUP? */
759
760static int
761riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
762 struct reggroup *reggroup)
763{
dbbb1059
AB		 764 unsigned int i;
765
766 /* Used by 'info registers' and 'info registers <groupname>'. */
767
768 if (gdbarch_register_name (gdbarch, regnum) == NULL
769 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
770 return 0;
771
772 if (reggroup == all_reggroup)
773 {
774 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM)
775 return 1;
776 /* Only include CSRs that have aliases. */
777 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
778 {
779 if (regnum == riscv_register_aliases[i].regnum)
780 return 1;
781 }
782 return 0;
783 }
784 else if (reggroup == float_reggroup)
8c49aa89
AB		 785 return (riscv_is_fp_regno_p (regnum)
786 || regnum == RISCV_CSR_FCSR_REGNUM
787 || regnum == RISCV_CSR_FFLAGS_REGNUM
788 || regnum == RISCV_CSR_FRM_REGNUM);
dbbb1059
AB		 789 else if (reggroup == general_reggroup)
790 return regnum < RISCV_FIRST_FP_REGNUM;
791 else if (reggroup == restore_reggroup || reggroup == save_reggroup)
792 {
793 if (riscv_has_fp_regs (gdbarch))
794 return regnum <= RISCV_LAST_FP_REGNUM;
795 else
796 return regnum < RISCV_FIRST_FP_REGNUM;
797 }
798 else if (reggroup == system_reggroup)
799 {
800 if (regnum == RISCV_PRIV_REGNUM)
801 return 1;
802 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM)
803 return 0;
804 /* Only include CSRs that have aliases. */
805 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
806 {
807 if (regnum == riscv_register_aliases[i].regnum)
808 return 1;
809 }
810 return 0;
811 }
812 else if (reggroup == vector_reggroup)
813 return 0;
814 else
815 return 0;
816}
817
818/* Implement the print_registers_info gdbarch method. This is used by
819 'info registers' and 'info all-registers'. */
820
821static void
822riscv_print_registers_info (struct gdbarch *gdbarch,
823 struct ui_file *file,
824 struct frame_info *frame,
825 int regnum, int print_all)
826{
827 if (regnum != -1)
828 {
829 /* Print one specified register. */
830 gdb_assert (regnum <= RISCV_LAST_REGNUM);
831 if (gdbarch_register_name (gdbarch, regnum) == NULL
832 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
833 error (_("Not a valid register for the current processor type"));
834 riscv_print_one_register_info (gdbarch, file, frame, regnum);
835 }
836 else
837 {
838 struct reggroup *reggroup;
839
840 if (print_all)
841 reggroup = all_reggroup;
842 else
843 reggroup = general_reggroup;
844
845 for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum)
846 {
847 /* Zero never changes, so might as well hide by default. */
848 if (regnum == RISCV_ZERO_REGNUM && !print_all)
849 continue;
850
851 /* Registers with no name are not valid on this ISA. */
852 if (gdbarch_register_name (gdbarch, regnum) == NULL
853 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
854 continue;
855
856 /* Is the register in the group we're interested in? */
857 if (!riscv_register_reggroup_p (gdbarch, regnum, reggroup))
858 continue;
859
860 riscv_print_one_register_info (gdbarch, file, frame, regnum);
861 }
862 }
863}
864
865/* Class that handles one decoded RiscV instruction. */
866
867class riscv_insn
868{
869public:
870
871 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
872 enum opcode
873 {
874 /* Unknown value is used at initialisation time. */
875 UNKNOWN = 0,
876
877 /* These instructions are all the ones we are interested in during the
878 prologue scan. */
879 ADD,
880 ADDI,
881 ADDIW,
882 ADDW,
883 AUIPC,
884 LUI,
885 SD,
886 SW,
5c720ed8
JW		 887 /* These are needed for software breakopint support. */
888 JAL,
889 JALR,
890 BEQ,
891 BNE,
892 BLT,
893 BGE,
894 BLTU,
895 BGEU,
896 /* These are needed for stepping over atomic sequences. */
897 LR,
898 SC,
dbbb1059
AB		 899
900 /* Other instructions are not interesting during the prologue scan, and
901 are ignored. */
902 OTHER
903 };
904
905 riscv_insn ()
906 : m_length (0),
907 m_opcode (OTHER),
908 m_rd (0),
909 m_rs1 (0),
910 m_rs2 (0)
911 {
912 /* Nothing. */
913 }
914
915 void decode (struct gdbarch *gdbarch, CORE_ADDR pc);
916
917 /* Get the length of the instruction in bytes. */
918 int length () const
919 { return m_length; }
920
921 /* Get the opcode for this instruction. */
922 enum opcode opcode () const
923 { return m_opcode; }
924
925 /* Get destination register field for this instruction. This is only
926 valid if the OPCODE implies there is such a field for this
927 instruction. */
928 int rd () const
929 { return m_rd; }
930
931 /* Get the RS1 register field for this instruction. This is only valid
932 if the OPCODE implies there is such a field for this instruction. */
933 int rs1 () const
934 { return m_rs1; }
935
936 /* Get the RS2 register field for this instruction. This is only valid
937 if the OPCODE implies there is such a field for this instruction. */
938 int rs2 () const
939 { return m_rs2; }
940
941 /* Get the immediate for this instruction in signed form. This is only
942 valid if the OPCODE implies there is such a field for this
943 instruction. */
944 int imm_signed () const
945 { return m_imm.s; }
946
947private:
948
949 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
950 int decode_register_index (unsigned long opcode, int offset)
951 {
952 return (opcode >> offset) & 0x1F;
953 }
954
5c720ed8
JW		 955 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
956 int decode_register_index_short (unsigned long opcode, int offset)
957 {
958 return ((opcode >> offset) & 0x7) + 8;
959 }
960
dbbb1059
AB		 961 /* Helper for DECODE, decode 32-bit R-type instruction. */
962 void decode_r_type_insn (enum opcode opcode, ULONGEST ival)
963 {
964 m_opcode = opcode;
965 m_rd = decode_register_index (ival, OP_SH_RD);
966 m_rs1 = decode_register_index (ival, OP_SH_RS1);
967 m_rs2 = decode_register_index (ival, OP_SH_RS2);
968 }
969
970 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
971 void decode_cr_type_insn (enum opcode opcode, ULONGEST ival)
972 {
973 m_opcode = opcode;
974 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
975 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
976 }
977
978 /* Helper for DECODE, decode 32-bit I-type instruction. */
979 void decode_i_type_insn (enum opcode opcode, ULONGEST ival)
980 {
981 m_opcode = opcode;
982 m_rd = decode_register_index (ival, OP_SH_RD);
983 m_rs1 = decode_register_index (ival, OP_SH_RS1);
984 m_imm.s = EXTRACT_ITYPE_IMM (ival);
985 }
986
987 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
988 void decode_ci_type_insn (enum opcode opcode, ULONGEST ival)
989 {
990 m_opcode = opcode;
991 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
992 m_imm.s = EXTRACT_RVC_IMM (ival);
993 }
994
995 /* Helper for DECODE, decode 32-bit S-type instruction. */
996 void decode_s_type_insn (enum opcode opcode, ULONGEST ival)
997 {
998 m_opcode = opcode;
999 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1000 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1001 m_imm.s = EXTRACT_STYPE_IMM (ival);
1002 }
1003
ff3a05b3
AB		 1004 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1005 encoding is different for each CS format instruction, so extracting
1006 the immediate is left up to the caller, who should pass the extracted
1007 immediate value through in IMM. */
1008 void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1009 {
1010 m_opcode = opcode;
1011 m_imm.s = imm;
1012 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1013 m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S);
1014 }
1015
1016 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1017 encoding is different for each CSS format instruction, so extracting
1018 the immediate is left up to the caller, who should pass the extracted
1019 immediate value through in IMM. */
1020 void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1021 {
1022 m_opcode = opcode;
1023 m_imm.s = imm;
1024 m_rs1 = RISCV_SP_REGNUM;
1025 /* Not a compressed register number in this case. */
1026 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1027 }
1028
dbbb1059
AB		 1029 /* Helper for DECODE, decode 32-bit U-type instruction. */
1030 void decode_u_type_insn (enum opcode opcode, ULONGEST ival)
1031 {
1032 m_opcode = opcode;
1033 m_rd = decode_register_index (ival, OP_SH_RD);
1034 m_imm.s = EXTRACT_UTYPE_IMM (ival);
1035 }
1036
5c720ed8
JW		 1037 /* Helper for DECODE, decode 32-bit J-type instruction. */
1038 void decode_j_type_insn (enum opcode opcode, ULONGEST ival)
1039 {
1040 m_opcode = opcode;
1041 m_rd = decode_register_index (ival, OP_SH_RD);
1042 m_imm.s = EXTRACT_UJTYPE_IMM (ival);
1043 }
1044
1045 /* Helper for DECODE, decode 32-bit J-type instruction. */
1046 void decode_cj_type_insn (enum opcode opcode, ULONGEST ival)
1047 {
1048 m_opcode = opcode;
1049 m_imm.s = EXTRACT_RVC_J_IMM (ival);
1050 }
1051
1052 void decode_b_type_insn (enum opcode opcode, ULONGEST ival)
1053 {
1054 m_opcode = opcode;
1055 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1056 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1057 m_imm.s = EXTRACT_SBTYPE_IMM (ival);
1058 }
1059
1060 void decode_cb_type_insn (enum opcode opcode, ULONGEST ival)
1061 {
1062 m_opcode = opcode;
1063 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1064 m_imm.s = EXTRACT_RVC_B_IMM (ival);
1065 }
1066
dbbb1059
AB		 1067 /* Fetch instruction from target memory at ADDR, return the content of
1068 the instruction, and update LEN with the instruction length. */
1069 static ULONGEST fetch_instruction (struct gdbarch *gdbarch,
1070 CORE_ADDR addr, int *len);
1071
1072 /* The length of the instruction in bytes. Should be 2 or 4. */
1073 int m_length;
1074
1075 /* The instruction opcode. */
1076 enum opcode m_opcode;
1077
1078 /* The three possible registers an instruction might reference. Not
1079 every instruction fills in all of these registers. Which fields are
1080 valid depends on the opcode. The naming of these fields matches the
1081 naming in the riscv isa manual. */
1082 int m_rd;
1083 int m_rs1;
1084 int m_rs2;
1085
1086 /* Possible instruction immediate. This is only valid if the instruction
1087 format contains an immediate, not all instruction, whether this is
1088 valid depends on the opcode. Despite only having one format for now
1089 the immediate is packed into a union, later instructions might require
1090 an unsigned formatted immediate, having the union in place now will
1091 reduce the need for code churn later. */
1092 union riscv_insn_immediate
1093 {
1094 riscv_insn_immediate ()
1095 : s (0)
1096 {
1097 /* Nothing. */
1098 }
1099
1100 int s;
1101 } m_imm;
1102};
1103
1104/* Fetch instruction from target memory at ADDR, return the content of the
1105 instruction, and update LEN with the instruction length. */
1106
1107ULONGEST
1108riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
1109 CORE_ADDR addr, int *len)
1110{
1111 enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
1112 gdb_byte buf[8];
1113 int instlen, status;
1114
1115 /* All insns are at least 16 bits. */
1116 status = target_read_memory (addr, buf, 2);
1117 if (status)
1118 memory_error (TARGET_XFER_E_IO, addr);
1119
1120 /* If we need more, grab it now. */
1121 instlen = riscv_insn_length (buf[0]);
89a3b63e 1122 gdb_assert (instlen <= sizeof (buf));
dbbb1059 1123 *len = instlen;
89a3b63e
AB		 1124
1125 if (instlen > 2)
dbbb1059
AB		 1126 {
1127 status = target_read_memory (addr + 2, buf + 2, instlen - 2);
1128 if (status)
1129 memory_error (TARGET_XFER_E_IO, addr + 2);
1130 }
1131
1132 return extract_unsigned_integer (buf, instlen, byte_order);
1133}
1134
1135/* Fetch from target memory an instruction at PC and decode it. */
1136
1137void
1138riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc)
1139{
1140 ULONGEST ival;
1141
1142 /* Fetch the instruction, and the instructions length. */
1143 ival = fetch_instruction (gdbarch, pc, &m_length);
1144
1145 if (m_length == 4)
1146 {
1147 if (is_add_insn (ival))
1148 decode_r_type_insn (ADD, ival);
1149 else if (is_addw_insn (ival))
1150 decode_r_type_insn (ADDW, ival);
1151 else if (is_addi_insn (ival))
1152 decode_i_type_insn (ADDI, ival);
1153 else if (is_addiw_insn (ival))
1154 decode_i_type_insn (ADDIW, ival);
1155 else if (is_auipc_insn (ival))
1156 decode_u_type_insn (AUIPC, ival);
1157 else if (is_lui_insn (ival))
1158 decode_u_type_insn (LUI, ival);
1159 else if (is_sd_insn (ival))
1160 decode_s_type_insn (SD, ival);
1161 else if (is_sw_insn (ival))
1162 decode_s_type_insn (SW, ival);
5c720ed8
JW		 1163 else if (is_jal_insn (ival))
1164 decode_j_type_insn (JAL, ival);
1165 else if (is_jalr_insn (ival))
1166 decode_i_type_insn (JALR, ival);
1167 else if (is_beq_insn (ival))
1168 decode_b_type_insn (BEQ, ival);
1169 else if (is_bne_insn (ival))
1170 decode_b_type_insn (BNE, ival);
1171 else if (is_blt_insn (ival))
1172 decode_b_type_insn (BLT, ival);
1173 else if (is_bge_insn (ival))
1174 decode_b_type_insn (BGE, ival);
1175 else if (is_bltu_insn (ival))
1176 decode_b_type_insn (BLTU, ival);
1177 else if (is_bgeu_insn (ival))
1178 decode_b_type_insn (BGEU, ival);
1179 else if (is_lr_w_insn (ival))
1180 decode_r_type_insn (LR, ival);
1181 else if (is_lr_d_insn (ival))
1182 decode_r_type_insn (LR, ival);
1183 else if (is_sc_w_insn (ival))
1184 decode_r_type_insn (SC, ival);
1185 else if (is_sc_d_insn (ival))
1186 decode_r_type_insn (SC, ival);
dbbb1059
AB		 1187 else
1188 /* None of the other fields are valid in this case. */
1189 m_opcode = OTHER;
1190 }
1191 else if (m_length == 2)
1192 {
5c720ed8
JW		 1193 int xlen = riscv_isa_xlen (gdbarch);
1194
1195 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1196 C_JALR. So must try to match C_JALR first as it has more bits in
1197 mask. */
1198 if (is_c_jalr_insn (ival))
1199 decode_cr_type_insn (JALR, ival);
1200 else if (is_c_add_insn (ival))
dbbb1059 1201 decode_cr_type_insn (ADD, ival);
5c720ed8
JW		 1202 /* C_ADDW is RV64 and RV128 only. */
1203 else if (xlen != 4 && is_c_addw_insn (ival))
dbbb1059
AB		 1204 decode_cr_type_insn (ADDW, ival);
1205 else if (is_c_addi_insn (ival))
1206 decode_ci_type_insn (ADDI, ival);
5c720ed8
JW		 1207 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1208 only and C_JAL is RV32 only. */
1209 else if (xlen != 4 && is_c_addiw_insn (ival))
dbbb1059 1210 decode_ci_type_insn (ADDIW, ival);
5c720ed8
JW		 1211 else if (xlen == 4 && is_c_jal_insn (ival))
1212 decode_cj_type_insn (JAL, ival);
1213 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1214 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1215 in mask. */
dbbb1059
AB		 1216 else if (is_c_addi16sp_insn (ival))
1217 {
1218 m_opcode = ADDI;
1219 m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD);
1220 m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival);
1221 }
ff3a05b3
AB		 1222 else if (is_c_addi4spn_insn (ival))
1223 {
1224 m_opcode = ADDI;
1225 m_rd = decode_register_index_short (ival, OP_SH_CRS2S);
1226 m_rs1 = RISCV_SP_REGNUM;
1227 m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival);
1228 }
5c720ed8 1229 else if (is_c_lui_insn (ival))
dbbb1059 1230 m_opcode = OTHER;
5c720ed8
JW		 1231 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1232 and C_FSW is RV32 only. */
1233 else if (xlen != 4 && is_c_sd_insn (ival))
ff3a05b3 1234 decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival));
5c720ed8 1235 else if (is_c_sw_insn (ival))
ff3a05b3
AB		 1236 decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival));
1237 else if (is_c_swsp_insn (ival))
1238 decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival));
1239 else if (xlen != 4 && is_c_sdsp_insn (ival))
1240 decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival));
5c720ed8
JW		 1241 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1242 So must try to match C_JR first as it ahs more bits in mask. */
1243 else if (is_c_jr_insn (ival))
1244 decode_cr_type_insn (JALR, ival);
1245 else if (is_c_j_insn (ival))
1246 decode_cj_type_insn (JAL, ival);
1247 else if (is_c_beqz_insn (ival))
1248 decode_cb_type_insn (BEQ, ival);
1249 else if (is_c_bnez_insn (ival))
1250 decode_cb_type_insn (BNE, ival);
dbbb1059
AB		 1251 else
1252 /* None of the other fields of INSN are valid in this case. */
1253 m_opcode = OTHER;
1254 }
1255 else
1256 internal_error (__FILE__, __LINE__,
1257 _("unable to decode %d byte instructions in "
1258 "prologue at %s"), m_length,
1259 core_addr_to_string (pc));
1260}
1261
1262/* The prologue scanner. This is currently only used for skipping the
1263 prologue of a function when the DWARF information is not sufficient.
1264 However, it is written with filling of the frame cache in mind, which
1265 is why different groups of stack setup instructions are split apart
1266 during the core of the inner loop. In the future, the intention is to
1267 extend this function to fully support building up a frame cache that
1268 can unwind register values when there is no DWARF information. */
1269
1270static CORE_ADDR
1271riscv_scan_prologue (struct gdbarch *gdbarch,
78a3b0fa
AB		 1272 CORE_ADDR start_pc, CORE_ADDR end_pc,
1273 struct riscv_unwind_cache *cache)
dbbb1059 1274{
78a3b0fa 1275 CORE_ADDR cur_pc, next_pc, after_prologue_pc;
dbbb1059
AB		 1276 CORE_ADDR end_prologue_addr = 0;
1277
78a3b0fa
AB		 1278 /* Find an upper limit on the function prologue using the debug
1279 information. If the debug information could not be used to provide
1280 that bound, then use an arbitrary large number as the upper bound. */
1281 after_prologue_pc = skip_prologue_using_sal (gdbarch, start_pc);
1282 if (after_prologue_pc == 0)
1283 after_prologue_pc = start_pc + 100; /* Arbitrary large number. */
1284 if (after_prologue_pc < end_pc)
1285 end_pc = after_prologue_pc;
1286
1287 pv_t regs[RISCV_NUM_INTEGER_REGS]; /* Number of GPR. */
1288 for (int regno = 0; regno < RISCV_NUM_INTEGER_REGS; regno++)
1289 regs[regno] = pv_register (regno, 0);
1290 pv_area stack (RISCV_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1291
1292 if (riscv_debug_unwinder)
1293 fprintf_unfiltered
1294 (gdb_stdlog,
1295 "Prologue scan for function starting at %s (limit %s)\n",
1296 core_addr_to_string (start_pc),
1297 core_addr_to_string (end_pc));
1298
1299 for (next_pc = cur_pc = start_pc; cur_pc < end_pc; cur_pc = next_pc)
dbbb1059
AB		 1300 {
1301 struct riscv_insn insn;
1302
1303 /* Decode the current instruction, and decide where the next
1304 instruction lives based on the size of this instruction. */
1305 insn.decode (gdbarch, cur_pc);
1306 gdb_assert (insn.length () > 0);
1307 next_pc = cur_pc + insn.length ();
1308
1309 /* Look for common stack adjustment insns. */
1310 if ((insn.opcode () == riscv_insn::ADDI
1311 || insn.opcode () == riscv_insn::ADDIW)
1312 && insn.rd () == RISCV_SP_REGNUM
1313 && insn.rs1 () == RISCV_SP_REGNUM)
1314 {
1315 /* Handle: addi sp, sp, -i
1316 or: addiw sp, sp, -i */
78a3b0fa
AB		 1317 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1318 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1319 regs[insn.rd ()]
1320 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
dbbb1059
AB		 1321 }
1322 else if ((insn.opcode () == riscv_insn::SW
1323 || insn.opcode () == riscv_insn::SD)
1324 && (insn.rs1 () == RISCV_SP_REGNUM
1325 || insn.rs1 () == RISCV_FP_REGNUM))
1326 {
1327 /* Handle: sw reg, offset(sp)
1328 or: sd reg, offset(sp)
1329 or: sw reg, offset(s0)
1330 or: sd reg, offset(s0) */
1331 /* Instruction storing a register onto the stack. */
78a3b0fa
AB		 1332 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1333 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
1334 stack.store (pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()),
1335 (insn.opcode () == riscv_insn::SW ? 4 : 8),
1336 regs[insn.rs2 ()]);
dbbb1059
AB		 1337 }
1338 else if (insn.opcode () == riscv_insn::ADDI
1339 && insn.rd () == RISCV_FP_REGNUM
1340 && insn.rs1 () == RISCV_SP_REGNUM)
1341 {
1342 /* Handle: addi s0, sp, size */
1343 /* Instructions setting up the frame pointer. */
78a3b0fa
AB		 1344 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1345 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1346 regs[insn.rd ()]
1347 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
dbbb1059
AB		 1348 }
1349 else if ((insn.opcode () == riscv_insn::ADD
1350 || insn.opcode () == riscv_insn::ADDW)
1351 && insn.rd () == RISCV_FP_REGNUM
1352 && insn.rs1 () == RISCV_SP_REGNUM
1353 && insn.rs2 () == RISCV_ZERO_REGNUM)
1354 {
1355 /* Handle: add s0, sp, 0
1356 or: addw s0, sp, 0 */
1357 /* Instructions setting up the frame pointer. */
78a3b0fa
AB		 1358 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1359 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1360 regs[insn.rd ()] = pv_add_constant (regs[insn.rs1 ()], 0);
dbbb1059
AB		 1361 }
1362 else if ((insn.rd () == RISCV_GP_REGNUM
1363 && (insn.opcode () == riscv_insn::AUIPC
1364 || insn.opcode () == riscv_insn::LUI
1365 || (insn.opcode () == riscv_insn::ADDI
1366 && insn.rs1 () == RISCV_GP_REGNUM)
1367 || (insn.opcode () == riscv_insn::ADD
1368 && (insn.rs1 () == RISCV_GP_REGNUM
1369 || insn.rs2 () == RISCV_GP_REGNUM))))
1370 || (insn.opcode () == riscv_insn::ADDI
1371 && insn.rd () == RISCV_ZERO_REGNUM
1372 && insn.rs1 () == RISCV_ZERO_REGNUM
1373 && insn.imm_signed () == 0))
1374 {
1375 /* Handle: auipc gp, n
1376 or: addi gp, gp, n
1377 or: add gp, gp, reg
1378 or: add gp, reg, gp
1379 or: lui gp, n
1380 or: add x0, x0, 0 (NOP) */
1381 /* These instructions are part of the prologue, but we don't need
1382 to do anything special to handle them. */
1383 }
1384 else
1385 {
78a3b0fa
AB		 1386 end_prologue_addr = cur_pc;
1387 break;
dbbb1059
AB		 1388 }
1389 }
1390
1391 if (end_prologue_addr == 0)
1392 end_prologue_addr = cur_pc;
1393
78a3b0fa
AB		 1394 if (riscv_debug_unwinder)
1395 fprintf_unfiltered (gdb_stdlog, "End of prologue at %s\n",
1396 core_addr_to_string (end_prologue_addr));
1397
1398 if (cache != NULL)
1399 {
1400 /* Figure out if it is a frame pointer or just a stack pointer. Also
1401 the offset held in the pv_t is from the original register value to
1402 the current value, which for a grows down stack means a negative
1403 value. The FRAME_BASE_OFFSET is the negation of this, how to get
1404 from the current value to the original value. */
1405 if (pv_is_register (regs[RISCV_FP_REGNUM], RISCV_SP_REGNUM))
1406 {
1407 cache->frame_base_reg = RISCV_FP_REGNUM;
1408 cache->frame_base_offset = -regs[RISCV_FP_REGNUM].k;
1409 }
1410 else
1411 {
1412 cache->frame_base_reg = RISCV_SP_REGNUM;
1413 cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k;
1414 }
1415
1416 /* Assign offset from old SP to all saved registers. As we don't
1417 have the previous value for the frame base register at this
1418 point, we store the offset as the address in the trad_frame, and
1419 then convert this to an actual address later. */
1420 for (int i = 0; i <= RISCV_NUM_INTEGER_REGS; i++)
1421 {
1422 CORE_ADDR offset;
1423 if (stack.find_reg (gdbarch, i, &offset))
1424 {
1425 if (riscv_debug_unwinder)
1426 fprintf_unfiltered (gdb_stdlog,
1427 "Register $%s at stack offset %ld\n",
1428 gdbarch_register_name (gdbarch, i),
1429 offset);
1430 trad_frame_set_addr (cache->regs, i, offset);
1431 }
1432 }
1433 }
1434
dbbb1059
AB		 1435 return end_prologue_addr;
1436}
1437
1438/* Implement the riscv_skip_prologue gdbarch method. */
1439
1440static CORE_ADDR
78a3b0fa 1441riscv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
dbbb1059 1442{
dbbb1059
AB		 1443 CORE_ADDR func_addr;
1444
1445 /* See if we can determine the end of the prologue via the symbol
1446 table. If so, then return either PC, or the PC after the
1447 prologue, whichever is greater. */
1448 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1449 {
1450 CORE_ADDR post_prologue_pc
1451 = skip_prologue_using_sal (gdbarch, func_addr);
1452
1453 if (post_prologue_pc != 0)
1454 return std::max (pc, post_prologue_pc);
1455 }
1456
1457 /* Can't determine prologue from the symbol table, need to examine
78a3b0fa
AB		 1458 instructions. Pass -1 for the end address to indicate the prologue
1459 scanner can scan as far as it needs to find the end of the prologue. */
1460 return riscv_scan_prologue (gdbarch, pc, ((CORE_ADDR) -1), NULL);
dbbb1059
AB		 1461}
1462
1463/* Implement the gdbarch push dummy code callback. */
1464
1465static CORE_ADDR
1466riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
1467 CORE_ADDR funaddr, struct value **args, int nargs,
1468 struct type *value_type, CORE_ADDR *real_pc,
1469 CORE_ADDR *bp_addr, struct regcache *regcache)
1470{
1471 /* Allocate space for a breakpoint, and keep the stack correctly
1472 aligned. */
1473 sp -= 16;
1474 *bp_addr = sp;
1475 *real_pc = funaddr;
1476 return sp;
1477}
1478
1479/* Compute the alignment of the type T. Used while setting up the
1480 arguments for a dummy call. */
1481
1482static int
1483riscv_type_alignment (struct type *t)
1484{
1485 t = check_typedef (t);
1486 switch (TYPE_CODE (t))
1487 {
1488 default:
1489 error (_("Could not compute alignment of type"));
1490
1491 case TYPE_CODE_RVALUE_REF:
1492 case TYPE_CODE_PTR:
1493 case TYPE_CODE_ENUM:
1494 case TYPE_CODE_INT:
1495 case TYPE_CODE_FLT:
1496 case TYPE_CODE_REF:
1497 case TYPE_CODE_CHAR:
1498 case TYPE_CODE_BOOL:
1499 return TYPE_LENGTH (t);
1500
1501 case TYPE_CODE_ARRAY:
1502 case TYPE_CODE_COMPLEX:
1503 return riscv_type_alignment (TYPE_TARGET_TYPE (t));
1504
1505 case TYPE_CODE_STRUCT:
1506 case TYPE_CODE_UNION:
1507 {
1508 int i;
1509 int align = 1;
1510
1511 for (i = 0; i < TYPE_NFIELDS (t); ++i)
1512 {
1513 if (TYPE_FIELD_LOC_KIND (t, i) == FIELD_LOC_KIND_BITPOS)
1514 {
1515 int a = riscv_type_alignment (TYPE_FIELD_TYPE (t, i));
1516 if (a > align)
1517 align = a;
1518 }
1519 }
1520 return align;
1521 }
1522 }
1523}
1524
1525/* Holds information about a single argument either being passed to an
1526 inferior function, or returned from an inferior function. This includes
1527 information about the size, type, etc of the argument, and also
1528 information about how the argument will be passed (or returned). */
1529
1530struct riscv_arg_info
1531{
1532 /* Contents of the argument. */
1533 const gdb_byte *contents;
1534
1535 /* Length of argument. */
1536 int length;
1537
1538 /* Alignment required for an argument of this type. */
1539 int align;
1540
1541 /* The type for this argument. */
1542 struct type *type;
1543
1544 /* Each argument can have either 1 or 2 locations assigned to it. Each
1545 location describes where part of the argument will be placed. The
1546 second location is valid based on the LOC_TYPE and C_LENGTH fields
1547 of the first location (which is always valid). */
1548 struct location
1549 {
1550 /* What type of location this is. */
1551 enum location_type
1552 {
1553 /* Argument passed in a register. */
1554 in_reg,
1555
1556 /* Argument passed as an on stack argument. */
1557 on_stack,
1558
1559 /* Argument passed by reference. The second location is always
1560 valid for a BY_REF argument, and describes where the address
1561 of the BY_REF argument should be placed. */
1562 by_ref
1563 } loc_type;
1564
1565 /* Information that depends on the location type. */
1566 union
1567 {
1568 /* Which register number to use. */
1569 int regno;
1570
1571 /* The offset into the stack region. */
1572 int offset;
1573 } loc_data;
1574
1575 /* The length of contents covered by this location. If this is less
1576 than the total length of the argument, then the second location
1577 will be valid, and will describe where the rest of the argument
1578 will go. */
1579 int c_length;
1580
1581 /* The offset within CONTENTS for this part of the argument. Will
1582 always be 0 for the first part. For the second part of the
1583 argument, this might be the C_LENGTH value of the first part,
1584 however, if we are passing a structure in two registers, and there's
1585 is padding between the first and second field, then this offset
1586 might be greater than the length of the first argument part. When
1587 the second argument location is not holding part of the argument
1588 value, but is instead holding the address of a reference argument,
1589 then this offset will be set to 0. */
1590 int c_offset;
1591 } argloc[2];
1592};
1593
1594/* Information about a set of registers being used for passing arguments as
1595 part of a function call. The register set must be numerically
1596 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1597 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1598
1599struct riscv_arg_reg
1600{
1601 riscv_arg_reg (int first, int last)
1602 : next_regnum (first),
1603 last_regnum (last)
1604 {
1605 /* Nothing. */
1606 }
1607
1608 /* The GDB register number to use in this set. */
1609 int next_regnum;
1610
1611 /* The last GDB register number to use in this set. */
1612 int last_regnum;
1613};
1614
1615/* Arguments can be passed as on stack arguments, or by reference. The
1616 on stack arguments must be in a continuous region starting from $sp,
1617 while the by reference arguments can be anywhere, but we'll put them
1618 on the stack after (at higher address) the on stack arguments.
1619
1620 This might not be the right approach to take. The ABI is clear that
1621 an argument passed by reference can be modified by the callee, which
1622 us placing the argument (temporarily) onto the stack will not achieve
1623 (changes will be lost). There's also the possibility that very large
1624 arguments could overflow the stack.
1625
1626 This struct is used to track offset into these two areas for where
1627 arguments are to be placed. */
1628struct riscv_memory_offsets
1629{
1630 riscv_memory_offsets ()
1631 : arg_offset (0),
1632 ref_offset (0)
1633 {
1634 /* Nothing. */
1635 }
1636
1637 /* Offset into on stack argument area. */
1638 int arg_offset;
1639
1640 /* Offset into the pass by reference area. */
1641 int ref_offset;
1642};
1643
1644/* Holds information about where arguments to a call will be placed. This
1645 is updated as arguments are added onto the call, and can be used to
1646 figure out where the next argument should be placed. */
1647
1648struct riscv_call_info
1649{
1650 riscv_call_info (struct gdbarch *gdbarch)
1651 : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7),
1652 float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7)
1653 {
1654 xlen = riscv_isa_xlen (gdbarch);
1655 flen = riscv_isa_flen (gdbarch);
1656
1657 /* Disable use of floating point registers if needed. */
1658 if (!riscv_has_fp_abi (gdbarch))
1659 float_regs.next_regnum = float_regs.last_regnum + 1;
1660 }
1661
1662 /* Track the memory areas used for holding in-memory arguments to a
1663 call. */
1664 struct riscv_memory_offsets memory;
1665
1666 /* Holds information about the next integer register to use for passing
1667 an argument. */
1668 struct riscv_arg_reg int_regs;
1669
1670 /* Holds information about the next floating point register to use for
1671 passing an argument. */
1672 struct riscv_arg_reg float_regs;
1673
1674 /* The XLEN and FLEN are copied in to this structure for convenience, and
1675 are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */
1676 int xlen;
1677 int flen;
1678};
1679
1680/* Return the number of registers available for use as parameters in the
1681 register set REG. Returned value can be 0 or more. */
1682
1683static int
1684riscv_arg_regs_available (struct riscv_arg_reg *reg)
1685{
1686 if (reg->next_regnum > reg->last_regnum)
1687 return 0;
1688
1689 return (reg->last_regnum - reg->next_regnum + 1);
1690}
1691
1692/* If there is at least one register available in the register set REG then
1693 the next register from REG is assigned to LOC and the length field of
1694 LOC is updated to LENGTH. The register set REG is updated to indicate
1695 that the assigned register is no longer available and the function
1696 returns true.
1697
1698 If there are no registers available in REG then the function returns
1699 false, and LOC and REG are unchanged. */
1700
1701static bool
1702riscv_assign_reg_location (struct riscv_arg_info::location *loc,
1703 struct riscv_arg_reg *reg,
1704 int length, int offset)
1705{
1706 if (reg->next_regnum <= reg->last_regnum)
1707 {
1708 loc->loc_type = riscv_arg_info::location::in_reg;
1709 loc->loc_data.regno = reg->next_regnum;
1710 reg->next_regnum++;
1711 loc->c_length = length;
1712 loc->c_offset = offset;
1713 return true;
1714 }
1715
1716 return false;
1717}
1718
1719/* Assign LOC a location as the next stack parameter, and update MEMORY to
1720 record that an area of stack has been used to hold the parameter
1721 described by LOC.
1722
1723 The length field of LOC is updated to LENGTH, the length of the
1724 parameter being stored, and ALIGN is the alignment required by the
1725 parameter, which will affect how memory is allocated out of MEMORY. */
1726
1727static void
1728riscv_assign_stack_location (struct riscv_arg_info::location *loc,
1729 struct riscv_memory_offsets *memory,
1730 int length, int align)
1731{
1732 loc->loc_type = riscv_arg_info::location::on_stack;
1733 memory->arg_offset
1734 = align_up (memory->arg_offset, align);
1735 loc->loc_data.offset = memory->arg_offset;
1736 memory->arg_offset += length;
1737 loc->c_length = length;
1738
1739 /* Offset is always 0, either we're the first location part, in which
1740 case we're reading content from the start of the argument, or we're
1741 passing the address of a reference argument, so 0. */
1742 loc->c_offset = 0;
1743}
1744
1745/* Update AINFO, which describes an argument that should be passed or
1746 returned using the integer ABI. The argloc fields within AINFO are
1747 updated to describe the location in which the argument will be passed to
1748 a function, or returned from a function.
1749
1750 The CINFO structure contains the ongoing call information, the holds
1751 information such as which argument registers are remaining to be
1752 assigned to parameter, and how much memory has been used by parameters
1753 so far.
1754
1755 By examining the state of CINFO a suitable location can be selected,
1756 and assigned to AINFO. */
1757
1758static void
1759riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo,
1760 struct riscv_call_info *cinfo)
1761{
1762 if (ainfo->length > (2 * cinfo->xlen))
1763 {
1764 /* Argument is going to be passed by reference. */
1765 ainfo->argloc[0].loc_type
1766 = riscv_arg_info::location::by_ref;
1767 cinfo->memory.ref_offset
1768 = align_up (cinfo->memory.ref_offset, ainfo->align);
1769 ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset;
1770 cinfo->memory.ref_offset += ainfo->length;
1771 ainfo->argloc[0].c_length = ainfo->length;
1772
1773 /* The second location for this argument is given over to holding the
1774 address of the by-reference data. Pass 0 for the offset as this
1775 is not part of the actual argument value. */
1776 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1777 &cinfo->int_regs,
1778 cinfo->xlen, 0))
1779 riscv_assign_stack_location (&ainfo->argloc[1],
1780 &cinfo->memory, cinfo->xlen,
1781 cinfo->xlen);
1782 }
1783 else
1784 {
1785 int len = (ainfo->length > cinfo->xlen) ? cinfo->xlen : ainfo->length;
1786
1787 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1788 &cinfo->int_regs, len, 0))
1789 riscv_assign_stack_location (&ainfo->argloc[0],
1790 &cinfo->memory, len, ainfo->align);
1791
1792 if (len < ainfo->length)
1793 {
1794 len = ainfo->length - len;
1795 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1796 &cinfo->int_regs, len,
1797 cinfo->xlen))
1798 riscv_assign_stack_location (&ainfo->argloc[1],
1799 &cinfo->memory, len, cinfo->xlen);
1800 }
1801 }
1802}
1803
1804/* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1805 is being passed with the floating point ABI. */
1806
1807static void
1808riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo,
1809 struct riscv_call_info *cinfo)
1810{
1811 if (ainfo->length > cinfo->flen)
1812 return riscv_call_arg_scalar_int (ainfo, cinfo);
1813 else
1814 {
1815 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1816 &cinfo->float_regs,
1817 ainfo->length, 0))
1818 return riscv_call_arg_scalar_int (ainfo, cinfo);
1819 }
1820}
1821
1822/* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1823 is a complex floating point argument, and is therefore handled
1824 differently to other argument types. */
1825
1826static void
1827riscv_call_arg_complex_float (struct riscv_arg_info *ainfo,
1828 struct riscv_call_info *cinfo)
1829{
1830 if (ainfo->length <= (2 * cinfo->flen)
1831 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
1832 {
1833 bool result;
1834 int len = ainfo->length / 2;
1835
1836 result = riscv_assign_reg_location (&ainfo->argloc[0],
1837 &cinfo->float_regs, len, len);
1838 gdb_assert (result);
1839
1840 result = riscv_assign_reg_location (&ainfo->argloc[1],
1841 &cinfo->float_regs, len, len);
1842 gdb_assert (result);
1843 }
1844 else
1845 return riscv_call_arg_scalar_int (ainfo, cinfo);
1846}
1847
1848/* A structure used for holding information about a structure type within
1849 the inferior program. The RiscV ABI has special rules for handling some
1850 structures with a single field or with two fields. The counting of
1851 fields here is done after flattening out all nested structures. */
1852
1853class riscv_struct_info
1854{
1855public:
1856 riscv_struct_info ()
1857 : m_number_of_fields (0),
1858 m_types { nullptr, nullptr }
1859 {
1860 /* Nothing. */
1861 }
1862
1863 /* Analyse TYPE descending into nested structures, count the number of
1864 scalar fields and record the types of the first two fields found. */
1865 void analyse (struct type *type);
1866
1867 /* The number of scalar fields found in the analysed type. This is
1868 currently only accurate if the value returned is 0, 1, or 2 as the
1869 analysis stops counting when the number of fields is 3. This is
1870 because the RiscV ABI only has special cases for 1 or 2 fields,
1871 anything else we just don't care about. */
1872 int number_of_fields () const
1873 { return m_number_of_fields; }
1874
1875 /* Return the type for scalar field INDEX within the analysed type. Will
1876 return nullptr if there is no field at that index. Only INDEX values
1877 0 and 1 can be requested as the RiscV ABI only has special cases for
1878 structures with 1 or 2 fields. */
1879 struct type *field_type (int index) const
1880 {
1881 gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0])));
1882 return m_types[index];
1883 }
1884
1885private:
1886 /* The number of scalar fields found within the structure after recursing
1887 into nested structures. */
1888 int m_number_of_fields;
1889
1890 /* The types of the first two scalar fields found within the structure
1891 after recursing into nested structures. */
1892 struct type *m_types[2];
1893};
1894
1895/* Analyse TYPE descending into nested structures, count the number of
1896 scalar fields and record the types of the first two fields found. */
1897
1898void
1899riscv_struct_info::analyse (struct type *type)
1900{
1901 unsigned int count = TYPE_NFIELDS (type);
1902 unsigned int i;
1903
1904 for (i = 0; i < count; ++i)
1905 {
1906 if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS)
1907 continue;
1908
1909 struct type *field_type = TYPE_FIELD_TYPE (type, i);
1910 field_type = check_typedef (field_type);
1911
1912 switch (TYPE_CODE (field_type))
1913 {
1914 case TYPE_CODE_STRUCT:
1915 analyse (field_type);
1916 break;
1917
1918 default:
1919 /* RiscV only flattens out structures. Anything else does not
1920 need to be flattened, we just record the type, and when we
1921 look at the analysis results we'll realise this is not a
1922 structure we can special case, and pass the structure in
1923 memory. */
1924 if (m_number_of_fields < 2)
1925 m_types[m_number_of_fields] = field_type;
1926 m_number_of_fields++;
1927 break;
1928 }
1929
1930 /* RiscV only has special handling for structures with 1 or 2 scalar
1931 fields, any more than that and the structure is just passed in
1932 memory. We can safely drop out early when we find 3 or more
1933 fields then. */
1934
1935 if (m_number_of_fields > 2)
1936 return;
1937 }
1938}
1939
1940/* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1941 is a structure. Small structures on RiscV have some special case
1942 handling in order that the structure might be passed in register.
1943 Larger structures are passed in memory. After assigning location
1944 information to AINFO, CINFO will have been updated. */
1945
1946static void
1947riscv_call_arg_struct (struct riscv_arg_info *ainfo,
1948 struct riscv_call_info *cinfo)
1949{
1950 if (riscv_arg_regs_available (&cinfo->float_regs) >= 1)
1951 {
1952 struct riscv_struct_info sinfo;
1953
1954 sinfo.analyse (ainfo->type);
1955 if (sinfo.number_of_fields () == 1
1956 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_COMPLEX)
1957 {
1958 gdb_assert (TYPE_LENGTH (ainfo->type)
1959 == TYPE_LENGTH (sinfo.field_type (0)));
1960 return riscv_call_arg_complex_float (ainfo, cinfo);
1961 }
1962
1963 if (sinfo.number_of_fields () == 1
1964 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT)
1965 {
1966 gdb_assert (TYPE_LENGTH (ainfo->type)
1967 == TYPE_LENGTH (sinfo.field_type (0)));
1968 return riscv_call_arg_scalar_float (ainfo, cinfo);
1969 }
1970
1971 if (sinfo.number_of_fields () == 2
1972 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
1973 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
1974 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
1975 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen
1976 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
1977 {
1978 int len0, len1, offset;
1979
1980 gdb_assert (TYPE_LENGTH (ainfo->type) <= (2 * cinfo->flen));
1981
1982 len0 = TYPE_LENGTH (sinfo.field_type (0));
1983 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1984 &cinfo->float_regs, len0, 0))
1985 error (_("failed during argument setup"));
1986
1987 len1 = TYPE_LENGTH (sinfo.field_type (1));
1988 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
1989 gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type)
1990 - TYPE_LENGTH (sinfo.field_type (0))));
1991
1992 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1993 &cinfo->float_regs,
1994 len1, offset))
1995 error (_("failed during argument setup"));
1996 return;
1997 }
1998
1999 if (sinfo.number_of_fields () == 2
2000 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2001 && (TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
2002 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
2003 && is_integral_type (sinfo.field_type (1))
2004 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen))
2005 {
2006 int len0, len1, offset;
2007
2008 gdb_assert (TYPE_LENGTH (ainfo->type)
2009 <= (cinfo->flen + cinfo->xlen));
2010
2011 len0 = TYPE_LENGTH (sinfo.field_type (0));
2012 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2013 &cinfo->float_regs, len0, 0))
2014 error (_("failed during argument setup"));
2015
2016 len1 = TYPE_LENGTH (sinfo.field_type (1));
2017 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2018 gdb_assert (len1 <= cinfo->xlen);
2019 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2020 &cinfo->int_regs, len1, offset))
2021 error (_("failed during argument setup"));
2022 return;
2023 }
2024
2025 if (sinfo.number_of_fields () == 2
2026 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2027 && (is_integral_type (sinfo.field_type (0))
2028 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen
2029 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
2030 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen))
2031 {
2032 int len0, len1, offset;
2033
2034 gdb_assert (TYPE_LENGTH (ainfo->type)
2035 <= (cinfo->flen + cinfo->xlen));
2036
2037 len0 = TYPE_LENGTH (sinfo.field_type (0));
2038 len1 = TYPE_LENGTH (sinfo.field_type (1));
2039 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2040
2041 gdb_assert (len0 <= cinfo->xlen);
2042 gdb_assert (len1 <= cinfo->flen);
2043
2044 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2045 &cinfo->int_regs, len0, 0))
2046 error (_("failed during argument setup"));
2047
2048 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2049 &cinfo->float_regs,
2050 len1, offset))
2051 error (_("failed during argument setup"));
2052
2053 return;
2054 }
2055 }
2056
2057 /* Non of the structure flattening cases apply, so we just pass using
2058 the integer ABI. */
2059 ainfo->length = align_up (ainfo->length, cinfo->xlen);
2060 riscv_call_arg_scalar_int (ainfo, cinfo);
2061}
2062
2063/* Assign a location to call (or return) argument AINFO, the location is
2064 selected from CINFO which holds information about what call argument
2065 locations are available for use next. The TYPE is the type of the
2066 argument being passed, this information is recorded into AINFO (along
2067 with some additional information derived from the type).
2068
2069 After assigning a location to AINFO, CINFO will have been updated. */
2070
2071static void
2072riscv_arg_location (struct gdbarch *gdbarch,
2073 struct riscv_arg_info *ainfo,
2074 struct riscv_call_info *cinfo,
2075 struct type *type)
2076{
2077 ainfo->type = type;
2078 ainfo->length = TYPE_LENGTH (ainfo->type);
2079 ainfo->align = riscv_type_alignment (ainfo->type);
2080 ainfo->contents = nullptr;
2081
2082 switch (TYPE_CODE (ainfo->type))
2083 {
2084 case TYPE_CODE_INT:
2085 case TYPE_CODE_BOOL:
2086 case TYPE_CODE_CHAR:
2087 case TYPE_CODE_RANGE:
2088 case TYPE_CODE_ENUM:
2089 case TYPE_CODE_PTR:
2090 if (ainfo->length <= cinfo->xlen)
2091 {
2092 ainfo->type = builtin_type (gdbarch)->builtin_long;
2093 ainfo->length = cinfo->xlen;
2094 }
2095 else if (ainfo->length <= (2 * cinfo->xlen))
2096 {
2097 ainfo->type = builtin_type (gdbarch)->builtin_long_long;
2098 ainfo->length = 2 * cinfo->xlen;
2099 }
2100
2101 /* Recalculate the alignment requirement. */
2102 ainfo->align = riscv_type_alignment (ainfo->type);
2103 riscv_call_arg_scalar_int (ainfo, cinfo);
2104 break;
2105
2106 case TYPE_CODE_FLT:
2107 riscv_call_arg_scalar_float (ainfo, cinfo);
2108 break;
2109
2110 case TYPE_CODE_COMPLEX:
2111 riscv_call_arg_complex_float (ainfo, cinfo);
2112 break;
2113
2114 case TYPE_CODE_STRUCT:
2115 riscv_call_arg_struct (ainfo, cinfo);
2116 break;
2117
2118 default:
2119 riscv_call_arg_scalar_int (ainfo, cinfo);
2120 break;
2121 }
2122}
2123
cab5bb9d
AB		 2124/* Used for printing debug information about the call argument location in
2125 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2126 addresses for the location of pass-by-reference and
2127 arguments-on-the-stack memory areas. */
2128
dbbb1059 2129static void
cab5bb9d 2130riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch,
dbbb1059
AB		 2131 struct riscv_arg_info *info,
2132 CORE_ADDR sp_refs, CORE_ADDR sp_args)
2133{
cab5bb9d 2134 fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x",
42ecac17 2135 TYPE_SAFE_NAME (info->type), info->length, info->align);
dbbb1059
AB		 2136 switch (info->argloc[0].loc_type)
2137 {
2138 case riscv_arg_info::location::in_reg:
cab5bb9d
AB		 2139 fprintf_unfiltered
2140 (stream, ", register %s",
2141 gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno));
dbbb1059
AB		 2142 if (info->argloc[0].c_length < info->length)
2143 {
2144 switch (info->argloc[1].loc_type)
2145 {
2146 case riscv_arg_info::location::in_reg:
cab5bb9d
AB		 2147 fprintf_unfiltered
2148 (stream, ", register %s",
2149 gdbarch_register_name (gdbarch,
2150 info->argloc[1].loc_data.regno));
dbbb1059
AB		 2151 break;
2152
2153 case riscv_arg_info::location::on_stack:
cab5bb9d
AB		 2154 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2155 info->argloc[1].loc_data.offset);
dbbb1059
AB		 2156 break;
2157
2158 case riscv_arg_info::location::by_ref:
2159 default:
2160 /* The second location should never be a reference, any
2161 argument being passed by reference just places its address
2162 in the first location and is done. */
2163 error (_("invalid argument location"));
2164 break;
2165 }
2166
2167 if (info->argloc[1].c_offset > info->argloc[0].c_length)
cab5bb9d
AB		 2168 fprintf_unfiltered (stream, " (offset 0x%x)",
2169 info->argloc[1].c_offset);
dbbb1059
AB		 2170 }
2171 break;
2172
2173 case riscv_arg_info::location::on_stack:
cab5bb9d
AB		 2174 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2175 info->argloc[0].loc_data.offset);
dbbb1059
AB		 2176 break;
2177
2178 case riscv_arg_info::location::by_ref:
cab5bb9d
AB		 2179 fprintf_unfiltered
2180 (stream, ", by reference, data at offset 0x%x (%s)",
2181 info->argloc[0].loc_data.offset,
2182 core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset));
dbbb1059
AB		 2183 if (info->argloc[1].loc_type
2184 == riscv_arg_info::location::in_reg)
cab5bb9d
AB		 2185 fprintf_unfiltered
2186 (stream, ", address in register %s",
2187 gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno));
dbbb1059
AB		 2188 else
2189 {
2190 gdb_assert (info->argloc[1].loc_type
2191 == riscv_arg_info::location::on_stack);
cab5bb9d
AB		 2192 fprintf_unfiltered
2193 (stream, ", address on stack at offset 0x%x (%s)",
2194 info->argloc[1].loc_data.offset,
2195 core_addr_to_string (sp_args + info->argloc[1].loc_data.offset));
dbbb1059
AB		 2196 }
2197 break;
2198
2199 default:
89a3b63e 2200 gdb_assert_not_reached (_("unknown argument location type"));
dbbb1059
AB		 2201 }
2202}
2203
2204/* Implement the push dummy call gdbarch callback. */
2205
2206static CORE_ADDR
2207riscv_push_dummy_call (struct gdbarch *gdbarch,
2208 struct value *function,
2209 struct regcache *regcache,
2210 CORE_ADDR bp_addr,
2211 int nargs,
2212 struct value **args,
2213 CORE_ADDR sp,
2214 int struct_return,
2215 CORE_ADDR struct_addr)
2216{
2217 int i;
2218 CORE_ADDR sp_args, sp_refs;
2219 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
dbbb1059
AB		 2220
2221 struct riscv_arg_info *arg_info =
2222 (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info));
2223 struct riscv_arg_info *info;
2224
2225 struct riscv_call_info call_info (gdbarch);
2226
2227 CORE_ADDR osp = sp;
2228
2229 /* We'll use register $a0 if we're returning a struct. */
2230 if (struct_return)
2231 ++call_info.int_regs.next_regnum;
2232
2233 for (i = 0, info = &arg_info[0];
2234 i < nargs;
2235 ++i, ++info)
2236 {
2237 struct value *arg_value;
2238 struct type *arg_type;
2239
2240 arg_value = args[i];
2241 arg_type = check_typedef (value_type (arg_value));
2242
2243 riscv_arg_location (gdbarch, info, &call_info, arg_type);
2244
2245 if (info->type != arg_type)
2246 arg_value = value_cast (info->type, arg_value);
2247 info->contents = value_contents (arg_value);
2248 }
2249
2250 /* Adjust the stack pointer and align it. */
2251 sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT);
2252 sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT);
2253
2254 if (riscv_debug_infcall > 0)
2255 {
2256 fprintf_unfiltered (gdb_stdlog, "dummy call args:\n");
2257 fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n",
2258 (riscv_has_fp_abi (gdbarch) ? "is" : "is not"));
2259 fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n",
2260 call_info.xlen, call_info.flen);
2261 if (struct_return)
2262 fprintf_unfiltered (gdb_stdlog,
2263 "[*] struct return pointer in register $A0\n");
2264 for (i = 0; i < nargs; ++i)
2265 {
2266 struct riscv_arg_info *info = &arg_info [i];
2267
2268 fprintf_unfiltered (gdb_stdlog, "[%2d] ", i);
cab5bb9d 2269 riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args);
dbbb1059
AB		 2270 fprintf_unfiltered (gdb_stdlog, "\n");
2271 }
2272 if (call_info.memory.arg_offset > 0
2273 || call_info.memory.ref_offset > 0)
2274 {
cab5bb9d
AB		 2275 fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n",
2276 core_addr_to_string (osp));
dbbb1059 2277 fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n",
cab5bb9d 2278 call_info.memory.arg_offset);
dbbb1059 2279 fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n",
cab5bb9d 2280 call_info.memory.ref_offset);
fb294655
AB		 2281 fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n",
2282 core_addr_to_string_nz (osp - sp));
dbbb1059
AB		 2283 }
2284 }
2285
2286 /* Now load the argument into registers, or onto the stack. */
2287
2288 if (struct_return)
2289 {
2290 gdb_byte buf[sizeof (LONGEST)];
2291
2292 store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr);
b66f5587 2293 regcache->cooked_write (RISCV_A0_REGNUM, buf);
dbbb1059
AB		 2294 }
2295
2296 for (i = 0; i < nargs; ++i)
2297 {
2298 CORE_ADDR dst;
2299 int second_arg_length = 0;
2300 const gdb_byte *second_arg_data;
2301 struct riscv_arg_info *info = &arg_info [i];
2302
2303 gdb_assert (info->length > 0);
2304
2305 switch (info->argloc[0].loc_type)
2306 {
2307 case riscv_arg_info::location::in_reg:
2308 {
2309 gdb_byte tmp [sizeof (ULONGEST)];
2310
2311 gdb_assert (info->argloc[0].c_length <= info->length);
2312 memset (tmp, 0, sizeof (tmp));
2313 memcpy (tmp, info->contents, info->argloc[0].c_length);
b66f5587 2314 regcache->cooked_write (info->argloc[0].loc_data.regno, tmp);
dbbb1059
AB		 2315 second_arg_length =
2316 ((info->argloc[0].c_length < info->length)
2317 ? info->argloc[1].c_length : 0);
2318 second_arg_data = info->contents + info->argloc[1].c_offset;
2319 }
2320 break;
2321
2322 case riscv_arg_info::location::on_stack:
2323 dst = sp_args + info->argloc[0].loc_data.offset;
2324 write_memory (dst, info->contents, info->length);
2325 second_arg_length = 0;
2326 break;
2327
2328 case riscv_arg_info::location::by_ref:
2329 dst = sp_refs + info->argloc[0].loc_data.offset;
2330 write_memory (dst, info->contents, info->length);
2331
2332 second_arg_length = call_info.xlen;
2333 second_arg_data = (gdb_byte *) &dst;
2334 break;
2335
2336 default:
89a3b63e 2337 gdb_assert_not_reached (_("unknown argument location type"));
dbbb1059
AB		 2338 }
2339
2340 if (second_arg_length > 0)
2341 {
2342 switch (info->argloc[1].loc_type)
2343 {
2344 case riscv_arg_info::location::in_reg:
2345 {
2346 gdb_byte tmp [sizeof (ULONGEST)];
2347
8c49aa89
AB		 2348 gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
2349 && second_arg_length <= call_info.flen)
2350 || second_arg_length <= call_info.xlen);
dbbb1059
AB		 2351 memset (tmp, 0, sizeof (tmp));
2352 memcpy (tmp, second_arg_data, second_arg_length);
b66f5587 2353 regcache->cooked_write (info->argloc[1].loc_data.regno, tmp);
dbbb1059
AB		 2354 }
2355 break;
2356
2357 case riscv_arg_info::location::on_stack:
2358 {
2359 CORE_ADDR arg_addr;
2360
2361 arg_addr = sp_args + info->argloc[1].loc_data.offset;
2362 write_memory (arg_addr, second_arg_data, second_arg_length);
2363 break;
2364 }
2365
2366 case riscv_arg_info::location::by_ref:
2367 default:
2368 /* The second location should never be a reference, any
2369 argument being passed by reference just places its address
2370 in the first location and is done. */
2371 error (_("invalid argument location"));
2372 break;
2373 }
2374 }
2375 }
2376
2377 /* Set the dummy return value to bp_addr.
2378 A dummy breakpoint will be setup to execute the call. */
2379
2380 if (riscv_debug_infcall > 0)
cab5bb9d
AB		 2381 fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n",
2382 core_addr_to_string (bp_addr));
dbbb1059
AB		 2383 regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr);
2384
2385 /* Finally, update the stack pointer. */
2386
2387 if (riscv_debug_infcall > 0)
cab5bb9d
AB		 2388 fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n",
2389 core_addr_to_string (sp));
dbbb1059
AB		 2390 regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp);
2391
2392 return sp;
2393}
2394
2395/* Implement the return_value gdbarch method. */
2396
2397static enum return_value_convention
2398riscv_return_value (struct gdbarch *gdbarch,
2399 struct value *function,
2400 struct type *type,
2401 struct regcache *regcache,
2402 gdb_byte *readbuf,
2403 const gdb_byte *writebuf)
2404{
dbbb1059
AB		 2405 struct riscv_call_info call_info (gdbarch);
2406 struct riscv_arg_info info;
2407 struct type *arg_type;
2408
2409 arg_type = check_typedef (type);
2410 riscv_arg_location (gdbarch, &info, &call_info, arg_type);
2411
2412 if (riscv_debug_infcall > 0)
2413 {
2414 fprintf_unfiltered (gdb_stdlog, "riscv return value:\n");
2415 fprintf_unfiltered (gdb_stdlog, "[R] ");
cab5bb9d 2416 riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0);
dbbb1059
AB		 2417 fprintf_unfiltered (gdb_stdlog, "\n");
2418 }
2419
2420 if (readbuf != nullptr || writebuf != nullptr)
2421 {
2422 int regnum;
2423
2424 switch (info.argloc[0].loc_type)
2425 {
2426 /* Return value in register(s). */
2427 case riscv_arg_info::location::in_reg:
2428 {
2429 regnum = info.argloc[0].loc_data.regno;
2430
2431 if (readbuf)
dca08e1f 2432 regcache->cooked_read (regnum, readbuf);
dbbb1059
AB		 2433
2434 if (writebuf)
b66f5587 2435 regcache->cooked_write (regnum, writebuf);
dbbb1059
AB		 2436
2437 /* A return value in register can have a second part in a
2438 second register. */
2439 if (info.argloc[0].c_length < info.length)
2440 {
2441 switch (info.argloc[1].loc_type)
2442 {
2443 case riscv_arg_info::location::in_reg:
2444 regnum = info.argloc[1].loc_data.regno;
2445
2446 if (readbuf)
2447 {
2448 readbuf += info.argloc[1].c_offset;
dca08e1f 2449 regcache->cooked_read (regnum, readbuf);
dbbb1059
AB		 2450 }
2451
2452 if (writebuf)
2453 {
2454 writebuf += info.argloc[1].c_offset;
b66f5587 2455 regcache->cooked_write (regnum, writebuf);
dbbb1059
AB		 2456 }
2457 break;
2458
2459 case riscv_arg_info::location::by_ref:
2460 case riscv_arg_info::location::on_stack:
2461 default:
2462 error (_("invalid argument location"));
2463 break;
2464 }
2465 }
2466 }
2467 break;
2468
2469 /* Return value by reference will have its address in A0. */
2470 case riscv_arg_info::location::by_ref:
2471 {
b2970c23 2472 ULONGEST addr;
dbbb1059
AB		 2473
2474 regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM,
2475 &addr);
2476 if (readbuf != nullptr)
2477 read_memory (addr, readbuf, info.length);
2478 if (writebuf != nullptr)
2479 write_memory (addr, writebuf, info.length);
2480 }
2481 break;
2482
2483 case riscv_arg_info::location::on_stack:
2484 default:
2485 error (_("invalid argument location"));
2486 break;
2487 }
2488 }
2489
2490 switch (info.argloc[0].loc_type)
2491 {
2492 case riscv_arg_info::location::in_reg:
2493 return RETURN_VALUE_REGISTER_CONVENTION;
2494 case riscv_arg_info::location::by_ref:
2495 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2496 case riscv_arg_info::location::on_stack:
2497 default:
2498 error (_("invalid argument location"));
2499 }
2500}
2501
2502/* Implement the frame_align gdbarch method. */
2503
2504static CORE_ADDR
2505riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2506{
2507 return align_down (addr, 16);
2508}
2509
2510/* Implement the unwind_pc gdbarch method. */
2511
2512static CORE_ADDR
2513riscv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2514{
2515 return frame_unwind_register_unsigned (next_frame, RISCV_PC_REGNUM);
2516}
2517
2518/* Implement the unwind_sp gdbarch method. */
2519
2520static CORE_ADDR
2521riscv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2522{
2523 return frame_unwind_register_unsigned (next_frame, RISCV_SP_REGNUM);
2524}
2525
2526/* Implement the dummy_id gdbarch method. */
2527
2528static struct frame_id
2529riscv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2530{
2531 return frame_id_build (get_frame_register_signed (this_frame, RISCV_SP_REGNUM),
2532 get_frame_pc (this_frame));
2533}
2534
2535/* Generate, or return the cached frame cache for the RiscV frame
2536 unwinder. */
2537
78a3b0fa 2538static struct riscv_unwind_cache *
dbbb1059
AB		 2539riscv_frame_cache (struct frame_info *this_frame, void **this_cache)
2540{
78a3b0fa
AB		 2541 CORE_ADDR pc, start_addr;
2542 struct riscv_unwind_cache *cache;
dbbb1059 2543 struct gdbarch *gdbarch = get_frame_arch (this_frame);
78a3b0fa 2544 int numregs, regno;
dbbb1059
AB		 2545
2546 if ((*this_cache) != NULL)
78a3b0fa 2547 return (struct riscv_unwind_cache *) *this_cache;
dbbb1059 2548
78a3b0fa
AB		 2549 cache = FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache);
2550 cache->regs = trad_frame_alloc_saved_regs (this_frame);
2551 (*this_cache) = cache;
dbbb1059 2552
78a3b0fa
AB		 2553 /* Scan the prologue, filling in the cache. */
2554 start_addr = get_frame_func (this_frame);
dbbb1059 2555 pc = get_frame_pc (this_frame);
78a3b0fa
AB		 2556 riscv_scan_prologue (gdbarch, start_addr, pc, cache);
2557
2558 /* We can now calculate the frame base address. */
2559 cache->frame_base
2560 = (get_frame_register_signed (this_frame, cache->frame_base_reg) +
2561 cache->frame_base_offset);
2562 if (riscv_debug_unwinder)
2563 fprintf_unfiltered (gdb_stdlog, "Frame base is %s ($%s + 0x%x)\n",
2564 core_addr_to_string (cache->frame_base),
2565 gdbarch_register_name (gdbarch,
2566 cache->frame_base_reg),
2567 cache->frame_base_offset);
2568
2569 /* The prologue scanner sets the address of registers stored to the stack
2570 as the offset of that register from the frame base. The prologue
2571 scanner doesn't know the actual frame base value, and so is unable to
2572 compute the exact address. We do now know the frame base value, so
2573 update the address of registers stored to the stack. */
2574 numregs = gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
2575 for (regno = 0; regno < numregs; ++regno)
2576 {
2577 if (trad_frame_addr_p (cache->regs, regno))
2578 cache->regs[regno].addr += cache->frame_base;
2579 }
2580
2581 /* The previous $pc can be found wherever the $ra value can be found.
2582 The previous $ra value is gone, this would have been stored be the
2583 previous frame if required. */
2584 cache->regs[gdbarch_pc_regnum (gdbarch)] = cache->regs[RISCV_RA_REGNUM];
2585 trad_frame_set_unknown (cache->regs, RISCV_RA_REGNUM);
2586
2587 /* Build the frame id. */
2588 cache->this_id = frame_id_build (cache->frame_base, start_addr);
dbbb1059 2589
78a3b0fa
AB		 2590 /* The previous $sp value is the frame base value. */
2591 trad_frame_set_value (cache->regs, gdbarch_sp_regnum (gdbarch),
2592 cache->frame_base);
dbbb1059 2593
78a3b0fa 2594 return cache;
dbbb1059
AB		 2595}
2596
2597/* Implement the this_id callback for RiscV frame unwinder. */
2598
2599static void
2600riscv_frame_this_id (struct frame_info *this_frame,
2601 void **prologue_cache,
2602 struct frame_id *this_id)
2603{
78a3b0fa 2604 struct riscv_unwind_cache *cache;
dbbb1059 2605
78a3b0fa
AB		 2606 cache = riscv_frame_cache (this_frame, prologue_cache);
2607 *this_id = cache->this_id;
dbbb1059
AB		 2608}
2609
2610/* Implement the prev_register callback for RiscV frame unwinder. */
2611
2612static struct value *
2613riscv_frame_prev_register (struct frame_info *this_frame,
2614 void **prologue_cache,
2615 int regnum)
2616{
78a3b0fa 2617 struct riscv_unwind_cache *cache;
dbbb1059 2618
78a3b0fa
AB		 2619 cache = riscv_frame_cache (this_frame, prologue_cache);
2620 return trad_frame_get_prev_register (this_frame, cache->regs, regnum);
dbbb1059
AB		 2621}
2622
2623/* Structure defining the RiscV normal frame unwind functions. Since we
2624 are the fallback unwinder (DWARF unwinder is used first), we use the
2625 default frame sniffer, which always accepts the frame. */
2626
2627static const struct frame_unwind riscv_frame_unwind =
2628{
2629 /*.type =*/ NORMAL_FRAME,
2630 /*.stop_reason =*/ default_frame_unwind_stop_reason,
2631 /*.this_id =*/ riscv_frame_this_id,
2632 /*.prev_register =*/ riscv_frame_prev_register,
2633 /*.unwind_data =*/ NULL,
2634 /*.sniffer =*/ default_frame_sniffer,
2635 /*.dealloc_cache =*/ NULL,
2636 /*.prev_arch =*/ NULL,
2637};
2638
2639/* Initialize the current architecture based on INFO. If possible,
2640 re-use an architecture from ARCHES, which is a list of
2641 architectures already created during this debugging session.
2642
2643 Called e.g. at program startup, when reading a core file, and when
2644 reading a binary file. */
2645
2646static struct gdbarch *
2647riscv_gdbarch_init (struct gdbarch_info info,
2648 struct gdbarch_list *arches)
2649{
2650 struct gdbarch *gdbarch;
2651 struct gdbarch_tdep *tdep;
2652 struct gdbarch_tdep tmp_tdep;
dbbb1059
AB		 2653 int i;
2654
2655 /* Ideally, we'd like to get as much information from the target for
2656 things like register size, and whether the target has floating point
2657 hardware. However, there are some things that the target can't tell
2658 us, like, what ABI is being used.
2659
2660 So, for now, we take as much information as possible from the ELF,
2661 including things like register size, and FP hardware support, along
2662 with information about the ABI.
2663
2664 Information about this target is built up in TMP_TDEP, and then we
2665 look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no
2666 match is found we'll create a new gdbarch and copy TMP_TDEP over. */
2667 memset (&tmp_tdep, 0, sizeof (tmp_tdep));
2668
2669 if (info.abfd != NULL
2670 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2671 {
2672 unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS];
2673 int e_flags = elf_elfheader (info.abfd)->e_flags;
2674
2675 if (eclass == ELFCLASS32)
2676 tmp_tdep.abi.fields.base_len = 1;
2677 else if (eclass == ELFCLASS64)
2678 tmp_tdep.abi.fields.base_len = 2;
2679 else
2680 internal_error (__FILE__, __LINE__,
2681 _("unknown ELF header class %d"), eclass);
2682
2683 if (e_flags & EF_RISCV_RVC)
27724bad 2684 tmp_tdep.core_features |= (1 << ('C' - 'A'));
dbbb1059
AB		 2685
2686 if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE)
2687 {
2688 tmp_tdep.abi.fields.float_abi = 2;
2689 tmp_tdep.core_features |= (1 << ('D' - 'A'));
2690 tmp_tdep.core_features |= (1 << ('F' - 'A'));
2691 }
2692 else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE)
2693 {
2694 tmp_tdep.abi.fields.float_abi = 1;
2695 tmp_tdep.core_features |= (1 << ('F' - 'A'));
2696 }
2697 }
2698 else
2699 {
2700 const struct bfd_arch_info *binfo = info.bfd_arch_info;
2701
2702 if (binfo->bits_per_word == 32)
2703 tmp_tdep.abi.fields.base_len = 1;
2704 else if (binfo->bits_per_word == 64)
2705 tmp_tdep.abi.fields.base_len = 2;
2706 else
2707 internal_error (__FILE__, __LINE__, _("unknown bits_per_word %d"),
2708 binfo->bits_per_word);
2709 }
2710
2711 /* Find a candidate among the list of pre-declared architectures. */
2712 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2713 arches != NULL;
2714 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2715 if (gdbarch_tdep (arches->gdbarch)->abi.value == tmp_tdep.abi.value)
2716 return arches->gdbarch;
2717
2718 /* None found, so create a new architecture from the information provided. */
2719 tdep = (struct gdbarch_tdep *) xmalloc (sizeof *tdep);
2720 gdbarch = gdbarch_alloc (&info, tdep);
2721 memcpy (tdep, &tmp_tdep, sizeof (tmp_tdep));
2722
2723 /* Target data types. */
2724 set_gdbarch_short_bit (gdbarch, 16);
2725 set_gdbarch_int_bit (gdbarch, 32);
2726 set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
2727 set_gdbarch_long_long_bit (gdbarch, 64);
2728 set_gdbarch_float_bit (gdbarch, 32);
2729 set_gdbarch_double_bit (gdbarch, 64);
2730 set_gdbarch_long_double_bit (gdbarch, 128);
2731 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
2732 set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
2733 set_gdbarch_char_signed (gdbarch, 0);
2734
2735 /* Information about the target architecture. */
2736 set_gdbarch_return_value (gdbarch, riscv_return_value);
2737 set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc);
2738 set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind);
2739
2740 /* Register architecture. */
dbbb1059 2741 set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1);
dbbb1059
AB		 2742 set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM);
2743 set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM);
2744 set_gdbarch_ps_regnum (gdbarch, RISCV_FP_REGNUM);
2745 set_gdbarch_deprecated_fp_regnum (gdbarch, RISCV_FP_REGNUM);
2746
2747 /* Functions to supply register information. */
2748 set_gdbarch_register_name (gdbarch, riscv_register_name);
2749 set_gdbarch_register_type (gdbarch, riscv_register_type);
2750 set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info);
2751 set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p);
2752
2753 /* Functions to analyze frames. */
dbbb1059
AB		 2754 set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue);
2755 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2756 set_gdbarch_frame_align (gdbarch, riscv_frame_align);
2757
2758 /* Functions to access frame data. */
2759 set_gdbarch_unwind_pc (gdbarch, riscv_unwind_pc);
2760 set_gdbarch_unwind_sp (gdbarch, riscv_unwind_sp);
2761
2762 /* Functions handling dummy frames. */
2763 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2764 set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code);
2765 set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call);
2766 set_gdbarch_dummy_id (gdbarch, riscv_dummy_id);
2767
2768 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
2769 unwinder. */
2770 dwarf2_append_unwinders (gdbarch);
2771 frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind);
2772
dbbb1059
AB		 2773 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
2774 user_reg_add (gdbarch, riscv_register_aliases[i].name,
2775 value_of_riscv_user_reg, &riscv_register_aliases[i].regnum);
2776
117a0e99
JW		 2777 /* Hook in OS ABI-specific overrides, if they have been registered. */
2778 gdbarch_init_osabi (info, gdbarch);
2779
dbbb1059
AB		 2780 return gdbarch;
2781}
2782
5c720ed8
JW		 2783/* This decodes the current instruction and determines the address of the
2784 next instruction. */
2785
2786static CORE_ADDR
2787riscv_next_pc (struct regcache *regcache, CORE_ADDR pc)
2788{
2789 struct gdbarch *gdbarch = regcache->arch ();
2790 struct riscv_insn insn;
2791 CORE_ADDR next_pc;
2792
2793 insn.decode (gdbarch, pc);
2794 next_pc = pc + insn.length ();
2795
2796 if (insn.opcode () == riscv_insn::JAL)
2797 next_pc = pc + insn.imm_signed ();
2798 else if (insn.opcode () == riscv_insn::JALR)
2799 {
2800 LONGEST source;
2801 regcache->cooked_read (insn.rs1 (), &source);
2802 next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR) 0x1;
2803 }
2804 else if (insn.opcode () == riscv_insn::BEQ)
2805 {
2806 LONGEST src1, src2;
2807 regcache->cooked_read (insn.rs1 (), &src1);
2808 regcache->cooked_read (insn.rs2 (), &src2);
2809 if (src1 == src2)
2810 next_pc = pc + insn.imm_signed ();
2811 }
2812 else if (insn.opcode () == riscv_insn::BNE)
2813 {
2814 LONGEST src1, src2;
2815 regcache->cooked_read (insn.rs1 (), &src1);
2816 regcache->cooked_read (insn.rs2 (), &src2);
2817 if (src1 != src2)
2818 next_pc = pc + insn.imm_signed ();
2819 }
2820 else if (insn.opcode () == riscv_insn::BLT)
2821 {
2822 LONGEST src1, src2;
2823 regcache->cooked_read (insn.rs1 (), &src1);
2824 regcache->cooked_read (insn.rs2 (), &src2);
2825 if (src1 < src2)
2826 next_pc = pc + insn.imm_signed ();
2827 }
2828 else if (insn.opcode () == riscv_insn::BGE)
2829 {
2830 LONGEST src1, src2;
2831 regcache->cooked_read (insn.rs1 (), &src1);
2832 regcache->cooked_read (insn.rs2 (), &src2);
2833 if (src1 >= src2)
2834 next_pc = pc + insn.imm_signed ();
2835 }
2836 else if (insn.opcode () == riscv_insn::BLTU)
2837 {
2838 ULONGEST src1, src2;
2839 regcache->cooked_read (insn.rs1 (), &src1);
2840 regcache->cooked_read (insn.rs2 (), &src2);
2841 if (src1 < src2)
2842 next_pc = pc + insn.imm_signed ();
2843 }
2844 else if (insn.opcode () == riscv_insn::BGEU)
2845 {
2846 ULONGEST src1, src2;
2847 regcache->cooked_read (insn.rs1 (), &src1);
2848 regcache->cooked_read (insn.rs2 (), &src2);
2849 if (src1 >= src2)
2850 next_pc = pc + insn.imm_signed ();
2851 }
2852
2853 return next_pc;
2854}
2855
2856/* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
2857 for the end of the sequence and put the breakpoint there. */
2858
2859static bool
2860riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc,
2861 CORE_ADDR *next_pc)
2862{
2863 struct gdbarch *gdbarch = regcache->arch ();
2864 struct riscv_insn insn;
2865 CORE_ADDR cur_step_pc = pc;
2866 CORE_ADDR last_addr = 0;
2867
2868 /* First instruction has to be a load reserved. */
2869 insn.decode (gdbarch, cur_step_pc);
2870 if (insn.opcode () != riscv_insn::LR)
2871 return false;
2872 cur_step_pc = cur_step_pc + insn.length ();
2873
2874 /* Next instruction should be branch to exit. */
2875 insn.decode (gdbarch, cur_step_pc);
2876 if (insn.opcode () != riscv_insn::BNE)
2877 return false;
2878 last_addr = cur_step_pc + insn.imm_signed ();
2879 cur_step_pc = cur_step_pc + insn.length ();
2880
2881 /* Next instruction should be store conditional. */
2882 insn.decode (gdbarch, cur_step_pc);
2883 if (insn.opcode () != riscv_insn::SC)
2884 return false;
2885 cur_step_pc = cur_step_pc + insn.length ();
2886
2887 /* Next instruction should be branch to start. */
2888 insn.decode (gdbarch, cur_step_pc);
2889 if (insn.opcode () != riscv_insn::BNE)
2890 return false;
2891 if (pc != (cur_step_pc + insn.imm_signed ()))
2892 return false;
2893 cur_step_pc = cur_step_pc + insn.length ();
2894
2895 /* We should now be at the end of the sequence. */
2896 if (cur_step_pc != last_addr)
2897 return false;
2898
2899 *next_pc = cur_step_pc;
2900 return true;
2901}
2902
2903/* This is called just before we want to resume the inferior, if we want to
2904 single-step it but there is no hardware or kernel single-step support. We
2905 find the target of the coming instruction and breakpoint it. */
2906
2907std::vector<CORE_ADDR>
2908riscv_software_single_step (struct regcache *regcache)
2909{
2910 CORE_ADDR pc, next_pc;
2911
2912 pc = regcache_read_pc (regcache);
2913
2914 if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc))
2915 return {next_pc};
2916
2917 next_pc = riscv_next_pc (regcache, pc);
2918
2919 return {next_pc};
2920}
2921
dbbb1059
AB		 2922void
2923_initialize_riscv_tdep (void)
2924{
2925 gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL);
2926
dbbb1059
AB		 2927 /* Add root prefix command for all "set debug riscv" and "show debug
2928 riscv" commands. */
2929 add_prefix_cmd ("riscv", no_class, set_debug_riscv_command,
2930 _("RISC-V specific debug commands."),
2931 &setdebugriscvcmdlist, "set debug riscv ", 0,
2932 &setdebuglist);
2933
2934 add_prefix_cmd ("riscv", no_class, show_debug_riscv_command,
2935 _("RISC-V specific debug commands."),
2936 &showdebugriscvcmdlist, "show debug riscv ", 0,
2937 &showdebuglist);
2938
2939 add_setshow_zuinteger_cmd ("infcall", class_maintenance,
2940 &riscv_debug_infcall, _("\
2941Set riscv inferior call debugging."), _("\
2942Show riscv inferior call debugging."), _("\
2943When non-zero, print debugging information for the riscv specific parts\n\
2944of the inferior call mechanism."),
2945 NULL,
2946 show_riscv_debug_variable,
2947 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
78a3b0fa
AB		 2948
2949 add_setshow_zuinteger_cmd ("unwinder", class_maintenance,
2950 &riscv_debug_unwinder, _("\
2951Set riscv stack unwinding debugging."), _("\
2952Show riscv stack unwinding debugging."), _("\
2953When non-zero, print debugging information for the riscv specific parts\n\
2954of the stack unwinding mechanism."),
2955 NULL,
2956 show_riscv_debug_variable,
2957 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
dbbb1059
AB		 2958
2959 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
2960 add_prefix_cmd ("riscv", no_class, set_riscv_command,
2961 _("RISC-V specific commands."),
2962 &setriscvcmdlist, "set riscv ", 0, &setlist);
2963
2964 add_prefix_cmd ("riscv", no_class, show_riscv_command,
2965 _("RISC-V specific commands."),
2966 &showriscvcmdlist, "show riscv ", 0, &showlist);
2967
2968
2969 use_compressed_breakpoints = AUTO_BOOLEAN_AUTO;
2970 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class,
2971 &use_compressed_breakpoints,
2972 _("\
2973Set debugger's use of compressed breakpoints."), _(" \
2974Show debugger's use of compressed breakpoints."), _("\
2975Debugging compressed code requires compressed breakpoints to be used. If\n \
2976left to 'auto' then gdb will use them if $misa indicates the C extension\n \
2977is supported. If that doesn't give the correct behavior, then this option\n\
2978can be used."),
2979 NULL,
2980 show_use_compressed_breakpoints,
2981 &setriscvcmdlist,
2982 &showriscvcmdlist);
2983}
GDB Binutils - Deliverables
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