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dbbb1059 AB |
1 | /* Target-dependent code for the RISC-V architecture, for GDB. |
2 | ||
3 | Copyright (C) 2018 Free Software Foundation, Inc. | |
4 | ||
dbbb1059 AB |
5 | This file is part of GDB. |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "inferior.h" | |
23 | #include "symtab.h" | |
24 | #include "value.h" | |
25 | #include "gdbcmd.h" | |
26 | #include "language.h" | |
27 | #include "gdbcore.h" | |
28 | #include "symfile.h" | |
29 | #include "objfiles.h" | |
30 | #include "gdbtypes.h" | |
31 | #include "target.h" | |
32 | #include "arch-utils.h" | |
33 | #include "regcache.h" | |
34 | #include "osabi.h" | |
35 | #include "riscv-tdep.h" | |
36 | #include "block.h" | |
37 | #include "reggroups.h" | |
38 | #include "opcode/riscv.h" | |
39 | #include "elf/riscv.h" | |
40 | #include "elf-bfd.h" | |
41 | #include "symcat.h" | |
42 | #include "dis-asm.h" | |
43 | #include "frame-unwind.h" | |
44 | #include "frame-base.h" | |
45 | #include "trad-frame.h" | |
46 | #include "infcall.h" | |
47 | #include "floatformat.h" | |
48 | #include "remote.h" | |
49 | #include "target-descriptions.h" | |
50 | #include "dwarf2-frame.h" | |
51 | #include "user-regs.h" | |
52 | #include "valprint.h" | |
53 | #include "common-defs.h" | |
54 | #include "opcode/riscv-opc.h" | |
55 | #include "cli/cli-decode.h" | |
76727919 | 56 | #include "observable.h" |
78a3b0fa | 57 | #include "prologue-value.h" |
dbbb1059 AB |
58 | |
59 | /* The stack must be 16-byte aligned. */ | |
60 | #define SP_ALIGNMENT 16 | |
61 | ||
ef2de9e7 JW |
62 | /* The biggest alignment that the target supports. */ |
63 | #define BIGGEST_ALIGNMENT 16 | |
64 | ||
dbbb1059 AB |
65 | /* Forward declarations. */ |
66 | static bool riscv_has_feature (struct gdbarch *gdbarch, char feature); | |
dbbb1059 AB |
67 | |
68 | /* Define a series of is_XXX_insn functions to check if the value INSN | |
69 | is an instance of instruction XXX. */ | |
70 | #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \ | |
71 | static inline bool is_ ## INSN_NAME ## _insn (long insn) \ | |
72 | { \ | |
73 | return (insn & INSN_MASK) == INSN_MATCH; \ | |
74 | } | |
75 | #include "opcode/riscv-opc.h" | |
76 | #undef DECLARE_INSN | |
77 | ||
78a3b0fa AB |
78 | /* Cached information about a frame. */ |
79 | ||
80 | struct riscv_unwind_cache | |
81 | { | |
82 | /* The register from which we can calculate the frame base. This is | |
83 | usually $sp or $fp. */ | |
84 | int frame_base_reg; | |
85 | ||
86 | /* The offset from the current value in register FRAME_BASE_REG to the | |
87 | actual frame base address. */ | |
88 | int frame_base_offset; | |
89 | ||
90 | /* Information about previous register values. */ | |
91 | struct trad_frame_saved_reg *regs; | |
92 | ||
93 | /* The id for this frame. */ | |
94 | struct frame_id this_id; | |
95 | ||
96 | /* The base (stack) address for this frame. This is the stack pointer | |
97 | value on entry to this frame before any adjustments are made. */ | |
98 | CORE_ADDR frame_base; | |
99 | }; | |
100 | ||
0dbfcfff AB |
101 | /* The preferred register names for all the general purpose and floating |
102 | point registers. These are what GDB will use when referencing a | |
103 | register. */ | |
dbbb1059 AB |
104 | |
105 | static const char * const riscv_gdb_reg_names[RISCV_LAST_FP_REGNUM + 1] = | |
106 | { | |
0dbfcfff AB |
107 | "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1", |
108 | "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", | |
109 | "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", | |
110 | "pc", | |
111 | "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1", | |
112 | "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", "fs2", "fs3", | |
113 | "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", | |
114 | "ft10", "ft11", | |
dbbb1059 AB |
115 | }; |
116 | ||
0dbfcfff | 117 | /* Map alternative register names onto their GDB register number. */ |
dbbb1059 | 118 | |
0dbfcfff | 119 | struct riscv_register_alias |
dbbb1059 AB |
120 | { |
121 | /* The register alias. Usually more descriptive than the | |
122 | architectural name of the register. */ | |
123 | const char *name; | |
124 | ||
125 | /* The GDB register number. */ | |
126 | int regnum; | |
127 | }; | |
128 | ||
129 | /* Table of register aliases. */ | |
130 | ||
0dbfcfff | 131 | static const struct riscv_register_alias riscv_register_aliases[] = |
dbbb1059 | 132 | { |
0dbfcfff AB |
133 | /* Aliases for general purpose registers. These are the architectural |
134 | names, as GDB uses the more user friendly names by default. */ | |
135 | { "x0", (RISCV_ZERO_REGNUM + 0) }, | |
136 | { "x1", (RISCV_ZERO_REGNUM + 1) }, | |
137 | { "x2", (RISCV_ZERO_REGNUM + 2) }, | |
138 | { "x3", (RISCV_ZERO_REGNUM + 3) }, | |
139 | { "x4", (RISCV_ZERO_REGNUM + 4) }, | |
140 | { "x5", (RISCV_ZERO_REGNUM + 5) }, | |
141 | { "x6", (RISCV_ZERO_REGNUM + 6) }, | |
142 | { "x7", (RISCV_ZERO_REGNUM + 7) }, | |
143 | { "x8", (RISCV_ZERO_REGNUM + 8) }, | |
144 | { "s0", (RISCV_ZERO_REGNUM + 8) }, /* fp, s0, and x8 are all aliases. */ | |
145 | { "x9", (RISCV_ZERO_REGNUM + 9) }, | |
146 | { "x10", (RISCV_ZERO_REGNUM + 10) }, | |
147 | { "x11", (RISCV_ZERO_REGNUM + 11) }, | |
148 | { "x12", (RISCV_ZERO_REGNUM + 12) }, | |
149 | { "x13", (RISCV_ZERO_REGNUM + 13) }, | |
150 | { "x14", (RISCV_ZERO_REGNUM + 14) }, | |
151 | { "x15", (RISCV_ZERO_REGNUM + 15) }, | |
152 | { "x16", (RISCV_ZERO_REGNUM + 16) }, | |
153 | { "x17", (RISCV_ZERO_REGNUM + 17) }, | |
154 | { "x18", (RISCV_ZERO_REGNUM + 18) }, | |
155 | { "x19", (RISCV_ZERO_REGNUM + 19) }, | |
156 | { "x20", (RISCV_ZERO_REGNUM + 20) }, | |
157 | { "x21", (RISCV_ZERO_REGNUM + 21) }, | |
158 | { "x22", (RISCV_ZERO_REGNUM + 22) }, | |
159 | { "x23", (RISCV_ZERO_REGNUM + 23) }, | |
160 | { "x24", (RISCV_ZERO_REGNUM + 24) }, | |
161 | { "x25", (RISCV_ZERO_REGNUM + 25) }, | |
162 | { "x26", (RISCV_ZERO_REGNUM + 26) }, | |
163 | { "x27", (RISCV_ZERO_REGNUM + 27) }, | |
164 | { "x28", (RISCV_ZERO_REGNUM + 28) }, | |
165 | { "x29", (RISCV_ZERO_REGNUM + 29) }, | |
166 | { "x30", (RISCV_ZERO_REGNUM + 30) }, | |
167 | { "x31", (RISCV_ZERO_REGNUM + 31) }, | |
168 | ||
169 | /* Aliases for the floating-point registers. These are the architectural | |
170 | names as GDB uses the more user friendly names by default. */ | |
171 | { "f0", (RISCV_FIRST_FP_REGNUM + 0) }, | |
172 | { "f1", (RISCV_FIRST_FP_REGNUM + 1) }, | |
173 | { "f2", (RISCV_FIRST_FP_REGNUM + 2) }, | |
174 | { "f3", (RISCV_FIRST_FP_REGNUM + 3) }, | |
175 | { "f4", (RISCV_FIRST_FP_REGNUM + 4) }, | |
176 | { "f5", (RISCV_FIRST_FP_REGNUM + 5) }, | |
177 | { "f6", (RISCV_FIRST_FP_REGNUM + 6) }, | |
178 | { "f7", (RISCV_FIRST_FP_REGNUM + 7) }, | |
179 | { "f8", (RISCV_FIRST_FP_REGNUM + 8) }, | |
180 | { "f9", (RISCV_FIRST_FP_REGNUM + 9) }, | |
181 | { "f10", (RISCV_FIRST_FP_REGNUM + 10) }, | |
182 | { "f11", (RISCV_FIRST_FP_REGNUM + 11) }, | |
183 | { "f12", (RISCV_FIRST_FP_REGNUM + 12) }, | |
184 | { "f13", (RISCV_FIRST_FP_REGNUM + 13) }, | |
185 | { "f14", (RISCV_FIRST_FP_REGNUM + 14) }, | |
186 | { "f15", (RISCV_FIRST_FP_REGNUM + 15) }, | |
187 | { "f16", (RISCV_FIRST_FP_REGNUM + 16) }, | |
188 | { "f17", (RISCV_FIRST_FP_REGNUM + 17) }, | |
189 | { "f18", (RISCV_FIRST_FP_REGNUM + 18) }, | |
190 | { "f19", (RISCV_FIRST_FP_REGNUM + 19) }, | |
191 | { "f20", (RISCV_FIRST_FP_REGNUM + 20) }, | |
192 | { "f21", (RISCV_FIRST_FP_REGNUM + 21) }, | |
193 | { "f22", (RISCV_FIRST_FP_REGNUM + 22) }, | |
194 | { "f23", (RISCV_FIRST_FP_REGNUM + 23) }, | |
195 | { "f24", (RISCV_FIRST_FP_REGNUM + 24) }, | |
196 | { "f25", (RISCV_FIRST_FP_REGNUM + 25) }, | |
197 | { "f26", (RISCV_FIRST_FP_REGNUM + 26) }, | |
198 | { "f27", (RISCV_FIRST_FP_REGNUM + 27) }, | |
199 | { "f28", (RISCV_FIRST_FP_REGNUM + 28) }, | |
200 | { "f29", (RISCV_FIRST_FP_REGNUM + 29) }, | |
201 | { "f30", (RISCV_FIRST_FP_REGNUM + 30) }, | |
202 | { "f31", (RISCV_FIRST_FP_REGNUM + 31) }, | |
dbbb1059 AB |
203 | }; |
204 | ||
205 | /* Controls whether we place compressed breakpoints or not. When in auto | |
206 | mode GDB tries to determine if the target supports compressed | |
207 | breakpoints, and uses them if it does. */ | |
208 | ||
209 | static enum auto_boolean use_compressed_breakpoints; | |
210 | ||
211 | /* The show callback for 'show riscv use-compressed-breakpoints'. */ | |
212 | ||
213 | static void | |
214 | show_use_compressed_breakpoints (struct ui_file *file, int from_tty, | |
215 | struct cmd_list_element *c, | |
216 | const char *value) | |
217 | { | |
dbbb1059 AB |
218 | fprintf_filtered (file, |
219 | _("Debugger's use of compressed breakpoints is set " | |
f37bc8b1 | 220 | "to %s.\n"), value); |
dbbb1059 AB |
221 | } |
222 | ||
223 | /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */ | |
224 | ||
225 | static struct cmd_list_element *setriscvcmdlist = NULL; | |
226 | static struct cmd_list_element *showriscvcmdlist = NULL; | |
227 | ||
228 | /* The show callback for the 'show riscv' prefix command. */ | |
229 | ||
230 | static void | |
231 | show_riscv_command (const char *args, int from_tty) | |
232 | { | |
233 | help_list (showriscvcmdlist, "show riscv ", all_commands, gdb_stdout); | |
234 | } | |
235 | ||
236 | /* The set callback for the 'set riscv' prefix command. */ | |
237 | ||
238 | static void | |
239 | set_riscv_command (const char *args, int from_tty) | |
240 | { | |
241 | printf_unfiltered | |
242 | (_("\"set riscv\" must be followed by an appropriate subcommand.\n")); | |
243 | help_list (setriscvcmdlist, "set riscv ", all_commands, gdb_stdout); | |
244 | } | |
245 | ||
246 | /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */ | |
247 | ||
248 | static struct cmd_list_element *setdebugriscvcmdlist = NULL; | |
249 | static struct cmd_list_element *showdebugriscvcmdlist = NULL; | |
250 | ||
251 | /* The show callback for the 'show debug riscv' prefix command. */ | |
252 | ||
253 | static void | |
254 | show_debug_riscv_command (const char *args, int from_tty) | |
255 | { | |
256 | help_list (showdebugriscvcmdlist, "show debug riscv ", all_commands, gdb_stdout); | |
257 | } | |
258 | ||
259 | /* The set callback for the 'set debug riscv' prefix command. */ | |
260 | ||
261 | static void | |
262 | set_debug_riscv_command (const char *args, int from_tty) | |
263 | { | |
264 | printf_unfiltered | |
265 | (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n")); | |
266 | help_list (setdebugriscvcmdlist, "set debug riscv ", all_commands, gdb_stdout); | |
267 | } | |
268 | ||
269 | /* The show callback for all 'show debug riscv VARNAME' variables. */ | |
270 | ||
271 | static void | |
272 | show_riscv_debug_variable (struct ui_file *file, int from_tty, | |
273 | struct cmd_list_element *c, | |
274 | const char *value) | |
275 | { | |
276 | fprintf_filtered (file, | |
277 | _("RiscV debug variable `%s' is set to: %s\n"), | |
278 | c->name, value); | |
279 | } | |
280 | ||
f37bc8b1 JB |
281 | /* When this is set to non-zero debugging information about breakpoint |
282 | kinds will be printed. */ | |
283 | ||
284 | static unsigned int riscv_debug_breakpoints = 0; | |
285 | ||
dbbb1059 AB |
286 | /* When this is set to non-zero debugging information about inferior calls |
287 | will be printed. */ | |
288 | ||
289 | static unsigned int riscv_debug_infcall = 0; | |
290 | ||
78a3b0fa AB |
291 | /* When this is set to non-zero debugging information about stack unwinding |
292 | will be printed. */ | |
293 | ||
294 | static unsigned int riscv_debug_unwinder = 0; | |
295 | ||
0b0eff8b AB |
296 | /* Read the MISA register from the target. There are a couple of locations |
297 | that the register might be found, these are all tried. If the MISA | |
298 | register can't be found at all then the default value of 0 is returned, | |
299 | this is inline with the RISC-V specification. */ | |
dbbb1059 AB |
300 | |
301 | static uint32_t | |
0b0eff8b | 302 | riscv_read_misa_reg () |
dbbb1059 | 303 | { |
0b3f9efc | 304 | uint32_t value = 0; |
dbbb1059 | 305 | |
0b3f9efc | 306 | if (target_has_registers) |
dbbb1059 | 307 | { |
0b0eff8b AB |
308 | /* Old cores might have MISA located at a different offset. */ |
309 | static int misa_regs[] = | |
310 | { RISCV_CSR_MISA_REGNUM, RISCV_CSR_LEGACY_MISA_REGNUM }; | |
311 | ||
dbbb1059 AB |
312 | struct frame_info *frame = get_current_frame (); |
313 | ||
0b0eff8b | 314 | for (int i = 0; i < ARRAY_SIZE (misa_regs); ++i) |
dbbb1059 | 315 | { |
0b0eff8b AB |
316 | bool success = false; |
317 | ||
318 | TRY | |
319 | { | |
320 | value = get_frame_register_unsigned (frame, misa_regs[i]); | |
321 | success = true; | |
322 | } | |
323 | CATCH (ex, RETURN_MASK_ERROR) | |
324 | { | |
325 | /* Ignore errors, it is acceptable for a target to not | |
326 | provide a MISA register, in which case the default value | |
327 | of 0 should be used. */ | |
328 | } | |
329 | END_CATCH | |
330 | ||
331 | if (success) | |
332 | break; | |
dbbb1059 | 333 | } |
dbbb1059 AB |
334 | } |
335 | ||
0b3f9efc | 336 | return value; |
dbbb1059 AB |
337 | } |
338 | ||
339 | /* Return true if FEATURE is available for the architecture GDBARCH. The | |
340 | FEATURE should be one of the single character feature codes described in | |
341 | the RiscV ISA manual, these are between 'A' and 'Z'. */ | |
342 | ||
343 | static bool | |
344 | riscv_has_feature (struct gdbarch *gdbarch, char feature) | |
345 | { | |
dbbb1059 AB |
346 | gdb_assert (feature >= 'A' && feature <= 'Z'); |
347 | ||
0b0eff8b AB |
348 | uint32_t misa = riscv_read_misa_reg (); |
349 | if (misa == 0) | |
dbbb1059 AB |
350 | misa = gdbarch_tdep (gdbarch)->core_features; |
351 | ||
352 | return (misa & (1 << (feature - 'A'))) != 0; | |
353 | } | |
354 | ||
8a613826 | 355 | /* See riscv-tdep.h. */ |
dbbb1059 | 356 | |
411baa47 | 357 | int |
dbbb1059 AB |
358 | riscv_isa_xlen (struct gdbarch *gdbarch) |
359 | { | |
360 | switch (gdbarch_tdep (gdbarch)->abi.fields.base_len) | |
361 | { | |
362 | default: | |
363 | warning (_("unknown xlen size, assuming 4 bytes")); | |
565e0eda | 364 | /* Fall through. */ |
dbbb1059 AB |
365 | case 1: |
366 | return 4; | |
367 | case 2: | |
368 | return 8; | |
369 | case 3: | |
370 | return 16; | |
371 | } | |
372 | } | |
373 | ||
8a613826 | 374 | /* See riscv-tdep.h. */ |
dbbb1059 | 375 | |
8a613826 | 376 | int |
dbbb1059 AB |
377 | riscv_isa_flen (struct gdbarch *gdbarch) |
378 | { | |
379 | if (riscv_has_feature (gdbarch, 'Q')) | |
380 | return 16; | |
381 | else if (riscv_has_feature (gdbarch, 'D')) | |
382 | return 8; | |
383 | else if (riscv_has_feature (gdbarch, 'F')) | |
384 | return 4; | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
389 | /* Return true if the target for GDBARCH has floating point hardware. */ | |
390 | ||
391 | static bool | |
392 | riscv_has_fp_regs (struct gdbarch *gdbarch) | |
393 | { | |
394 | return (riscv_isa_flen (gdbarch) > 0); | |
395 | } | |
396 | ||
397 | /* Return true if GDBARCH is using any of the floating point hardware ABIs. */ | |
398 | ||
399 | static bool | |
400 | riscv_has_fp_abi (struct gdbarch *gdbarch) | |
401 | { | |
402 | return (gdbarch_tdep (gdbarch)->abi.fields.float_abi != 0); | |
403 | } | |
404 | ||
8c49aa89 AB |
405 | /* Return true if REGNO is a floating pointer register. */ |
406 | ||
407 | static bool | |
408 | riscv_is_fp_regno_p (int regno) | |
409 | { | |
410 | return (regno >= RISCV_FIRST_FP_REGNUM | |
411 | && regno <= RISCV_LAST_FP_REGNUM); | |
412 | } | |
413 | ||
dbbb1059 AB |
414 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
415 | ||
416 | static int | |
417 | riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
418 | { | |
419 | if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO) | |
420 | { | |
3ba2ee38 | 421 | bool unaligned_p = false; |
f37bc8b1 JB |
422 | gdb_byte buf[1]; |
423 | ||
3ba2ee38 JW |
424 | /* Some targets don't support unaligned reads. The address can only |
425 | be unaligned if the C extension is supported. So it is safe to | |
426 | use a compressed breakpoint in this case. */ | |
427 | if (*pcptr & 0x2) | |
428 | unaligned_p = true; | |
429 | else | |
430 | { | |
431 | /* Read the opcode byte to determine the instruction length. */ | |
432 | read_code (*pcptr, buf, 1); | |
433 | } | |
f37bc8b1 JB |
434 | |
435 | if (riscv_debug_breakpoints) | |
3ba2ee38 JW |
436 | { |
437 | const char *bp = (unaligned_p || riscv_insn_length (buf[0]) == 2 | |
438 | ? "C.EBREAK" : "EBREAK"); | |
439 | ||
440 | fprintf_unfiltered (gdb_stdlog, "Using %s for breakpoint at %s ", | |
441 | bp, paddress (gdbarch, *pcptr)); | |
442 | if (unaligned_p) | |
443 | fprintf_unfiltered (gdb_stdlog, "(unaligned address)\n"); | |
444 | else | |
445 | fprintf_unfiltered (gdb_stdlog, "(instruction length %d)\n", | |
446 | riscv_insn_length (buf[0])); | |
447 | } | |
448 | if (unaligned_p || riscv_insn_length (buf[0]) == 2) | |
dbbb1059 AB |
449 | return 2; |
450 | else | |
451 | return 4; | |
452 | } | |
453 | else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE) | |
454 | return 2; | |
455 | else | |
456 | return 4; | |
457 | } | |
458 | ||
459 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ | |
460 | ||
461 | static const gdb_byte * | |
462 | riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
463 | { | |
464 | static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, }; | |
465 | static const gdb_byte c_ebreak[] = { 0x02, 0x90 }; | |
466 | ||
467 | *size = kind; | |
468 | switch (kind) | |
469 | { | |
470 | case 2: | |
471 | return c_ebreak; | |
472 | case 4: | |
473 | return ebreak; | |
474 | default: | |
89a3b63e | 475 | gdb_assert_not_reached (_("unhandled breakpoint kind")); |
dbbb1059 AB |
476 | } |
477 | } | |
478 | ||
479 | /* Callback function for user_reg_add. */ | |
480 | ||
481 | static struct value * | |
482 | value_of_riscv_user_reg (struct frame_info *frame, const void *baton) | |
483 | { | |
484 | const int *reg_p = (const int *) baton; | |
485 | return value_of_register (*reg_p, frame); | |
486 | } | |
487 | ||
488 | /* Implement the register_name gdbarch method. */ | |
489 | ||
490 | static const char * | |
491 | riscv_register_name (struct gdbarch *gdbarch, int regnum) | |
492 | { | |
dbbb1059 | 493 | /* Prefer to use the alias. */ |
0dbfcfff | 494 | if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_FP_REGNUM) |
dbbb1059 | 495 | { |
0dbfcfff AB |
496 | gdb_assert (regnum < ARRAY_SIZE (riscv_gdb_reg_names)); |
497 | return riscv_gdb_reg_names[regnum]; | |
dbbb1059 AB |
498 | } |
499 | ||
0dbfcfff AB |
500 | /* Check that there's no gap between the set of registers handled above, |
501 | and the set of registers handled next. */ | |
502 | gdb_assert ((RISCV_LAST_FP_REGNUM + 1) == RISCV_FIRST_CSR_REGNUM); | |
dbbb1059 AB |
503 | |
504 | if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM) | |
505 | { | |
420ecd9c AB |
506 | #define DECLARE_CSR(NAME,VALUE) \ |
507 | case RISCV_ ## VALUE ## _REGNUM: return # NAME; | |
dbbb1059 | 508 | |
420ecd9c AB |
509 | switch (regnum) |
510 | { | |
511 | #include "opcode/riscv-opc.h" | |
512 | default: | |
513 | { | |
514 | static char buf[20]; | |
515 | ||
516 | xsnprintf (buf, sizeof (buf), "csr%d", | |
517 | regnum - RISCV_FIRST_CSR_REGNUM); | |
518 | return buf; | |
519 | } | |
520 | } | |
521 | #undef DECLARE_CSR | |
dbbb1059 AB |
522 | } |
523 | ||
524 | if (regnum == RISCV_PRIV_REGNUM) | |
525 | return "priv"; | |
526 | ||
527 | return NULL; | |
528 | } | |
529 | ||
270b9329 JW |
530 | /* Construct a type for 64-bit FP registers. */ |
531 | ||
532 | static struct type * | |
533 | riscv_fpreg_d_type (struct gdbarch *gdbarch) | |
534 | { | |
535 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
536 | ||
537 | if (tdep->riscv_fpreg_d_type == nullptr) | |
538 | { | |
539 | const struct builtin_type *bt = builtin_type (gdbarch); | |
540 | ||
541 | /* The type we're building is this: */ | |
542 | #if 0 | |
543 | union __gdb_builtin_type_fpreg_d | |
544 | { | |
545 | float f; | |
546 | double d; | |
547 | }; | |
548 | #endif | |
549 | ||
550 | struct type *t; | |
551 | ||
552 | t = arch_composite_type (gdbarch, | |
553 | "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION); | |
554 | append_composite_type_field (t, "float", bt->builtin_float); | |
555 | append_composite_type_field (t, "double", bt->builtin_double); | |
556 | TYPE_VECTOR (t) = 1; | |
557 | TYPE_NAME (t) = "builtin_type_fpreg_d"; | |
558 | tdep->riscv_fpreg_d_type = t; | |
559 | } | |
560 | ||
561 | return tdep->riscv_fpreg_d_type; | |
562 | } | |
563 | ||
564 | /* Construct a type for 128-bit FP registers. */ | |
565 | ||
566 | static struct type * | |
567 | riscv_fpreg_q_type (struct gdbarch *gdbarch) | |
568 | { | |
569 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
570 | ||
571 | if (tdep->riscv_fpreg_q_type == nullptr) | |
572 | { | |
573 | const struct builtin_type *bt = builtin_type (gdbarch); | |
574 | ||
575 | /* The type we're building is this: */ | |
576 | #if 0 | |
577 | union __gdb_builtin_type_fpreg_d | |
578 | { | |
579 | float f; | |
580 | double d; | |
581 | long double ld; | |
582 | }; | |
583 | #endif | |
584 | ||
585 | struct type *t; | |
586 | ||
587 | t = arch_composite_type (gdbarch, | |
588 | "__gdb_builtin_type_fpreg_q", TYPE_CODE_UNION); | |
589 | append_composite_type_field (t, "float", bt->builtin_float); | |
590 | append_composite_type_field (t, "double", bt->builtin_double); | |
591 | append_composite_type_field (t, "long double", bt->builtin_long_double); | |
592 | TYPE_VECTOR (t) = 1; | |
593 | TYPE_NAME (t) = "builtin_type_fpreg_q"; | |
594 | tdep->riscv_fpreg_q_type = t; | |
595 | } | |
596 | ||
597 | return tdep->riscv_fpreg_q_type; | |
598 | } | |
599 | ||
dbbb1059 AB |
600 | /* Implement the register_type gdbarch method. */ |
601 | ||
602 | static struct type * | |
603 | riscv_register_type (struct gdbarch *gdbarch, int regnum) | |
604 | { | |
605 | int regsize; | |
606 | ||
607 | if (regnum < RISCV_FIRST_FP_REGNUM) | |
608 | { | |
609 | if (regnum == gdbarch_pc_regnum (gdbarch) | |
610 | || regnum == RISCV_RA_REGNUM) | |
611 | return builtin_type (gdbarch)->builtin_func_ptr; | |
612 | ||
613 | if (regnum == RISCV_FP_REGNUM | |
614 | || regnum == RISCV_SP_REGNUM | |
615 | || regnum == RISCV_GP_REGNUM | |
616 | || regnum == RISCV_TP_REGNUM) | |
617 | return builtin_type (gdbarch)->builtin_data_ptr; | |
618 | ||
619 | /* Remaining GPRs vary in size based on the current ISA. */ | |
620 | regsize = riscv_isa_xlen (gdbarch); | |
621 | switch (regsize) | |
622 | { | |
623 | case 4: | |
624 | return builtin_type (gdbarch)->builtin_uint32; | |
625 | case 8: | |
626 | return builtin_type (gdbarch)->builtin_uint64; | |
627 | case 16: | |
628 | return builtin_type (gdbarch)->builtin_uint128; | |
629 | default: | |
630 | internal_error (__FILE__, __LINE__, | |
631 | _("unknown isa regsize %i"), regsize); | |
632 | } | |
633 | } | |
634 | else if (regnum <= RISCV_LAST_FP_REGNUM) | |
635 | { | |
636 | regsize = riscv_isa_xlen (gdbarch); | |
637 | switch (regsize) | |
638 | { | |
639 | case 4: | |
640 | return builtin_type (gdbarch)->builtin_float; | |
641 | case 8: | |
270b9329 | 642 | return riscv_fpreg_d_type (gdbarch); |
dbbb1059 | 643 | case 16: |
270b9329 | 644 | return riscv_fpreg_q_type (gdbarch); |
dbbb1059 AB |
645 | default: |
646 | internal_error (__FILE__, __LINE__, | |
647 | _("unknown isa regsize %i"), regsize); | |
648 | } | |
649 | } | |
650 | else if (regnum == RISCV_PRIV_REGNUM) | |
651 | return builtin_type (gdbarch)->builtin_int8; | |
652 | else | |
653 | { | |
654 | if (regnum == RISCV_CSR_FFLAGS_REGNUM | |
655 | || regnum == RISCV_CSR_FRM_REGNUM | |
656 | || regnum == RISCV_CSR_FCSR_REGNUM) | |
657 | return builtin_type (gdbarch)->builtin_int32; | |
658 | ||
659 | regsize = riscv_isa_xlen (gdbarch); | |
660 | switch (regsize) | |
661 | { | |
662 | case 4: | |
663 | return builtin_type (gdbarch)->builtin_int32; | |
664 | case 8: | |
665 | return builtin_type (gdbarch)->builtin_int64; | |
666 | case 16: | |
667 | return builtin_type (gdbarch)->builtin_int128; | |
668 | default: | |
669 | internal_error (__FILE__, __LINE__, | |
670 | _("unknown isa regsize %i"), regsize); | |
671 | } | |
672 | } | |
673 | } | |
674 | ||
675 | /* Helper for riscv_print_registers_info, prints info for a single register | |
676 | REGNUM. */ | |
677 | ||
678 | static void | |
679 | riscv_print_one_register_info (struct gdbarch *gdbarch, | |
680 | struct ui_file *file, | |
681 | struct frame_info *frame, | |
682 | int regnum) | |
683 | { | |
684 | const char *name = gdbarch_register_name (gdbarch, regnum); | |
685 | struct value *val = value_of_register (regnum, frame); | |
686 | struct type *regtype = value_type (val); | |
687 | int print_raw_format; | |
688 | enum tab_stops { value_column_1 = 15 }; | |
689 | ||
690 | fputs_filtered (name, file); | |
691 | print_spaces_filtered (value_column_1 - strlen (name), file); | |
692 | ||
693 | print_raw_format = (value_entirely_available (val) | |
694 | && !value_optimized_out (val)); | |
695 | ||
270b9329 JW |
696 | if (TYPE_CODE (regtype) == TYPE_CODE_FLT |
697 | || (TYPE_CODE (regtype) == TYPE_CODE_UNION | |
698 | && TYPE_NFIELDS (regtype) == 2 | |
699 | && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT | |
700 | && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT) | |
701 | || (TYPE_CODE (regtype) == TYPE_CODE_UNION | |
702 | && TYPE_NFIELDS (regtype) == 3 | |
703 | && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT | |
704 | && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT | |
705 | && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 2)) == TYPE_CODE_FLT)) | |
dbbb1059 AB |
706 | { |
707 | struct value_print_options opts; | |
708 | const gdb_byte *valaddr = value_contents_for_printing (val); | |
709 | enum bfd_endian byte_order = gdbarch_byte_order (get_type_arch (regtype)); | |
710 | ||
711 | get_user_print_options (&opts); | |
712 | opts.deref_ref = 1; | |
713 | ||
714 | val_print (regtype, | |
715 | value_embedded_offset (val), 0, | |
716 | file, 0, val, &opts, current_language); | |
717 | ||
718 | if (print_raw_format) | |
719 | { | |
720 | fprintf_filtered (file, "\t(raw "); | |
721 | print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order, | |
722 | true); | |
723 | fprintf_filtered (file, ")"); | |
724 | } | |
725 | } | |
726 | else | |
727 | { | |
728 | struct value_print_options opts; | |
729 | ||
730 | /* Print the register in hex. */ | |
731 | get_formatted_print_options (&opts, 'x'); | |
732 | opts.deref_ref = 1; | |
733 | val_print (regtype, | |
734 | value_embedded_offset (val), 0, | |
735 | file, 0, val, &opts, current_language); | |
736 | ||
737 | if (print_raw_format) | |
738 | { | |
739 | if (regnum == RISCV_CSR_MSTATUS_REGNUM) | |
740 | { | |
741 | LONGEST d; | |
742 | int size = register_size (gdbarch, regnum); | |
743 | unsigned xlen; | |
744 | ||
745 | d = value_as_long (val); | |
746 | xlen = size * 4; | |
747 | fprintf_filtered (file, | |
748 | "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X " | |
749 | "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X " | |
750 | "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X", | |
751 | (int) ((d >> (xlen - 1)) & 0x1), | |
752 | (int) ((d >> 24) & 0x1f), | |
753 | (int) ((d >> 19) & 0x1), | |
754 | (int) ((d >> 18) & 0x1), | |
755 | (int) ((d >> 17) & 0x1), | |
756 | (int) ((d >> 15) & 0x3), | |
757 | (int) ((d >> 13) & 0x3), | |
758 | (int) ((d >> 11) & 0x3), | |
759 | (int) ((d >> 9) & 0x3), | |
760 | (int) ((d >> 8) & 0x1), | |
761 | (int) ((d >> 7) & 0x1), | |
762 | (int) ((d >> 6) & 0x1), | |
763 | (int) ((d >> 5) & 0x1), | |
764 | (int) ((d >> 4) & 0x1), | |
765 | (int) ((d >> 3) & 0x1), | |
766 | (int) ((d >> 2) & 0x1), | |
767 | (int) ((d >> 1) & 0x1), | |
768 | (int) ((d >> 0) & 0x1)); | |
769 | } | |
770 | else if (regnum == RISCV_CSR_MISA_REGNUM) | |
771 | { | |
772 | int base; | |
773 | unsigned xlen, i; | |
774 | LONGEST d; | |
775 | ||
776 | d = value_as_long (val); | |
777 | base = d >> 30; | |
778 | xlen = 16; | |
779 | ||
780 | for (; base > 0; base--) | |
781 | xlen *= 2; | |
782 | fprintf_filtered (file, "\tRV%d", xlen); | |
783 | ||
784 | for (i = 0; i < 26; i++) | |
785 | { | |
786 | if (d & (1 << i)) | |
787 | fprintf_filtered (file, "%c", 'A' + i); | |
788 | } | |
789 | } | |
790 | else if (regnum == RISCV_CSR_FCSR_REGNUM | |
791 | || regnum == RISCV_CSR_FFLAGS_REGNUM | |
792 | || regnum == RISCV_CSR_FRM_REGNUM) | |
793 | { | |
794 | LONGEST d; | |
795 | ||
796 | d = value_as_long (val); | |
797 | ||
798 | fprintf_filtered (file, "\t"); | |
799 | if (regnum != RISCV_CSR_FRM_REGNUM) | |
800 | fprintf_filtered (file, | |
801 | "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d", | |
802 | (int) ((d >> 5) & 0x7), | |
803 | (int) ((d >> 4) & 0x1), | |
804 | (int) ((d >> 3) & 0x1), | |
805 | (int) ((d >> 2) & 0x1), | |
806 | (int) ((d >> 1) & 0x1), | |
807 | (int) ((d >> 0) & 0x1)); | |
808 | ||
809 | if (regnum != RISCV_CSR_FFLAGS_REGNUM) | |
810 | { | |
811 | static const char * const sfrm[] = | |
812 | { | |
813 | "RNE (round to nearest; ties to even)", | |
814 | "RTZ (Round towards zero)", | |
815 | "RDN (Round down towards -INF)", | |
816 | "RUP (Round up towards +INF)", | |
817 | "RMM (Round to nearest; ties to max magnitude)", | |
818 | "INVALID[5]", | |
819 | "INVALID[6]", | |
820 | "dynamic rounding mode", | |
821 | }; | |
822 | int frm = ((regnum == RISCV_CSR_FCSR_REGNUM) | |
823 | ? (d >> 5) : d) & 0x3; | |
824 | ||
825 | fprintf_filtered (file, "%sFRM:%i [%s]", | |
826 | (regnum == RISCV_CSR_FCSR_REGNUM | |
827 | ? " " : ""), | |
828 | frm, sfrm[frm]); | |
829 | } | |
830 | } | |
831 | else if (regnum == RISCV_PRIV_REGNUM) | |
832 | { | |
833 | LONGEST d; | |
834 | uint8_t priv; | |
835 | ||
836 | d = value_as_long (val); | |
837 | priv = d & 0xff; | |
838 | ||
839 | if (priv < 4) | |
840 | { | |
841 | static const char * const sprv[] = | |
842 | { | |
843 | "User/Application", | |
844 | "Supervisor", | |
845 | "Hypervisor", | |
846 | "Machine" | |
847 | }; | |
848 | fprintf_filtered (file, "\tprv:%d [%s]", | |
849 | priv, sprv[priv]); | |
850 | } | |
851 | else | |
852 | fprintf_filtered (file, "\tprv:%d [INVALID]", priv); | |
853 | } | |
854 | else | |
855 | { | |
856 | /* If not a vector register, print it also according to its | |
857 | natural format. */ | |
858 | if (TYPE_VECTOR (regtype) == 0) | |
859 | { | |
860 | get_user_print_options (&opts); | |
861 | opts.deref_ref = 1; | |
862 | fprintf_filtered (file, "\t"); | |
863 | val_print (regtype, | |
864 | value_embedded_offset (val), 0, | |
865 | file, 0, val, &opts, current_language); | |
866 | } | |
867 | } | |
868 | } | |
869 | } | |
870 | fprintf_filtered (file, "\n"); | |
871 | } | |
872 | ||
0dbfcfff AB |
873 | /* Return true if REGNUM is a valid CSR register. The CSR register space |
874 | is sparsely populated, so not every number is a named CSR. */ | |
875 | ||
876 | static bool | |
877 | riscv_is_regnum_a_named_csr (int regnum) | |
878 | { | |
879 | gdb_assert (regnum >= RISCV_FIRST_CSR_REGNUM | |
880 | && regnum <= RISCV_LAST_CSR_REGNUM); | |
881 | ||
882 | switch (regnum) | |
883 | { | |
884 | #define DECLARE_CSR(name, num) case RISCV_ ## num ## _REGNUM: | |
885 | #include "opcode/riscv-opc.h" | |
886 | #undef DECLARE_CSR | |
887 | return true; | |
888 | ||
889 | default: | |
890 | return false; | |
891 | } | |
892 | } | |
893 | ||
dbbb1059 AB |
894 | /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member |
895 | of REGGROUP? */ | |
896 | ||
897 | static int | |
898 | riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
899 | struct reggroup *reggroup) | |
900 | { | |
dbbb1059 AB |
901 | /* Used by 'info registers' and 'info registers <groupname>'. */ |
902 | ||
903 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
904 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
905 | return 0; | |
906 | ||
907 | if (reggroup == all_reggroup) | |
908 | { | |
909 | if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM) | |
910 | return 1; | |
0dbfcfff AB |
911 | if (riscv_is_regnum_a_named_csr (regnum)) |
912 | return 1; | |
dbbb1059 AB |
913 | return 0; |
914 | } | |
915 | else if (reggroup == float_reggroup) | |
8c49aa89 AB |
916 | return (riscv_is_fp_regno_p (regnum) |
917 | || regnum == RISCV_CSR_FCSR_REGNUM | |
918 | || regnum == RISCV_CSR_FFLAGS_REGNUM | |
919 | || regnum == RISCV_CSR_FRM_REGNUM); | |
dbbb1059 AB |
920 | else if (reggroup == general_reggroup) |
921 | return regnum < RISCV_FIRST_FP_REGNUM; | |
922 | else if (reggroup == restore_reggroup || reggroup == save_reggroup) | |
923 | { | |
924 | if (riscv_has_fp_regs (gdbarch)) | |
925 | return regnum <= RISCV_LAST_FP_REGNUM; | |
926 | else | |
927 | return regnum < RISCV_FIRST_FP_REGNUM; | |
928 | } | |
929 | else if (reggroup == system_reggroup) | |
930 | { | |
931 | if (regnum == RISCV_PRIV_REGNUM) | |
932 | return 1; | |
933 | if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM) | |
934 | return 0; | |
0dbfcfff AB |
935 | if (riscv_is_regnum_a_named_csr (regnum)) |
936 | return 1; | |
dbbb1059 AB |
937 | return 0; |
938 | } | |
939 | else if (reggroup == vector_reggroup) | |
940 | return 0; | |
941 | else | |
942 | return 0; | |
943 | } | |
944 | ||
945 | /* Implement the print_registers_info gdbarch method. This is used by | |
946 | 'info registers' and 'info all-registers'. */ | |
947 | ||
948 | static void | |
949 | riscv_print_registers_info (struct gdbarch *gdbarch, | |
950 | struct ui_file *file, | |
951 | struct frame_info *frame, | |
952 | int regnum, int print_all) | |
953 | { | |
954 | if (regnum != -1) | |
955 | { | |
956 | /* Print one specified register. */ | |
957 | gdb_assert (regnum <= RISCV_LAST_REGNUM); | |
958 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
959 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
960 | error (_("Not a valid register for the current processor type")); | |
961 | riscv_print_one_register_info (gdbarch, file, frame, regnum); | |
962 | } | |
963 | else | |
964 | { | |
965 | struct reggroup *reggroup; | |
966 | ||
967 | if (print_all) | |
968 | reggroup = all_reggroup; | |
969 | else | |
970 | reggroup = general_reggroup; | |
971 | ||
972 | for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum) | |
973 | { | |
974 | /* Zero never changes, so might as well hide by default. */ | |
975 | if (regnum == RISCV_ZERO_REGNUM && !print_all) | |
976 | continue; | |
977 | ||
978 | /* Registers with no name are not valid on this ISA. */ | |
979 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
980 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
981 | continue; | |
982 | ||
983 | /* Is the register in the group we're interested in? */ | |
984 | if (!riscv_register_reggroup_p (gdbarch, regnum, reggroup)) | |
985 | continue; | |
986 | ||
987 | riscv_print_one_register_info (gdbarch, file, frame, regnum); | |
988 | } | |
989 | } | |
990 | } | |
991 | ||
992 | /* Class that handles one decoded RiscV instruction. */ | |
993 | ||
994 | class riscv_insn | |
995 | { | |
996 | public: | |
997 | ||
998 | /* Enum of all the opcodes that GDB cares about during the prologue scan. */ | |
999 | enum opcode | |
1000 | { | |
1001 | /* Unknown value is used at initialisation time. */ | |
1002 | UNKNOWN = 0, | |
1003 | ||
1004 | /* These instructions are all the ones we are interested in during the | |
1005 | prologue scan. */ | |
1006 | ADD, | |
1007 | ADDI, | |
1008 | ADDIW, | |
1009 | ADDW, | |
1010 | AUIPC, | |
1011 | LUI, | |
1012 | SD, | |
1013 | SW, | |
5c720ed8 JW |
1014 | /* These are needed for software breakopint support. */ |
1015 | JAL, | |
1016 | JALR, | |
1017 | BEQ, | |
1018 | BNE, | |
1019 | BLT, | |
1020 | BGE, | |
1021 | BLTU, | |
1022 | BGEU, | |
1023 | /* These are needed for stepping over atomic sequences. */ | |
1024 | LR, | |
1025 | SC, | |
dbbb1059 AB |
1026 | |
1027 | /* Other instructions are not interesting during the prologue scan, and | |
1028 | are ignored. */ | |
1029 | OTHER | |
1030 | }; | |
1031 | ||
1032 | riscv_insn () | |
1033 | : m_length (0), | |
1034 | m_opcode (OTHER), | |
1035 | m_rd (0), | |
1036 | m_rs1 (0), | |
1037 | m_rs2 (0) | |
1038 | { | |
1039 | /* Nothing. */ | |
1040 | } | |
1041 | ||
1042 | void decode (struct gdbarch *gdbarch, CORE_ADDR pc); | |
1043 | ||
1044 | /* Get the length of the instruction in bytes. */ | |
1045 | int length () const | |
1046 | { return m_length; } | |
1047 | ||
1048 | /* Get the opcode for this instruction. */ | |
1049 | enum opcode opcode () const | |
1050 | { return m_opcode; } | |
1051 | ||
1052 | /* Get destination register field for this instruction. This is only | |
1053 | valid if the OPCODE implies there is such a field for this | |
1054 | instruction. */ | |
1055 | int rd () const | |
1056 | { return m_rd; } | |
1057 | ||
1058 | /* Get the RS1 register field for this instruction. This is only valid | |
1059 | if the OPCODE implies there is such a field for this instruction. */ | |
1060 | int rs1 () const | |
1061 | { return m_rs1; } | |
1062 | ||
1063 | /* Get the RS2 register field for this instruction. This is only valid | |
1064 | if the OPCODE implies there is such a field for this instruction. */ | |
1065 | int rs2 () const | |
1066 | { return m_rs2; } | |
1067 | ||
1068 | /* Get the immediate for this instruction in signed form. This is only | |
1069 | valid if the OPCODE implies there is such a field for this | |
1070 | instruction. */ | |
1071 | int imm_signed () const | |
1072 | { return m_imm.s; } | |
1073 | ||
1074 | private: | |
1075 | ||
1076 | /* Extract 5 bit register field at OFFSET from instruction OPCODE. */ | |
1077 | int decode_register_index (unsigned long opcode, int offset) | |
1078 | { | |
1079 | return (opcode >> offset) & 0x1F; | |
1080 | } | |
1081 | ||
5c720ed8 JW |
1082 | /* Extract 5 bit register field at OFFSET from instruction OPCODE. */ |
1083 | int decode_register_index_short (unsigned long opcode, int offset) | |
1084 | { | |
1085 | return ((opcode >> offset) & 0x7) + 8; | |
1086 | } | |
1087 | ||
dbbb1059 AB |
1088 | /* Helper for DECODE, decode 32-bit R-type instruction. */ |
1089 | void decode_r_type_insn (enum opcode opcode, ULONGEST ival) | |
1090 | { | |
1091 | m_opcode = opcode; | |
1092 | m_rd = decode_register_index (ival, OP_SH_RD); | |
1093 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
1094 | m_rs2 = decode_register_index (ival, OP_SH_RS2); | |
1095 | } | |
1096 | ||
1097 | /* Helper for DECODE, decode 16-bit compressed R-type instruction. */ | |
1098 | void decode_cr_type_insn (enum opcode opcode, ULONGEST ival) | |
1099 | { | |
1100 | m_opcode = opcode; | |
1101 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S); | |
1102 | m_rs2 = decode_register_index (ival, OP_SH_CRS2); | |
1103 | } | |
1104 | ||
1105 | /* Helper for DECODE, decode 32-bit I-type instruction. */ | |
1106 | void decode_i_type_insn (enum opcode opcode, ULONGEST ival) | |
1107 | { | |
1108 | m_opcode = opcode; | |
1109 | m_rd = decode_register_index (ival, OP_SH_RD); | |
1110 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
1111 | m_imm.s = EXTRACT_ITYPE_IMM (ival); | |
1112 | } | |
1113 | ||
1114 | /* Helper for DECODE, decode 16-bit compressed I-type instruction. */ | |
1115 | void decode_ci_type_insn (enum opcode opcode, ULONGEST ival) | |
1116 | { | |
1117 | m_opcode = opcode; | |
1118 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S); | |
1119 | m_imm.s = EXTRACT_RVC_IMM (ival); | |
1120 | } | |
1121 | ||
1122 | /* Helper for DECODE, decode 32-bit S-type instruction. */ | |
1123 | void decode_s_type_insn (enum opcode opcode, ULONGEST ival) | |
1124 | { | |
1125 | m_opcode = opcode; | |
1126 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
1127 | m_rs2 = decode_register_index (ival, OP_SH_RS2); | |
1128 | m_imm.s = EXTRACT_STYPE_IMM (ival); | |
1129 | } | |
1130 | ||
ff3a05b3 AB |
1131 | /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate |
1132 | encoding is different for each CS format instruction, so extracting | |
1133 | the immediate is left up to the caller, who should pass the extracted | |
1134 | immediate value through in IMM. */ | |
1135 | void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm) | |
1136 | { | |
1137 | m_opcode = opcode; | |
1138 | m_imm.s = imm; | |
1139 | m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S); | |
1140 | m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S); | |
1141 | } | |
1142 | ||
1143 | /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate | |
1144 | encoding is different for each CSS format instruction, so extracting | |
1145 | the immediate is left up to the caller, who should pass the extracted | |
1146 | immediate value through in IMM. */ | |
1147 | void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm) | |
1148 | { | |
1149 | m_opcode = opcode; | |
1150 | m_imm.s = imm; | |
1151 | m_rs1 = RISCV_SP_REGNUM; | |
1152 | /* Not a compressed register number in this case. */ | |
1153 | m_rs2 = decode_register_index (ival, OP_SH_CRS2); | |
1154 | } | |
1155 | ||
dbbb1059 AB |
1156 | /* Helper for DECODE, decode 32-bit U-type instruction. */ |
1157 | void decode_u_type_insn (enum opcode opcode, ULONGEST ival) | |
1158 | { | |
1159 | m_opcode = opcode; | |
1160 | m_rd = decode_register_index (ival, OP_SH_RD); | |
1161 | m_imm.s = EXTRACT_UTYPE_IMM (ival); | |
1162 | } | |
1163 | ||
5c720ed8 JW |
1164 | /* Helper for DECODE, decode 32-bit J-type instruction. */ |
1165 | void decode_j_type_insn (enum opcode opcode, ULONGEST ival) | |
1166 | { | |
1167 | m_opcode = opcode; | |
1168 | m_rd = decode_register_index (ival, OP_SH_RD); | |
1169 | m_imm.s = EXTRACT_UJTYPE_IMM (ival); | |
1170 | } | |
1171 | ||
1172 | /* Helper for DECODE, decode 32-bit J-type instruction. */ | |
1173 | void decode_cj_type_insn (enum opcode opcode, ULONGEST ival) | |
1174 | { | |
1175 | m_opcode = opcode; | |
1176 | m_imm.s = EXTRACT_RVC_J_IMM (ival); | |
1177 | } | |
1178 | ||
1179 | void decode_b_type_insn (enum opcode opcode, ULONGEST ival) | |
1180 | { | |
1181 | m_opcode = opcode; | |
1182 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
1183 | m_rs2 = decode_register_index (ival, OP_SH_RS2); | |
1184 | m_imm.s = EXTRACT_SBTYPE_IMM (ival); | |
1185 | } | |
1186 | ||
1187 | void decode_cb_type_insn (enum opcode opcode, ULONGEST ival) | |
1188 | { | |
1189 | m_opcode = opcode; | |
1190 | m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S); | |
1191 | m_imm.s = EXTRACT_RVC_B_IMM (ival); | |
1192 | } | |
1193 | ||
dbbb1059 AB |
1194 | /* Fetch instruction from target memory at ADDR, return the content of |
1195 | the instruction, and update LEN with the instruction length. */ | |
1196 | static ULONGEST fetch_instruction (struct gdbarch *gdbarch, | |
1197 | CORE_ADDR addr, int *len); | |
1198 | ||
1199 | /* The length of the instruction in bytes. Should be 2 or 4. */ | |
1200 | int m_length; | |
1201 | ||
1202 | /* The instruction opcode. */ | |
1203 | enum opcode m_opcode; | |
1204 | ||
1205 | /* The three possible registers an instruction might reference. Not | |
1206 | every instruction fills in all of these registers. Which fields are | |
1207 | valid depends on the opcode. The naming of these fields matches the | |
1208 | naming in the riscv isa manual. */ | |
1209 | int m_rd; | |
1210 | int m_rs1; | |
1211 | int m_rs2; | |
1212 | ||
1213 | /* Possible instruction immediate. This is only valid if the instruction | |
1214 | format contains an immediate, not all instruction, whether this is | |
1215 | valid depends on the opcode. Despite only having one format for now | |
1216 | the immediate is packed into a union, later instructions might require | |
1217 | an unsigned formatted immediate, having the union in place now will | |
1218 | reduce the need for code churn later. */ | |
1219 | union riscv_insn_immediate | |
1220 | { | |
1221 | riscv_insn_immediate () | |
1222 | : s (0) | |
1223 | { | |
1224 | /* Nothing. */ | |
1225 | } | |
1226 | ||
1227 | int s; | |
1228 | } m_imm; | |
1229 | }; | |
1230 | ||
1231 | /* Fetch instruction from target memory at ADDR, return the content of the | |
1232 | instruction, and update LEN with the instruction length. */ | |
1233 | ||
1234 | ULONGEST | |
1235 | riscv_insn::fetch_instruction (struct gdbarch *gdbarch, | |
1236 | CORE_ADDR addr, int *len) | |
1237 | { | |
1238 | enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch); | |
1239 | gdb_byte buf[8]; | |
1240 | int instlen, status; | |
1241 | ||
1242 | /* All insns are at least 16 bits. */ | |
1243 | status = target_read_memory (addr, buf, 2); | |
1244 | if (status) | |
1245 | memory_error (TARGET_XFER_E_IO, addr); | |
1246 | ||
1247 | /* If we need more, grab it now. */ | |
1248 | instlen = riscv_insn_length (buf[0]); | |
89a3b63e | 1249 | gdb_assert (instlen <= sizeof (buf)); |
dbbb1059 | 1250 | *len = instlen; |
89a3b63e AB |
1251 | |
1252 | if (instlen > 2) | |
dbbb1059 AB |
1253 | { |
1254 | status = target_read_memory (addr + 2, buf + 2, instlen - 2); | |
1255 | if (status) | |
1256 | memory_error (TARGET_XFER_E_IO, addr + 2); | |
1257 | } | |
1258 | ||
1259 | return extract_unsigned_integer (buf, instlen, byte_order); | |
1260 | } | |
1261 | ||
17cf2897 AB |
1262 | /* Fetch from target memory an instruction at PC and decode it. This can |
1263 | throw an error if the memory access fails, callers are responsible for | |
1264 | handling this error if that is appropriate. */ | |
dbbb1059 AB |
1265 | |
1266 | void | |
1267 | riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1268 | { | |
1269 | ULONGEST ival; | |
1270 | ||
1271 | /* Fetch the instruction, and the instructions length. */ | |
1272 | ival = fetch_instruction (gdbarch, pc, &m_length); | |
1273 | ||
1274 | if (m_length == 4) | |
1275 | { | |
1276 | if (is_add_insn (ival)) | |
1277 | decode_r_type_insn (ADD, ival); | |
1278 | else if (is_addw_insn (ival)) | |
1279 | decode_r_type_insn (ADDW, ival); | |
1280 | else if (is_addi_insn (ival)) | |
1281 | decode_i_type_insn (ADDI, ival); | |
1282 | else if (is_addiw_insn (ival)) | |
1283 | decode_i_type_insn (ADDIW, ival); | |
1284 | else if (is_auipc_insn (ival)) | |
1285 | decode_u_type_insn (AUIPC, ival); | |
1286 | else if (is_lui_insn (ival)) | |
1287 | decode_u_type_insn (LUI, ival); | |
1288 | else if (is_sd_insn (ival)) | |
1289 | decode_s_type_insn (SD, ival); | |
1290 | else if (is_sw_insn (ival)) | |
1291 | decode_s_type_insn (SW, ival); | |
5c720ed8 JW |
1292 | else if (is_jal_insn (ival)) |
1293 | decode_j_type_insn (JAL, ival); | |
1294 | else if (is_jalr_insn (ival)) | |
1295 | decode_i_type_insn (JALR, ival); | |
1296 | else if (is_beq_insn (ival)) | |
1297 | decode_b_type_insn (BEQ, ival); | |
1298 | else if (is_bne_insn (ival)) | |
1299 | decode_b_type_insn (BNE, ival); | |
1300 | else if (is_blt_insn (ival)) | |
1301 | decode_b_type_insn (BLT, ival); | |
1302 | else if (is_bge_insn (ival)) | |
1303 | decode_b_type_insn (BGE, ival); | |
1304 | else if (is_bltu_insn (ival)) | |
1305 | decode_b_type_insn (BLTU, ival); | |
1306 | else if (is_bgeu_insn (ival)) | |
1307 | decode_b_type_insn (BGEU, ival); | |
1308 | else if (is_lr_w_insn (ival)) | |
1309 | decode_r_type_insn (LR, ival); | |
1310 | else if (is_lr_d_insn (ival)) | |
1311 | decode_r_type_insn (LR, ival); | |
1312 | else if (is_sc_w_insn (ival)) | |
1313 | decode_r_type_insn (SC, ival); | |
1314 | else if (is_sc_d_insn (ival)) | |
1315 | decode_r_type_insn (SC, ival); | |
dbbb1059 AB |
1316 | else |
1317 | /* None of the other fields are valid in this case. */ | |
1318 | m_opcode = OTHER; | |
1319 | } | |
1320 | else if (m_length == 2) | |
1321 | { | |
5c720ed8 JW |
1322 | int xlen = riscv_isa_xlen (gdbarch); |
1323 | ||
1324 | /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a | |
1325 | C_JALR. So must try to match C_JALR first as it has more bits in | |
1326 | mask. */ | |
1327 | if (is_c_jalr_insn (ival)) | |
1328 | decode_cr_type_insn (JALR, ival); | |
1329 | else if (is_c_add_insn (ival)) | |
dbbb1059 | 1330 | decode_cr_type_insn (ADD, ival); |
5c720ed8 JW |
1331 | /* C_ADDW is RV64 and RV128 only. */ |
1332 | else if (xlen != 4 && is_c_addw_insn (ival)) | |
dbbb1059 AB |
1333 | decode_cr_type_insn (ADDW, ival); |
1334 | else if (is_c_addi_insn (ival)) | |
1335 | decode_ci_type_insn (ADDI, ival); | |
5c720ed8 JW |
1336 | /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128 |
1337 | only and C_JAL is RV32 only. */ | |
1338 | else if (xlen != 4 && is_c_addiw_insn (ival)) | |
dbbb1059 | 1339 | decode_ci_type_insn (ADDIW, ival); |
5c720ed8 JW |
1340 | else if (xlen == 4 && is_c_jal_insn (ival)) |
1341 | decode_cj_type_insn (JAL, ival); | |
1342 | /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a | |
1343 | C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits | |
1344 | in mask. */ | |
dbbb1059 AB |
1345 | else if (is_c_addi16sp_insn (ival)) |
1346 | { | |
1347 | m_opcode = ADDI; | |
1348 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD); | |
1349 | m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival); | |
1350 | } | |
ff3a05b3 AB |
1351 | else if (is_c_addi4spn_insn (ival)) |
1352 | { | |
1353 | m_opcode = ADDI; | |
1354 | m_rd = decode_register_index_short (ival, OP_SH_CRS2S); | |
1355 | m_rs1 = RISCV_SP_REGNUM; | |
1356 | m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival); | |
1357 | } | |
5c720ed8 | 1358 | else if (is_c_lui_insn (ival)) |
d354055e AB |
1359 | { |
1360 | m_opcode = LUI; | |
1361 | m_rd = decode_register_index (ival, OP_SH_CRS1S); | |
1362 | m_imm.s = EXTRACT_RVC_LUI_IMM (ival); | |
1363 | } | |
5c720ed8 JW |
1364 | /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only, |
1365 | and C_FSW is RV32 only. */ | |
1366 | else if (xlen != 4 && is_c_sd_insn (ival)) | |
ff3a05b3 | 1367 | decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival)); |
5c720ed8 | 1368 | else if (is_c_sw_insn (ival)) |
ff3a05b3 AB |
1369 | decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival)); |
1370 | else if (is_c_swsp_insn (ival)) | |
1371 | decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival)); | |
1372 | else if (xlen != 4 && is_c_sdsp_insn (ival)) | |
1373 | decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival)); | |
5c720ed8 JW |
1374 | /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR. |
1375 | So must try to match C_JR first as it ahs more bits in mask. */ | |
1376 | else if (is_c_jr_insn (ival)) | |
1377 | decode_cr_type_insn (JALR, ival); | |
1378 | else if (is_c_j_insn (ival)) | |
1379 | decode_cj_type_insn (JAL, ival); | |
1380 | else if (is_c_beqz_insn (ival)) | |
1381 | decode_cb_type_insn (BEQ, ival); | |
1382 | else if (is_c_bnez_insn (ival)) | |
1383 | decode_cb_type_insn (BNE, ival); | |
dbbb1059 AB |
1384 | else |
1385 | /* None of the other fields of INSN are valid in this case. */ | |
1386 | m_opcode = OTHER; | |
1387 | } | |
1388 | else | |
1389 | internal_error (__FILE__, __LINE__, | |
1390 | _("unable to decode %d byte instructions in " | |
1391 | "prologue at %s"), m_length, | |
1392 | core_addr_to_string (pc)); | |
1393 | } | |
1394 | ||
1395 | /* The prologue scanner. This is currently only used for skipping the | |
1396 | prologue of a function when the DWARF information is not sufficient. | |
1397 | However, it is written with filling of the frame cache in mind, which | |
1398 | is why different groups of stack setup instructions are split apart | |
1399 | during the core of the inner loop. In the future, the intention is to | |
1400 | extend this function to fully support building up a frame cache that | |
1401 | can unwind register values when there is no DWARF information. */ | |
1402 | ||
1403 | static CORE_ADDR | |
1404 | riscv_scan_prologue (struct gdbarch *gdbarch, | |
78a3b0fa AB |
1405 | CORE_ADDR start_pc, CORE_ADDR end_pc, |
1406 | struct riscv_unwind_cache *cache) | |
dbbb1059 | 1407 | { |
78a3b0fa | 1408 | CORE_ADDR cur_pc, next_pc, after_prologue_pc; |
dbbb1059 AB |
1409 | CORE_ADDR end_prologue_addr = 0; |
1410 | ||
78a3b0fa AB |
1411 | /* Find an upper limit on the function prologue using the debug |
1412 | information. If the debug information could not be used to provide | |
1413 | that bound, then use an arbitrary large number as the upper bound. */ | |
1414 | after_prologue_pc = skip_prologue_using_sal (gdbarch, start_pc); | |
1415 | if (after_prologue_pc == 0) | |
1416 | after_prologue_pc = start_pc + 100; /* Arbitrary large number. */ | |
1417 | if (after_prologue_pc < end_pc) | |
1418 | end_pc = after_prologue_pc; | |
1419 | ||
1420 | pv_t regs[RISCV_NUM_INTEGER_REGS]; /* Number of GPR. */ | |
1421 | for (int regno = 0; regno < RISCV_NUM_INTEGER_REGS; regno++) | |
1422 | regs[regno] = pv_register (regno, 0); | |
1423 | pv_area stack (RISCV_SP_REGNUM, gdbarch_addr_bit (gdbarch)); | |
1424 | ||
1425 | if (riscv_debug_unwinder) | |
1426 | fprintf_unfiltered | |
1427 | (gdb_stdlog, | |
1428 | "Prologue scan for function starting at %s (limit %s)\n", | |
1429 | core_addr_to_string (start_pc), | |
1430 | core_addr_to_string (end_pc)); | |
1431 | ||
1432 | for (next_pc = cur_pc = start_pc; cur_pc < end_pc; cur_pc = next_pc) | |
dbbb1059 AB |
1433 | { |
1434 | struct riscv_insn insn; | |
1435 | ||
1436 | /* Decode the current instruction, and decide where the next | |
1437 | instruction lives based on the size of this instruction. */ | |
1438 | insn.decode (gdbarch, cur_pc); | |
1439 | gdb_assert (insn.length () > 0); | |
1440 | next_pc = cur_pc + insn.length (); | |
1441 | ||
1442 | /* Look for common stack adjustment insns. */ | |
1443 | if ((insn.opcode () == riscv_insn::ADDI | |
1444 | || insn.opcode () == riscv_insn::ADDIW) | |
1445 | && insn.rd () == RISCV_SP_REGNUM | |
1446 | && insn.rs1 () == RISCV_SP_REGNUM) | |
1447 | { | |
1448 | /* Handle: addi sp, sp, -i | |
1449 | or: addiw sp, sp, -i */ | |
78a3b0fa AB |
1450 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
1451 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1452 | regs[insn.rd ()] | |
1453 | = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()); | |
dbbb1059 AB |
1454 | } |
1455 | else if ((insn.opcode () == riscv_insn::SW | |
1456 | || insn.opcode () == riscv_insn::SD) | |
1457 | && (insn.rs1 () == RISCV_SP_REGNUM | |
1458 | || insn.rs1 () == RISCV_FP_REGNUM)) | |
1459 | { | |
1460 | /* Handle: sw reg, offset(sp) | |
1461 | or: sd reg, offset(sp) | |
1462 | or: sw reg, offset(s0) | |
1463 | or: sd reg, offset(s0) */ | |
1464 | /* Instruction storing a register onto the stack. */ | |
78a3b0fa AB |
1465 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); |
1466 | gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS); | |
1467 | stack.store (pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()), | |
1468 | (insn.opcode () == riscv_insn::SW ? 4 : 8), | |
1469 | regs[insn.rs2 ()]); | |
dbbb1059 AB |
1470 | } |
1471 | else if (insn.opcode () == riscv_insn::ADDI | |
1472 | && insn.rd () == RISCV_FP_REGNUM | |
1473 | && insn.rs1 () == RISCV_SP_REGNUM) | |
1474 | { | |
1475 | /* Handle: addi s0, sp, size */ | |
1476 | /* Instructions setting up the frame pointer. */ | |
78a3b0fa AB |
1477 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
1478 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1479 | regs[insn.rd ()] | |
1480 | = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()); | |
dbbb1059 AB |
1481 | } |
1482 | else if ((insn.opcode () == riscv_insn::ADD | |
1483 | || insn.opcode () == riscv_insn::ADDW) | |
1484 | && insn.rd () == RISCV_FP_REGNUM | |
1485 | && insn.rs1 () == RISCV_SP_REGNUM | |
1486 | && insn.rs2 () == RISCV_ZERO_REGNUM) | |
1487 | { | |
1488 | /* Handle: add s0, sp, 0 | |
1489 | or: addw s0, sp, 0 */ | |
1490 | /* Instructions setting up the frame pointer. */ | |
78a3b0fa AB |
1491 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
1492 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1493 | regs[insn.rd ()] = pv_add_constant (regs[insn.rs1 ()], 0); | |
dbbb1059 | 1494 | } |
d354055e AB |
1495 | else if ((insn.opcode () == riscv_insn::ADDI |
1496 | && insn.rd () == RISCV_ZERO_REGNUM | |
1497 | && insn.rs1 () == RISCV_ZERO_REGNUM | |
1498 | && insn.imm_signed () == 0)) | |
dbbb1059 | 1499 | { |
d354055e | 1500 | /* Handle: add x0, x0, 0 (NOP) */ |
dbbb1059 | 1501 | } |
d354055e AB |
1502 | else if (insn.opcode () == riscv_insn::AUIPC) |
1503 | { | |
1504 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); | |
1505 | regs[insn.rd ()] = pv_constant (cur_pc + insn.imm_signed ()); | |
1506 | } | |
1507 | else if (insn.opcode () == riscv_insn::LUI) | |
1508 | { | |
1509 | /* Handle: lui REG, n | |
1510 | Where REG is not gp register. */ | |
1511 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); | |
1512 | regs[insn.rd ()] = pv_constant (insn.imm_signed ()); | |
1513 | } | |
1514 | else if (insn.opcode () == riscv_insn::ADDI) | |
1515 | { | |
1516 | /* Handle: addi REG1, REG2, IMM */ | |
1517 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); | |
1518 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1519 | regs[insn.rd ()] | |
1520 | = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()); | |
1521 | } | |
1522 | else if (insn.opcode () == riscv_insn::ADD) | |
1523 | { | |
1524 | /* Handle: addi REG1, REG2, IMM */ | |
1525 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); | |
1526 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1527 | gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS); | |
1528 | regs[insn.rd ()] = pv_add (regs[insn.rs1 ()], regs[insn.rs2 ()]); | |
1529 | } | |
dbbb1059 AB |
1530 | else |
1531 | { | |
78a3b0fa AB |
1532 | end_prologue_addr = cur_pc; |
1533 | break; | |
dbbb1059 AB |
1534 | } |
1535 | } | |
1536 | ||
1537 | if (end_prologue_addr == 0) | |
1538 | end_prologue_addr = cur_pc; | |
1539 | ||
78a3b0fa AB |
1540 | if (riscv_debug_unwinder) |
1541 | fprintf_unfiltered (gdb_stdlog, "End of prologue at %s\n", | |
1542 | core_addr_to_string (end_prologue_addr)); | |
1543 | ||
1544 | if (cache != NULL) | |
1545 | { | |
1546 | /* Figure out if it is a frame pointer or just a stack pointer. Also | |
1547 | the offset held in the pv_t is from the original register value to | |
1548 | the current value, which for a grows down stack means a negative | |
1549 | value. The FRAME_BASE_OFFSET is the negation of this, how to get | |
1550 | from the current value to the original value. */ | |
1551 | if (pv_is_register (regs[RISCV_FP_REGNUM], RISCV_SP_REGNUM)) | |
1552 | { | |
1553 | cache->frame_base_reg = RISCV_FP_REGNUM; | |
1554 | cache->frame_base_offset = -regs[RISCV_FP_REGNUM].k; | |
1555 | } | |
1556 | else | |
1557 | { | |
1558 | cache->frame_base_reg = RISCV_SP_REGNUM; | |
1559 | cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k; | |
1560 | } | |
1561 | ||
1562 | /* Assign offset from old SP to all saved registers. As we don't | |
1563 | have the previous value for the frame base register at this | |
1564 | point, we store the offset as the address in the trad_frame, and | |
1565 | then convert this to an actual address later. */ | |
1566 | for (int i = 0; i <= RISCV_NUM_INTEGER_REGS; i++) | |
1567 | { | |
1568 | CORE_ADDR offset; | |
1569 | if (stack.find_reg (gdbarch, i, &offset)) | |
1570 | { | |
1571 | if (riscv_debug_unwinder) | |
1572 | fprintf_unfiltered (gdb_stdlog, | |
1573 | "Register $%s at stack offset %ld\n", | |
1574 | gdbarch_register_name (gdbarch, i), | |
1575 | offset); | |
1576 | trad_frame_set_addr (cache->regs, i, offset); | |
1577 | } | |
1578 | } | |
1579 | } | |
1580 | ||
dbbb1059 AB |
1581 | return end_prologue_addr; |
1582 | } | |
1583 | ||
1584 | /* Implement the riscv_skip_prologue gdbarch method. */ | |
1585 | ||
1586 | static CORE_ADDR | |
78a3b0fa | 1587 | riscv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
dbbb1059 | 1588 | { |
dbbb1059 AB |
1589 | CORE_ADDR func_addr; |
1590 | ||
1591 | /* See if we can determine the end of the prologue via the symbol | |
1592 | table. If so, then return either PC, or the PC after the | |
1593 | prologue, whichever is greater. */ | |
1594 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
1595 | { | |
1596 | CORE_ADDR post_prologue_pc | |
1597 | = skip_prologue_using_sal (gdbarch, func_addr); | |
1598 | ||
1599 | if (post_prologue_pc != 0) | |
1600 | return std::max (pc, post_prologue_pc); | |
1601 | } | |
1602 | ||
1603 | /* Can't determine prologue from the symbol table, need to examine | |
78a3b0fa AB |
1604 | instructions. Pass -1 for the end address to indicate the prologue |
1605 | scanner can scan as far as it needs to find the end of the prologue. */ | |
1606 | return riscv_scan_prologue (gdbarch, pc, ((CORE_ADDR) -1), NULL); | |
dbbb1059 AB |
1607 | } |
1608 | ||
1609 | /* Implement the gdbarch push dummy code callback. */ | |
1610 | ||
1611 | static CORE_ADDR | |
1612 | riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
1613 | CORE_ADDR funaddr, struct value **args, int nargs, | |
1614 | struct type *value_type, CORE_ADDR *real_pc, | |
1615 | CORE_ADDR *bp_addr, struct regcache *regcache) | |
1616 | { | |
1617 | /* Allocate space for a breakpoint, and keep the stack correctly | |
1618 | aligned. */ | |
1619 | sp -= 16; | |
1620 | *bp_addr = sp; | |
1621 | *real_pc = funaddr; | |
1622 | return sp; | |
1623 | } | |
1624 | ||
1625 | /* Compute the alignment of the type T. Used while setting up the | |
1626 | arguments for a dummy call. */ | |
1627 | ||
1628 | static int | |
1629 | riscv_type_alignment (struct type *t) | |
1630 | { | |
1631 | t = check_typedef (t); | |
1632 | switch (TYPE_CODE (t)) | |
1633 | { | |
1634 | default: | |
1635 | error (_("Could not compute alignment of type")); | |
1636 | ||
1637 | case TYPE_CODE_RVALUE_REF: | |
1638 | case TYPE_CODE_PTR: | |
1639 | case TYPE_CODE_ENUM: | |
1640 | case TYPE_CODE_INT: | |
1641 | case TYPE_CODE_FLT: | |
1642 | case TYPE_CODE_REF: | |
1643 | case TYPE_CODE_CHAR: | |
1644 | case TYPE_CODE_BOOL: | |
1645 | return TYPE_LENGTH (t); | |
1646 | ||
1647 | case TYPE_CODE_ARRAY: | |
ef2de9e7 JW |
1648 | if (TYPE_VECTOR (t)) |
1649 | return std::min (TYPE_LENGTH (t), (unsigned) BIGGEST_ALIGNMENT); | |
1650 | /* FALLTHROUGH */ | |
1651 | ||
dbbb1059 AB |
1652 | case TYPE_CODE_COMPLEX: |
1653 | return riscv_type_alignment (TYPE_TARGET_TYPE (t)); | |
1654 | ||
1655 | case TYPE_CODE_STRUCT: | |
1656 | case TYPE_CODE_UNION: | |
1657 | { | |
1658 | int i; | |
1659 | int align = 1; | |
1660 | ||
1661 | for (i = 0; i < TYPE_NFIELDS (t); ++i) | |
1662 | { | |
1663 | if (TYPE_FIELD_LOC_KIND (t, i) == FIELD_LOC_KIND_BITPOS) | |
1664 | { | |
1665 | int a = riscv_type_alignment (TYPE_FIELD_TYPE (t, i)); | |
1666 | if (a > align) | |
1667 | align = a; | |
1668 | } | |
1669 | } | |
1670 | return align; | |
1671 | } | |
1672 | } | |
1673 | } | |
1674 | ||
1675 | /* Holds information about a single argument either being passed to an | |
1676 | inferior function, or returned from an inferior function. This includes | |
1677 | information about the size, type, etc of the argument, and also | |
1678 | information about how the argument will be passed (or returned). */ | |
1679 | ||
1680 | struct riscv_arg_info | |
1681 | { | |
1682 | /* Contents of the argument. */ | |
1683 | const gdb_byte *contents; | |
1684 | ||
1685 | /* Length of argument. */ | |
1686 | int length; | |
1687 | ||
1688 | /* Alignment required for an argument of this type. */ | |
1689 | int align; | |
1690 | ||
1691 | /* The type for this argument. */ | |
1692 | struct type *type; | |
1693 | ||
1694 | /* Each argument can have either 1 or 2 locations assigned to it. Each | |
1695 | location describes where part of the argument will be placed. The | |
1696 | second location is valid based on the LOC_TYPE and C_LENGTH fields | |
1697 | of the first location (which is always valid). */ | |
1698 | struct location | |
1699 | { | |
1700 | /* What type of location this is. */ | |
1701 | enum location_type | |
1702 | { | |
1703 | /* Argument passed in a register. */ | |
1704 | in_reg, | |
1705 | ||
1706 | /* Argument passed as an on stack argument. */ | |
1707 | on_stack, | |
1708 | ||
1709 | /* Argument passed by reference. The second location is always | |
1710 | valid for a BY_REF argument, and describes where the address | |
1711 | of the BY_REF argument should be placed. */ | |
1712 | by_ref | |
1713 | } loc_type; | |
1714 | ||
1715 | /* Information that depends on the location type. */ | |
1716 | union | |
1717 | { | |
1718 | /* Which register number to use. */ | |
1719 | int regno; | |
1720 | ||
1721 | /* The offset into the stack region. */ | |
1722 | int offset; | |
1723 | } loc_data; | |
1724 | ||
1725 | /* The length of contents covered by this location. If this is less | |
1726 | than the total length of the argument, then the second location | |
1727 | will be valid, and will describe where the rest of the argument | |
1728 | will go. */ | |
1729 | int c_length; | |
1730 | ||
1731 | /* The offset within CONTENTS for this part of the argument. Will | |
1732 | always be 0 for the first part. For the second part of the | |
1733 | argument, this might be the C_LENGTH value of the first part, | |
1734 | however, if we are passing a structure in two registers, and there's | |
1735 | is padding between the first and second field, then this offset | |
1736 | might be greater than the length of the first argument part. When | |
1737 | the second argument location is not holding part of the argument | |
1738 | value, but is instead holding the address of a reference argument, | |
1739 | then this offset will be set to 0. */ | |
1740 | int c_offset; | |
1741 | } argloc[2]; | |
8b2d40cb JW |
1742 | |
1743 | /* TRUE if this is an unnamed argument. */ | |
1744 | bool is_unnamed; | |
dbbb1059 AB |
1745 | }; |
1746 | ||
1747 | /* Information about a set of registers being used for passing arguments as | |
1748 | part of a function call. The register set must be numerically | |
1749 | sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be | |
1750 | disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */ | |
1751 | ||
1752 | struct riscv_arg_reg | |
1753 | { | |
1754 | riscv_arg_reg (int first, int last) | |
1755 | : next_regnum (first), | |
1756 | last_regnum (last) | |
1757 | { | |
1758 | /* Nothing. */ | |
1759 | } | |
1760 | ||
1761 | /* The GDB register number to use in this set. */ | |
1762 | int next_regnum; | |
1763 | ||
1764 | /* The last GDB register number to use in this set. */ | |
1765 | int last_regnum; | |
1766 | }; | |
1767 | ||
1768 | /* Arguments can be passed as on stack arguments, or by reference. The | |
1769 | on stack arguments must be in a continuous region starting from $sp, | |
1770 | while the by reference arguments can be anywhere, but we'll put them | |
1771 | on the stack after (at higher address) the on stack arguments. | |
1772 | ||
1773 | This might not be the right approach to take. The ABI is clear that | |
1774 | an argument passed by reference can be modified by the callee, which | |
1775 | us placing the argument (temporarily) onto the stack will not achieve | |
1776 | (changes will be lost). There's also the possibility that very large | |
1777 | arguments could overflow the stack. | |
1778 | ||
1779 | This struct is used to track offset into these two areas for where | |
1780 | arguments are to be placed. */ | |
1781 | struct riscv_memory_offsets | |
1782 | { | |
1783 | riscv_memory_offsets () | |
1784 | : arg_offset (0), | |
1785 | ref_offset (0) | |
1786 | { | |
1787 | /* Nothing. */ | |
1788 | } | |
1789 | ||
1790 | /* Offset into on stack argument area. */ | |
1791 | int arg_offset; | |
1792 | ||
1793 | /* Offset into the pass by reference area. */ | |
1794 | int ref_offset; | |
1795 | }; | |
1796 | ||
1797 | /* Holds information about where arguments to a call will be placed. This | |
1798 | is updated as arguments are added onto the call, and can be used to | |
1799 | figure out where the next argument should be placed. */ | |
1800 | ||
1801 | struct riscv_call_info | |
1802 | { | |
1803 | riscv_call_info (struct gdbarch *gdbarch) | |
1804 | : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7), | |
1805 | float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7) | |
1806 | { | |
1807 | xlen = riscv_isa_xlen (gdbarch); | |
1808 | flen = riscv_isa_flen (gdbarch); | |
1809 | ||
1810 | /* Disable use of floating point registers if needed. */ | |
1811 | if (!riscv_has_fp_abi (gdbarch)) | |
1812 | float_regs.next_regnum = float_regs.last_regnum + 1; | |
1813 | } | |
1814 | ||
1815 | /* Track the memory areas used for holding in-memory arguments to a | |
1816 | call. */ | |
1817 | struct riscv_memory_offsets memory; | |
1818 | ||
1819 | /* Holds information about the next integer register to use for passing | |
1820 | an argument. */ | |
1821 | struct riscv_arg_reg int_regs; | |
1822 | ||
1823 | /* Holds information about the next floating point register to use for | |
1824 | passing an argument. */ | |
1825 | struct riscv_arg_reg float_regs; | |
1826 | ||
1827 | /* The XLEN and FLEN are copied in to this structure for convenience, and | |
1828 | are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */ | |
1829 | int xlen; | |
1830 | int flen; | |
1831 | }; | |
1832 | ||
1833 | /* Return the number of registers available for use as parameters in the | |
1834 | register set REG. Returned value can be 0 or more. */ | |
1835 | ||
1836 | static int | |
1837 | riscv_arg_regs_available (struct riscv_arg_reg *reg) | |
1838 | { | |
1839 | if (reg->next_regnum > reg->last_regnum) | |
1840 | return 0; | |
1841 | ||
1842 | return (reg->last_regnum - reg->next_regnum + 1); | |
1843 | } | |
1844 | ||
1845 | /* If there is at least one register available in the register set REG then | |
1846 | the next register from REG is assigned to LOC and the length field of | |
1847 | LOC is updated to LENGTH. The register set REG is updated to indicate | |
1848 | that the assigned register is no longer available and the function | |
1849 | returns true. | |
1850 | ||
1851 | If there are no registers available in REG then the function returns | |
1852 | false, and LOC and REG are unchanged. */ | |
1853 | ||
1854 | static bool | |
1855 | riscv_assign_reg_location (struct riscv_arg_info::location *loc, | |
1856 | struct riscv_arg_reg *reg, | |
1857 | int length, int offset) | |
1858 | { | |
1859 | if (reg->next_regnum <= reg->last_regnum) | |
1860 | { | |
1861 | loc->loc_type = riscv_arg_info::location::in_reg; | |
1862 | loc->loc_data.regno = reg->next_regnum; | |
1863 | reg->next_regnum++; | |
1864 | loc->c_length = length; | |
1865 | loc->c_offset = offset; | |
1866 | return true; | |
1867 | } | |
1868 | ||
1869 | return false; | |
1870 | } | |
1871 | ||
1872 | /* Assign LOC a location as the next stack parameter, and update MEMORY to | |
1873 | record that an area of stack has been used to hold the parameter | |
1874 | described by LOC. | |
1875 | ||
1876 | The length field of LOC is updated to LENGTH, the length of the | |
1877 | parameter being stored, and ALIGN is the alignment required by the | |
1878 | parameter, which will affect how memory is allocated out of MEMORY. */ | |
1879 | ||
1880 | static void | |
1881 | riscv_assign_stack_location (struct riscv_arg_info::location *loc, | |
1882 | struct riscv_memory_offsets *memory, | |
1883 | int length, int align) | |
1884 | { | |
1885 | loc->loc_type = riscv_arg_info::location::on_stack; | |
1886 | memory->arg_offset | |
1887 | = align_up (memory->arg_offset, align); | |
1888 | loc->loc_data.offset = memory->arg_offset; | |
1889 | memory->arg_offset += length; | |
1890 | loc->c_length = length; | |
1891 | ||
1892 | /* Offset is always 0, either we're the first location part, in which | |
1893 | case we're reading content from the start of the argument, or we're | |
1894 | passing the address of a reference argument, so 0. */ | |
1895 | loc->c_offset = 0; | |
1896 | } | |
1897 | ||
1898 | /* Update AINFO, which describes an argument that should be passed or | |
1899 | returned using the integer ABI. The argloc fields within AINFO are | |
1900 | updated to describe the location in which the argument will be passed to | |
1901 | a function, or returned from a function. | |
1902 | ||
1903 | The CINFO structure contains the ongoing call information, the holds | |
1904 | information such as which argument registers are remaining to be | |
1905 | assigned to parameter, and how much memory has been used by parameters | |
1906 | so far. | |
1907 | ||
1908 | By examining the state of CINFO a suitable location can be selected, | |
1909 | and assigned to AINFO. */ | |
1910 | ||
1911 | static void | |
1912 | riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo, | |
1913 | struct riscv_call_info *cinfo) | |
1914 | { | |
1915 | if (ainfo->length > (2 * cinfo->xlen)) | |
1916 | { | |
1917 | /* Argument is going to be passed by reference. */ | |
1918 | ainfo->argloc[0].loc_type | |
1919 | = riscv_arg_info::location::by_ref; | |
1920 | cinfo->memory.ref_offset | |
1921 | = align_up (cinfo->memory.ref_offset, ainfo->align); | |
1922 | ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset; | |
1923 | cinfo->memory.ref_offset += ainfo->length; | |
1924 | ainfo->argloc[0].c_length = ainfo->length; | |
1925 | ||
1926 | /* The second location for this argument is given over to holding the | |
1927 | address of the by-reference data. Pass 0 for the offset as this | |
1928 | is not part of the actual argument value. */ | |
1929 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
1930 | &cinfo->int_regs, | |
1931 | cinfo->xlen, 0)) | |
1932 | riscv_assign_stack_location (&ainfo->argloc[1], | |
1933 | &cinfo->memory, cinfo->xlen, | |
1934 | cinfo->xlen); | |
1935 | } | |
1936 | else | |
1937 | { | |
174f8ac8 JW |
1938 | int len = std::min (ainfo->length, cinfo->xlen); |
1939 | int align = std::max (ainfo->align, cinfo->xlen); | |
dbbb1059 | 1940 | |
8b2d40cb JW |
1941 | /* Unnamed arguments in registers that require 2*XLEN alignment are |
1942 | passed in an aligned register pair. */ | |
1943 | if (ainfo->is_unnamed && (align == cinfo->xlen * 2) | |
1944 | && cinfo->int_regs.next_regnum & 1) | |
1945 | cinfo->int_regs.next_regnum++; | |
1946 | ||
dbbb1059 AB |
1947 | if (!riscv_assign_reg_location (&ainfo->argloc[0], |
1948 | &cinfo->int_regs, len, 0)) | |
1949 | riscv_assign_stack_location (&ainfo->argloc[0], | |
174f8ac8 | 1950 | &cinfo->memory, len, align); |
dbbb1059 AB |
1951 | |
1952 | if (len < ainfo->length) | |
1953 | { | |
1954 | len = ainfo->length - len; | |
1955 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
1956 | &cinfo->int_regs, len, | |
1957 | cinfo->xlen)) | |
1958 | riscv_assign_stack_location (&ainfo->argloc[1], | |
1959 | &cinfo->memory, len, cinfo->xlen); | |
1960 | } | |
1961 | } | |
1962 | } | |
1963 | ||
1964 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO | |
1965 | is being passed with the floating point ABI. */ | |
1966 | ||
1967 | static void | |
1968 | riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo, | |
1969 | struct riscv_call_info *cinfo) | |
1970 | { | |
1971 | if (ainfo->length > cinfo->flen) | |
1972 | return riscv_call_arg_scalar_int (ainfo, cinfo); | |
1973 | else | |
1974 | { | |
1975 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
1976 | &cinfo->float_regs, | |
1977 | ainfo->length, 0)) | |
1978 | return riscv_call_arg_scalar_int (ainfo, cinfo); | |
1979 | } | |
1980 | } | |
1981 | ||
1982 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO | |
1983 | is a complex floating point argument, and is therefore handled | |
1984 | differently to other argument types. */ | |
1985 | ||
1986 | static void | |
1987 | riscv_call_arg_complex_float (struct riscv_arg_info *ainfo, | |
1988 | struct riscv_call_info *cinfo) | |
1989 | { | |
1990 | if (ainfo->length <= (2 * cinfo->flen) | |
1991 | && riscv_arg_regs_available (&cinfo->float_regs) >= 2) | |
1992 | { | |
1993 | bool result; | |
1994 | int len = ainfo->length / 2; | |
1995 | ||
1996 | result = riscv_assign_reg_location (&ainfo->argloc[0], | |
1997 | &cinfo->float_regs, len, len); | |
1998 | gdb_assert (result); | |
1999 | ||
2000 | result = riscv_assign_reg_location (&ainfo->argloc[1], | |
2001 | &cinfo->float_regs, len, len); | |
2002 | gdb_assert (result); | |
2003 | } | |
2004 | else | |
2005 | return riscv_call_arg_scalar_int (ainfo, cinfo); | |
2006 | } | |
2007 | ||
2008 | /* A structure used for holding information about a structure type within | |
2009 | the inferior program. The RiscV ABI has special rules for handling some | |
2010 | structures with a single field or with two fields. The counting of | |
2011 | fields here is done after flattening out all nested structures. */ | |
2012 | ||
2013 | class riscv_struct_info | |
2014 | { | |
2015 | public: | |
2016 | riscv_struct_info () | |
2017 | : m_number_of_fields (0), | |
2018 | m_types { nullptr, nullptr } | |
2019 | { | |
2020 | /* Nothing. */ | |
2021 | } | |
2022 | ||
2023 | /* Analyse TYPE descending into nested structures, count the number of | |
2024 | scalar fields and record the types of the first two fields found. */ | |
2025 | void analyse (struct type *type); | |
2026 | ||
2027 | /* The number of scalar fields found in the analysed type. This is | |
2028 | currently only accurate if the value returned is 0, 1, or 2 as the | |
2029 | analysis stops counting when the number of fields is 3. This is | |
2030 | because the RiscV ABI only has special cases for 1 or 2 fields, | |
2031 | anything else we just don't care about. */ | |
2032 | int number_of_fields () const | |
2033 | { return m_number_of_fields; } | |
2034 | ||
2035 | /* Return the type for scalar field INDEX within the analysed type. Will | |
2036 | return nullptr if there is no field at that index. Only INDEX values | |
2037 | 0 and 1 can be requested as the RiscV ABI only has special cases for | |
2038 | structures with 1 or 2 fields. */ | |
2039 | struct type *field_type (int index) const | |
2040 | { | |
2041 | gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0]))); | |
2042 | return m_types[index]; | |
2043 | } | |
2044 | ||
2045 | private: | |
2046 | /* The number of scalar fields found within the structure after recursing | |
2047 | into nested structures. */ | |
2048 | int m_number_of_fields; | |
2049 | ||
2050 | /* The types of the first two scalar fields found within the structure | |
2051 | after recursing into nested structures. */ | |
2052 | struct type *m_types[2]; | |
2053 | }; | |
2054 | ||
2055 | /* Analyse TYPE descending into nested structures, count the number of | |
2056 | scalar fields and record the types of the first two fields found. */ | |
2057 | ||
2058 | void | |
2059 | riscv_struct_info::analyse (struct type *type) | |
2060 | { | |
2061 | unsigned int count = TYPE_NFIELDS (type); | |
2062 | unsigned int i; | |
2063 | ||
2064 | for (i = 0; i < count; ++i) | |
2065 | { | |
2066 | if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS) | |
2067 | continue; | |
2068 | ||
2069 | struct type *field_type = TYPE_FIELD_TYPE (type, i); | |
2070 | field_type = check_typedef (field_type); | |
2071 | ||
2072 | switch (TYPE_CODE (field_type)) | |
2073 | { | |
2074 | case TYPE_CODE_STRUCT: | |
2075 | analyse (field_type); | |
2076 | break; | |
2077 | ||
2078 | default: | |
2079 | /* RiscV only flattens out structures. Anything else does not | |
2080 | need to be flattened, we just record the type, and when we | |
2081 | look at the analysis results we'll realise this is not a | |
2082 | structure we can special case, and pass the structure in | |
2083 | memory. */ | |
2084 | if (m_number_of_fields < 2) | |
2085 | m_types[m_number_of_fields] = field_type; | |
2086 | m_number_of_fields++; | |
2087 | break; | |
2088 | } | |
2089 | ||
2090 | /* RiscV only has special handling for structures with 1 or 2 scalar | |
2091 | fields, any more than that and the structure is just passed in | |
2092 | memory. We can safely drop out early when we find 3 or more | |
2093 | fields then. */ | |
2094 | ||
2095 | if (m_number_of_fields > 2) | |
2096 | return; | |
2097 | } | |
2098 | } | |
2099 | ||
2100 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO | |
2101 | is a structure. Small structures on RiscV have some special case | |
2102 | handling in order that the structure might be passed in register. | |
2103 | Larger structures are passed in memory. After assigning location | |
2104 | information to AINFO, CINFO will have been updated. */ | |
2105 | ||
2106 | static void | |
2107 | riscv_call_arg_struct (struct riscv_arg_info *ainfo, | |
2108 | struct riscv_call_info *cinfo) | |
2109 | { | |
2110 | if (riscv_arg_regs_available (&cinfo->float_regs) >= 1) | |
2111 | { | |
2112 | struct riscv_struct_info sinfo; | |
2113 | ||
2114 | sinfo.analyse (ainfo->type); | |
2115 | if (sinfo.number_of_fields () == 1 | |
2116 | && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_COMPLEX) | |
2117 | { | |
2118 | gdb_assert (TYPE_LENGTH (ainfo->type) | |
2119 | == TYPE_LENGTH (sinfo.field_type (0))); | |
2120 | return riscv_call_arg_complex_float (ainfo, cinfo); | |
2121 | } | |
2122 | ||
2123 | if (sinfo.number_of_fields () == 1 | |
2124 | && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT) | |
2125 | { | |
2126 | gdb_assert (TYPE_LENGTH (ainfo->type) | |
2127 | == TYPE_LENGTH (sinfo.field_type (0))); | |
2128 | return riscv_call_arg_scalar_float (ainfo, cinfo); | |
2129 | } | |
2130 | ||
2131 | if (sinfo.number_of_fields () == 2 | |
2132 | && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT | |
2133 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen | |
2134 | && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT | |
2135 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen | |
2136 | && riscv_arg_regs_available (&cinfo->float_regs) >= 2) | |
2137 | { | |
2138 | int len0, len1, offset; | |
2139 | ||
2140 | gdb_assert (TYPE_LENGTH (ainfo->type) <= (2 * cinfo->flen)); | |
2141 | ||
2142 | len0 = TYPE_LENGTH (sinfo.field_type (0)); | |
2143 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
2144 | &cinfo->float_regs, len0, 0)) | |
2145 | error (_("failed during argument setup")); | |
2146 | ||
2147 | len1 = TYPE_LENGTH (sinfo.field_type (1)); | |
2148 | offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1))); | |
2149 | gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type) | |
2150 | - TYPE_LENGTH (sinfo.field_type (0)))); | |
2151 | ||
2152 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
2153 | &cinfo->float_regs, | |
2154 | len1, offset)) | |
2155 | error (_("failed during argument setup")); | |
2156 | return; | |
2157 | } | |
2158 | ||
2159 | if (sinfo.number_of_fields () == 2 | |
2160 | && riscv_arg_regs_available (&cinfo->int_regs) >= 1 | |
2161 | && (TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT | |
2162 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen | |
2163 | && is_integral_type (sinfo.field_type (1)) | |
2164 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen)) | |
2165 | { | |
2166 | int len0, len1, offset; | |
2167 | ||
2168 | gdb_assert (TYPE_LENGTH (ainfo->type) | |
2169 | <= (cinfo->flen + cinfo->xlen)); | |
2170 | ||
2171 | len0 = TYPE_LENGTH (sinfo.field_type (0)); | |
2172 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
2173 | &cinfo->float_regs, len0, 0)) | |
2174 | error (_("failed during argument setup")); | |
2175 | ||
2176 | len1 = TYPE_LENGTH (sinfo.field_type (1)); | |
2177 | offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1))); | |
2178 | gdb_assert (len1 <= cinfo->xlen); | |
2179 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
2180 | &cinfo->int_regs, len1, offset)) | |
2181 | error (_("failed during argument setup")); | |
2182 | return; | |
2183 | } | |
2184 | ||
2185 | if (sinfo.number_of_fields () == 2 | |
2186 | && riscv_arg_regs_available (&cinfo->int_regs) >= 1 | |
2187 | && (is_integral_type (sinfo.field_type (0)) | |
2188 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen | |
2189 | && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT | |
2190 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen)) | |
2191 | { | |
2192 | int len0, len1, offset; | |
2193 | ||
2194 | gdb_assert (TYPE_LENGTH (ainfo->type) | |
2195 | <= (cinfo->flen + cinfo->xlen)); | |
2196 | ||
2197 | len0 = TYPE_LENGTH (sinfo.field_type (0)); | |
2198 | len1 = TYPE_LENGTH (sinfo.field_type (1)); | |
2199 | offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1))); | |
2200 | ||
2201 | gdb_assert (len0 <= cinfo->xlen); | |
2202 | gdb_assert (len1 <= cinfo->flen); | |
2203 | ||
2204 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
2205 | &cinfo->int_regs, len0, 0)) | |
2206 | error (_("failed during argument setup")); | |
2207 | ||
2208 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
2209 | &cinfo->float_regs, | |
2210 | len1, offset)) | |
2211 | error (_("failed during argument setup")); | |
2212 | ||
2213 | return; | |
2214 | } | |
2215 | } | |
2216 | ||
2217 | /* Non of the structure flattening cases apply, so we just pass using | |
2218 | the integer ABI. */ | |
2219 | ainfo->length = align_up (ainfo->length, cinfo->xlen); | |
2220 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
2221 | } | |
2222 | ||
2223 | /* Assign a location to call (or return) argument AINFO, the location is | |
2224 | selected from CINFO which holds information about what call argument | |
2225 | locations are available for use next. The TYPE is the type of the | |
2226 | argument being passed, this information is recorded into AINFO (along | |
8b2d40cb JW |
2227 | with some additional information derived from the type). IS_UNNAMED |
2228 | is true if this is an unnamed (stdarg) argument, this info is also | |
2229 | recorded into AINFO. | |
dbbb1059 AB |
2230 | |
2231 | After assigning a location to AINFO, CINFO will have been updated. */ | |
2232 | ||
2233 | static void | |
2234 | riscv_arg_location (struct gdbarch *gdbarch, | |
2235 | struct riscv_arg_info *ainfo, | |
2236 | struct riscv_call_info *cinfo, | |
8b2d40cb | 2237 | struct type *type, bool is_unnamed) |
dbbb1059 AB |
2238 | { |
2239 | ainfo->type = type; | |
2240 | ainfo->length = TYPE_LENGTH (ainfo->type); | |
2241 | ainfo->align = riscv_type_alignment (ainfo->type); | |
8b2d40cb | 2242 | ainfo->is_unnamed = is_unnamed; |
dbbb1059 AB |
2243 | ainfo->contents = nullptr; |
2244 | ||
2245 | switch (TYPE_CODE (ainfo->type)) | |
2246 | { | |
2247 | case TYPE_CODE_INT: | |
2248 | case TYPE_CODE_BOOL: | |
2249 | case TYPE_CODE_CHAR: | |
2250 | case TYPE_CODE_RANGE: | |
2251 | case TYPE_CODE_ENUM: | |
2252 | case TYPE_CODE_PTR: | |
2253 | if (ainfo->length <= cinfo->xlen) | |
2254 | { | |
2255 | ainfo->type = builtin_type (gdbarch)->builtin_long; | |
2256 | ainfo->length = cinfo->xlen; | |
2257 | } | |
2258 | else if (ainfo->length <= (2 * cinfo->xlen)) | |
2259 | { | |
2260 | ainfo->type = builtin_type (gdbarch)->builtin_long_long; | |
2261 | ainfo->length = 2 * cinfo->xlen; | |
2262 | } | |
2263 | ||
2264 | /* Recalculate the alignment requirement. */ | |
2265 | ainfo->align = riscv_type_alignment (ainfo->type); | |
2266 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
2267 | break; | |
2268 | ||
2269 | case TYPE_CODE_FLT: | |
2270 | riscv_call_arg_scalar_float (ainfo, cinfo); | |
2271 | break; | |
2272 | ||
2273 | case TYPE_CODE_COMPLEX: | |
2274 | riscv_call_arg_complex_float (ainfo, cinfo); | |
2275 | break; | |
2276 | ||
2277 | case TYPE_CODE_STRUCT: | |
2278 | riscv_call_arg_struct (ainfo, cinfo); | |
2279 | break; | |
2280 | ||
2281 | default: | |
2282 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
2283 | break; | |
2284 | } | |
2285 | } | |
2286 | ||
cab5bb9d AB |
2287 | /* Used for printing debug information about the call argument location in |
2288 | INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base | |
2289 | addresses for the location of pass-by-reference and | |
2290 | arguments-on-the-stack memory areas. */ | |
2291 | ||
dbbb1059 | 2292 | static void |
cab5bb9d | 2293 | riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch, |
dbbb1059 AB |
2294 | struct riscv_arg_info *info, |
2295 | CORE_ADDR sp_refs, CORE_ADDR sp_args) | |
2296 | { | |
cab5bb9d | 2297 | fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x", |
42ecac17 | 2298 | TYPE_SAFE_NAME (info->type), info->length, info->align); |
dbbb1059 AB |
2299 | switch (info->argloc[0].loc_type) |
2300 | { | |
2301 | case riscv_arg_info::location::in_reg: | |
cab5bb9d AB |
2302 | fprintf_unfiltered |
2303 | (stream, ", register %s", | |
2304 | gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno)); | |
dbbb1059 AB |
2305 | if (info->argloc[0].c_length < info->length) |
2306 | { | |
2307 | switch (info->argloc[1].loc_type) | |
2308 | { | |
2309 | case riscv_arg_info::location::in_reg: | |
cab5bb9d AB |
2310 | fprintf_unfiltered |
2311 | (stream, ", register %s", | |
2312 | gdbarch_register_name (gdbarch, | |
2313 | info->argloc[1].loc_data.regno)); | |
dbbb1059 AB |
2314 | break; |
2315 | ||
2316 | case riscv_arg_info::location::on_stack: | |
cab5bb9d AB |
2317 | fprintf_unfiltered (stream, ", on stack at offset 0x%x", |
2318 | info->argloc[1].loc_data.offset); | |
dbbb1059 AB |
2319 | break; |
2320 | ||
2321 | case riscv_arg_info::location::by_ref: | |
2322 | default: | |
2323 | /* The second location should never be a reference, any | |
2324 | argument being passed by reference just places its address | |
2325 | in the first location and is done. */ | |
2326 | error (_("invalid argument location")); | |
2327 | break; | |
2328 | } | |
2329 | ||
2330 | if (info->argloc[1].c_offset > info->argloc[0].c_length) | |
cab5bb9d AB |
2331 | fprintf_unfiltered (stream, " (offset 0x%x)", |
2332 | info->argloc[1].c_offset); | |
dbbb1059 AB |
2333 | } |
2334 | break; | |
2335 | ||
2336 | case riscv_arg_info::location::on_stack: | |
cab5bb9d AB |
2337 | fprintf_unfiltered (stream, ", on stack at offset 0x%x", |
2338 | info->argloc[0].loc_data.offset); | |
dbbb1059 AB |
2339 | break; |
2340 | ||
2341 | case riscv_arg_info::location::by_ref: | |
cab5bb9d AB |
2342 | fprintf_unfiltered |
2343 | (stream, ", by reference, data at offset 0x%x (%s)", | |
2344 | info->argloc[0].loc_data.offset, | |
2345 | core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset)); | |
dbbb1059 AB |
2346 | if (info->argloc[1].loc_type |
2347 | == riscv_arg_info::location::in_reg) | |
cab5bb9d AB |
2348 | fprintf_unfiltered |
2349 | (stream, ", address in register %s", | |
2350 | gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno)); | |
dbbb1059 AB |
2351 | else |
2352 | { | |
2353 | gdb_assert (info->argloc[1].loc_type | |
2354 | == riscv_arg_info::location::on_stack); | |
cab5bb9d AB |
2355 | fprintf_unfiltered |
2356 | (stream, ", address on stack at offset 0x%x (%s)", | |
2357 | info->argloc[1].loc_data.offset, | |
2358 | core_addr_to_string (sp_args + info->argloc[1].loc_data.offset)); | |
dbbb1059 AB |
2359 | } |
2360 | break; | |
2361 | ||
2362 | default: | |
89a3b63e | 2363 | gdb_assert_not_reached (_("unknown argument location type")); |
dbbb1059 AB |
2364 | } |
2365 | } | |
2366 | ||
2367 | /* Implement the push dummy call gdbarch callback. */ | |
2368 | ||
2369 | static CORE_ADDR | |
2370 | riscv_push_dummy_call (struct gdbarch *gdbarch, | |
2371 | struct value *function, | |
2372 | struct regcache *regcache, | |
2373 | CORE_ADDR bp_addr, | |
2374 | int nargs, | |
2375 | struct value **args, | |
2376 | CORE_ADDR sp, | |
cf84fa6b | 2377 | function_call_return_method return_method, |
dbbb1059 AB |
2378 | CORE_ADDR struct_addr) |
2379 | { | |
2380 | int i; | |
2381 | CORE_ADDR sp_args, sp_refs; | |
2382 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
dbbb1059 AB |
2383 | |
2384 | struct riscv_arg_info *arg_info = | |
2385 | (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info)); | |
dbbb1059 AB |
2386 | |
2387 | struct riscv_call_info call_info (gdbarch); | |
2388 | ||
2389 | CORE_ADDR osp = sp; | |
2390 | ||
8b2d40cb JW |
2391 | struct type *ftype = check_typedef (value_type (function)); |
2392 | ||
2393 | if (TYPE_CODE (ftype) == TYPE_CODE_PTR) | |
2394 | ftype = check_typedef (TYPE_TARGET_TYPE (ftype)); | |
2395 | ||
dbbb1059 | 2396 | /* We'll use register $a0 if we're returning a struct. */ |
cf84fa6b | 2397 | if (return_method == return_method_struct) |
dbbb1059 AB |
2398 | ++call_info.int_regs.next_regnum; |
2399 | ||
b926417a | 2400 | for (i = 0; i < nargs; ++i) |
dbbb1059 AB |
2401 | { |
2402 | struct value *arg_value; | |
2403 | struct type *arg_type; | |
b926417a | 2404 | struct riscv_arg_info *info = &arg_info[i]; |
dbbb1059 AB |
2405 | |
2406 | arg_value = args[i]; | |
2407 | arg_type = check_typedef (value_type (arg_value)); | |
2408 | ||
8b2d40cb JW |
2409 | riscv_arg_location (gdbarch, info, &call_info, arg_type, |
2410 | TYPE_VARARGS (ftype) && i >= TYPE_NFIELDS (ftype)); | |
dbbb1059 AB |
2411 | |
2412 | if (info->type != arg_type) | |
2413 | arg_value = value_cast (info->type, arg_value); | |
2414 | info->contents = value_contents (arg_value); | |
2415 | } | |
2416 | ||
2417 | /* Adjust the stack pointer and align it. */ | |
2418 | sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT); | |
2419 | sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT); | |
2420 | ||
2421 | if (riscv_debug_infcall > 0) | |
2422 | { | |
2423 | fprintf_unfiltered (gdb_stdlog, "dummy call args:\n"); | |
2424 | fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n", | |
2425 | (riscv_has_fp_abi (gdbarch) ? "is" : "is not")); | |
2426 | fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n", | |
2427 | call_info.xlen, call_info.flen); | |
cf84fa6b | 2428 | if (return_method == return_method_struct) |
dbbb1059 AB |
2429 | fprintf_unfiltered (gdb_stdlog, |
2430 | "[*] struct return pointer in register $A0\n"); | |
2431 | for (i = 0; i < nargs; ++i) | |
2432 | { | |
2433 | struct riscv_arg_info *info = &arg_info [i]; | |
2434 | ||
2435 | fprintf_unfiltered (gdb_stdlog, "[%2d] ", i); | |
cab5bb9d | 2436 | riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args); |
dbbb1059 AB |
2437 | fprintf_unfiltered (gdb_stdlog, "\n"); |
2438 | } | |
2439 | if (call_info.memory.arg_offset > 0 | |
2440 | || call_info.memory.ref_offset > 0) | |
2441 | { | |
cab5bb9d AB |
2442 | fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n", |
2443 | core_addr_to_string (osp)); | |
dbbb1059 | 2444 | fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n", |
cab5bb9d | 2445 | call_info.memory.arg_offset); |
dbbb1059 | 2446 | fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n", |
cab5bb9d | 2447 | call_info.memory.ref_offset); |
fb294655 AB |
2448 | fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n", |
2449 | core_addr_to_string_nz (osp - sp)); | |
dbbb1059 AB |
2450 | } |
2451 | } | |
2452 | ||
2453 | /* Now load the argument into registers, or onto the stack. */ | |
2454 | ||
cf84fa6b | 2455 | if (return_method == return_method_struct) |
dbbb1059 AB |
2456 | { |
2457 | gdb_byte buf[sizeof (LONGEST)]; | |
2458 | ||
2459 | store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr); | |
b66f5587 | 2460 | regcache->cooked_write (RISCV_A0_REGNUM, buf); |
dbbb1059 AB |
2461 | } |
2462 | ||
2463 | for (i = 0; i < nargs; ++i) | |
2464 | { | |
2465 | CORE_ADDR dst; | |
2466 | int second_arg_length = 0; | |
2467 | const gdb_byte *second_arg_data; | |
2468 | struct riscv_arg_info *info = &arg_info [i]; | |
2469 | ||
2470 | gdb_assert (info->length > 0); | |
2471 | ||
2472 | switch (info->argloc[0].loc_type) | |
2473 | { | |
2474 | case riscv_arg_info::location::in_reg: | |
2475 | { | |
2476 | gdb_byte tmp [sizeof (ULONGEST)]; | |
2477 | ||
2478 | gdb_assert (info->argloc[0].c_length <= info->length); | |
3399f1b3 JW |
2479 | /* FP values in FP registers must be NaN-boxed. */ |
2480 | if (riscv_is_fp_regno_p (info->argloc[0].loc_data.regno) | |
2481 | && info->argloc[0].c_length < call_info.flen) | |
2482 | memset (tmp, -1, sizeof (tmp)); | |
2483 | else | |
2484 | memset (tmp, 0, sizeof (tmp)); | |
dbbb1059 | 2485 | memcpy (tmp, info->contents, info->argloc[0].c_length); |
b66f5587 | 2486 | regcache->cooked_write (info->argloc[0].loc_data.regno, tmp); |
dbbb1059 AB |
2487 | second_arg_length = |
2488 | ((info->argloc[0].c_length < info->length) | |
2489 | ? info->argloc[1].c_length : 0); | |
2490 | second_arg_data = info->contents + info->argloc[1].c_offset; | |
2491 | } | |
2492 | break; | |
2493 | ||
2494 | case riscv_arg_info::location::on_stack: | |
2495 | dst = sp_args + info->argloc[0].loc_data.offset; | |
2496 | write_memory (dst, info->contents, info->length); | |
2497 | second_arg_length = 0; | |
2498 | break; | |
2499 | ||
2500 | case riscv_arg_info::location::by_ref: | |
2501 | dst = sp_refs + info->argloc[0].loc_data.offset; | |
2502 | write_memory (dst, info->contents, info->length); | |
2503 | ||
2504 | second_arg_length = call_info.xlen; | |
2505 | second_arg_data = (gdb_byte *) &dst; | |
2506 | break; | |
2507 | ||
2508 | default: | |
89a3b63e | 2509 | gdb_assert_not_reached (_("unknown argument location type")); |
dbbb1059 AB |
2510 | } |
2511 | ||
2512 | if (second_arg_length > 0) | |
2513 | { | |
2514 | switch (info->argloc[1].loc_type) | |
2515 | { | |
2516 | case riscv_arg_info::location::in_reg: | |
2517 | { | |
2518 | gdb_byte tmp [sizeof (ULONGEST)]; | |
2519 | ||
8c49aa89 AB |
2520 | gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno) |
2521 | && second_arg_length <= call_info.flen) | |
2522 | || second_arg_length <= call_info.xlen); | |
3399f1b3 JW |
2523 | /* FP values in FP registers must be NaN-boxed. */ |
2524 | if (riscv_is_fp_regno_p (info->argloc[1].loc_data.regno) | |
2525 | && second_arg_length < call_info.flen) | |
2526 | memset (tmp, -1, sizeof (tmp)); | |
2527 | else | |
2528 | memset (tmp, 0, sizeof (tmp)); | |
dbbb1059 | 2529 | memcpy (tmp, second_arg_data, second_arg_length); |
b66f5587 | 2530 | regcache->cooked_write (info->argloc[1].loc_data.regno, tmp); |
dbbb1059 AB |
2531 | } |
2532 | break; | |
2533 | ||
2534 | case riscv_arg_info::location::on_stack: | |
2535 | { | |
2536 | CORE_ADDR arg_addr; | |
2537 | ||
2538 | arg_addr = sp_args + info->argloc[1].loc_data.offset; | |
2539 | write_memory (arg_addr, second_arg_data, second_arg_length); | |
2540 | break; | |
2541 | } | |
2542 | ||
2543 | case riscv_arg_info::location::by_ref: | |
2544 | default: | |
2545 | /* The second location should never be a reference, any | |
2546 | argument being passed by reference just places its address | |
2547 | in the first location and is done. */ | |
2548 | error (_("invalid argument location")); | |
2549 | break; | |
2550 | } | |
2551 | } | |
2552 | } | |
2553 | ||
2554 | /* Set the dummy return value to bp_addr. | |
2555 | A dummy breakpoint will be setup to execute the call. */ | |
2556 | ||
2557 | if (riscv_debug_infcall > 0) | |
cab5bb9d AB |
2558 | fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n", |
2559 | core_addr_to_string (bp_addr)); | |
dbbb1059 AB |
2560 | regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr); |
2561 | ||
2562 | /* Finally, update the stack pointer. */ | |
2563 | ||
2564 | if (riscv_debug_infcall > 0) | |
cab5bb9d AB |
2565 | fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n", |
2566 | core_addr_to_string (sp)); | |
dbbb1059 AB |
2567 | regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp); |
2568 | ||
2569 | return sp; | |
2570 | } | |
2571 | ||
2572 | /* Implement the return_value gdbarch method. */ | |
2573 | ||
2574 | static enum return_value_convention | |
2575 | riscv_return_value (struct gdbarch *gdbarch, | |
2576 | struct value *function, | |
2577 | struct type *type, | |
2578 | struct regcache *regcache, | |
2579 | gdb_byte *readbuf, | |
2580 | const gdb_byte *writebuf) | |
2581 | { | |
dbbb1059 AB |
2582 | struct riscv_call_info call_info (gdbarch); |
2583 | struct riscv_arg_info info; | |
2584 | struct type *arg_type; | |
2585 | ||
2586 | arg_type = check_typedef (type); | |
8b2d40cb | 2587 | riscv_arg_location (gdbarch, &info, &call_info, arg_type, false); |
dbbb1059 AB |
2588 | |
2589 | if (riscv_debug_infcall > 0) | |
2590 | { | |
2591 | fprintf_unfiltered (gdb_stdlog, "riscv return value:\n"); | |
2592 | fprintf_unfiltered (gdb_stdlog, "[R] "); | |
cab5bb9d | 2593 | riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0); |
dbbb1059 AB |
2594 | fprintf_unfiltered (gdb_stdlog, "\n"); |
2595 | } | |
2596 | ||
2597 | if (readbuf != nullptr || writebuf != nullptr) | |
2598 | { | |
2599 | int regnum; | |
2600 | ||
2601 | switch (info.argloc[0].loc_type) | |
2602 | { | |
2603 | /* Return value in register(s). */ | |
2604 | case riscv_arg_info::location::in_reg: | |
2605 | { | |
2606 | regnum = info.argloc[0].loc_data.regno; | |
2607 | ||
2608 | if (readbuf) | |
dca08e1f | 2609 | regcache->cooked_read (regnum, readbuf); |
dbbb1059 AB |
2610 | |
2611 | if (writebuf) | |
b66f5587 | 2612 | regcache->cooked_write (regnum, writebuf); |
dbbb1059 AB |
2613 | |
2614 | /* A return value in register can have a second part in a | |
2615 | second register. */ | |
2616 | if (info.argloc[0].c_length < info.length) | |
2617 | { | |
2618 | switch (info.argloc[1].loc_type) | |
2619 | { | |
2620 | case riscv_arg_info::location::in_reg: | |
2621 | regnum = info.argloc[1].loc_data.regno; | |
2622 | ||
2623 | if (readbuf) | |
2624 | { | |
2625 | readbuf += info.argloc[1].c_offset; | |
dca08e1f | 2626 | regcache->cooked_read (regnum, readbuf); |
dbbb1059 AB |
2627 | } |
2628 | ||
2629 | if (writebuf) | |
2630 | { | |
2631 | writebuf += info.argloc[1].c_offset; | |
b66f5587 | 2632 | regcache->cooked_write (regnum, writebuf); |
dbbb1059 AB |
2633 | } |
2634 | break; | |
2635 | ||
2636 | case riscv_arg_info::location::by_ref: | |
2637 | case riscv_arg_info::location::on_stack: | |
2638 | default: | |
2639 | error (_("invalid argument location")); | |
2640 | break; | |
2641 | } | |
2642 | } | |
2643 | } | |
2644 | break; | |
2645 | ||
2646 | /* Return value by reference will have its address in A0. */ | |
2647 | case riscv_arg_info::location::by_ref: | |
2648 | { | |
b2970c23 | 2649 | ULONGEST addr; |
dbbb1059 AB |
2650 | |
2651 | regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM, | |
2652 | &addr); | |
2653 | if (readbuf != nullptr) | |
2654 | read_memory (addr, readbuf, info.length); | |
2655 | if (writebuf != nullptr) | |
2656 | write_memory (addr, writebuf, info.length); | |
2657 | } | |
2658 | break; | |
2659 | ||
2660 | case riscv_arg_info::location::on_stack: | |
2661 | default: | |
2662 | error (_("invalid argument location")); | |
2663 | break; | |
2664 | } | |
2665 | } | |
2666 | ||
2667 | switch (info.argloc[0].loc_type) | |
2668 | { | |
2669 | case riscv_arg_info::location::in_reg: | |
2670 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2671 | case riscv_arg_info::location::by_ref: | |
2672 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2673 | case riscv_arg_info::location::on_stack: | |
2674 | default: | |
2675 | error (_("invalid argument location")); | |
2676 | } | |
2677 | } | |
2678 | ||
2679 | /* Implement the frame_align gdbarch method. */ | |
2680 | ||
2681 | static CORE_ADDR | |
2682 | riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2683 | { | |
2684 | return align_down (addr, 16); | |
2685 | } | |
2686 | ||
2687 | /* Implement the unwind_pc gdbarch method. */ | |
2688 | ||
2689 | static CORE_ADDR | |
2690 | riscv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2691 | { | |
2692 | return frame_unwind_register_unsigned (next_frame, RISCV_PC_REGNUM); | |
2693 | } | |
2694 | ||
2695 | /* Implement the unwind_sp gdbarch method. */ | |
2696 | ||
2697 | static CORE_ADDR | |
2698 | riscv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2699 | { | |
2700 | return frame_unwind_register_unsigned (next_frame, RISCV_SP_REGNUM); | |
2701 | } | |
2702 | ||
2703 | /* Implement the dummy_id gdbarch method. */ | |
2704 | ||
2705 | static struct frame_id | |
2706 | riscv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
2707 | { | |
2708 | return frame_id_build (get_frame_register_signed (this_frame, RISCV_SP_REGNUM), | |
2709 | get_frame_pc (this_frame)); | |
2710 | } | |
2711 | ||
2712 | /* Generate, or return the cached frame cache for the RiscV frame | |
2713 | unwinder. */ | |
2714 | ||
78a3b0fa | 2715 | static struct riscv_unwind_cache * |
dbbb1059 AB |
2716 | riscv_frame_cache (struct frame_info *this_frame, void **this_cache) |
2717 | { | |
78a3b0fa AB |
2718 | CORE_ADDR pc, start_addr; |
2719 | struct riscv_unwind_cache *cache; | |
dbbb1059 | 2720 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
78a3b0fa | 2721 | int numregs, regno; |
dbbb1059 AB |
2722 | |
2723 | if ((*this_cache) != NULL) | |
78a3b0fa | 2724 | return (struct riscv_unwind_cache *) *this_cache; |
dbbb1059 | 2725 | |
78a3b0fa AB |
2726 | cache = FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache); |
2727 | cache->regs = trad_frame_alloc_saved_regs (this_frame); | |
2728 | (*this_cache) = cache; | |
dbbb1059 | 2729 | |
78a3b0fa AB |
2730 | /* Scan the prologue, filling in the cache. */ |
2731 | start_addr = get_frame_func (this_frame); | |
dbbb1059 | 2732 | pc = get_frame_pc (this_frame); |
78a3b0fa AB |
2733 | riscv_scan_prologue (gdbarch, start_addr, pc, cache); |
2734 | ||
2735 | /* We can now calculate the frame base address. */ | |
2736 | cache->frame_base | |
6c9d681b AB |
2737 | = (get_frame_register_signed (this_frame, cache->frame_base_reg) |
2738 | + cache->frame_base_offset); | |
78a3b0fa AB |
2739 | if (riscv_debug_unwinder) |
2740 | fprintf_unfiltered (gdb_stdlog, "Frame base is %s ($%s + 0x%x)\n", | |
2741 | core_addr_to_string (cache->frame_base), | |
2742 | gdbarch_register_name (gdbarch, | |
2743 | cache->frame_base_reg), | |
2744 | cache->frame_base_offset); | |
2745 | ||
2746 | /* The prologue scanner sets the address of registers stored to the stack | |
2747 | as the offset of that register from the frame base. The prologue | |
2748 | scanner doesn't know the actual frame base value, and so is unable to | |
2749 | compute the exact address. We do now know the frame base value, so | |
2750 | update the address of registers stored to the stack. */ | |
2751 | numregs = gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); | |
2752 | for (regno = 0; regno < numregs; ++regno) | |
2753 | { | |
2754 | if (trad_frame_addr_p (cache->regs, regno)) | |
2755 | cache->regs[regno].addr += cache->frame_base; | |
2756 | } | |
2757 | ||
2758 | /* The previous $pc can be found wherever the $ra value can be found. | |
2759 | The previous $ra value is gone, this would have been stored be the | |
2760 | previous frame if required. */ | |
2761 | cache->regs[gdbarch_pc_regnum (gdbarch)] = cache->regs[RISCV_RA_REGNUM]; | |
2762 | trad_frame_set_unknown (cache->regs, RISCV_RA_REGNUM); | |
2763 | ||
2764 | /* Build the frame id. */ | |
2765 | cache->this_id = frame_id_build (cache->frame_base, start_addr); | |
dbbb1059 | 2766 | |
78a3b0fa AB |
2767 | /* The previous $sp value is the frame base value. */ |
2768 | trad_frame_set_value (cache->regs, gdbarch_sp_regnum (gdbarch), | |
2769 | cache->frame_base); | |
dbbb1059 | 2770 | |
78a3b0fa | 2771 | return cache; |
dbbb1059 AB |
2772 | } |
2773 | ||
2774 | /* Implement the this_id callback for RiscV frame unwinder. */ | |
2775 | ||
2776 | static void | |
2777 | riscv_frame_this_id (struct frame_info *this_frame, | |
2778 | void **prologue_cache, | |
2779 | struct frame_id *this_id) | |
2780 | { | |
78a3b0fa | 2781 | struct riscv_unwind_cache *cache; |
dbbb1059 | 2782 | |
17cf2897 AB |
2783 | TRY |
2784 | { | |
2785 | cache = riscv_frame_cache (this_frame, prologue_cache); | |
2786 | *this_id = cache->this_id; | |
2787 | } | |
2788 | CATCH (ex, RETURN_MASK_ERROR) | |
2789 | { | |
2790 | /* Ignore errors, this leaves the frame id as the predefined outer | |
2791 | frame id which terminates the backtrace at this point. */ | |
2792 | } | |
2793 | END_CATCH | |
dbbb1059 AB |
2794 | } |
2795 | ||
2796 | /* Implement the prev_register callback for RiscV frame unwinder. */ | |
2797 | ||
2798 | static struct value * | |
2799 | riscv_frame_prev_register (struct frame_info *this_frame, | |
2800 | void **prologue_cache, | |
2801 | int regnum) | |
2802 | { | |
78a3b0fa | 2803 | struct riscv_unwind_cache *cache; |
dbbb1059 | 2804 | |
78a3b0fa AB |
2805 | cache = riscv_frame_cache (this_frame, prologue_cache); |
2806 | return trad_frame_get_prev_register (this_frame, cache->regs, regnum); | |
dbbb1059 AB |
2807 | } |
2808 | ||
2809 | /* Structure defining the RiscV normal frame unwind functions. Since we | |
2810 | are the fallback unwinder (DWARF unwinder is used first), we use the | |
2811 | default frame sniffer, which always accepts the frame. */ | |
2812 | ||
2813 | static const struct frame_unwind riscv_frame_unwind = | |
2814 | { | |
2815 | /*.type =*/ NORMAL_FRAME, | |
2816 | /*.stop_reason =*/ default_frame_unwind_stop_reason, | |
2817 | /*.this_id =*/ riscv_frame_this_id, | |
2818 | /*.prev_register =*/ riscv_frame_prev_register, | |
2819 | /*.unwind_data =*/ NULL, | |
2820 | /*.sniffer =*/ default_frame_sniffer, | |
2821 | /*.dealloc_cache =*/ NULL, | |
2822 | /*.prev_arch =*/ NULL, | |
2823 | }; | |
2824 | ||
2825 | /* Initialize the current architecture based on INFO. If possible, | |
2826 | re-use an architecture from ARCHES, which is a list of | |
2827 | architectures already created during this debugging session. | |
2828 | ||
2829 | Called e.g. at program startup, when reading a core file, and when | |
2830 | reading a binary file. */ | |
2831 | ||
2832 | static struct gdbarch * | |
2833 | riscv_gdbarch_init (struct gdbarch_info info, | |
2834 | struct gdbarch_list *arches) | |
2835 | { | |
2836 | struct gdbarch *gdbarch; | |
2837 | struct gdbarch_tdep *tdep; | |
2838 | struct gdbarch_tdep tmp_tdep; | |
dbbb1059 AB |
2839 | int i; |
2840 | ||
2841 | /* Ideally, we'd like to get as much information from the target for | |
2842 | things like register size, and whether the target has floating point | |
2843 | hardware. However, there are some things that the target can't tell | |
2844 | us, like, what ABI is being used. | |
2845 | ||
2846 | So, for now, we take as much information as possible from the ELF, | |
2847 | including things like register size, and FP hardware support, along | |
2848 | with information about the ABI. | |
2849 | ||
2850 | Information about this target is built up in TMP_TDEP, and then we | |
2851 | look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no | |
2852 | match is found we'll create a new gdbarch and copy TMP_TDEP over. */ | |
2853 | memset (&tmp_tdep, 0, sizeof (tmp_tdep)); | |
2854 | ||
2855 | if (info.abfd != NULL | |
2856 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
2857 | { | |
2858 | unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS]; | |
2859 | int e_flags = elf_elfheader (info.abfd)->e_flags; | |
2860 | ||
2861 | if (eclass == ELFCLASS32) | |
2862 | tmp_tdep.abi.fields.base_len = 1; | |
2863 | else if (eclass == ELFCLASS64) | |
2864 | tmp_tdep.abi.fields.base_len = 2; | |
2865 | else | |
2866 | internal_error (__FILE__, __LINE__, | |
2867 | _("unknown ELF header class %d"), eclass); | |
2868 | ||
2869 | if (e_flags & EF_RISCV_RVC) | |
27724bad | 2870 | tmp_tdep.core_features |= (1 << ('C' - 'A')); |
dbbb1059 AB |
2871 | |
2872 | if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE) | |
2873 | { | |
2874 | tmp_tdep.abi.fields.float_abi = 2; | |
2875 | tmp_tdep.core_features |= (1 << ('D' - 'A')); | |
2876 | tmp_tdep.core_features |= (1 << ('F' - 'A')); | |
2877 | } | |
2878 | else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE) | |
2879 | { | |
2880 | tmp_tdep.abi.fields.float_abi = 1; | |
2881 | tmp_tdep.core_features |= (1 << ('F' - 'A')); | |
2882 | } | |
2883 | } | |
2884 | else | |
2885 | { | |
2886 | const struct bfd_arch_info *binfo = info.bfd_arch_info; | |
2887 | ||
2888 | if (binfo->bits_per_word == 32) | |
2889 | tmp_tdep.abi.fields.base_len = 1; | |
2890 | else if (binfo->bits_per_word == 64) | |
2891 | tmp_tdep.abi.fields.base_len = 2; | |
2892 | else | |
2893 | internal_error (__FILE__, __LINE__, _("unknown bits_per_word %d"), | |
2894 | binfo->bits_per_word); | |
2895 | } | |
2896 | ||
2897 | /* Find a candidate among the list of pre-declared architectures. */ | |
2898 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
2899 | arches != NULL; | |
2900 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
2901 | if (gdbarch_tdep (arches->gdbarch)->abi.value == tmp_tdep.abi.value) | |
2902 | return arches->gdbarch; | |
2903 | ||
2904 | /* None found, so create a new architecture from the information provided. */ | |
2905 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof *tdep); | |
2906 | gdbarch = gdbarch_alloc (&info, tdep); | |
2907 | memcpy (tdep, &tmp_tdep, sizeof (tmp_tdep)); | |
2908 | ||
2909 | /* Target data types. */ | |
2910 | set_gdbarch_short_bit (gdbarch, 16); | |
2911 | set_gdbarch_int_bit (gdbarch, 32); | |
2912 | set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8); | |
2913 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2914 | set_gdbarch_float_bit (gdbarch, 32); | |
2915 | set_gdbarch_double_bit (gdbarch, 64); | |
2916 | set_gdbarch_long_double_bit (gdbarch, 128); | |
2917 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); | |
2918 | set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8); | |
2919 | set_gdbarch_char_signed (gdbarch, 0); | |
2920 | ||
2921 | /* Information about the target architecture. */ | |
2922 | set_gdbarch_return_value (gdbarch, riscv_return_value); | |
2923 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc); | |
2924 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind); | |
5a77b1b4 | 2925 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
dbbb1059 AB |
2926 | |
2927 | /* Register architecture. */ | |
dbbb1059 | 2928 | set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1); |
dbbb1059 AB |
2929 | set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM); |
2930 | set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM); | |
2931 | set_gdbarch_ps_regnum (gdbarch, RISCV_FP_REGNUM); | |
2932 | set_gdbarch_deprecated_fp_regnum (gdbarch, RISCV_FP_REGNUM); | |
2933 | ||
2934 | /* Functions to supply register information. */ | |
2935 | set_gdbarch_register_name (gdbarch, riscv_register_name); | |
2936 | set_gdbarch_register_type (gdbarch, riscv_register_type); | |
2937 | set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info); | |
2938 | set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p); | |
2939 | ||
2940 | /* Functions to analyze frames. */ | |
dbbb1059 AB |
2941 | set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue); |
2942 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2943 | set_gdbarch_frame_align (gdbarch, riscv_frame_align); | |
2944 | ||
2945 | /* Functions to access frame data. */ | |
2946 | set_gdbarch_unwind_pc (gdbarch, riscv_unwind_pc); | |
2947 | set_gdbarch_unwind_sp (gdbarch, riscv_unwind_sp); | |
2948 | ||
2949 | /* Functions handling dummy frames. */ | |
2950 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
2951 | set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code); | |
2952 | set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call); | |
2953 | set_gdbarch_dummy_id (gdbarch, riscv_dummy_id); | |
2954 | ||
2955 | /* Frame unwinders. Use DWARF debug info if available, otherwise use our own | |
2956 | unwinder. */ | |
2957 | dwarf2_append_unwinders (gdbarch); | |
2958 | frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind); | |
2959 | ||
dbbb1059 AB |
2960 | for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) |
2961 | user_reg_add (gdbarch, riscv_register_aliases[i].name, | |
2962 | value_of_riscv_user_reg, &riscv_register_aliases[i].regnum); | |
2963 | ||
117a0e99 JW |
2964 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
2965 | gdbarch_init_osabi (info, gdbarch); | |
2966 | ||
dbbb1059 AB |
2967 | return gdbarch; |
2968 | } | |
2969 | ||
5c720ed8 JW |
2970 | /* This decodes the current instruction and determines the address of the |
2971 | next instruction. */ | |
2972 | ||
2973 | static CORE_ADDR | |
2974 | riscv_next_pc (struct regcache *regcache, CORE_ADDR pc) | |
2975 | { | |
2976 | struct gdbarch *gdbarch = regcache->arch (); | |
2977 | struct riscv_insn insn; | |
2978 | CORE_ADDR next_pc; | |
2979 | ||
2980 | insn.decode (gdbarch, pc); | |
2981 | next_pc = pc + insn.length (); | |
2982 | ||
2983 | if (insn.opcode () == riscv_insn::JAL) | |
2984 | next_pc = pc + insn.imm_signed (); | |
2985 | else if (insn.opcode () == riscv_insn::JALR) | |
2986 | { | |
2987 | LONGEST source; | |
2988 | regcache->cooked_read (insn.rs1 (), &source); | |
2989 | next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR) 0x1; | |
2990 | } | |
2991 | else if (insn.opcode () == riscv_insn::BEQ) | |
2992 | { | |
2993 | LONGEST src1, src2; | |
2994 | regcache->cooked_read (insn.rs1 (), &src1); | |
2995 | regcache->cooked_read (insn.rs2 (), &src2); | |
2996 | if (src1 == src2) | |
2997 | next_pc = pc + insn.imm_signed (); | |
2998 | } | |
2999 | else if (insn.opcode () == riscv_insn::BNE) | |
3000 | { | |
3001 | LONGEST src1, src2; | |
3002 | regcache->cooked_read (insn.rs1 (), &src1); | |
3003 | regcache->cooked_read (insn.rs2 (), &src2); | |
3004 | if (src1 != src2) | |
3005 | next_pc = pc + insn.imm_signed (); | |
3006 | } | |
3007 | else if (insn.opcode () == riscv_insn::BLT) | |
3008 | { | |
3009 | LONGEST src1, src2; | |
3010 | regcache->cooked_read (insn.rs1 (), &src1); | |
3011 | regcache->cooked_read (insn.rs2 (), &src2); | |
3012 | if (src1 < src2) | |
3013 | next_pc = pc + insn.imm_signed (); | |
3014 | } | |
3015 | else if (insn.opcode () == riscv_insn::BGE) | |
3016 | { | |
3017 | LONGEST src1, src2; | |
3018 | regcache->cooked_read (insn.rs1 (), &src1); | |
3019 | regcache->cooked_read (insn.rs2 (), &src2); | |
3020 | if (src1 >= src2) | |
3021 | next_pc = pc + insn.imm_signed (); | |
3022 | } | |
3023 | else if (insn.opcode () == riscv_insn::BLTU) | |
3024 | { | |
3025 | ULONGEST src1, src2; | |
3026 | regcache->cooked_read (insn.rs1 (), &src1); | |
3027 | regcache->cooked_read (insn.rs2 (), &src2); | |
3028 | if (src1 < src2) | |
3029 | next_pc = pc + insn.imm_signed (); | |
3030 | } | |
3031 | else if (insn.opcode () == riscv_insn::BGEU) | |
3032 | { | |
3033 | ULONGEST src1, src2; | |
3034 | regcache->cooked_read (insn.rs1 (), &src1); | |
3035 | regcache->cooked_read (insn.rs2 (), &src2); | |
3036 | if (src1 >= src2) | |
3037 | next_pc = pc + insn.imm_signed (); | |
3038 | } | |
3039 | ||
3040 | return next_pc; | |
3041 | } | |
3042 | ||
3043 | /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look | |
3044 | for the end of the sequence and put the breakpoint there. */ | |
3045 | ||
3046 | static bool | |
3047 | riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc, | |
3048 | CORE_ADDR *next_pc) | |
3049 | { | |
3050 | struct gdbarch *gdbarch = regcache->arch (); | |
3051 | struct riscv_insn insn; | |
3052 | CORE_ADDR cur_step_pc = pc; | |
3053 | CORE_ADDR last_addr = 0; | |
3054 | ||
3055 | /* First instruction has to be a load reserved. */ | |
3056 | insn.decode (gdbarch, cur_step_pc); | |
3057 | if (insn.opcode () != riscv_insn::LR) | |
3058 | return false; | |
3059 | cur_step_pc = cur_step_pc + insn.length (); | |
3060 | ||
3061 | /* Next instruction should be branch to exit. */ | |
3062 | insn.decode (gdbarch, cur_step_pc); | |
3063 | if (insn.opcode () != riscv_insn::BNE) | |
3064 | return false; | |
3065 | last_addr = cur_step_pc + insn.imm_signed (); | |
3066 | cur_step_pc = cur_step_pc + insn.length (); | |
3067 | ||
3068 | /* Next instruction should be store conditional. */ | |
3069 | insn.decode (gdbarch, cur_step_pc); | |
3070 | if (insn.opcode () != riscv_insn::SC) | |
3071 | return false; | |
3072 | cur_step_pc = cur_step_pc + insn.length (); | |
3073 | ||
3074 | /* Next instruction should be branch to start. */ | |
3075 | insn.decode (gdbarch, cur_step_pc); | |
3076 | if (insn.opcode () != riscv_insn::BNE) | |
3077 | return false; | |
3078 | if (pc != (cur_step_pc + insn.imm_signed ())) | |
3079 | return false; | |
3080 | cur_step_pc = cur_step_pc + insn.length (); | |
3081 | ||
3082 | /* We should now be at the end of the sequence. */ | |
3083 | if (cur_step_pc != last_addr) | |
3084 | return false; | |
3085 | ||
3086 | *next_pc = cur_step_pc; | |
3087 | return true; | |
3088 | } | |
3089 | ||
3090 | /* This is called just before we want to resume the inferior, if we want to | |
3091 | single-step it but there is no hardware or kernel single-step support. We | |
3092 | find the target of the coming instruction and breakpoint it. */ | |
3093 | ||
3094 | std::vector<CORE_ADDR> | |
3095 | riscv_software_single_step (struct regcache *regcache) | |
3096 | { | |
3097 | CORE_ADDR pc, next_pc; | |
3098 | ||
3099 | pc = regcache_read_pc (regcache); | |
3100 | ||
3101 | if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc)) | |
3102 | return {next_pc}; | |
3103 | ||
3104 | next_pc = riscv_next_pc (regcache, pc); | |
3105 | ||
3106 | return {next_pc}; | |
3107 | } | |
3108 | ||
dbbb1059 AB |
3109 | void |
3110 | _initialize_riscv_tdep (void) | |
3111 | { | |
3112 | gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL); | |
3113 | ||
dbbb1059 AB |
3114 | /* Add root prefix command for all "set debug riscv" and "show debug |
3115 | riscv" commands. */ | |
3116 | add_prefix_cmd ("riscv", no_class, set_debug_riscv_command, | |
3117 | _("RISC-V specific debug commands."), | |
3118 | &setdebugriscvcmdlist, "set debug riscv ", 0, | |
3119 | &setdebuglist); | |
3120 | ||
3121 | add_prefix_cmd ("riscv", no_class, show_debug_riscv_command, | |
3122 | _("RISC-V specific debug commands."), | |
3123 | &showdebugriscvcmdlist, "show debug riscv ", 0, | |
3124 | &showdebuglist); | |
3125 | ||
f37bc8b1 JB |
3126 | add_setshow_zuinteger_cmd ("breakpoints", class_maintenance, |
3127 | &riscv_debug_breakpoints, _("\ | |
3128 | Set riscv breakpoint debugging."), _("\ | |
3129 | Show riscv breakpoint debugging."), _("\ | |
3130 | When non-zero, print debugging information for the riscv specific parts\n\ | |
3131 | of the breakpoint mechanism."), | |
3132 | NULL, | |
3133 | show_riscv_debug_variable, | |
3134 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); | |
3135 | ||
dbbb1059 AB |
3136 | add_setshow_zuinteger_cmd ("infcall", class_maintenance, |
3137 | &riscv_debug_infcall, _("\ | |
3138 | Set riscv inferior call debugging."), _("\ | |
3139 | Show riscv inferior call debugging."), _("\ | |
3140 | When non-zero, print debugging information for the riscv specific parts\n\ | |
3141 | of the inferior call mechanism."), | |
3142 | NULL, | |
3143 | show_riscv_debug_variable, | |
3144 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); | |
78a3b0fa AB |
3145 | |
3146 | add_setshow_zuinteger_cmd ("unwinder", class_maintenance, | |
3147 | &riscv_debug_unwinder, _("\ | |
3148 | Set riscv stack unwinding debugging."), _("\ | |
3149 | Show riscv stack unwinding debugging."), _("\ | |
3150 | When non-zero, print debugging information for the riscv specific parts\n\ | |
3151 | of the stack unwinding mechanism."), | |
3152 | NULL, | |
3153 | show_riscv_debug_variable, | |
3154 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); | |
dbbb1059 AB |
3155 | |
3156 | /* Add root prefix command for all "set riscv" and "show riscv" commands. */ | |
3157 | add_prefix_cmd ("riscv", no_class, set_riscv_command, | |
3158 | _("RISC-V specific commands."), | |
3159 | &setriscvcmdlist, "set riscv ", 0, &setlist); | |
3160 | ||
3161 | add_prefix_cmd ("riscv", no_class, show_riscv_command, | |
3162 | _("RISC-V specific commands."), | |
3163 | &showriscvcmdlist, "show riscv ", 0, &showlist); | |
3164 | ||
3165 | ||
3166 | use_compressed_breakpoints = AUTO_BOOLEAN_AUTO; | |
3167 | add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class, | |
3168 | &use_compressed_breakpoints, | |
3169 | _("\ | |
3170 | Set debugger's use of compressed breakpoints."), _(" \ | |
3171 | Show debugger's use of compressed breakpoints."), _("\ | |
f37bc8b1 JB |
3172 | Debugging compressed code requires compressed breakpoints to be used. If\n\ |
3173 | left to 'auto' then gdb will use them if the existing instruction is a\n\ | |
3174 | compressed instruction. If that doesn't give the correct behavior, then\n\ | |
3175 | this option can be used."), | |
dbbb1059 AB |
3176 | NULL, |
3177 | show_use_compressed_breakpoints, | |
3178 | &setriscvcmdlist, | |
3179 | &showriscvcmdlist); | |
3180 | } |