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gdb: Initial baremetal riscv support
[deliverable/binutils-gdb.git] / gdb / riscv-tdep.c
CommitLineData
dbbb1059
AB		 1/* Target-dependent code for the RISC-V architecture, for GDB.
2
3 Copyright (C) 2018 Free Software Foundation, Inc.
4
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin
7 and by Todd Snyder <todd@bluespec.com>
8 and by Mike Frysinger <vapier@gentoo.org>.
9
10 This file is part of GDB.
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24
25#include "defs.h"
26#include "frame.h"
27#include "inferior.h"
28#include "symtab.h"
29#include "value.h"
30#include "gdbcmd.h"
31#include "language.h"
32#include "gdbcore.h"
33#include "symfile.h"
34#include "objfiles.h"
35#include "gdbtypes.h"
36#include "target.h"
37#include "arch-utils.h"
38#include "regcache.h"
39#include "osabi.h"
40#include "riscv-tdep.h"
41#include "block.h"
42#include "reggroups.h"
43#include "opcode/riscv.h"
44#include "elf/riscv.h"
45#include "elf-bfd.h"
46#include "symcat.h"
47#include "dis-asm.h"
48#include "frame-unwind.h"
49#include "frame-base.h"
50#include "trad-frame.h"
51#include "infcall.h"
52#include "floatformat.h"
53#include "remote.h"
54#include "target-descriptions.h"
55#include "dwarf2-frame.h"
56#include "user-regs.h"
57#include "valprint.h"
58#include "common-defs.h"
59#include "opcode/riscv-opc.h"
60#include "cli/cli-decode.h"
61#include "observer.h"
62
63/* The stack must be 16-byte aligned. */
64#define SP_ALIGNMENT 16
65
66/* Forward declarations. */
67static bool riscv_has_feature (struct gdbarch *gdbarch, char feature);
68struct riscv_inferior_data;
69struct riscv_inferior_data * riscv_inferior_data (struct inferior *const inf);
70
71/* Define a series of is_XXX_insn functions to check if the value INSN
72 is an instance of instruction XXX. */
73#define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
74static inline bool is_ ## INSN_NAME ## _insn (long insn) \
75{ \
76 return (insn & INSN_MASK) == INSN_MATCH; \
77}
78#include "opcode/riscv-opc.h"
79#undef DECLARE_INSN
80
81/* Per inferior information for RiscV. */
82
83struct riscv_inferior_data
84{
85 /* True when MISA_VALUE is valid, otherwise false. */
86 bool misa_read;
87
88 /* If MISA_READ is true then MISA_VALUE holds the value of the MISA
89 register read from the target. */
90 uint32_t misa_value;
91};
92
93/* Key created when the RiscV per-inferior data is registered. */
94
95static const struct inferior_data *riscv_inferior_data_reg;
96
97/* Architectural name for core registers. */
98
99static const char * const riscv_gdb_reg_names[RISCV_LAST_FP_REGNUM + 1] =
100{
101 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
102 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
103 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
104 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
105 "pc",
106 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
107 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
108 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
109 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
110};
111
112/* Maps "pretty" register names onto their GDB register number. */
113
114struct register_alias
115{
116 /* The register alias. Usually more descriptive than the
117 architectural name of the register. */
118 const char *name;
119
120 /* The GDB register number. */
121 int regnum;
122};
123
124/* Table of register aliases. */
125
126static const struct register_alias riscv_register_aliases[] =
127{
128 { "zero", 0 },
129 { "ra", 1 },
130 { "sp", 2 },
131 { "gp", 3 },
132 { "tp", 4 },
133 { "t0", 5 },
134 { "t1", 6 },
135 { "t2", 7 },
136 { "fp", 8 },
137 { "s0", 8 },
138 { "s1", 9 },
139 { "a0", 10 },
140 { "a1", 11 },
141 { "a2", 12 },
142 { "a3", 13 },
143 { "a4", 14 },
144 { "a5", 15 },
145 { "a6", 16 },
146 { "a7", 17 },
147 { "s2", 18 },
148 { "s3", 19 },
149 { "s4", 20 },
150 { "s5", 21 },
151 { "s6", 22 },
152 { "s7", 23 },
153 { "s8", 24 },
154 { "s9", 25 },
155 { "s10", 26 },
156 { "s11", 27 },
157 { "t3", 28 },
158 { "t4", 29 },
159 { "t5", 30 },
160 { "t6", 31 },
161 /* pc is 32. */
162 { "ft0", 33 },
163 { "ft1", 34 },
164 { "ft2", 35 },
165 { "ft3", 36 },
166 { "ft4", 37 },
167 { "ft5", 38 },
168 { "ft6", 39 },
169 { "ft7", 40 },
170 { "fs0", 41 },
171 { "fs1", 42 },
172 { "fa0", 43 },
173 { "fa1", 44 },
174 { "fa2", 45 },
175 { "fa3", 46 },
176 { "fa4", 47 },
177 { "fa5", 48 },
178 { "fa6", 49 },
179 { "fa7", 50 },
180 { "fs2", 51 },
181 { "fs3", 52 },
182 { "fs4", 53 },
183 { "fs5", 54 },
184 { "fs6", 55 },
185 { "fs7", 56 },
186 { "fs8", 57 },
187 { "fs9", 58 },
188 { "fs10", 59 },
189 { "fs11", 60 },
190 { "ft8", 61 },
191 { "ft9", 62 },
192 { "ft10", 63 },
193 { "ft11", 64 },
194#define DECLARE_CSR(name, num) { #name, (num) + 65 },
195#include "opcode/riscv-opc.h"
196#undef DECLARE_CSR
197};
198
199/* Controls whether we place compressed breakpoints or not. When in auto
200 mode GDB tries to determine if the target supports compressed
201 breakpoints, and uses them if it does. */
202
203static enum auto_boolean use_compressed_breakpoints;
204
205/* The show callback for 'show riscv use-compressed-breakpoints'. */
206
207static void
208show_use_compressed_breakpoints (struct ui_file *file, int from_tty,
209 struct cmd_list_element *c,
210 const char *value)
211{
212 const char *additional_info;
213 struct gdbarch *gdbarch = target_gdbarch ();
214
215 if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO)
216 if (riscv_has_feature (gdbarch, 'C'))
217 additional_info = _(" (currently on)");
218 else
219 additional_info = _(" (currently off)");
220 else
221 additional_info = "";
222
223 fprintf_filtered (file,
224 _("Debugger's use of compressed breakpoints is set "
225 "to %s%s.\n"), value, additional_info);
226}
227
228/* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
229
230static struct cmd_list_element *setriscvcmdlist = NULL;
231static struct cmd_list_element *showriscvcmdlist = NULL;
232
233/* The show callback for the 'show riscv' prefix command. */
234
235static void
236show_riscv_command (const char *args, int from_tty)
237{
238 help_list (showriscvcmdlist, "show riscv ", all_commands, gdb_stdout);
239}
240
241/* The set callback for the 'set riscv' prefix command. */
242
243static void
244set_riscv_command (const char *args, int from_tty)
245{
246 printf_unfiltered
247 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
248 help_list (setriscvcmdlist, "set riscv ", all_commands, gdb_stdout);
249}
250
251/* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
252
253static struct cmd_list_element *setdebugriscvcmdlist = NULL;
254static struct cmd_list_element *showdebugriscvcmdlist = NULL;
255
256/* The show callback for the 'show debug riscv' prefix command. */
257
258static void
259show_debug_riscv_command (const char *args, int from_tty)
260{
261 help_list (showdebugriscvcmdlist, "show debug riscv ", all_commands, gdb_stdout);
262}
263
264/* The set callback for the 'set debug riscv' prefix command. */
265
266static void
267set_debug_riscv_command (const char *args, int from_tty)
268{
269 printf_unfiltered
270 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
271 help_list (setdebugriscvcmdlist, "set debug riscv ", all_commands, gdb_stdout);
272}
273
274/* The show callback for all 'show debug riscv VARNAME' variables. */
275
276static void
277show_riscv_debug_variable (struct ui_file *file, int from_tty,
278 struct cmd_list_element *c,
279 const char *value)
280{
281 fprintf_filtered (file,
282 _("RiscV debug variable `%s' is set to: %s\n"),
283 c->name, value);
284}
285
286/* When this is set to non-zero debugging information about inferior calls
287 will be printed. */
288
289static unsigned int riscv_debug_infcall = 0;
290
291/* Read the MISA register from the target. The register will only be read
292 once, and the value read will be cached. If the register can't be read
293 from the target then a default value (0) will be returned. If the
294 pointer READ_P is not null, then the bool pointed to is updated to
295 indicate if the value returned was read from the target (true) or is the
296 default (false). */
297
298static uint32_t
299riscv_read_misa_reg (bool *read_p)
300{
301 struct riscv_inferior_data *inf_data
302 = riscv_inferior_data (current_inferior ());
303
304 if (!inf_data->misa_read && target_has_registers)
305 {
306 uint32_t value = 0;
307 struct frame_info *frame = get_current_frame ();
308
309 TRY
310 {
311 value = get_frame_register_unsigned (frame, RISCV_CSR_MISA_REGNUM);
312 }
313 CATCH (ex, RETURN_MASK_ERROR)
314 {
315 /* Old cores might have MISA located at a different offset. */
316 value = get_frame_register_unsigned (frame,
317 RISCV_CSR_LEGACY_MISA_REGNUM);
318 }
319 END_CATCH
320
321 inf_data->misa_read = true;
322 inf_data->misa_value = value;
323 }
324
325 if (read_p != nullptr)
326 *read_p = inf_data->misa_read;
327
328 return inf_data->misa_value;
329}
330
331/* Return true if FEATURE is available for the architecture GDBARCH. The
332 FEATURE should be one of the single character feature codes described in
333 the RiscV ISA manual, these are between 'A' and 'Z'. */
334
335static bool
336riscv_has_feature (struct gdbarch *gdbarch, char feature)
337{
338 bool have_read_misa = false;
339 uint32_t misa;
340
341 gdb_assert (feature >= 'A' && feature <= 'Z');
342
343 /* It would be nice to always check with the real target where possible,
344 however, for compressed instructions this is a bad idea.
345
346 The call to `set_gdbarch_decr_pc_after_break' is made just once per
347 GDBARCH and we decide at that point if we should decrement by 2 or 4
348 bytes based on whether the BFD has compressed instruction support or
349 not.
350
351 If the BFD was not compiled with compressed instruction support, but we
352 are running on a target with compressed instructions then we might
353 place a 4-byte breakpoint, then decrement the $pc by 2 bytes leading to
354 confusion.
355
356 It's safer if we just make decisions about compressed instruction
357 support based on the BFD. */
358 if (feature != 'C')
359 misa = riscv_read_misa_reg (&have_read_misa);
360 if (!have_read_misa || misa == 0)
361 misa = gdbarch_tdep (gdbarch)->core_features;
362
363 return (misa & (1 << (feature - 'A'))) != 0;
364}
365
366/* Return the width in bytes of the general purpose registers for GDBARCH.
367 Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
368 RV128. */
369
370static int
371riscv_isa_xlen (struct gdbarch *gdbarch)
372{
373 switch (gdbarch_tdep (gdbarch)->abi.fields.base_len)
374 {
375 default:
376 warning (_("unknown xlen size, assuming 4 bytes"));
377 case 1:
378 return 4;
379 case 2:
380 return 8;
381 case 3:
382 return 16;
383 }
384}
385
386/* Return the width in bytes of the floating point registers for GDBARCH.
387 If this architecture has no floating point registers, then return 0.
388 Possible values are 4, 8, or 16 for depending on which of single, double
389 or quad floating point support is available. */
390
391static int
392riscv_isa_flen (struct gdbarch *gdbarch)
393{
394 if (riscv_has_feature (gdbarch, 'Q'))
395 return 16;
396 else if (riscv_has_feature (gdbarch, 'D'))
397 return 8;
398 else if (riscv_has_feature (gdbarch, 'F'))
399 return 4;
400
401 return 0;
402}
403
404/* Return true if the target for GDBARCH has floating point hardware. */
405
406static bool
407riscv_has_fp_regs (struct gdbarch *gdbarch)
408{
409 return (riscv_isa_flen (gdbarch) > 0);
410}
411
412/* Return true if GDBARCH is using any of the floating point hardware ABIs. */
413
414static bool
415riscv_has_fp_abi (struct gdbarch *gdbarch)
416{
417 return (gdbarch_tdep (gdbarch)->abi.fields.float_abi != 0);
418}
419
420/* Implement the breakpoint_kind_from_pc gdbarch method. */
421
422static int
423riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
424{
425 if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO)
426 {
427 if (riscv_has_feature (gdbarch, 'C'))
428 return 2;
429 else
430 return 4;
431 }
432 else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE)
433 return 2;
434 else
435 return 4;
436}
437
438/* Implement the sw_breakpoint_from_kind gdbarch method. */
439
440static const gdb_byte *
441riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
442{
443 static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, };
444 static const gdb_byte c_ebreak[] = { 0x02, 0x90 };
445
446 *size = kind;
447 switch (kind)
448 {
449 case 2:
450 return c_ebreak;
451 case 4:
452 return ebreak;
453 default:
454 gdb_assert_not_reached ("unhandled breakpoint kind");
455 }
456}
457
458/* Callback function for user_reg_add. */
459
460static struct value *
461value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
462{
463 const int *reg_p = (const int *) baton;
464 return value_of_register (*reg_p, frame);
465}
466
467/* Implement the register_name gdbarch method. */
468
469static const char *
470riscv_register_name (struct gdbarch *gdbarch, int regnum)
471{
472 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
473 return tdesc_register_name (gdbarch, regnum);
474
475 /* Prefer to use the alias. */
476 if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_REGNUM)
477 {
478 int i;
479
480 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
481 if (regnum == riscv_register_aliases[i].regnum)
482 return riscv_register_aliases[i].name;
483 }
484
485 if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
486 return riscv_gdb_reg_names[regnum];
487
488 if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
489 {
490 static char buf[20];
491
492 sprintf (buf, "csr%d", regnum - RISCV_FIRST_CSR_REGNUM);
493 return buf;
494 }
495
496 if (regnum == RISCV_PRIV_REGNUM)
497 return "priv";
498
499 return NULL;
500}
501
502/* Implement the pseudo_register_read gdbarch method. */
503
504static enum register_status
505riscv_pseudo_register_read (struct gdbarch *gdbarch,
506 readable_regcache *regcache,
507 int regnum,
508 gdb_byte *buf)
509{
510 return regcache->raw_read (regnum, buf);
511}
512
513/* Implement the pseudo_register_write gdbarch method. */
514
515static void
516riscv_pseudo_register_write (struct gdbarch *gdbarch,
517 struct regcache *regcache,
518 int cookednum,
519 const gdb_byte *buf)
520{
521 regcache_raw_write (regcache, cookednum, buf);
522}
523
524/* Implement the register_type gdbarch method. */
525
526static struct type *
527riscv_register_type (struct gdbarch *gdbarch, int regnum)
528{
529 int regsize;
530
531 if (regnum < RISCV_FIRST_FP_REGNUM)
532 {
533 if (regnum == gdbarch_pc_regnum (gdbarch)
534 || regnum == RISCV_RA_REGNUM)
535 return builtin_type (gdbarch)->builtin_func_ptr;
536
537 if (regnum == RISCV_FP_REGNUM
538 || regnum == RISCV_SP_REGNUM
539 || regnum == RISCV_GP_REGNUM
540 || regnum == RISCV_TP_REGNUM)
541 return builtin_type (gdbarch)->builtin_data_ptr;
542
543 /* Remaining GPRs vary in size based on the current ISA. */
544 regsize = riscv_isa_xlen (gdbarch);
545 switch (regsize)
546 {
547 case 4:
548 return builtin_type (gdbarch)->builtin_uint32;
549 case 8:
550 return builtin_type (gdbarch)->builtin_uint64;
551 case 16:
552 return builtin_type (gdbarch)->builtin_uint128;
553 default:
554 internal_error (__FILE__, __LINE__,
555 _("unknown isa regsize %i"), regsize);
556 }
557 }
558 else if (regnum <= RISCV_LAST_FP_REGNUM)
559 {
560 regsize = riscv_isa_xlen (gdbarch);
561 switch (regsize)
562 {
563 case 4:
564 return builtin_type (gdbarch)->builtin_float;
565 case 8:
566 return builtin_type (gdbarch)->builtin_double;
567 case 16:
568 return builtin_type (gdbarch)->builtin_long_double;
569 default:
570 internal_error (__FILE__, __LINE__,
571 _("unknown isa regsize %i"), regsize);
572 }
573 }
574 else if (regnum == RISCV_PRIV_REGNUM)
575 return builtin_type (gdbarch)->builtin_int8;
576 else
577 {
578 if (regnum == RISCV_CSR_FFLAGS_REGNUM
579 || regnum == RISCV_CSR_FRM_REGNUM
580 || regnum == RISCV_CSR_FCSR_REGNUM)
581 return builtin_type (gdbarch)->builtin_int32;
582
583 regsize = riscv_isa_xlen (gdbarch);
584 switch (regsize)
585 {
586 case 4:
587 return builtin_type (gdbarch)->builtin_int32;
588 case 8:
589 return builtin_type (gdbarch)->builtin_int64;
590 case 16:
591 return builtin_type (gdbarch)->builtin_int128;
592 default:
593 internal_error (__FILE__, __LINE__,
594 _("unknown isa regsize %i"), regsize);
595 }
596 }
597}
598
599/* Helper for riscv_print_registers_info, prints info for a single register
600 REGNUM. */
601
602static void
603riscv_print_one_register_info (struct gdbarch *gdbarch,
604 struct ui_file *file,
605 struct frame_info *frame,
606 int regnum)
607{
608 const char *name = gdbarch_register_name (gdbarch, regnum);
609 struct value *val = value_of_register (regnum, frame);
610 struct type *regtype = value_type (val);
611 int print_raw_format;
612 enum tab_stops { value_column_1 = 15 };
613
614 fputs_filtered (name, file);
615 print_spaces_filtered (value_column_1 - strlen (name), file);
616
617 print_raw_format = (value_entirely_available (val)
618 && !value_optimized_out (val));
619
620 if (TYPE_CODE (regtype) == TYPE_CODE_FLT)
621 {
622 struct value_print_options opts;
623 const gdb_byte *valaddr = value_contents_for_printing (val);
624 enum bfd_endian byte_order = gdbarch_byte_order (get_type_arch (regtype));
625
626 get_user_print_options (&opts);
627 opts.deref_ref = 1;
628
629 val_print (regtype,
630 value_embedded_offset (val), 0,
631 file, 0, val, &opts, current_language);
632
633 if (print_raw_format)
634 {
635 fprintf_filtered (file, "\t(raw ");
636 print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order,
637 true);
638 fprintf_filtered (file, ")");
639 }
640 }
641 else
642 {
643 struct value_print_options opts;
644
645 /* Print the register in hex. */
646 get_formatted_print_options (&opts, 'x');
647 opts.deref_ref = 1;
648 val_print (regtype,
649 value_embedded_offset (val), 0,
650 file, 0, val, &opts, current_language);
651
652 if (print_raw_format)
653 {
654 if (regnum == RISCV_CSR_MSTATUS_REGNUM)
655 {
656 LONGEST d;
657 int size = register_size (gdbarch, regnum);
658 unsigned xlen;
659
660 d = value_as_long (val);
661 xlen = size * 4;
662 fprintf_filtered (file,
663 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
664 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
665 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
666 (int) ((d >> (xlen - 1)) & 0x1),
667 (int) ((d >> 24) & 0x1f),
668 (int) ((d >> 19) & 0x1),
669 (int) ((d >> 18) & 0x1),
670 (int) ((d >> 17) & 0x1),
671 (int) ((d >> 15) & 0x3),
672 (int) ((d >> 13) & 0x3),
673 (int) ((d >> 11) & 0x3),
674 (int) ((d >> 9) & 0x3),
675 (int) ((d >> 8) & 0x1),
676 (int) ((d >> 7) & 0x1),
677 (int) ((d >> 6) & 0x1),
678 (int) ((d >> 5) & 0x1),
679 (int) ((d >> 4) & 0x1),
680 (int) ((d >> 3) & 0x1),
681 (int) ((d >> 2) & 0x1),
682 (int) ((d >> 1) & 0x1),
683 (int) ((d >> 0) & 0x1));
684 }
685 else if (regnum == RISCV_CSR_MISA_REGNUM)
686 {
687 int base;
688 unsigned xlen, i;
689 LONGEST d;
690
691 d = value_as_long (val);
692 base = d >> 30;
693 xlen = 16;
694
695 for (; base > 0; base--)
696 xlen *= 2;
697 fprintf_filtered (file, "\tRV%d", xlen);
698
699 for (i = 0; i < 26; i++)
700 {
701 if (d & (1 << i))
702 fprintf_filtered (file, "%c", 'A' + i);
703 }
704 }
705 else if (regnum == RISCV_CSR_FCSR_REGNUM
706 || regnum == RISCV_CSR_FFLAGS_REGNUM
707 || regnum == RISCV_CSR_FRM_REGNUM)
708 {
709 LONGEST d;
710
711 d = value_as_long (val);
712
713 fprintf_filtered (file, "\t");
714 if (regnum != RISCV_CSR_FRM_REGNUM)
715 fprintf_filtered (file,
716 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
717 (int) ((d >> 5) & 0x7),
718 (int) ((d >> 4) & 0x1),
719 (int) ((d >> 3) & 0x1),
720 (int) ((d >> 2) & 0x1),
721 (int) ((d >> 1) & 0x1),
722 (int) ((d >> 0) & 0x1));
723
724 if (regnum != RISCV_CSR_FFLAGS_REGNUM)
725 {
726 static const char * const sfrm[] =
727 {
728 "RNE (round to nearest; ties to even)",
729 "RTZ (Round towards zero)",
730 "RDN (Round down towards -INF)",
731 "RUP (Round up towards +INF)",
732 "RMM (Round to nearest; ties to max magnitude)",
733 "INVALID[5]",
734 "INVALID[6]",
735 "dynamic rounding mode",
736 };
737 int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
738 ? (d >> 5) : d) & 0x3;
739
740 fprintf_filtered (file, "%sFRM:%i [%s]",
741 (regnum == RISCV_CSR_FCSR_REGNUM
742 ? " " : ""),
743 frm, sfrm[frm]);
744 }
745 }
746 else if (regnum == RISCV_PRIV_REGNUM)
747 {
748 LONGEST d;
749 uint8_t priv;
750
751 d = value_as_long (val);
752 priv = d & 0xff;
753
754 if (priv < 4)
755 {
756 static const char * const sprv[] =
757 {
758 "User/Application",
759 "Supervisor",
760 "Hypervisor",
761 "Machine"
762 };
763 fprintf_filtered (file, "\tprv:%d [%s]",
764 priv, sprv[priv]);
765 }
766 else
767 fprintf_filtered (file, "\tprv:%d [INVALID]", priv);
768 }
769 else
770 {
771 /* If not a vector register, print it also according to its
772 natural format. */
773 if (TYPE_VECTOR (regtype) == 0)
774 {
775 get_user_print_options (&opts);
776 opts.deref_ref = 1;
777 fprintf_filtered (file, "\t");
778 val_print (regtype,
779 value_embedded_offset (val), 0,
780 file, 0, val, &opts, current_language);
781 }
782 }
783 }
784 }
785 fprintf_filtered (file, "\n");
786}
787
788/* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
789 of REGGROUP? */
790
791static int
792riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
793 struct reggroup *reggroup)
794{
795 int float_p;
796 int raw_p;
797 unsigned int i;
798
799 /* Used by 'info registers' and 'info registers <groupname>'. */
800
801 if (gdbarch_register_name (gdbarch, regnum) == NULL
802 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
803 return 0;
804
805 if (reggroup == all_reggroup)
806 {
807 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM)
808 return 1;
809 /* Only include CSRs that have aliases. */
810 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
811 {
812 if (regnum == riscv_register_aliases[i].regnum)
813 return 1;
814 }
815 return 0;
816 }
817 else if (reggroup == float_reggroup)
818 return ((regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
819 || (regnum == RISCV_CSR_FCSR_REGNUM
820 || regnum == RISCV_CSR_FFLAGS_REGNUM
821 || regnum == RISCV_CSR_FRM_REGNUM));
822 else if (reggroup == general_reggroup)
823 return regnum < RISCV_FIRST_FP_REGNUM;
824 else if (reggroup == restore_reggroup || reggroup == save_reggroup)
825 {
826 if (riscv_has_fp_regs (gdbarch))
827 return regnum <= RISCV_LAST_FP_REGNUM;
828 else
829 return regnum < RISCV_FIRST_FP_REGNUM;
830 }
831 else if (reggroup == system_reggroup)
832 {
833 if (regnum == RISCV_PRIV_REGNUM)
834 return 1;
835 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM)
836 return 0;
837 /* Only include CSRs that have aliases. */
838 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
839 {
840 if (regnum == riscv_register_aliases[i].regnum)
841 return 1;
842 }
843 return 0;
844 }
845 else if (reggroup == vector_reggroup)
846 return 0;
847 else
848 return 0;
849}
850
851/* Implement the print_registers_info gdbarch method. This is used by
852 'info registers' and 'info all-registers'. */
853
854static void
855riscv_print_registers_info (struct gdbarch *gdbarch,
856 struct ui_file *file,
857 struct frame_info *frame,
858 int regnum, int print_all)
859{
860 if (regnum != -1)
861 {
862 /* Print one specified register. */
863 gdb_assert (regnum <= RISCV_LAST_REGNUM);
864 if (gdbarch_register_name (gdbarch, regnum) == NULL
865 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
866 error (_("Not a valid register for the current processor type"));
867 riscv_print_one_register_info (gdbarch, file, frame, regnum);
868 }
869 else
870 {
871 struct reggroup *reggroup;
872
873 if (print_all)
874 reggroup = all_reggroup;
875 else
876 reggroup = general_reggroup;
877
878 for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum)
879 {
880 /* Zero never changes, so might as well hide by default. */
881 if (regnum == RISCV_ZERO_REGNUM && !print_all)
882 continue;
883
884 /* Registers with no name are not valid on this ISA. */
885 if (gdbarch_register_name (gdbarch, regnum) == NULL
886 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
887 continue;
888
889 /* Is the register in the group we're interested in? */
890 if (!riscv_register_reggroup_p (gdbarch, regnum, reggroup))
891 continue;
892
893 riscv_print_one_register_info (gdbarch, file, frame, regnum);
894 }
895 }
896}
897
898/* Class that handles one decoded RiscV instruction. */
899
900class riscv_insn
901{
902public:
903
904 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
905 enum opcode
906 {
907 /* Unknown value is used at initialisation time. */
908 UNKNOWN = 0,
909
910 /* These instructions are all the ones we are interested in during the
911 prologue scan. */
912 ADD,
913 ADDI,
914 ADDIW,
915 ADDW,
916 AUIPC,
917 LUI,
918 SD,
919 SW,
920
921 /* Other instructions are not interesting during the prologue scan, and
922 are ignored. */
923 OTHER
924 };
925
926 riscv_insn ()
927 : m_length (0),
928 m_opcode (OTHER),
929 m_rd (0),
930 m_rs1 (0),
931 m_rs2 (0)
932 {
933 /* Nothing. */
934 }
935
936 void decode (struct gdbarch *gdbarch, CORE_ADDR pc);
937
938 /* Get the length of the instruction in bytes. */
939 int length () const
940 { return m_length; }
941
942 /* Get the opcode for this instruction. */
943 enum opcode opcode () const
944 { return m_opcode; }
945
946 /* Get destination register field for this instruction. This is only
947 valid if the OPCODE implies there is such a field for this
948 instruction. */
949 int rd () const
950 { return m_rd; }
951
952 /* Get the RS1 register field for this instruction. This is only valid
953 if the OPCODE implies there is such a field for this instruction. */
954 int rs1 () const
955 { return m_rs1; }
956
957 /* Get the RS2 register field for this instruction. This is only valid
958 if the OPCODE implies there is such a field for this instruction. */
959 int rs2 () const
960 { return m_rs2; }
961
962 /* Get the immediate for this instruction in signed form. This is only
963 valid if the OPCODE implies there is such a field for this
964 instruction. */
965 int imm_signed () const
966 { return m_imm.s; }
967
968private:
969
970 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
971 int decode_register_index (unsigned long opcode, int offset)
972 {
973 return (opcode >> offset) & 0x1F;
974 }
975
976 /* Helper for DECODE, decode 32-bit R-type instruction. */
977 void decode_r_type_insn (enum opcode opcode, ULONGEST ival)
978 {
979 m_opcode = opcode;
980 m_rd = decode_register_index (ival, OP_SH_RD);
981 m_rs1 = decode_register_index (ival, OP_SH_RS1);
982 m_rs2 = decode_register_index (ival, OP_SH_RS2);
983 }
984
985 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
986 void decode_cr_type_insn (enum opcode opcode, ULONGEST ival)
987 {
988 m_opcode = opcode;
989 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
990 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
991 }
992
993 /* Helper for DECODE, decode 32-bit I-type instruction. */
994 void decode_i_type_insn (enum opcode opcode, ULONGEST ival)
995 {
996 m_opcode = opcode;
997 m_rd = decode_register_index (ival, OP_SH_RD);
998 m_rs1 = decode_register_index (ival, OP_SH_RS1);
999 m_imm.s = EXTRACT_ITYPE_IMM (ival);
1000 }
1001
1002 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
1003 void decode_ci_type_insn (enum opcode opcode, ULONGEST ival)
1004 {
1005 m_opcode = opcode;
1006 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
1007 m_imm.s = EXTRACT_RVC_IMM (ival);
1008 }
1009
1010 /* Helper for DECODE, decode 32-bit S-type instruction. */
1011 void decode_s_type_insn (enum opcode opcode, ULONGEST ival)
1012 {
1013 m_opcode = opcode;
1014 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1015 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1016 m_imm.s = EXTRACT_STYPE_IMM (ival);
1017 }
1018
1019 /* Helper for DECODE, decode 32-bit U-type instruction. */
1020 void decode_u_type_insn (enum opcode opcode, ULONGEST ival)
1021 {
1022 m_opcode = opcode;
1023 m_rd = decode_register_index (ival, OP_SH_RD);
1024 m_imm.s = EXTRACT_UTYPE_IMM (ival);
1025 }
1026
1027 /* Fetch instruction from target memory at ADDR, return the content of
1028 the instruction, and update LEN with the instruction length. */
1029 static ULONGEST fetch_instruction (struct gdbarch *gdbarch,
1030 CORE_ADDR addr, int *len);
1031
1032 /* The length of the instruction in bytes. Should be 2 or 4. */
1033 int m_length;
1034
1035 /* The instruction opcode. */
1036 enum opcode m_opcode;
1037
1038 /* The three possible registers an instruction might reference. Not
1039 every instruction fills in all of these registers. Which fields are
1040 valid depends on the opcode. The naming of these fields matches the
1041 naming in the riscv isa manual. */
1042 int m_rd;
1043 int m_rs1;
1044 int m_rs2;
1045
1046 /* Possible instruction immediate. This is only valid if the instruction
1047 format contains an immediate, not all instruction, whether this is
1048 valid depends on the opcode. Despite only having one format for now
1049 the immediate is packed into a union, later instructions might require
1050 an unsigned formatted immediate, having the union in place now will
1051 reduce the need for code churn later. */
1052 union riscv_insn_immediate
1053 {
1054 riscv_insn_immediate ()
1055 : s (0)
1056 {
1057 /* Nothing. */
1058 }
1059
1060 int s;
1061 } m_imm;
1062};
1063
1064/* Fetch instruction from target memory at ADDR, return the content of the
1065 instruction, and update LEN with the instruction length. */
1066
1067ULONGEST
1068riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
1069 CORE_ADDR addr, int *len)
1070{
1071 enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
1072 gdb_byte buf[8];
1073 int instlen, status;
1074
1075 /* All insns are at least 16 bits. */
1076 status = target_read_memory (addr, buf, 2);
1077 if (status)
1078 memory_error (TARGET_XFER_E_IO, addr);
1079
1080 /* If we need more, grab it now. */
1081 instlen = riscv_insn_length (buf[0]);
1082 *len = instlen;
1083 if (instlen > sizeof (buf))
1084 internal_error (__FILE__, __LINE__,
1085 _("%s: riscv_insn_length returned %i"),
1086 __func__, instlen);
1087 else if (instlen > 2)
1088 {
1089 status = target_read_memory (addr + 2, buf + 2, instlen - 2);
1090 if (status)
1091 memory_error (TARGET_XFER_E_IO, addr + 2);
1092 }
1093
1094 return extract_unsigned_integer (buf, instlen, byte_order);
1095}
1096
1097/* Fetch from target memory an instruction at PC and decode it. */
1098
1099void
1100riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc)
1101{
1102 ULONGEST ival;
1103
1104 /* Fetch the instruction, and the instructions length. */
1105 ival = fetch_instruction (gdbarch, pc, &m_length);
1106
1107 if (m_length == 4)
1108 {
1109 if (is_add_insn (ival))
1110 decode_r_type_insn (ADD, ival);
1111 else if (is_addw_insn (ival))
1112 decode_r_type_insn (ADDW, ival);
1113 else if (is_addi_insn (ival))
1114 decode_i_type_insn (ADDI, ival);
1115 else if (is_addiw_insn (ival))
1116 decode_i_type_insn (ADDIW, ival);
1117 else if (is_auipc_insn (ival))
1118 decode_u_type_insn (AUIPC, ival);
1119 else if (is_lui_insn (ival))
1120 decode_u_type_insn (LUI, ival);
1121 else if (is_sd_insn (ival))
1122 decode_s_type_insn (SD, ival);
1123 else if (is_sw_insn (ival))
1124 decode_s_type_insn (SW, ival);
1125 else
1126 /* None of the other fields are valid in this case. */
1127 m_opcode = OTHER;
1128 }
1129 else if (m_length == 2)
1130 {
1131 if (is_c_add_insn (ival))
1132 decode_cr_type_insn (ADD, ival);
1133 else if (is_c_addw_insn (ival))
1134 decode_cr_type_insn (ADDW, ival);
1135 else if (is_c_addi_insn (ival))
1136 decode_ci_type_insn (ADDI, ival);
1137 else if (is_c_addiw_insn (ival))
1138 decode_ci_type_insn (ADDIW, ival);
1139 else if (is_c_addi16sp_insn (ival))
1140 {
1141 m_opcode = ADDI;
1142 m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD);
1143 m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival);
1144 }
1145 else if (is_lui_insn (ival))
1146 m_opcode = OTHER;
1147 else if (is_c_sd_insn (ival))
1148 m_opcode = OTHER;
1149 else if (is_sw_insn (ival))
1150 m_opcode = OTHER;
1151 else
1152 /* None of the other fields of INSN are valid in this case. */
1153 m_opcode = OTHER;
1154 }
1155 else
1156 internal_error (__FILE__, __LINE__,
1157 _("unable to decode %d byte instructions in "
1158 "prologue at %s"), m_length,
1159 core_addr_to_string (pc));
1160}
1161
1162/* The prologue scanner. This is currently only used for skipping the
1163 prologue of a function when the DWARF information is not sufficient.
1164 However, it is written with filling of the frame cache in mind, which
1165 is why different groups of stack setup instructions are split apart
1166 during the core of the inner loop. In the future, the intention is to
1167 extend this function to fully support building up a frame cache that
1168 can unwind register values when there is no DWARF information. */
1169
1170static CORE_ADDR
1171riscv_scan_prologue (struct gdbarch *gdbarch,
1172 CORE_ADDR start_pc, CORE_ADDR limit_pc)
1173{
1174 CORE_ADDR cur_pc, next_pc;
1175 long frame_offset = 0;
1176 CORE_ADDR end_prologue_addr = 0;
1177
1178 if (limit_pc > start_pc + 200)
1179 limit_pc = start_pc + 200;
1180
1181 for (next_pc = cur_pc = start_pc; cur_pc < limit_pc; cur_pc = next_pc)
1182 {
1183 struct riscv_insn insn;
1184
1185 /* Decode the current instruction, and decide where the next
1186 instruction lives based on the size of this instruction. */
1187 insn.decode (gdbarch, cur_pc);
1188 gdb_assert (insn.length () > 0);
1189 next_pc = cur_pc + insn.length ();
1190
1191 /* Look for common stack adjustment insns. */
1192 if ((insn.opcode () == riscv_insn::ADDI
1193 || insn.opcode () == riscv_insn::ADDIW)
1194 && insn.rd () == RISCV_SP_REGNUM
1195 && insn.rs1 () == RISCV_SP_REGNUM)
1196 {
1197 /* Handle: addi sp, sp, -i
1198 or: addiw sp, sp, -i */
1199 if (insn.imm_signed () < 0)
1200 frame_offset += insn.imm_signed ();
1201 else
1202 break;
1203 }
1204 else if ((insn.opcode () == riscv_insn::SW
1205 || insn.opcode () == riscv_insn::SD)
1206 && (insn.rs1 () == RISCV_SP_REGNUM
1207 || insn.rs1 () == RISCV_FP_REGNUM))
1208 {
1209 /* Handle: sw reg, offset(sp)
1210 or: sd reg, offset(sp)
1211 or: sw reg, offset(s0)
1212 or: sd reg, offset(s0) */
1213 /* Instruction storing a register onto the stack. */
1214 }
1215 else if (insn.opcode () == riscv_insn::ADDI
1216 && insn.rd () == RISCV_FP_REGNUM
1217 && insn.rs1 () == RISCV_SP_REGNUM)
1218 {
1219 /* Handle: addi s0, sp, size */
1220 /* Instructions setting up the frame pointer. */
1221 }
1222 else if ((insn.opcode () == riscv_insn::ADD
1223 || insn.opcode () == riscv_insn::ADDW)
1224 && insn.rd () == RISCV_FP_REGNUM
1225 && insn.rs1 () == RISCV_SP_REGNUM
1226 && insn.rs2 () == RISCV_ZERO_REGNUM)
1227 {
1228 /* Handle: add s0, sp, 0
1229 or: addw s0, sp, 0 */
1230 /* Instructions setting up the frame pointer. */
1231 }
1232 else if ((insn.rd () == RISCV_GP_REGNUM
1233 && (insn.opcode () == riscv_insn::AUIPC
1234 || insn.opcode () == riscv_insn::LUI
1235 || (insn.opcode () == riscv_insn::ADDI
1236 && insn.rs1 () == RISCV_GP_REGNUM)
1237 || (insn.opcode () == riscv_insn::ADD
1238 && (insn.rs1 () == RISCV_GP_REGNUM
1239 || insn.rs2 () == RISCV_GP_REGNUM))))
1240 || (insn.opcode () == riscv_insn::ADDI
1241 && insn.rd () == RISCV_ZERO_REGNUM
1242 && insn.rs1 () == RISCV_ZERO_REGNUM
1243 && insn.imm_signed () == 0))
1244 {
1245 /* Handle: auipc gp, n
1246 or: addi gp, gp, n
1247 or: add gp, gp, reg
1248 or: add gp, reg, gp
1249 or: lui gp, n
1250 or: add x0, x0, 0 (NOP) */
1251 /* These instructions are part of the prologue, but we don't need
1252 to do anything special to handle them. */
1253 }
1254 else
1255 {
1256 if (end_prologue_addr == 0)
1257 end_prologue_addr = cur_pc;
1258 }
1259 }
1260
1261 if (end_prologue_addr == 0)
1262 end_prologue_addr = cur_pc;
1263
1264 return end_prologue_addr;
1265}
1266
1267/* Implement the riscv_skip_prologue gdbarch method. */
1268
1269static CORE_ADDR
1270riscv_skip_prologue (struct gdbarch *gdbarch,
1271 CORE_ADDR pc)
1272{
1273 CORE_ADDR limit_pc;
1274 CORE_ADDR func_addr;
1275
1276 /* See if we can determine the end of the prologue via the symbol
1277 table. If so, then return either PC, or the PC after the
1278 prologue, whichever is greater. */
1279 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1280 {
1281 CORE_ADDR post_prologue_pc
1282 = skip_prologue_using_sal (gdbarch, func_addr);
1283
1284 if (post_prologue_pc != 0)
1285 return std::max (pc, post_prologue_pc);
1286 }
1287
1288 /* Can't determine prologue from the symbol table, need to examine
1289 instructions. */
1290
1291 /* Find an upper limit on the function prologue using the debug
1292 information. If the debug information could not be used to provide
1293 that bound, then use an arbitrary large number as the upper bound. */
1294 limit_pc = skip_prologue_using_sal (gdbarch, pc);
1295 if (limit_pc == 0)
1296 limit_pc = pc + 100; /* MAGIC! */
1297
1298 return riscv_scan_prologue (gdbarch, pc, limit_pc);
1299}
1300
1301/* Implement the gdbarch push dummy code callback. */
1302
1303static CORE_ADDR
1304riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
1305 CORE_ADDR funaddr, struct value **args, int nargs,
1306 struct type *value_type, CORE_ADDR *real_pc,
1307 CORE_ADDR *bp_addr, struct regcache *regcache)
1308{
1309 /* Allocate space for a breakpoint, and keep the stack correctly
1310 aligned. */
1311 sp -= 16;
1312 *bp_addr = sp;
1313 *real_pc = funaddr;
1314 return sp;
1315}
1316
1317/* Compute the alignment of the type T. Used while setting up the
1318 arguments for a dummy call. */
1319
1320static int
1321riscv_type_alignment (struct type *t)
1322{
1323 t = check_typedef (t);
1324 switch (TYPE_CODE (t))
1325 {
1326 default:
1327 error (_("Could not compute alignment of type"));
1328
1329 case TYPE_CODE_RVALUE_REF:
1330 case TYPE_CODE_PTR:
1331 case TYPE_CODE_ENUM:
1332 case TYPE_CODE_INT:
1333 case TYPE_CODE_FLT:
1334 case TYPE_CODE_REF:
1335 case TYPE_CODE_CHAR:
1336 case TYPE_CODE_BOOL:
1337 return TYPE_LENGTH (t);
1338
1339 case TYPE_CODE_ARRAY:
1340 case TYPE_CODE_COMPLEX:
1341 return riscv_type_alignment (TYPE_TARGET_TYPE (t));
1342
1343 case TYPE_CODE_STRUCT:
1344 case TYPE_CODE_UNION:
1345 {
1346 int i;
1347 int align = 1;
1348
1349 for (i = 0; i < TYPE_NFIELDS (t); ++i)
1350 {
1351 if (TYPE_FIELD_LOC_KIND (t, i) == FIELD_LOC_KIND_BITPOS)
1352 {
1353 int a = riscv_type_alignment (TYPE_FIELD_TYPE (t, i));
1354 if (a > align)
1355 align = a;
1356 }
1357 }
1358 return align;
1359 }
1360 }
1361}
1362
1363/* Holds information about a single argument either being passed to an
1364 inferior function, or returned from an inferior function. This includes
1365 information about the size, type, etc of the argument, and also
1366 information about how the argument will be passed (or returned). */
1367
1368struct riscv_arg_info
1369{
1370 /* Contents of the argument. */
1371 const gdb_byte *contents;
1372
1373 /* Length of argument. */
1374 int length;
1375
1376 /* Alignment required for an argument of this type. */
1377 int align;
1378
1379 /* The type for this argument. */
1380 struct type *type;
1381
1382 /* Each argument can have either 1 or 2 locations assigned to it. Each
1383 location describes where part of the argument will be placed. The
1384 second location is valid based on the LOC_TYPE and C_LENGTH fields
1385 of the first location (which is always valid). */
1386 struct location
1387 {
1388 /* What type of location this is. */
1389 enum location_type
1390 {
1391 /* Argument passed in a register. */
1392 in_reg,
1393
1394 /* Argument passed as an on stack argument. */
1395 on_stack,
1396
1397 /* Argument passed by reference. The second location is always
1398 valid for a BY_REF argument, and describes where the address
1399 of the BY_REF argument should be placed. */
1400 by_ref
1401 } loc_type;
1402
1403 /* Information that depends on the location type. */
1404 union
1405 {
1406 /* Which register number to use. */
1407 int regno;
1408
1409 /* The offset into the stack region. */
1410 int offset;
1411 } loc_data;
1412
1413 /* The length of contents covered by this location. If this is less
1414 than the total length of the argument, then the second location
1415 will be valid, and will describe where the rest of the argument
1416 will go. */
1417 int c_length;
1418
1419 /* The offset within CONTENTS for this part of the argument. Will
1420 always be 0 for the first part. For the second part of the
1421 argument, this might be the C_LENGTH value of the first part,
1422 however, if we are passing a structure in two registers, and there's
1423 is padding between the first and second field, then this offset
1424 might be greater than the length of the first argument part. When
1425 the second argument location is not holding part of the argument
1426 value, but is instead holding the address of a reference argument,
1427 then this offset will be set to 0. */
1428 int c_offset;
1429 } argloc[2];
1430};
1431
1432/* Information about a set of registers being used for passing arguments as
1433 part of a function call. The register set must be numerically
1434 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1435 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1436
1437struct riscv_arg_reg
1438{
1439 riscv_arg_reg (int first, int last)
1440 : next_regnum (first),
1441 last_regnum (last)
1442 {
1443 /* Nothing. */
1444 }
1445
1446 /* The GDB register number to use in this set. */
1447 int next_regnum;
1448
1449 /* The last GDB register number to use in this set. */
1450 int last_regnum;
1451};
1452
1453/* Arguments can be passed as on stack arguments, or by reference. The
1454 on stack arguments must be in a continuous region starting from $sp,
1455 while the by reference arguments can be anywhere, but we'll put them
1456 on the stack after (at higher address) the on stack arguments.
1457
1458 This might not be the right approach to take. The ABI is clear that
1459 an argument passed by reference can be modified by the callee, which
1460 us placing the argument (temporarily) onto the stack will not achieve
1461 (changes will be lost). There's also the possibility that very large
1462 arguments could overflow the stack.
1463
1464 This struct is used to track offset into these two areas for where
1465 arguments are to be placed. */
1466struct riscv_memory_offsets
1467{
1468 riscv_memory_offsets ()
1469 : arg_offset (0),
1470 ref_offset (0)
1471 {
1472 /* Nothing. */
1473 }
1474
1475 /* Offset into on stack argument area. */
1476 int arg_offset;
1477
1478 /* Offset into the pass by reference area. */
1479 int ref_offset;
1480};
1481
1482/* Holds information about where arguments to a call will be placed. This
1483 is updated as arguments are added onto the call, and can be used to
1484 figure out where the next argument should be placed. */
1485
1486struct riscv_call_info
1487{
1488 riscv_call_info (struct gdbarch *gdbarch)
1489 : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7),
1490 float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7)
1491 {
1492 xlen = riscv_isa_xlen (gdbarch);
1493 flen = riscv_isa_flen (gdbarch);
1494
1495 /* Disable use of floating point registers if needed. */
1496 if (!riscv_has_fp_abi (gdbarch))
1497 float_regs.next_regnum = float_regs.last_regnum + 1;
1498 }
1499
1500 /* Track the memory areas used for holding in-memory arguments to a
1501 call. */
1502 struct riscv_memory_offsets memory;
1503
1504 /* Holds information about the next integer register to use for passing
1505 an argument. */
1506 struct riscv_arg_reg int_regs;
1507
1508 /* Holds information about the next floating point register to use for
1509 passing an argument. */
1510 struct riscv_arg_reg float_regs;
1511
1512 /* The XLEN and FLEN are copied in to this structure for convenience, and
1513 are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */
1514 int xlen;
1515 int flen;
1516};
1517
1518/* Return the number of registers available for use as parameters in the
1519 register set REG. Returned value can be 0 or more. */
1520
1521static int
1522riscv_arg_regs_available (struct riscv_arg_reg *reg)
1523{
1524 if (reg->next_regnum > reg->last_regnum)
1525 return 0;
1526
1527 return (reg->last_regnum - reg->next_regnum + 1);
1528}
1529
1530/* If there is at least one register available in the register set REG then
1531 the next register from REG is assigned to LOC and the length field of
1532 LOC is updated to LENGTH. The register set REG is updated to indicate
1533 that the assigned register is no longer available and the function
1534 returns true.
1535
1536 If there are no registers available in REG then the function returns
1537 false, and LOC and REG are unchanged. */
1538
1539static bool
1540riscv_assign_reg_location (struct riscv_arg_info::location *loc,
1541 struct riscv_arg_reg *reg,
1542 int length, int offset)
1543{
1544 if (reg->next_regnum <= reg->last_regnum)
1545 {
1546 loc->loc_type = riscv_arg_info::location::in_reg;
1547 loc->loc_data.regno = reg->next_regnum;
1548 reg->next_regnum++;
1549 loc->c_length = length;
1550 loc->c_offset = offset;
1551 return true;
1552 }
1553
1554 return false;
1555}
1556
1557/* Assign LOC a location as the next stack parameter, and update MEMORY to
1558 record that an area of stack has been used to hold the parameter
1559 described by LOC.
1560
1561 The length field of LOC is updated to LENGTH, the length of the
1562 parameter being stored, and ALIGN is the alignment required by the
1563 parameter, which will affect how memory is allocated out of MEMORY. */
1564
1565static void
1566riscv_assign_stack_location (struct riscv_arg_info::location *loc,
1567 struct riscv_memory_offsets *memory,
1568 int length, int align)
1569{
1570 loc->loc_type = riscv_arg_info::location::on_stack;
1571 memory->arg_offset
1572 = align_up (memory->arg_offset, align);
1573 loc->loc_data.offset = memory->arg_offset;
1574 memory->arg_offset += length;
1575 loc->c_length = length;
1576
1577 /* Offset is always 0, either we're the first location part, in which
1578 case we're reading content from the start of the argument, or we're
1579 passing the address of a reference argument, so 0. */
1580 loc->c_offset = 0;
1581}
1582
1583/* Update AINFO, which describes an argument that should be passed or
1584 returned using the integer ABI. The argloc fields within AINFO are
1585 updated to describe the location in which the argument will be passed to
1586 a function, or returned from a function.
1587
1588 The CINFO structure contains the ongoing call information, the holds
1589 information such as which argument registers are remaining to be
1590 assigned to parameter, and how much memory has been used by parameters
1591 so far.
1592
1593 By examining the state of CINFO a suitable location can be selected,
1594 and assigned to AINFO. */
1595
1596static void
1597riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo,
1598 struct riscv_call_info *cinfo)
1599{
1600 if (ainfo->length > (2 * cinfo->xlen))
1601 {
1602 /* Argument is going to be passed by reference. */
1603 ainfo->argloc[0].loc_type
1604 = riscv_arg_info::location::by_ref;
1605 cinfo->memory.ref_offset
1606 = align_up (cinfo->memory.ref_offset, ainfo->align);
1607 ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset;
1608 cinfo->memory.ref_offset += ainfo->length;
1609 ainfo->argloc[0].c_length = ainfo->length;
1610
1611 /* The second location for this argument is given over to holding the
1612 address of the by-reference data. Pass 0 for the offset as this
1613 is not part of the actual argument value. */
1614 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1615 &cinfo->int_regs,
1616 cinfo->xlen, 0))
1617 riscv_assign_stack_location (&ainfo->argloc[1],
1618 &cinfo->memory, cinfo->xlen,
1619 cinfo->xlen);
1620 }
1621 else
1622 {
1623 int len = (ainfo->length > cinfo->xlen) ? cinfo->xlen : ainfo->length;
1624
1625 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1626 &cinfo->int_regs, len, 0))
1627 riscv_assign_stack_location (&ainfo->argloc[0],
1628 &cinfo->memory, len, ainfo->align);
1629
1630 if (len < ainfo->length)
1631 {
1632 len = ainfo->length - len;
1633 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1634 &cinfo->int_regs, len,
1635 cinfo->xlen))
1636 riscv_assign_stack_location (&ainfo->argloc[1],
1637 &cinfo->memory, len, cinfo->xlen);
1638 }
1639 }
1640}
1641
1642/* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1643 is being passed with the floating point ABI. */
1644
1645static void
1646riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo,
1647 struct riscv_call_info *cinfo)
1648{
1649 if (ainfo->length > cinfo->flen)
1650 return riscv_call_arg_scalar_int (ainfo, cinfo);
1651 else
1652 {
1653 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1654 &cinfo->float_regs,
1655 ainfo->length, 0))
1656 return riscv_call_arg_scalar_int (ainfo, cinfo);
1657 }
1658}
1659
1660/* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1661 is a complex floating point argument, and is therefore handled
1662 differently to other argument types. */
1663
1664static void
1665riscv_call_arg_complex_float (struct riscv_arg_info *ainfo,
1666 struct riscv_call_info *cinfo)
1667{
1668 if (ainfo->length <= (2 * cinfo->flen)
1669 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
1670 {
1671 bool result;
1672 int len = ainfo->length / 2;
1673
1674 result = riscv_assign_reg_location (&ainfo->argloc[0],
1675 &cinfo->float_regs, len, len);
1676 gdb_assert (result);
1677
1678 result = riscv_assign_reg_location (&ainfo->argloc[1],
1679 &cinfo->float_regs, len, len);
1680 gdb_assert (result);
1681 }
1682 else
1683 return riscv_call_arg_scalar_int (ainfo, cinfo);
1684}
1685
1686/* A structure used for holding information about a structure type within
1687 the inferior program. The RiscV ABI has special rules for handling some
1688 structures with a single field or with two fields. The counting of
1689 fields here is done after flattening out all nested structures. */
1690
1691class riscv_struct_info
1692{
1693public:
1694 riscv_struct_info ()
1695 : m_number_of_fields (0),
1696 m_types { nullptr, nullptr }
1697 {
1698 /* Nothing. */
1699 }
1700
1701 /* Analyse TYPE descending into nested structures, count the number of
1702 scalar fields and record the types of the first two fields found. */
1703 void analyse (struct type *type);
1704
1705 /* The number of scalar fields found in the analysed type. This is
1706 currently only accurate if the value returned is 0, 1, or 2 as the
1707 analysis stops counting when the number of fields is 3. This is
1708 because the RiscV ABI only has special cases for 1 or 2 fields,
1709 anything else we just don't care about. */
1710 int number_of_fields () const
1711 { return m_number_of_fields; }
1712
1713 /* Return the type for scalar field INDEX within the analysed type. Will
1714 return nullptr if there is no field at that index. Only INDEX values
1715 0 and 1 can be requested as the RiscV ABI only has special cases for
1716 structures with 1 or 2 fields. */
1717 struct type *field_type (int index) const
1718 {
1719 gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0])));
1720 return m_types[index];
1721 }
1722
1723private:
1724 /* The number of scalar fields found within the structure after recursing
1725 into nested structures. */
1726 int m_number_of_fields;
1727
1728 /* The types of the first two scalar fields found within the structure
1729 after recursing into nested structures. */
1730 struct type *m_types[2];
1731};
1732
1733/* Analyse TYPE descending into nested structures, count the number of
1734 scalar fields and record the types of the first two fields found. */
1735
1736void
1737riscv_struct_info::analyse (struct type *type)
1738{
1739 unsigned int count = TYPE_NFIELDS (type);
1740 unsigned int i;
1741
1742 for (i = 0; i < count; ++i)
1743 {
1744 if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS)
1745 continue;
1746
1747 struct type *field_type = TYPE_FIELD_TYPE (type, i);
1748 field_type = check_typedef (field_type);
1749
1750 switch (TYPE_CODE (field_type))
1751 {
1752 case TYPE_CODE_STRUCT:
1753 analyse (field_type);
1754 break;
1755
1756 default:
1757 /* RiscV only flattens out structures. Anything else does not
1758 need to be flattened, we just record the type, and when we
1759 look at the analysis results we'll realise this is not a
1760 structure we can special case, and pass the structure in
1761 memory. */
1762 if (m_number_of_fields < 2)
1763 m_types[m_number_of_fields] = field_type;
1764 m_number_of_fields++;
1765 break;
1766 }
1767
1768 /* RiscV only has special handling for structures with 1 or 2 scalar
1769 fields, any more than that and the structure is just passed in
1770 memory. We can safely drop out early when we find 3 or more
1771 fields then. */
1772
1773 if (m_number_of_fields > 2)
1774 return;
1775 }
1776}
1777
1778/* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1779 is a structure. Small structures on RiscV have some special case
1780 handling in order that the structure might be passed in register.
1781 Larger structures are passed in memory. After assigning location
1782 information to AINFO, CINFO will have been updated. */
1783
1784static void
1785riscv_call_arg_struct (struct riscv_arg_info *ainfo,
1786 struct riscv_call_info *cinfo)
1787{
1788 if (riscv_arg_regs_available (&cinfo->float_regs) >= 1)
1789 {
1790 struct riscv_struct_info sinfo;
1791
1792 sinfo.analyse (ainfo->type);
1793 if (sinfo.number_of_fields () == 1
1794 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_COMPLEX)
1795 {
1796 gdb_assert (TYPE_LENGTH (ainfo->type)
1797 == TYPE_LENGTH (sinfo.field_type (0)));
1798 return riscv_call_arg_complex_float (ainfo, cinfo);
1799 }
1800
1801 if (sinfo.number_of_fields () == 1
1802 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT)
1803 {
1804 gdb_assert (TYPE_LENGTH (ainfo->type)
1805 == TYPE_LENGTH (sinfo.field_type (0)));
1806 return riscv_call_arg_scalar_float (ainfo, cinfo);
1807 }
1808
1809 if (sinfo.number_of_fields () == 2
1810 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
1811 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
1812 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
1813 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen
1814 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
1815 {
1816 int len0, len1, offset;
1817
1818 gdb_assert (TYPE_LENGTH (ainfo->type) <= (2 * cinfo->flen));
1819
1820 len0 = TYPE_LENGTH (sinfo.field_type (0));
1821 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1822 &cinfo->float_regs, len0, 0))
1823 error (_("failed during argument setup"));
1824
1825 len1 = TYPE_LENGTH (sinfo.field_type (1));
1826 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
1827 gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type)
1828 - TYPE_LENGTH (sinfo.field_type (0))));
1829
1830 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1831 &cinfo->float_regs,
1832 len1, offset))
1833 error (_("failed during argument setup"));
1834 return;
1835 }
1836
1837 if (sinfo.number_of_fields () == 2
1838 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
1839 && (TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
1840 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
1841 && is_integral_type (sinfo.field_type (1))
1842 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen))
1843 {
1844 int len0, len1, offset;
1845
1846 gdb_assert (TYPE_LENGTH (ainfo->type)
1847 <= (cinfo->flen + cinfo->xlen));
1848
1849 len0 = TYPE_LENGTH (sinfo.field_type (0));
1850 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1851 &cinfo->float_regs, len0, 0))
1852 error (_("failed during argument setup"));
1853
1854 len1 = TYPE_LENGTH (sinfo.field_type (1));
1855 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
1856 gdb_assert (len1 <= cinfo->xlen);
1857 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1858 &cinfo->int_regs, len1, offset))
1859 error (_("failed during argument setup"));
1860 return;
1861 }
1862
1863 if (sinfo.number_of_fields () == 2
1864 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
1865 && (is_integral_type (sinfo.field_type (0))
1866 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen
1867 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
1868 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen))
1869 {
1870 int len0, len1, offset;
1871
1872 gdb_assert (TYPE_LENGTH (ainfo->type)
1873 <= (cinfo->flen + cinfo->xlen));
1874
1875 len0 = TYPE_LENGTH (sinfo.field_type (0));
1876 len1 = TYPE_LENGTH (sinfo.field_type (1));
1877 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
1878
1879 gdb_assert (len0 <= cinfo->xlen);
1880 gdb_assert (len1 <= cinfo->flen);
1881
1882 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1883 &cinfo->int_regs, len0, 0))
1884 error (_("failed during argument setup"));
1885
1886 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1887 &cinfo->float_regs,
1888 len1, offset))
1889 error (_("failed during argument setup"));
1890
1891 return;
1892 }
1893 }
1894
1895 /* Non of the structure flattening cases apply, so we just pass using
1896 the integer ABI. */
1897 ainfo->length = align_up (ainfo->length, cinfo->xlen);
1898 riscv_call_arg_scalar_int (ainfo, cinfo);
1899}
1900
1901/* Assign a location to call (or return) argument AINFO, the location is
1902 selected from CINFO which holds information about what call argument
1903 locations are available for use next. The TYPE is the type of the
1904 argument being passed, this information is recorded into AINFO (along
1905 with some additional information derived from the type).
1906
1907 After assigning a location to AINFO, CINFO will have been updated. */
1908
1909static void
1910riscv_arg_location (struct gdbarch *gdbarch,
1911 struct riscv_arg_info *ainfo,
1912 struct riscv_call_info *cinfo,
1913 struct type *type)
1914{
1915 ainfo->type = type;
1916 ainfo->length = TYPE_LENGTH (ainfo->type);
1917 ainfo->align = riscv_type_alignment (ainfo->type);
1918 ainfo->contents = nullptr;
1919
1920 switch (TYPE_CODE (ainfo->type))
1921 {
1922 case TYPE_CODE_INT:
1923 case TYPE_CODE_BOOL:
1924 case TYPE_CODE_CHAR:
1925 case TYPE_CODE_RANGE:
1926 case TYPE_CODE_ENUM:
1927 case TYPE_CODE_PTR:
1928 if (ainfo->length <= cinfo->xlen)
1929 {
1930 ainfo->type = builtin_type (gdbarch)->builtin_long;
1931 ainfo->length = cinfo->xlen;
1932 }
1933 else if (ainfo->length <= (2 * cinfo->xlen))
1934 {
1935 ainfo->type = builtin_type (gdbarch)->builtin_long_long;
1936 ainfo->length = 2 * cinfo->xlen;
1937 }
1938
1939 /* Recalculate the alignment requirement. */
1940 ainfo->align = riscv_type_alignment (ainfo->type);
1941 riscv_call_arg_scalar_int (ainfo, cinfo);
1942 break;
1943
1944 case TYPE_CODE_FLT:
1945 riscv_call_arg_scalar_float (ainfo, cinfo);
1946 break;
1947
1948 case TYPE_CODE_COMPLEX:
1949 riscv_call_arg_complex_float (ainfo, cinfo);
1950 break;
1951
1952 case TYPE_CODE_STRUCT:
1953 riscv_call_arg_struct (ainfo, cinfo);
1954 break;
1955
1956 default:
1957 riscv_call_arg_scalar_int (ainfo, cinfo);
1958 break;
1959 }
1960}
1961
1962static void
1963riscv_print_arg_location (FILE *stream, struct gdbarch *gdbarch,
1964 struct riscv_arg_info *info,
1965 CORE_ADDR sp_refs, CORE_ADDR sp_args)
1966{
1967 const char* type_name = TYPE_NAME (info->type);
1968 if (type_name == nullptr)
1969 type_name = "???";
1970
1971 fprintf (stream, "type: '%s', length: 0x%x, alignment: 0x%x",
1972 type_name, info->length, info->align);
1973 switch (info->argloc[0].loc_type)
1974 {
1975 case riscv_arg_info::location::in_reg:
1976 fprintf (stream, ", register %s",
1977 gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno));
1978 if (info->argloc[0].c_length < info->length)
1979 {
1980 switch (info->argloc[1].loc_type)
1981 {
1982 case riscv_arg_info::location::in_reg:
1983 fprintf (stream, ", register %s",
1984 gdbarch_register_name (gdbarch,
1985 info->argloc[1].loc_data.regno));
1986 break;
1987
1988 case riscv_arg_info::location::on_stack:
1989 fprintf (stream, ", on stack at offset 0x%x",
1990 info->argloc[1].loc_data.offset);
1991 break;
1992
1993 case riscv_arg_info::location::by_ref:
1994 default:
1995 /* The second location should never be a reference, any
1996 argument being passed by reference just places its address
1997 in the first location and is done. */
1998 error (_("invalid argument location"));
1999 break;
2000 }
2001
2002 if (info->argloc[1].c_offset > info->argloc[0].c_length)
2003 fprintf (stream, " (offset 0x%x)", info->argloc[1].c_offset);
2004 }
2005 break;
2006
2007 case riscv_arg_info::location::on_stack:
2008 fprintf (stream, ", on stack at offset 0x%x",
2009 info->argloc[0].loc_data.offset);
2010 break;
2011
2012 case riscv_arg_info::location::by_ref:
2013 fprintf (stream, ", by reference, data at offset 0x%x (0x%lx)",
2014 info->argloc[0].loc_data.offset,
2015 (sp_refs + info->argloc[0].loc_data.offset));
2016 if (info->argloc[1].loc_type
2017 == riscv_arg_info::location::in_reg)
2018 fprintf (stream, ", address in register %s",
2019 gdbarch_register_name (gdbarch,
2020 info->argloc[1].loc_data.regno));
2021 else
2022 {
2023 gdb_assert (info->argloc[1].loc_type
2024 == riscv_arg_info::location::on_stack);
2025 fprintf (stream, ", address on stack at offset 0x%x (0x%lx)",
2026 info->argloc[1].loc_data.offset,
2027 (sp_args + info->argloc[1].loc_data.offset));
2028 }
2029 break;
2030
2031 default:
2032 error ("unknown argument location type");
2033 }
2034}
2035
2036/* Implement the push dummy call gdbarch callback. */
2037
2038static CORE_ADDR
2039riscv_push_dummy_call (struct gdbarch *gdbarch,
2040 struct value *function,
2041 struct regcache *regcache,
2042 CORE_ADDR bp_addr,
2043 int nargs,
2044 struct value **args,
2045 CORE_ADDR sp,
2046 int struct_return,
2047 CORE_ADDR struct_addr)
2048{
2049 int i;
2050 CORE_ADDR sp_args, sp_refs;
2051 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2052 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2053
2054 struct riscv_arg_info *arg_info =
2055 (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info));
2056 struct riscv_arg_info *info;
2057
2058 struct riscv_call_info call_info (gdbarch);
2059
2060 CORE_ADDR osp = sp;
2061
2062 /* We'll use register $a0 if we're returning a struct. */
2063 if (struct_return)
2064 ++call_info.int_regs.next_regnum;
2065
2066 for (i = 0, info = &arg_info[0];
2067 i < nargs;
2068 ++i, ++info)
2069 {
2070 struct value *arg_value;
2071 struct type *arg_type;
2072
2073 arg_value = args[i];
2074 arg_type = check_typedef (value_type (arg_value));
2075
2076 riscv_arg_location (gdbarch, info, &call_info, arg_type);
2077
2078 if (info->type != arg_type)
2079 arg_value = value_cast (info->type, arg_value);
2080 info->contents = value_contents (arg_value);
2081 }
2082
2083 /* Adjust the stack pointer and align it. */
2084 sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT);
2085 sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT);
2086
2087 if (riscv_debug_infcall > 0)
2088 {
2089 fprintf_unfiltered (gdb_stdlog, "dummy call args:\n");
2090 fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n",
2091 (riscv_has_fp_abi (gdbarch) ? "is" : "is not"));
2092 fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n",
2093 call_info.xlen, call_info.flen);
2094 if (struct_return)
2095 fprintf_unfiltered (gdb_stdlog,
2096 "[*] struct return pointer in register $A0\n");
2097 for (i = 0; i < nargs; ++i)
2098 {
2099 struct riscv_arg_info *info = &arg_info [i];
2100
2101 fprintf_unfiltered (gdb_stdlog, "[%2d] ", i);
2102 riscv_print_arg_location (stderr, gdbarch, info, sp_refs, sp_args);
2103 fprintf_unfiltered (gdb_stdlog, "\n");
2104 }
2105 if (call_info.memory.arg_offset > 0
2106 || call_info.memory.ref_offset > 0)
2107 {
2108 fprintf_unfiltered (gdb_stdlog, " Original sp: 0x%lx\n",
2109 osp);
2110 fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n",
2111 call_info.memory.arg_offset);
2112 fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n",
2113 call_info.memory.ref_offset);
2114 fprintf_unfiltered (gdb_stdlog, " Stack allocated: 0x%lx\n",
2115 (osp - sp));
2116 }
2117 }
2118
2119 /* Now load the argument into registers, or onto the stack. */
2120
2121 if (struct_return)
2122 {
2123 gdb_byte buf[sizeof (LONGEST)];
2124
2125 store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr);
2126 regcache_cooked_write (regcache, RISCV_A0_REGNUM, buf);
2127 }
2128
2129 for (i = 0; i < nargs; ++i)
2130 {
2131 CORE_ADDR dst;
2132 int second_arg_length = 0;
2133 const gdb_byte *second_arg_data;
2134 struct riscv_arg_info *info = &arg_info [i];
2135
2136 gdb_assert (info->length > 0);
2137
2138 switch (info->argloc[0].loc_type)
2139 {
2140 case riscv_arg_info::location::in_reg:
2141 {
2142 gdb_byte tmp [sizeof (ULONGEST)];
2143
2144 gdb_assert (info->argloc[0].c_length <= info->length);
2145 memset (tmp, 0, sizeof (tmp));
2146 memcpy (tmp, info->contents, info->argloc[0].c_length);
2147 regcache_cooked_write (regcache,
2148 info->argloc[0].loc_data.regno,
2149 tmp);
2150 second_arg_length =
2151 ((info->argloc[0].c_length < info->length)
2152 ? info->argloc[1].c_length : 0);
2153 second_arg_data = info->contents + info->argloc[1].c_offset;
2154 }
2155 break;
2156
2157 case riscv_arg_info::location::on_stack:
2158 dst = sp_args + info->argloc[0].loc_data.offset;
2159 write_memory (dst, info->contents, info->length);
2160 second_arg_length = 0;
2161 break;
2162
2163 case riscv_arg_info::location::by_ref:
2164 dst = sp_refs + info->argloc[0].loc_data.offset;
2165 write_memory (dst, info->contents, info->length);
2166
2167 second_arg_length = call_info.xlen;
2168 second_arg_data = (gdb_byte *) &dst;
2169 break;
2170
2171 default:
2172 error ("unknown argument location type");
2173 }
2174
2175 if (second_arg_length > 0)
2176 {
2177 switch (info->argloc[1].loc_type)
2178 {
2179 case riscv_arg_info::location::in_reg:
2180 {
2181 gdb_byte tmp [sizeof (ULONGEST)];
2182
2183 gdb_assert (second_arg_length <= call_info.xlen);
2184 memset (tmp, 0, sizeof (tmp));
2185 memcpy (tmp, second_arg_data, second_arg_length);
2186 regcache_cooked_write (regcache,
2187 info->argloc[1].loc_data.regno,
2188 tmp);
2189 }
2190 break;
2191
2192 case riscv_arg_info::location::on_stack:
2193 {
2194 CORE_ADDR arg_addr;
2195
2196 arg_addr = sp_args + info->argloc[1].loc_data.offset;
2197 write_memory (arg_addr, second_arg_data, second_arg_length);
2198 break;
2199 }
2200
2201 case riscv_arg_info::location::by_ref:
2202 default:
2203 /* The second location should never be a reference, any
2204 argument being passed by reference just places its address
2205 in the first location and is done. */
2206 error (_("invalid argument location"));
2207 break;
2208 }
2209 }
2210 }
2211
2212 /* Set the dummy return value to bp_addr.
2213 A dummy breakpoint will be setup to execute the call. */
2214
2215 if (riscv_debug_infcall > 0)
2216 fprintf_unfiltered (gdb_stdlog, ": writing $ra = 0x%lx\n", bp_addr);
2217 regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr);
2218
2219 /* Finally, update the stack pointer. */
2220
2221 if (riscv_debug_infcall > 0)
2222 fprintf_unfiltered (gdb_stdlog, ": writing $sp = 0x%lx\n", sp);
2223 regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp);
2224
2225 return sp;
2226}
2227
2228/* Implement the return_value gdbarch method. */
2229
2230static enum return_value_convention
2231riscv_return_value (struct gdbarch *gdbarch,
2232 struct value *function,
2233 struct type *type,
2234 struct regcache *regcache,
2235 gdb_byte *readbuf,
2236 const gdb_byte *writebuf)
2237{
2238 enum type_code rv_type = TYPE_CODE (type);
2239 unsigned int rv_size = TYPE_LENGTH (type);
2240 int fp, regnum, flen;
2241 ULONGEST tmp;
2242 struct riscv_call_info call_info (gdbarch);
2243 struct riscv_arg_info info;
2244 struct type *arg_type;
2245
2246 arg_type = check_typedef (type);
2247 riscv_arg_location (gdbarch, &info, &call_info, arg_type);
2248
2249 if (riscv_debug_infcall > 0)
2250 {
2251 fprintf_unfiltered (gdb_stdlog, "riscv return value:\n");
2252 fprintf_unfiltered (gdb_stdlog, "[R] ");
2253 riscv_print_arg_location (stderr, gdbarch, &info, 0, 0);
2254 fprintf_unfiltered (gdb_stdlog, "\n");
2255 }
2256
2257 if (readbuf != nullptr || writebuf != nullptr)
2258 {
2259 int regnum;
2260
2261 switch (info.argloc[0].loc_type)
2262 {
2263 /* Return value in register(s). */
2264 case riscv_arg_info::location::in_reg:
2265 {
2266 regnum = info.argloc[0].loc_data.regno;
2267
2268 if (readbuf)
2269 regcache_cooked_read (regcache, regnum, readbuf);
2270
2271 if (writebuf)
2272 regcache_cooked_write (regcache, regnum, writebuf);
2273
2274 /* A return value in register can have a second part in a
2275 second register. */
2276 if (info.argloc[0].c_length < info.length)
2277 {
2278 switch (info.argloc[1].loc_type)
2279 {
2280 case riscv_arg_info::location::in_reg:
2281 regnum = info.argloc[1].loc_data.regno;
2282
2283 if (readbuf)
2284 {
2285 readbuf += info.argloc[1].c_offset;
2286 regcache_cooked_read (regcache, regnum, readbuf);
2287 }
2288
2289 if (writebuf)
2290 {
2291 writebuf += info.argloc[1].c_offset;
2292 regcache_cooked_write (regcache, regnum, writebuf);
2293 }
2294 break;
2295
2296 case riscv_arg_info::location::by_ref:
2297 case riscv_arg_info::location::on_stack:
2298 default:
2299 error (_("invalid argument location"));
2300 break;
2301 }
2302 }
2303 }
2304 break;
2305
2306 /* Return value by reference will have its address in A0. */
2307 case riscv_arg_info::location::by_ref:
2308 {
2309 CORE_ADDR addr;
2310
2311 regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM,
2312 &addr);
2313 if (readbuf != nullptr)
2314 read_memory (addr, readbuf, info.length);
2315 if (writebuf != nullptr)
2316 write_memory (addr, writebuf, info.length);
2317 }
2318 break;
2319
2320 case riscv_arg_info::location::on_stack:
2321 default:
2322 error (_("invalid argument location"));
2323 break;
2324 }
2325 }
2326
2327 switch (info.argloc[0].loc_type)
2328 {
2329 case riscv_arg_info::location::in_reg:
2330 return RETURN_VALUE_REGISTER_CONVENTION;
2331 case riscv_arg_info::location::by_ref:
2332 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2333 case riscv_arg_info::location::on_stack:
2334 default:
2335 error (_("invalid argument location"));
2336 }
2337}
2338
2339/* Implement the frame_align gdbarch method. */
2340
2341static CORE_ADDR
2342riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2343{
2344 return align_down (addr, 16);
2345}
2346
2347/* Implement the unwind_pc gdbarch method. */
2348
2349static CORE_ADDR
2350riscv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2351{
2352 return frame_unwind_register_unsigned (next_frame, RISCV_PC_REGNUM);
2353}
2354
2355/* Implement the unwind_sp gdbarch method. */
2356
2357static CORE_ADDR
2358riscv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2359{
2360 return frame_unwind_register_unsigned (next_frame, RISCV_SP_REGNUM);
2361}
2362
2363/* Implement the dummy_id gdbarch method. */
2364
2365static struct frame_id
2366riscv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2367{
2368 return frame_id_build (get_frame_register_signed (this_frame, RISCV_SP_REGNUM),
2369 get_frame_pc (this_frame));
2370}
2371
2372/* Generate, or return the cached frame cache for the RiscV frame
2373 unwinder. */
2374
2375static struct trad_frame_cache *
2376riscv_frame_cache (struct frame_info *this_frame, void **this_cache)
2377{
2378 CORE_ADDR pc;
2379 CORE_ADDR start_addr;
2380 CORE_ADDR stack_addr;
2381 struct trad_frame_cache *this_trad_cache;
2382 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2383
2384 if ((*this_cache) != NULL)
2385 return (struct trad_frame_cache *) *this_cache;
2386 this_trad_cache = trad_frame_cache_zalloc (this_frame);
2387 (*this_cache) = this_trad_cache;
2388
2389 trad_frame_set_reg_realreg (this_trad_cache, gdbarch_pc_regnum (gdbarch),
2390 RISCV_RA_REGNUM);
2391
2392 pc = get_frame_pc (this_frame);
2393 find_pc_partial_function (pc, NULL, &start_addr, NULL);
2394 stack_addr = get_frame_register_signed (this_frame, RISCV_SP_REGNUM);
2395 trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr));
2396
2397 trad_frame_set_this_base (this_trad_cache, stack_addr);
2398
2399 return this_trad_cache;
2400}
2401
2402/* Implement the this_id callback for RiscV frame unwinder. */
2403
2404static void
2405riscv_frame_this_id (struct frame_info *this_frame,
2406 void **prologue_cache,
2407 struct frame_id *this_id)
2408{
2409 struct trad_frame_cache *info;
2410
2411 info = riscv_frame_cache (this_frame, prologue_cache);
2412 trad_frame_get_id (info, this_id);
2413}
2414
2415/* Implement the prev_register callback for RiscV frame unwinder. */
2416
2417static struct value *
2418riscv_frame_prev_register (struct frame_info *this_frame,
2419 void **prologue_cache,
2420 int regnum)
2421{
2422 struct trad_frame_cache *info;
2423
2424 info = riscv_frame_cache (this_frame, prologue_cache);
2425 return trad_frame_get_register (info, this_frame, regnum);
2426}
2427
2428/* Structure defining the RiscV normal frame unwind functions. Since we
2429 are the fallback unwinder (DWARF unwinder is used first), we use the
2430 default frame sniffer, which always accepts the frame. */
2431
2432static const struct frame_unwind riscv_frame_unwind =
2433{
2434 /*.type =*/ NORMAL_FRAME,
2435 /*.stop_reason =*/ default_frame_unwind_stop_reason,
2436 /*.this_id =*/ riscv_frame_this_id,
2437 /*.prev_register =*/ riscv_frame_prev_register,
2438 /*.unwind_data =*/ NULL,
2439 /*.sniffer =*/ default_frame_sniffer,
2440 /*.dealloc_cache =*/ NULL,
2441 /*.prev_arch =*/ NULL,
2442};
2443
2444/* Initialize the current architecture based on INFO. If possible,
2445 re-use an architecture from ARCHES, which is a list of
2446 architectures already created during this debugging session.
2447
2448 Called e.g. at program startup, when reading a core file, and when
2449 reading a binary file. */
2450
2451static struct gdbarch *
2452riscv_gdbarch_init (struct gdbarch_info info,
2453 struct gdbarch_list *arches)
2454{
2455 struct gdbarch *gdbarch;
2456 struct gdbarch_tdep *tdep;
2457 struct gdbarch_tdep tmp_tdep;
2458 bool has_compressed_isa = false;
2459 int i;
2460
2461 /* Ideally, we'd like to get as much information from the target for
2462 things like register size, and whether the target has floating point
2463 hardware. However, there are some things that the target can't tell
2464 us, like, what ABI is being used.
2465
2466 So, for now, we take as much information as possible from the ELF,
2467 including things like register size, and FP hardware support, along
2468 with information about the ABI.
2469
2470 Information about this target is built up in TMP_TDEP, and then we
2471 look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no
2472 match is found we'll create a new gdbarch and copy TMP_TDEP over. */
2473 memset (&tmp_tdep, 0, sizeof (tmp_tdep));
2474
2475 if (info.abfd != NULL
2476 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2477 {
2478 unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS];
2479 int e_flags = elf_elfheader (info.abfd)->e_flags;
2480
2481 if (eclass == ELFCLASS32)
2482 tmp_tdep.abi.fields.base_len = 1;
2483 else if (eclass == ELFCLASS64)
2484 tmp_tdep.abi.fields.base_len = 2;
2485 else
2486 internal_error (__FILE__, __LINE__,
2487 _("unknown ELF header class %d"), eclass);
2488
2489 if (e_flags & EF_RISCV_RVC)
2490 {
2491 has_compressed_isa = true;
2492 tmp_tdep.core_features |= (1 << ('C' - 'A'));
2493 }
2494
2495 if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE)
2496 {
2497 tmp_tdep.abi.fields.float_abi = 2;
2498 tmp_tdep.core_features |= (1 << ('D' - 'A'));
2499 tmp_tdep.core_features |= (1 << ('F' - 'A'));
2500 }
2501 else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE)
2502 {
2503 tmp_tdep.abi.fields.float_abi = 1;
2504 tmp_tdep.core_features |= (1 << ('F' - 'A'));
2505 }
2506 }
2507 else
2508 {
2509 const struct bfd_arch_info *binfo = info.bfd_arch_info;
2510
2511 if (binfo->bits_per_word == 32)
2512 tmp_tdep.abi.fields.base_len = 1;
2513 else if (binfo->bits_per_word == 64)
2514 tmp_tdep.abi.fields.base_len = 2;
2515 else
2516 internal_error (__FILE__, __LINE__, _("unknown bits_per_word %d"),
2517 binfo->bits_per_word);
2518 }
2519
2520 /* Find a candidate among the list of pre-declared architectures. */
2521 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2522 arches != NULL;
2523 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2524 if (gdbarch_tdep (arches->gdbarch)->abi.value == tmp_tdep.abi.value)
2525 return arches->gdbarch;
2526
2527 /* None found, so create a new architecture from the information provided. */
2528 tdep = (struct gdbarch_tdep *) xmalloc (sizeof *tdep);
2529 gdbarch = gdbarch_alloc (&info, tdep);
2530 memcpy (tdep, &tmp_tdep, sizeof (tmp_tdep));
2531
2532 /* Target data types. */
2533 set_gdbarch_short_bit (gdbarch, 16);
2534 set_gdbarch_int_bit (gdbarch, 32);
2535 set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
2536 set_gdbarch_long_long_bit (gdbarch, 64);
2537 set_gdbarch_float_bit (gdbarch, 32);
2538 set_gdbarch_double_bit (gdbarch, 64);
2539 set_gdbarch_long_double_bit (gdbarch, 128);
2540 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
2541 set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
2542 set_gdbarch_char_signed (gdbarch, 0);
2543
2544 /* Information about the target architecture. */
2545 set_gdbarch_return_value (gdbarch, riscv_return_value);
2546 set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc);
2547 set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind);
2548
2549 /* Register architecture. */
2550 set_gdbarch_pseudo_register_read (gdbarch, riscv_pseudo_register_read);
2551 set_gdbarch_pseudo_register_write (gdbarch, riscv_pseudo_register_write);
2552 set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1);
2553 set_gdbarch_num_pseudo_regs (gdbarch, RISCV_LAST_REGNUM + 1);
2554 set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM);
2555 set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM);
2556 set_gdbarch_ps_regnum (gdbarch, RISCV_FP_REGNUM);
2557 set_gdbarch_deprecated_fp_regnum (gdbarch, RISCV_FP_REGNUM);
2558
2559 /* Functions to supply register information. */
2560 set_gdbarch_register_name (gdbarch, riscv_register_name);
2561 set_gdbarch_register_type (gdbarch, riscv_register_type);
2562 set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info);
2563 set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p);
2564
2565 /* Functions to analyze frames. */
2566 set_gdbarch_decr_pc_after_break (gdbarch, (has_compressed_isa ? 2 : 4));
2567 set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue);
2568 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2569 set_gdbarch_frame_align (gdbarch, riscv_frame_align);
2570
2571 /* Functions to access frame data. */
2572 set_gdbarch_unwind_pc (gdbarch, riscv_unwind_pc);
2573 set_gdbarch_unwind_sp (gdbarch, riscv_unwind_sp);
2574
2575 /* Functions handling dummy frames. */
2576 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2577 set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code);
2578 set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call);
2579 set_gdbarch_dummy_id (gdbarch, riscv_dummy_id);
2580
2581 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
2582 unwinder. */
2583 dwarf2_append_unwinders (gdbarch);
2584 frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind);
2585
2586 /* Check any target description for validity. */
2587 if (tdesc_has_registers (info.target_desc))
2588 {
2589 const struct tdesc_feature *feature;
2590 struct tdesc_arch_data *tdesc_data;
2591 int valid_p;
2592
2593 feature = tdesc_find_feature (info.target_desc, "org.gnu.gdb.riscv.cpu");
2594 if (feature == NULL)
2595 goto no_tdata;
2596
2597 tdesc_data = tdesc_data_alloc ();
2598
2599 valid_p = 1;
2600 for (i = RISCV_ZERO_REGNUM; i <= RISCV_LAST_FP_REGNUM; ++i)
2601 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
2602 riscv_gdb_reg_names[i]);
2603 for (i = RISCV_FIRST_CSR_REGNUM; i <= RISCV_LAST_CSR_REGNUM; ++i)
2604 {
2605 char buf[20];
2606
2607 sprintf (buf, "csr%d", i - RISCV_FIRST_CSR_REGNUM);
2608 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, buf);
2609 }
2610
2611 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "priv");
2612
2613 if (!valid_p)
2614 tdesc_data_cleanup (tdesc_data);
2615 else
2616 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
2617 }
2618 no_tdata:
2619
2620 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
2621 user_reg_add (gdbarch, riscv_register_aliases[i].name,
2622 value_of_riscv_user_reg, &riscv_register_aliases[i].regnum);
2623
2624 return gdbarch;
2625}
2626
2627
2628/* Allocate new riscv_inferior_data object. */
2629
2630static struct riscv_inferior_data *
2631riscv_new_inferior_data (void)
2632{
2633 struct riscv_inferior_data *inf_data
2634 = new (struct riscv_inferior_data);
2635 inf_data->misa_read = false;
2636 return inf_data;
2637}
2638
2639/* Free inferior data. */
2640
2641static void
2642riscv_inferior_data_cleanup (struct inferior *inf, void *data)
2643{
2644 struct riscv_inferior_data *inf_data =
2645 static_cast <struct riscv_inferior_data *> (data);
2646 delete (inf_data);
2647}
2648
2649/* Return riscv_inferior_data for the given INFERIOR. If not yet created,
2650 construct it. */
2651
2652struct riscv_inferior_data *
2653riscv_inferior_data (struct inferior *const inf)
2654{
2655 struct riscv_inferior_data *inf_data;
2656
2657 gdb_assert (inf != NULL);
2658
2659 inf_data
2660 = (struct riscv_inferior_data *) inferior_data (inf, riscv_inferior_data_reg);
2661 if (inf_data == NULL)
2662 {
2663 inf_data = riscv_new_inferior_data ();
2664 set_inferior_data (inf, riscv_inferior_data_reg, inf_data);
2665 }
2666
2667 return inf_data;
2668}
2669
2670/* Free the inferior data when an inferior exits. */
2671
2672static void
2673riscv_invalidate_inferior_data (struct inferior *inf)
2674{
2675 struct riscv_inferior_data *inf_data;
2676
2677 gdb_assert (inf != NULL);
2678
2679 /* Don't call RISCV_INFERIOR_DATA as we don't want to create the data if
2680 we've not already created it by this point. */
2681 inf_data
2682 = (struct riscv_inferior_data *) inferior_data (inf, riscv_inferior_data_reg);
2683 if (inf_data != NULL)
2684 {
2685 delete (inf_data);
2686 set_inferior_data (inf, riscv_inferior_data_reg, NULL);
2687 }
2688}
2689
2690void
2691_initialize_riscv_tdep (void)
2692{
2693 gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL);
2694
2695 /* Register per-inferior data. */
2696 riscv_inferior_data_reg
2697 = register_inferior_data_with_cleanup (NULL, riscv_inferior_data_cleanup);
2698
2699 /* Observers used to invalidate the inferior data when needed. */
2700 observer_attach_inferior_exit (riscv_invalidate_inferior_data);
2701 observer_attach_inferior_appeared (riscv_invalidate_inferior_data);
2702
2703 /* Add root prefix command for all "set debug riscv" and "show debug
2704 riscv" commands. */
2705 add_prefix_cmd ("riscv", no_class, set_debug_riscv_command,
2706 _("RISC-V specific debug commands."),
2707 &setdebugriscvcmdlist, "set debug riscv ", 0,
2708 &setdebuglist);
2709
2710 add_prefix_cmd ("riscv", no_class, show_debug_riscv_command,
2711 _("RISC-V specific debug commands."),
2712 &showdebugriscvcmdlist, "show debug riscv ", 0,
2713 &showdebuglist);
2714
2715 add_setshow_zuinteger_cmd ("infcall", class_maintenance,
2716 &riscv_debug_infcall, _("\
2717Set riscv inferior call debugging."), _("\
2718Show riscv inferior call debugging."), _("\
2719When non-zero, print debugging information for the riscv specific parts\n\
2720of the inferior call mechanism."),
2721 NULL,
2722 show_riscv_debug_variable,
2723 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
2724
2725 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
2726 add_prefix_cmd ("riscv", no_class, set_riscv_command,
2727 _("RISC-V specific commands."),
2728 &setriscvcmdlist, "set riscv ", 0, &setlist);
2729
2730 add_prefix_cmd ("riscv", no_class, show_riscv_command,
2731 _("RISC-V specific commands."),
2732 &showriscvcmdlist, "show riscv ", 0, &showlist);
2733
2734
2735 use_compressed_breakpoints = AUTO_BOOLEAN_AUTO;
2736 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class,
2737 &use_compressed_breakpoints,
2738 _("\
2739Set debugger's use of compressed breakpoints."), _(" \
2740Show debugger's use of compressed breakpoints."), _("\
2741Debugging compressed code requires compressed breakpoints to be used. If\n \
2742left to 'auto' then gdb will use them if $misa indicates the C extension\n \
2743is supported. If that doesn't give the correct behavior, then this option\n\
2744can be used."),
2745 NULL,
2746 show_use_compressed_breakpoints,
2747 &setriscvcmdlist,
2748 &showriscvcmdlist);
2749}
GDB Binutils - Deliverables
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