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dbbb1059 AB |
1 | /* Target-dependent code for the RISC-V architecture, for GDB. |
2 | ||
3 | Copyright (C) 2018 Free Software Foundation, Inc. | |
4 | ||
dbbb1059 AB |
5 | This file is part of GDB. |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "inferior.h" | |
23 | #include "symtab.h" | |
24 | #include "value.h" | |
25 | #include "gdbcmd.h" | |
26 | #include "language.h" | |
27 | #include "gdbcore.h" | |
28 | #include "symfile.h" | |
29 | #include "objfiles.h" | |
30 | #include "gdbtypes.h" | |
31 | #include "target.h" | |
32 | #include "arch-utils.h" | |
33 | #include "regcache.h" | |
34 | #include "osabi.h" | |
35 | #include "riscv-tdep.h" | |
36 | #include "block.h" | |
37 | #include "reggroups.h" | |
38 | #include "opcode/riscv.h" | |
39 | #include "elf/riscv.h" | |
40 | #include "elf-bfd.h" | |
41 | #include "symcat.h" | |
42 | #include "dis-asm.h" | |
43 | #include "frame-unwind.h" | |
44 | #include "frame-base.h" | |
45 | #include "trad-frame.h" | |
46 | #include "infcall.h" | |
47 | #include "floatformat.h" | |
48 | #include "remote.h" | |
49 | #include "target-descriptions.h" | |
50 | #include "dwarf2-frame.h" | |
51 | #include "user-regs.h" | |
52 | #include "valprint.h" | |
53 | #include "common-defs.h" | |
54 | #include "opcode/riscv-opc.h" | |
55 | #include "cli/cli-decode.h" | |
76727919 | 56 | #include "observable.h" |
dbbb1059 AB |
57 | |
58 | /* The stack must be 16-byte aligned. */ | |
59 | #define SP_ALIGNMENT 16 | |
60 | ||
61 | /* Forward declarations. */ | |
62 | static bool riscv_has_feature (struct gdbarch *gdbarch, char feature); | |
dbbb1059 AB |
63 | |
64 | /* Define a series of is_XXX_insn functions to check if the value INSN | |
65 | is an instance of instruction XXX. */ | |
66 | #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \ | |
67 | static inline bool is_ ## INSN_NAME ## _insn (long insn) \ | |
68 | { \ | |
69 | return (insn & INSN_MASK) == INSN_MATCH; \ | |
70 | } | |
71 | #include "opcode/riscv-opc.h" | |
72 | #undef DECLARE_INSN | |
73 | ||
dbbb1059 AB |
74 | /* Architectural name for core registers. */ |
75 | ||
76 | static const char * const riscv_gdb_reg_names[RISCV_LAST_FP_REGNUM + 1] = | |
77 | { | |
78 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", | |
79 | "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", | |
80 | "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", | |
81 | "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", | |
82 | "pc", | |
83 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
84 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
85 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
86 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
87 | }; | |
88 | ||
89 | /* Maps "pretty" register names onto their GDB register number. */ | |
90 | ||
91 | struct register_alias | |
92 | { | |
93 | /* The register alias. Usually more descriptive than the | |
94 | architectural name of the register. */ | |
95 | const char *name; | |
96 | ||
97 | /* The GDB register number. */ | |
98 | int regnum; | |
99 | }; | |
100 | ||
101 | /* Table of register aliases. */ | |
102 | ||
103 | static const struct register_alias riscv_register_aliases[] = | |
104 | { | |
105 | { "zero", 0 }, | |
106 | { "ra", 1 }, | |
107 | { "sp", 2 }, | |
108 | { "gp", 3 }, | |
109 | { "tp", 4 }, | |
110 | { "t0", 5 }, | |
111 | { "t1", 6 }, | |
112 | { "t2", 7 }, | |
dbbb1059 | 113 | { "s0", 8 }, |
41823f29 | 114 | { "fp", 8 }, |
dbbb1059 AB |
115 | { "s1", 9 }, |
116 | { "a0", 10 }, | |
117 | { "a1", 11 }, | |
118 | { "a2", 12 }, | |
119 | { "a3", 13 }, | |
120 | { "a4", 14 }, | |
121 | { "a5", 15 }, | |
122 | { "a6", 16 }, | |
123 | { "a7", 17 }, | |
124 | { "s2", 18 }, | |
125 | { "s3", 19 }, | |
126 | { "s4", 20 }, | |
127 | { "s5", 21 }, | |
128 | { "s6", 22 }, | |
129 | { "s7", 23 }, | |
130 | { "s8", 24 }, | |
131 | { "s9", 25 }, | |
132 | { "s10", 26 }, | |
133 | { "s11", 27 }, | |
134 | { "t3", 28 }, | |
135 | { "t4", 29 }, | |
136 | { "t5", 30 }, | |
137 | { "t6", 31 }, | |
138 | /* pc is 32. */ | |
139 | { "ft0", 33 }, | |
140 | { "ft1", 34 }, | |
141 | { "ft2", 35 }, | |
142 | { "ft3", 36 }, | |
143 | { "ft4", 37 }, | |
144 | { "ft5", 38 }, | |
145 | { "ft6", 39 }, | |
146 | { "ft7", 40 }, | |
147 | { "fs0", 41 }, | |
148 | { "fs1", 42 }, | |
149 | { "fa0", 43 }, | |
150 | { "fa1", 44 }, | |
151 | { "fa2", 45 }, | |
152 | { "fa3", 46 }, | |
153 | { "fa4", 47 }, | |
154 | { "fa5", 48 }, | |
155 | { "fa6", 49 }, | |
156 | { "fa7", 50 }, | |
157 | { "fs2", 51 }, | |
158 | { "fs3", 52 }, | |
159 | { "fs4", 53 }, | |
160 | { "fs5", 54 }, | |
161 | { "fs6", 55 }, | |
162 | { "fs7", 56 }, | |
163 | { "fs8", 57 }, | |
164 | { "fs9", 58 }, | |
165 | { "fs10", 59 }, | |
166 | { "fs11", 60 }, | |
167 | { "ft8", 61 }, | |
168 | { "ft9", 62 }, | |
169 | { "ft10", 63 }, | |
170 | { "ft11", 64 }, | |
171 | #define DECLARE_CSR(name, num) { #name, (num) + 65 }, | |
172 | #include "opcode/riscv-opc.h" | |
173 | #undef DECLARE_CSR | |
174 | }; | |
175 | ||
176 | /* Controls whether we place compressed breakpoints or not. When in auto | |
177 | mode GDB tries to determine if the target supports compressed | |
178 | breakpoints, and uses them if it does. */ | |
179 | ||
180 | static enum auto_boolean use_compressed_breakpoints; | |
181 | ||
182 | /* The show callback for 'show riscv use-compressed-breakpoints'. */ | |
183 | ||
184 | static void | |
185 | show_use_compressed_breakpoints (struct ui_file *file, int from_tty, | |
186 | struct cmd_list_element *c, | |
187 | const char *value) | |
188 | { | |
189 | const char *additional_info; | |
190 | struct gdbarch *gdbarch = target_gdbarch (); | |
191 | ||
192 | if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO) | |
193 | if (riscv_has_feature (gdbarch, 'C')) | |
194 | additional_info = _(" (currently on)"); | |
195 | else | |
196 | additional_info = _(" (currently off)"); | |
197 | else | |
198 | additional_info = ""; | |
199 | ||
200 | fprintf_filtered (file, | |
201 | _("Debugger's use of compressed breakpoints is set " | |
202 | "to %s%s.\n"), value, additional_info); | |
203 | } | |
204 | ||
205 | /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */ | |
206 | ||
207 | static struct cmd_list_element *setriscvcmdlist = NULL; | |
208 | static struct cmd_list_element *showriscvcmdlist = NULL; | |
209 | ||
210 | /* The show callback for the 'show riscv' prefix command. */ | |
211 | ||
212 | static void | |
213 | show_riscv_command (const char *args, int from_tty) | |
214 | { | |
215 | help_list (showriscvcmdlist, "show riscv ", all_commands, gdb_stdout); | |
216 | } | |
217 | ||
218 | /* The set callback for the 'set riscv' prefix command. */ | |
219 | ||
220 | static void | |
221 | set_riscv_command (const char *args, int from_tty) | |
222 | { | |
223 | printf_unfiltered | |
224 | (_("\"set riscv\" must be followed by an appropriate subcommand.\n")); | |
225 | help_list (setriscvcmdlist, "set riscv ", all_commands, gdb_stdout); | |
226 | } | |
227 | ||
228 | /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */ | |
229 | ||
230 | static struct cmd_list_element *setdebugriscvcmdlist = NULL; | |
231 | static struct cmd_list_element *showdebugriscvcmdlist = NULL; | |
232 | ||
233 | /* The show callback for the 'show debug riscv' prefix command. */ | |
234 | ||
235 | static void | |
236 | show_debug_riscv_command (const char *args, int from_tty) | |
237 | { | |
238 | help_list (showdebugriscvcmdlist, "show debug riscv ", all_commands, gdb_stdout); | |
239 | } | |
240 | ||
241 | /* The set callback for the 'set debug riscv' prefix command. */ | |
242 | ||
243 | static void | |
244 | set_debug_riscv_command (const char *args, int from_tty) | |
245 | { | |
246 | printf_unfiltered | |
247 | (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n")); | |
248 | help_list (setdebugriscvcmdlist, "set debug riscv ", all_commands, gdb_stdout); | |
249 | } | |
250 | ||
251 | /* The show callback for all 'show debug riscv VARNAME' variables. */ | |
252 | ||
253 | static void | |
254 | show_riscv_debug_variable (struct ui_file *file, int from_tty, | |
255 | struct cmd_list_element *c, | |
256 | const char *value) | |
257 | { | |
258 | fprintf_filtered (file, | |
259 | _("RiscV debug variable `%s' is set to: %s\n"), | |
260 | c->name, value); | |
261 | } | |
262 | ||
263 | /* When this is set to non-zero debugging information about inferior calls | |
264 | will be printed. */ | |
265 | ||
266 | static unsigned int riscv_debug_infcall = 0; | |
267 | ||
268 | /* Read the MISA register from the target. The register will only be read | |
269 | once, and the value read will be cached. If the register can't be read | |
270 | from the target then a default value (0) will be returned. If the | |
271 | pointer READ_P is not null, then the bool pointed to is updated to | |
272 | indicate if the value returned was read from the target (true) or is the | |
273 | default (false). */ | |
274 | ||
275 | static uint32_t | |
276 | riscv_read_misa_reg (bool *read_p) | |
277 | { | |
0b3f9efc | 278 | uint32_t value = 0; |
dbbb1059 | 279 | |
0b3f9efc | 280 | if (target_has_registers) |
dbbb1059 | 281 | { |
dbbb1059 AB |
282 | struct frame_info *frame = get_current_frame (); |
283 | ||
284 | TRY | |
285 | { | |
0b3f9efc AB |
286 | value = get_frame_register_unsigned (frame, |
287 | RISCV_CSR_MISA_REGNUM); | |
dbbb1059 AB |
288 | } |
289 | CATCH (ex, RETURN_MASK_ERROR) | |
290 | { | |
291 | /* Old cores might have MISA located at a different offset. */ | |
292 | value = get_frame_register_unsigned (frame, | |
293 | RISCV_CSR_LEGACY_MISA_REGNUM); | |
294 | } | |
295 | END_CATCH | |
dbbb1059 AB |
296 | } |
297 | ||
0b3f9efc | 298 | return value; |
dbbb1059 AB |
299 | } |
300 | ||
301 | /* Return true if FEATURE is available for the architecture GDBARCH. The | |
302 | FEATURE should be one of the single character feature codes described in | |
303 | the RiscV ISA manual, these are between 'A' and 'Z'. */ | |
304 | ||
305 | static bool | |
306 | riscv_has_feature (struct gdbarch *gdbarch, char feature) | |
307 | { | |
308 | bool have_read_misa = false; | |
309 | uint32_t misa; | |
310 | ||
311 | gdb_assert (feature >= 'A' && feature <= 'Z'); | |
312 | ||
27724bad | 313 | misa = riscv_read_misa_reg (&have_read_misa); |
dbbb1059 AB |
314 | if (!have_read_misa || misa == 0) |
315 | misa = gdbarch_tdep (gdbarch)->core_features; | |
316 | ||
317 | return (misa & (1 << (feature - 'A'))) != 0; | |
318 | } | |
319 | ||
320 | /* Return the width in bytes of the general purpose registers for GDBARCH. | |
321 | Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or | |
322 | RV128. */ | |
323 | ||
411baa47 | 324 | int |
dbbb1059 AB |
325 | riscv_isa_xlen (struct gdbarch *gdbarch) |
326 | { | |
327 | switch (gdbarch_tdep (gdbarch)->abi.fields.base_len) | |
328 | { | |
329 | default: | |
330 | warning (_("unknown xlen size, assuming 4 bytes")); | |
565e0eda | 331 | /* Fall through. */ |
dbbb1059 AB |
332 | case 1: |
333 | return 4; | |
334 | case 2: | |
335 | return 8; | |
336 | case 3: | |
337 | return 16; | |
338 | } | |
339 | } | |
340 | ||
341 | /* Return the width in bytes of the floating point registers for GDBARCH. | |
342 | If this architecture has no floating point registers, then return 0. | |
343 | Possible values are 4, 8, or 16 for depending on which of single, double | |
344 | or quad floating point support is available. */ | |
345 | ||
346 | static int | |
347 | riscv_isa_flen (struct gdbarch *gdbarch) | |
348 | { | |
349 | if (riscv_has_feature (gdbarch, 'Q')) | |
350 | return 16; | |
351 | else if (riscv_has_feature (gdbarch, 'D')) | |
352 | return 8; | |
353 | else if (riscv_has_feature (gdbarch, 'F')) | |
354 | return 4; | |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
359 | /* Return true if the target for GDBARCH has floating point hardware. */ | |
360 | ||
361 | static bool | |
362 | riscv_has_fp_regs (struct gdbarch *gdbarch) | |
363 | { | |
364 | return (riscv_isa_flen (gdbarch) > 0); | |
365 | } | |
366 | ||
367 | /* Return true if GDBARCH is using any of the floating point hardware ABIs. */ | |
368 | ||
369 | static bool | |
370 | riscv_has_fp_abi (struct gdbarch *gdbarch) | |
371 | { | |
372 | return (gdbarch_tdep (gdbarch)->abi.fields.float_abi != 0); | |
373 | } | |
374 | ||
8c49aa89 AB |
375 | /* Return true if REGNO is a floating pointer register. */ |
376 | ||
377 | static bool | |
378 | riscv_is_fp_regno_p (int regno) | |
379 | { | |
380 | return (regno >= RISCV_FIRST_FP_REGNUM | |
381 | && regno <= RISCV_LAST_FP_REGNUM); | |
382 | } | |
383 | ||
dbbb1059 AB |
384 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
385 | ||
386 | static int | |
387 | riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
388 | { | |
389 | if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO) | |
390 | { | |
391 | if (riscv_has_feature (gdbarch, 'C')) | |
392 | return 2; | |
393 | else | |
394 | return 4; | |
395 | } | |
396 | else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE) | |
397 | return 2; | |
398 | else | |
399 | return 4; | |
400 | } | |
401 | ||
402 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ | |
403 | ||
404 | static const gdb_byte * | |
405 | riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
406 | { | |
407 | static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, }; | |
408 | static const gdb_byte c_ebreak[] = { 0x02, 0x90 }; | |
409 | ||
410 | *size = kind; | |
411 | switch (kind) | |
412 | { | |
413 | case 2: | |
414 | return c_ebreak; | |
415 | case 4: | |
416 | return ebreak; | |
417 | default: | |
89a3b63e | 418 | gdb_assert_not_reached (_("unhandled breakpoint kind")); |
dbbb1059 AB |
419 | } |
420 | } | |
421 | ||
422 | /* Callback function for user_reg_add. */ | |
423 | ||
424 | static struct value * | |
425 | value_of_riscv_user_reg (struct frame_info *frame, const void *baton) | |
426 | { | |
427 | const int *reg_p = (const int *) baton; | |
428 | return value_of_register (*reg_p, frame); | |
429 | } | |
430 | ||
431 | /* Implement the register_name gdbarch method. */ | |
432 | ||
433 | static const char * | |
434 | riscv_register_name (struct gdbarch *gdbarch, int regnum) | |
435 | { | |
dbbb1059 AB |
436 | /* Prefer to use the alias. */ |
437 | if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_REGNUM) | |
438 | { | |
439 | int i; | |
440 | ||
441 | for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) | |
442 | if (regnum == riscv_register_aliases[i].regnum) | |
443 | return riscv_register_aliases[i].name; | |
444 | } | |
445 | ||
446 | if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_FP_REGNUM) | |
447 | return riscv_gdb_reg_names[regnum]; | |
448 | ||
449 | if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM) | |
450 | { | |
451 | static char buf[20]; | |
452 | ||
89a3b63e AB |
453 | xsnprintf (buf, sizeof (buf), "csr%d", |
454 | regnum - RISCV_FIRST_CSR_REGNUM); | |
dbbb1059 AB |
455 | return buf; |
456 | } | |
457 | ||
458 | if (regnum == RISCV_PRIV_REGNUM) | |
459 | return "priv"; | |
460 | ||
461 | return NULL; | |
462 | } | |
463 | ||
dbbb1059 AB |
464 | /* Implement the register_type gdbarch method. */ |
465 | ||
466 | static struct type * | |
467 | riscv_register_type (struct gdbarch *gdbarch, int regnum) | |
468 | { | |
469 | int regsize; | |
470 | ||
471 | if (regnum < RISCV_FIRST_FP_REGNUM) | |
472 | { | |
473 | if (regnum == gdbarch_pc_regnum (gdbarch) | |
474 | || regnum == RISCV_RA_REGNUM) | |
475 | return builtin_type (gdbarch)->builtin_func_ptr; | |
476 | ||
477 | if (regnum == RISCV_FP_REGNUM | |
478 | || regnum == RISCV_SP_REGNUM | |
479 | || regnum == RISCV_GP_REGNUM | |
480 | || regnum == RISCV_TP_REGNUM) | |
481 | return builtin_type (gdbarch)->builtin_data_ptr; | |
482 | ||
483 | /* Remaining GPRs vary in size based on the current ISA. */ | |
484 | regsize = riscv_isa_xlen (gdbarch); | |
485 | switch (regsize) | |
486 | { | |
487 | case 4: | |
488 | return builtin_type (gdbarch)->builtin_uint32; | |
489 | case 8: | |
490 | return builtin_type (gdbarch)->builtin_uint64; | |
491 | case 16: | |
492 | return builtin_type (gdbarch)->builtin_uint128; | |
493 | default: | |
494 | internal_error (__FILE__, __LINE__, | |
495 | _("unknown isa regsize %i"), regsize); | |
496 | } | |
497 | } | |
498 | else if (regnum <= RISCV_LAST_FP_REGNUM) | |
499 | { | |
500 | regsize = riscv_isa_xlen (gdbarch); | |
501 | switch (regsize) | |
502 | { | |
503 | case 4: | |
504 | return builtin_type (gdbarch)->builtin_float; | |
505 | case 8: | |
506 | return builtin_type (gdbarch)->builtin_double; | |
507 | case 16: | |
508 | return builtin_type (gdbarch)->builtin_long_double; | |
509 | default: | |
510 | internal_error (__FILE__, __LINE__, | |
511 | _("unknown isa regsize %i"), regsize); | |
512 | } | |
513 | } | |
514 | else if (regnum == RISCV_PRIV_REGNUM) | |
515 | return builtin_type (gdbarch)->builtin_int8; | |
516 | else | |
517 | { | |
518 | if (regnum == RISCV_CSR_FFLAGS_REGNUM | |
519 | || regnum == RISCV_CSR_FRM_REGNUM | |
520 | || regnum == RISCV_CSR_FCSR_REGNUM) | |
521 | return builtin_type (gdbarch)->builtin_int32; | |
522 | ||
523 | regsize = riscv_isa_xlen (gdbarch); | |
524 | switch (regsize) | |
525 | { | |
526 | case 4: | |
527 | return builtin_type (gdbarch)->builtin_int32; | |
528 | case 8: | |
529 | return builtin_type (gdbarch)->builtin_int64; | |
530 | case 16: | |
531 | return builtin_type (gdbarch)->builtin_int128; | |
532 | default: | |
533 | internal_error (__FILE__, __LINE__, | |
534 | _("unknown isa regsize %i"), regsize); | |
535 | } | |
536 | } | |
537 | } | |
538 | ||
539 | /* Helper for riscv_print_registers_info, prints info for a single register | |
540 | REGNUM. */ | |
541 | ||
542 | static void | |
543 | riscv_print_one_register_info (struct gdbarch *gdbarch, | |
544 | struct ui_file *file, | |
545 | struct frame_info *frame, | |
546 | int regnum) | |
547 | { | |
548 | const char *name = gdbarch_register_name (gdbarch, regnum); | |
549 | struct value *val = value_of_register (regnum, frame); | |
550 | struct type *regtype = value_type (val); | |
551 | int print_raw_format; | |
552 | enum tab_stops { value_column_1 = 15 }; | |
553 | ||
554 | fputs_filtered (name, file); | |
555 | print_spaces_filtered (value_column_1 - strlen (name), file); | |
556 | ||
557 | print_raw_format = (value_entirely_available (val) | |
558 | && !value_optimized_out (val)); | |
559 | ||
560 | if (TYPE_CODE (regtype) == TYPE_CODE_FLT) | |
561 | { | |
562 | struct value_print_options opts; | |
563 | const gdb_byte *valaddr = value_contents_for_printing (val); | |
564 | enum bfd_endian byte_order = gdbarch_byte_order (get_type_arch (regtype)); | |
565 | ||
566 | get_user_print_options (&opts); | |
567 | opts.deref_ref = 1; | |
568 | ||
569 | val_print (regtype, | |
570 | value_embedded_offset (val), 0, | |
571 | file, 0, val, &opts, current_language); | |
572 | ||
573 | if (print_raw_format) | |
574 | { | |
575 | fprintf_filtered (file, "\t(raw "); | |
576 | print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order, | |
577 | true); | |
578 | fprintf_filtered (file, ")"); | |
579 | } | |
580 | } | |
581 | else | |
582 | { | |
583 | struct value_print_options opts; | |
584 | ||
585 | /* Print the register in hex. */ | |
586 | get_formatted_print_options (&opts, 'x'); | |
587 | opts.deref_ref = 1; | |
588 | val_print (regtype, | |
589 | value_embedded_offset (val), 0, | |
590 | file, 0, val, &opts, current_language); | |
591 | ||
592 | if (print_raw_format) | |
593 | { | |
594 | if (regnum == RISCV_CSR_MSTATUS_REGNUM) | |
595 | { | |
596 | LONGEST d; | |
597 | int size = register_size (gdbarch, regnum); | |
598 | unsigned xlen; | |
599 | ||
600 | d = value_as_long (val); | |
601 | xlen = size * 4; | |
602 | fprintf_filtered (file, | |
603 | "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X " | |
604 | "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X " | |
605 | "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X", | |
606 | (int) ((d >> (xlen - 1)) & 0x1), | |
607 | (int) ((d >> 24) & 0x1f), | |
608 | (int) ((d >> 19) & 0x1), | |
609 | (int) ((d >> 18) & 0x1), | |
610 | (int) ((d >> 17) & 0x1), | |
611 | (int) ((d >> 15) & 0x3), | |
612 | (int) ((d >> 13) & 0x3), | |
613 | (int) ((d >> 11) & 0x3), | |
614 | (int) ((d >> 9) & 0x3), | |
615 | (int) ((d >> 8) & 0x1), | |
616 | (int) ((d >> 7) & 0x1), | |
617 | (int) ((d >> 6) & 0x1), | |
618 | (int) ((d >> 5) & 0x1), | |
619 | (int) ((d >> 4) & 0x1), | |
620 | (int) ((d >> 3) & 0x1), | |
621 | (int) ((d >> 2) & 0x1), | |
622 | (int) ((d >> 1) & 0x1), | |
623 | (int) ((d >> 0) & 0x1)); | |
624 | } | |
625 | else if (regnum == RISCV_CSR_MISA_REGNUM) | |
626 | { | |
627 | int base; | |
628 | unsigned xlen, i; | |
629 | LONGEST d; | |
630 | ||
631 | d = value_as_long (val); | |
632 | base = d >> 30; | |
633 | xlen = 16; | |
634 | ||
635 | for (; base > 0; base--) | |
636 | xlen *= 2; | |
637 | fprintf_filtered (file, "\tRV%d", xlen); | |
638 | ||
639 | for (i = 0; i < 26; i++) | |
640 | { | |
641 | if (d & (1 << i)) | |
642 | fprintf_filtered (file, "%c", 'A' + i); | |
643 | } | |
644 | } | |
645 | else if (regnum == RISCV_CSR_FCSR_REGNUM | |
646 | || regnum == RISCV_CSR_FFLAGS_REGNUM | |
647 | || regnum == RISCV_CSR_FRM_REGNUM) | |
648 | { | |
649 | LONGEST d; | |
650 | ||
651 | d = value_as_long (val); | |
652 | ||
653 | fprintf_filtered (file, "\t"); | |
654 | if (regnum != RISCV_CSR_FRM_REGNUM) | |
655 | fprintf_filtered (file, | |
656 | "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d", | |
657 | (int) ((d >> 5) & 0x7), | |
658 | (int) ((d >> 4) & 0x1), | |
659 | (int) ((d >> 3) & 0x1), | |
660 | (int) ((d >> 2) & 0x1), | |
661 | (int) ((d >> 1) & 0x1), | |
662 | (int) ((d >> 0) & 0x1)); | |
663 | ||
664 | if (regnum != RISCV_CSR_FFLAGS_REGNUM) | |
665 | { | |
666 | static const char * const sfrm[] = | |
667 | { | |
668 | "RNE (round to nearest; ties to even)", | |
669 | "RTZ (Round towards zero)", | |
670 | "RDN (Round down towards -INF)", | |
671 | "RUP (Round up towards +INF)", | |
672 | "RMM (Round to nearest; ties to max magnitude)", | |
673 | "INVALID[5]", | |
674 | "INVALID[6]", | |
675 | "dynamic rounding mode", | |
676 | }; | |
677 | int frm = ((regnum == RISCV_CSR_FCSR_REGNUM) | |
678 | ? (d >> 5) : d) & 0x3; | |
679 | ||
680 | fprintf_filtered (file, "%sFRM:%i [%s]", | |
681 | (regnum == RISCV_CSR_FCSR_REGNUM | |
682 | ? " " : ""), | |
683 | frm, sfrm[frm]); | |
684 | } | |
685 | } | |
686 | else if (regnum == RISCV_PRIV_REGNUM) | |
687 | { | |
688 | LONGEST d; | |
689 | uint8_t priv; | |
690 | ||
691 | d = value_as_long (val); | |
692 | priv = d & 0xff; | |
693 | ||
694 | if (priv < 4) | |
695 | { | |
696 | static const char * const sprv[] = | |
697 | { | |
698 | "User/Application", | |
699 | "Supervisor", | |
700 | "Hypervisor", | |
701 | "Machine" | |
702 | }; | |
703 | fprintf_filtered (file, "\tprv:%d [%s]", | |
704 | priv, sprv[priv]); | |
705 | } | |
706 | else | |
707 | fprintf_filtered (file, "\tprv:%d [INVALID]", priv); | |
708 | } | |
709 | else | |
710 | { | |
711 | /* If not a vector register, print it also according to its | |
712 | natural format. */ | |
713 | if (TYPE_VECTOR (regtype) == 0) | |
714 | { | |
715 | get_user_print_options (&opts); | |
716 | opts.deref_ref = 1; | |
717 | fprintf_filtered (file, "\t"); | |
718 | val_print (regtype, | |
719 | value_embedded_offset (val), 0, | |
720 | file, 0, val, &opts, current_language); | |
721 | } | |
722 | } | |
723 | } | |
724 | } | |
725 | fprintf_filtered (file, "\n"); | |
726 | } | |
727 | ||
728 | /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member | |
729 | of REGGROUP? */ | |
730 | ||
731 | static int | |
732 | riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
733 | struct reggroup *reggroup) | |
734 | { | |
dbbb1059 AB |
735 | unsigned int i; |
736 | ||
737 | /* Used by 'info registers' and 'info registers <groupname>'. */ | |
738 | ||
739 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
740 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
741 | return 0; | |
742 | ||
743 | if (reggroup == all_reggroup) | |
744 | { | |
745 | if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM) | |
746 | return 1; | |
747 | /* Only include CSRs that have aliases. */ | |
748 | for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) | |
749 | { | |
750 | if (regnum == riscv_register_aliases[i].regnum) | |
751 | return 1; | |
752 | } | |
753 | return 0; | |
754 | } | |
755 | else if (reggroup == float_reggroup) | |
8c49aa89 AB |
756 | return (riscv_is_fp_regno_p (regnum) |
757 | || regnum == RISCV_CSR_FCSR_REGNUM | |
758 | || regnum == RISCV_CSR_FFLAGS_REGNUM | |
759 | || regnum == RISCV_CSR_FRM_REGNUM); | |
dbbb1059 AB |
760 | else if (reggroup == general_reggroup) |
761 | return regnum < RISCV_FIRST_FP_REGNUM; | |
762 | else if (reggroup == restore_reggroup || reggroup == save_reggroup) | |
763 | { | |
764 | if (riscv_has_fp_regs (gdbarch)) | |
765 | return regnum <= RISCV_LAST_FP_REGNUM; | |
766 | else | |
767 | return regnum < RISCV_FIRST_FP_REGNUM; | |
768 | } | |
769 | else if (reggroup == system_reggroup) | |
770 | { | |
771 | if (regnum == RISCV_PRIV_REGNUM) | |
772 | return 1; | |
773 | if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM) | |
774 | return 0; | |
775 | /* Only include CSRs that have aliases. */ | |
776 | for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) | |
777 | { | |
778 | if (regnum == riscv_register_aliases[i].regnum) | |
779 | return 1; | |
780 | } | |
781 | return 0; | |
782 | } | |
783 | else if (reggroup == vector_reggroup) | |
784 | return 0; | |
785 | else | |
786 | return 0; | |
787 | } | |
788 | ||
789 | /* Implement the print_registers_info gdbarch method. This is used by | |
790 | 'info registers' and 'info all-registers'. */ | |
791 | ||
792 | static void | |
793 | riscv_print_registers_info (struct gdbarch *gdbarch, | |
794 | struct ui_file *file, | |
795 | struct frame_info *frame, | |
796 | int regnum, int print_all) | |
797 | { | |
798 | if (regnum != -1) | |
799 | { | |
800 | /* Print one specified register. */ | |
801 | gdb_assert (regnum <= RISCV_LAST_REGNUM); | |
802 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
803 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
804 | error (_("Not a valid register for the current processor type")); | |
805 | riscv_print_one_register_info (gdbarch, file, frame, regnum); | |
806 | } | |
807 | else | |
808 | { | |
809 | struct reggroup *reggroup; | |
810 | ||
811 | if (print_all) | |
812 | reggroup = all_reggroup; | |
813 | else | |
814 | reggroup = general_reggroup; | |
815 | ||
816 | for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum) | |
817 | { | |
818 | /* Zero never changes, so might as well hide by default. */ | |
819 | if (regnum == RISCV_ZERO_REGNUM && !print_all) | |
820 | continue; | |
821 | ||
822 | /* Registers with no name are not valid on this ISA. */ | |
823 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
824 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
825 | continue; | |
826 | ||
827 | /* Is the register in the group we're interested in? */ | |
828 | if (!riscv_register_reggroup_p (gdbarch, regnum, reggroup)) | |
829 | continue; | |
830 | ||
831 | riscv_print_one_register_info (gdbarch, file, frame, regnum); | |
832 | } | |
833 | } | |
834 | } | |
835 | ||
836 | /* Class that handles one decoded RiscV instruction. */ | |
837 | ||
838 | class riscv_insn | |
839 | { | |
840 | public: | |
841 | ||
842 | /* Enum of all the opcodes that GDB cares about during the prologue scan. */ | |
843 | enum opcode | |
844 | { | |
845 | /* Unknown value is used at initialisation time. */ | |
846 | UNKNOWN = 0, | |
847 | ||
848 | /* These instructions are all the ones we are interested in during the | |
849 | prologue scan. */ | |
850 | ADD, | |
851 | ADDI, | |
852 | ADDIW, | |
853 | ADDW, | |
854 | AUIPC, | |
855 | LUI, | |
856 | SD, | |
857 | SW, | |
5c720ed8 JW |
858 | /* These are needed for software breakopint support. */ |
859 | JAL, | |
860 | JALR, | |
861 | BEQ, | |
862 | BNE, | |
863 | BLT, | |
864 | BGE, | |
865 | BLTU, | |
866 | BGEU, | |
867 | /* These are needed for stepping over atomic sequences. */ | |
868 | LR, | |
869 | SC, | |
dbbb1059 AB |
870 | |
871 | /* Other instructions are not interesting during the prologue scan, and | |
872 | are ignored. */ | |
873 | OTHER | |
874 | }; | |
875 | ||
876 | riscv_insn () | |
877 | : m_length (0), | |
878 | m_opcode (OTHER), | |
879 | m_rd (0), | |
880 | m_rs1 (0), | |
881 | m_rs2 (0) | |
882 | { | |
883 | /* Nothing. */ | |
884 | } | |
885 | ||
886 | void decode (struct gdbarch *gdbarch, CORE_ADDR pc); | |
887 | ||
888 | /* Get the length of the instruction in bytes. */ | |
889 | int length () const | |
890 | { return m_length; } | |
891 | ||
892 | /* Get the opcode for this instruction. */ | |
893 | enum opcode opcode () const | |
894 | { return m_opcode; } | |
895 | ||
896 | /* Get destination register field for this instruction. This is only | |
897 | valid if the OPCODE implies there is such a field for this | |
898 | instruction. */ | |
899 | int rd () const | |
900 | { return m_rd; } | |
901 | ||
902 | /* Get the RS1 register field for this instruction. This is only valid | |
903 | if the OPCODE implies there is such a field for this instruction. */ | |
904 | int rs1 () const | |
905 | { return m_rs1; } | |
906 | ||
907 | /* Get the RS2 register field for this instruction. This is only valid | |
908 | if the OPCODE implies there is such a field for this instruction. */ | |
909 | int rs2 () const | |
910 | { return m_rs2; } | |
911 | ||
912 | /* Get the immediate for this instruction in signed form. This is only | |
913 | valid if the OPCODE implies there is such a field for this | |
914 | instruction. */ | |
915 | int imm_signed () const | |
916 | { return m_imm.s; } | |
917 | ||
918 | private: | |
919 | ||
920 | /* Extract 5 bit register field at OFFSET from instruction OPCODE. */ | |
921 | int decode_register_index (unsigned long opcode, int offset) | |
922 | { | |
923 | return (opcode >> offset) & 0x1F; | |
924 | } | |
925 | ||
5c720ed8 JW |
926 | /* Extract 5 bit register field at OFFSET from instruction OPCODE. */ |
927 | int decode_register_index_short (unsigned long opcode, int offset) | |
928 | { | |
929 | return ((opcode >> offset) & 0x7) + 8; | |
930 | } | |
931 | ||
dbbb1059 AB |
932 | /* Helper for DECODE, decode 32-bit R-type instruction. */ |
933 | void decode_r_type_insn (enum opcode opcode, ULONGEST ival) | |
934 | { | |
935 | m_opcode = opcode; | |
936 | m_rd = decode_register_index (ival, OP_SH_RD); | |
937 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
938 | m_rs2 = decode_register_index (ival, OP_SH_RS2); | |
939 | } | |
940 | ||
941 | /* Helper for DECODE, decode 16-bit compressed R-type instruction. */ | |
942 | void decode_cr_type_insn (enum opcode opcode, ULONGEST ival) | |
943 | { | |
944 | m_opcode = opcode; | |
945 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S); | |
946 | m_rs2 = decode_register_index (ival, OP_SH_CRS2); | |
947 | } | |
948 | ||
949 | /* Helper for DECODE, decode 32-bit I-type instruction. */ | |
950 | void decode_i_type_insn (enum opcode opcode, ULONGEST ival) | |
951 | { | |
952 | m_opcode = opcode; | |
953 | m_rd = decode_register_index (ival, OP_SH_RD); | |
954 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
955 | m_imm.s = EXTRACT_ITYPE_IMM (ival); | |
956 | } | |
957 | ||
958 | /* Helper for DECODE, decode 16-bit compressed I-type instruction. */ | |
959 | void decode_ci_type_insn (enum opcode opcode, ULONGEST ival) | |
960 | { | |
961 | m_opcode = opcode; | |
962 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S); | |
963 | m_imm.s = EXTRACT_RVC_IMM (ival); | |
964 | } | |
965 | ||
966 | /* Helper for DECODE, decode 32-bit S-type instruction. */ | |
967 | void decode_s_type_insn (enum opcode opcode, ULONGEST ival) | |
968 | { | |
969 | m_opcode = opcode; | |
970 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
971 | m_rs2 = decode_register_index (ival, OP_SH_RS2); | |
972 | m_imm.s = EXTRACT_STYPE_IMM (ival); | |
973 | } | |
974 | ||
ff3a05b3 AB |
975 | /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate |
976 | encoding is different for each CS format instruction, so extracting | |
977 | the immediate is left up to the caller, who should pass the extracted | |
978 | immediate value through in IMM. */ | |
979 | void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm) | |
980 | { | |
981 | m_opcode = opcode; | |
982 | m_imm.s = imm; | |
983 | m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S); | |
984 | m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S); | |
985 | } | |
986 | ||
987 | /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate | |
988 | encoding is different for each CSS format instruction, so extracting | |
989 | the immediate is left up to the caller, who should pass the extracted | |
990 | immediate value through in IMM. */ | |
991 | void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm) | |
992 | { | |
993 | m_opcode = opcode; | |
994 | m_imm.s = imm; | |
995 | m_rs1 = RISCV_SP_REGNUM; | |
996 | /* Not a compressed register number in this case. */ | |
997 | m_rs2 = decode_register_index (ival, OP_SH_CRS2); | |
998 | } | |
999 | ||
dbbb1059 AB |
1000 | /* Helper for DECODE, decode 32-bit U-type instruction. */ |
1001 | void decode_u_type_insn (enum opcode opcode, ULONGEST ival) | |
1002 | { | |
1003 | m_opcode = opcode; | |
1004 | m_rd = decode_register_index (ival, OP_SH_RD); | |
1005 | m_imm.s = EXTRACT_UTYPE_IMM (ival); | |
1006 | } | |
1007 | ||
5c720ed8 JW |
1008 | /* Helper for DECODE, decode 32-bit J-type instruction. */ |
1009 | void decode_j_type_insn (enum opcode opcode, ULONGEST ival) | |
1010 | { | |
1011 | m_opcode = opcode; | |
1012 | m_rd = decode_register_index (ival, OP_SH_RD); | |
1013 | m_imm.s = EXTRACT_UJTYPE_IMM (ival); | |
1014 | } | |
1015 | ||
1016 | /* Helper for DECODE, decode 32-bit J-type instruction. */ | |
1017 | void decode_cj_type_insn (enum opcode opcode, ULONGEST ival) | |
1018 | { | |
1019 | m_opcode = opcode; | |
1020 | m_imm.s = EXTRACT_RVC_J_IMM (ival); | |
1021 | } | |
1022 | ||
1023 | void decode_b_type_insn (enum opcode opcode, ULONGEST ival) | |
1024 | { | |
1025 | m_opcode = opcode; | |
1026 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
1027 | m_rs2 = decode_register_index (ival, OP_SH_RS2); | |
1028 | m_imm.s = EXTRACT_SBTYPE_IMM (ival); | |
1029 | } | |
1030 | ||
1031 | void decode_cb_type_insn (enum opcode opcode, ULONGEST ival) | |
1032 | { | |
1033 | m_opcode = opcode; | |
1034 | m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S); | |
1035 | m_imm.s = EXTRACT_RVC_B_IMM (ival); | |
1036 | } | |
1037 | ||
dbbb1059 AB |
1038 | /* Fetch instruction from target memory at ADDR, return the content of |
1039 | the instruction, and update LEN with the instruction length. */ | |
1040 | static ULONGEST fetch_instruction (struct gdbarch *gdbarch, | |
1041 | CORE_ADDR addr, int *len); | |
1042 | ||
1043 | /* The length of the instruction in bytes. Should be 2 or 4. */ | |
1044 | int m_length; | |
1045 | ||
1046 | /* The instruction opcode. */ | |
1047 | enum opcode m_opcode; | |
1048 | ||
1049 | /* The three possible registers an instruction might reference. Not | |
1050 | every instruction fills in all of these registers. Which fields are | |
1051 | valid depends on the opcode. The naming of these fields matches the | |
1052 | naming in the riscv isa manual. */ | |
1053 | int m_rd; | |
1054 | int m_rs1; | |
1055 | int m_rs2; | |
1056 | ||
1057 | /* Possible instruction immediate. This is only valid if the instruction | |
1058 | format contains an immediate, not all instruction, whether this is | |
1059 | valid depends on the opcode. Despite only having one format for now | |
1060 | the immediate is packed into a union, later instructions might require | |
1061 | an unsigned formatted immediate, having the union in place now will | |
1062 | reduce the need for code churn later. */ | |
1063 | union riscv_insn_immediate | |
1064 | { | |
1065 | riscv_insn_immediate () | |
1066 | : s (0) | |
1067 | { | |
1068 | /* Nothing. */ | |
1069 | } | |
1070 | ||
1071 | int s; | |
1072 | } m_imm; | |
1073 | }; | |
1074 | ||
1075 | /* Fetch instruction from target memory at ADDR, return the content of the | |
1076 | instruction, and update LEN with the instruction length. */ | |
1077 | ||
1078 | ULONGEST | |
1079 | riscv_insn::fetch_instruction (struct gdbarch *gdbarch, | |
1080 | CORE_ADDR addr, int *len) | |
1081 | { | |
1082 | enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch); | |
1083 | gdb_byte buf[8]; | |
1084 | int instlen, status; | |
1085 | ||
1086 | /* All insns are at least 16 bits. */ | |
1087 | status = target_read_memory (addr, buf, 2); | |
1088 | if (status) | |
1089 | memory_error (TARGET_XFER_E_IO, addr); | |
1090 | ||
1091 | /* If we need more, grab it now. */ | |
1092 | instlen = riscv_insn_length (buf[0]); | |
89a3b63e | 1093 | gdb_assert (instlen <= sizeof (buf)); |
dbbb1059 | 1094 | *len = instlen; |
89a3b63e AB |
1095 | |
1096 | if (instlen > 2) | |
dbbb1059 AB |
1097 | { |
1098 | status = target_read_memory (addr + 2, buf + 2, instlen - 2); | |
1099 | if (status) | |
1100 | memory_error (TARGET_XFER_E_IO, addr + 2); | |
1101 | } | |
1102 | ||
1103 | return extract_unsigned_integer (buf, instlen, byte_order); | |
1104 | } | |
1105 | ||
1106 | /* Fetch from target memory an instruction at PC and decode it. */ | |
1107 | ||
1108 | void | |
1109 | riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1110 | { | |
1111 | ULONGEST ival; | |
1112 | ||
1113 | /* Fetch the instruction, and the instructions length. */ | |
1114 | ival = fetch_instruction (gdbarch, pc, &m_length); | |
1115 | ||
1116 | if (m_length == 4) | |
1117 | { | |
1118 | if (is_add_insn (ival)) | |
1119 | decode_r_type_insn (ADD, ival); | |
1120 | else if (is_addw_insn (ival)) | |
1121 | decode_r_type_insn (ADDW, ival); | |
1122 | else if (is_addi_insn (ival)) | |
1123 | decode_i_type_insn (ADDI, ival); | |
1124 | else if (is_addiw_insn (ival)) | |
1125 | decode_i_type_insn (ADDIW, ival); | |
1126 | else if (is_auipc_insn (ival)) | |
1127 | decode_u_type_insn (AUIPC, ival); | |
1128 | else if (is_lui_insn (ival)) | |
1129 | decode_u_type_insn (LUI, ival); | |
1130 | else if (is_sd_insn (ival)) | |
1131 | decode_s_type_insn (SD, ival); | |
1132 | else if (is_sw_insn (ival)) | |
1133 | decode_s_type_insn (SW, ival); | |
5c720ed8 JW |
1134 | else if (is_jal_insn (ival)) |
1135 | decode_j_type_insn (JAL, ival); | |
1136 | else if (is_jalr_insn (ival)) | |
1137 | decode_i_type_insn (JALR, ival); | |
1138 | else if (is_beq_insn (ival)) | |
1139 | decode_b_type_insn (BEQ, ival); | |
1140 | else if (is_bne_insn (ival)) | |
1141 | decode_b_type_insn (BNE, ival); | |
1142 | else if (is_blt_insn (ival)) | |
1143 | decode_b_type_insn (BLT, ival); | |
1144 | else if (is_bge_insn (ival)) | |
1145 | decode_b_type_insn (BGE, ival); | |
1146 | else if (is_bltu_insn (ival)) | |
1147 | decode_b_type_insn (BLTU, ival); | |
1148 | else if (is_bgeu_insn (ival)) | |
1149 | decode_b_type_insn (BGEU, ival); | |
1150 | else if (is_lr_w_insn (ival)) | |
1151 | decode_r_type_insn (LR, ival); | |
1152 | else if (is_lr_d_insn (ival)) | |
1153 | decode_r_type_insn (LR, ival); | |
1154 | else if (is_sc_w_insn (ival)) | |
1155 | decode_r_type_insn (SC, ival); | |
1156 | else if (is_sc_d_insn (ival)) | |
1157 | decode_r_type_insn (SC, ival); | |
dbbb1059 AB |
1158 | else |
1159 | /* None of the other fields are valid in this case. */ | |
1160 | m_opcode = OTHER; | |
1161 | } | |
1162 | else if (m_length == 2) | |
1163 | { | |
5c720ed8 JW |
1164 | int xlen = riscv_isa_xlen (gdbarch); |
1165 | ||
1166 | /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a | |
1167 | C_JALR. So must try to match C_JALR first as it has more bits in | |
1168 | mask. */ | |
1169 | if (is_c_jalr_insn (ival)) | |
1170 | decode_cr_type_insn (JALR, ival); | |
1171 | else if (is_c_add_insn (ival)) | |
dbbb1059 | 1172 | decode_cr_type_insn (ADD, ival); |
5c720ed8 JW |
1173 | /* C_ADDW is RV64 and RV128 only. */ |
1174 | else if (xlen != 4 && is_c_addw_insn (ival)) | |
dbbb1059 AB |
1175 | decode_cr_type_insn (ADDW, ival); |
1176 | else if (is_c_addi_insn (ival)) | |
1177 | decode_ci_type_insn (ADDI, ival); | |
5c720ed8 JW |
1178 | /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128 |
1179 | only and C_JAL is RV32 only. */ | |
1180 | else if (xlen != 4 && is_c_addiw_insn (ival)) | |
dbbb1059 | 1181 | decode_ci_type_insn (ADDIW, ival); |
5c720ed8 JW |
1182 | else if (xlen == 4 && is_c_jal_insn (ival)) |
1183 | decode_cj_type_insn (JAL, ival); | |
1184 | /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a | |
1185 | C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits | |
1186 | in mask. */ | |
dbbb1059 AB |
1187 | else if (is_c_addi16sp_insn (ival)) |
1188 | { | |
1189 | m_opcode = ADDI; | |
1190 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD); | |
1191 | m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival); | |
1192 | } | |
ff3a05b3 AB |
1193 | else if (is_c_addi4spn_insn (ival)) |
1194 | { | |
1195 | m_opcode = ADDI; | |
1196 | m_rd = decode_register_index_short (ival, OP_SH_CRS2S); | |
1197 | m_rs1 = RISCV_SP_REGNUM; | |
1198 | m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival); | |
1199 | } | |
5c720ed8 | 1200 | else if (is_c_lui_insn (ival)) |
dbbb1059 | 1201 | m_opcode = OTHER; |
5c720ed8 JW |
1202 | /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only, |
1203 | and C_FSW is RV32 only. */ | |
1204 | else if (xlen != 4 && is_c_sd_insn (ival)) | |
ff3a05b3 | 1205 | decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival)); |
5c720ed8 | 1206 | else if (is_c_sw_insn (ival)) |
ff3a05b3 AB |
1207 | decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival)); |
1208 | else if (is_c_swsp_insn (ival)) | |
1209 | decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival)); | |
1210 | else if (xlen != 4 && is_c_sdsp_insn (ival)) | |
1211 | decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival)); | |
5c720ed8 JW |
1212 | /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR. |
1213 | So must try to match C_JR first as it ahs more bits in mask. */ | |
1214 | else if (is_c_jr_insn (ival)) | |
1215 | decode_cr_type_insn (JALR, ival); | |
1216 | else if (is_c_j_insn (ival)) | |
1217 | decode_cj_type_insn (JAL, ival); | |
1218 | else if (is_c_beqz_insn (ival)) | |
1219 | decode_cb_type_insn (BEQ, ival); | |
1220 | else if (is_c_bnez_insn (ival)) | |
1221 | decode_cb_type_insn (BNE, ival); | |
dbbb1059 AB |
1222 | else |
1223 | /* None of the other fields of INSN are valid in this case. */ | |
1224 | m_opcode = OTHER; | |
1225 | } | |
1226 | else | |
1227 | internal_error (__FILE__, __LINE__, | |
1228 | _("unable to decode %d byte instructions in " | |
1229 | "prologue at %s"), m_length, | |
1230 | core_addr_to_string (pc)); | |
1231 | } | |
1232 | ||
1233 | /* The prologue scanner. This is currently only used for skipping the | |
1234 | prologue of a function when the DWARF information is not sufficient. | |
1235 | However, it is written with filling of the frame cache in mind, which | |
1236 | is why different groups of stack setup instructions are split apart | |
1237 | during the core of the inner loop. In the future, the intention is to | |
1238 | extend this function to fully support building up a frame cache that | |
1239 | can unwind register values when there is no DWARF information. */ | |
1240 | ||
1241 | static CORE_ADDR | |
1242 | riscv_scan_prologue (struct gdbarch *gdbarch, | |
1243 | CORE_ADDR start_pc, CORE_ADDR limit_pc) | |
1244 | { | |
1245 | CORE_ADDR cur_pc, next_pc; | |
1246 | long frame_offset = 0; | |
1247 | CORE_ADDR end_prologue_addr = 0; | |
1248 | ||
1249 | if (limit_pc > start_pc + 200) | |
1250 | limit_pc = start_pc + 200; | |
1251 | ||
1252 | for (next_pc = cur_pc = start_pc; cur_pc < limit_pc; cur_pc = next_pc) | |
1253 | { | |
1254 | struct riscv_insn insn; | |
1255 | ||
1256 | /* Decode the current instruction, and decide where the next | |
1257 | instruction lives based on the size of this instruction. */ | |
1258 | insn.decode (gdbarch, cur_pc); | |
1259 | gdb_assert (insn.length () > 0); | |
1260 | next_pc = cur_pc + insn.length (); | |
1261 | ||
1262 | /* Look for common stack adjustment insns. */ | |
1263 | if ((insn.opcode () == riscv_insn::ADDI | |
1264 | || insn.opcode () == riscv_insn::ADDIW) | |
1265 | && insn.rd () == RISCV_SP_REGNUM | |
1266 | && insn.rs1 () == RISCV_SP_REGNUM) | |
1267 | { | |
1268 | /* Handle: addi sp, sp, -i | |
1269 | or: addiw sp, sp, -i */ | |
1270 | if (insn.imm_signed () < 0) | |
1271 | frame_offset += insn.imm_signed (); | |
1272 | else | |
1273 | break; | |
1274 | } | |
1275 | else if ((insn.opcode () == riscv_insn::SW | |
1276 | || insn.opcode () == riscv_insn::SD) | |
1277 | && (insn.rs1 () == RISCV_SP_REGNUM | |
1278 | || insn.rs1 () == RISCV_FP_REGNUM)) | |
1279 | { | |
1280 | /* Handle: sw reg, offset(sp) | |
1281 | or: sd reg, offset(sp) | |
1282 | or: sw reg, offset(s0) | |
1283 | or: sd reg, offset(s0) */ | |
1284 | /* Instruction storing a register onto the stack. */ | |
1285 | } | |
1286 | else if (insn.opcode () == riscv_insn::ADDI | |
1287 | && insn.rd () == RISCV_FP_REGNUM | |
1288 | && insn.rs1 () == RISCV_SP_REGNUM) | |
1289 | { | |
1290 | /* Handle: addi s0, sp, size */ | |
1291 | /* Instructions setting up the frame pointer. */ | |
1292 | } | |
1293 | else if ((insn.opcode () == riscv_insn::ADD | |
1294 | || insn.opcode () == riscv_insn::ADDW) | |
1295 | && insn.rd () == RISCV_FP_REGNUM | |
1296 | && insn.rs1 () == RISCV_SP_REGNUM | |
1297 | && insn.rs2 () == RISCV_ZERO_REGNUM) | |
1298 | { | |
1299 | /* Handle: add s0, sp, 0 | |
1300 | or: addw s0, sp, 0 */ | |
1301 | /* Instructions setting up the frame pointer. */ | |
1302 | } | |
1303 | else if ((insn.rd () == RISCV_GP_REGNUM | |
1304 | && (insn.opcode () == riscv_insn::AUIPC | |
1305 | || insn.opcode () == riscv_insn::LUI | |
1306 | || (insn.opcode () == riscv_insn::ADDI | |
1307 | && insn.rs1 () == RISCV_GP_REGNUM) | |
1308 | || (insn.opcode () == riscv_insn::ADD | |
1309 | && (insn.rs1 () == RISCV_GP_REGNUM | |
1310 | || insn.rs2 () == RISCV_GP_REGNUM)))) | |
1311 | || (insn.opcode () == riscv_insn::ADDI | |
1312 | && insn.rd () == RISCV_ZERO_REGNUM | |
1313 | && insn.rs1 () == RISCV_ZERO_REGNUM | |
1314 | && insn.imm_signed () == 0)) | |
1315 | { | |
1316 | /* Handle: auipc gp, n | |
1317 | or: addi gp, gp, n | |
1318 | or: add gp, gp, reg | |
1319 | or: add gp, reg, gp | |
1320 | or: lui gp, n | |
1321 | or: add x0, x0, 0 (NOP) */ | |
1322 | /* These instructions are part of the prologue, but we don't need | |
1323 | to do anything special to handle them. */ | |
1324 | } | |
1325 | else | |
1326 | { | |
1327 | if (end_prologue_addr == 0) | |
1328 | end_prologue_addr = cur_pc; | |
1329 | } | |
1330 | } | |
1331 | ||
1332 | if (end_prologue_addr == 0) | |
1333 | end_prologue_addr = cur_pc; | |
1334 | ||
1335 | return end_prologue_addr; | |
1336 | } | |
1337 | ||
1338 | /* Implement the riscv_skip_prologue gdbarch method. */ | |
1339 | ||
1340 | static CORE_ADDR | |
1341 | riscv_skip_prologue (struct gdbarch *gdbarch, | |
1342 | CORE_ADDR pc) | |
1343 | { | |
1344 | CORE_ADDR limit_pc; | |
1345 | CORE_ADDR func_addr; | |
1346 | ||
1347 | /* See if we can determine the end of the prologue via the symbol | |
1348 | table. If so, then return either PC, or the PC after the | |
1349 | prologue, whichever is greater. */ | |
1350 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
1351 | { | |
1352 | CORE_ADDR post_prologue_pc | |
1353 | = skip_prologue_using_sal (gdbarch, func_addr); | |
1354 | ||
1355 | if (post_prologue_pc != 0) | |
1356 | return std::max (pc, post_prologue_pc); | |
1357 | } | |
1358 | ||
1359 | /* Can't determine prologue from the symbol table, need to examine | |
1360 | instructions. */ | |
1361 | ||
1362 | /* Find an upper limit on the function prologue using the debug | |
1363 | information. If the debug information could not be used to provide | |
1364 | that bound, then use an arbitrary large number as the upper bound. */ | |
1365 | limit_pc = skip_prologue_using_sal (gdbarch, pc); | |
1366 | if (limit_pc == 0) | |
1367 | limit_pc = pc + 100; /* MAGIC! */ | |
1368 | ||
1369 | return riscv_scan_prologue (gdbarch, pc, limit_pc); | |
1370 | } | |
1371 | ||
1372 | /* Implement the gdbarch push dummy code callback. */ | |
1373 | ||
1374 | static CORE_ADDR | |
1375 | riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
1376 | CORE_ADDR funaddr, struct value **args, int nargs, | |
1377 | struct type *value_type, CORE_ADDR *real_pc, | |
1378 | CORE_ADDR *bp_addr, struct regcache *regcache) | |
1379 | { | |
1380 | /* Allocate space for a breakpoint, and keep the stack correctly | |
1381 | aligned. */ | |
1382 | sp -= 16; | |
1383 | *bp_addr = sp; | |
1384 | *real_pc = funaddr; | |
1385 | return sp; | |
1386 | } | |
1387 | ||
1388 | /* Compute the alignment of the type T. Used while setting up the | |
1389 | arguments for a dummy call. */ | |
1390 | ||
1391 | static int | |
1392 | riscv_type_alignment (struct type *t) | |
1393 | { | |
1394 | t = check_typedef (t); | |
1395 | switch (TYPE_CODE (t)) | |
1396 | { | |
1397 | default: | |
1398 | error (_("Could not compute alignment of type")); | |
1399 | ||
1400 | case TYPE_CODE_RVALUE_REF: | |
1401 | case TYPE_CODE_PTR: | |
1402 | case TYPE_CODE_ENUM: | |
1403 | case TYPE_CODE_INT: | |
1404 | case TYPE_CODE_FLT: | |
1405 | case TYPE_CODE_REF: | |
1406 | case TYPE_CODE_CHAR: | |
1407 | case TYPE_CODE_BOOL: | |
1408 | return TYPE_LENGTH (t); | |
1409 | ||
1410 | case TYPE_CODE_ARRAY: | |
1411 | case TYPE_CODE_COMPLEX: | |
1412 | return riscv_type_alignment (TYPE_TARGET_TYPE (t)); | |
1413 | ||
1414 | case TYPE_CODE_STRUCT: | |
1415 | case TYPE_CODE_UNION: | |
1416 | { | |
1417 | int i; | |
1418 | int align = 1; | |
1419 | ||
1420 | for (i = 0; i < TYPE_NFIELDS (t); ++i) | |
1421 | { | |
1422 | if (TYPE_FIELD_LOC_KIND (t, i) == FIELD_LOC_KIND_BITPOS) | |
1423 | { | |
1424 | int a = riscv_type_alignment (TYPE_FIELD_TYPE (t, i)); | |
1425 | if (a > align) | |
1426 | align = a; | |
1427 | } | |
1428 | } | |
1429 | return align; | |
1430 | } | |
1431 | } | |
1432 | } | |
1433 | ||
1434 | /* Holds information about a single argument either being passed to an | |
1435 | inferior function, or returned from an inferior function. This includes | |
1436 | information about the size, type, etc of the argument, and also | |
1437 | information about how the argument will be passed (or returned). */ | |
1438 | ||
1439 | struct riscv_arg_info | |
1440 | { | |
1441 | /* Contents of the argument. */ | |
1442 | const gdb_byte *contents; | |
1443 | ||
1444 | /* Length of argument. */ | |
1445 | int length; | |
1446 | ||
1447 | /* Alignment required for an argument of this type. */ | |
1448 | int align; | |
1449 | ||
1450 | /* The type for this argument. */ | |
1451 | struct type *type; | |
1452 | ||
1453 | /* Each argument can have either 1 or 2 locations assigned to it. Each | |
1454 | location describes where part of the argument will be placed. The | |
1455 | second location is valid based on the LOC_TYPE and C_LENGTH fields | |
1456 | of the first location (which is always valid). */ | |
1457 | struct location | |
1458 | { | |
1459 | /* What type of location this is. */ | |
1460 | enum location_type | |
1461 | { | |
1462 | /* Argument passed in a register. */ | |
1463 | in_reg, | |
1464 | ||
1465 | /* Argument passed as an on stack argument. */ | |
1466 | on_stack, | |
1467 | ||
1468 | /* Argument passed by reference. The second location is always | |
1469 | valid for a BY_REF argument, and describes where the address | |
1470 | of the BY_REF argument should be placed. */ | |
1471 | by_ref | |
1472 | } loc_type; | |
1473 | ||
1474 | /* Information that depends on the location type. */ | |
1475 | union | |
1476 | { | |
1477 | /* Which register number to use. */ | |
1478 | int regno; | |
1479 | ||
1480 | /* The offset into the stack region. */ | |
1481 | int offset; | |
1482 | } loc_data; | |
1483 | ||
1484 | /* The length of contents covered by this location. If this is less | |
1485 | than the total length of the argument, then the second location | |
1486 | will be valid, and will describe where the rest of the argument | |
1487 | will go. */ | |
1488 | int c_length; | |
1489 | ||
1490 | /* The offset within CONTENTS for this part of the argument. Will | |
1491 | always be 0 for the first part. For the second part of the | |
1492 | argument, this might be the C_LENGTH value of the first part, | |
1493 | however, if we are passing a structure in two registers, and there's | |
1494 | is padding between the first and second field, then this offset | |
1495 | might be greater than the length of the first argument part. When | |
1496 | the second argument location is not holding part of the argument | |
1497 | value, but is instead holding the address of a reference argument, | |
1498 | then this offset will be set to 0. */ | |
1499 | int c_offset; | |
1500 | } argloc[2]; | |
1501 | }; | |
1502 | ||
1503 | /* Information about a set of registers being used for passing arguments as | |
1504 | part of a function call. The register set must be numerically | |
1505 | sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be | |
1506 | disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */ | |
1507 | ||
1508 | struct riscv_arg_reg | |
1509 | { | |
1510 | riscv_arg_reg (int first, int last) | |
1511 | : next_regnum (first), | |
1512 | last_regnum (last) | |
1513 | { | |
1514 | /* Nothing. */ | |
1515 | } | |
1516 | ||
1517 | /* The GDB register number to use in this set. */ | |
1518 | int next_regnum; | |
1519 | ||
1520 | /* The last GDB register number to use in this set. */ | |
1521 | int last_regnum; | |
1522 | }; | |
1523 | ||
1524 | /* Arguments can be passed as on stack arguments, or by reference. The | |
1525 | on stack arguments must be in a continuous region starting from $sp, | |
1526 | while the by reference arguments can be anywhere, but we'll put them | |
1527 | on the stack after (at higher address) the on stack arguments. | |
1528 | ||
1529 | This might not be the right approach to take. The ABI is clear that | |
1530 | an argument passed by reference can be modified by the callee, which | |
1531 | us placing the argument (temporarily) onto the stack will not achieve | |
1532 | (changes will be lost). There's also the possibility that very large | |
1533 | arguments could overflow the stack. | |
1534 | ||
1535 | This struct is used to track offset into these two areas for where | |
1536 | arguments are to be placed. */ | |
1537 | struct riscv_memory_offsets | |
1538 | { | |
1539 | riscv_memory_offsets () | |
1540 | : arg_offset (0), | |
1541 | ref_offset (0) | |
1542 | { | |
1543 | /* Nothing. */ | |
1544 | } | |
1545 | ||
1546 | /* Offset into on stack argument area. */ | |
1547 | int arg_offset; | |
1548 | ||
1549 | /* Offset into the pass by reference area. */ | |
1550 | int ref_offset; | |
1551 | }; | |
1552 | ||
1553 | /* Holds information about where arguments to a call will be placed. This | |
1554 | is updated as arguments are added onto the call, and can be used to | |
1555 | figure out where the next argument should be placed. */ | |
1556 | ||
1557 | struct riscv_call_info | |
1558 | { | |
1559 | riscv_call_info (struct gdbarch *gdbarch) | |
1560 | : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7), | |
1561 | float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7) | |
1562 | { | |
1563 | xlen = riscv_isa_xlen (gdbarch); | |
1564 | flen = riscv_isa_flen (gdbarch); | |
1565 | ||
1566 | /* Disable use of floating point registers if needed. */ | |
1567 | if (!riscv_has_fp_abi (gdbarch)) | |
1568 | float_regs.next_regnum = float_regs.last_regnum + 1; | |
1569 | } | |
1570 | ||
1571 | /* Track the memory areas used for holding in-memory arguments to a | |
1572 | call. */ | |
1573 | struct riscv_memory_offsets memory; | |
1574 | ||
1575 | /* Holds information about the next integer register to use for passing | |
1576 | an argument. */ | |
1577 | struct riscv_arg_reg int_regs; | |
1578 | ||
1579 | /* Holds information about the next floating point register to use for | |
1580 | passing an argument. */ | |
1581 | struct riscv_arg_reg float_regs; | |
1582 | ||
1583 | /* The XLEN and FLEN are copied in to this structure for convenience, and | |
1584 | are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */ | |
1585 | int xlen; | |
1586 | int flen; | |
1587 | }; | |
1588 | ||
1589 | /* Return the number of registers available for use as parameters in the | |
1590 | register set REG. Returned value can be 0 or more. */ | |
1591 | ||
1592 | static int | |
1593 | riscv_arg_regs_available (struct riscv_arg_reg *reg) | |
1594 | { | |
1595 | if (reg->next_regnum > reg->last_regnum) | |
1596 | return 0; | |
1597 | ||
1598 | return (reg->last_regnum - reg->next_regnum + 1); | |
1599 | } | |
1600 | ||
1601 | /* If there is at least one register available in the register set REG then | |
1602 | the next register from REG is assigned to LOC and the length field of | |
1603 | LOC is updated to LENGTH. The register set REG is updated to indicate | |
1604 | that the assigned register is no longer available and the function | |
1605 | returns true. | |
1606 | ||
1607 | If there are no registers available in REG then the function returns | |
1608 | false, and LOC and REG are unchanged. */ | |
1609 | ||
1610 | static bool | |
1611 | riscv_assign_reg_location (struct riscv_arg_info::location *loc, | |
1612 | struct riscv_arg_reg *reg, | |
1613 | int length, int offset) | |
1614 | { | |
1615 | if (reg->next_regnum <= reg->last_regnum) | |
1616 | { | |
1617 | loc->loc_type = riscv_arg_info::location::in_reg; | |
1618 | loc->loc_data.regno = reg->next_regnum; | |
1619 | reg->next_regnum++; | |
1620 | loc->c_length = length; | |
1621 | loc->c_offset = offset; | |
1622 | return true; | |
1623 | } | |
1624 | ||
1625 | return false; | |
1626 | } | |
1627 | ||
1628 | /* Assign LOC a location as the next stack parameter, and update MEMORY to | |
1629 | record that an area of stack has been used to hold the parameter | |
1630 | described by LOC. | |
1631 | ||
1632 | The length field of LOC is updated to LENGTH, the length of the | |
1633 | parameter being stored, and ALIGN is the alignment required by the | |
1634 | parameter, which will affect how memory is allocated out of MEMORY. */ | |
1635 | ||
1636 | static void | |
1637 | riscv_assign_stack_location (struct riscv_arg_info::location *loc, | |
1638 | struct riscv_memory_offsets *memory, | |
1639 | int length, int align) | |
1640 | { | |
1641 | loc->loc_type = riscv_arg_info::location::on_stack; | |
1642 | memory->arg_offset | |
1643 | = align_up (memory->arg_offset, align); | |
1644 | loc->loc_data.offset = memory->arg_offset; | |
1645 | memory->arg_offset += length; | |
1646 | loc->c_length = length; | |
1647 | ||
1648 | /* Offset is always 0, either we're the first location part, in which | |
1649 | case we're reading content from the start of the argument, or we're | |
1650 | passing the address of a reference argument, so 0. */ | |
1651 | loc->c_offset = 0; | |
1652 | } | |
1653 | ||
1654 | /* Update AINFO, which describes an argument that should be passed or | |
1655 | returned using the integer ABI. The argloc fields within AINFO are | |
1656 | updated to describe the location in which the argument will be passed to | |
1657 | a function, or returned from a function. | |
1658 | ||
1659 | The CINFO structure contains the ongoing call information, the holds | |
1660 | information such as which argument registers are remaining to be | |
1661 | assigned to parameter, and how much memory has been used by parameters | |
1662 | so far. | |
1663 | ||
1664 | By examining the state of CINFO a suitable location can be selected, | |
1665 | and assigned to AINFO. */ | |
1666 | ||
1667 | static void | |
1668 | riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo, | |
1669 | struct riscv_call_info *cinfo) | |
1670 | { | |
1671 | if (ainfo->length > (2 * cinfo->xlen)) | |
1672 | { | |
1673 | /* Argument is going to be passed by reference. */ | |
1674 | ainfo->argloc[0].loc_type | |
1675 | = riscv_arg_info::location::by_ref; | |
1676 | cinfo->memory.ref_offset | |
1677 | = align_up (cinfo->memory.ref_offset, ainfo->align); | |
1678 | ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset; | |
1679 | cinfo->memory.ref_offset += ainfo->length; | |
1680 | ainfo->argloc[0].c_length = ainfo->length; | |
1681 | ||
1682 | /* The second location for this argument is given over to holding the | |
1683 | address of the by-reference data. Pass 0 for the offset as this | |
1684 | is not part of the actual argument value. */ | |
1685 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
1686 | &cinfo->int_regs, | |
1687 | cinfo->xlen, 0)) | |
1688 | riscv_assign_stack_location (&ainfo->argloc[1], | |
1689 | &cinfo->memory, cinfo->xlen, | |
1690 | cinfo->xlen); | |
1691 | } | |
1692 | else | |
1693 | { | |
1694 | int len = (ainfo->length > cinfo->xlen) ? cinfo->xlen : ainfo->length; | |
1695 | ||
1696 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
1697 | &cinfo->int_regs, len, 0)) | |
1698 | riscv_assign_stack_location (&ainfo->argloc[0], | |
1699 | &cinfo->memory, len, ainfo->align); | |
1700 | ||
1701 | if (len < ainfo->length) | |
1702 | { | |
1703 | len = ainfo->length - len; | |
1704 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
1705 | &cinfo->int_regs, len, | |
1706 | cinfo->xlen)) | |
1707 | riscv_assign_stack_location (&ainfo->argloc[1], | |
1708 | &cinfo->memory, len, cinfo->xlen); | |
1709 | } | |
1710 | } | |
1711 | } | |
1712 | ||
1713 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO | |
1714 | is being passed with the floating point ABI. */ | |
1715 | ||
1716 | static void | |
1717 | riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo, | |
1718 | struct riscv_call_info *cinfo) | |
1719 | { | |
1720 | if (ainfo->length > cinfo->flen) | |
1721 | return riscv_call_arg_scalar_int (ainfo, cinfo); | |
1722 | else | |
1723 | { | |
1724 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
1725 | &cinfo->float_regs, | |
1726 | ainfo->length, 0)) | |
1727 | return riscv_call_arg_scalar_int (ainfo, cinfo); | |
1728 | } | |
1729 | } | |
1730 | ||
1731 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO | |
1732 | is a complex floating point argument, and is therefore handled | |
1733 | differently to other argument types. */ | |
1734 | ||
1735 | static void | |
1736 | riscv_call_arg_complex_float (struct riscv_arg_info *ainfo, | |
1737 | struct riscv_call_info *cinfo) | |
1738 | { | |
1739 | if (ainfo->length <= (2 * cinfo->flen) | |
1740 | && riscv_arg_regs_available (&cinfo->float_regs) >= 2) | |
1741 | { | |
1742 | bool result; | |
1743 | int len = ainfo->length / 2; | |
1744 | ||
1745 | result = riscv_assign_reg_location (&ainfo->argloc[0], | |
1746 | &cinfo->float_regs, len, len); | |
1747 | gdb_assert (result); | |
1748 | ||
1749 | result = riscv_assign_reg_location (&ainfo->argloc[1], | |
1750 | &cinfo->float_regs, len, len); | |
1751 | gdb_assert (result); | |
1752 | } | |
1753 | else | |
1754 | return riscv_call_arg_scalar_int (ainfo, cinfo); | |
1755 | } | |
1756 | ||
1757 | /* A structure used for holding information about a structure type within | |
1758 | the inferior program. The RiscV ABI has special rules for handling some | |
1759 | structures with a single field or with two fields. The counting of | |
1760 | fields here is done after flattening out all nested structures. */ | |
1761 | ||
1762 | class riscv_struct_info | |
1763 | { | |
1764 | public: | |
1765 | riscv_struct_info () | |
1766 | : m_number_of_fields (0), | |
1767 | m_types { nullptr, nullptr } | |
1768 | { | |
1769 | /* Nothing. */ | |
1770 | } | |
1771 | ||
1772 | /* Analyse TYPE descending into nested structures, count the number of | |
1773 | scalar fields and record the types of the first two fields found. */ | |
1774 | void analyse (struct type *type); | |
1775 | ||
1776 | /* The number of scalar fields found in the analysed type. This is | |
1777 | currently only accurate if the value returned is 0, 1, or 2 as the | |
1778 | analysis stops counting when the number of fields is 3. This is | |
1779 | because the RiscV ABI only has special cases for 1 or 2 fields, | |
1780 | anything else we just don't care about. */ | |
1781 | int number_of_fields () const | |
1782 | { return m_number_of_fields; } | |
1783 | ||
1784 | /* Return the type for scalar field INDEX within the analysed type. Will | |
1785 | return nullptr if there is no field at that index. Only INDEX values | |
1786 | 0 and 1 can be requested as the RiscV ABI only has special cases for | |
1787 | structures with 1 or 2 fields. */ | |
1788 | struct type *field_type (int index) const | |
1789 | { | |
1790 | gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0]))); | |
1791 | return m_types[index]; | |
1792 | } | |
1793 | ||
1794 | private: | |
1795 | /* The number of scalar fields found within the structure after recursing | |
1796 | into nested structures. */ | |
1797 | int m_number_of_fields; | |
1798 | ||
1799 | /* The types of the first two scalar fields found within the structure | |
1800 | after recursing into nested structures. */ | |
1801 | struct type *m_types[2]; | |
1802 | }; | |
1803 | ||
1804 | /* Analyse TYPE descending into nested structures, count the number of | |
1805 | scalar fields and record the types of the first two fields found. */ | |
1806 | ||
1807 | void | |
1808 | riscv_struct_info::analyse (struct type *type) | |
1809 | { | |
1810 | unsigned int count = TYPE_NFIELDS (type); | |
1811 | unsigned int i; | |
1812 | ||
1813 | for (i = 0; i < count; ++i) | |
1814 | { | |
1815 | if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS) | |
1816 | continue; | |
1817 | ||
1818 | struct type *field_type = TYPE_FIELD_TYPE (type, i); | |
1819 | field_type = check_typedef (field_type); | |
1820 | ||
1821 | switch (TYPE_CODE (field_type)) | |
1822 | { | |
1823 | case TYPE_CODE_STRUCT: | |
1824 | analyse (field_type); | |
1825 | break; | |
1826 | ||
1827 | default: | |
1828 | /* RiscV only flattens out structures. Anything else does not | |
1829 | need to be flattened, we just record the type, and when we | |
1830 | look at the analysis results we'll realise this is not a | |
1831 | structure we can special case, and pass the structure in | |
1832 | memory. */ | |
1833 | if (m_number_of_fields < 2) | |
1834 | m_types[m_number_of_fields] = field_type; | |
1835 | m_number_of_fields++; | |
1836 | break; | |
1837 | } | |
1838 | ||
1839 | /* RiscV only has special handling for structures with 1 or 2 scalar | |
1840 | fields, any more than that and the structure is just passed in | |
1841 | memory. We can safely drop out early when we find 3 or more | |
1842 | fields then. */ | |
1843 | ||
1844 | if (m_number_of_fields > 2) | |
1845 | return; | |
1846 | } | |
1847 | } | |
1848 | ||
1849 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO | |
1850 | is a structure. Small structures on RiscV have some special case | |
1851 | handling in order that the structure might be passed in register. | |
1852 | Larger structures are passed in memory. After assigning location | |
1853 | information to AINFO, CINFO will have been updated. */ | |
1854 | ||
1855 | static void | |
1856 | riscv_call_arg_struct (struct riscv_arg_info *ainfo, | |
1857 | struct riscv_call_info *cinfo) | |
1858 | { | |
1859 | if (riscv_arg_regs_available (&cinfo->float_regs) >= 1) | |
1860 | { | |
1861 | struct riscv_struct_info sinfo; | |
1862 | ||
1863 | sinfo.analyse (ainfo->type); | |
1864 | if (sinfo.number_of_fields () == 1 | |
1865 | && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_COMPLEX) | |
1866 | { | |
1867 | gdb_assert (TYPE_LENGTH (ainfo->type) | |
1868 | == TYPE_LENGTH (sinfo.field_type (0))); | |
1869 | return riscv_call_arg_complex_float (ainfo, cinfo); | |
1870 | } | |
1871 | ||
1872 | if (sinfo.number_of_fields () == 1 | |
1873 | && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT) | |
1874 | { | |
1875 | gdb_assert (TYPE_LENGTH (ainfo->type) | |
1876 | == TYPE_LENGTH (sinfo.field_type (0))); | |
1877 | return riscv_call_arg_scalar_float (ainfo, cinfo); | |
1878 | } | |
1879 | ||
1880 | if (sinfo.number_of_fields () == 2 | |
1881 | && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT | |
1882 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen | |
1883 | && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT | |
1884 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen | |
1885 | && riscv_arg_regs_available (&cinfo->float_regs) >= 2) | |
1886 | { | |
1887 | int len0, len1, offset; | |
1888 | ||
1889 | gdb_assert (TYPE_LENGTH (ainfo->type) <= (2 * cinfo->flen)); | |
1890 | ||
1891 | len0 = TYPE_LENGTH (sinfo.field_type (0)); | |
1892 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
1893 | &cinfo->float_regs, len0, 0)) | |
1894 | error (_("failed during argument setup")); | |
1895 | ||
1896 | len1 = TYPE_LENGTH (sinfo.field_type (1)); | |
1897 | offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1))); | |
1898 | gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type) | |
1899 | - TYPE_LENGTH (sinfo.field_type (0)))); | |
1900 | ||
1901 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
1902 | &cinfo->float_regs, | |
1903 | len1, offset)) | |
1904 | error (_("failed during argument setup")); | |
1905 | return; | |
1906 | } | |
1907 | ||
1908 | if (sinfo.number_of_fields () == 2 | |
1909 | && riscv_arg_regs_available (&cinfo->int_regs) >= 1 | |
1910 | && (TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT | |
1911 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen | |
1912 | && is_integral_type (sinfo.field_type (1)) | |
1913 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen)) | |
1914 | { | |
1915 | int len0, len1, offset; | |
1916 | ||
1917 | gdb_assert (TYPE_LENGTH (ainfo->type) | |
1918 | <= (cinfo->flen + cinfo->xlen)); | |
1919 | ||
1920 | len0 = TYPE_LENGTH (sinfo.field_type (0)); | |
1921 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
1922 | &cinfo->float_regs, len0, 0)) | |
1923 | error (_("failed during argument setup")); | |
1924 | ||
1925 | len1 = TYPE_LENGTH (sinfo.field_type (1)); | |
1926 | offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1))); | |
1927 | gdb_assert (len1 <= cinfo->xlen); | |
1928 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
1929 | &cinfo->int_regs, len1, offset)) | |
1930 | error (_("failed during argument setup")); | |
1931 | return; | |
1932 | } | |
1933 | ||
1934 | if (sinfo.number_of_fields () == 2 | |
1935 | && riscv_arg_regs_available (&cinfo->int_regs) >= 1 | |
1936 | && (is_integral_type (sinfo.field_type (0)) | |
1937 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen | |
1938 | && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT | |
1939 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen)) | |
1940 | { | |
1941 | int len0, len1, offset; | |
1942 | ||
1943 | gdb_assert (TYPE_LENGTH (ainfo->type) | |
1944 | <= (cinfo->flen + cinfo->xlen)); | |
1945 | ||
1946 | len0 = TYPE_LENGTH (sinfo.field_type (0)); | |
1947 | len1 = TYPE_LENGTH (sinfo.field_type (1)); | |
1948 | offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1))); | |
1949 | ||
1950 | gdb_assert (len0 <= cinfo->xlen); | |
1951 | gdb_assert (len1 <= cinfo->flen); | |
1952 | ||
1953 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
1954 | &cinfo->int_regs, len0, 0)) | |
1955 | error (_("failed during argument setup")); | |
1956 | ||
1957 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
1958 | &cinfo->float_regs, | |
1959 | len1, offset)) | |
1960 | error (_("failed during argument setup")); | |
1961 | ||
1962 | return; | |
1963 | } | |
1964 | } | |
1965 | ||
1966 | /* Non of the structure flattening cases apply, so we just pass using | |
1967 | the integer ABI. */ | |
1968 | ainfo->length = align_up (ainfo->length, cinfo->xlen); | |
1969 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
1970 | } | |
1971 | ||
1972 | /* Assign a location to call (or return) argument AINFO, the location is | |
1973 | selected from CINFO which holds information about what call argument | |
1974 | locations are available for use next. The TYPE is the type of the | |
1975 | argument being passed, this information is recorded into AINFO (along | |
1976 | with some additional information derived from the type). | |
1977 | ||
1978 | After assigning a location to AINFO, CINFO will have been updated. */ | |
1979 | ||
1980 | static void | |
1981 | riscv_arg_location (struct gdbarch *gdbarch, | |
1982 | struct riscv_arg_info *ainfo, | |
1983 | struct riscv_call_info *cinfo, | |
1984 | struct type *type) | |
1985 | { | |
1986 | ainfo->type = type; | |
1987 | ainfo->length = TYPE_LENGTH (ainfo->type); | |
1988 | ainfo->align = riscv_type_alignment (ainfo->type); | |
1989 | ainfo->contents = nullptr; | |
1990 | ||
1991 | switch (TYPE_CODE (ainfo->type)) | |
1992 | { | |
1993 | case TYPE_CODE_INT: | |
1994 | case TYPE_CODE_BOOL: | |
1995 | case TYPE_CODE_CHAR: | |
1996 | case TYPE_CODE_RANGE: | |
1997 | case TYPE_CODE_ENUM: | |
1998 | case TYPE_CODE_PTR: | |
1999 | if (ainfo->length <= cinfo->xlen) | |
2000 | { | |
2001 | ainfo->type = builtin_type (gdbarch)->builtin_long; | |
2002 | ainfo->length = cinfo->xlen; | |
2003 | } | |
2004 | else if (ainfo->length <= (2 * cinfo->xlen)) | |
2005 | { | |
2006 | ainfo->type = builtin_type (gdbarch)->builtin_long_long; | |
2007 | ainfo->length = 2 * cinfo->xlen; | |
2008 | } | |
2009 | ||
2010 | /* Recalculate the alignment requirement. */ | |
2011 | ainfo->align = riscv_type_alignment (ainfo->type); | |
2012 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
2013 | break; | |
2014 | ||
2015 | case TYPE_CODE_FLT: | |
2016 | riscv_call_arg_scalar_float (ainfo, cinfo); | |
2017 | break; | |
2018 | ||
2019 | case TYPE_CODE_COMPLEX: | |
2020 | riscv_call_arg_complex_float (ainfo, cinfo); | |
2021 | break; | |
2022 | ||
2023 | case TYPE_CODE_STRUCT: | |
2024 | riscv_call_arg_struct (ainfo, cinfo); | |
2025 | break; | |
2026 | ||
2027 | default: | |
2028 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
2029 | break; | |
2030 | } | |
2031 | } | |
2032 | ||
cab5bb9d AB |
2033 | /* Used for printing debug information about the call argument location in |
2034 | INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base | |
2035 | addresses for the location of pass-by-reference and | |
2036 | arguments-on-the-stack memory areas. */ | |
2037 | ||
dbbb1059 | 2038 | static void |
cab5bb9d | 2039 | riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch, |
dbbb1059 AB |
2040 | struct riscv_arg_info *info, |
2041 | CORE_ADDR sp_refs, CORE_ADDR sp_args) | |
2042 | { | |
cab5bb9d | 2043 | fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x", |
42ecac17 | 2044 | TYPE_SAFE_NAME (info->type), info->length, info->align); |
dbbb1059 AB |
2045 | switch (info->argloc[0].loc_type) |
2046 | { | |
2047 | case riscv_arg_info::location::in_reg: | |
cab5bb9d AB |
2048 | fprintf_unfiltered |
2049 | (stream, ", register %s", | |
2050 | gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno)); | |
dbbb1059 AB |
2051 | if (info->argloc[0].c_length < info->length) |
2052 | { | |
2053 | switch (info->argloc[1].loc_type) | |
2054 | { | |
2055 | case riscv_arg_info::location::in_reg: | |
cab5bb9d AB |
2056 | fprintf_unfiltered |
2057 | (stream, ", register %s", | |
2058 | gdbarch_register_name (gdbarch, | |
2059 | info->argloc[1].loc_data.regno)); | |
dbbb1059 AB |
2060 | break; |
2061 | ||
2062 | case riscv_arg_info::location::on_stack: | |
cab5bb9d AB |
2063 | fprintf_unfiltered (stream, ", on stack at offset 0x%x", |
2064 | info->argloc[1].loc_data.offset); | |
dbbb1059 AB |
2065 | break; |
2066 | ||
2067 | case riscv_arg_info::location::by_ref: | |
2068 | default: | |
2069 | /* The second location should never be a reference, any | |
2070 | argument being passed by reference just places its address | |
2071 | in the first location and is done. */ | |
2072 | error (_("invalid argument location")); | |
2073 | break; | |
2074 | } | |
2075 | ||
2076 | if (info->argloc[1].c_offset > info->argloc[0].c_length) | |
cab5bb9d AB |
2077 | fprintf_unfiltered (stream, " (offset 0x%x)", |
2078 | info->argloc[1].c_offset); | |
dbbb1059 AB |
2079 | } |
2080 | break; | |
2081 | ||
2082 | case riscv_arg_info::location::on_stack: | |
cab5bb9d AB |
2083 | fprintf_unfiltered (stream, ", on stack at offset 0x%x", |
2084 | info->argloc[0].loc_data.offset); | |
dbbb1059 AB |
2085 | break; |
2086 | ||
2087 | case riscv_arg_info::location::by_ref: | |
cab5bb9d AB |
2088 | fprintf_unfiltered |
2089 | (stream, ", by reference, data at offset 0x%x (%s)", | |
2090 | info->argloc[0].loc_data.offset, | |
2091 | core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset)); | |
dbbb1059 AB |
2092 | if (info->argloc[1].loc_type |
2093 | == riscv_arg_info::location::in_reg) | |
cab5bb9d AB |
2094 | fprintf_unfiltered |
2095 | (stream, ", address in register %s", | |
2096 | gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno)); | |
dbbb1059 AB |
2097 | else |
2098 | { | |
2099 | gdb_assert (info->argloc[1].loc_type | |
2100 | == riscv_arg_info::location::on_stack); | |
cab5bb9d AB |
2101 | fprintf_unfiltered |
2102 | (stream, ", address on stack at offset 0x%x (%s)", | |
2103 | info->argloc[1].loc_data.offset, | |
2104 | core_addr_to_string (sp_args + info->argloc[1].loc_data.offset)); | |
dbbb1059 AB |
2105 | } |
2106 | break; | |
2107 | ||
2108 | default: | |
89a3b63e | 2109 | gdb_assert_not_reached (_("unknown argument location type")); |
dbbb1059 AB |
2110 | } |
2111 | } | |
2112 | ||
2113 | /* Implement the push dummy call gdbarch callback. */ | |
2114 | ||
2115 | static CORE_ADDR | |
2116 | riscv_push_dummy_call (struct gdbarch *gdbarch, | |
2117 | struct value *function, | |
2118 | struct regcache *regcache, | |
2119 | CORE_ADDR bp_addr, | |
2120 | int nargs, | |
2121 | struct value **args, | |
2122 | CORE_ADDR sp, | |
2123 | int struct_return, | |
2124 | CORE_ADDR struct_addr) | |
2125 | { | |
2126 | int i; | |
2127 | CORE_ADDR sp_args, sp_refs; | |
2128 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
dbbb1059 AB |
2129 | |
2130 | struct riscv_arg_info *arg_info = | |
2131 | (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info)); | |
2132 | struct riscv_arg_info *info; | |
2133 | ||
2134 | struct riscv_call_info call_info (gdbarch); | |
2135 | ||
2136 | CORE_ADDR osp = sp; | |
2137 | ||
2138 | /* We'll use register $a0 if we're returning a struct. */ | |
2139 | if (struct_return) | |
2140 | ++call_info.int_regs.next_regnum; | |
2141 | ||
2142 | for (i = 0, info = &arg_info[0]; | |
2143 | i < nargs; | |
2144 | ++i, ++info) | |
2145 | { | |
2146 | struct value *arg_value; | |
2147 | struct type *arg_type; | |
2148 | ||
2149 | arg_value = args[i]; | |
2150 | arg_type = check_typedef (value_type (arg_value)); | |
2151 | ||
2152 | riscv_arg_location (gdbarch, info, &call_info, arg_type); | |
2153 | ||
2154 | if (info->type != arg_type) | |
2155 | arg_value = value_cast (info->type, arg_value); | |
2156 | info->contents = value_contents (arg_value); | |
2157 | } | |
2158 | ||
2159 | /* Adjust the stack pointer and align it. */ | |
2160 | sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT); | |
2161 | sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT); | |
2162 | ||
2163 | if (riscv_debug_infcall > 0) | |
2164 | { | |
2165 | fprintf_unfiltered (gdb_stdlog, "dummy call args:\n"); | |
2166 | fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n", | |
2167 | (riscv_has_fp_abi (gdbarch) ? "is" : "is not")); | |
2168 | fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n", | |
2169 | call_info.xlen, call_info.flen); | |
2170 | if (struct_return) | |
2171 | fprintf_unfiltered (gdb_stdlog, | |
2172 | "[*] struct return pointer in register $A0\n"); | |
2173 | for (i = 0; i < nargs; ++i) | |
2174 | { | |
2175 | struct riscv_arg_info *info = &arg_info [i]; | |
2176 | ||
2177 | fprintf_unfiltered (gdb_stdlog, "[%2d] ", i); | |
cab5bb9d | 2178 | riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args); |
dbbb1059 AB |
2179 | fprintf_unfiltered (gdb_stdlog, "\n"); |
2180 | } | |
2181 | if (call_info.memory.arg_offset > 0 | |
2182 | || call_info.memory.ref_offset > 0) | |
2183 | { | |
cab5bb9d AB |
2184 | fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n", |
2185 | core_addr_to_string (osp)); | |
dbbb1059 | 2186 | fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n", |
cab5bb9d | 2187 | call_info.memory.arg_offset); |
dbbb1059 | 2188 | fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n", |
cab5bb9d | 2189 | call_info.memory.ref_offset); |
fb294655 AB |
2190 | fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n", |
2191 | core_addr_to_string_nz (osp - sp)); | |
dbbb1059 AB |
2192 | } |
2193 | } | |
2194 | ||
2195 | /* Now load the argument into registers, or onto the stack. */ | |
2196 | ||
2197 | if (struct_return) | |
2198 | { | |
2199 | gdb_byte buf[sizeof (LONGEST)]; | |
2200 | ||
2201 | store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr); | |
b66f5587 | 2202 | regcache->cooked_write (RISCV_A0_REGNUM, buf); |
dbbb1059 AB |
2203 | } |
2204 | ||
2205 | for (i = 0; i < nargs; ++i) | |
2206 | { | |
2207 | CORE_ADDR dst; | |
2208 | int second_arg_length = 0; | |
2209 | const gdb_byte *second_arg_data; | |
2210 | struct riscv_arg_info *info = &arg_info [i]; | |
2211 | ||
2212 | gdb_assert (info->length > 0); | |
2213 | ||
2214 | switch (info->argloc[0].loc_type) | |
2215 | { | |
2216 | case riscv_arg_info::location::in_reg: | |
2217 | { | |
2218 | gdb_byte tmp [sizeof (ULONGEST)]; | |
2219 | ||
2220 | gdb_assert (info->argloc[0].c_length <= info->length); | |
2221 | memset (tmp, 0, sizeof (tmp)); | |
2222 | memcpy (tmp, info->contents, info->argloc[0].c_length); | |
b66f5587 | 2223 | regcache->cooked_write (info->argloc[0].loc_data.regno, tmp); |
dbbb1059 AB |
2224 | second_arg_length = |
2225 | ((info->argloc[0].c_length < info->length) | |
2226 | ? info->argloc[1].c_length : 0); | |
2227 | second_arg_data = info->contents + info->argloc[1].c_offset; | |
2228 | } | |
2229 | break; | |
2230 | ||
2231 | case riscv_arg_info::location::on_stack: | |
2232 | dst = sp_args + info->argloc[0].loc_data.offset; | |
2233 | write_memory (dst, info->contents, info->length); | |
2234 | second_arg_length = 0; | |
2235 | break; | |
2236 | ||
2237 | case riscv_arg_info::location::by_ref: | |
2238 | dst = sp_refs + info->argloc[0].loc_data.offset; | |
2239 | write_memory (dst, info->contents, info->length); | |
2240 | ||
2241 | second_arg_length = call_info.xlen; | |
2242 | second_arg_data = (gdb_byte *) &dst; | |
2243 | break; | |
2244 | ||
2245 | default: | |
89a3b63e | 2246 | gdb_assert_not_reached (_("unknown argument location type")); |
dbbb1059 AB |
2247 | } |
2248 | ||
2249 | if (second_arg_length > 0) | |
2250 | { | |
2251 | switch (info->argloc[1].loc_type) | |
2252 | { | |
2253 | case riscv_arg_info::location::in_reg: | |
2254 | { | |
2255 | gdb_byte tmp [sizeof (ULONGEST)]; | |
2256 | ||
8c49aa89 AB |
2257 | gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno) |
2258 | && second_arg_length <= call_info.flen) | |
2259 | || second_arg_length <= call_info.xlen); | |
dbbb1059 AB |
2260 | memset (tmp, 0, sizeof (tmp)); |
2261 | memcpy (tmp, second_arg_data, second_arg_length); | |
b66f5587 | 2262 | regcache->cooked_write (info->argloc[1].loc_data.regno, tmp); |
dbbb1059 AB |
2263 | } |
2264 | break; | |
2265 | ||
2266 | case riscv_arg_info::location::on_stack: | |
2267 | { | |
2268 | CORE_ADDR arg_addr; | |
2269 | ||
2270 | arg_addr = sp_args + info->argloc[1].loc_data.offset; | |
2271 | write_memory (arg_addr, second_arg_data, second_arg_length); | |
2272 | break; | |
2273 | } | |
2274 | ||
2275 | case riscv_arg_info::location::by_ref: | |
2276 | default: | |
2277 | /* The second location should never be a reference, any | |
2278 | argument being passed by reference just places its address | |
2279 | in the first location and is done. */ | |
2280 | error (_("invalid argument location")); | |
2281 | break; | |
2282 | } | |
2283 | } | |
2284 | } | |
2285 | ||
2286 | /* Set the dummy return value to bp_addr. | |
2287 | A dummy breakpoint will be setup to execute the call. */ | |
2288 | ||
2289 | if (riscv_debug_infcall > 0) | |
cab5bb9d AB |
2290 | fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n", |
2291 | core_addr_to_string (bp_addr)); | |
dbbb1059 AB |
2292 | regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr); |
2293 | ||
2294 | /* Finally, update the stack pointer. */ | |
2295 | ||
2296 | if (riscv_debug_infcall > 0) | |
cab5bb9d AB |
2297 | fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n", |
2298 | core_addr_to_string (sp)); | |
dbbb1059 AB |
2299 | regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp); |
2300 | ||
2301 | return sp; | |
2302 | } | |
2303 | ||
2304 | /* Implement the return_value gdbarch method. */ | |
2305 | ||
2306 | static enum return_value_convention | |
2307 | riscv_return_value (struct gdbarch *gdbarch, | |
2308 | struct value *function, | |
2309 | struct type *type, | |
2310 | struct regcache *regcache, | |
2311 | gdb_byte *readbuf, | |
2312 | const gdb_byte *writebuf) | |
2313 | { | |
dbbb1059 AB |
2314 | struct riscv_call_info call_info (gdbarch); |
2315 | struct riscv_arg_info info; | |
2316 | struct type *arg_type; | |
2317 | ||
2318 | arg_type = check_typedef (type); | |
2319 | riscv_arg_location (gdbarch, &info, &call_info, arg_type); | |
2320 | ||
2321 | if (riscv_debug_infcall > 0) | |
2322 | { | |
2323 | fprintf_unfiltered (gdb_stdlog, "riscv return value:\n"); | |
2324 | fprintf_unfiltered (gdb_stdlog, "[R] "); | |
cab5bb9d | 2325 | riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0); |
dbbb1059 AB |
2326 | fprintf_unfiltered (gdb_stdlog, "\n"); |
2327 | } | |
2328 | ||
2329 | if (readbuf != nullptr || writebuf != nullptr) | |
2330 | { | |
2331 | int regnum; | |
2332 | ||
2333 | switch (info.argloc[0].loc_type) | |
2334 | { | |
2335 | /* Return value in register(s). */ | |
2336 | case riscv_arg_info::location::in_reg: | |
2337 | { | |
2338 | regnum = info.argloc[0].loc_data.regno; | |
2339 | ||
2340 | if (readbuf) | |
dca08e1f | 2341 | regcache->cooked_read (regnum, readbuf); |
dbbb1059 AB |
2342 | |
2343 | if (writebuf) | |
b66f5587 | 2344 | regcache->cooked_write (regnum, writebuf); |
dbbb1059 AB |
2345 | |
2346 | /* A return value in register can have a second part in a | |
2347 | second register. */ | |
2348 | if (info.argloc[0].c_length < info.length) | |
2349 | { | |
2350 | switch (info.argloc[1].loc_type) | |
2351 | { | |
2352 | case riscv_arg_info::location::in_reg: | |
2353 | regnum = info.argloc[1].loc_data.regno; | |
2354 | ||
2355 | if (readbuf) | |
2356 | { | |
2357 | readbuf += info.argloc[1].c_offset; | |
dca08e1f | 2358 | regcache->cooked_read (regnum, readbuf); |
dbbb1059 AB |
2359 | } |
2360 | ||
2361 | if (writebuf) | |
2362 | { | |
2363 | writebuf += info.argloc[1].c_offset; | |
b66f5587 | 2364 | regcache->cooked_write (regnum, writebuf); |
dbbb1059 AB |
2365 | } |
2366 | break; | |
2367 | ||
2368 | case riscv_arg_info::location::by_ref: | |
2369 | case riscv_arg_info::location::on_stack: | |
2370 | default: | |
2371 | error (_("invalid argument location")); | |
2372 | break; | |
2373 | } | |
2374 | } | |
2375 | } | |
2376 | break; | |
2377 | ||
2378 | /* Return value by reference will have its address in A0. */ | |
2379 | case riscv_arg_info::location::by_ref: | |
2380 | { | |
b2970c23 | 2381 | ULONGEST addr; |
dbbb1059 AB |
2382 | |
2383 | regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM, | |
2384 | &addr); | |
2385 | if (readbuf != nullptr) | |
2386 | read_memory (addr, readbuf, info.length); | |
2387 | if (writebuf != nullptr) | |
2388 | write_memory (addr, writebuf, info.length); | |
2389 | } | |
2390 | break; | |
2391 | ||
2392 | case riscv_arg_info::location::on_stack: | |
2393 | default: | |
2394 | error (_("invalid argument location")); | |
2395 | break; | |
2396 | } | |
2397 | } | |
2398 | ||
2399 | switch (info.argloc[0].loc_type) | |
2400 | { | |
2401 | case riscv_arg_info::location::in_reg: | |
2402 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2403 | case riscv_arg_info::location::by_ref: | |
2404 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2405 | case riscv_arg_info::location::on_stack: | |
2406 | default: | |
2407 | error (_("invalid argument location")); | |
2408 | } | |
2409 | } | |
2410 | ||
2411 | /* Implement the frame_align gdbarch method. */ | |
2412 | ||
2413 | static CORE_ADDR | |
2414 | riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2415 | { | |
2416 | return align_down (addr, 16); | |
2417 | } | |
2418 | ||
2419 | /* Implement the unwind_pc gdbarch method. */ | |
2420 | ||
2421 | static CORE_ADDR | |
2422 | riscv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2423 | { | |
2424 | return frame_unwind_register_unsigned (next_frame, RISCV_PC_REGNUM); | |
2425 | } | |
2426 | ||
2427 | /* Implement the unwind_sp gdbarch method. */ | |
2428 | ||
2429 | static CORE_ADDR | |
2430 | riscv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2431 | { | |
2432 | return frame_unwind_register_unsigned (next_frame, RISCV_SP_REGNUM); | |
2433 | } | |
2434 | ||
2435 | /* Implement the dummy_id gdbarch method. */ | |
2436 | ||
2437 | static struct frame_id | |
2438 | riscv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
2439 | { | |
2440 | return frame_id_build (get_frame_register_signed (this_frame, RISCV_SP_REGNUM), | |
2441 | get_frame_pc (this_frame)); | |
2442 | } | |
2443 | ||
2444 | /* Generate, or return the cached frame cache for the RiscV frame | |
2445 | unwinder. */ | |
2446 | ||
2447 | static struct trad_frame_cache * | |
2448 | riscv_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2449 | { | |
2450 | CORE_ADDR pc; | |
2451 | CORE_ADDR start_addr; | |
2452 | CORE_ADDR stack_addr; | |
2453 | struct trad_frame_cache *this_trad_cache; | |
2454 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2455 | ||
2456 | if ((*this_cache) != NULL) | |
2457 | return (struct trad_frame_cache *) *this_cache; | |
2458 | this_trad_cache = trad_frame_cache_zalloc (this_frame); | |
2459 | (*this_cache) = this_trad_cache; | |
2460 | ||
2461 | trad_frame_set_reg_realreg (this_trad_cache, gdbarch_pc_regnum (gdbarch), | |
2462 | RISCV_RA_REGNUM); | |
2463 | ||
2464 | pc = get_frame_pc (this_frame); | |
2465 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
2466 | stack_addr = get_frame_register_signed (this_frame, RISCV_SP_REGNUM); | |
2467 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); | |
2468 | ||
2469 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
2470 | ||
2471 | return this_trad_cache; | |
2472 | } | |
2473 | ||
2474 | /* Implement the this_id callback for RiscV frame unwinder. */ | |
2475 | ||
2476 | static void | |
2477 | riscv_frame_this_id (struct frame_info *this_frame, | |
2478 | void **prologue_cache, | |
2479 | struct frame_id *this_id) | |
2480 | { | |
2481 | struct trad_frame_cache *info; | |
2482 | ||
2483 | info = riscv_frame_cache (this_frame, prologue_cache); | |
2484 | trad_frame_get_id (info, this_id); | |
2485 | } | |
2486 | ||
2487 | /* Implement the prev_register callback for RiscV frame unwinder. */ | |
2488 | ||
2489 | static struct value * | |
2490 | riscv_frame_prev_register (struct frame_info *this_frame, | |
2491 | void **prologue_cache, | |
2492 | int regnum) | |
2493 | { | |
2494 | struct trad_frame_cache *info; | |
2495 | ||
2496 | info = riscv_frame_cache (this_frame, prologue_cache); | |
2497 | return trad_frame_get_register (info, this_frame, regnum); | |
2498 | } | |
2499 | ||
2500 | /* Structure defining the RiscV normal frame unwind functions. Since we | |
2501 | are the fallback unwinder (DWARF unwinder is used first), we use the | |
2502 | default frame sniffer, which always accepts the frame. */ | |
2503 | ||
2504 | static const struct frame_unwind riscv_frame_unwind = | |
2505 | { | |
2506 | /*.type =*/ NORMAL_FRAME, | |
2507 | /*.stop_reason =*/ default_frame_unwind_stop_reason, | |
2508 | /*.this_id =*/ riscv_frame_this_id, | |
2509 | /*.prev_register =*/ riscv_frame_prev_register, | |
2510 | /*.unwind_data =*/ NULL, | |
2511 | /*.sniffer =*/ default_frame_sniffer, | |
2512 | /*.dealloc_cache =*/ NULL, | |
2513 | /*.prev_arch =*/ NULL, | |
2514 | }; | |
2515 | ||
2516 | /* Initialize the current architecture based on INFO. If possible, | |
2517 | re-use an architecture from ARCHES, which is a list of | |
2518 | architectures already created during this debugging session. | |
2519 | ||
2520 | Called e.g. at program startup, when reading a core file, and when | |
2521 | reading a binary file. */ | |
2522 | ||
2523 | static struct gdbarch * | |
2524 | riscv_gdbarch_init (struct gdbarch_info info, | |
2525 | struct gdbarch_list *arches) | |
2526 | { | |
2527 | struct gdbarch *gdbarch; | |
2528 | struct gdbarch_tdep *tdep; | |
2529 | struct gdbarch_tdep tmp_tdep; | |
dbbb1059 AB |
2530 | int i; |
2531 | ||
2532 | /* Ideally, we'd like to get as much information from the target for | |
2533 | things like register size, and whether the target has floating point | |
2534 | hardware. However, there are some things that the target can't tell | |
2535 | us, like, what ABI is being used. | |
2536 | ||
2537 | So, for now, we take as much information as possible from the ELF, | |
2538 | including things like register size, and FP hardware support, along | |
2539 | with information about the ABI. | |
2540 | ||
2541 | Information about this target is built up in TMP_TDEP, and then we | |
2542 | look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no | |
2543 | match is found we'll create a new gdbarch and copy TMP_TDEP over. */ | |
2544 | memset (&tmp_tdep, 0, sizeof (tmp_tdep)); | |
2545 | ||
2546 | if (info.abfd != NULL | |
2547 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
2548 | { | |
2549 | unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS]; | |
2550 | int e_flags = elf_elfheader (info.abfd)->e_flags; | |
2551 | ||
2552 | if (eclass == ELFCLASS32) | |
2553 | tmp_tdep.abi.fields.base_len = 1; | |
2554 | else if (eclass == ELFCLASS64) | |
2555 | tmp_tdep.abi.fields.base_len = 2; | |
2556 | else | |
2557 | internal_error (__FILE__, __LINE__, | |
2558 | _("unknown ELF header class %d"), eclass); | |
2559 | ||
2560 | if (e_flags & EF_RISCV_RVC) | |
27724bad | 2561 | tmp_tdep.core_features |= (1 << ('C' - 'A')); |
dbbb1059 AB |
2562 | |
2563 | if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE) | |
2564 | { | |
2565 | tmp_tdep.abi.fields.float_abi = 2; | |
2566 | tmp_tdep.core_features |= (1 << ('D' - 'A')); | |
2567 | tmp_tdep.core_features |= (1 << ('F' - 'A')); | |
2568 | } | |
2569 | else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE) | |
2570 | { | |
2571 | tmp_tdep.abi.fields.float_abi = 1; | |
2572 | tmp_tdep.core_features |= (1 << ('F' - 'A')); | |
2573 | } | |
2574 | } | |
2575 | else | |
2576 | { | |
2577 | const struct bfd_arch_info *binfo = info.bfd_arch_info; | |
2578 | ||
2579 | if (binfo->bits_per_word == 32) | |
2580 | tmp_tdep.abi.fields.base_len = 1; | |
2581 | else if (binfo->bits_per_word == 64) | |
2582 | tmp_tdep.abi.fields.base_len = 2; | |
2583 | else | |
2584 | internal_error (__FILE__, __LINE__, _("unknown bits_per_word %d"), | |
2585 | binfo->bits_per_word); | |
2586 | } | |
2587 | ||
2588 | /* Find a candidate among the list of pre-declared architectures. */ | |
2589 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
2590 | arches != NULL; | |
2591 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
2592 | if (gdbarch_tdep (arches->gdbarch)->abi.value == tmp_tdep.abi.value) | |
2593 | return arches->gdbarch; | |
2594 | ||
2595 | /* None found, so create a new architecture from the information provided. */ | |
2596 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof *tdep); | |
2597 | gdbarch = gdbarch_alloc (&info, tdep); | |
2598 | memcpy (tdep, &tmp_tdep, sizeof (tmp_tdep)); | |
2599 | ||
2600 | /* Target data types. */ | |
2601 | set_gdbarch_short_bit (gdbarch, 16); | |
2602 | set_gdbarch_int_bit (gdbarch, 32); | |
2603 | set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8); | |
2604 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2605 | set_gdbarch_float_bit (gdbarch, 32); | |
2606 | set_gdbarch_double_bit (gdbarch, 64); | |
2607 | set_gdbarch_long_double_bit (gdbarch, 128); | |
2608 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); | |
2609 | set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8); | |
2610 | set_gdbarch_char_signed (gdbarch, 0); | |
2611 | ||
2612 | /* Information about the target architecture. */ | |
2613 | set_gdbarch_return_value (gdbarch, riscv_return_value); | |
2614 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc); | |
2615 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind); | |
2616 | ||
2617 | /* Register architecture. */ | |
dbbb1059 | 2618 | set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1); |
dbbb1059 AB |
2619 | set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM); |
2620 | set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM); | |
2621 | set_gdbarch_ps_regnum (gdbarch, RISCV_FP_REGNUM); | |
2622 | set_gdbarch_deprecated_fp_regnum (gdbarch, RISCV_FP_REGNUM); | |
2623 | ||
2624 | /* Functions to supply register information. */ | |
2625 | set_gdbarch_register_name (gdbarch, riscv_register_name); | |
2626 | set_gdbarch_register_type (gdbarch, riscv_register_type); | |
2627 | set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info); | |
2628 | set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p); | |
2629 | ||
2630 | /* Functions to analyze frames. */ | |
dbbb1059 AB |
2631 | set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue); |
2632 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2633 | set_gdbarch_frame_align (gdbarch, riscv_frame_align); | |
2634 | ||
2635 | /* Functions to access frame data. */ | |
2636 | set_gdbarch_unwind_pc (gdbarch, riscv_unwind_pc); | |
2637 | set_gdbarch_unwind_sp (gdbarch, riscv_unwind_sp); | |
2638 | ||
2639 | /* Functions handling dummy frames. */ | |
2640 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
2641 | set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code); | |
2642 | set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call); | |
2643 | set_gdbarch_dummy_id (gdbarch, riscv_dummy_id); | |
2644 | ||
2645 | /* Frame unwinders. Use DWARF debug info if available, otherwise use our own | |
2646 | unwinder. */ | |
2647 | dwarf2_append_unwinders (gdbarch); | |
2648 | frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind); | |
2649 | ||
dbbb1059 AB |
2650 | for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) |
2651 | user_reg_add (gdbarch, riscv_register_aliases[i].name, | |
2652 | value_of_riscv_user_reg, &riscv_register_aliases[i].regnum); | |
2653 | ||
117a0e99 JW |
2654 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
2655 | gdbarch_init_osabi (info, gdbarch); | |
2656 | ||
dbbb1059 AB |
2657 | return gdbarch; |
2658 | } | |
2659 | ||
5c720ed8 JW |
2660 | /* This decodes the current instruction and determines the address of the |
2661 | next instruction. */ | |
2662 | ||
2663 | static CORE_ADDR | |
2664 | riscv_next_pc (struct regcache *regcache, CORE_ADDR pc) | |
2665 | { | |
2666 | struct gdbarch *gdbarch = regcache->arch (); | |
2667 | struct riscv_insn insn; | |
2668 | CORE_ADDR next_pc; | |
2669 | ||
2670 | insn.decode (gdbarch, pc); | |
2671 | next_pc = pc + insn.length (); | |
2672 | ||
2673 | if (insn.opcode () == riscv_insn::JAL) | |
2674 | next_pc = pc + insn.imm_signed (); | |
2675 | else if (insn.opcode () == riscv_insn::JALR) | |
2676 | { | |
2677 | LONGEST source; | |
2678 | regcache->cooked_read (insn.rs1 (), &source); | |
2679 | next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR) 0x1; | |
2680 | } | |
2681 | else if (insn.opcode () == riscv_insn::BEQ) | |
2682 | { | |
2683 | LONGEST src1, src2; | |
2684 | regcache->cooked_read (insn.rs1 (), &src1); | |
2685 | regcache->cooked_read (insn.rs2 (), &src2); | |
2686 | if (src1 == src2) | |
2687 | next_pc = pc + insn.imm_signed (); | |
2688 | } | |
2689 | else if (insn.opcode () == riscv_insn::BNE) | |
2690 | { | |
2691 | LONGEST src1, src2; | |
2692 | regcache->cooked_read (insn.rs1 (), &src1); | |
2693 | regcache->cooked_read (insn.rs2 (), &src2); | |
2694 | if (src1 != src2) | |
2695 | next_pc = pc + insn.imm_signed (); | |
2696 | } | |
2697 | else if (insn.opcode () == riscv_insn::BLT) | |
2698 | { | |
2699 | LONGEST src1, src2; | |
2700 | regcache->cooked_read (insn.rs1 (), &src1); | |
2701 | regcache->cooked_read (insn.rs2 (), &src2); | |
2702 | if (src1 < src2) | |
2703 | next_pc = pc + insn.imm_signed (); | |
2704 | } | |
2705 | else if (insn.opcode () == riscv_insn::BGE) | |
2706 | { | |
2707 | LONGEST src1, src2; | |
2708 | regcache->cooked_read (insn.rs1 (), &src1); | |
2709 | regcache->cooked_read (insn.rs2 (), &src2); | |
2710 | if (src1 >= src2) | |
2711 | next_pc = pc + insn.imm_signed (); | |
2712 | } | |
2713 | else if (insn.opcode () == riscv_insn::BLTU) | |
2714 | { | |
2715 | ULONGEST src1, src2; | |
2716 | regcache->cooked_read (insn.rs1 (), &src1); | |
2717 | regcache->cooked_read (insn.rs2 (), &src2); | |
2718 | if (src1 < src2) | |
2719 | next_pc = pc + insn.imm_signed (); | |
2720 | } | |
2721 | else if (insn.opcode () == riscv_insn::BGEU) | |
2722 | { | |
2723 | ULONGEST src1, src2; | |
2724 | regcache->cooked_read (insn.rs1 (), &src1); | |
2725 | regcache->cooked_read (insn.rs2 (), &src2); | |
2726 | if (src1 >= src2) | |
2727 | next_pc = pc + insn.imm_signed (); | |
2728 | } | |
2729 | ||
2730 | return next_pc; | |
2731 | } | |
2732 | ||
2733 | /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look | |
2734 | for the end of the sequence and put the breakpoint there. */ | |
2735 | ||
2736 | static bool | |
2737 | riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc, | |
2738 | CORE_ADDR *next_pc) | |
2739 | { | |
2740 | struct gdbarch *gdbarch = regcache->arch (); | |
2741 | struct riscv_insn insn; | |
2742 | CORE_ADDR cur_step_pc = pc; | |
2743 | CORE_ADDR last_addr = 0; | |
2744 | ||
2745 | /* First instruction has to be a load reserved. */ | |
2746 | insn.decode (gdbarch, cur_step_pc); | |
2747 | if (insn.opcode () != riscv_insn::LR) | |
2748 | return false; | |
2749 | cur_step_pc = cur_step_pc + insn.length (); | |
2750 | ||
2751 | /* Next instruction should be branch to exit. */ | |
2752 | insn.decode (gdbarch, cur_step_pc); | |
2753 | if (insn.opcode () != riscv_insn::BNE) | |
2754 | return false; | |
2755 | last_addr = cur_step_pc + insn.imm_signed (); | |
2756 | cur_step_pc = cur_step_pc + insn.length (); | |
2757 | ||
2758 | /* Next instruction should be store conditional. */ | |
2759 | insn.decode (gdbarch, cur_step_pc); | |
2760 | if (insn.opcode () != riscv_insn::SC) | |
2761 | return false; | |
2762 | cur_step_pc = cur_step_pc + insn.length (); | |
2763 | ||
2764 | /* Next instruction should be branch to start. */ | |
2765 | insn.decode (gdbarch, cur_step_pc); | |
2766 | if (insn.opcode () != riscv_insn::BNE) | |
2767 | return false; | |
2768 | if (pc != (cur_step_pc + insn.imm_signed ())) | |
2769 | return false; | |
2770 | cur_step_pc = cur_step_pc + insn.length (); | |
2771 | ||
2772 | /* We should now be at the end of the sequence. */ | |
2773 | if (cur_step_pc != last_addr) | |
2774 | return false; | |
2775 | ||
2776 | *next_pc = cur_step_pc; | |
2777 | return true; | |
2778 | } | |
2779 | ||
2780 | /* This is called just before we want to resume the inferior, if we want to | |
2781 | single-step it but there is no hardware or kernel single-step support. We | |
2782 | find the target of the coming instruction and breakpoint it. */ | |
2783 | ||
2784 | std::vector<CORE_ADDR> | |
2785 | riscv_software_single_step (struct regcache *regcache) | |
2786 | { | |
2787 | CORE_ADDR pc, next_pc; | |
2788 | ||
2789 | pc = regcache_read_pc (regcache); | |
2790 | ||
2791 | if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc)) | |
2792 | return {next_pc}; | |
2793 | ||
2794 | next_pc = riscv_next_pc (regcache, pc); | |
2795 | ||
2796 | return {next_pc}; | |
2797 | } | |
2798 | ||
dbbb1059 AB |
2799 | void |
2800 | _initialize_riscv_tdep (void) | |
2801 | { | |
2802 | gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL); | |
2803 | ||
dbbb1059 AB |
2804 | /* Add root prefix command for all "set debug riscv" and "show debug |
2805 | riscv" commands. */ | |
2806 | add_prefix_cmd ("riscv", no_class, set_debug_riscv_command, | |
2807 | _("RISC-V specific debug commands."), | |
2808 | &setdebugriscvcmdlist, "set debug riscv ", 0, | |
2809 | &setdebuglist); | |
2810 | ||
2811 | add_prefix_cmd ("riscv", no_class, show_debug_riscv_command, | |
2812 | _("RISC-V specific debug commands."), | |
2813 | &showdebugriscvcmdlist, "show debug riscv ", 0, | |
2814 | &showdebuglist); | |
2815 | ||
2816 | add_setshow_zuinteger_cmd ("infcall", class_maintenance, | |
2817 | &riscv_debug_infcall, _("\ | |
2818 | Set riscv inferior call debugging."), _("\ | |
2819 | Show riscv inferior call debugging."), _("\ | |
2820 | When non-zero, print debugging information for the riscv specific parts\n\ | |
2821 | of the inferior call mechanism."), | |
2822 | NULL, | |
2823 | show_riscv_debug_variable, | |
2824 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); | |
2825 | ||
2826 | /* Add root prefix command for all "set riscv" and "show riscv" commands. */ | |
2827 | add_prefix_cmd ("riscv", no_class, set_riscv_command, | |
2828 | _("RISC-V specific commands."), | |
2829 | &setriscvcmdlist, "set riscv ", 0, &setlist); | |
2830 | ||
2831 | add_prefix_cmd ("riscv", no_class, show_riscv_command, | |
2832 | _("RISC-V specific commands."), | |
2833 | &showriscvcmdlist, "show riscv ", 0, &showlist); | |
2834 | ||
2835 | ||
2836 | use_compressed_breakpoints = AUTO_BOOLEAN_AUTO; | |
2837 | add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class, | |
2838 | &use_compressed_breakpoints, | |
2839 | _("\ | |
2840 | Set debugger's use of compressed breakpoints."), _(" \ | |
2841 | Show debugger's use of compressed breakpoints."), _("\ | |
2842 | Debugging compressed code requires compressed breakpoints to be used. If\n \ | |
2843 | left to 'auto' then gdb will use them if $misa indicates the C extension\n \ | |
2844 | is supported. If that doesn't give the correct behavior, then this option\n\ | |
2845 | can be used."), | |
2846 | NULL, | |
2847 | show_use_compressed_breakpoints, | |
2848 | &setriscvcmdlist, | |
2849 | &showriscvcmdlist); | |
2850 | } |