[deliverable/binutils-gdb.git] / gdb / riscv-tdep.h

/* Target-dependent header for the RISC-V architecture, for GDB, the
   GNU Debugger.

   Copyright (C) 2018-2021 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef RISCV_TDEP_H
#define RISCV_TDEP_H

#include "arch/riscv.h"

/* RiscV register numbers.  */
enum
{
  RISCV_ZERO_REGNUM = 0,	/* Read-only register, always 0.  */
  RISCV_RA_REGNUM = 1,		/* Return Address.  */
  RISCV_SP_REGNUM = 2,		/* Stack Pointer.  */
  RISCV_GP_REGNUM = 3,		/* Global Pointer.  */
  RISCV_TP_REGNUM = 4,		/* Thread Pointer.  */
  RISCV_FP_REGNUM = 8,		/* Frame Pointer.  */
  RISCV_A0_REGNUM = 10,		/* First argument.  */
  RISCV_A1_REGNUM = 11,		/* Second argument.  */
  RISCV_PC_REGNUM = 32,		/* Program Counter.  */

  RISCV_NUM_INTEGER_REGS = 32,

  RISCV_FIRST_FP_REGNUM = 33,	/* First Floating Point Register */
  RISCV_FA0_REGNUM = 43,
  RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1,
  RISCV_LAST_FP_REGNUM = 64,	/* Last Floating Point Register */

  RISCV_FIRST_CSR_REGNUM = 65,  /* First CSR */
#define DECLARE_CSR(name, num, class, define_version, abort_version) \
  RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
  RISCV_LAST_CSR_REGNUM = 4160,
  RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM,

  RISCV_PRIV_REGNUM = 4161,

  RISCV_LAST_REGNUM = RISCV_PRIV_REGNUM
};

/* RiscV DWARF register numbers.  */
enum
{
  RISCV_DWARF_REGNUM_X0 = 0,
  RISCV_DWARF_REGNUM_X31 = 31,
  RISCV_DWARF_REGNUM_F0 = 32,
  RISCV_DWARF_REGNUM_F31 = 63,
  RISCV_DWARF_FIRST_CSR = 4096,
  RISCV_DWARF_LAST_CSR = 8191,
};

/* RISC-V specific per-architecture information.  */
struct gdbarch_tdep
{
  /* Features about the target hardware that impact how the gdbarch is
     configured.  Two gdbarch instances are compatible only if this field
     matches.  */
  struct riscv_gdbarch_features isa_features;

  /* Features about the abi that impact how the gdbarch is configured.  Two
     gdbarch instances are compatible only if this field matches.  */
  struct riscv_gdbarch_features abi_features;

  /* ISA-specific data types.  */
  struct type *riscv_fpreg_d_type = nullptr;

  /* Use for tracking unknown CSRs in the target description.
     UNKNOWN_CSRS_FIRST_REGNUM is the number assigned to the first unknown
     CSR.  All other unknown CSRs will be assigned sequential numbers after
     this, with UNKNOWN_CSRS_COUNT being the total number of unknown CSRs.  */
  int unknown_csrs_first_regnum = -1;
  int unknown_csrs_count = 0;

  /* Some targets (QEMU) are reporting three registers twice in the target
     description they send.  These three register numbers, when not set to
     -1, are for the duplicate copies of these registers.  */
  int duplicate_fflags_regnum = -1;
  int duplicate_frm_regnum = -1;
  int duplicate_fcsr_regnum = -1;

};


/* Return the width in bytes  of the general purpose registers for GDBARCH.
   Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
   RV128.  */
extern int riscv_isa_xlen (struct gdbarch *gdbarch);

/* Return the width in bytes of the hardware floating point registers for
   GDBARCH.  If this architecture has no floating point registers, then
   return 0.  Possible values are 4, 8, or 16 for depending on which of
   single, double or quad floating point support is available.  */
extern int riscv_isa_flen (struct gdbarch *gdbarch);

/* Return the width in bytes of the general purpose register abi for
   GDBARCH.  This can be equal to, or less than RISCV_ISA_XLEN and reflects
   how the binary was compiled rather than the hardware that is available.
   It is possible that a binary compiled for RV32 is being run on an RV64
   target, in which case the isa xlen is 8-bytes, and the abi xlen is
   4-bytes.  This will impact how inferior functions are called.  */
extern int riscv_abi_xlen (struct gdbarch *gdbarch);

/* Return the width in bytes of the floating point register abi for
   GDBARCH.  This reflects how the binary was compiled rather than the
   hardware that is available.  It is possible that a binary is compiled
   for single precision floating point, and then run on a target with
   double precision floating point.  A return value of 0 indicates that no
   floating point abi is in use (floating point arguments will be passed
   in integer registers) other possible return value are 4, 8, or 16 as
   with RISCV_ISA_FLEN.  */
extern int riscv_abi_flen (struct gdbarch *gdbarch);

/* Return true if GDBARCH is using the embedded x-regs abi, that is the
   target only has 16 x-registers, which includes a reduced number of
   argument registers.  */
extern bool riscv_abi_embedded (struct gdbarch *gdbarch);

/* Single step based on where the current instruction will take us.  */
extern std::vector<CORE_ADDR> riscv_software_single_step
  (struct regcache *regcache);

/* Supply register REGNUM from the buffer REGS (length LEN) into
   REGCACHE.  REGSET describes the layout of the buffer.  If REGNUM is -1
   then all registers described by REGSET are supplied.

   The register RISCV_ZERO_REGNUM should not be described by REGSET,
   however, this register (which always has the value 0) will be supplied
   by this function if requested.

   The registers RISCV_CSR_FFLAGS_REGNUM and RISCV_CSR_FRM_REGNUM should
   not be described by REGSET, however, these register will be provided if
   requested assuming either:
   (a) REGCACHE already contains the value of RISCV_CSR_FCSR_REGNUM, or
   (b) REGSET describes the location of RISCV_CSR_FCSR_REGNUM in the REGS
       buffer.

   This function can be used as the supply function for either x-regs or
   f-regs when loading corefiles, and doesn't care which abi is currently
   in use.  */

extern void riscv_supply_regset (const struct regset *regset,
				  struct regcache *regcache, int regnum,
				  const void *regs, size_t len);

/* The names of the RISC-V target description features.  */
extern const char *riscv_feature_name_csr;

#endif /* RISCV_TDEP_H */
Commit	Line	Data
06ab9219 TT	1	/* Target-dependent header for the RISC-V architecture, for GDB, the
06ab9219 TT	2	GNU Debugger.
dbbb1059	3
3666a048	4	Copyright (C) 2018-2021 Free Software Foundation, Inc.
dbbb1059	5
dbbb1059 AB	6	This file is part of GDB.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 3 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	20
	21	#ifndef RISCV_TDEP_H
	22	#define RISCV_TDEP_H
	23
b5ffee31 AB	24	#include "arch/riscv.h"
b5ffee31 AB	25
dbbb1059 AB	26	/* RiscV register numbers. */
	27	enum
	28	{
	29	RISCV_ZERO_REGNUM = 0, /* Read-only register, always 0. */
	30	RISCV_RA_REGNUM = 1, /* Return Address. */
	31	RISCV_SP_REGNUM = 2, /* Stack Pointer. */
	32	RISCV_GP_REGNUM = 3, /* Global Pointer. */
	33	RISCV_TP_REGNUM = 4, /* Thread Pointer. */
	34	RISCV_FP_REGNUM = 8, /* Frame Pointer. */
	35	RISCV_A0_REGNUM = 10, /* First argument. */
	36	RISCV_A1_REGNUM = 11, /* Second argument. */
	37	RISCV_PC_REGNUM = 32, /* Program Counter. */
	38
78a3b0fa AB	39	RISCV_NUM_INTEGER_REGS = 32,
78a3b0fa AB	40
dbbb1059 AB	41	RISCV_FIRST_FP_REGNUM = 33, /* First Floating Point Register */
	42	RISCV_FA0_REGNUM = 43,
	43	RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1,
	44	RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */
	45
	46	RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */
8f595e9b	47	#define DECLARE_CSR(name, num, class, define_version, abort_version) \
06ab9219	48	RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
dbbb1059 AB	49	#include "opcode/riscv-opc.h"
	50	#undef DECLARE_CSR
	51	RISCV_LAST_CSR_REGNUM = 4160,
ce73f310	52	RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM,
dbbb1059 AB	53
	54	RISCV_PRIV_REGNUM = 4161,
	55
	56	RISCV_LAST_REGNUM = RISCV_PRIV_REGNUM
	57	};
	58
fb44d95a AB	59	/* RiscV DWARF register numbers. */
	60	enum
	61	{
	62	RISCV_DWARF_REGNUM_X0 = 0,
	63	RISCV_DWARF_REGNUM_X31 = 31,
	64	RISCV_DWARF_REGNUM_F0 = 32,
	65	RISCV_DWARF_REGNUM_F31 = 63,
550820e1 AB	66	RISCV_DWARF_FIRST_CSR = 4096,
550820e1 AB	67	RISCV_DWARF_LAST_CSR = 8191,
fb44d95a AB	68	};
fb44d95a AB	69
dbbb1059 AB	70	/* RISC-V specific per-architecture information. */
	71	struct gdbarch_tdep
	72	{
113b7b81 AB	73	/* Features about the target hardware that impact how the gdbarch is
	74	configured. Two gdbarch instances are compatible only if this field
	75	matches. */
	76	struct riscv_gdbarch_features isa_features;
	77
	78	/* Features about the abi that impact how the gdbarch is configured. Two
	79	gdbarch instances are compatible only if this field matches. */
	80	struct riscv_gdbarch_features abi_features;
270b9329 JW	81
270b9329 JW	82	/* ISA-specific data types. */
b5ffee31	83	struct type *riscv_fpreg_d_type = nullptr;
2e52d038 AB	84
	85	/* Use for tracking unknown CSRs in the target description.
	86	UNKNOWN_CSRS_FIRST_REGNUM is the number assigned to the first unknown
	87	CSR. All other unknown CSRs will be assigned sequential numbers after
	88	this, with UNKNOWN_CSRS_COUNT being the total number of unknown CSRs. */
	89	int unknown_csrs_first_regnum = -1;
	90	int unknown_csrs_count = 0;
	91
	92	/* Some targets (QEMU) are reporting three registers twice in the target
	93	description they send. These three register numbers, when not set to
	94	-1, are for the duplicate copies of these registers. */
	95	int duplicate_fflags_regnum = -1;
	96	int duplicate_frm_regnum = -1;
	97	int duplicate_fcsr_regnum = -1;
	98
dbbb1059 AB	99	};
dbbb1059 AB	100
8a613826 JW	101
	102	/* Return the width in bytes of the general purpose registers for GDBARCH.
	103	Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
	104	RV128. */
411baa47 JW	105	extern int riscv_isa_xlen (struct gdbarch *gdbarch);
411baa47 JW	106
113b7b81 AB	107	/* Return the width in bytes of the hardware floating point registers for
	108	GDBARCH. If this architecture has no floating point registers, then
	109	return 0. Possible values are 4, 8, or 16 for depending on which of
	110	single, double or quad floating point support is available. */
8a613826 JW	111	extern int riscv_isa_flen (struct gdbarch *gdbarch);
8a613826 JW	112
113b7b81 AB	113	/* Return the width in bytes of the general purpose register abi for
	114	GDBARCH. This can be equal to, or less than RISCV_ISA_XLEN and reflects
	115	how the binary was compiled rather than the hardware that is available.
	116	It is possible that a binary compiled for RV32 is being run on an RV64
	117	target, in which case the isa xlen is 8-bytes, and the abi xlen is
	118	4-bytes. This will impact how inferior functions are called. */
	119	extern int riscv_abi_xlen (struct gdbarch *gdbarch);
	120
	121	/* Return the width in bytes of the floating point register abi for
	122	GDBARCH. This reflects how the binary was compiled rather than the
	123	hardware that is available. It is possible that a binary is compiled
	124	for single precision floating point, and then run on a target with
	125	double precision floating point. A return value of 0 indicates that no
	126	floating point abi is in use (floating point arguments will be passed
	127	in integer registers) other possible return value are 4, 8, or 16 as
	128	with RISCV_ISA_FLEN. */
	129	extern int riscv_abi_flen (struct gdbarch *gdbarch);
	130
25428040 AB	131	/* Return true if GDBARCH is using the embedded x-regs abi, that is the
	132	target only has 16 x-registers, which includes a reduced number of
	133	argument registers. */
	134	extern bool riscv_abi_embedded (struct gdbarch *gdbarch);
	135
5c720ed8	136	/* Single step based on where the current instruction will take us. */
06ab9219 TT	137	extern std::vector<CORE_ADDR> riscv_software_single_step
06ab9219 TT	138	(struct regcache *regcache);
5c720ed8	139
6a9ad81c AB	140	/* Supply register REGNUM from the buffer REGS (length LEN) into
	141	REGCACHE. REGSET describes the layout of the buffer. If REGNUM is -1
	142	then all registers described by REGSET are supplied.
	143
	144	The register RISCV_ZERO_REGNUM should not be described by REGSET,
	145	however, this register (which always has the value 0) will be supplied
	146	by this function if requested.
	147
	148	The registers RISCV_CSR_FFLAGS_REGNUM and RISCV_CSR_FRM_REGNUM should
	149	not be described by REGSET, however, these register will be provided if
	150	requested assuming either:
	151	(a) REGCACHE already contains the value of RISCV_CSR_FCSR_REGNUM, or
	152	(b) REGSET describes the location of RISCV_CSR_FCSR_REGNUM in the REGS
	153	buffer.
	154
	155	This function can be used as the supply function for either x-regs or
	156	f-regs when loading corefiles, and doesn't care which abi is currently
	157	in use. */
	158
	159	extern void riscv_supply_regset (const struct regset *regset,
	160	struct regcache *regcache, int regnum,
	161	const void *regs, size_t len);
	162
d782d24b AB	163	/* The names of the RISC-V target description features. */
	164	extern const char *riscv_feature_name_csr;
	165
dbbb1059	166	#endif /* RISCV_TDEP_H */