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* gdb.dwarf2/dw2-error.exp: Pass test name to "file" test.
[deliverable/binutils-gdb.git] / gdb / rl78-tdep.c
CommitLineData
9058f767
KB		 1/* Target-dependent code for the Renesas RL78 for GDB, the GNU debugger.
2
28e7fd62 3 Copyright (C) 2011-2013 Free Software Foundation, Inc.
9058f767
KB		 4
5 Contributed by Red Hat, Inc.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22#include "defs.h"
23#include "arch-utils.h"
24#include "prologue-value.h"
25#include "target.h"
26#include "regcache.h"
27#include "opcode/rl78.h"
28#include "dis-asm.h"
29#include "gdbtypes.h"
30#include "frame.h"
31#include "frame-unwind.h"
32#include "frame-base.h"
33#include "value.h"
34#include "gdbcore.h"
35#include "dwarf2-frame.h"
c47a44f4 36#include "reggroups.h"
9058f767
KB		 37
38#include "elf/rl78.h"
39#include "elf-bfd.h"
40
41/* Register Banks. */
42
43enum
44{
45 RL78_BANK0 = 0,
46 RL78_BANK1 = 1,
47 RL78_BANK2 = 2,
48 RL78_BANK3 = 3,
49 RL78_NUMBANKS = 4,
50 RL78_REGS_PER_BANK = 8
51};
52
53/* Register Numbers. */
54
55enum
56{
57 /* All general purpose registers are 8 bits wide. */
c47a44f4
KB		 58 RL78_RAW_BANK0_R0_REGNUM = 0,
59 RL78_RAW_BANK0_R1_REGNUM,
60 RL78_RAW_BANK0_R2_REGNUM,
61 RL78_RAW_BANK0_R3_REGNUM,
62 RL78_RAW_BANK0_R4_REGNUM,
63 RL78_RAW_BANK0_R5_REGNUM,
64 RL78_RAW_BANK0_R6_REGNUM,
65 RL78_RAW_BANK0_R7_REGNUM,
66
67 RL78_RAW_BANK1_R0_REGNUM,
68 RL78_RAW_BANK1_R1_REGNUM,
69 RL78_RAW_BANK1_R2_REGNUM,
70 RL78_RAW_BANK1_R3_REGNUM,
71 RL78_RAW_BANK1_R4_REGNUM,
72 RL78_RAW_BANK1_R5_REGNUM,
73 RL78_RAW_BANK1_R6_REGNUM,
74 RL78_RAW_BANK1_R7_REGNUM,
75
76 RL78_RAW_BANK2_R0_REGNUM,
77 RL78_RAW_BANK2_R1_REGNUM,
78 RL78_RAW_BANK2_R2_REGNUM,
79 RL78_RAW_BANK2_R3_REGNUM,
80 RL78_RAW_BANK2_R4_REGNUM,
81 RL78_RAW_BANK2_R5_REGNUM,
82 RL78_RAW_BANK2_R6_REGNUM,
83 RL78_RAW_BANK2_R7_REGNUM,
84
85 RL78_RAW_BANK3_R0_REGNUM,
86 RL78_RAW_BANK3_R1_REGNUM,
87 RL78_RAW_BANK3_R2_REGNUM,
88 RL78_RAW_BANK3_R3_REGNUM,
89 RL78_RAW_BANK3_R4_REGNUM,
90 RL78_RAW_BANK3_R5_REGNUM,
91 RL78_RAW_BANK3_R6_REGNUM,
92 RL78_RAW_BANK3_R7_REGNUM,
93
94 RL78_PSW_REGNUM, /* 8 bits */
95 RL78_ES_REGNUM, /* 8 bits */
96 RL78_CS_REGNUM, /* 8 bits */
97 RL78_PC_REGNUM, /* 20 bits; we'll use 32 bits for it. */
98
99 /* Fixed address SFRs (some of those above are SFRs too.) */
100 RL78_SPL_REGNUM, /* 8 bits; lower half of SP */
101 RL78_SPH_REGNUM, /* 8 bits; upper half of SP */
102 RL78_PMC_REGNUM, /* 8 bits */
103 RL78_MEM_REGNUM, /* 8 bits ?? */
104
105 RL78_NUM_REGS,
106
107 /* Pseudo registers. */
108 RL78_SP_REGNUM = RL78_NUM_REGS,
109
110 RL78_X_REGNUM,
111 RL78_A_REGNUM,
112 RL78_C_REGNUM,
113 RL78_B_REGNUM,
114 RL78_E_REGNUM,
115 RL78_D_REGNUM,
116 RL78_L_REGNUM,
117 RL78_H_REGNUM,
118
119 RL78_AX_REGNUM,
120 RL78_BC_REGNUM,
121 RL78_DE_REGNUM,
122 RL78_HL_REGNUM,
123
124 RL78_BANK0_R0_REGNUM,
9058f767
KB		 125 RL78_BANK0_R1_REGNUM,
126 RL78_BANK0_R2_REGNUM,
127 RL78_BANK0_R3_REGNUM,
128 RL78_BANK0_R4_REGNUM,
129 RL78_BANK0_R5_REGNUM,
130 RL78_BANK0_R6_REGNUM,
131 RL78_BANK0_R7_REGNUM,
132
133 RL78_BANK1_R0_REGNUM,
134 RL78_BANK1_R1_REGNUM,
135 RL78_BANK1_R2_REGNUM,
136 RL78_BANK1_R3_REGNUM,
137 RL78_BANK1_R4_REGNUM,
138 RL78_BANK1_R5_REGNUM,
139 RL78_BANK1_R6_REGNUM,
140 RL78_BANK1_R7_REGNUM,
141
142 RL78_BANK2_R0_REGNUM,
143 RL78_BANK2_R1_REGNUM,
144 RL78_BANK2_R2_REGNUM,
145 RL78_BANK2_R3_REGNUM,
146 RL78_BANK2_R4_REGNUM,
147 RL78_BANK2_R5_REGNUM,
148 RL78_BANK2_R6_REGNUM,
149 RL78_BANK2_R7_REGNUM,
150
151 RL78_BANK3_R0_REGNUM,
152 RL78_BANK3_R1_REGNUM,
153 RL78_BANK3_R2_REGNUM,
154 RL78_BANK3_R3_REGNUM,
155 RL78_BANK3_R4_REGNUM,
156 RL78_BANK3_R5_REGNUM,
157 RL78_BANK3_R6_REGNUM,
158 RL78_BANK3_R7_REGNUM,
159
c47a44f4 160 RL78_BANK0_RP0_REGNUM,
9058f767
KB		 161 RL78_BANK0_RP1_REGNUM,
162 RL78_BANK0_RP2_REGNUM,
163 RL78_BANK0_RP3_REGNUM,
164
165 RL78_BANK1_RP0_REGNUM,
166 RL78_BANK1_RP1_REGNUM,
167 RL78_BANK1_RP2_REGNUM,
168 RL78_BANK1_RP3_REGNUM,
169
170 RL78_BANK2_RP0_REGNUM,
171 RL78_BANK2_RP1_REGNUM,
172 RL78_BANK2_RP2_REGNUM,
173 RL78_BANK2_RP3_REGNUM,
174
175 RL78_BANK3_RP0_REGNUM,
176 RL78_BANK3_RP1_REGNUM,
177 RL78_BANK3_RP2_REGNUM,
178 RL78_BANK3_RP3_REGNUM,
179
9058f767
KB		 180 RL78_NUM_TOTAL_REGS,
181 RL78_NUM_PSEUDO_REGS = RL78_NUM_TOTAL_REGS - RL78_NUM_REGS
182};
183
184/* Architecture specific data. */
185
186struct gdbarch_tdep
187{
188 /* The ELF header flags specify the multilib used. */
189 int elf_flags;
190
191 struct type *rl78_void,
192 *rl78_uint8,
193 *rl78_int8,
194 *rl78_uint16,
195 *rl78_int16,
196 *rl78_uint32,
197 *rl78_int32,
198 *rl78_data_pointer,
199 *rl78_code_pointer;
200};
201
202/* This structure holds the results of a prologue analysis. */
203
204struct rl78_prologue
205{
206 /* The offset from the frame base to the stack pointer --- always
207 zero or negative.
208
209 Calling this a "size" is a bit misleading, but given that the
210 stack grows downwards, using offsets for everything keeps one
211 from going completely sign-crazy: you never change anything's
212 sign for an ADD instruction; always change the second operand's
213 sign for a SUB instruction; and everything takes care of
214 itself. */
215 int frame_size;
216
217 /* Non-zero if this function has initialized the frame pointer from
218 the stack pointer, zero otherwise. */
219 int has_frame_ptr;
220
221 /* If has_frame_ptr is non-zero, this is the offset from the frame
222 base to where the frame pointer points. This is always zero or
223 negative. */
224 int frame_ptr_offset;
225
226 /* The address of the first instruction at which the frame has been
227 set up and the arguments are where the debug info says they are
228 --- as best as we can tell. */
229 CORE_ADDR prologue_end;
230
231 /* reg_offset[R] is the offset from the CFA at which register R is
232 saved, or 1 if register R has not been saved. (Real values are
233 always zero or negative.) */
234 int reg_offset[RL78_NUM_TOTAL_REGS];
235};
236
237/* Implement the "register_type" gdbarch method. */
238
239static struct type *
240rl78_register_type (struct gdbarch *gdbarch, int reg_nr)
241{
242 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
243
244 if (reg_nr == RL78_PC_REGNUM)
245 return tdep->rl78_code_pointer;
246 else if (reg_nr <= RL78_MEM_REGNUM
c47a44f4
KB		 247 || (RL78_X_REGNUM <= reg_nr && reg_nr <= RL78_H_REGNUM)
248 || (RL78_BANK0_R0_REGNUM <= reg_nr
249 && reg_nr <= RL78_BANK3_R7_REGNUM))
9058f767
KB		 250 return tdep->rl78_int8;
251 else
252 return tdep->rl78_data_pointer;
253}
254
255/* Implement the "register_name" gdbarch method. */
256
257static const char *
258rl78_register_name (struct gdbarch *gdbarch, int regnr)
259{
260 static const char *const reg_names[] =
261 {
c47a44f4
KB		 262 "", /* bank0_r0 */
263 "", /* bank0_r1 */
264 "", /* bank0_r2 */
265 "", /* bank0_r3 */
266 "", /* bank0_r4 */
267 "", /* bank0_r5 */
268 "", /* bank0_r6 */
269 "", /* bank0_r7 */
270
271 "", /* bank1_r0 */
272 "", /* bank1_r1 */
273 "", /* bank1_r2 */
274 "", /* bank1_r3 */
275 "", /* bank1_r4 */
276 "", /* bank1_r5 */
277 "", /* bank1_r6 */
278 "", /* bank1_r7 */
279
280 "", /* bank2_r0 */
281 "", /* bank2_r1 */
282 "", /* bank2_r2 */
283 "", /* bank2_r3 */
284 "", /* bank2_r4 */
285 "", /* bank2_r5 */
286 "", /* bank2_r6 */
287 "", /* bank2_r7 */
288
289 "", /* bank3_r0 */
290 "", /* bank3_r1 */
291 "", /* bank3_r2 */
292 "", /* bank3_r3 */
293 "", /* bank3_r4 */
294 "", /* bank3_r5 */
295 "", /* bank3_r6 */
296 "", /* bank3_r7 */
297
298 "psw",
299 "es",
300 "cs",
301 "pc",
302
303 "", /* spl */
304 "", /* sph */
305 "pmc",
306 "mem",
307
308 "sp",
309
310 "x",
311 "a",
312 "c",
313 "b",
314 "e",
315 "d",
316 "l",
317 "h",
318
319 "ax",
320 "bc",
321 "de",
322 "hl",
323
9058f767
KB		 324 "bank0_r0",
325 "bank0_r1",
326 "bank0_r2",
327 "bank0_r3",
328 "bank0_r4",
329 "bank0_r5",
330 "bank0_r6",
331 "bank0_r7",
332
333 "bank1_r0",
334 "bank1_r1",
335 "bank1_r2",
336 "bank1_r3",
337 "bank1_r4",
338 "bank1_r5",
339 "bank1_r6",
340 "bank1_r7",
341
342 "bank2_r0",
343 "bank2_r1",
344 "bank2_r2",
345 "bank2_r3",
346 "bank2_r4",
347 "bank2_r5",
348 "bank2_r6",
349 "bank2_r7",
350
351 "bank3_r0",
352 "bank3_r1",
353 "bank3_r2",
354 "bank3_r3",
355 "bank3_r4",
356 "bank3_r5",
357 "bank3_r6",
358 "bank3_r7",
359
9058f767
KB		 360 "bank0_rp0",
361 "bank0_rp1",
362 "bank0_rp2",
363 "bank0_rp3",
364
365 "bank1_rp0",
366 "bank1_rp1",
367 "bank1_rp2",
368 "bank1_rp3",
369
370 "bank2_rp0",
371 "bank2_rp1",
372 "bank2_rp2",
373 "bank2_rp3",
374
375 "bank3_rp0",
376 "bank3_rp1",
377 "bank3_rp2",
c47a44f4
KB		 378 "bank3_rp3"
379 };
9058f767 380
c47a44f4
KB		 381 return reg_names[regnr];
382}
9058f767 383
c47a44f4 384/* Implement the "register_reggroup_p" gdbarch method. */
9058f767 385
c47a44f4
KB		 386static int
387rl78_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
388 struct reggroup *group)
389{
390 if (group == all_reggroup)
391 return 1;
9058f767 392
c47a44f4
KB		 393 /* All other registers are saved and restored. */
394 if (group == save_reggroup || group == restore_reggroup)
395 {
396 if (regnum < RL78_NUM_REGS)
397 return 1;
398 else
399 return 0;
400 }
401
402 if ((RL78_BANK0_R0_REGNUM <= regnum && regnum <= RL78_BANK3_R7_REGNUM)
403 || regnum == RL78_ES_REGNUM
404 || regnum == RL78_CS_REGNUM
405 || regnum == RL78_SPL_REGNUM
406 || regnum == RL78_SPH_REGNUM
407 || regnum == RL78_PMC_REGNUM
408 || regnum == RL78_MEM_REGNUM
409 || (RL78_BANK0_RP0_REGNUM <= regnum && regnum <= RL78_BANK3_RP3_REGNUM))
410 return group == system_reggroup;
411
412 return group == general_reggroup;
9058f767
KB		 413}
414
415/* Strip bits to form an instruction address. (When fetching a
416 32-bit address from the stack, the high eight bits are garbage.
417 This function strips off those unused bits.) */
418
419static CORE_ADDR
420rl78_make_instruction_address (CORE_ADDR addr)
421{
422 return addr & 0xffffff;
423}
424
425/* Set / clear bits necessary to make a data address. */
426
427static CORE_ADDR
428rl78_make_data_address (CORE_ADDR addr)
429{
430 return (addr & 0xffff) | 0xf0000;
431}
432
433/* Implement the "pseudo_register_read" gdbarch method. */
434
435static enum register_status
436rl78_pseudo_register_read (struct gdbarch *gdbarch,
437 struct regcache *regcache,
438 int reg, gdb_byte *buffer)
439{
440 enum register_status status;
441
c47a44f4
KB		 442 if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
443 {
444 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
445 + (reg - RL78_BANK0_R0_REGNUM);
446
447 status = regcache_raw_read (regcache, raw_regnum, buffer);
448 }
449 else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
9058f767
KB		 450 {
451 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
c47a44f4 452 + RL78_RAW_BANK0_R0_REGNUM;
9058f767
KB		 453
454 status = regcache_raw_read (regcache, raw_regnum, buffer);
455 if (status == REG_VALID)
456 status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
457 }
458 else if (reg == RL78_SP_REGNUM)
459 {
460 status = regcache_raw_read (regcache, RL78_SPL_REGNUM, buffer);
461 if (status == REG_VALID)
462 status = regcache_raw_read (regcache, RL78_SPH_REGNUM, buffer + 1);
463 }
464 else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
465 {
466 ULONGEST psw;
467
468 status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
469 if (status == REG_VALID)
470 {
471 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
472 int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
c47a44f4 473 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 474 + (reg - RL78_X_REGNUM);
475 status = regcache_raw_read (regcache, raw_regnum, buffer);
476 }
477 }
478 else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
479 {
480 ULONGEST psw;
481
482 status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
483 if (status == REG_VALID)
484 {
485 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
486 int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
c47a44f4 487 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 488 + 2 * (reg - RL78_AX_REGNUM);
489 status = regcache_raw_read (regcache, raw_regnum, buffer);
490 if (status == REG_VALID)
491 status = regcache_raw_read (regcache, raw_regnum + 1,
492 buffer + 1);
493 }
494 }
495 else
496 gdb_assert_not_reached ("invalid pseudo register number");
497 return status;
498}
499
500/* Implement the "pseudo_register_write" gdbarch method. */
501
502static void
503rl78_pseudo_register_write (struct gdbarch *gdbarch,
504 struct regcache *regcache,
505 int reg, const gdb_byte *buffer)
506{
c47a44f4
KB		 507 if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
508 {
509 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
510 + (reg - RL78_BANK0_R0_REGNUM);
511
512 regcache_raw_write (regcache, raw_regnum, buffer);
513 }
514 else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
9058f767
KB		 515 {
516 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
c47a44f4 517 + RL78_RAW_BANK0_R0_REGNUM;
9058f767
KB		 518
519 regcache_raw_write (regcache, raw_regnum, buffer);
520 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
521 }
522 else if (reg == RL78_SP_REGNUM)
523 {
524 regcache_raw_write (regcache, RL78_SPL_REGNUM, buffer);
525 regcache_raw_write (regcache, RL78_SPH_REGNUM, buffer + 1);
526 }
527 else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
528 {
529 ULONGEST psw;
530 int bank;
531 int raw_regnum;
532
533 regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
534 bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
535 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
c47a44f4 536 raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 537 + (reg - RL78_X_REGNUM);
538 regcache_raw_write (regcache, raw_regnum, buffer);
539 }
540 else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
541 {
542 ULONGEST psw;
543 int bank, raw_regnum;
544
545 regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
546 bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
547 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
c47a44f4 548 raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 549 + 2 * (reg - RL78_AX_REGNUM);
550 regcache_raw_write (regcache, raw_regnum, buffer);
551 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
552 }
553 else
554 gdb_assert_not_reached ("invalid pseudo register number");
555}
556
557/* Implement the "breakpoint_from_pc" gdbarch method. */
558
693be288 559static const gdb_byte *
9058f767
KB		 560rl78_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
561 int *lenptr)
562{
563 /* The documented BRK instruction is actually a two byte sequence,
564 {0x61, 0xcc}, but instructions may be as short as one byte.
565 Correspondence with Renesas revealed that the one byte sequence
566 0xff is used when a one byte breakpoint instruction is required. */
567 static gdb_byte breakpoint[] = { 0xff };
568
569 *lenptr = sizeof breakpoint;
570 return breakpoint;
571}
572
573/* Define a "handle" struct for fetching the next opcode. */
574
575struct rl78_get_opcode_byte_handle
576{
577 CORE_ADDR pc;
578};
579
580/* Fetch a byte on behalf of the opcode decoder. HANDLE contains
581 the memory address of the next byte to fetch. If successful,
582 the address in the handle is updated and the byte fetched is
583 returned as the value of the function. If not successful, -1
584 is returned. */
585
586static int
587rl78_get_opcode_byte (void *handle)
588{
589 struct rl78_get_opcode_byte_handle *opcdata = handle;
590 int status;
591 gdb_byte byte;
592
593 status = target_read_memory (opcdata->pc, &byte, 1);
594 if (status == 0)
595 {
596 opcdata->pc += 1;
597 return byte;
598 }
599 else
600 return -1;
601}
602
603/* Function for finding saved registers in a 'struct pv_area'; this
604 function is passed to pv_area_scan.
605
606 If VALUE is a saved register, ADDR says it was saved at a constant
607 offset from the frame base, and SIZE indicates that the whole
608 register was saved, record its offset. */
609
610static void
611check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size,
612 pv_t value)
613{
614 struct rl78_prologue *result = (struct rl78_prologue *) result_untyped;
615
616 if (value.kind == pvk_register
617 && value.k == 0
618 && pv_is_register (addr, RL78_SP_REGNUM)
f5656ead 619 && size == register_size (target_gdbarch (), value.reg))
9058f767
KB		 620 result->reg_offset[value.reg] = addr.k;
621}
622
623/* Analyze a prologue starting at START_PC, going no further than
624 LIMIT_PC. Fill in RESULT as appropriate. */
625
626static void
627rl78_analyze_prologue (CORE_ADDR start_pc,
628 CORE_ADDR limit_pc, struct rl78_prologue *result)
629{
630 CORE_ADDR pc, next_pc;
631 int rn;
632 pv_t reg[RL78_NUM_TOTAL_REGS];
633 struct pv_area *stack;
634 struct cleanup *back_to;
635 CORE_ADDR after_last_frame_setup_insn = start_pc;
636 int bank = 0;
637
638 memset (result, 0, sizeof (*result));
639
640 for (rn = 0; rn < RL78_NUM_TOTAL_REGS; rn++)
641 {
642 reg[rn] = pv_register (rn, 0);
643 result->reg_offset[rn] = 1;
644 }
645
f5656ead 646 stack = make_pv_area (RL78_SP_REGNUM, gdbarch_addr_bit (target_gdbarch ()));
9058f767
KB		 647 back_to = make_cleanup_free_pv_area (stack);
648
649 /* The call instruction has saved the return address on the stack. */
650 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -4);
651 pv_area_store (stack, reg[RL78_SP_REGNUM], 4, reg[RL78_PC_REGNUM]);
652
653 pc = start_pc;
654 while (pc < limit_pc)
655 {
656 int bytes_read;
657 struct rl78_get_opcode_byte_handle opcode_handle;
658 RL78_Opcode_Decoded opc;
659
660 opcode_handle.pc = pc;
661 bytes_read = rl78_decode_opcode (pc, &opc, rl78_get_opcode_byte,
662 &opcode_handle);
663 next_pc = pc + bytes_read;
664
665 if (opc.id == RLO_sel)
666 {
667 bank = opc.op[1].addend;
668 }
669 else if (opc.id == RLO_mov
670 && opc.op[0].type == RL78_Operand_PreDec
671 && opc.op[0].reg == RL78_Reg_SP
672 && opc.op[1].type == RL78_Operand_Register)
673 {
674 int rsrc = (bank * RL78_REGS_PER_BANK)
675 + 2 * (opc.op[1].reg - RL78_Reg_AX);
676
677 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
678 pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc]);
679 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
680 pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc + 1]);
681 after_last_frame_setup_insn = next_pc;
682 }
683 else if (opc.id == RLO_sub
684 && opc.op[0].type == RL78_Operand_Register
685 && opc.op[0].reg == RL78_Reg_SP
686 && opc.op[1].type == RL78_Operand_Immediate)
687 {
688 int addend = opc.op[1].addend;
689
690 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM],
691 -addend);
692 after_last_frame_setup_insn = next_pc;
693 }
694 else
695 {
696 /* Terminate the prologue scan. */
697 break;
698 }
699
700 pc = next_pc;
701 }
702
703 /* Is the frame size (offset, really) a known constant? */
704 if (pv_is_register (reg[RL78_SP_REGNUM], RL78_SP_REGNUM))
705 result->frame_size = reg[RL78_SP_REGNUM].k;
706
707 /* Record where all the registers were saved. */
708 pv_area_scan (stack, check_for_saved, (void *) result);
709
710 result->prologue_end = after_last_frame_setup_insn;
711
712 do_cleanups (back_to);
713}
714
715/* Implement the "addr_bits_remove" gdbarch method. */
716
717static CORE_ADDR
718rl78_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
719{
720 return addr & 0xffffff;
721}
722
723/* Implement the "address_to_pointer" gdbarch method. */
724
725static void
726rl78_address_to_pointer (struct gdbarch *gdbarch,
727 struct type *type, gdb_byte *buf, CORE_ADDR addr)
728{
729 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
730
731 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
732 addr & 0xffffff);
733}
734
735/* Implement the "pointer_to_address" gdbarch method. */
736
737static CORE_ADDR
738rl78_pointer_to_address (struct gdbarch *gdbarch,
739 struct type *type, const gdb_byte *buf)
740{
741 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
742 CORE_ADDR addr
743 = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
744
745 /* Is it a code address? */
746 if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC
747 || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD
748 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))
749 || TYPE_LENGTH (type) == 4)
750 return rl78_make_instruction_address (addr);
751 else
752 return rl78_make_data_address (addr);
753}
754
755/* Implement the "skip_prologue" gdbarch method. */
756
757static CORE_ADDR
758rl78_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
759{
e4569f1e 760 const char *name;
9058f767
KB		 761 CORE_ADDR func_addr, func_end;
762 struct rl78_prologue p;
763
764 /* Try to find the extent of the function that contains PC. */
765 if (!find_pc_partial_function (pc, &name, &func_addr, &func_end))
766 return pc;
767
768 rl78_analyze_prologue (pc, func_end, &p);
769 return p.prologue_end;
770}
771
772/* Implement the "unwind_pc" gdbarch method. */
773
774static CORE_ADDR
775rl78_unwind_pc (struct gdbarch *arch, struct frame_info *next_frame)
776{
777 return rl78_addr_bits_remove
778 (arch, frame_unwind_register_unsigned (next_frame,
779 RL78_PC_REGNUM));
780}
781
782/* Implement the "unwind_sp" gdbarch method. */
783
784static CORE_ADDR
785rl78_unwind_sp (struct gdbarch *arch, struct frame_info *next_frame)
786{
787 return frame_unwind_register_unsigned (next_frame, RL78_SP_REGNUM);
788}
789
790/* Given a frame described by THIS_FRAME, decode the prologue of its
791 associated function if there is not cache entry as specified by
792 THIS_PROLOGUE_CACHE. Save the decoded prologue in the cache and
793 return that struct as the value of this function. */
794
795static struct rl78_prologue *
796rl78_analyze_frame_prologue (struct frame_info *this_frame,
797 void **this_prologue_cache)
798{
799 if (!*this_prologue_cache)
800 {
801 CORE_ADDR func_start, stop_addr;
802
803 *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct rl78_prologue);
804
805 func_start = get_frame_func (this_frame);
806 stop_addr = get_frame_pc (this_frame);
807
808 /* If we couldn't find any function containing the PC, then
809 just initialize the prologue cache, but don't do anything. */
810 if (!func_start)
811 stop_addr = func_start;
812
813 rl78_analyze_prologue (func_start, stop_addr, *this_prologue_cache);
814 }
815
816 return *this_prologue_cache;
817}
818
819/* Given a frame and a prologue cache, return this frame's base. */
820
821static CORE_ADDR
822rl78_frame_base (struct frame_info *this_frame, void **this_prologue_cache)
823{
824 struct rl78_prologue *p
825 = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
826 CORE_ADDR sp = get_frame_register_unsigned (this_frame, RL78_SP_REGNUM);
827
828 return rl78_make_data_address (sp - p->frame_size);
829}
830
831/* Implement the "frame_this_id" method for unwinding frames. */
832
833static void
834rl78_this_id (struct frame_info *this_frame,
835 void **this_prologue_cache, struct frame_id *this_id)
836{
837 *this_id = frame_id_build (rl78_frame_base (this_frame,
838 this_prologue_cache),
839 get_frame_func (this_frame));
840}
841
842/* Implement the "frame_prev_register" method for unwinding frames. */
843
844static struct value *
845rl78_prev_register (struct frame_info *this_frame,
846 void **this_prologue_cache, int regnum)
847{
848 struct rl78_prologue *p
849 = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
850 CORE_ADDR frame_base = rl78_frame_base (this_frame, this_prologue_cache);
851
852 if (regnum == RL78_SP_REGNUM)
853 return frame_unwind_got_constant (this_frame, regnum, frame_base);
854
855 else if (regnum == RL78_SPL_REGNUM)
856 return frame_unwind_got_constant (this_frame, regnum,
857 (frame_base & 0xff));
858
859 else if (regnum == RL78_SPH_REGNUM)
860 return frame_unwind_got_constant (this_frame, regnum,
861 ((frame_base >> 8) & 0xff));
862
863 /* If prologue analysis says we saved this register somewhere,
864 return a description of the stack slot holding it. */
865 else if (p->reg_offset[regnum] != 1)
866 {
867 struct value *rv =
868 frame_unwind_got_memory (this_frame, regnum,
869 frame_base + p->reg_offset[regnum]);
870
871 if (regnum == RL78_PC_REGNUM)
872 {
873 ULONGEST pc = rl78_make_instruction_address (value_as_long (rv));
874
875 return frame_unwind_got_constant (this_frame, regnum, pc);
876 }
877 return rv;
878 }
879
880 /* Otherwise, presume we haven't changed the value of this
881 register, and get it from the next frame. */
882 else
883 return frame_unwind_got_register (this_frame, regnum, regnum);
884}
885
886static const struct frame_unwind rl78_unwind =
887{
888 NORMAL_FRAME,
889 default_frame_unwind_stop_reason,
890 rl78_this_id,
891 rl78_prev_register,
892 NULL,
893 default_frame_sniffer
894};
895
896/* Implement the "dwarf_reg_to_regnum" gdbarch method. */
897
898static int
899rl78_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
900{
901 if (0 <= reg && reg <= 31)
902 {
903 if ((reg & 1) == 0)
904 /* Map even registers to their 16-bit counterparts. This
905 is usually what is required from the DWARF info. */
906 return (reg >> 1) + RL78_BANK0_RP0_REGNUM;
907 else
908 return reg;
909 }
910 else if (reg == 32)
911 return RL78_SP_REGNUM;
912 else if (reg == 33)
913 return RL78_PC_REGNUM;
914 else
915 internal_error (__FILE__, __LINE__,
916 _("Undefined dwarf2 register mapping of reg %d"),
917 reg);
918}
919
c47a44f4
KB		 920/* Implement the `register_sim_regno' gdbarch method. */
921
922static int
923rl78_register_sim_regno (struct gdbarch *gdbarch, int regnum)
924{
925 gdb_assert (regnum < RL78_NUM_REGS);
926
927 /* So long as regnum is in [0, RL78_NUM_REGS), it's valid. We
928 just want to override the default here which disallows register
929 numbers which have no names. */
930 return regnum;
931}
932
9058f767
KB		 933/* Implement the "return_value" gdbarch method. */
934
935static enum return_value_convention
936rl78_return_value (struct gdbarch *gdbarch,
6a3a010b 937 struct value *function,
9058f767
KB		 938 struct type *valtype,
939 struct regcache *regcache,
940 gdb_byte *readbuf, const gdb_byte *writebuf)
941{
942 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
943 ULONGEST valtype_len = TYPE_LENGTH (valtype);
944
945 if (valtype_len > 8)
946 return RETURN_VALUE_STRUCT_CONVENTION;
947
948 if (readbuf)
949 {
950 ULONGEST u;
c47a44f4 951 int argreg = RL78_RAW_BANK1_R0_REGNUM;
9058f767
KB		 952 int offset = 0;
953
954 while (valtype_len > 0)
955 {
956 regcache_cooked_read_unsigned (regcache, argreg, &u);
957 store_unsigned_integer (readbuf + offset, 1, byte_order, u);
958 valtype_len -= 1;
959 offset += 1;
960 argreg++;
961 }
962 }
963
964 if (writebuf)
965 {
966 ULONGEST u;
c47a44f4 967 int argreg = RL78_RAW_BANK1_R0_REGNUM;
9058f767
KB		 968 int offset = 0;
969
970 while (valtype_len > 0)
971 {
972 u = extract_unsigned_integer (writebuf + offset, 1, byte_order);
973 regcache_cooked_write_unsigned (regcache, argreg, u);
974 valtype_len -= 1;
975 offset += 1;
976 argreg++;
977 }
978 }
979
980 return RETURN_VALUE_REGISTER_CONVENTION;
981}
982
983
984/* Implement the "frame_align" gdbarch method. */
985
986static CORE_ADDR
987rl78_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
988{
989 return rl78_make_data_address (align_down (sp, 2));
990}
991
992
993/* Implement the "dummy_id" gdbarch method. */
994
995static struct frame_id
996rl78_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
997{
998 return
999 frame_id_build (rl78_make_data_address
1000 (get_frame_register_unsigned
1001 (this_frame, RL78_SP_REGNUM)),
1002 get_frame_pc (this_frame));
1003}
1004
1005
1006/* Implement the "push_dummy_call" gdbarch method. */
1007
1008static CORE_ADDR
1009rl78_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1010 struct regcache *regcache, CORE_ADDR bp_addr,
1011 int nargs, struct value **args, CORE_ADDR sp,
1012 int struct_return, CORE_ADDR struct_addr)
1013{
1014 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1015 gdb_byte buf[4];
1016 int i;
1017
1018 /* Push arguments in reverse order. */
1019 for (i = nargs - 1; i >= 0; i--)
1020 {
1021 struct type *value_type = value_enclosing_type (args[i]);
1022 int len = TYPE_LENGTH (value_type);
1023 int container_len = (len + 1) & ~1;
9058f767
KB		 1024
1025 sp -= container_len;
1026 write_memory (rl78_make_data_address (sp),
1027 value_contents_all (args[i]), len);
1028 }
1029
1030 /* Store struct value address. */
1031 if (struct_return)
1032 {
1033 store_unsigned_integer (buf, 2, byte_order, struct_addr);
1034 sp -= 2;
1035 write_memory (rl78_make_data_address (sp), buf, 2);
1036 }
1037
1038 /* Store return address. */
1039 sp -= 4;
1040 store_unsigned_integer (buf, 4, byte_order, bp_addr);
1041 write_memory (rl78_make_data_address (sp), buf, 4);
1042
1043 /* Finally, update the stack pointer... */
1044 regcache_cooked_write_unsigned (regcache, RL78_SP_REGNUM, sp);
1045
1046 /* DWARF2/GCC uses the stack address *before* the function call as a
1047 frame's CFA. */
1048 return rl78_make_data_address (sp + 4);
1049}
1050
1051/* Allocate and initialize a gdbarch object. */
1052
1053static struct gdbarch *
1054rl78_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1055{
1056 struct gdbarch *gdbarch;
1057 struct gdbarch_tdep *tdep;
1058 int elf_flags;
1059
1060 /* Extract the elf_flags if available. */
1061 if (info.abfd != NULL
1062 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1063 elf_flags = elf_elfheader (info.abfd)->e_flags;
1064 else
1065 elf_flags = 0;
1066
1067
1068 /* Try to find the architecture in the list of already defined
1069 architectures. */
1070 for (arches = gdbarch_list_lookup_by_info (arches, &info);
1071 arches != NULL;
1072 arches = gdbarch_list_lookup_by_info (arches->next, &info))
1073 {
1074 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
1075 continue;
1076
1077 return arches->gdbarch;
1078 }
1079
1080 /* None found, create a new architecture from the information
1081 provided. */
1082 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
1083 gdbarch = gdbarch_alloc (&info, tdep);
1084 tdep->elf_flags = elf_flags;
1085
1086 /* Initialize types. */
1087 tdep->rl78_void = arch_type (gdbarch, TYPE_CODE_VOID, 1, "void");
1088 tdep->rl78_uint8 = arch_integer_type (gdbarch, 8, 1, "uint8_t");
1089 tdep->rl78_int8 = arch_integer_type (gdbarch, 8, 0, "int8_t");
1090 tdep->rl78_uint16 = arch_integer_type (gdbarch, 16, 1, "uint16_t");
1091 tdep->rl78_int16 = arch_integer_type (gdbarch, 16, 0, "int16_t");
1092 tdep->rl78_uint32 = arch_integer_type (gdbarch, 32, 1, "uint32_t");
1093 tdep->rl78_int32 = arch_integer_type (gdbarch, 32, 0, "int32_t");
1094
1095 tdep->rl78_data_pointer
1096 = arch_type (gdbarch, TYPE_CODE_PTR, 16 / TARGET_CHAR_BIT,
1097 xstrdup ("rl78_data_addr_t"));
1098 TYPE_TARGET_TYPE (tdep->rl78_data_pointer) = tdep->rl78_void;
1099 TYPE_UNSIGNED (tdep->rl78_data_pointer) = 1;
1100
1101 tdep->rl78_code_pointer
1102 = arch_type (gdbarch, TYPE_CODE_PTR, 32 / TARGET_CHAR_BIT,
1103 xstrdup ("rl78_code_addr_t"));
1104 TYPE_TARGET_TYPE (tdep->rl78_code_pointer) = tdep->rl78_void;
1105 TYPE_UNSIGNED (tdep->rl78_code_pointer) = 1;
1106
1107 /* Registers. */
1108 set_gdbarch_num_regs (gdbarch, RL78_NUM_REGS);
1109 set_gdbarch_num_pseudo_regs (gdbarch, RL78_NUM_PSEUDO_REGS);
1110 set_gdbarch_register_name (gdbarch, rl78_register_name);
1111 set_gdbarch_register_type (gdbarch, rl78_register_type);
1112 set_gdbarch_pc_regnum (gdbarch, RL78_PC_REGNUM);
1113 set_gdbarch_sp_regnum (gdbarch, RL78_SP_REGNUM);
1114 set_gdbarch_pseudo_register_read (gdbarch, rl78_pseudo_register_read);
1115 set_gdbarch_pseudo_register_write (gdbarch, rl78_pseudo_register_write);
1116 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rl78_dwarf_reg_to_regnum);
c47a44f4
KB		 1117 set_gdbarch_register_reggroup_p (gdbarch, rl78_register_reggroup_p);
1118 set_gdbarch_register_sim_regno (gdbarch, rl78_register_sim_regno);
9058f767
KB		 1119
1120 /* Data types. */
1121 set_gdbarch_char_signed (gdbarch, 0);
1122 set_gdbarch_short_bit (gdbarch, 16);
1123 set_gdbarch_int_bit (gdbarch, 16);
1124 set_gdbarch_long_bit (gdbarch, 32);
1125 set_gdbarch_long_long_bit (gdbarch, 64);
1126 set_gdbarch_ptr_bit (gdbarch, 16);
1127 set_gdbarch_addr_bit (gdbarch, 32);
1128 set_gdbarch_float_bit (gdbarch, 32);
1129 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
1130 set_gdbarch_double_bit (gdbarch, 32);
1131 set_gdbarch_long_double_bit (gdbarch, 64);
1132 set_gdbarch_double_format (gdbarch, floatformats_ieee_single);
1133 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
1134 set_gdbarch_pointer_to_address (gdbarch, rl78_pointer_to_address);
1135 set_gdbarch_address_to_pointer (gdbarch, rl78_address_to_pointer);
1136 set_gdbarch_addr_bits_remove (gdbarch, rl78_addr_bits_remove);
1137
1138 /* Breakpoints. */
1139 set_gdbarch_breakpoint_from_pc (gdbarch, rl78_breakpoint_from_pc);
1140 set_gdbarch_decr_pc_after_break (gdbarch, 1);
1141
1142 /* Disassembly. */
1143 set_gdbarch_print_insn (gdbarch, print_insn_rl78);
1144
1145 /* Frames, prologues, etc. */
1146 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1147 set_gdbarch_skip_prologue (gdbarch, rl78_skip_prologue);
1148 set_gdbarch_unwind_pc (gdbarch, rl78_unwind_pc);
1149 set_gdbarch_unwind_sp (gdbarch, rl78_unwind_sp);
1150 set_gdbarch_frame_align (gdbarch, rl78_frame_align);
1151 frame_unwind_append_unwinder (gdbarch, &rl78_unwind);
1152
1153 /* Dummy frames, return values. */
1154 set_gdbarch_dummy_id (gdbarch, rl78_dummy_id);
1155 set_gdbarch_push_dummy_call (gdbarch, rl78_push_dummy_call);
1156 set_gdbarch_return_value (gdbarch, rl78_return_value);
1157
1158 /* Virtual tables. */
1159 set_gdbarch_vbit_in_delta (gdbarch, 1);
1160
1161 return gdbarch;
1162}
1163
693be288
JK		 1164/* -Wmissing-prototypes */
1165extern initialize_file_ftype _initialize_rl78_tdep;
1166
9058f767
KB		 1167/* Register the above initialization routine. */
1168
1169void
1170_initialize_rl78_tdep (void)
1171{
1172 register_gdbarch_init (bfd_arch_rl78, rl78_gdbarch_init);
1173}
GDB Binutils - Deliverables
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