Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Target-dependent code for GDB, the GNU debugger. |
b6ba6518 | 2 | Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
1e698235 | 3 | 1998, 1999, 2000, 2001, 2002, 2003 |
c906108c SS |
4 | Free Software Foundation, Inc. |
5 | ||
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
22 | |
23 | #include "defs.h" | |
24 | #include "frame.h" | |
25 | #include "inferior.h" | |
26 | #include "symtab.h" | |
27 | #include "target.h" | |
28 | #include "gdbcore.h" | |
29 | #include "gdbcmd.h" | |
30 | #include "symfile.h" | |
31 | #include "objfiles.h" | |
7a78ae4e | 32 | #include "arch-utils.h" |
4e052eda | 33 | #include "regcache.h" |
d16aafd8 | 34 | #include "doublest.h" |
fd0407d6 | 35 | #include "value.h" |
1fcc0bb8 | 36 | #include "parser-defs.h" |
4be87837 | 37 | #include "osabi.h" |
7a78ae4e | 38 | |
2fccf04a | 39 | #include "libbfd.h" /* for bfd_default_set_arch_mach */ |
7a78ae4e | 40 | #include "coff/internal.h" /* for libcoff.h */ |
2fccf04a | 41 | #include "libcoff.h" /* for xcoff_data */ |
11ed25ac KB |
42 | #include "coff/xcoff.h" |
43 | #include "libxcoff.h" | |
7a78ae4e | 44 | |
9aa1e687 | 45 | #include "elf-bfd.h" |
7a78ae4e | 46 | |
6ded7999 | 47 | #include "solib-svr4.h" |
9aa1e687 | 48 | #include "ppc-tdep.h" |
7a78ae4e | 49 | |
338ef23d AC |
50 | #include "gdb_assert.h" |
51 | ||
7a78ae4e ND |
52 | /* If the kernel has to deliver a signal, it pushes a sigcontext |
53 | structure on the stack and then calls the signal handler, passing | |
54 | the address of the sigcontext in an argument register. Usually | |
55 | the signal handler doesn't save this register, so we have to | |
56 | access the sigcontext structure via an offset from the signal handler | |
57 | frame. | |
58 | The following constants were determined by experimentation on AIX 3.2. */ | |
59 | #define SIG_FRAME_PC_OFFSET 96 | |
60 | #define SIG_FRAME_LR_OFFSET 108 | |
61 | #define SIG_FRAME_FP_OFFSET 284 | |
62 | ||
7a78ae4e ND |
63 | /* To be used by skip_prologue. */ |
64 | ||
65 | struct rs6000_framedata | |
66 | { | |
67 | int offset; /* total size of frame --- the distance | |
68 | by which we decrement sp to allocate | |
69 | the frame */ | |
70 | int saved_gpr; /* smallest # of saved gpr */ | |
71 | int saved_fpr; /* smallest # of saved fpr */ | |
6be8bc0c | 72 | int saved_vr; /* smallest # of saved vr */ |
96ff0de4 | 73 | int saved_ev; /* smallest # of saved ev */ |
7a78ae4e ND |
74 | int alloca_reg; /* alloca register number (frame ptr) */ |
75 | char frameless; /* true if frameless functions. */ | |
76 | char nosavedpc; /* true if pc not saved. */ | |
77 | int gpr_offset; /* offset of saved gprs from prev sp */ | |
78 | int fpr_offset; /* offset of saved fprs from prev sp */ | |
6be8bc0c | 79 | int vr_offset; /* offset of saved vrs from prev sp */ |
96ff0de4 | 80 | int ev_offset; /* offset of saved evs from prev sp */ |
7a78ae4e ND |
81 | int lr_offset; /* offset of saved lr */ |
82 | int cr_offset; /* offset of saved cr */ | |
6be8bc0c | 83 | int vrsave_offset; /* offset of saved vrsave register */ |
7a78ae4e ND |
84 | }; |
85 | ||
86 | /* Description of a single register. */ | |
87 | ||
88 | struct reg | |
89 | { | |
90 | char *name; /* name of register */ | |
91 | unsigned char sz32; /* size on 32-bit arch, 0 if nonextant */ | |
92 | unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */ | |
93 | unsigned char fpr; /* whether register is floating-point */ | |
489461e2 | 94 | unsigned char pseudo; /* whether register is pseudo */ |
7a78ae4e ND |
95 | }; |
96 | ||
c906108c SS |
97 | /* Breakpoint shadows for the single step instructions will be kept here. */ |
98 | ||
c5aa993b JM |
99 | static struct sstep_breaks |
100 | { | |
101 | /* Address, or 0 if this is not in use. */ | |
102 | CORE_ADDR address; | |
103 | /* Shadow contents. */ | |
104 | char data[4]; | |
105 | } | |
106 | stepBreaks[2]; | |
c906108c SS |
107 | |
108 | /* Hook for determining the TOC address when calling functions in the | |
109 | inferior under AIX. The initialization code in rs6000-nat.c sets | |
110 | this hook to point to find_toc_address. */ | |
111 | ||
7a78ae4e ND |
112 | CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL; |
113 | ||
114 | /* Hook to set the current architecture when starting a child process. | |
115 | rs6000-nat.c sets this. */ | |
116 | ||
117 | void (*rs6000_set_host_arch_hook) (int) = NULL; | |
c906108c SS |
118 | |
119 | /* Static function prototypes */ | |
120 | ||
a14ed312 KB |
121 | static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc, |
122 | CORE_ADDR safety); | |
077276e8 KB |
123 | static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR, |
124 | struct rs6000_framedata *); | |
7a78ae4e ND |
125 | static void frame_get_saved_regs (struct frame_info * fi, |
126 | struct rs6000_framedata * fdatap); | |
127 | static CORE_ADDR frame_initial_stack_address (struct frame_info *); | |
c906108c | 128 | |
64b84175 KB |
129 | /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ |
130 | int | |
131 | altivec_register_p (int regno) | |
132 | { | |
133 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
134 | if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) | |
135 | return 0; | |
136 | else | |
137 | return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); | |
138 | } | |
139 | ||
0a613259 AC |
140 | /* Use the architectures FP registers? */ |
141 | int | |
142 | ppc_floating_point_unit_p (struct gdbarch *gdbarch) | |
143 | { | |
144 | const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch); | |
145 | if (info->arch == bfd_arch_powerpc) | |
146 | return (info->mach != bfd_mach_ppc_e500); | |
147 | if (info->arch == bfd_arch_rs6000) | |
148 | return 1; | |
149 | return 0; | |
150 | } | |
151 | ||
7a78ae4e | 152 | /* Read a LEN-byte address from debugged memory address MEMADDR. */ |
c906108c | 153 | |
7a78ae4e ND |
154 | static CORE_ADDR |
155 | read_memory_addr (CORE_ADDR memaddr, int len) | |
156 | { | |
157 | return read_memory_unsigned_integer (memaddr, len); | |
158 | } | |
c906108c | 159 | |
7a78ae4e ND |
160 | static CORE_ADDR |
161 | rs6000_skip_prologue (CORE_ADDR pc) | |
b83266a0 SS |
162 | { |
163 | struct rs6000_framedata frame; | |
077276e8 | 164 | pc = skip_prologue (pc, 0, &frame); |
b83266a0 SS |
165 | return pc; |
166 | } | |
167 | ||
168 | ||
c906108c SS |
169 | /* Fill in fi->saved_regs */ |
170 | ||
171 | struct frame_extra_info | |
172 | { | |
173 | /* Functions calling alloca() change the value of the stack | |
174 | pointer. We need to use initial stack pointer (which is saved in | |
175 | r31 by gcc) in such cases. If a compiler emits traceback table, | |
176 | then we should use the alloca register specified in traceback | |
177 | table. FIXME. */ | |
c5aa993b | 178 | CORE_ADDR initial_sp; /* initial stack pointer. */ |
c906108c SS |
179 | }; |
180 | ||
9aa1e687 | 181 | void |
7a78ae4e | 182 | rs6000_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c | 183 | { |
c9012c71 AC |
184 | struct frame_extra_info *extra_info = |
185 | frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info)); | |
186 | extra_info->initial_sp = 0; | |
bdd78e62 AC |
187 | if (get_next_frame (fi) != NULL |
188 | && get_frame_pc (fi) < TEXT_SEGMENT_BASE) | |
7a292a7a | 189 | /* We're in get_prev_frame */ |
c906108c SS |
190 | /* and this is a special signal frame. */ |
191 | /* (fi->pc will be some low address in the kernel, */ | |
192 | /* to which the signal handler returns). */ | |
5a203e44 | 193 | deprecated_set_frame_type (fi, SIGTRAMP_FRAME); |
c906108c SS |
194 | } |
195 | ||
7a78ae4e ND |
196 | /* Put here the code to store, into a struct frame_saved_regs, |
197 | the addresses of the saved registers of frame described by FRAME_INFO. | |
198 | This includes special registers such as pc and fp saved in special | |
199 | ways in the stack frame. sp is even more special: | |
200 | the address we return for it IS the sp for the next frame. */ | |
c906108c | 201 | |
7a78ae4e ND |
202 | /* In this implementation for RS/6000, we do *not* save sp. I am |
203 | not sure if it will be needed. The following function takes care of gpr's | |
204 | and fpr's only. */ | |
205 | ||
9aa1e687 | 206 | void |
7a78ae4e | 207 | rs6000_frame_init_saved_regs (struct frame_info *fi) |
c906108c SS |
208 | { |
209 | frame_get_saved_regs (fi, NULL); | |
210 | } | |
211 | ||
7a78ae4e ND |
212 | static CORE_ADDR |
213 | rs6000_frame_args_address (struct frame_info *fi) | |
c906108c | 214 | { |
c9012c71 AC |
215 | struct frame_extra_info *extra_info = get_frame_extra_info (fi); |
216 | if (extra_info->initial_sp != 0) | |
217 | return extra_info->initial_sp; | |
c906108c SS |
218 | else |
219 | return frame_initial_stack_address (fi); | |
220 | } | |
221 | ||
7a78ae4e ND |
222 | /* Immediately after a function call, return the saved pc. |
223 | Can't go through the frames for this because on some machines | |
224 | the new frame is not set up until the new function executes | |
225 | some instructions. */ | |
226 | ||
227 | static CORE_ADDR | |
228 | rs6000_saved_pc_after_call (struct frame_info *fi) | |
229 | { | |
2188cbdd | 230 | return read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum); |
7a78ae4e | 231 | } |
c906108c SS |
232 | |
233 | /* Calculate the destination of a branch/jump. Return -1 if not a branch. */ | |
234 | ||
235 | static CORE_ADDR | |
7a78ae4e | 236 | branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety) |
c906108c SS |
237 | { |
238 | CORE_ADDR dest; | |
239 | int immediate; | |
240 | int absolute; | |
241 | int ext_op; | |
242 | ||
243 | absolute = (int) ((instr >> 1) & 1); | |
244 | ||
c5aa993b JM |
245 | switch (opcode) |
246 | { | |
247 | case 18: | |
248 | immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */ | |
249 | if (absolute) | |
250 | dest = immediate; | |
251 | else | |
252 | dest = pc + immediate; | |
253 | break; | |
254 | ||
255 | case 16: | |
256 | immediate = ((instr & ~3) << 16) >> 16; /* br conditional */ | |
257 | if (absolute) | |
258 | dest = immediate; | |
259 | else | |
260 | dest = pc + immediate; | |
261 | break; | |
262 | ||
263 | case 19: | |
264 | ext_op = (instr >> 1) & 0x3ff; | |
265 | ||
266 | if (ext_op == 16) /* br conditional register */ | |
267 | { | |
2188cbdd | 268 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; |
c5aa993b JM |
269 | |
270 | /* If we are about to return from a signal handler, dest is | |
271 | something like 0x3c90. The current frame is a signal handler | |
272 | caller frame, upon completion of the sigreturn system call | |
273 | execution will return to the saved PC in the frame. */ | |
274 | if (dest < TEXT_SEGMENT_BASE) | |
275 | { | |
276 | struct frame_info *fi; | |
277 | ||
278 | fi = get_current_frame (); | |
279 | if (fi != NULL) | |
8b36eed8 | 280 | dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET, |
21283beb | 281 | gdbarch_tdep (current_gdbarch)->wordsize); |
c5aa993b JM |
282 | } |
283 | } | |
284 | ||
285 | else if (ext_op == 528) /* br cond to count reg */ | |
286 | { | |
2188cbdd | 287 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3; |
c5aa993b JM |
288 | |
289 | /* If we are about to execute a system call, dest is something | |
290 | like 0x22fc or 0x3b00. Upon completion the system call | |
291 | will return to the address in the link register. */ | |
292 | if (dest < TEXT_SEGMENT_BASE) | |
2188cbdd | 293 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; |
c5aa993b JM |
294 | } |
295 | else | |
296 | return -1; | |
297 | break; | |
c906108c | 298 | |
c5aa993b JM |
299 | default: |
300 | return -1; | |
301 | } | |
c906108c SS |
302 | return (dest < TEXT_SEGMENT_BASE) ? safety : dest; |
303 | } | |
304 | ||
305 | ||
306 | /* Sequence of bytes for breakpoint instruction. */ | |
307 | ||
f4f9705a | 308 | const static unsigned char * |
7a78ae4e | 309 | rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size) |
c906108c | 310 | { |
aaab4dba AC |
311 | static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 }; |
312 | static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d }; | |
c906108c | 313 | *bp_size = 4; |
d7449b42 | 314 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
315 | return big_breakpoint; |
316 | else | |
317 | return little_breakpoint; | |
318 | } | |
319 | ||
320 | ||
321 | /* AIX does not support PT_STEP. Simulate it. */ | |
322 | ||
323 | void | |
379d08a1 AC |
324 | rs6000_software_single_step (enum target_signal signal, |
325 | int insert_breakpoints_p) | |
c906108c | 326 | { |
7c40d541 KB |
327 | CORE_ADDR dummy; |
328 | int breakp_sz; | |
f4f9705a | 329 | const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz); |
c906108c SS |
330 | int ii, insn; |
331 | CORE_ADDR loc; | |
332 | CORE_ADDR breaks[2]; | |
333 | int opcode; | |
334 | ||
c5aa993b JM |
335 | if (insert_breakpoints_p) |
336 | { | |
c906108c | 337 | |
c5aa993b | 338 | loc = read_pc (); |
c906108c | 339 | |
c5aa993b | 340 | insn = read_memory_integer (loc, 4); |
c906108c | 341 | |
7c40d541 | 342 | breaks[0] = loc + breakp_sz; |
c5aa993b JM |
343 | opcode = insn >> 26; |
344 | breaks[1] = branch_dest (opcode, insn, loc, breaks[0]); | |
c906108c | 345 | |
c5aa993b JM |
346 | /* Don't put two breakpoints on the same address. */ |
347 | if (breaks[1] == breaks[0]) | |
348 | breaks[1] = -1; | |
c906108c | 349 | |
c5aa993b | 350 | stepBreaks[1].address = 0; |
c906108c | 351 | |
c5aa993b JM |
352 | for (ii = 0; ii < 2; ++ii) |
353 | { | |
c906108c | 354 | |
c5aa993b JM |
355 | /* ignore invalid breakpoint. */ |
356 | if (breaks[ii] == -1) | |
357 | continue; | |
7c40d541 | 358 | target_insert_breakpoint (breaks[ii], stepBreaks[ii].data); |
c5aa993b JM |
359 | stepBreaks[ii].address = breaks[ii]; |
360 | } | |
c906108c | 361 | |
c5aa993b JM |
362 | } |
363 | else | |
364 | { | |
c906108c | 365 | |
c5aa993b JM |
366 | /* remove step breakpoints. */ |
367 | for (ii = 0; ii < 2; ++ii) | |
368 | if (stepBreaks[ii].address != 0) | |
7c40d541 KB |
369 | target_remove_breakpoint (stepBreaks[ii].address, |
370 | stepBreaks[ii].data); | |
c5aa993b | 371 | } |
c906108c | 372 | errno = 0; /* FIXME, don't ignore errors! */ |
c5aa993b | 373 | /* What errors? {read,write}_memory call error(). */ |
c906108c SS |
374 | } |
375 | ||
376 | ||
377 | /* return pc value after skipping a function prologue and also return | |
378 | information about a function frame. | |
379 | ||
380 | in struct rs6000_framedata fdata: | |
c5aa993b JM |
381 | - frameless is TRUE, if function does not have a frame. |
382 | - nosavedpc is TRUE, if function does not save %pc value in its frame. | |
383 | - offset is the initial size of this stack frame --- the amount by | |
384 | which we decrement the sp to allocate the frame. | |
385 | - saved_gpr is the number of the first saved gpr. | |
386 | - saved_fpr is the number of the first saved fpr. | |
6be8bc0c | 387 | - saved_vr is the number of the first saved vr. |
96ff0de4 | 388 | - saved_ev is the number of the first saved ev. |
c5aa993b JM |
389 | - alloca_reg is the number of the register used for alloca() handling. |
390 | Otherwise -1. | |
391 | - gpr_offset is the offset of the first saved gpr from the previous frame. | |
392 | - fpr_offset is the offset of the first saved fpr from the previous frame. | |
6be8bc0c | 393 | - vr_offset is the offset of the first saved vr from the previous frame. |
96ff0de4 | 394 | - ev_offset is the offset of the first saved ev from the previous frame. |
c5aa993b JM |
395 | - lr_offset is the offset of the saved lr |
396 | - cr_offset is the offset of the saved cr | |
6be8bc0c | 397 | - vrsave_offset is the offset of the saved vrsave register |
c5aa993b | 398 | */ |
c906108c SS |
399 | |
400 | #define SIGNED_SHORT(x) \ | |
401 | ((sizeof (short) == 2) \ | |
402 | ? ((int)(short)(x)) \ | |
403 | : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) | |
404 | ||
405 | #define GET_SRC_REG(x) (((x) >> 21) & 0x1f) | |
406 | ||
55d05f3b KB |
407 | /* Limit the number of skipped non-prologue instructions, as the examining |
408 | of the prologue is expensive. */ | |
409 | static int max_skip_non_prologue_insns = 10; | |
410 | ||
411 | /* Given PC representing the starting address of a function, and | |
412 | LIM_PC which is the (sloppy) limit to which to scan when looking | |
413 | for a prologue, attempt to further refine this limit by using | |
414 | the line data in the symbol table. If successful, a better guess | |
415 | on where the prologue ends is returned, otherwise the previous | |
416 | value of lim_pc is returned. */ | |
417 | static CORE_ADDR | |
418 | refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc) | |
419 | { | |
420 | struct symtab_and_line prologue_sal; | |
421 | ||
422 | prologue_sal = find_pc_line (pc, 0); | |
423 | if (prologue_sal.line != 0) | |
424 | { | |
425 | int i; | |
426 | CORE_ADDR addr = prologue_sal.end; | |
427 | ||
428 | /* Handle the case in which compiler's optimizer/scheduler | |
429 | has moved instructions into the prologue. We scan ahead | |
430 | in the function looking for address ranges whose corresponding | |
431 | line number is less than or equal to the first one that we | |
432 | found for the function. (It can be less than when the | |
433 | scheduler puts a body instruction before the first prologue | |
434 | instruction.) */ | |
435 | for (i = 2 * max_skip_non_prologue_insns; | |
436 | i > 0 && (lim_pc == 0 || addr < lim_pc); | |
437 | i--) | |
438 | { | |
439 | struct symtab_and_line sal; | |
440 | ||
441 | sal = find_pc_line (addr, 0); | |
442 | if (sal.line == 0) | |
443 | break; | |
444 | if (sal.line <= prologue_sal.line | |
445 | && sal.symtab == prologue_sal.symtab) | |
446 | { | |
447 | prologue_sal = sal; | |
448 | } | |
449 | addr = sal.end; | |
450 | } | |
451 | ||
452 | if (lim_pc == 0 || prologue_sal.end < lim_pc) | |
453 | lim_pc = prologue_sal.end; | |
454 | } | |
455 | return lim_pc; | |
456 | } | |
457 | ||
458 | ||
7a78ae4e | 459 | static CORE_ADDR |
077276e8 | 460 | skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) |
c906108c SS |
461 | { |
462 | CORE_ADDR orig_pc = pc; | |
55d05f3b | 463 | CORE_ADDR last_prologue_pc = pc; |
6be8bc0c | 464 | CORE_ADDR li_found_pc = 0; |
c906108c SS |
465 | char buf[4]; |
466 | unsigned long op; | |
467 | long offset = 0; | |
6be8bc0c | 468 | long vr_saved_offset = 0; |
482ca3f5 KB |
469 | int lr_reg = -1; |
470 | int cr_reg = -1; | |
6be8bc0c | 471 | int vr_reg = -1; |
96ff0de4 EZ |
472 | int ev_reg = -1; |
473 | long ev_offset = 0; | |
6be8bc0c | 474 | int vrsave_reg = -1; |
c906108c SS |
475 | int reg; |
476 | int framep = 0; | |
477 | int minimal_toc_loaded = 0; | |
ddb20c56 | 478 | int prev_insn_was_prologue_insn = 1; |
55d05f3b | 479 | int num_skip_non_prologue_insns = 0; |
96ff0de4 | 480 | const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch); |
6f99cb26 | 481 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
96ff0de4 | 482 | |
55d05f3b KB |
483 | /* Attempt to find the end of the prologue when no limit is specified. |
484 | Note that refine_prologue_limit() has been written so that it may | |
485 | be used to "refine" the limits of non-zero PC values too, but this | |
486 | is only safe if we 1) trust the line information provided by the | |
487 | compiler and 2) iterate enough to actually find the end of the | |
488 | prologue. | |
489 | ||
490 | It may become a good idea at some point (for both performance and | |
491 | accuracy) to unconditionally call refine_prologue_limit(). But, | |
492 | until we can make a clear determination that this is beneficial, | |
493 | we'll play it safe and only use it to obtain a limit when none | |
494 | has been specified. */ | |
495 | if (lim_pc == 0) | |
496 | lim_pc = refine_prologue_limit (pc, lim_pc); | |
c906108c | 497 | |
ddb20c56 | 498 | memset (fdata, 0, sizeof (struct rs6000_framedata)); |
c906108c SS |
499 | fdata->saved_gpr = -1; |
500 | fdata->saved_fpr = -1; | |
6be8bc0c | 501 | fdata->saved_vr = -1; |
96ff0de4 | 502 | fdata->saved_ev = -1; |
c906108c SS |
503 | fdata->alloca_reg = -1; |
504 | fdata->frameless = 1; | |
505 | fdata->nosavedpc = 1; | |
506 | ||
55d05f3b | 507 | for (;; pc += 4) |
c906108c | 508 | { |
ddb20c56 KB |
509 | /* Sometimes it isn't clear if an instruction is a prologue |
510 | instruction or not. When we encounter one of these ambiguous | |
511 | cases, we'll set prev_insn_was_prologue_insn to 0 (false). | |
512 | Otherwise, we'll assume that it really is a prologue instruction. */ | |
513 | if (prev_insn_was_prologue_insn) | |
514 | last_prologue_pc = pc; | |
55d05f3b KB |
515 | |
516 | /* Stop scanning if we've hit the limit. */ | |
517 | if (lim_pc != 0 && pc >= lim_pc) | |
518 | break; | |
519 | ||
ddb20c56 KB |
520 | prev_insn_was_prologue_insn = 1; |
521 | ||
55d05f3b | 522 | /* Fetch the instruction and convert it to an integer. */ |
ddb20c56 KB |
523 | if (target_read_memory (pc, buf, 4)) |
524 | break; | |
525 | op = extract_signed_integer (buf, 4); | |
c906108c | 526 | |
c5aa993b JM |
527 | if ((op & 0xfc1fffff) == 0x7c0802a6) |
528 | { /* mflr Rx */ | |
98f08d3d | 529 | lr_reg = (op & 0x03e00000); |
c5aa993b | 530 | continue; |
c906108c | 531 | |
c5aa993b JM |
532 | } |
533 | else if ((op & 0xfc1fffff) == 0x7c000026) | |
534 | { /* mfcr Rx */ | |
98f08d3d | 535 | cr_reg = (op & 0x03e00000); |
c5aa993b | 536 | continue; |
c906108c | 537 | |
c906108c | 538 | } |
c5aa993b JM |
539 | else if ((op & 0xfc1f0000) == 0xd8010000) |
540 | { /* stfd Rx,NUM(r1) */ | |
541 | reg = GET_SRC_REG (op); | |
542 | if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) | |
543 | { | |
544 | fdata->saved_fpr = reg; | |
545 | fdata->fpr_offset = SIGNED_SHORT (op) + offset; | |
546 | } | |
547 | continue; | |
c906108c | 548 | |
c5aa993b JM |
549 | } |
550 | else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ | |
7a78ae4e ND |
551 | (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ |
552 | (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ | |
553 | (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ | |
c5aa993b JM |
554 | { |
555 | ||
556 | reg = GET_SRC_REG (op); | |
557 | if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) | |
558 | { | |
559 | fdata->saved_gpr = reg; | |
7a78ae4e | 560 | if ((op & 0xfc1f0003) == 0xf8010000) |
98f08d3d | 561 | op &= ~3UL; |
c5aa993b JM |
562 | fdata->gpr_offset = SIGNED_SHORT (op) + offset; |
563 | } | |
564 | continue; | |
c906108c | 565 | |
ddb20c56 KB |
566 | } |
567 | else if ((op & 0xffff0000) == 0x60000000) | |
568 | { | |
96ff0de4 | 569 | /* nop */ |
ddb20c56 KB |
570 | /* Allow nops in the prologue, but do not consider them to |
571 | be part of the prologue unless followed by other prologue | |
572 | instructions. */ | |
573 | prev_insn_was_prologue_insn = 0; | |
574 | continue; | |
575 | ||
c906108c | 576 | } |
c5aa993b JM |
577 | else if ((op & 0xffff0000) == 0x3c000000) |
578 | { /* addis 0,0,NUM, used | |
579 | for >= 32k frames */ | |
580 | fdata->offset = (op & 0x0000ffff) << 16; | |
581 | fdata->frameless = 0; | |
582 | continue; | |
583 | ||
584 | } | |
585 | else if ((op & 0xffff0000) == 0x60000000) | |
586 | { /* ori 0,0,NUM, 2nd ha | |
587 | lf of >= 32k frames */ | |
588 | fdata->offset |= (op & 0x0000ffff); | |
589 | fdata->frameless = 0; | |
590 | continue; | |
591 | ||
592 | } | |
98f08d3d KB |
593 | else if (lr_reg != -1 && |
594 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ | |
595 | (((op & 0xffff0000) == (lr_reg | 0xf8010000)) || | |
596 | /* stw Rx, NUM(r1) */ | |
597 | ((op & 0xffff0000) == (lr_reg | 0x90010000)) || | |
598 | /* stwu Rx, NUM(r1) */ | |
599 | ((op & 0xffff0000) == (lr_reg | 0x94010000)))) | |
600 | { /* where Rx == lr */ | |
601 | fdata->lr_offset = offset; | |
c5aa993b JM |
602 | fdata->nosavedpc = 0; |
603 | lr_reg = 0; | |
98f08d3d KB |
604 | if ((op & 0xfc000003) == 0xf8000000 || /* std */ |
605 | (op & 0xfc000000) == 0x90000000) /* stw */ | |
606 | { | |
607 | /* Does not update r1, so add displacement to lr_offset. */ | |
608 | fdata->lr_offset += SIGNED_SHORT (op); | |
609 | } | |
c5aa993b JM |
610 | continue; |
611 | ||
612 | } | |
98f08d3d KB |
613 | else if (cr_reg != -1 && |
614 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ | |
615 | (((op & 0xffff0000) == (cr_reg | 0xf8010000)) || | |
616 | /* stw Rx, NUM(r1) */ | |
617 | ((op & 0xffff0000) == (cr_reg | 0x90010000)) || | |
618 | /* stwu Rx, NUM(r1) */ | |
619 | ((op & 0xffff0000) == (cr_reg | 0x94010000)))) | |
620 | { /* where Rx == cr */ | |
621 | fdata->cr_offset = offset; | |
c5aa993b | 622 | cr_reg = 0; |
98f08d3d KB |
623 | if ((op & 0xfc000003) == 0xf8000000 || |
624 | (op & 0xfc000000) == 0x90000000) | |
625 | { | |
626 | /* Does not update r1, so add displacement to cr_offset. */ | |
627 | fdata->cr_offset += SIGNED_SHORT (op); | |
628 | } | |
c5aa993b JM |
629 | continue; |
630 | ||
631 | } | |
632 | else if (op == 0x48000005) | |
633 | { /* bl .+4 used in | |
634 | -mrelocatable */ | |
635 | continue; | |
636 | ||
637 | } | |
638 | else if (op == 0x48000004) | |
639 | { /* b .+4 (xlc) */ | |
640 | break; | |
641 | ||
c5aa993b | 642 | } |
6be8bc0c EZ |
643 | else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used |
644 | in V.4 -mminimal-toc */ | |
c5aa993b JM |
645 | (op & 0xffff0000) == 0x3bde0000) |
646 | { /* addi 30,30,foo@l */ | |
647 | continue; | |
c906108c | 648 | |
c5aa993b JM |
649 | } |
650 | else if ((op & 0xfc000001) == 0x48000001) | |
651 | { /* bl foo, | |
652 | to save fprs??? */ | |
c906108c | 653 | |
c5aa993b | 654 | fdata->frameless = 0; |
6be8bc0c EZ |
655 | /* Don't skip over the subroutine call if it is not within |
656 | the first three instructions of the prologue. */ | |
c5aa993b JM |
657 | if ((pc - orig_pc) > 8) |
658 | break; | |
659 | ||
660 | op = read_memory_integer (pc + 4, 4); | |
661 | ||
6be8bc0c EZ |
662 | /* At this point, make sure this is not a trampoline |
663 | function (a function that simply calls another functions, | |
664 | and nothing else). If the next is not a nop, this branch | |
665 | was part of the function prologue. */ | |
c5aa993b JM |
666 | |
667 | if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ | |
668 | break; /* don't skip over | |
669 | this branch */ | |
670 | continue; | |
671 | ||
c5aa993b | 672 | } |
98f08d3d KB |
673 | /* update stack pointer */ |
674 | else if ((op & 0xfc1f0000) == 0x94010000) | |
675 | { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */ | |
c5aa993b JM |
676 | fdata->frameless = 0; |
677 | fdata->offset = SIGNED_SHORT (op); | |
678 | offset = fdata->offset; | |
679 | continue; | |
c5aa993b | 680 | } |
98f08d3d KB |
681 | else if ((op & 0xfc1f016a) == 0x7c01016e) |
682 | { /* stwux rX,r1,rY */ | |
683 | /* no way to figure out what r1 is going to be */ | |
684 | fdata->frameless = 0; | |
685 | offset = fdata->offset; | |
686 | continue; | |
687 | } | |
688 | else if ((op & 0xfc1f0003) == 0xf8010001) | |
689 | { /* stdu rX,NUM(r1) */ | |
690 | fdata->frameless = 0; | |
691 | fdata->offset = SIGNED_SHORT (op & ~3UL); | |
692 | offset = fdata->offset; | |
693 | continue; | |
694 | } | |
695 | else if ((op & 0xfc1f016a) == 0x7c01016a) | |
696 | { /* stdux rX,r1,rY */ | |
697 | /* no way to figure out what r1 is going to be */ | |
c5aa993b JM |
698 | fdata->frameless = 0; |
699 | offset = fdata->offset; | |
700 | continue; | |
c5aa993b | 701 | } |
98f08d3d KB |
702 | /* Load up minimal toc pointer */ |
703 | else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */ | |
704 | (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */ | |
c5aa993b | 705 | && !minimal_toc_loaded) |
98f08d3d | 706 | { |
c5aa993b JM |
707 | minimal_toc_loaded = 1; |
708 | continue; | |
709 | ||
f6077098 KB |
710 | /* move parameters from argument registers to local variable |
711 | registers */ | |
712 | } | |
713 | else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ | |
714 | (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ | |
715 | (((op >> 21) & 31) <= 10) && | |
96ff0de4 | 716 | ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */ |
f6077098 KB |
717 | { |
718 | continue; | |
719 | ||
c5aa993b JM |
720 | /* store parameters in stack */ |
721 | } | |
6be8bc0c | 722 | else if ((op & 0xfc1f0003) == 0xf8010000 || /* std rx,NUM(r1) */ |
c5aa993b | 723 | (op & 0xfc1f0000) == 0xd8010000 || /* stfd Rx,NUM(r1) */ |
7a78ae4e ND |
724 | (op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ |
725 | { | |
c5aa993b | 726 | continue; |
c906108c | 727 | |
c5aa993b JM |
728 | /* store parameters in stack via frame pointer */ |
729 | } | |
730 | else if (framep && | |
731 | ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r1) */ | |
732 | (op & 0xfc1f0000) == 0xd81f0000 || /* stfd Rx,NUM(r1) */ | |
733 | (op & 0xfc1f0000) == 0xfc1f0000)) | |
734 | { /* frsp, fp?,NUM(r1) */ | |
735 | continue; | |
736 | ||
737 | /* Set up frame pointer */ | |
738 | } | |
739 | else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ | |
740 | || op == 0x7c3f0b78) | |
741 | { /* mr r31, r1 */ | |
742 | fdata->frameless = 0; | |
743 | framep = 1; | |
6f99cb26 | 744 | fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); |
c5aa993b JM |
745 | continue; |
746 | ||
747 | /* Another way to set up the frame pointer. */ | |
748 | } | |
749 | else if ((op & 0xfc1fffff) == 0x38010000) | |
750 | { /* addi rX, r1, 0x0 */ | |
751 | fdata->frameless = 0; | |
752 | framep = 1; | |
6f99cb26 AC |
753 | fdata->alloca_reg = (tdep->ppc_gp0_regnum |
754 | + ((op & ~0x38010000) >> 21)); | |
c5aa993b | 755 | continue; |
c5aa993b | 756 | } |
6be8bc0c EZ |
757 | /* AltiVec related instructions. */ |
758 | /* Store the vrsave register (spr 256) in another register for | |
759 | later manipulation, or load a register into the vrsave | |
760 | register. 2 instructions are used: mfvrsave and | |
761 | mtvrsave. They are shorthand notation for mfspr Rn, SPR256 | |
762 | and mtspr SPR256, Rn. */ | |
763 | /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 | |
764 | mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ | |
765 | else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ | |
766 | { | |
767 | vrsave_reg = GET_SRC_REG (op); | |
768 | continue; | |
769 | } | |
770 | else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ | |
771 | { | |
772 | continue; | |
773 | } | |
774 | /* Store the register where vrsave was saved to onto the stack: | |
775 | rS is the register where vrsave was stored in a previous | |
776 | instruction. */ | |
777 | /* 100100 sssss 00001 dddddddd dddddddd */ | |
778 | else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ | |
779 | { | |
780 | if (vrsave_reg == GET_SRC_REG (op)) | |
781 | { | |
782 | fdata->vrsave_offset = SIGNED_SHORT (op) + offset; | |
783 | vrsave_reg = -1; | |
784 | } | |
785 | continue; | |
786 | } | |
787 | /* Compute the new value of vrsave, by modifying the register | |
788 | where vrsave was saved to. */ | |
789 | else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ | |
790 | || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ | |
791 | { | |
792 | continue; | |
793 | } | |
794 | /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first | |
795 | in a pair of insns to save the vector registers on the | |
796 | stack. */ | |
797 | /* 001110 00000 00000 iiii iiii iiii iiii */ | |
96ff0de4 EZ |
798 | /* 001110 01110 00000 iiii iiii iiii iiii */ |
799 | else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ | |
800 | || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ | |
6be8bc0c EZ |
801 | { |
802 | li_found_pc = pc; | |
803 | vr_saved_offset = SIGNED_SHORT (op); | |
804 | } | |
805 | /* Store vector register S at (r31+r0) aligned to 16 bytes. */ | |
806 | /* 011111 sssss 11111 00000 00111001110 */ | |
807 | else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ | |
808 | { | |
809 | if (pc == (li_found_pc + 4)) | |
810 | { | |
811 | vr_reg = GET_SRC_REG (op); | |
812 | /* If this is the first vector reg to be saved, or if | |
813 | it has a lower number than others previously seen, | |
814 | reupdate the frame info. */ | |
815 | if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) | |
816 | { | |
817 | fdata->saved_vr = vr_reg; | |
818 | fdata->vr_offset = vr_saved_offset + offset; | |
819 | } | |
820 | vr_saved_offset = -1; | |
821 | vr_reg = -1; | |
822 | li_found_pc = 0; | |
823 | } | |
824 | } | |
825 | /* End AltiVec related instructions. */ | |
96ff0de4 EZ |
826 | |
827 | /* Start BookE related instructions. */ | |
828 | /* Store gen register S at (r31+uimm). | |
829 | Any register less than r13 is volatile, so we don't care. */ | |
830 | /* 000100 sssss 11111 iiiii 01100100001 */ | |
831 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
832 | && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ | |
833 | { | |
834 | if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ | |
835 | { | |
836 | unsigned int imm; | |
837 | ev_reg = GET_SRC_REG (op); | |
838 | imm = (op >> 11) & 0x1f; | |
839 | ev_offset = imm * 8; | |
840 | /* If this is the first vector reg to be saved, or if | |
841 | it has a lower number than others previously seen, | |
842 | reupdate the frame info. */ | |
843 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
844 | { | |
845 | fdata->saved_ev = ev_reg; | |
846 | fdata->ev_offset = ev_offset + offset; | |
847 | } | |
848 | } | |
849 | continue; | |
850 | } | |
851 | /* Store gen register rS at (r1+rB). */ | |
852 | /* 000100 sssss 00001 bbbbb 01100100000 */ | |
853 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
854 | && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ | |
855 | { | |
856 | if (pc == (li_found_pc + 4)) | |
857 | { | |
858 | ev_reg = GET_SRC_REG (op); | |
859 | /* If this is the first vector reg to be saved, or if | |
860 | it has a lower number than others previously seen, | |
861 | reupdate the frame info. */ | |
862 | /* We know the contents of rB from the previous instruction. */ | |
863 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
864 | { | |
865 | fdata->saved_ev = ev_reg; | |
866 | fdata->ev_offset = vr_saved_offset + offset; | |
867 | } | |
868 | vr_saved_offset = -1; | |
869 | ev_reg = -1; | |
870 | li_found_pc = 0; | |
871 | } | |
872 | continue; | |
873 | } | |
874 | /* Store gen register r31 at (rA+uimm). */ | |
875 | /* 000100 11111 aaaaa iiiii 01100100001 */ | |
876 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
877 | && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ | |
878 | { | |
879 | /* Wwe know that the source register is 31 already, but | |
880 | it can't hurt to compute it. */ | |
881 | ev_reg = GET_SRC_REG (op); | |
882 | ev_offset = ((op >> 11) & 0x1f) * 8; | |
883 | /* If this is the first vector reg to be saved, or if | |
884 | it has a lower number than others previously seen, | |
885 | reupdate the frame info. */ | |
886 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
887 | { | |
888 | fdata->saved_ev = ev_reg; | |
889 | fdata->ev_offset = ev_offset + offset; | |
890 | } | |
891 | ||
892 | continue; | |
893 | } | |
894 | /* Store gen register S at (r31+r0). | |
895 | Store param on stack when offset from SP bigger than 4 bytes. */ | |
896 | /* 000100 sssss 11111 00000 01100100000 */ | |
897 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
898 | && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ | |
899 | { | |
900 | if (pc == (li_found_pc + 4)) | |
901 | { | |
902 | if ((op & 0x03e00000) >= 0x01a00000) | |
903 | { | |
904 | ev_reg = GET_SRC_REG (op); | |
905 | /* If this is the first vector reg to be saved, or if | |
906 | it has a lower number than others previously seen, | |
907 | reupdate the frame info. */ | |
908 | /* We know the contents of r0 from the previous | |
909 | instruction. */ | |
910 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
911 | { | |
912 | fdata->saved_ev = ev_reg; | |
913 | fdata->ev_offset = vr_saved_offset + offset; | |
914 | } | |
915 | ev_reg = -1; | |
916 | } | |
917 | vr_saved_offset = -1; | |
918 | li_found_pc = 0; | |
919 | continue; | |
920 | } | |
921 | } | |
922 | /* End BookE related instructions. */ | |
923 | ||
c5aa993b JM |
924 | else |
925 | { | |
55d05f3b KB |
926 | /* Not a recognized prologue instruction. |
927 | Handle optimizer code motions into the prologue by continuing | |
928 | the search if we have no valid frame yet or if the return | |
929 | address is not yet saved in the frame. */ | |
930 | if (fdata->frameless == 0 | |
931 | && (lr_reg == -1 || fdata->nosavedpc == 0)) | |
932 | break; | |
933 | ||
934 | if (op == 0x4e800020 /* blr */ | |
935 | || op == 0x4e800420) /* bctr */ | |
936 | /* Do not scan past epilogue in frameless functions or | |
937 | trampolines. */ | |
938 | break; | |
939 | if ((op & 0xf4000000) == 0x40000000) /* bxx */ | |
64366f1c | 940 | /* Never skip branches. */ |
55d05f3b KB |
941 | break; |
942 | ||
943 | if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) | |
944 | /* Do not scan too many insns, scanning insns is expensive with | |
945 | remote targets. */ | |
946 | break; | |
947 | ||
948 | /* Continue scanning. */ | |
949 | prev_insn_was_prologue_insn = 0; | |
950 | continue; | |
c5aa993b | 951 | } |
c906108c SS |
952 | } |
953 | ||
954 | #if 0 | |
955 | /* I have problems with skipping over __main() that I need to address | |
956 | * sometime. Previously, I used to use misc_function_vector which | |
957 | * didn't work as well as I wanted to be. -MGO */ | |
958 | ||
959 | /* If the first thing after skipping a prolog is a branch to a function, | |
960 | this might be a call to an initializer in main(), introduced by gcc2. | |
64366f1c | 961 | We'd like to skip over it as well. Fortunately, xlc does some extra |
c906108c | 962 | work before calling a function right after a prologue, thus we can |
64366f1c | 963 | single out such gcc2 behaviour. */ |
c906108c | 964 | |
c906108c | 965 | |
c5aa993b JM |
966 | if ((op & 0xfc000001) == 0x48000001) |
967 | { /* bl foo, an initializer function? */ | |
968 | op = read_memory_integer (pc + 4, 4); | |
969 | ||
970 | if (op == 0x4def7b82) | |
971 | { /* cror 0xf, 0xf, 0xf (nop) */ | |
c906108c | 972 | |
64366f1c EZ |
973 | /* Check and see if we are in main. If so, skip over this |
974 | initializer function as well. */ | |
c906108c | 975 | |
c5aa993b | 976 | tmp = find_pc_misc_function (pc); |
51cc5b07 | 977 | if (tmp >= 0 && STREQ (misc_function_vector[tmp].name, main_name ())) |
c5aa993b JM |
978 | return pc + 8; |
979 | } | |
c906108c | 980 | } |
c906108c | 981 | #endif /* 0 */ |
c5aa993b JM |
982 | |
983 | fdata->offset = -fdata->offset; | |
ddb20c56 | 984 | return last_prologue_pc; |
c906108c SS |
985 | } |
986 | ||
987 | ||
988 | /************************************************************************* | |
f6077098 | 989 | Support for creating pushing a dummy frame into the stack, and popping |
c906108c SS |
990 | frames, etc. |
991 | *************************************************************************/ | |
992 | ||
c906108c | 993 | |
64366f1c | 994 | /* Pop the innermost frame, go back to the caller. */ |
c5aa993b | 995 | |
c906108c | 996 | static void |
7a78ae4e | 997 | rs6000_pop_frame (void) |
c906108c | 998 | { |
470d5666 | 999 | CORE_ADDR pc, lr, sp, prev_sp, addr; /* %pc, %lr, %sp */ |
c906108c SS |
1000 | struct rs6000_framedata fdata; |
1001 | struct frame_info *frame = get_current_frame (); | |
470d5666 | 1002 | int ii, wordsize; |
c906108c SS |
1003 | |
1004 | pc = read_pc (); | |
c193f6ac | 1005 | sp = get_frame_base (frame); |
c906108c | 1006 | |
bdd78e62 | 1007 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), |
8b36eed8 AC |
1008 | get_frame_base (frame), |
1009 | get_frame_base (frame))) | |
c906108c | 1010 | { |
7a78ae4e ND |
1011 | generic_pop_dummy_frame (); |
1012 | flush_cached_frames (); | |
1013 | return; | |
c906108c SS |
1014 | } |
1015 | ||
1016 | /* Make sure that all registers are valid. */ | |
b8b527c5 | 1017 | deprecated_read_register_bytes (0, NULL, DEPRECATED_REGISTER_BYTES); |
c906108c | 1018 | |
64366f1c | 1019 | /* Figure out previous %pc value. If the function is frameless, it is |
c906108c | 1020 | still in the link register, otherwise walk the frames and retrieve the |
64366f1c | 1021 | saved %pc value in the previous frame. */ |
c906108c | 1022 | |
be41e9f4 | 1023 | addr = get_frame_func (frame); |
bdd78e62 | 1024 | (void) skip_prologue (addr, get_frame_pc (frame), &fdata); |
c906108c | 1025 | |
21283beb | 1026 | wordsize = gdbarch_tdep (current_gdbarch)->wordsize; |
c906108c SS |
1027 | if (fdata.frameless) |
1028 | prev_sp = sp; | |
1029 | else | |
7a78ae4e | 1030 | prev_sp = read_memory_addr (sp, wordsize); |
c906108c | 1031 | if (fdata.lr_offset == 0) |
2188cbdd | 1032 | lr = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum); |
c906108c | 1033 | else |
7a78ae4e | 1034 | lr = read_memory_addr (prev_sp + fdata.lr_offset, wordsize); |
c906108c SS |
1035 | |
1036 | /* reset %pc value. */ | |
1037 | write_register (PC_REGNUM, lr); | |
1038 | ||
64366f1c | 1039 | /* reset register values if any was saved earlier. */ |
c906108c SS |
1040 | |
1041 | if (fdata.saved_gpr != -1) | |
1042 | { | |
1043 | addr = prev_sp + fdata.gpr_offset; | |
c5aa993b JM |
1044 | for (ii = fdata.saved_gpr; ii <= 31; ++ii) |
1045 | { | |
524d7c18 AC |
1046 | read_memory (addr, &deprecated_registers[REGISTER_BYTE (ii)], |
1047 | wordsize); | |
7a78ae4e | 1048 | addr += wordsize; |
c5aa993b | 1049 | } |
c906108c SS |
1050 | } |
1051 | ||
1052 | if (fdata.saved_fpr != -1) | |
1053 | { | |
1054 | addr = prev_sp + fdata.fpr_offset; | |
c5aa993b JM |
1055 | for (ii = fdata.saved_fpr; ii <= 31; ++ii) |
1056 | { | |
524d7c18 | 1057 | read_memory (addr, &deprecated_registers[REGISTER_BYTE (ii + FP0_REGNUM)], 8); |
c5aa993b JM |
1058 | addr += 8; |
1059 | } | |
c906108c SS |
1060 | } |
1061 | ||
1062 | write_register (SP_REGNUM, prev_sp); | |
1063 | target_store_registers (-1); | |
1064 | flush_cached_frames (); | |
1065 | } | |
1066 | ||
7a78ae4e | 1067 | /* Fixup the call sequence of a dummy function, with the real function |
64366f1c | 1068 | address. Its arguments will be passed by gdb. */ |
c906108c | 1069 | |
7a78ae4e ND |
1070 | static void |
1071 | rs6000_fix_call_dummy (char *dummyname, CORE_ADDR pc, CORE_ADDR fun, | |
ea7c478f | 1072 | int nargs, struct value **args, struct type *type, |
7a78ae4e | 1073 | int gcc_p) |
c906108c | 1074 | { |
c906108c SS |
1075 | int ii; |
1076 | CORE_ADDR target_addr; | |
1077 | ||
7a78ae4e | 1078 | if (rs6000_find_toc_address_hook != NULL) |
f6077098 | 1079 | { |
7a78ae4e | 1080 | CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (fun); |
2188cbdd EZ |
1081 | write_register (gdbarch_tdep (current_gdbarch)->ppc_toc_regnum, |
1082 | tocvalue); | |
f6077098 | 1083 | } |
c906108c SS |
1084 | } |
1085 | ||
11269d7e AC |
1086 | /* All the ABI's require 16 byte alignment. */ |
1087 | static CORE_ADDR | |
1088 | rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
1089 | { | |
1090 | return (addr & -16); | |
1091 | } | |
1092 | ||
7a78ae4e | 1093 | /* Pass the arguments in either registers, or in the stack. In RS/6000, |
c906108c SS |
1094 | the first eight words of the argument list (that might be less than |
1095 | eight parameters if some parameters occupy more than one word) are | |
7a78ae4e | 1096 | passed in r3..r10 registers. float and double parameters are |
64366f1c EZ |
1097 | passed in fpr's, in addition to that. Rest of the parameters if any |
1098 | are passed in user stack. There might be cases in which half of the | |
c906108c SS |
1099 | parameter is copied into registers, the other half is pushed into |
1100 | stack. | |
1101 | ||
7a78ae4e ND |
1102 | Stack must be aligned on 64-bit boundaries when synthesizing |
1103 | function calls. | |
1104 | ||
c906108c SS |
1105 | If the function is returning a structure, then the return address is passed |
1106 | in r3, then the first 7 words of the parameters can be passed in registers, | |
64366f1c | 1107 | starting from r4. */ |
c906108c | 1108 | |
7a78ae4e | 1109 | static CORE_ADDR |
ea7c478f | 1110 | rs6000_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
7a78ae4e | 1111 | int struct_return, CORE_ADDR struct_addr) |
c906108c SS |
1112 | { |
1113 | int ii; | |
1114 | int len = 0; | |
c5aa993b JM |
1115 | int argno; /* current argument number */ |
1116 | int argbytes; /* current argument byte */ | |
1117 | char tmp_buffer[50]; | |
1118 | int f_argno = 0; /* current floating point argno */ | |
21283beb | 1119 | int wordsize = gdbarch_tdep (current_gdbarch)->wordsize; |
c906108c | 1120 | |
ea7c478f | 1121 | struct value *arg = 0; |
c906108c SS |
1122 | struct type *type; |
1123 | ||
1124 | CORE_ADDR saved_sp; | |
1125 | ||
64366f1c EZ |
1126 | /* The first eight words of ther arguments are passed in registers. |
1127 | Copy them appropriately. | |
c906108c SS |
1128 | |
1129 | If the function is returning a `struct', then the first word (which | |
64366f1c | 1130 | will be passed in r3) is used for struct return address. In that |
c906108c | 1131 | case we should advance one word and start from r4 register to copy |
64366f1c | 1132 | parameters. */ |
c906108c | 1133 | |
c5aa993b | 1134 | ii = struct_return ? 1 : 0; |
c906108c SS |
1135 | |
1136 | /* | |
c5aa993b JM |
1137 | effectively indirect call... gcc does... |
1138 | ||
1139 | return_val example( float, int); | |
1140 | ||
1141 | eabi: | |
1142 | float in fp0, int in r3 | |
1143 | offset of stack on overflow 8/16 | |
1144 | for varargs, must go by type. | |
1145 | power open: | |
1146 | float in r3&r4, int in r5 | |
1147 | offset of stack on overflow different | |
1148 | both: | |
1149 | return in r3 or f0. If no float, must study how gcc emulates floats; | |
1150 | pay attention to arg promotion. | |
1151 | User may have to cast\args to handle promotion correctly | |
1152 | since gdb won't know if prototype supplied or not. | |
1153 | */ | |
c906108c | 1154 | |
c5aa993b JM |
1155 | for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii) |
1156 | { | |
f6077098 | 1157 | int reg_size = REGISTER_RAW_SIZE (ii + 3); |
c5aa993b JM |
1158 | |
1159 | arg = args[argno]; | |
1160 | type = check_typedef (VALUE_TYPE (arg)); | |
1161 | len = TYPE_LENGTH (type); | |
1162 | ||
1163 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1164 | { | |
1165 | ||
64366f1c | 1166 | /* Floating point arguments are passed in fpr's, as well as gpr's. |
c5aa993b | 1167 | There are 13 fpr's reserved for passing parameters. At this point |
64366f1c | 1168 | there is no way we would run out of them. */ |
c5aa993b JM |
1169 | |
1170 | if (len > 8) | |
1171 | printf_unfiltered ( | |
1172 | "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno); | |
1173 | ||
524d7c18 | 1174 | memcpy (&deprecated_registers[REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)], |
c5aa993b JM |
1175 | VALUE_CONTENTS (arg), |
1176 | len); | |
1177 | ++f_argno; | |
1178 | } | |
1179 | ||
f6077098 | 1180 | if (len > reg_size) |
c5aa993b JM |
1181 | { |
1182 | ||
64366f1c | 1183 | /* Argument takes more than one register. */ |
c5aa993b JM |
1184 | while (argbytes < len) |
1185 | { | |
524d7c18 AC |
1186 | memset (&deprecated_registers[REGISTER_BYTE (ii + 3)], 0, |
1187 | reg_size); | |
1188 | memcpy (&deprecated_registers[REGISTER_BYTE (ii + 3)], | |
c5aa993b | 1189 | ((char *) VALUE_CONTENTS (arg)) + argbytes, |
f6077098 KB |
1190 | (len - argbytes) > reg_size |
1191 | ? reg_size : len - argbytes); | |
1192 | ++ii, argbytes += reg_size; | |
c5aa993b JM |
1193 | |
1194 | if (ii >= 8) | |
1195 | goto ran_out_of_registers_for_arguments; | |
1196 | } | |
1197 | argbytes = 0; | |
1198 | --ii; | |
1199 | } | |
1200 | else | |
64366f1c EZ |
1201 | { |
1202 | /* Argument can fit in one register. No problem. */ | |
d7449b42 | 1203 | int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0; |
524d7c18 AC |
1204 | memset (&deprecated_registers[REGISTER_BYTE (ii + 3)], 0, reg_size); |
1205 | memcpy ((char *)&deprecated_registers[REGISTER_BYTE (ii + 3)] + adj, | |
f6077098 | 1206 | VALUE_CONTENTS (arg), len); |
c5aa993b JM |
1207 | } |
1208 | ++argno; | |
c906108c | 1209 | } |
c906108c SS |
1210 | |
1211 | ran_out_of_registers_for_arguments: | |
1212 | ||
7a78ae4e | 1213 | saved_sp = read_sp (); |
cc9836a8 | 1214 | |
64366f1c | 1215 | /* Location for 8 parameters are always reserved. */ |
7a78ae4e | 1216 | sp -= wordsize * 8; |
f6077098 | 1217 | |
64366f1c | 1218 | /* Another six words for back chain, TOC register, link register, etc. */ |
7a78ae4e | 1219 | sp -= wordsize * 6; |
f6077098 | 1220 | |
64366f1c | 1221 | /* Stack pointer must be quadword aligned. */ |
7a78ae4e | 1222 | sp &= -16; |
c906108c | 1223 | |
64366f1c EZ |
1224 | /* If there are more arguments, allocate space for them in |
1225 | the stack, then push them starting from the ninth one. */ | |
c906108c | 1226 | |
c5aa993b JM |
1227 | if ((argno < nargs) || argbytes) |
1228 | { | |
1229 | int space = 0, jj; | |
c906108c | 1230 | |
c5aa993b JM |
1231 | if (argbytes) |
1232 | { | |
1233 | space += ((len - argbytes + 3) & -4); | |
1234 | jj = argno + 1; | |
1235 | } | |
1236 | else | |
1237 | jj = argno; | |
c906108c | 1238 | |
c5aa993b JM |
1239 | for (; jj < nargs; ++jj) |
1240 | { | |
ea7c478f | 1241 | struct value *val = args[jj]; |
c5aa993b JM |
1242 | space += ((TYPE_LENGTH (VALUE_TYPE (val))) + 3) & -4; |
1243 | } | |
c906108c | 1244 | |
64366f1c | 1245 | /* Add location required for the rest of the parameters. */ |
f6077098 | 1246 | space = (space + 15) & -16; |
c5aa993b | 1247 | sp -= space; |
c906108c | 1248 | |
64366f1c EZ |
1249 | /* This is another instance we need to be concerned about |
1250 | securing our stack space. If we write anything underneath %sp | |
1251 | (r1), we might conflict with the kernel who thinks he is free | |
1252 | to use this area. So, update %sp first before doing anything | |
1253 | else. */ | |
c906108c | 1254 | |
c5aa993b | 1255 | write_register (SP_REGNUM, sp); |
c906108c | 1256 | |
64366f1c EZ |
1257 | /* If the last argument copied into the registers didn't fit there |
1258 | completely, push the rest of it into stack. */ | |
c906108c | 1259 | |
c5aa993b JM |
1260 | if (argbytes) |
1261 | { | |
1262 | write_memory (sp + 24 + (ii * 4), | |
1263 | ((char *) VALUE_CONTENTS (arg)) + argbytes, | |
1264 | len - argbytes); | |
1265 | ++argno; | |
1266 | ii += ((len - argbytes + 3) & -4) / 4; | |
1267 | } | |
c906108c | 1268 | |
64366f1c | 1269 | /* Push the rest of the arguments into stack. */ |
c5aa993b JM |
1270 | for (; argno < nargs; ++argno) |
1271 | { | |
c906108c | 1272 | |
c5aa993b JM |
1273 | arg = args[argno]; |
1274 | type = check_typedef (VALUE_TYPE (arg)); | |
1275 | len = TYPE_LENGTH (type); | |
c906108c SS |
1276 | |
1277 | ||
64366f1c EZ |
1278 | /* Float types should be passed in fpr's, as well as in the |
1279 | stack. */ | |
c5aa993b JM |
1280 | if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13) |
1281 | { | |
c906108c | 1282 | |
c5aa993b JM |
1283 | if (len > 8) |
1284 | printf_unfiltered ( | |
1285 | "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno); | |
c906108c | 1286 | |
524d7c18 | 1287 | memcpy (&deprecated_registers[REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)], |
c5aa993b JM |
1288 | VALUE_CONTENTS (arg), |
1289 | len); | |
1290 | ++f_argno; | |
1291 | } | |
c906108c | 1292 | |
c5aa993b JM |
1293 | write_memory (sp + 24 + (ii * 4), (char *) VALUE_CONTENTS (arg), len); |
1294 | ii += ((len + 3) & -4) / 4; | |
1295 | } | |
c906108c | 1296 | } |
c906108c | 1297 | else |
64366f1c | 1298 | /* Secure stack areas first, before doing anything else. */ |
c906108c SS |
1299 | write_register (SP_REGNUM, sp); |
1300 | ||
c906108c | 1301 | /* set back chain properly */ |
fbd9dcd3 | 1302 | store_unsigned_integer (tmp_buffer, 4, saved_sp); |
c906108c SS |
1303 | write_memory (sp, tmp_buffer, 4); |
1304 | ||
1305 | target_store_registers (-1); | |
1306 | return sp; | |
1307 | } | |
c906108c SS |
1308 | |
1309 | /* Function: ppc_push_return_address (pc, sp) | |
64366f1c | 1310 | Set up the return address for the inferior function call. */ |
c906108c | 1311 | |
7a78ae4e ND |
1312 | static CORE_ADDR |
1313 | ppc_push_return_address (CORE_ADDR pc, CORE_ADDR sp) | |
c906108c | 1314 | { |
2188cbdd EZ |
1315 | write_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum, |
1316 | CALL_DUMMY_ADDRESS ()); | |
c906108c SS |
1317 | return sp; |
1318 | } | |
1319 | ||
7a78ae4e | 1320 | /* Extract a function return value of type TYPE from raw register array |
64366f1c | 1321 | REGBUF, and copy that return value into VALBUF in virtual format. */ |
96ff0de4 | 1322 | static void |
46d79c04 | 1323 | e500_extract_return_value (struct type *valtype, struct regcache *regbuf, void *valbuf) |
96ff0de4 EZ |
1324 | { |
1325 | int offset = 0; | |
1326 | int vallen = TYPE_LENGTH (valtype); | |
1327 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1328 | ||
1329 | if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY | |
1330 | && vallen == 8 | |
1331 | && TYPE_VECTOR (valtype)) | |
1332 | { | |
1333 | regcache_raw_read (regbuf, tdep->ppc_ev0_regnum + 3, valbuf); | |
1334 | } | |
1335 | else | |
1336 | { | |
1337 | /* Return value is copied starting from r3. Note that r3 for us | |
1338 | is a pseudo register. */ | |
1339 | int offset = 0; | |
1340 | int return_regnum = tdep->ppc_gp0_regnum + 3; | |
1341 | int reg_size = REGISTER_RAW_SIZE (return_regnum); | |
1342 | int reg_part_size; | |
1343 | char *val_buffer; | |
1344 | int copied = 0; | |
1345 | int i = 0; | |
1346 | ||
1347 | /* Compute where we will start storing the value from. */ | |
1348 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1349 | { | |
1350 | if (vallen <= reg_size) | |
1351 | offset = reg_size - vallen; | |
1352 | else | |
1353 | offset = reg_size + (reg_size - vallen); | |
1354 | } | |
1355 | ||
1356 | /* How big does the local buffer need to be? */ | |
1357 | if (vallen <= reg_size) | |
1358 | val_buffer = alloca (reg_size); | |
1359 | else | |
1360 | val_buffer = alloca (vallen); | |
1361 | ||
1362 | /* Read all we need into our private buffer. We copy it in | |
1363 | chunks that are as long as one register, never shorter, even | |
1364 | if the value is smaller than the register. */ | |
1365 | while (copied < vallen) | |
1366 | { | |
1367 | reg_part_size = REGISTER_RAW_SIZE (return_regnum + i); | |
1368 | /* It is a pseudo/cooked register. */ | |
1369 | regcache_cooked_read (regbuf, return_regnum + i, | |
1370 | val_buffer + copied); | |
1371 | copied += reg_part_size; | |
1372 | i++; | |
1373 | } | |
1374 | /* Put the stuff in the return buffer. */ | |
1375 | memcpy (valbuf, val_buffer + offset, vallen); | |
1376 | } | |
1377 | } | |
c906108c | 1378 | |
7a78ae4e ND |
1379 | static void |
1380 | rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf) | |
c906108c SS |
1381 | { |
1382 | int offset = 0; | |
ace1378a | 1383 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 1384 | |
c5aa993b JM |
1385 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT) |
1386 | { | |
c906108c | 1387 | |
c5aa993b JM |
1388 | double dd; |
1389 | float ff; | |
1390 | /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes. | |
1391 | We need to truncate the return value into float size (4 byte) if | |
64366f1c | 1392 | necessary. */ |
c906108c | 1393 | |
c5aa993b JM |
1394 | if (TYPE_LENGTH (valtype) > 4) /* this is a double */ |
1395 | memcpy (valbuf, | |
1396 | ®buf[REGISTER_BYTE (FP0_REGNUM + 1)], | |
1397 | TYPE_LENGTH (valtype)); | |
1398 | else | |
1399 | { /* float */ | |
1400 | memcpy (&dd, ®buf[REGISTER_BYTE (FP0_REGNUM + 1)], 8); | |
1401 | ff = (float) dd; | |
1402 | memcpy (valbuf, &ff, sizeof (float)); | |
1403 | } | |
1404 | } | |
ace1378a EZ |
1405 | else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY |
1406 | && TYPE_LENGTH (valtype) == 16 | |
1407 | && TYPE_VECTOR (valtype)) | |
1408 | { | |
1409 | memcpy (valbuf, regbuf + REGISTER_BYTE (tdep->ppc_vr0_regnum + 2), | |
1410 | TYPE_LENGTH (valtype)); | |
1411 | } | |
c5aa993b JM |
1412 | else |
1413 | { | |
1414 | /* return value is copied starting from r3. */ | |
d7449b42 | 1415 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
c5aa993b JM |
1416 | && TYPE_LENGTH (valtype) < REGISTER_RAW_SIZE (3)) |
1417 | offset = REGISTER_RAW_SIZE (3) - TYPE_LENGTH (valtype); | |
1418 | ||
1419 | memcpy (valbuf, | |
1420 | regbuf + REGISTER_BYTE (3) + offset, | |
c906108c | 1421 | TYPE_LENGTH (valtype)); |
c906108c | 1422 | } |
c906108c SS |
1423 | } |
1424 | ||
977adac5 ND |
1425 | /* Return whether handle_inferior_event() should proceed through code |
1426 | starting at PC in function NAME when stepping. | |
1427 | ||
1428 | The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to | |
1429 | handle memory references that are too distant to fit in instructions | |
1430 | generated by the compiler. For example, if 'foo' in the following | |
1431 | instruction: | |
1432 | ||
1433 | lwz r9,foo(r2) | |
1434 | ||
1435 | is greater than 32767, the linker might replace the lwz with a branch to | |
1436 | somewhere in @FIX1 that does the load in 2 instructions and then branches | |
1437 | back to where execution should continue. | |
1438 | ||
1439 | GDB should silently step over @FIX code, just like AIX dbx does. | |
1440 | Unfortunately, the linker uses the "b" instruction for the branches, | |
1441 | meaning that the link register doesn't get set. Therefore, GDB's usual | |
1442 | step_over_function() mechanism won't work. | |
1443 | ||
1444 | Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks | |
1445 | in handle_inferior_event() to skip past @FIX code. */ | |
1446 | ||
1447 | int | |
1448 | rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name) | |
1449 | { | |
1450 | return name && !strncmp (name, "@FIX", 4); | |
1451 | } | |
1452 | ||
1453 | /* Skip code that the user doesn't want to see when stepping: | |
1454 | ||
1455 | 1. Indirect function calls use a piece of trampoline code to do context | |
1456 | switching, i.e. to set the new TOC table. Skip such code if we are on | |
1457 | its first instruction (as when we have single-stepped to here). | |
1458 | ||
1459 | 2. Skip shared library trampoline code (which is different from | |
c906108c | 1460 | indirect function call trampolines). |
977adac5 ND |
1461 | |
1462 | 3. Skip bigtoc fixup code. | |
1463 | ||
c906108c | 1464 | Result is desired PC to step until, or NULL if we are not in |
977adac5 | 1465 | code that should be skipped. */ |
c906108c SS |
1466 | |
1467 | CORE_ADDR | |
7a78ae4e | 1468 | rs6000_skip_trampoline_code (CORE_ADDR pc) |
c906108c SS |
1469 | { |
1470 | register unsigned int ii, op; | |
977adac5 | 1471 | int rel; |
c906108c | 1472 | CORE_ADDR solib_target_pc; |
977adac5 | 1473 | struct minimal_symbol *msymbol; |
c906108c | 1474 | |
c5aa993b JM |
1475 | static unsigned trampoline_code[] = |
1476 | { | |
1477 | 0x800b0000, /* l r0,0x0(r11) */ | |
1478 | 0x90410014, /* st r2,0x14(r1) */ | |
1479 | 0x7c0903a6, /* mtctr r0 */ | |
1480 | 0x804b0004, /* l r2,0x4(r11) */ | |
1481 | 0x816b0008, /* l r11,0x8(r11) */ | |
1482 | 0x4e800420, /* bctr */ | |
1483 | 0x4e800020, /* br */ | |
1484 | 0 | |
c906108c SS |
1485 | }; |
1486 | ||
977adac5 ND |
1487 | /* Check for bigtoc fixup code. */ |
1488 | msymbol = lookup_minimal_symbol_by_pc (pc); | |
22abf04a | 1489 | if (msymbol && rs6000_in_solib_return_trampoline (pc, DEPRECATED_SYMBOL_NAME (msymbol))) |
977adac5 ND |
1490 | { |
1491 | /* Double-check that the third instruction from PC is relative "b". */ | |
1492 | op = read_memory_integer (pc + 8, 4); | |
1493 | if ((op & 0xfc000003) == 0x48000000) | |
1494 | { | |
1495 | /* Extract bits 6-29 as a signed 24-bit relative word address and | |
1496 | add it to the containing PC. */ | |
1497 | rel = ((int)(op << 6) >> 6); | |
1498 | return pc + 8 + rel; | |
1499 | } | |
1500 | } | |
1501 | ||
c906108c SS |
1502 | /* If pc is in a shared library trampoline, return its target. */ |
1503 | solib_target_pc = find_solib_trampoline_target (pc); | |
1504 | if (solib_target_pc) | |
1505 | return solib_target_pc; | |
1506 | ||
c5aa993b JM |
1507 | for (ii = 0; trampoline_code[ii]; ++ii) |
1508 | { | |
1509 | op = read_memory_integer (pc + (ii * 4), 4); | |
1510 | if (op != trampoline_code[ii]) | |
1511 | return 0; | |
1512 | } | |
1513 | ii = read_register (11); /* r11 holds destination addr */ | |
21283beb | 1514 | pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */ |
c906108c SS |
1515 | return pc; |
1516 | } | |
1517 | ||
1518 | /* Determines whether the function FI has a frame on the stack or not. */ | |
1519 | ||
9aa1e687 | 1520 | int |
c877c8e6 | 1521 | rs6000_frameless_function_invocation (struct frame_info *fi) |
c906108c SS |
1522 | { |
1523 | CORE_ADDR func_start; | |
1524 | struct rs6000_framedata fdata; | |
1525 | ||
1526 | /* Don't even think about framelessness except on the innermost frame | |
1527 | or if the function was interrupted by a signal. */ | |
75e3c1f9 AC |
1528 | if (get_next_frame (fi) != NULL |
1529 | && !(get_frame_type (get_next_frame (fi)) == SIGTRAMP_FRAME)) | |
c906108c | 1530 | return 0; |
c5aa993b | 1531 | |
be41e9f4 | 1532 | func_start = get_frame_func (fi); |
c906108c SS |
1533 | |
1534 | /* If we failed to find the start of the function, it is a mistake | |
64366f1c | 1535 | to inspect the instructions. */ |
c906108c SS |
1536 | |
1537 | if (!func_start) | |
1538 | { | |
1539 | /* A frame with a zero PC is usually created by dereferencing a NULL | |
c5aa993b | 1540 | function pointer, normally causing an immediate core dump of the |
64366f1c | 1541 | inferior. Mark function as frameless, as the inferior has no chance |
c5aa993b | 1542 | of setting up a stack frame. */ |
bdd78e62 | 1543 | if (get_frame_pc (fi) == 0) |
c906108c SS |
1544 | return 1; |
1545 | else | |
1546 | return 0; | |
1547 | } | |
1548 | ||
bdd78e62 | 1549 | (void) skip_prologue (func_start, get_frame_pc (fi), &fdata); |
c906108c SS |
1550 | return fdata.frameless; |
1551 | } | |
1552 | ||
64366f1c | 1553 | /* Return the PC saved in a frame. */ |
c906108c | 1554 | |
9aa1e687 | 1555 | CORE_ADDR |
c877c8e6 | 1556 | rs6000_frame_saved_pc (struct frame_info *fi) |
c906108c SS |
1557 | { |
1558 | CORE_ADDR func_start; | |
1559 | struct rs6000_framedata fdata; | |
21283beb | 1560 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
a88376a3 | 1561 | int wordsize = tdep->wordsize; |
c906108c | 1562 | |
5a203e44 | 1563 | if ((get_frame_type (fi) == SIGTRAMP_FRAME)) |
8b36eed8 AC |
1564 | return read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET, |
1565 | wordsize); | |
c906108c | 1566 | |
bdd78e62 | 1567 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), |
8b36eed8 AC |
1568 | get_frame_base (fi), |
1569 | get_frame_base (fi))) | |
bdd78e62 | 1570 | return deprecated_read_register_dummy (get_frame_pc (fi), |
8b36eed8 | 1571 | get_frame_base (fi), PC_REGNUM); |
c906108c | 1572 | |
be41e9f4 | 1573 | func_start = get_frame_func (fi); |
c906108c SS |
1574 | |
1575 | /* If we failed to find the start of the function, it is a mistake | |
64366f1c | 1576 | to inspect the instructions. */ |
c906108c SS |
1577 | if (!func_start) |
1578 | return 0; | |
1579 | ||
bdd78e62 | 1580 | (void) skip_prologue (func_start, get_frame_pc (fi), &fdata); |
c906108c | 1581 | |
75e3c1f9 | 1582 | if (fdata.lr_offset == 0 && get_next_frame (fi) != NULL) |
c906108c | 1583 | { |
75e3c1f9 | 1584 | if ((get_frame_type (get_next_frame (fi)) == SIGTRAMP_FRAME)) |
8b36eed8 AC |
1585 | return read_memory_addr ((get_frame_base (get_next_frame (fi)) |
1586 | + SIG_FRAME_LR_OFFSET), | |
7a78ae4e | 1587 | wordsize); |
bdd78e62 | 1588 | else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (get_next_frame (fi)), 0, 0)) |
8b69000d AC |
1589 | /* The link register wasn't saved by this frame and the next |
1590 | (inner, newer) frame is a dummy. Get the link register | |
1591 | value by unwinding it from that [dummy] frame. */ | |
1592 | { | |
1593 | ULONGEST lr; | |
1594 | frame_unwind_unsigned_register (get_next_frame (fi), | |
1595 | tdep->ppc_lr_regnum, &lr); | |
1596 | return lr; | |
1597 | } | |
c906108c | 1598 | else |
618ce49f AC |
1599 | return read_memory_addr (DEPRECATED_FRAME_CHAIN (fi) |
1600 | + tdep->lr_frame_offset, | |
7a78ae4e | 1601 | wordsize); |
c906108c SS |
1602 | } |
1603 | ||
1604 | if (fdata.lr_offset == 0) | |
2188cbdd | 1605 | return read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum); |
c906108c | 1606 | |
618ce49f AC |
1607 | return read_memory_addr (DEPRECATED_FRAME_CHAIN (fi) + fdata.lr_offset, |
1608 | wordsize); | |
c906108c SS |
1609 | } |
1610 | ||
1611 | /* If saved registers of frame FI are not known yet, read and cache them. | |
1612 | &FDATAP contains rs6000_framedata; TDATAP can be NULL, | |
1613 | in which case the framedata are read. */ | |
1614 | ||
1615 | static void | |
7a78ae4e | 1616 | frame_get_saved_regs (struct frame_info *fi, struct rs6000_framedata *fdatap) |
c906108c | 1617 | { |
c5aa993b | 1618 | CORE_ADDR frame_addr; |
c906108c | 1619 | struct rs6000_framedata work_fdata; |
6be8bc0c EZ |
1620 | struct gdbarch_tdep * tdep = gdbarch_tdep (current_gdbarch); |
1621 | int wordsize = tdep->wordsize; | |
c906108c | 1622 | |
c9012c71 | 1623 | if (get_frame_saved_regs (fi)) |
c906108c | 1624 | return; |
c5aa993b | 1625 | |
c906108c SS |
1626 | if (fdatap == NULL) |
1627 | { | |
1628 | fdatap = &work_fdata; | |
be41e9f4 | 1629 | (void) skip_prologue (get_frame_func (fi), get_frame_pc (fi), fdatap); |
c906108c SS |
1630 | } |
1631 | ||
1632 | frame_saved_regs_zalloc (fi); | |
1633 | ||
1634 | /* If there were any saved registers, figure out parent's stack | |
64366f1c | 1635 | pointer. */ |
c906108c | 1636 | /* The following is true only if the frame doesn't have a call to |
64366f1c | 1637 | alloca(), FIXME. */ |
c906108c | 1638 | |
6be8bc0c EZ |
1639 | if (fdatap->saved_fpr == 0 |
1640 | && fdatap->saved_gpr == 0 | |
1641 | && fdatap->saved_vr == 0 | |
96ff0de4 | 1642 | && fdatap->saved_ev == 0 |
6be8bc0c EZ |
1643 | && fdatap->lr_offset == 0 |
1644 | && fdatap->cr_offset == 0 | |
96ff0de4 EZ |
1645 | && fdatap->vr_offset == 0 |
1646 | && fdatap->ev_offset == 0) | |
c906108c | 1647 | frame_addr = 0; |
c906108c | 1648 | else |
bf75c8c1 AC |
1649 | /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most |
1650 | address of the current frame. Things might be easier if the | |
1651 | ->frame pointed to the outer-most address of the frame. In the | |
1652 | mean time, the address of the prev frame is used as the base | |
1653 | address of this frame. */ | |
618ce49f | 1654 | frame_addr = DEPRECATED_FRAME_CHAIN (fi); |
c5aa993b | 1655 | |
c906108c SS |
1656 | /* if != -1, fdatap->saved_fpr is the smallest number of saved_fpr. |
1657 | All fpr's from saved_fpr to fp31 are saved. */ | |
1658 | ||
1659 | if (fdatap->saved_fpr >= 0) | |
1660 | { | |
1661 | int i; | |
7a78ae4e | 1662 | CORE_ADDR fpr_addr = frame_addr + fdatap->fpr_offset; |
c906108c SS |
1663 | for (i = fdatap->saved_fpr; i < 32; i++) |
1664 | { | |
c9012c71 | 1665 | get_frame_saved_regs (fi)[FP0_REGNUM + i] = fpr_addr; |
7a78ae4e | 1666 | fpr_addr += 8; |
c906108c SS |
1667 | } |
1668 | } | |
1669 | ||
1670 | /* if != -1, fdatap->saved_gpr is the smallest number of saved_gpr. | |
1671 | All gpr's from saved_gpr to gpr31 are saved. */ | |
1672 | ||
1673 | if (fdatap->saved_gpr >= 0) | |
1674 | { | |
1675 | int i; | |
7a78ae4e | 1676 | CORE_ADDR gpr_addr = frame_addr + fdatap->gpr_offset; |
c906108c SS |
1677 | for (i = fdatap->saved_gpr; i < 32; i++) |
1678 | { | |
366cfc9e | 1679 | get_frame_saved_regs (fi)[tdep->ppc_gp0_regnum + i] = gpr_addr; |
7a78ae4e | 1680 | gpr_addr += wordsize; |
c906108c SS |
1681 | } |
1682 | } | |
1683 | ||
6be8bc0c EZ |
1684 | /* if != -1, fdatap->saved_vr is the smallest number of saved_vr. |
1685 | All vr's from saved_vr to vr31 are saved. */ | |
1686 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
1687 | { | |
1688 | if (fdatap->saved_vr >= 0) | |
1689 | { | |
1690 | int i; | |
1691 | CORE_ADDR vr_addr = frame_addr + fdatap->vr_offset; | |
1692 | for (i = fdatap->saved_vr; i < 32; i++) | |
1693 | { | |
c9012c71 | 1694 | get_frame_saved_regs (fi)[tdep->ppc_vr0_regnum + i] = vr_addr; |
6be8bc0c EZ |
1695 | vr_addr += REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum); |
1696 | } | |
1697 | } | |
1698 | } | |
1699 | ||
96ff0de4 EZ |
1700 | /* if != -1, fdatap->saved_ev is the smallest number of saved_ev. |
1701 | All vr's from saved_ev to ev31 are saved. ????? */ | |
1702 | if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1) | |
1703 | { | |
1704 | if (fdatap->saved_ev >= 0) | |
1705 | { | |
1706 | int i; | |
1707 | CORE_ADDR ev_addr = frame_addr + fdatap->ev_offset; | |
1708 | for (i = fdatap->saved_ev; i < 32; i++) | |
1709 | { | |
c9012c71 AC |
1710 | get_frame_saved_regs (fi)[tdep->ppc_ev0_regnum + i] = ev_addr; |
1711 | get_frame_saved_regs (fi)[tdep->ppc_gp0_regnum + i] = ev_addr + 4; | |
96ff0de4 EZ |
1712 | ev_addr += REGISTER_RAW_SIZE (tdep->ppc_ev0_regnum); |
1713 | } | |
1714 | } | |
1715 | } | |
1716 | ||
c906108c SS |
1717 | /* If != 0, fdatap->cr_offset is the offset from the frame that holds |
1718 | the CR. */ | |
1719 | if (fdatap->cr_offset != 0) | |
c9012c71 | 1720 | get_frame_saved_regs (fi)[tdep->ppc_cr_regnum] = frame_addr + fdatap->cr_offset; |
c906108c SS |
1721 | |
1722 | /* If != 0, fdatap->lr_offset is the offset from the frame that holds | |
1723 | the LR. */ | |
1724 | if (fdatap->lr_offset != 0) | |
c9012c71 | 1725 | get_frame_saved_regs (fi)[tdep->ppc_lr_regnum] = frame_addr + fdatap->lr_offset; |
6be8bc0c EZ |
1726 | |
1727 | /* If != 0, fdatap->vrsave_offset is the offset from the frame that holds | |
1728 | the VRSAVE. */ | |
1729 | if (fdatap->vrsave_offset != 0) | |
c9012c71 | 1730 | get_frame_saved_regs (fi)[tdep->ppc_vrsave_regnum] = frame_addr + fdatap->vrsave_offset; |
c906108c SS |
1731 | } |
1732 | ||
1733 | /* Return the address of a frame. This is the inital %sp value when the frame | |
64366f1c EZ |
1734 | was first allocated. For functions calling alloca(), it might be saved in |
1735 | an alloca register. */ | |
c906108c SS |
1736 | |
1737 | static CORE_ADDR | |
7a78ae4e | 1738 | frame_initial_stack_address (struct frame_info *fi) |
c906108c SS |
1739 | { |
1740 | CORE_ADDR tmpaddr; | |
1741 | struct rs6000_framedata fdata; | |
1742 | struct frame_info *callee_fi; | |
1743 | ||
64366f1c EZ |
1744 | /* If the initial stack pointer (frame address) of this frame is known, |
1745 | just return it. */ | |
c906108c | 1746 | |
c9012c71 AC |
1747 | if (get_frame_extra_info (fi)->initial_sp) |
1748 | return get_frame_extra_info (fi)->initial_sp; | |
c906108c | 1749 | |
64366f1c | 1750 | /* Find out if this function is using an alloca register. */ |
c906108c | 1751 | |
be41e9f4 | 1752 | (void) skip_prologue (get_frame_func (fi), get_frame_pc (fi), &fdata); |
c906108c | 1753 | |
64366f1c EZ |
1754 | /* If saved registers of this frame are not known yet, read and |
1755 | cache them. */ | |
c906108c | 1756 | |
c9012c71 | 1757 | if (!get_frame_saved_regs (fi)) |
c906108c SS |
1758 | frame_get_saved_regs (fi, &fdata); |
1759 | ||
1760 | /* If no alloca register used, then fi->frame is the value of the %sp for | |
64366f1c | 1761 | this frame, and it is good enough. */ |
c906108c SS |
1762 | |
1763 | if (fdata.alloca_reg < 0) | |
1764 | { | |
c9012c71 AC |
1765 | get_frame_extra_info (fi)->initial_sp = get_frame_base (fi); |
1766 | return get_frame_extra_info (fi)->initial_sp; | |
c906108c SS |
1767 | } |
1768 | ||
953836b2 AC |
1769 | /* There is an alloca register, use its value, in the current frame, |
1770 | as the initial stack pointer. */ | |
1771 | { | |
d9d9c31f | 1772 | char tmpbuf[MAX_REGISTER_SIZE]; |
953836b2 AC |
1773 | if (frame_register_read (fi, fdata.alloca_reg, tmpbuf)) |
1774 | { | |
c9012c71 | 1775 | get_frame_extra_info (fi)->initial_sp |
953836b2 AC |
1776 | = extract_unsigned_integer (tmpbuf, |
1777 | REGISTER_RAW_SIZE (fdata.alloca_reg)); | |
1778 | } | |
1779 | else | |
1780 | /* NOTE: cagney/2002-04-17: At present the only time | |
1781 | frame_register_read will fail is when the register isn't | |
1782 | available. If that does happen, use the frame. */ | |
c9012c71 | 1783 | get_frame_extra_info (fi)->initial_sp = get_frame_base (fi); |
953836b2 | 1784 | } |
c9012c71 | 1785 | return get_frame_extra_info (fi)->initial_sp; |
c906108c SS |
1786 | } |
1787 | ||
7a78ae4e ND |
1788 | /* Describe the pointer in each stack frame to the previous stack frame |
1789 | (its caller). */ | |
1790 | ||
618ce49f AC |
1791 | /* DEPRECATED_FRAME_CHAIN takes a frame's nominal address and produces |
1792 | the frame's chain-pointer. */ | |
7a78ae4e ND |
1793 | |
1794 | /* In the case of the RS/6000, the frame's nominal address | |
1795 | is the address of a 4-byte word containing the calling frame's address. */ | |
1796 | ||
9aa1e687 | 1797 | CORE_ADDR |
7a78ae4e | 1798 | rs6000_frame_chain (struct frame_info *thisframe) |
c906108c | 1799 | { |
7a78ae4e | 1800 | CORE_ADDR fp, fpp, lr; |
21283beb | 1801 | int wordsize = gdbarch_tdep (current_gdbarch)->wordsize; |
c906108c | 1802 | |
bdd78e62 | 1803 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (thisframe), |
8b36eed8 AC |
1804 | get_frame_base (thisframe), |
1805 | get_frame_base (thisframe))) | |
9f3b7f07 AC |
1806 | /* A dummy frame always correctly chains back to the previous |
1807 | frame. */ | |
8b36eed8 | 1808 | return read_memory_addr (get_frame_base (thisframe), wordsize); |
c906108c | 1809 | |
bdd78e62 AC |
1810 | if (inside_entry_file (get_frame_pc (thisframe)) |
1811 | || get_frame_pc (thisframe) == entry_point_address ()) | |
c906108c SS |
1812 | return 0; |
1813 | ||
5a203e44 | 1814 | if ((get_frame_type (thisframe) == SIGTRAMP_FRAME)) |
8b36eed8 AC |
1815 | fp = read_memory_addr (get_frame_base (thisframe) + SIG_FRAME_FP_OFFSET, |
1816 | wordsize); | |
75e3c1f9 AC |
1817 | else if (get_next_frame (thisframe) != NULL |
1818 | && (get_frame_type (get_next_frame (thisframe)) == SIGTRAMP_FRAME) | |
c877c8e6 | 1819 | && FRAMELESS_FUNCTION_INVOCATION (thisframe)) |
c906108c SS |
1820 | /* A frameless function interrupted by a signal did not change the |
1821 | frame pointer. */ | |
c193f6ac | 1822 | fp = get_frame_base (thisframe); |
c906108c | 1823 | else |
8b36eed8 | 1824 | fp = read_memory_addr (get_frame_base (thisframe), wordsize); |
7a78ae4e ND |
1825 | return fp; |
1826 | } | |
1827 | ||
1828 | /* Return the size of register REG when words are WORDSIZE bytes long. If REG | |
64366f1c | 1829 | isn't available with that word size, return 0. */ |
7a78ae4e ND |
1830 | |
1831 | static int | |
1832 | regsize (const struct reg *reg, int wordsize) | |
1833 | { | |
1834 | return wordsize == 8 ? reg->sz64 : reg->sz32; | |
1835 | } | |
1836 | ||
1837 | /* Return the name of register number N, or null if no such register exists | |
64366f1c | 1838 | in the current architecture. */ |
7a78ae4e | 1839 | |
fa88f677 | 1840 | static const char * |
7a78ae4e ND |
1841 | rs6000_register_name (int n) |
1842 | { | |
21283beb | 1843 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
1844 | const struct reg *reg = tdep->regs + n; |
1845 | ||
1846 | if (!regsize (reg, tdep->wordsize)) | |
1847 | return NULL; | |
1848 | return reg->name; | |
1849 | } | |
1850 | ||
1851 | /* Index within `registers' of the first byte of the space for | |
1852 | register N. */ | |
1853 | ||
1854 | static int | |
1855 | rs6000_register_byte (int n) | |
1856 | { | |
21283beb | 1857 | return gdbarch_tdep (current_gdbarch)->regoff[n]; |
7a78ae4e ND |
1858 | } |
1859 | ||
1860 | /* Return the number of bytes of storage in the actual machine representation | |
64366f1c | 1861 | for register N if that register is available, else return 0. */ |
7a78ae4e ND |
1862 | |
1863 | static int | |
1864 | rs6000_register_raw_size (int n) | |
1865 | { | |
21283beb | 1866 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
1867 | const struct reg *reg = tdep->regs + n; |
1868 | return regsize (reg, tdep->wordsize); | |
1869 | } | |
1870 | ||
7a78ae4e ND |
1871 | /* Return the GDB type object for the "standard" data type |
1872 | of data in register N. */ | |
1873 | ||
1874 | static struct type * | |
fba45db2 | 1875 | rs6000_register_virtual_type (int n) |
7a78ae4e | 1876 | { |
21283beb | 1877 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
1878 | const struct reg *reg = tdep->regs + n; |
1879 | ||
1fcc0bb8 EZ |
1880 | if (reg->fpr) |
1881 | return builtin_type_double; | |
1882 | else | |
1883 | { | |
1884 | int size = regsize (reg, tdep->wordsize); | |
1885 | switch (size) | |
1886 | { | |
1887 | case 8: | |
c8001721 EZ |
1888 | if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum) |
1889 | return builtin_type_vec64; | |
1890 | else | |
1891 | return builtin_type_int64; | |
1fcc0bb8 EZ |
1892 | break; |
1893 | case 16: | |
08cf96df | 1894 | return builtin_type_vec128; |
1fcc0bb8 EZ |
1895 | break; |
1896 | default: | |
1897 | return builtin_type_int32; | |
1898 | break; | |
1899 | } | |
1900 | } | |
7a78ae4e ND |
1901 | } |
1902 | ||
7a78ae4e ND |
1903 | /* Return whether register N requires conversion when moving from raw format |
1904 | to virtual format. | |
1905 | ||
1906 | The register format for RS/6000 floating point registers is always | |
64366f1c | 1907 | double, we need a conversion if the memory format is float. */ |
7a78ae4e ND |
1908 | |
1909 | static int | |
1910 | rs6000_register_convertible (int n) | |
1911 | { | |
21283beb | 1912 | const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + n; |
7a78ae4e ND |
1913 | return reg->fpr; |
1914 | } | |
1915 | ||
1916 | /* Convert data from raw format for register N in buffer FROM | |
64366f1c | 1917 | to virtual format with type TYPE in buffer TO. */ |
7a78ae4e ND |
1918 | |
1919 | static void | |
1920 | rs6000_register_convert_to_virtual (int n, struct type *type, | |
1921 | char *from, char *to) | |
1922 | { | |
1923 | if (TYPE_LENGTH (type) != REGISTER_RAW_SIZE (n)) | |
7a292a7a | 1924 | { |
f1908289 AC |
1925 | double val = deprecated_extract_floating (from, REGISTER_RAW_SIZE (n)); |
1926 | deprecated_store_floating (to, TYPE_LENGTH (type), val); | |
7a78ae4e ND |
1927 | } |
1928 | else | |
1929 | memcpy (to, from, REGISTER_RAW_SIZE (n)); | |
1930 | } | |
1931 | ||
1932 | /* Convert data from virtual format with type TYPE in buffer FROM | |
64366f1c | 1933 | to raw format for register N in buffer TO. */ |
7a292a7a | 1934 | |
7a78ae4e ND |
1935 | static void |
1936 | rs6000_register_convert_to_raw (struct type *type, int n, | |
1937 | char *from, char *to) | |
1938 | { | |
1939 | if (TYPE_LENGTH (type) != REGISTER_RAW_SIZE (n)) | |
1940 | { | |
f1908289 AC |
1941 | double val = deprecated_extract_floating (from, TYPE_LENGTH (type)); |
1942 | deprecated_store_floating (to, REGISTER_RAW_SIZE (n), val); | |
7a292a7a | 1943 | } |
7a78ae4e ND |
1944 | else |
1945 | memcpy (to, from, REGISTER_RAW_SIZE (n)); | |
1946 | } | |
c906108c | 1947 | |
c8001721 EZ |
1948 | static void |
1949 | e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
1950 | int reg_nr, void *buffer) | |
1951 | { | |
1952 | int base_regnum; | |
1953 | int offset = 0; | |
d9d9c31f | 1954 | char temp_buffer[MAX_REGISTER_SIZE]; |
c8001721 EZ |
1955 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1956 | ||
1957 | if (reg_nr >= tdep->ppc_gp0_regnum | |
1958 | && reg_nr <= tdep->ppc_gplast_regnum) | |
1959 | { | |
1960 | base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum; | |
1961 | ||
1962 | /* Build the value in the provided buffer. */ | |
1963 | /* Read the raw register of which this one is the lower portion. */ | |
1964 | regcache_raw_read (regcache, base_regnum, temp_buffer); | |
1965 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1966 | offset = 4; | |
1967 | memcpy ((char *) buffer, temp_buffer + offset, 4); | |
1968 | } | |
1969 | } | |
1970 | ||
1971 | static void | |
1972 | e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
1973 | int reg_nr, const void *buffer) | |
1974 | { | |
1975 | int base_regnum; | |
1976 | int offset = 0; | |
d9d9c31f | 1977 | char temp_buffer[MAX_REGISTER_SIZE]; |
c8001721 EZ |
1978 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1979 | ||
1980 | if (reg_nr >= tdep->ppc_gp0_regnum | |
1981 | && reg_nr <= tdep->ppc_gplast_regnum) | |
1982 | { | |
1983 | base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum; | |
1984 | /* reg_nr is 32 bit here, and base_regnum is 64 bits. */ | |
1985 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1986 | offset = 4; | |
1987 | ||
1988 | /* Let's read the value of the base register into a temporary | |
1989 | buffer, so that overwriting the last four bytes with the new | |
1990 | value of the pseudo will leave the upper 4 bytes unchanged. */ | |
1991 | regcache_raw_read (regcache, base_regnum, temp_buffer); | |
1992 | ||
1993 | /* Write as an 8 byte quantity. */ | |
1994 | memcpy (temp_buffer + offset, (char *) buffer, 4); | |
1995 | regcache_raw_write (regcache, base_regnum, temp_buffer); | |
1996 | } | |
1997 | } | |
1998 | ||
1999 | /* Convert a dwarf2 register number to a gdb REGNUM. */ | |
2000 | static int | |
2001 | e500_dwarf2_reg_to_regnum (int num) | |
2002 | { | |
2003 | int regnum; | |
2004 | if (0 <= num && num <= 31) | |
2005 | return num + gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum; | |
2006 | else | |
2007 | return num; | |
2008 | } | |
2009 | ||
2188cbdd | 2010 | /* Convert a dbx stab register number (from `r' declaration) to a gdb |
64366f1c | 2011 | REGNUM. */ |
2188cbdd EZ |
2012 | static int |
2013 | rs6000_stab_reg_to_regnum (int num) | |
2014 | { | |
2015 | int regnum; | |
2016 | switch (num) | |
2017 | { | |
2018 | case 64: | |
2019 | regnum = gdbarch_tdep (current_gdbarch)->ppc_mq_regnum; | |
2020 | break; | |
2021 | case 65: | |
2022 | regnum = gdbarch_tdep (current_gdbarch)->ppc_lr_regnum; | |
2023 | break; | |
2024 | case 66: | |
2025 | regnum = gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum; | |
2026 | break; | |
2027 | case 76: | |
2028 | regnum = gdbarch_tdep (current_gdbarch)->ppc_xer_regnum; | |
2029 | break; | |
2030 | default: | |
2031 | regnum = num; | |
2032 | break; | |
2033 | } | |
2034 | return regnum; | |
2035 | } | |
2036 | ||
7a78ae4e | 2037 | /* Store the address of the place in which to copy the structure the |
11269d7e | 2038 | subroutine will return. */ |
7a78ae4e ND |
2039 | |
2040 | static void | |
2041 | rs6000_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
2042 | { | |
da3eff49 AC |
2043 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2044 | write_register (tdep->ppc_gp0_regnum + 3, addr); | |
7a78ae4e ND |
2045 | } |
2046 | ||
2047 | /* Write into appropriate registers a function return value | |
2048 | of type TYPE, given in virtual format. */ | |
96ff0de4 EZ |
2049 | static void |
2050 | e500_store_return_value (struct type *type, char *valbuf) | |
2051 | { | |
2052 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2053 | ||
2054 | /* Everything is returned in GPR3 and up. */ | |
2055 | int copied = 0; | |
2056 | int i = 0; | |
2057 | int len = TYPE_LENGTH (type); | |
2058 | while (copied < len) | |
2059 | { | |
2060 | int regnum = gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum + 3 + i; | |
2061 | int reg_size = REGISTER_RAW_SIZE (regnum); | |
2062 | char *reg_val_buf = alloca (reg_size); | |
2063 | ||
2064 | memcpy (reg_val_buf, valbuf + copied, reg_size); | |
2065 | copied += reg_size; | |
4caf0990 | 2066 | deprecated_write_register_gen (regnum, reg_val_buf); |
96ff0de4 EZ |
2067 | i++; |
2068 | } | |
2069 | } | |
7a78ae4e ND |
2070 | |
2071 | static void | |
2072 | rs6000_store_return_value (struct type *type, char *valbuf) | |
2073 | { | |
ace1378a EZ |
2074 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2075 | ||
7a78ae4e ND |
2076 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
2077 | ||
2078 | /* Floating point values are returned starting from FPR1 and up. | |
2079 | Say a double_double_double type could be returned in | |
64366f1c | 2080 | FPR1/FPR2/FPR3 triple. */ |
7a78ae4e | 2081 | |
73937e03 AC |
2082 | deprecated_write_register_bytes (REGISTER_BYTE (FP0_REGNUM + 1), valbuf, |
2083 | TYPE_LENGTH (type)); | |
ace1378a EZ |
2084 | else if (TYPE_CODE (type) == TYPE_CODE_ARRAY) |
2085 | { | |
2086 | if (TYPE_LENGTH (type) == 16 | |
2087 | && TYPE_VECTOR (type)) | |
73937e03 AC |
2088 | deprecated_write_register_bytes (REGISTER_BYTE (tdep->ppc_vr0_regnum + 2), |
2089 | valbuf, TYPE_LENGTH (type)); | |
ace1378a | 2090 | } |
7a78ae4e | 2091 | else |
64366f1c | 2092 | /* Everything else is returned in GPR3 and up. */ |
73937e03 AC |
2093 | deprecated_write_register_bytes (REGISTER_BYTE (gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum + 3), |
2094 | valbuf, TYPE_LENGTH (type)); | |
7a78ae4e ND |
2095 | } |
2096 | ||
2097 | /* Extract from an array REGBUF containing the (raw) register state | |
2098 | the address in which a function should return its structure value, | |
2099 | as a CORE_ADDR (or an expression that can be used as one). */ | |
2100 | ||
2101 | static CORE_ADDR | |
11269d7e AC |
2102 | rs6000_extract_struct_value_address (struct regcache *regcache) |
2103 | { | |
2104 | /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior | |
2105 | function call GDB knows the address of the struct return value | |
2106 | and hence, should not need to call this function. Unfortunately, | |
e8a8712a AC |
2107 | the current call_function_by_hand() code only saves the most |
2108 | recent struct address leading to occasional calls. The code | |
2109 | should instead maintain a stack of such addresses (in the dummy | |
2110 | frame object). */ | |
11269d7e AC |
2111 | /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've |
2112 | really got no idea where the return value is being stored. While | |
2113 | r3, on function entry, contained the address it will have since | |
2114 | been reused (scratch) and hence wouldn't be valid */ | |
2115 | return 0; | |
7a78ae4e ND |
2116 | } |
2117 | ||
2118 | /* Return whether PC is in a dummy function call. | |
2119 | ||
2120 | FIXME: This just checks for the end of the stack, which is broken | |
64366f1c | 2121 | for things like stepping through gcc nested function stubs. */ |
7a78ae4e ND |
2122 | |
2123 | static int | |
2124 | rs6000_pc_in_call_dummy (CORE_ADDR pc, CORE_ADDR sp, CORE_ADDR fp) | |
2125 | { | |
2126 | return sp < pc && pc < fp; | |
2127 | } | |
2128 | ||
64366f1c | 2129 | /* Hook called when a new child process is started. */ |
7a78ae4e ND |
2130 | |
2131 | void | |
2132 | rs6000_create_inferior (int pid) | |
2133 | { | |
2134 | if (rs6000_set_host_arch_hook) | |
2135 | rs6000_set_host_arch_hook (pid); | |
c906108c SS |
2136 | } |
2137 | \f | |
7a78ae4e ND |
2138 | /* Support for CONVERT_FROM_FUNC_PTR_ADDR(ADDR). |
2139 | ||
2140 | Usually a function pointer's representation is simply the address | |
2141 | of the function. On the RS/6000 however, a function pointer is | |
2142 | represented by a pointer to a TOC entry. This TOC entry contains | |
2143 | three words, the first word is the address of the function, the | |
2144 | second word is the TOC pointer (r2), and the third word is the | |
2145 | static chain value. Throughout GDB it is currently assumed that a | |
2146 | function pointer contains the address of the function, which is not | |
2147 | easy to fix. In addition, the conversion of a function address to | |
2148 | a function pointer would require allocation of a TOC entry in the | |
2149 | inferior's memory space, with all its drawbacks. To be able to | |
2150 | call C++ virtual methods in the inferior (which are called via | |
f517ea4e | 2151 | function pointers), find_function_addr uses this function to get the |
7a78ae4e ND |
2152 | function address from a function pointer. */ |
2153 | ||
f517ea4e PS |
2154 | /* Return real function address if ADDR (a function pointer) is in the data |
2155 | space and is therefore a special function pointer. */ | |
c906108c | 2156 | |
7a78ae4e ND |
2157 | CORE_ADDR |
2158 | rs6000_convert_from_func_ptr_addr (CORE_ADDR addr) | |
c906108c SS |
2159 | { |
2160 | struct obj_section *s; | |
2161 | ||
2162 | s = find_pc_section (addr); | |
2163 | if (s && s->the_bfd_section->flags & SEC_CODE) | |
7a78ae4e | 2164 | return addr; |
c906108c | 2165 | |
7a78ae4e | 2166 | /* ADDR is in the data space, so it's a special function pointer. */ |
21283beb | 2167 | return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize); |
c906108c | 2168 | } |
c906108c | 2169 | \f |
c5aa993b | 2170 | |
7a78ae4e | 2171 | /* Handling the various POWER/PowerPC variants. */ |
c906108c SS |
2172 | |
2173 | ||
7a78ae4e ND |
2174 | /* The arrays here called registers_MUMBLE hold information about available |
2175 | registers. | |
c906108c SS |
2176 | |
2177 | For each family of PPC variants, I've tried to isolate out the | |
2178 | common registers and put them up front, so that as long as you get | |
2179 | the general family right, GDB will correctly identify the registers | |
2180 | common to that family. The common register sets are: | |
2181 | ||
2182 | For the 60x family: hid0 hid1 iabr dabr pir | |
2183 | ||
2184 | For the 505 and 860 family: eie eid nri | |
2185 | ||
2186 | For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi | |
c5aa993b JM |
2187 | tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1 |
2188 | pbu1 pbl2 pbu2 | |
c906108c SS |
2189 | |
2190 | Most of these register groups aren't anything formal. I arrived at | |
2191 | them by looking at the registers that occurred in more than one | |
6f5987a6 KB |
2192 | processor. |
2193 | ||
2194 | Note: kevinb/2002-04-30: Support for the fpscr register was added | |
2195 | during April, 2002. Slot 70 is being used for PowerPC and slot 71 | |
2196 | for Power. For PowerPC, slot 70 was unused and was already in the | |
2197 | PPC_UISA_SPRS which is ideally where fpscr should go. For Power, | |
2198 | slot 70 was being used for "mq", so the next available slot (71) | |
2199 | was chosen. It would have been nice to be able to make the | |
2200 | register numbers the same across processor cores, but this wasn't | |
2201 | possible without either 1) renumbering some registers for some | |
2202 | processors or 2) assigning fpscr to a really high slot that's | |
2203 | larger than any current register number. Doing (1) is bad because | |
2204 | existing stubs would break. Doing (2) is undesirable because it | |
2205 | would introduce a really large gap between fpscr and the rest of | |
2206 | the registers for most processors. */ | |
7a78ae4e | 2207 | |
64366f1c | 2208 | /* Convenience macros for populating register arrays. */ |
7a78ae4e | 2209 | |
64366f1c | 2210 | /* Within another macro, convert S to a string. */ |
7a78ae4e ND |
2211 | |
2212 | #define STR(s) #s | |
2213 | ||
2214 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems | |
64366f1c | 2215 | and 64 bits on 64-bit systems. */ |
489461e2 | 2216 | #define R(name) { STR(name), 4, 8, 0, 0 } |
7a78ae4e ND |
2217 | |
2218 | /* Return a struct reg defining register NAME that's 32 bits on all | |
64366f1c | 2219 | systems. */ |
489461e2 | 2220 | #define R4(name) { STR(name), 4, 4, 0, 0 } |
7a78ae4e ND |
2221 | |
2222 | /* Return a struct reg defining register NAME that's 64 bits on all | |
64366f1c | 2223 | systems. */ |
489461e2 | 2224 | #define R8(name) { STR(name), 8, 8, 0, 0 } |
7a78ae4e | 2225 | |
1fcc0bb8 | 2226 | /* Return a struct reg defining register NAME that's 128 bits on all |
64366f1c | 2227 | systems. */ |
489461e2 | 2228 | #define R16(name) { STR(name), 16, 16, 0, 0 } |
1fcc0bb8 | 2229 | |
64366f1c | 2230 | /* Return a struct reg defining floating-point register NAME. */ |
489461e2 EZ |
2231 | #define F(name) { STR(name), 8, 8, 1, 0 } |
2232 | ||
64366f1c | 2233 | /* Return a struct reg defining a pseudo register NAME. */ |
489461e2 | 2234 | #define P(name) { STR(name), 4, 8, 0, 1} |
7a78ae4e ND |
2235 | |
2236 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit | |
64366f1c | 2237 | systems and that doesn't exist on 64-bit systems. */ |
489461e2 | 2238 | #define R32(name) { STR(name), 4, 0, 0, 0 } |
7a78ae4e ND |
2239 | |
2240 | /* Return a struct reg defining register NAME that's 64 bits on 64-bit | |
64366f1c | 2241 | systems and that doesn't exist on 32-bit systems. */ |
489461e2 | 2242 | #define R64(name) { STR(name), 0, 8, 0, 0 } |
7a78ae4e | 2243 | |
64366f1c | 2244 | /* Return a struct reg placeholder for a register that doesn't exist. */ |
489461e2 | 2245 | #define R0 { 0, 0, 0, 0, 0 } |
7a78ae4e ND |
2246 | |
2247 | /* UISA registers common across all architectures, including POWER. */ | |
2248 | ||
2249 | #define COMMON_UISA_REGS \ | |
2250 | /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ | |
2251 | /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ | |
2252 | /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ | |
2253 | /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ | |
2254 | /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \ | |
2255 | /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \ | |
2256 | /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \ | |
2257 | /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \ | |
2258 | /* 64 */ R(pc), R(ps) | |
2259 | ||
ebeac11a EZ |
2260 | #define COMMON_UISA_NOFP_REGS \ |
2261 | /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ | |
2262 | /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ | |
2263 | /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ | |
2264 | /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ | |
2265 | /* 32 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
2266 | /* 40 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
2267 | /* 48 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
2268 | /* 56 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
2269 | /* 64 */ R(pc), R(ps) | |
2270 | ||
7a78ae4e ND |
2271 | /* UISA-level SPRs for PowerPC. */ |
2272 | #define PPC_UISA_SPRS \ | |
e3f36dbd | 2273 | /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr) |
7a78ae4e | 2274 | |
c8001721 EZ |
2275 | /* UISA-level SPRs for PowerPC without floating point support. */ |
2276 | #define PPC_UISA_NOFP_SPRS \ | |
2277 | /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0 | |
2278 | ||
7a78ae4e ND |
2279 | /* Segment registers, for PowerPC. */ |
2280 | #define PPC_SEGMENT_REGS \ | |
2281 | /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \ | |
2282 | /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \ | |
2283 | /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \ | |
2284 | /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15) | |
2285 | ||
2286 | /* OEA SPRs for PowerPC. */ | |
2287 | #define PPC_OEA_SPRS \ | |
2288 | /* 87 */ R4(pvr), \ | |
2289 | /* 88 */ R(ibat0u), R(ibat0l), R(ibat1u), R(ibat1l), \ | |
2290 | /* 92 */ R(ibat2u), R(ibat2l), R(ibat3u), R(ibat3l), \ | |
2291 | /* 96 */ R(dbat0u), R(dbat0l), R(dbat1u), R(dbat1l), \ | |
2292 | /* 100 */ R(dbat2u), R(dbat2l), R(dbat3u), R(dbat3l), \ | |
2293 | /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \ | |
2294 | /* 108 */ R(sprg0), R(sprg1), R(sprg2), R(sprg3), \ | |
2295 | /* 112 */ R(srr0), R(srr1), R(tbl), R(tbu), \ | |
2296 | /* 116 */ R4(dec), R(dabr), R4(ear) | |
2297 | ||
64366f1c | 2298 | /* AltiVec registers. */ |
1fcc0bb8 EZ |
2299 | #define PPC_ALTIVEC_REGS \ |
2300 | /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \ | |
2301 | /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \ | |
2302 | /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \ | |
2303 | /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \ | |
2304 | /*151*/R4(vscr), R4(vrsave) | |
2305 | ||
c8001721 EZ |
2306 | /* Vectors of hi-lo general purpose registers. */ |
2307 | #define PPC_EV_REGS \ | |
2308 | /* 0*/R8(ev0), R8(ev1), R8(ev2), R8(ev3), R8(ev4), R8(ev5), R8(ev6), R8(ev7), \ | |
2309 | /* 8*/R8(ev8), R8(ev9), R8(ev10),R8(ev11),R8(ev12),R8(ev13),R8(ev14),R8(ev15), \ | |
2310 | /*16*/R8(ev16),R8(ev17),R8(ev18),R8(ev19),R8(ev20),R8(ev21),R8(ev22),R8(ev23), \ | |
2311 | /*24*/R8(ev24),R8(ev25),R8(ev26),R8(ev27),R8(ev28),R8(ev29),R8(ev30),R8(ev31) | |
2312 | ||
2313 | /* Lower half of the EV registers. */ | |
2314 | #define PPC_GPRS_PSEUDO_REGS \ | |
2315 | /* 0 */ P(r0), P(r1), P(r2), P(r3), P(r4), P(r5), P(r6), P(r7), \ | |
2316 | /* 8 */ P(r8), P(r9), P(r10),P(r11),P(r12),P(r13),P(r14),P(r15), \ | |
2317 | /* 16 */ P(r16),P(r17),P(r18),P(r19),P(r20),P(r21),P(r22),P(r23), \ | |
338ef23d | 2318 | /* 24 */ P(r24),P(r25),P(r26),P(r27),P(r28),P(r29),P(r30),P(r31) |
c8001721 | 2319 | |
7a78ae4e | 2320 | /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover |
64366f1c | 2321 | user-level SPR's. */ |
7a78ae4e | 2322 | static const struct reg registers_power[] = |
c906108c | 2323 | { |
7a78ae4e | 2324 | COMMON_UISA_REGS, |
e3f36dbd KB |
2325 | /* 66 */ R4(cnd), R(lr), R(cnt), R4(xer), R4(mq), |
2326 | /* 71 */ R4(fpscr) | |
c906108c SS |
2327 | }; |
2328 | ||
7a78ae4e | 2329 | /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only |
64366f1c | 2330 | view of the PowerPC. */ |
7a78ae4e | 2331 | static const struct reg registers_powerpc[] = |
c906108c | 2332 | { |
7a78ae4e | 2333 | COMMON_UISA_REGS, |
1fcc0bb8 EZ |
2334 | PPC_UISA_SPRS, |
2335 | PPC_ALTIVEC_REGS | |
c906108c SS |
2336 | }; |
2337 | ||
ebeac11a EZ |
2338 | /* PowerPC UISA - a PPC processor as viewed by user-level |
2339 | code, but without floating point registers. */ | |
2340 | static const struct reg registers_powerpc_nofp[] = | |
2341 | { | |
2342 | COMMON_UISA_NOFP_REGS, | |
2343 | PPC_UISA_SPRS | |
2344 | }; | |
2345 | ||
64366f1c | 2346 | /* IBM PowerPC 403. */ |
7a78ae4e | 2347 | static const struct reg registers_403[] = |
c5aa993b | 2348 | { |
7a78ae4e ND |
2349 | COMMON_UISA_REGS, |
2350 | PPC_UISA_SPRS, | |
2351 | PPC_SEGMENT_REGS, | |
2352 | PPC_OEA_SPRS, | |
2353 | /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr), | |
2354 | /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit), | |
2355 | /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3), | |
2356 | /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2), | |
2357 | /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr), | |
2358 | /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2) | |
c906108c SS |
2359 | }; |
2360 | ||
64366f1c | 2361 | /* IBM PowerPC 403GC. */ |
7a78ae4e | 2362 | static const struct reg registers_403GC[] = |
c5aa993b | 2363 | { |
7a78ae4e ND |
2364 | COMMON_UISA_REGS, |
2365 | PPC_UISA_SPRS, | |
2366 | PPC_SEGMENT_REGS, | |
2367 | PPC_OEA_SPRS, | |
2368 | /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr), | |
2369 | /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit), | |
2370 | /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3), | |
2371 | /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2), | |
2372 | /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr), | |
2373 | /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2), | |
2374 | /* 143 */ R(zpr), R(pid), R(sgr), R(dcwr), | |
2375 | /* 147 */ R(tbhu), R(tblu) | |
c906108c SS |
2376 | }; |
2377 | ||
64366f1c | 2378 | /* Motorola PowerPC 505. */ |
7a78ae4e | 2379 | static const struct reg registers_505[] = |
c5aa993b | 2380 | { |
7a78ae4e ND |
2381 | COMMON_UISA_REGS, |
2382 | PPC_UISA_SPRS, | |
2383 | PPC_SEGMENT_REGS, | |
2384 | PPC_OEA_SPRS, | |
2385 | /* 119 */ R(eie), R(eid), R(nri) | |
c906108c SS |
2386 | }; |
2387 | ||
64366f1c | 2388 | /* Motorola PowerPC 860 or 850. */ |
7a78ae4e | 2389 | static const struct reg registers_860[] = |
c5aa993b | 2390 | { |
7a78ae4e ND |
2391 | COMMON_UISA_REGS, |
2392 | PPC_UISA_SPRS, | |
2393 | PPC_SEGMENT_REGS, | |
2394 | PPC_OEA_SPRS, | |
2395 | /* 119 */ R(eie), R(eid), R(nri), R(cmpa), | |
2396 | /* 123 */ R(cmpb), R(cmpc), R(cmpd), R(icr), | |
2397 | /* 127 */ R(der), R(counta), R(countb), R(cmpe), | |
2398 | /* 131 */ R(cmpf), R(cmpg), R(cmph), R(lctrl1), | |
2399 | /* 135 */ R(lctrl2), R(ictrl), R(bar), R(ic_cst), | |
2400 | /* 139 */ R(ic_adr), R(ic_dat), R(dc_cst), R(dc_adr), | |
2401 | /* 143 */ R(dc_dat), R(dpdr), R(dpir), R(immr), | |
2402 | /* 147 */ R(mi_ctr), R(mi_ap), R(mi_epn), R(mi_twc), | |
2403 | /* 151 */ R(mi_rpn), R(md_ctr), R(m_casid), R(md_ap), | |
2404 | /* 155 */ R(md_epn), R(md_twb), R(md_twc), R(md_rpn), | |
2405 | /* 159 */ R(m_tw), R(mi_dbcam), R(mi_dbram0), R(mi_dbram1), | |
2406 | /* 163 */ R(md_dbcam), R(md_dbram0), R(md_dbram1) | |
c906108c SS |
2407 | }; |
2408 | ||
7a78ae4e ND |
2409 | /* Motorola PowerPC 601. Note that the 601 has different register numbers |
2410 | for reading and writing RTCU and RTCL. However, how one reads and writes a | |
c906108c | 2411 | register is the stub's problem. */ |
7a78ae4e | 2412 | static const struct reg registers_601[] = |
c5aa993b | 2413 | { |
7a78ae4e ND |
2414 | COMMON_UISA_REGS, |
2415 | PPC_UISA_SPRS, | |
2416 | PPC_SEGMENT_REGS, | |
2417 | PPC_OEA_SPRS, | |
2418 | /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), | |
2419 | /* 123 */ R(pir), R(mq), R(rtcu), R(rtcl) | |
c906108c SS |
2420 | }; |
2421 | ||
64366f1c | 2422 | /* Motorola PowerPC 602. */ |
7a78ae4e | 2423 | static const struct reg registers_602[] = |
c5aa993b | 2424 | { |
7a78ae4e ND |
2425 | COMMON_UISA_REGS, |
2426 | PPC_UISA_SPRS, | |
2427 | PPC_SEGMENT_REGS, | |
2428 | PPC_OEA_SPRS, | |
2429 | /* 119 */ R(hid0), R(hid1), R(iabr), R0, | |
2430 | /* 123 */ R0, R(tcr), R(ibr), R(esassr), | |
2431 | /* 127 */ R(sebr), R(ser), R(sp), R(lt) | |
c906108c SS |
2432 | }; |
2433 | ||
64366f1c | 2434 | /* Motorola/IBM PowerPC 603 or 603e. */ |
7a78ae4e | 2435 | static const struct reg registers_603[] = |
c5aa993b | 2436 | { |
7a78ae4e ND |
2437 | COMMON_UISA_REGS, |
2438 | PPC_UISA_SPRS, | |
2439 | PPC_SEGMENT_REGS, | |
2440 | PPC_OEA_SPRS, | |
2441 | /* 119 */ R(hid0), R(hid1), R(iabr), R0, | |
2442 | /* 123 */ R0, R(dmiss), R(dcmp), R(hash1), | |
2443 | /* 127 */ R(hash2), R(imiss), R(icmp), R(rpa) | |
c906108c SS |
2444 | }; |
2445 | ||
64366f1c | 2446 | /* Motorola PowerPC 604 or 604e. */ |
7a78ae4e | 2447 | static const struct reg registers_604[] = |
c5aa993b | 2448 | { |
7a78ae4e ND |
2449 | COMMON_UISA_REGS, |
2450 | PPC_UISA_SPRS, | |
2451 | PPC_SEGMENT_REGS, | |
2452 | PPC_OEA_SPRS, | |
2453 | /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), | |
2454 | /* 123 */ R(pir), R(mmcr0), R(pmc1), R(pmc2), | |
2455 | /* 127 */ R(sia), R(sda) | |
c906108c SS |
2456 | }; |
2457 | ||
64366f1c | 2458 | /* Motorola/IBM PowerPC 750 or 740. */ |
7a78ae4e | 2459 | static const struct reg registers_750[] = |
c5aa993b | 2460 | { |
7a78ae4e ND |
2461 | COMMON_UISA_REGS, |
2462 | PPC_UISA_SPRS, | |
2463 | PPC_SEGMENT_REGS, | |
2464 | PPC_OEA_SPRS, | |
2465 | /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), | |
2466 | /* 123 */ R0, R(ummcr0), R(upmc1), R(upmc2), | |
2467 | /* 127 */ R(usia), R(ummcr1), R(upmc3), R(upmc4), | |
2468 | /* 131 */ R(mmcr0), R(pmc1), R(pmc2), R(sia), | |
2469 | /* 135 */ R(mmcr1), R(pmc3), R(pmc4), R(l2cr), | |
2470 | /* 139 */ R(ictc), R(thrm1), R(thrm2), R(thrm3) | |
c906108c SS |
2471 | }; |
2472 | ||
2473 | ||
64366f1c | 2474 | /* Motorola PowerPC 7400. */ |
1fcc0bb8 EZ |
2475 | static const struct reg registers_7400[] = |
2476 | { | |
2477 | /* gpr0-gpr31, fpr0-fpr31 */ | |
2478 | COMMON_UISA_REGS, | |
2479 | /* ctr, xre, lr, cr */ | |
2480 | PPC_UISA_SPRS, | |
2481 | /* sr0-sr15 */ | |
2482 | PPC_SEGMENT_REGS, | |
2483 | PPC_OEA_SPRS, | |
2484 | /* vr0-vr31, vrsave, vscr */ | |
2485 | PPC_ALTIVEC_REGS | |
2486 | /* FIXME? Add more registers? */ | |
2487 | }; | |
2488 | ||
c8001721 EZ |
2489 | /* Motorola e500. */ |
2490 | static const struct reg registers_e500[] = | |
2491 | { | |
2492 | R(pc), R(ps), | |
2493 | /* cr, lr, ctr, xer, "" */ | |
2494 | PPC_UISA_NOFP_SPRS, | |
2495 | /* 7...38 */ | |
2496 | PPC_EV_REGS, | |
338ef23d AC |
2497 | R8(acc), R(spefscr), |
2498 | /* NOTE: Add new registers here the end of the raw register | |
2499 | list and just before the first pseudo register. */ | |
c8001721 EZ |
2500 | /* 39...70 */ |
2501 | PPC_GPRS_PSEUDO_REGS | |
2502 | }; | |
2503 | ||
c906108c | 2504 | /* Information about a particular processor variant. */ |
7a78ae4e | 2505 | |
c906108c | 2506 | struct variant |
c5aa993b JM |
2507 | { |
2508 | /* Name of this variant. */ | |
2509 | char *name; | |
c906108c | 2510 | |
c5aa993b JM |
2511 | /* English description of the variant. */ |
2512 | char *description; | |
c906108c | 2513 | |
64366f1c | 2514 | /* bfd_arch_info.arch corresponding to variant. */ |
7a78ae4e ND |
2515 | enum bfd_architecture arch; |
2516 | ||
64366f1c | 2517 | /* bfd_arch_info.mach corresponding to variant. */ |
7a78ae4e ND |
2518 | unsigned long mach; |
2519 | ||
489461e2 EZ |
2520 | /* Number of real registers. */ |
2521 | int nregs; | |
2522 | ||
2523 | /* Number of pseudo registers. */ | |
2524 | int npregs; | |
2525 | ||
2526 | /* Number of total registers (the sum of nregs and npregs). */ | |
2527 | int num_tot_regs; | |
2528 | ||
c5aa993b JM |
2529 | /* Table of register names; registers[R] is the name of the register |
2530 | number R. */ | |
7a78ae4e | 2531 | const struct reg *regs; |
c5aa993b | 2532 | }; |
c906108c | 2533 | |
489461e2 EZ |
2534 | #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0])) |
2535 | ||
2536 | static int | |
2537 | num_registers (const struct reg *reg_list, int num_tot_regs) | |
2538 | { | |
2539 | int i; | |
2540 | int nregs = 0; | |
2541 | ||
2542 | for (i = 0; i < num_tot_regs; i++) | |
2543 | if (!reg_list[i].pseudo) | |
2544 | nregs++; | |
2545 | ||
2546 | return nregs; | |
2547 | } | |
2548 | ||
2549 | static int | |
2550 | num_pseudo_registers (const struct reg *reg_list, int num_tot_regs) | |
2551 | { | |
2552 | int i; | |
2553 | int npregs = 0; | |
2554 | ||
2555 | for (i = 0; i < num_tot_regs; i++) | |
2556 | if (reg_list[i].pseudo) | |
2557 | npregs ++; | |
2558 | ||
2559 | return npregs; | |
2560 | } | |
c906108c | 2561 | |
c906108c SS |
2562 | /* Information in this table comes from the following web sites: |
2563 | IBM: http://www.chips.ibm.com:80/products/embedded/ | |
2564 | Motorola: http://www.mot.com/SPS/PowerPC/ | |
2565 | ||
2566 | I'm sure I've got some of the variant descriptions not quite right. | |
2567 | Please report any inaccuracies you find to GDB's maintainer. | |
2568 | ||
2569 | If you add entries to this table, please be sure to allow the new | |
2570 | value as an argument to the --with-cpu flag, in configure.in. */ | |
2571 | ||
489461e2 | 2572 | static struct variant variants[] = |
c906108c | 2573 | { |
489461e2 | 2574 | |
7a78ae4e | 2575 | {"powerpc", "PowerPC user-level", bfd_arch_powerpc, |
489461e2 EZ |
2576 | bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc), |
2577 | registers_powerpc}, | |
7a78ae4e | 2578 | {"power", "POWER user-level", bfd_arch_rs6000, |
489461e2 EZ |
2579 | bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power), |
2580 | registers_power}, | |
7a78ae4e | 2581 | {"403", "IBM PowerPC 403", bfd_arch_powerpc, |
489461e2 EZ |
2582 | bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403), |
2583 | registers_403}, | |
7a78ae4e | 2584 | {"601", "Motorola PowerPC 601", bfd_arch_powerpc, |
489461e2 EZ |
2585 | bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601), |
2586 | registers_601}, | |
7a78ae4e | 2587 | {"602", "Motorola PowerPC 602", bfd_arch_powerpc, |
489461e2 EZ |
2588 | bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602), |
2589 | registers_602}, | |
7a78ae4e | 2590 | {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, |
489461e2 EZ |
2591 | bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603), |
2592 | registers_603}, | |
7a78ae4e | 2593 | {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, |
489461e2 EZ |
2594 | 604, -1, -1, tot_num_registers (registers_604), |
2595 | registers_604}, | |
7a78ae4e | 2596 | {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, |
489461e2 EZ |
2597 | bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC), |
2598 | registers_403GC}, | |
7a78ae4e | 2599 | {"505", "Motorola PowerPC 505", bfd_arch_powerpc, |
489461e2 EZ |
2600 | bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505), |
2601 | registers_505}, | |
7a78ae4e | 2602 | {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, |
489461e2 EZ |
2603 | bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860), |
2604 | registers_860}, | |
7a78ae4e | 2605 | {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, |
489461e2 EZ |
2606 | bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750), |
2607 | registers_750}, | |
1fcc0bb8 | 2608 | {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, |
489461e2 EZ |
2609 | bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400), |
2610 | registers_7400}, | |
c8001721 EZ |
2611 | {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, |
2612 | bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500), | |
2613 | registers_e500}, | |
7a78ae4e | 2614 | |
5d57ee30 KB |
2615 | /* 64-bit */ |
2616 | {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, | |
489461e2 EZ |
2617 | bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc), |
2618 | registers_powerpc}, | |
7a78ae4e | 2619 | {"620", "Motorola PowerPC 620", bfd_arch_powerpc, |
489461e2 EZ |
2620 | bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc), |
2621 | registers_powerpc}, | |
5d57ee30 | 2622 | {"630", "Motorola PowerPC 630", bfd_arch_powerpc, |
489461e2 EZ |
2623 | bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc), |
2624 | registers_powerpc}, | |
7a78ae4e | 2625 | {"a35", "PowerPC A35", bfd_arch_powerpc, |
489461e2 EZ |
2626 | bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc), |
2627 | registers_powerpc}, | |
5d57ee30 | 2628 | {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, |
489461e2 EZ |
2629 | bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc), |
2630 | registers_powerpc}, | |
5d57ee30 | 2631 | {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, |
489461e2 EZ |
2632 | bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc), |
2633 | registers_powerpc}, | |
5d57ee30 | 2634 | |
64366f1c | 2635 | /* FIXME: I haven't checked the register sets of the following. */ |
7a78ae4e | 2636 | {"rs1", "IBM POWER RS1", bfd_arch_rs6000, |
489461e2 EZ |
2637 | bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power), |
2638 | registers_power}, | |
7a78ae4e | 2639 | {"rsc", "IBM POWER RSC", bfd_arch_rs6000, |
489461e2 EZ |
2640 | bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power), |
2641 | registers_power}, | |
7a78ae4e | 2642 | {"rs2", "IBM POWER RS2", bfd_arch_rs6000, |
489461e2 EZ |
2643 | bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power), |
2644 | registers_power}, | |
7a78ae4e | 2645 | |
489461e2 | 2646 | {0, 0, 0, 0, 0, 0, 0, 0} |
c906108c SS |
2647 | }; |
2648 | ||
64366f1c | 2649 | /* Initialize the number of registers and pseudo registers in each variant. */ |
489461e2 EZ |
2650 | |
2651 | static void | |
2652 | init_variants (void) | |
2653 | { | |
2654 | struct variant *v; | |
2655 | ||
2656 | for (v = variants; v->name; v++) | |
2657 | { | |
2658 | if (v->nregs == -1) | |
2659 | v->nregs = num_registers (v->regs, v->num_tot_regs); | |
2660 | if (v->npregs == -1) | |
2661 | v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs); | |
2662 | } | |
2663 | } | |
c906108c | 2664 | |
7a78ae4e | 2665 | /* Return the variant corresponding to architecture ARCH and machine number |
64366f1c | 2666 | MACH. If no such variant exists, return null. */ |
c906108c | 2667 | |
7a78ae4e ND |
2668 | static const struct variant * |
2669 | find_variant_by_arch (enum bfd_architecture arch, unsigned long mach) | |
c906108c | 2670 | { |
7a78ae4e | 2671 | const struct variant *v; |
c5aa993b | 2672 | |
7a78ae4e ND |
2673 | for (v = variants; v->name; v++) |
2674 | if (arch == v->arch && mach == v->mach) | |
2675 | return v; | |
c906108c | 2676 | |
7a78ae4e | 2677 | return NULL; |
c906108c | 2678 | } |
9364a0ef EZ |
2679 | |
2680 | static int | |
2681 | gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info) | |
2682 | { | |
2683 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2684 | return print_insn_big_powerpc (memaddr, info); | |
2685 | else | |
2686 | return print_insn_little_powerpc (memaddr, info); | |
2687 | } | |
7a78ae4e | 2688 | \f |
7a78ae4e ND |
2689 | /* Initialize the current architecture based on INFO. If possible, re-use an |
2690 | architecture from ARCHES, which is a list of architectures already created | |
2691 | during this debugging session. | |
c906108c | 2692 | |
7a78ae4e | 2693 | Called e.g. at program startup, when reading a core file, and when reading |
64366f1c | 2694 | a binary file. */ |
c906108c | 2695 | |
7a78ae4e ND |
2696 | static struct gdbarch * |
2697 | rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2698 | { | |
2699 | struct gdbarch *gdbarch; | |
2700 | struct gdbarch_tdep *tdep; | |
9aa1e687 | 2701 | int wordsize, from_xcoff_exec, from_elf_exec, power, i, off; |
7a78ae4e ND |
2702 | struct reg *regs; |
2703 | const struct variant *v; | |
2704 | enum bfd_architecture arch; | |
2705 | unsigned long mach; | |
2706 | bfd abfd; | |
7b112f9c | 2707 | int sysv_abi; |
5bf1c677 | 2708 | asection *sect; |
7a78ae4e | 2709 | |
9aa1e687 | 2710 | from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && |
7a78ae4e ND |
2711 | bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; |
2712 | ||
9aa1e687 KB |
2713 | from_elf_exec = info.abfd && info.abfd->format == bfd_object && |
2714 | bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
2715 | ||
2716 | sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
2717 | ||
e712c1cf | 2718 | /* Check word size. If INFO is from a binary file, infer it from |
64366f1c | 2719 | that, else choose a likely default. */ |
9aa1e687 | 2720 | if (from_xcoff_exec) |
c906108c | 2721 | { |
11ed25ac | 2722 | if (bfd_xcoff_is_xcoff64 (info.abfd)) |
7a78ae4e ND |
2723 | wordsize = 8; |
2724 | else | |
2725 | wordsize = 4; | |
c906108c | 2726 | } |
9aa1e687 KB |
2727 | else if (from_elf_exec) |
2728 | { | |
2729 | if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
2730 | wordsize = 8; | |
2731 | else | |
2732 | wordsize = 4; | |
2733 | } | |
c906108c | 2734 | else |
7a78ae4e | 2735 | { |
27b15785 KB |
2736 | if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) |
2737 | wordsize = info.bfd_arch_info->bits_per_word / | |
2738 | info.bfd_arch_info->bits_per_byte; | |
2739 | else | |
2740 | wordsize = 4; | |
7a78ae4e | 2741 | } |
c906108c | 2742 | |
64366f1c | 2743 | /* Find a candidate among extant architectures. */ |
7a78ae4e ND |
2744 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
2745 | arches != NULL; | |
2746 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
2747 | { | |
2748 | /* Word size in the various PowerPC bfd_arch_info structs isn't | |
2749 | meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform | |
64366f1c | 2750 | separate word size check. */ |
7a78ae4e | 2751 | tdep = gdbarch_tdep (arches->gdbarch); |
4be87837 | 2752 | if (tdep && tdep->wordsize == wordsize) |
7a78ae4e ND |
2753 | return arches->gdbarch; |
2754 | } | |
c906108c | 2755 | |
7a78ae4e ND |
2756 | /* None found, create a new architecture from INFO, whose bfd_arch_info |
2757 | validity depends on the source: | |
2758 | - executable useless | |
2759 | - rs6000_host_arch() good | |
2760 | - core file good | |
2761 | - "set arch" trust blindly | |
2762 | - GDB startup useless but harmless */ | |
c906108c | 2763 | |
9aa1e687 | 2764 | if (!from_xcoff_exec) |
c906108c | 2765 | { |
b732d07d | 2766 | arch = info.bfd_arch_info->arch; |
7a78ae4e | 2767 | mach = info.bfd_arch_info->mach; |
c906108c | 2768 | } |
7a78ae4e | 2769 | else |
c906108c | 2770 | { |
7a78ae4e | 2771 | arch = bfd_arch_powerpc; |
35cec841 | 2772 | bfd_default_set_arch_mach (&abfd, arch, 0); |
7a78ae4e | 2773 | info.bfd_arch_info = bfd_get_arch_info (&abfd); |
35cec841 | 2774 | mach = info.bfd_arch_info->mach; |
7a78ae4e ND |
2775 | } |
2776 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
2777 | tdep->wordsize = wordsize; | |
5bf1c677 EZ |
2778 | |
2779 | /* For e500 executables, the apuinfo section is of help here. Such | |
2780 | section contains the identifier and revision number of each | |
2781 | Application-specific Processing Unit that is present on the | |
2782 | chip. The content of the section is determined by the assembler | |
2783 | which looks at each instruction and determines which unit (and | |
2784 | which version of it) can execute it. In our case we just look for | |
2785 | the existance of the section. */ | |
2786 | ||
2787 | if (info.abfd) | |
2788 | { | |
2789 | sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo"); | |
2790 | if (sect) | |
2791 | { | |
2792 | arch = info.bfd_arch_info->arch; | |
2793 | mach = bfd_mach_ppc_e500; | |
2794 | bfd_default_set_arch_mach (&abfd, arch, mach); | |
2795 | info.bfd_arch_info = bfd_get_arch_info (&abfd); | |
2796 | } | |
2797 | } | |
2798 | ||
7a78ae4e ND |
2799 | gdbarch = gdbarch_alloc (&info, tdep); |
2800 | power = arch == bfd_arch_rs6000; | |
2801 | ||
489461e2 EZ |
2802 | /* Initialize the number of real and pseudo registers in each variant. */ |
2803 | init_variants (); | |
2804 | ||
64366f1c | 2805 | /* Choose variant. */ |
7a78ae4e ND |
2806 | v = find_variant_by_arch (arch, mach); |
2807 | if (!v) | |
dd47e6fd EZ |
2808 | return NULL; |
2809 | ||
7a78ae4e ND |
2810 | tdep->regs = v->regs; |
2811 | ||
2188cbdd EZ |
2812 | tdep->ppc_gp0_regnum = 0; |
2813 | tdep->ppc_gplast_regnum = 31; | |
2814 | tdep->ppc_toc_regnum = 2; | |
2815 | tdep->ppc_ps_regnum = 65; | |
2816 | tdep->ppc_cr_regnum = 66; | |
2817 | tdep->ppc_lr_regnum = 67; | |
2818 | tdep->ppc_ctr_regnum = 68; | |
2819 | tdep->ppc_xer_regnum = 69; | |
2820 | if (v->mach == bfd_mach_ppc_601) | |
2821 | tdep->ppc_mq_regnum = 124; | |
e3f36dbd | 2822 | else if (power) |
2188cbdd | 2823 | tdep->ppc_mq_regnum = 70; |
e3f36dbd KB |
2824 | else |
2825 | tdep->ppc_mq_regnum = -1; | |
2826 | tdep->ppc_fpscr_regnum = power ? 71 : 70; | |
2188cbdd | 2827 | |
c8001721 EZ |
2828 | set_gdbarch_pc_regnum (gdbarch, 64); |
2829 | set_gdbarch_sp_regnum (gdbarch, 1); | |
0ba6dca9 | 2830 | set_gdbarch_deprecated_fp_regnum (gdbarch, 1); |
96ff0de4 EZ |
2831 | set_gdbarch_deprecated_extract_return_value (gdbarch, |
2832 | rs6000_extract_return_value); | |
46d79c04 | 2833 | set_gdbarch_deprecated_store_return_value (gdbarch, rs6000_store_return_value); |
c8001721 | 2834 | |
1fcc0bb8 EZ |
2835 | if (v->arch == bfd_arch_powerpc) |
2836 | switch (v->mach) | |
2837 | { | |
2838 | case bfd_mach_ppc: | |
2839 | tdep->ppc_vr0_regnum = 71; | |
2840 | tdep->ppc_vrsave_regnum = 104; | |
c8001721 EZ |
2841 | tdep->ppc_ev0_regnum = -1; |
2842 | tdep->ppc_ev31_regnum = -1; | |
1fcc0bb8 EZ |
2843 | break; |
2844 | case bfd_mach_ppc_7400: | |
2845 | tdep->ppc_vr0_regnum = 119; | |
54c2a1e6 | 2846 | tdep->ppc_vrsave_regnum = 152; |
c8001721 EZ |
2847 | tdep->ppc_ev0_regnum = -1; |
2848 | tdep->ppc_ev31_regnum = -1; | |
2849 | break; | |
2850 | case bfd_mach_ppc_e500: | |
338ef23d AC |
2851 | tdep->ppc_gp0_regnum = 41; |
2852 | tdep->ppc_gplast_regnum = tdep->ppc_gp0_regnum + 32 - 1; | |
c8001721 EZ |
2853 | tdep->ppc_toc_regnum = -1; |
2854 | tdep->ppc_ps_regnum = 1; | |
2855 | tdep->ppc_cr_regnum = 2; | |
2856 | tdep->ppc_lr_regnum = 3; | |
2857 | tdep->ppc_ctr_regnum = 4; | |
2858 | tdep->ppc_xer_regnum = 5; | |
2859 | tdep->ppc_ev0_regnum = 7; | |
2860 | tdep->ppc_ev31_regnum = 38; | |
2861 | set_gdbarch_pc_regnum (gdbarch, 0); | |
338ef23d | 2862 | set_gdbarch_sp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1); |
0ba6dca9 | 2863 | set_gdbarch_deprecated_fp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1); |
c8001721 EZ |
2864 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, e500_dwarf2_reg_to_regnum); |
2865 | set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read); | |
2866 | set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write); | |
96ff0de4 | 2867 | set_gdbarch_extract_return_value (gdbarch, e500_extract_return_value); |
46d79c04 | 2868 | set_gdbarch_deprecated_store_return_value (gdbarch, e500_store_return_value); |
1fcc0bb8 EZ |
2869 | break; |
2870 | default: | |
2871 | tdep->ppc_vr0_regnum = -1; | |
2872 | tdep->ppc_vrsave_regnum = -1; | |
c8001721 EZ |
2873 | tdep->ppc_ev0_regnum = -1; |
2874 | tdep->ppc_ev31_regnum = -1; | |
1fcc0bb8 EZ |
2875 | break; |
2876 | } | |
2877 | ||
338ef23d AC |
2878 | /* Sanity check on registers. */ |
2879 | gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0); | |
2880 | ||
a88376a3 KB |
2881 | /* Set lr_frame_offset. */ |
2882 | if (wordsize == 8) | |
2883 | tdep->lr_frame_offset = 16; | |
2884 | else if (sysv_abi) | |
2885 | tdep->lr_frame_offset = 4; | |
2886 | else | |
2887 | tdep->lr_frame_offset = 8; | |
2888 | ||
2889 | /* Calculate byte offsets in raw register array. */ | |
489461e2 EZ |
2890 | tdep->regoff = xmalloc (v->num_tot_regs * sizeof (int)); |
2891 | for (i = off = 0; i < v->num_tot_regs; i++) | |
7a78ae4e ND |
2892 | { |
2893 | tdep->regoff[i] = off; | |
2894 | off += regsize (v->regs + i, wordsize); | |
c906108c SS |
2895 | } |
2896 | ||
56a6dfb9 KB |
2897 | /* Select instruction printer. */ |
2898 | if (arch == power) | |
9364a0ef | 2899 | set_gdbarch_print_insn (gdbarch, print_insn_rs6000); |
56a6dfb9 | 2900 | else |
9364a0ef | 2901 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc); |
7495d1dc | 2902 | |
7a78ae4e ND |
2903 | set_gdbarch_read_pc (gdbarch, generic_target_read_pc); |
2904 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); | |
7a78ae4e | 2905 | set_gdbarch_read_sp (gdbarch, generic_target_read_sp); |
6c0e89ed | 2906 | set_gdbarch_deprecated_dummy_write_sp (gdbarch, generic_target_write_sp); |
7a78ae4e ND |
2907 | |
2908 | set_gdbarch_num_regs (gdbarch, v->nregs); | |
c8001721 | 2909 | set_gdbarch_num_pseudo_regs (gdbarch, v->npregs); |
7a78ae4e | 2910 | set_gdbarch_register_name (gdbarch, rs6000_register_name); |
b1e29e33 | 2911 | set_gdbarch_deprecated_register_size (gdbarch, wordsize); |
b8b527c5 | 2912 | set_gdbarch_deprecated_register_bytes (gdbarch, off); |
7a78ae4e ND |
2913 | set_gdbarch_register_byte (gdbarch, rs6000_register_byte); |
2914 | set_gdbarch_register_raw_size (gdbarch, rs6000_register_raw_size); | |
a0ed5532 | 2915 | set_gdbarch_deprecated_max_register_raw_size (gdbarch, 16); |
b2e75d78 | 2916 | set_gdbarch_register_virtual_size (gdbarch, generic_register_size); |
a0ed5532 | 2917 | set_gdbarch_deprecated_max_register_virtual_size (gdbarch, 16); |
7a78ae4e ND |
2918 | set_gdbarch_register_virtual_type (gdbarch, rs6000_register_virtual_type); |
2919 | ||
2920 | set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
2921 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
2922 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2923 | set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
2924 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2925 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2926 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
ab9fe00e KB |
2927 | if (sysv_abi) |
2928 | set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); | |
2929 | else | |
2930 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4e409299 | 2931 | set_gdbarch_char_signed (gdbarch, 0); |
7a78ae4e | 2932 | |
b1e29e33 | 2933 | set_gdbarch_deprecated_fix_call_dummy (gdbarch, rs6000_fix_call_dummy); |
11269d7e | 2934 | set_gdbarch_frame_align (gdbarch, rs6000_frame_align); |
58223630 | 2935 | set_gdbarch_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos); |
28f617b3 | 2936 | set_gdbarch_deprecated_push_return_address (gdbarch, ppc_push_return_address); |
7a78ae4e | 2937 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
7a78ae4e ND |
2938 | |
2939 | set_gdbarch_register_convertible (gdbarch, rs6000_register_convertible); | |
2940 | set_gdbarch_register_convert_to_virtual (gdbarch, rs6000_register_convert_to_virtual); | |
2941 | set_gdbarch_register_convert_to_raw (gdbarch, rs6000_register_convert_to_raw); | |
2188cbdd | 2942 | set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); |
2ea5f656 KB |
2943 | /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments() |
2944 | is correct for the SysV ABI when the wordsize is 8, but I'm also | |
2945 | fairly certain that ppc_sysv_abi_push_arguments() will give even | |
2946 | worse results since it only works for 32-bit code. So, for the moment, | |
2947 | we're better off calling rs6000_push_arguments() since it works for | |
2948 | 64-bit code. At some point in the future, this matter needs to be | |
2949 | revisited. */ | |
2950 | if (sysv_abi && wordsize == 4) | |
b81774d8 | 2951 | set_gdbarch_deprecated_push_arguments (gdbarch, ppc_sysv_abi_push_arguments); |
9aa1e687 | 2952 | else |
b81774d8 | 2953 | set_gdbarch_deprecated_push_arguments (gdbarch, rs6000_push_arguments); |
7a78ae4e | 2954 | |
4183d812 | 2955 | set_gdbarch_deprecated_store_struct_return (gdbarch, rs6000_store_struct_return); |
11269d7e | 2956 | set_gdbarch_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address); |
749b82f6 | 2957 | set_gdbarch_deprecated_pop_frame (gdbarch, rs6000_pop_frame); |
7a78ae4e ND |
2958 | |
2959 | set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); | |
2960 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2961 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
2962 | set_gdbarch_function_start_offset (gdbarch, 0); | |
2963 | set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc); | |
2964 | ||
2965 | /* Not sure on this. FIXMEmgo */ | |
2966 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
2967 | ||
8e0662df | 2968 | if (sysv_abi) |
7b112f9c JT |
2969 | set_gdbarch_use_struct_convention (gdbarch, |
2970 | ppc_sysv_abi_use_struct_convention); | |
8e0662df | 2971 | else |
7b112f9c JT |
2972 | set_gdbarch_use_struct_convention (gdbarch, |
2973 | generic_use_struct_convention); | |
8e0662df | 2974 | |
7b112f9c JT |
2975 | set_gdbarch_frameless_function_invocation (gdbarch, |
2976 | rs6000_frameless_function_invocation); | |
618ce49f | 2977 | set_gdbarch_deprecated_frame_chain (gdbarch, rs6000_frame_chain); |
8bedc050 | 2978 | set_gdbarch_deprecated_frame_saved_pc (gdbarch, rs6000_frame_saved_pc); |
7b112f9c | 2979 | |
f30ee0bc | 2980 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, rs6000_frame_init_saved_regs); |
e9582e71 | 2981 | set_gdbarch_deprecated_init_extra_frame_info (gdbarch, rs6000_init_extra_frame_info); |
7b112f9c | 2982 | |
15813d3f AC |
2983 | if (!sysv_abi) |
2984 | { | |
2985 | /* Handle RS/6000 function pointers (which are really function | |
2986 | descriptors). */ | |
f517ea4e PS |
2987 | set_gdbarch_convert_from_func_ptr_addr (gdbarch, |
2988 | rs6000_convert_from_func_ptr_addr); | |
9aa1e687 | 2989 | } |
7a78ae4e ND |
2990 | set_gdbarch_frame_args_address (gdbarch, rs6000_frame_args_address); |
2991 | set_gdbarch_frame_locals_address (gdbarch, rs6000_frame_args_address); | |
6913c89a | 2992 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, rs6000_saved_pc_after_call); |
7a78ae4e ND |
2993 | |
2994 | /* We can't tell how many args there are | |
2995 | now that the C compiler delays popping them. */ | |
2996 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); | |
2997 | ||
7b112f9c | 2998 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4be87837 | 2999 | gdbarch_init_osabi (info, gdbarch); |
7b112f9c | 3000 | |
7a78ae4e | 3001 | return gdbarch; |
c906108c SS |
3002 | } |
3003 | ||
7b112f9c JT |
3004 | static void |
3005 | rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
3006 | { | |
3007 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3008 | ||
3009 | if (tdep == NULL) | |
3010 | return; | |
3011 | ||
4be87837 | 3012 | /* FIXME: Dump gdbarch_tdep. */ |
7b112f9c JT |
3013 | } |
3014 | ||
1fcc0bb8 EZ |
3015 | static struct cmd_list_element *info_powerpc_cmdlist = NULL; |
3016 | ||
3017 | static void | |
3018 | rs6000_info_powerpc_command (char *args, int from_tty) | |
3019 | { | |
3020 | help_list (info_powerpc_cmdlist, "info powerpc ", class_info, gdb_stdout); | |
3021 | } | |
3022 | ||
c906108c SS |
3023 | /* Initialization code. */ |
3024 | ||
3025 | void | |
fba45db2 | 3026 | _initialize_rs6000_tdep (void) |
c906108c | 3027 | { |
7b112f9c JT |
3028 | gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); |
3029 | gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); | |
1fcc0bb8 EZ |
3030 | |
3031 | /* Add root prefix command for "info powerpc" commands */ | |
3032 | add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command, | |
3033 | "Various POWERPC info specific commands.", | |
3034 | &info_powerpc_cmdlist, "info powerpc ", 0, &infolist); | |
c906108c | 3035 | } |