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[deliverable/binutils-gdb.git] / gdb / rs6000-tdep.c
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c906108c 1/* Target-dependent code for GDB, the GNU debugger.
7aea86e6 2
6aba47ca 3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4c38e0a4
JB		 4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010 Free Software Foundation, Inc.
c906108c 6
c5aa993b 7 This file is part of GDB.
c906108c 8
c5aa993b
JM		 9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
c5aa993b 12 (at your option) any later version.
c906108c 13
c5aa993b
JM		 14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
c906108c 18
c5aa993b 19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c
SS		 21
22#include "defs.h"
23#include "frame.h"
24#include "inferior.h"
25#include "symtab.h"
26#include "target.h"
27#include "gdbcore.h"
28#include "gdbcmd.h"
c906108c 29#include "objfiles.h"
7a78ae4e 30#include "arch-utils.h"
4e052eda 31#include "regcache.h"
d195bc9f 32#include "regset.h"
d16aafd8 33#include "doublest.h"
fd0407d6 34#include "value.h"
1fcc0bb8 35#include "parser-defs.h"
4be87837 36#include "osabi.h"
7d9b040b 37#include "infcall.h"
9f643768
JB		 38#include "sim-regno.h"
39#include "gdb/sim-ppc.h"
6ced10dd 40#include "reggroups.h"
4fc771b8 41#include "dwarf2-frame.h"
7cc46491
DJ		 42#include "target-descriptions.h"
43#include "user-regs.h"
7a78ae4e 44
2fccf04a 45#include "libbfd.h" /* for bfd_default_set_arch_mach */
7a78ae4e 46#include "coff/internal.h" /* for libcoff.h */
2fccf04a 47#include "libcoff.h" /* for xcoff_data */
11ed25ac
KB		 48#include "coff/xcoff.h"
49#include "libxcoff.h"
7a78ae4e 50
9aa1e687 51#include "elf-bfd.h"
55eddb0f 52#include "elf/ppc.h"
7a78ae4e 53
6ded7999 54#include "solib-svr4.h"
9aa1e687 55#include "ppc-tdep.h"
7a78ae4e 56
338ef23d 57#include "gdb_assert.h"
a89aa300 58#include "dis-asm.h"
338ef23d 59
61a65099
KB		 60#include "trad-frame.h"
61#include "frame-unwind.h"
62#include "frame-base.h"
63
7cc46491 64#include "features/rs6000/powerpc-32.c"
7284e1be 65#include "features/rs6000/powerpc-altivec32.c"
604c2f83 66#include "features/rs6000/powerpc-vsx32.c"
7cc46491
DJ		 67#include "features/rs6000/powerpc-403.c"
68#include "features/rs6000/powerpc-403gc.c"
4d09ffea 69#include "features/rs6000/powerpc-405.c"
7cc46491
DJ		 70#include "features/rs6000/powerpc-505.c"
71#include "features/rs6000/powerpc-601.c"
72#include "features/rs6000/powerpc-602.c"
73#include "features/rs6000/powerpc-603.c"
74#include "features/rs6000/powerpc-604.c"
75#include "features/rs6000/powerpc-64.c"
7284e1be 76#include "features/rs6000/powerpc-altivec64.c"
604c2f83 77#include "features/rs6000/powerpc-vsx64.c"
7cc46491
DJ		 78#include "features/rs6000/powerpc-7400.c"
79#include "features/rs6000/powerpc-750.c"
80#include "features/rs6000/powerpc-860.c"
81#include "features/rs6000/powerpc-e500.c"
82#include "features/rs6000/rs6000.c"
83
5a9e69ba
TJB		 84/* Determine if regnum is an SPE pseudo-register. */
85#define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
86 && (regnum) >= (tdep)->ppc_ev0_regnum \
87 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
88
f949c649
TJB		 89/* Determine if regnum is a decimal float pseudo-register. */
90#define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_dl0_regnum \
92 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
93
604c2f83
LM		 94/* Determine if regnum is a POWER7 VSX register. */
95#define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_vsr0_regnum \
97 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
98
99/* Determine if regnum is a POWER7 Extended FP register. */
100#define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
101 && (regnum) >= (tdep)->ppc_efpr0_regnum \
102 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_fprs)
103
55eddb0f
DJ		 104/* The list of available "set powerpc ..." and "show powerpc ..."
105 commands. */
106static struct cmd_list_element *setpowerpccmdlist = NULL;
107static struct cmd_list_element *showpowerpccmdlist = NULL;
108
109static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO;
110
111/* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
112static const char *powerpc_vector_strings[] =
113{
114 "auto",
115 "generic",
116 "altivec",
117 "spe",
118 NULL
119};
120
121/* A variable that can be configured by the user. */
122static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO;
123static const char *powerpc_vector_abi_string = "auto";
124
7a78ae4e
ND		 125/* To be used by skip_prologue. */
126
127struct rs6000_framedata
128 {
129 int offset; /* total size of frame --- the distance
130 by which we decrement sp to allocate
131 the frame */
132 int saved_gpr; /* smallest # of saved gpr */
46a9b8ed 133 unsigned int gpr_mask; /* Each bit is an individual saved GPR. */
7a78ae4e 134 int saved_fpr; /* smallest # of saved fpr */
6be8bc0c 135 int saved_vr; /* smallest # of saved vr */
96ff0de4 136 int saved_ev; /* smallest # of saved ev */
7a78ae4e
ND		 137 int alloca_reg; /* alloca register number (frame ptr) */
138 char frameless; /* true if frameless functions. */
139 char nosavedpc; /* true if pc not saved. */
46a9b8ed 140 char used_bl; /* true if link register clobbered */
7a78ae4e
ND		 141 int gpr_offset; /* offset of saved gprs from prev sp */
142 int fpr_offset; /* offset of saved fprs from prev sp */
6be8bc0c 143 int vr_offset; /* offset of saved vrs from prev sp */
96ff0de4 144 int ev_offset; /* offset of saved evs from prev sp */
7a78ae4e 145 int lr_offset; /* offset of saved lr */
46a9b8ed 146 int lr_register; /* register of saved lr, if trustworthy */
7a78ae4e 147 int cr_offset; /* offset of saved cr */
6be8bc0c 148 int vrsave_offset; /* offset of saved vrsave register */
7a78ae4e
ND		 149 };
150
c906108c 151
604c2f83
LM		 152/* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
153int
154vsx_register_p (struct gdbarch *gdbarch, int regno)
155{
156 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
157 if (tdep->ppc_vsr0_regnum < 0)
158 return 0;
159 else
160 return (regno >= tdep->ppc_vsr0_upper_regnum && regno
161 <= tdep->ppc_vsr0_upper_regnum + 31);
162}
163
64b84175
KB		 164/* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
165int
be8626e0 166altivec_register_p (struct gdbarch *gdbarch, int regno)
64b84175 167{
be8626e0 168 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
64b84175
KB		 169 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
170 return 0;
171 else
172 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
173}
174
383f0f5b 175
867e2dc5
JB		 176/* Return true if REGNO is an SPE register, false otherwise. */
177int
be8626e0 178spe_register_p (struct gdbarch *gdbarch, int regno)
867e2dc5 179{
be8626e0 180 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
867e2dc5
JB		 181
182 /* Is it a reference to EV0 -- EV31, and do we have those? */
5a9e69ba 183 if (IS_SPE_PSEUDOREG (tdep, regno))
867e2dc5
JB		 184 return 1;
185
6ced10dd
JB		 186 /* Is it a reference to one of the raw upper GPR halves? */
187 if (tdep->ppc_ev0_upper_regnum >= 0
188 && tdep->ppc_ev0_upper_regnum <= regno
189 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
190 return 1;
191
867e2dc5
JB		 192 /* Is it a reference to the 64-bit accumulator, and do we have that? */
193 if (tdep->ppc_acc_regnum >= 0
194 && tdep->ppc_acc_regnum == regno)
195 return 1;
196
197 /* Is it a reference to the SPE floating-point status and control register,
198 and do we have that? */
199 if (tdep->ppc_spefscr_regnum >= 0
200 && tdep->ppc_spefscr_regnum == regno)
201 return 1;
202
203 return 0;
204}
205
206
383f0f5b
JB		 207/* Return non-zero if the architecture described by GDBARCH has
208 floating-point registers (f0 --- f31 and fpscr). */
0a613259
AC		 209int
210ppc_floating_point_unit_p (struct gdbarch *gdbarch)
211{
383f0f5b
JB		 212 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
213
214 return (tdep->ppc_fp0_regnum >= 0
215 && tdep->ppc_fpscr_regnum >= 0);
0a613259 216}
9f643768 217
604c2f83
LM		 218/* Return non-zero if the architecture described by GDBARCH has
219 VSX registers (vsr0 --- vsr63). */
63807e1d 220static int
604c2f83
LM		 221ppc_vsx_support_p (struct gdbarch *gdbarch)
222{
223 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
224
225 return tdep->ppc_vsr0_regnum >= 0;
226}
227
06caf7d2
CES		 228/* Return non-zero if the architecture described by GDBARCH has
229 Altivec registers (vr0 --- vr31, vrsave and vscr). */
230int
231ppc_altivec_support_p (struct gdbarch *gdbarch)
232{
233 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
234
235 return (tdep->ppc_vr0_regnum >= 0
236 && tdep->ppc_vrsave_regnum >= 0);
237}
09991fa0
JB		 238
239/* Check that TABLE[GDB_REGNO] is not already initialized, and then
240 set it to SIM_REGNO.
241
242 This is a helper function for init_sim_regno_table, constructing
243 the table mapping GDB register numbers to sim register numbers; we
244 initialize every element in that table to -1 before we start
245 filling it in. */
9f643768
JB		 246static void
247set_sim_regno (int *table, int gdb_regno, int sim_regno)
248{
249 /* Make sure we don't try to assign any given GDB register a sim
250 register number more than once. */
251 gdb_assert (table[gdb_regno] == -1);
252 table[gdb_regno] = sim_regno;
253}
254
09991fa0
JB		 255
256/* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
257 numbers to simulator register numbers, based on the values placed
258 in the ARCH->tdep->ppc_foo_regnum members. */
9f643768
JB		 259static void
260init_sim_regno_table (struct gdbarch *arch)
261{
262 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
7cc46491 263 int total_regs = gdbarch_num_regs (arch);
9f643768
JB		 264 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
265 int i;
7cc46491
DJ		 266 static const char *const segment_regs[] = {
267 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
268 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
269 };
9f643768
JB		 270
271 /* Presume that all registers not explicitly mentioned below are
272 unavailable from the sim. */
273 for (i = 0; i < total_regs; i++)
274 sim_regno[i] = -1;
275
276 /* General-purpose registers. */
277 for (i = 0; i < ppc_num_gprs; i++)
278 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
279
280 /* Floating-point registers. */
281 if (tdep->ppc_fp0_regnum >= 0)
282 for (i = 0; i < ppc_num_fprs; i++)
283 set_sim_regno (sim_regno,
284 tdep->ppc_fp0_regnum + i,
285 sim_ppc_f0_regnum + i);
286 if (tdep->ppc_fpscr_regnum >= 0)
287 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
288
289 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
290 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
291 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
292
293 /* Segment registers. */
7cc46491
DJ		 294 for (i = 0; i < ppc_num_srs; i++)
295 {
296 int gdb_regno;
297
298 gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1);
299 if (gdb_regno >= 0)
300 set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i);
301 }
9f643768
JB		 302
303 /* Altivec registers. */
304 if (tdep->ppc_vr0_regnum >= 0)
305 {
306 for (i = 0; i < ppc_num_vrs; i++)
307 set_sim_regno (sim_regno,
308 tdep->ppc_vr0_regnum + i,
309 sim_ppc_vr0_regnum + i);
310
311 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
312 we can treat this more like the other cases. */
313 set_sim_regno (sim_regno,
314 tdep->ppc_vr0_regnum + ppc_num_vrs,
315 sim_ppc_vscr_regnum);
316 }
317 /* vsave is a special-purpose register, so the code below handles it. */
318
319 /* SPE APU (E500) registers. */
6ced10dd
JB		 320 if (tdep->ppc_ev0_upper_regnum >= 0)
321 for (i = 0; i < ppc_num_gprs; i++)
322 set_sim_regno (sim_regno,
323 tdep->ppc_ev0_upper_regnum + i,
324 sim_ppc_rh0_regnum + i);
9f643768
JB		 325 if (tdep->ppc_acc_regnum >= 0)
326 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
327 /* spefscr is a special-purpose register, so the code below handles it. */
328
7cc46491 329#ifdef WITH_SIM
9f643768
JB		 330 /* Now handle all special-purpose registers. Verify that they
331 haven't mistakenly been assigned numbers by any of the above
7cc46491
DJ		 332 code. */
333 for (i = 0; i < sim_ppc_num_sprs; i++)
334 {
335 const char *spr_name = sim_spr_register_name (i);
336 int gdb_regno = -1;
337
338 if (spr_name != NULL)
339 gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1);
340
341 if (gdb_regno != -1)
342 set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i);
343 }
344#endif
9f643768
JB		 345
346 /* Drop the initialized array into place. */
347 tdep->sim_regno = sim_regno;
348}
349
09991fa0
JB		 350
351/* Given a GDB register number REG, return the corresponding SIM
352 register number. */
9f643768 353static int
e7faf938 354rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg)
9f643768 355{
e7faf938 356 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9f643768
JB		 357 int sim_regno;
358
7cc46491 359 if (tdep->sim_regno == NULL)
e7faf938 360 init_sim_regno_table (gdbarch);
7cc46491 361
f57d151a 362 gdb_assert (0 <= reg
e7faf938
MD		 363 && reg <= gdbarch_num_regs (gdbarch)
364 + gdbarch_num_pseudo_regs (gdbarch));
9f643768
JB		 365 sim_regno = tdep->sim_regno[reg];
366
367 if (sim_regno >= 0)
368 return sim_regno;
369 else
370 return LEGACY_SIM_REGNO_IGNORE;
371}
372
d195bc9f
MK		 373\f
374
375/* Register set support functions. */
376
f2db237a
AM		 377/* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
378 Write the register to REGCACHE. */
379
7284e1be 380void
d195bc9f 381ppc_supply_reg (struct regcache *regcache, int regnum,
f2db237a 382 const gdb_byte *regs, size_t offset, int regsize)
d195bc9f
MK		 383{
384 if (regnum != -1 && offset != -1)
f2db237a
AM		 385 {
386 if (regsize > 4)
387 {
388 struct gdbarch *gdbarch = get_regcache_arch (regcache);
389 int gdb_regsize = register_size (gdbarch, regnum);
390 if (gdb_regsize < regsize
391 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
392 offset += regsize - gdb_regsize;
393 }
394 regcache_raw_supply (regcache, regnum, regs + offset);
395 }
d195bc9f
MK		 396}
397
f2db237a
AM		 398/* Read register REGNUM from REGCACHE and store to REGS + OFFSET
399 in a field REGSIZE wide. Zero pad as necessary. */
400
7284e1be 401void
d195bc9f 402ppc_collect_reg (const struct regcache *regcache, int regnum,
f2db237a 403 gdb_byte *regs, size_t offset, int regsize)
d195bc9f
MK		 404{
405 if (regnum != -1 && offset != -1)
f2db237a
AM		 406 {
407 if (regsize > 4)
408 {
409 struct gdbarch *gdbarch = get_regcache_arch (regcache);
410 int gdb_regsize = register_size (gdbarch, regnum);
411 if (gdb_regsize < regsize)
412 {
413 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
414 {
415 memset (regs + offset, 0, regsize - gdb_regsize);
416 offset += regsize - gdb_regsize;
417 }
418 else
419 memset (regs + offset + regsize - gdb_regsize, 0,
420 regsize - gdb_regsize);
421 }
422 }
423 regcache_raw_collect (regcache, regnum, regs + offset);
424 }
d195bc9f
MK		 425}
426
f2db237a
AM		 427static int
428ppc_greg_offset (struct gdbarch *gdbarch,
429 struct gdbarch_tdep *tdep,
430 const struct ppc_reg_offsets *offsets,
431 int regnum,
432 int *regsize)
433{
434 *regsize = offsets->gpr_size;
435 if (regnum >= tdep->ppc_gp0_regnum
436 && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs)
437 return (offsets->r0_offset
438 + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size);
439
440 if (regnum == gdbarch_pc_regnum (gdbarch))
441 return offsets->pc_offset;
442
443 if (regnum == tdep->ppc_ps_regnum)
444 return offsets->ps_offset;
445
446 if (regnum == tdep->ppc_lr_regnum)
447 return offsets->lr_offset;
448
449 if (regnum == tdep->ppc_ctr_regnum)
450 return offsets->ctr_offset;
451
452 *regsize = offsets->xr_size;
453 if (regnum == tdep->ppc_cr_regnum)
454 return offsets->cr_offset;
455
456 if (regnum == tdep->ppc_xer_regnum)
457 return offsets->xer_offset;
458
459 if (regnum == tdep->ppc_mq_regnum)
460 return offsets->mq_offset;
461
462 return -1;
463}
464
465static int
466ppc_fpreg_offset (struct gdbarch_tdep *tdep,
467 const struct ppc_reg_offsets *offsets,
468 int regnum)
469{
470 if (regnum >= tdep->ppc_fp0_regnum
471 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs)
472 return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8;
473
474 if (regnum == tdep->ppc_fpscr_regnum)
475 return offsets->fpscr_offset;
476
477 return -1;
478}
479
06caf7d2
CES		 480static int
481ppc_vrreg_offset (struct gdbarch_tdep *tdep,
482 const struct ppc_reg_offsets *offsets,
483 int regnum)
484{
485 if (regnum >= tdep->ppc_vr0_regnum
486 && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs)
487 return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16;
488
489 if (regnum == tdep->ppc_vrsave_regnum - 1)
490 return offsets->vscr_offset;
491
492 if (regnum == tdep->ppc_vrsave_regnum)
493 return offsets->vrsave_offset;
494
495 return -1;
496}
497
d195bc9f
MK		 498/* Supply register REGNUM in the general-purpose register set REGSET
499 from the buffer specified by GREGS and LEN to register cache
500 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
501
502void
503ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
504 int regnum, const void *gregs, size_t len)
505{
506 struct gdbarch *gdbarch = get_regcache_arch (regcache);
507 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
508 const struct ppc_reg_offsets *offsets = regset->descr;
509 size_t offset;
f2db237a 510 int regsize;
d195bc9f 511
f2db237a 512 if (regnum == -1)
d195bc9f 513 {
f2db237a
AM		 514 int i;
515 int gpr_size = offsets->gpr_size;
516
517 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
518 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
519 i++, offset += gpr_size)
520 ppc_supply_reg (regcache, i, gregs, offset, gpr_size);
521
522 ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch),
523 gregs, offsets->pc_offset, gpr_size);
524 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
525 gregs, offsets->ps_offset, gpr_size);
526 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
527 gregs, offsets->lr_offset, gpr_size);
528 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
529 gregs, offsets->ctr_offset, gpr_size);
530 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
531 gregs, offsets->cr_offset, offsets->xr_size);
532 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
533 gregs, offsets->xer_offset, offsets->xr_size);
534 ppc_supply_reg (regcache, tdep->ppc_mq_regnum,
535 gregs, offsets->mq_offset, offsets->xr_size);
536 return;
d195bc9f
MK		 537 }
538
f2db237a
AM		 539 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
540 ppc_supply_reg (regcache, regnum, gregs, offset, regsize);
d195bc9f
MK		 541}
542
543/* Supply register REGNUM in the floating-point register set REGSET
544 from the buffer specified by FPREGS and LEN to register cache
545 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
546
547void
548ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
549 int regnum, const void *fpregs, size_t len)
550{
551 struct gdbarch *gdbarch = get_regcache_arch (regcache);
f2db237a
AM		 552 struct gdbarch_tdep *tdep;
553 const struct ppc_reg_offsets *offsets;
d195bc9f 554 size_t offset;
d195bc9f 555
f2db237a
AM		 556 if (!ppc_floating_point_unit_p (gdbarch))
557 return;
383f0f5b 558
f2db237a
AM		 559 tdep = gdbarch_tdep (gdbarch);
560 offsets = regset->descr;
561 if (regnum == -1)
d195bc9f 562 {
f2db237a
AM		 563 int i;
564
565 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
566 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
567 i++, offset += 8)
568 ppc_supply_reg (regcache, i, fpregs, offset, 8);
569
570 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
571 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
572 return;
d195bc9f
MK		 573 }
574
f2db237a
AM		 575 offset = ppc_fpreg_offset (tdep, offsets, regnum);
576 ppc_supply_reg (regcache, regnum, fpregs, offset,
577 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
d195bc9f
MK		 578}
579
604c2f83
LM		 580/* Supply register REGNUM in the VSX register set REGSET
581 from the buffer specified by VSXREGS and LEN to register cache
582 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
583
584void
585ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache,
586 int regnum, const void *vsxregs, size_t len)
587{
588 struct gdbarch *gdbarch = get_regcache_arch (regcache);
589 struct gdbarch_tdep *tdep;
590
591 if (!ppc_vsx_support_p (gdbarch))
592 return;
593
594 tdep = gdbarch_tdep (gdbarch);
595
596 if (regnum == -1)
597 {
598 int i;
599
600 for (i = tdep->ppc_vsr0_upper_regnum;
601 i < tdep->ppc_vsr0_upper_regnum + 32;
602 i++)
603 ppc_supply_reg (regcache, i, vsxregs, 0, 8);
604
605 return;
606 }
607 else
608 ppc_supply_reg (regcache, regnum, vsxregs, 0, 8);
609}
610
06caf7d2
CES		 611/* Supply register REGNUM in the Altivec register set REGSET
612 from the buffer specified by VRREGS and LEN to register cache
613 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
614
615void
616ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache,
617 int regnum, const void *vrregs, size_t len)
618{
619 struct gdbarch *gdbarch = get_regcache_arch (regcache);
620 struct gdbarch_tdep *tdep;
621 const struct ppc_reg_offsets *offsets;
622 size_t offset;
623
624 if (!ppc_altivec_support_p (gdbarch))
625 return;
626
627 tdep = gdbarch_tdep (gdbarch);
628 offsets = regset->descr;
629 if (regnum == -1)
630 {
631 int i;
632
633 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
634 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
635 i++, offset += 16)
636 ppc_supply_reg (regcache, i, vrregs, offset, 16);
637
638 ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
639 vrregs, offsets->vscr_offset, 4);
640
641 ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum,
642 vrregs, offsets->vrsave_offset, 4);
643 return;
644 }
645
646 offset = ppc_vrreg_offset (tdep, offsets, regnum);
647 if (regnum != tdep->ppc_vrsave_regnum
648 && regnum != tdep->ppc_vrsave_regnum - 1)
649 ppc_supply_reg (regcache, regnum, vrregs, offset, 16);
650 else
651 ppc_supply_reg (regcache, regnum,
652 vrregs, offset, 4);
653}
654
d195bc9f 655/* Collect register REGNUM in the general-purpose register set
f2db237a 656 REGSET from register cache REGCACHE into the buffer specified by
d195bc9f
MK		 657 GREGS and LEN. If REGNUM is -1, do this for all registers in
658 REGSET. */
659
660void
661ppc_collect_gregset (const struct regset *regset,
662 const struct regcache *regcache,
663 int regnum, void *gregs, size_t len)
664{
665 struct gdbarch *gdbarch = get_regcache_arch (regcache);
666 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
667 const struct ppc_reg_offsets *offsets = regset->descr;
668 size_t offset;
f2db237a 669 int regsize;
d195bc9f 670
f2db237a 671 if (regnum == -1)
d195bc9f 672 {
f2db237a
AM		 673 int i;
674 int gpr_size = offsets->gpr_size;
675
676 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
677 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
678 i++, offset += gpr_size)
679 ppc_collect_reg (regcache, i, gregs, offset, gpr_size);
680
681 ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch),
682 gregs, offsets->pc_offset, gpr_size);
683 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
684 gregs, offsets->ps_offset, gpr_size);
685 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
686 gregs, offsets->lr_offset, gpr_size);
687 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
688 gregs, offsets->ctr_offset, gpr_size);
689 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
690 gregs, offsets->cr_offset, offsets->xr_size);
691 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
692 gregs, offsets->xer_offset, offsets->xr_size);
693 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
694 gregs, offsets->mq_offset, offsets->xr_size);
695 return;
d195bc9f
MK		 696 }
697
f2db237a
AM		 698 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
699 ppc_collect_reg (regcache, regnum, gregs, offset, regsize);
d195bc9f
MK		 700}
701
702/* Collect register REGNUM in the floating-point register set
f2db237a 703 REGSET from register cache REGCACHE into the buffer specified by
d195bc9f
MK		 704 FPREGS and LEN. If REGNUM is -1, do this for all registers in
705 REGSET. */
706
707void
708ppc_collect_fpregset (const struct regset *regset,
709 const struct regcache *regcache,
710 int regnum, void *fpregs, size_t len)
711{
712 struct gdbarch *gdbarch = get_regcache_arch (regcache);
f2db237a
AM		 713 struct gdbarch_tdep *tdep;
714 const struct ppc_reg_offsets *offsets;
d195bc9f 715 size_t offset;
d195bc9f 716
f2db237a
AM		 717 if (!ppc_floating_point_unit_p (gdbarch))
718 return;
383f0f5b 719
f2db237a
AM		 720 tdep = gdbarch_tdep (gdbarch);
721 offsets = regset->descr;
722 if (regnum == -1)
d195bc9f 723 {
f2db237a
AM		 724 int i;
725
726 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
727 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
728 i++, offset += 8)
729 ppc_collect_reg (regcache, i, fpregs, offset, 8);
730
731 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
732 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
733 return;
d195bc9f
MK		 734 }
735
f2db237a
AM		 736 offset = ppc_fpreg_offset (tdep, offsets, regnum);
737 ppc_collect_reg (regcache, regnum, fpregs, offset,
738 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
d195bc9f 739}
06caf7d2 740
604c2f83
LM		 741/* Collect register REGNUM in the VSX register set
742 REGSET from register cache REGCACHE into the buffer specified by
743 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
744 REGSET. */
745
746void
747ppc_collect_vsxregset (const struct regset *regset,
748 const struct regcache *regcache,
749 int regnum, void *vsxregs, size_t len)
750{
751 struct gdbarch *gdbarch = get_regcache_arch (regcache);
752 struct gdbarch_tdep *tdep;
753
754 if (!ppc_vsx_support_p (gdbarch))
755 return;
756
757 tdep = gdbarch_tdep (gdbarch);
758
759 if (regnum == -1)
760 {
761 int i;
762
763 for (i = tdep->ppc_vsr0_upper_regnum;
764 i < tdep->ppc_vsr0_upper_regnum + 32;
765 i++)
766 ppc_collect_reg (regcache, i, vsxregs, 0, 8);
767
768 return;
769 }
770 else
771 ppc_collect_reg (regcache, regnum, vsxregs, 0, 8);
772}
773
774
06caf7d2
CES		 775/* Collect register REGNUM in the Altivec register set
776 REGSET from register cache REGCACHE into the buffer specified by
777 VRREGS and LEN. If REGNUM is -1, do this for all registers in
778 REGSET. */
779
780void
781ppc_collect_vrregset (const struct regset *regset,
782 const struct regcache *regcache,
783 int regnum, void *vrregs, size_t len)
784{
785 struct gdbarch *gdbarch = get_regcache_arch (regcache);
786 struct gdbarch_tdep *tdep;
787 const struct ppc_reg_offsets *offsets;
788 size_t offset;
789
790 if (!ppc_altivec_support_p (gdbarch))
791 return;
792
793 tdep = gdbarch_tdep (gdbarch);
794 offsets = regset->descr;
795 if (regnum == -1)
796 {
797 int i;
798
799 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
800 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
801 i++, offset += 16)
802 ppc_collect_reg (regcache, i, vrregs, offset, 16);
803
804 ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
805 vrregs, offsets->vscr_offset, 4);
806
807 ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum,
808 vrregs, offsets->vrsave_offset, 4);
809 return;
810 }
811
812 offset = ppc_vrreg_offset (tdep, offsets, regnum);
813 if (regnum != tdep->ppc_vrsave_regnum
814 && regnum != tdep->ppc_vrsave_regnum - 1)
815 ppc_collect_reg (regcache, regnum, vrregs, offset, 16);
816 else
817 ppc_collect_reg (regcache, regnum,
818 vrregs, offset, 4);
819}
d195bc9f 820\f
0a613259 821
0d1243d9
PG		 822static int
823insn_changes_sp_or_jumps (unsigned long insn)
824{
825 int opcode = (insn >> 26) & 0x03f;
826 int sd = (insn >> 21) & 0x01f;
827 int a = (insn >> 16) & 0x01f;
828 int subcode = (insn >> 1) & 0x3ff;
829
830 /* Changes the stack pointer. */
831
832 /* NOTE: There are many ways to change the value of a given register.
833 The ways below are those used when the register is R1, the SP,
834 in a funtion's epilogue. */
835
836 if (opcode == 31 && subcode == 444 && a == 1)
837 return 1; /* mr R1,Rn */
838 if (opcode == 14 && sd == 1)
839 return 1; /* addi R1,Rn,simm */
840 if (opcode == 58 && sd == 1)
841 return 1; /* ld R1,ds(Rn) */
842
843 /* Transfers control. */
844
845 if (opcode == 18)
846 return 1; /* b */
847 if (opcode == 16)
848 return 1; /* bc */
849 if (opcode == 19 && subcode == 16)
850 return 1; /* bclr */
851 if (opcode == 19 && subcode == 528)
852 return 1; /* bcctr */
853
854 return 0;
855}
856
857/* Return true if we are in the function's epilogue, i.e. after the
858 instruction that destroyed the function's stack frame.
859
860 1) scan forward from the point of execution:
861 a) If you find an instruction that modifies the stack pointer
862 or transfers control (except a return), execution is not in
863 an epilogue, return.
864 b) Stop scanning if you find a return instruction or reach the
865 end of the function or reach the hard limit for the size of
866 an epilogue.
867 2) scan backward from the point of execution:
868 a) If you find an instruction that modifies the stack pointer,
869 execution *is* in an epilogue, return.
870 b) Stop scanning if you reach an instruction that transfers
871 control or the beginning of the function or reach the hard
872 limit for the size of an epilogue. */
873
874static int
875rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
876{
46a9b8ed 877 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 878 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
0d1243d9
PG		 879 bfd_byte insn_buf[PPC_INSN_SIZE];
880 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
881 unsigned long insn;
882 struct frame_info *curfrm;
883
884 /* Find the search limits based on function boundaries and hard limit. */
885
886 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
887 return 0;
888
889 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
890 if (epilogue_start < func_start) epilogue_start = func_start;
891
892 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
893 if (epilogue_end > func_end) epilogue_end = func_end;
894
895 curfrm = get_current_frame ();
896
897 /* Scan forward until next 'blr'. */
898
899 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
900 {
901 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
902 return 0;
e17a4113 903 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
0d1243d9
PG		 904 if (insn == 0x4e800020)
905 break;
46a9b8ed
DJ		 906 /* Assume a bctr is a tail call unless it points strictly within
907 this function. */
908 if (insn == 0x4e800420)
909 {
910 CORE_ADDR ctr = get_frame_register_unsigned (curfrm,
911 tdep->ppc_ctr_regnum);
912 if (ctr > func_start && ctr < func_end)
913 return 0;
914 else
915 break;
916 }
0d1243d9
PG		 917 if (insn_changes_sp_or_jumps (insn))
918 return 0;
919 }
920
921 /* Scan backward until adjustment to stack pointer (R1). */
922
923 for (scan_pc = pc - PPC_INSN_SIZE;
924 scan_pc >= epilogue_start;
925 scan_pc -= PPC_INSN_SIZE)
926 {
927 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
928 return 0;
e17a4113 929 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
0d1243d9
PG		 930 if (insn_changes_sp_or_jumps (insn))
931 return 1;
932 }
933
934 return 0;
935}
936
143985b7 937/* Get the ith function argument for the current function. */
b9362cc7 938static CORE_ADDR
143985b7
AF		 939rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
940 struct type *type)
941{
50fd1280 942 return get_frame_register_unsigned (frame, 3 + argi);
143985b7
AF		 943}
944
c906108c
SS		 945/* Sequence of bytes for breakpoint instruction. */
946
f4f9705a 947const static unsigned char *
67d57894
MD		 948rs6000_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
949 int *bp_size)
c906108c 950{
aaab4dba
AC		 951 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
952 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
c906108c 953 *bp_size = 4;
67d57894 954 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
c906108c
SS		 955 return big_breakpoint;
956 else
957 return little_breakpoint;
958}
959
f74c6cad
LM		 960/* Instruction masks for displaced stepping. */
961#define BRANCH_MASK 0xfc000000
962#define BP_MASK 0xFC0007FE
963#define B_INSN 0x48000000
964#define BC_INSN 0x40000000
965#define BXL_INSN 0x4c000000
966#define BP_INSN 0x7C000008
967
968/* Fix up the state of registers and memory after having single-stepped
969 a displaced instruction. */
63807e1d 970static void
f74c6cad 971ppc_displaced_step_fixup (struct gdbarch *gdbarch,
63807e1d
PA		 972 struct displaced_step_closure *closure,
973 CORE_ADDR from, CORE_ADDR to,
974 struct regcache *regs)
f74c6cad 975{
e17a4113 976 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
f74c6cad
LM		 977 /* Since we use simple_displaced_step_copy_insn, our closure is a
978 copy of the instruction. */
979 ULONGEST insn = extract_unsigned_integer ((gdb_byte *) closure,
e17a4113 980 PPC_INSN_SIZE, byte_order);
f74c6cad
LM		 981 ULONGEST opcode = 0;
982 /* Offset for non PC-relative instructions. */
983 LONGEST offset = PPC_INSN_SIZE;
984
985 opcode = insn & BRANCH_MASK;
986
987 if (debug_displaced)
988 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 989 "displaced: (ppc) fixup (%s, %s)\n",
990 paddress (gdbarch, from), paddress (gdbarch, to));
f74c6cad
LM		 991
992
993 /* Handle PC-relative branch instructions. */
994 if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN)
995 {
a4fafde3 996 ULONGEST current_pc;
f74c6cad
LM		 997
998 /* Read the current PC value after the instruction has been executed
999 in a displaced location. Calculate the offset to be applied to the
1000 original PC value before the displaced stepping. */
1001 regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1002 &current_pc);
1003 offset = current_pc - to;
1004
1005 if (opcode != BXL_INSN)
1006 {
1007 /* Check for AA bit indicating whether this is an absolute
1008 addressing or PC-relative (1: absolute, 0: relative). */
1009 if (!(insn & 0x2))
1010 {
1011 /* PC-relative addressing is being used in the branch. */
1012 if (debug_displaced)
1013 fprintf_unfiltered
1014 (gdb_stdlog,
5af949e3
UW		 1015 "displaced: (ppc) branch instruction: %s\n"
1016 "displaced: (ppc) adjusted PC from %s to %s\n",
1017 paddress (gdbarch, insn), paddress (gdbarch, current_pc),
1018 paddress (gdbarch, from + offset));
f74c6cad
LM		 1019
1020 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1021 from + offset);
1022 }
1023 }
1024 else
1025 {
1026 /* If we're here, it means we have a branch to LR or CTR. If the
1027 branch was taken, the offset is probably greater than 4 (the next
1028 instruction), so it's safe to assume that an offset of 4 means we
1029 did not take the branch. */
1030 if (offset == PPC_INSN_SIZE)
1031 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1032 from + PPC_INSN_SIZE);
1033 }
1034
1035 /* Check for LK bit indicating whether we should set the link
1036 register to point to the next instruction
1037 (1: Set, 0: Don't set). */
1038 if (insn & 0x1)
1039 {
1040 /* Link register needs to be set to the next instruction's PC. */
1041 regcache_cooked_write_unsigned (regs,
1042 gdbarch_tdep (gdbarch)->ppc_lr_regnum,
1043 from + PPC_INSN_SIZE);
1044 if (debug_displaced)
1045 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 1046 "displaced: (ppc) adjusted LR to %s\n",
1047 paddress (gdbarch, from + PPC_INSN_SIZE));
f74c6cad
LM		 1048
1049 }
1050 }
1051 /* Check for breakpoints in the inferior. If we've found one, place the PC
1052 right at the breakpoint instruction. */
1053 else if ((insn & BP_MASK) == BP_INSN)
1054 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from);
1055 else
1056 /* Handle any other instructions that do not fit in the categories above. */
1057 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1058 from + offset);
1059}
c906108c 1060
99e40580
UW		 1061/* Always use hardware single-stepping to execute the
1062 displaced instruction. */
1063static int
1064ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
1065 struct displaced_step_closure *closure)
1066{
1067 return 1;
1068}
1069
ce5eab59
UW		 1070/* Instruction masks used during single-stepping of atomic sequences. */
1071#define LWARX_MASK 0xfc0007fe
1072#define LWARX_INSTRUCTION 0x7c000028
1073#define LDARX_INSTRUCTION 0x7c0000A8
1074#define STWCX_MASK 0xfc0007ff
1075#define STWCX_INSTRUCTION 0x7c00012d
1076#define STDCX_INSTRUCTION 0x7c0001ad
ce5eab59
UW		 1077
1078/* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1079 instruction and ending with a STWCX/STDCX instruction. If such a sequence
1080 is found, attempt to step through it. A breakpoint is placed at the end of
1081 the sequence. */
1082
4a7622d1
UW		 1083int
1084ppc_deal_with_atomic_sequence (struct frame_info *frame)
ce5eab59 1085{
a6d9a66e 1086 struct gdbarch *gdbarch = get_frame_arch (frame);
6c95b8df 1087 struct address_space *aspace = get_frame_address_space (frame);
e17a4113 1088 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
0b1b3e42 1089 CORE_ADDR pc = get_frame_pc (frame);
ce5eab59
UW		 1090 CORE_ADDR breaks[2] = {-1, -1};
1091 CORE_ADDR loc = pc;
24d45690 1092 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
e17a4113 1093 int insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
ce5eab59
UW		 1094 int insn_count;
1095 int index;
1096 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
1097 const int atomic_sequence_length = 16; /* Instruction sequence length. */
24d45690 1098 int opcode; /* Branch instruction's OPcode. */
ce5eab59
UW		 1099 int bc_insn_count = 0; /* Conditional branch instruction count. */
1100
1101 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1102 if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
1103 && (insn & LWARX_MASK) != LDARX_INSTRUCTION)
1104 return 0;
1105
1106 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1107 instructions. */
1108 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
1109 {
1110 loc += PPC_INSN_SIZE;
e17a4113 1111 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
ce5eab59
UW		 1112
1113 /* Assume that there is at most one conditional branch in the atomic
1114 sequence. If a conditional branch is found, put a breakpoint in
1115 its destination address. */
f74c6cad 1116 if ((insn & BRANCH_MASK) == BC_INSN)
ce5eab59 1117 {
4a7622d1
UW		 1118 int immediate = ((insn & ~3) << 16) >> 16;
1119 int absolute = ((insn >> 1) & 1);
1120
ce5eab59
UW		 1121 if (bc_insn_count >= 1)
1122 return 0; /* More than one conditional branch found, fallback
1123 to the standard single-step code. */
4a7622d1
UW		 1124
1125 if (absolute)
1126 breaks[1] = immediate;
1127 else
1128 breaks[1] = pc + immediate;
1129
1130 bc_insn_count++;
1131 last_breakpoint++;
ce5eab59
UW		 1132 }
1133
1134 if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
1135 || (insn & STWCX_MASK) == STDCX_INSTRUCTION)
1136 break;
1137 }
1138
1139 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1140 if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
1141 && (insn & STWCX_MASK) != STDCX_INSTRUCTION)
1142 return 0;
1143
24d45690 1144 closing_insn = loc;
ce5eab59 1145 loc += PPC_INSN_SIZE;
e17a4113 1146 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
ce5eab59
UW		 1147
1148 /* Insert a breakpoint right after the end of the atomic sequence. */
1149 breaks[0] = loc;
1150
24d45690
UW		 1151 /* Check for duplicated breakpoints. Check also for a breakpoint
1152 placed (branch instruction's destination) at the stwcx/stdcx
1153 instruction, this resets the reservation and take us back to the
1154 lwarx/ldarx instruction at the beginning of the atomic sequence. */
1155 if (last_breakpoint && ((breaks[1] == breaks[0])
1156 || (breaks[1] == closing_insn)))
ce5eab59
UW		 1157 last_breakpoint = 0;
1158
1159 /* Effectively inserts the breakpoints. */
1160 for (index = 0; index <= last_breakpoint; index++)
6c95b8df 1161 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
ce5eab59
UW		 1162
1163 return 1;
1164}
1165
c906108c 1166
c906108c
SS		 1167#define SIGNED_SHORT(x) \
1168 ((sizeof (short) == 2) \
1169 ? ((int)(short)(x)) \
1170 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1171
1172#define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1173
55d05f3b
KB		 1174/* Limit the number of skipped non-prologue instructions, as the examining
1175 of the prologue is expensive. */
1176static int max_skip_non_prologue_insns = 10;
1177
773df3e5
JB		 1178/* Return nonzero if the given instruction OP can be part of the prologue
1179 of a function and saves a parameter on the stack. FRAMEP should be
1180 set if one of the previous instructions in the function has set the
1181 Frame Pointer. */
1182
1183static int
1184store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
1185{
1186 /* Move parameters from argument registers to temporary register. */
1187 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1188 {
1189 /* Rx must be scratch register r0. */
1190 const int rx_regno = (op >> 16) & 31;
1191 /* Ry: Only r3 - r10 are used for parameter passing. */
1192 const int ry_regno = GET_SRC_REG (op);
1193
1194 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
1195 {
1196 *r0_contains_arg = 1;
1197 return 1;
1198 }
1199 else
1200 return 0;
1201 }
1202
1203 /* Save a General Purpose Register on stack. */
1204
1205 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1206 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1207 {
1208 /* Rx: Only r3 - r10 are used for parameter passing. */
1209 const int rx_regno = GET_SRC_REG (op);
1210
1211 return (rx_regno >= 3 && rx_regno <= 10);
1212 }
1213
1214 /* Save a General Purpose Register on stack via the Frame Pointer. */
1215
1216 if (framep &&
1217 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1218 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1219 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1220 {
1221 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1222 However, the compiler sometimes uses r0 to hold an argument. */
1223 const int rx_regno = GET_SRC_REG (op);
1224
1225 return ((rx_regno >= 3 && rx_regno <= 10)
1226 || (rx_regno == 0 && *r0_contains_arg));
1227 }
1228
1229 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1230 {
1231 /* Only f2 - f8 are used for parameter passing. */
1232 const int src_regno = GET_SRC_REG (op);
1233
1234 return (src_regno >= 2 && src_regno <= 8);
1235 }
1236
1237 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1238 {
1239 /* Only f2 - f8 are used for parameter passing. */
1240 const int src_regno = GET_SRC_REG (op);
1241
1242 return (src_regno >= 2 && src_regno <= 8);
1243 }
1244
1245 /* Not an insn that saves a parameter on stack. */
1246 return 0;
1247}
55d05f3b 1248
3c77c82a
DJ		 1249/* Assuming that INSN is a "bl" instruction located at PC, return
1250 nonzero if the destination of the branch is a "blrl" instruction.
1251
1252 This sequence is sometimes found in certain function prologues.
1253 It allows the function to load the LR register with a value that
1254 they can use to access PIC data using PC-relative offsets. */
1255
1256static int
e17a4113 1257bl_to_blrl_insn_p (CORE_ADDR pc, int insn, enum bfd_endian byte_order)
3c77c82a 1258{
0b1b3e42
UW		 1259 CORE_ADDR dest;
1260 int immediate;
1261 int absolute;
3c77c82a
DJ		 1262 int dest_insn;
1263
0b1b3e42
UW		 1264 absolute = (int) ((insn >> 1) & 1);
1265 immediate = ((insn & ~3) << 6) >> 6;
1266 if (absolute)
1267 dest = immediate;
1268 else
1269 dest = pc + immediate;
1270
e17a4113 1271 dest_insn = read_memory_integer (dest, 4, byte_order);
3c77c82a
DJ		 1272 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
1273 return 1;
1274
1275 return 0;
1276}
1277
8ab3d180
KB		 1278/* Masks for decoding a branch-and-link (bl) instruction.
1279
1280 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1281 The former is anded with the opcode in question; if the result of
1282 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1283 question is a ``bl'' instruction.
1284
1285 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1286 the branch displacement. */
1287
1288#define BL_MASK 0xfc000001
1289#define BL_INSTRUCTION 0x48000001
1290#define BL_DISPLACEMENT_MASK 0x03fffffc
1291
de9f48f0 1292static unsigned long
e17a4113 1293rs6000_fetch_instruction (struct gdbarch *gdbarch, const CORE_ADDR pc)
de9f48f0 1294{
e17a4113 1295 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
de9f48f0
JG		 1296 gdb_byte buf[4];
1297 unsigned long op;
1298
1299 /* Fetch the instruction and convert it to an integer. */
1300 if (target_read_memory (pc, buf, 4))
1301 return 0;
e17a4113 1302 op = extract_unsigned_integer (buf, 4, byte_order);
de9f48f0
JG		 1303
1304 return op;
1305}
1306
1307/* GCC generates several well-known sequences of instructions at the begining
1308 of each function prologue when compiling with -fstack-check. If one of
1309 such sequences starts at START_PC, then return the address of the
1310 instruction immediately past this sequence. Otherwise, return START_PC. */
1311
1312static CORE_ADDR
e17a4113 1313rs6000_skip_stack_check (struct gdbarch *gdbarch, const CORE_ADDR start_pc)
de9f48f0
JG		 1314{
1315 CORE_ADDR pc = start_pc;
e17a4113 1316 unsigned long op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1317
1318 /* First possible sequence: A small number of probes.
1319 stw 0, -<some immediate>(1)
1320 [repeat this instruction any (small) number of times]
1321 */
1322
1323 if ((op & 0xffff0000) == 0x90010000)
1324 {
1325 while ((op & 0xffff0000) == 0x90010000)
1326 {
1327 pc = pc + 4;
e17a4113 1328 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1329 }
1330 return pc;
1331 }
1332
1333 /* Second sequence: A probing loop.
1334 addi 12,1,-<some immediate>
1335 lis 0,-<some immediate>
1336 [possibly ori 0,0,<some immediate>]
1337 add 0,12,0
1338 cmpw 0,12,0
1339 beq 0,<disp>
1340 addi 12,12,-<some immediate>
1341 stw 0,0(12)
1342 b <disp>
1343 [possibly one last probe: stw 0,<some immediate>(12)]
1344 */
1345
1346 while (1)
1347 {
1348 /* addi 12,1,-<some immediate> */
1349 if ((op & 0xffff0000) != 0x39810000)
1350 break;
1351
1352 /* lis 0,-<some immediate> */
1353 pc = pc + 4;
e17a4113 1354 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1355 if ((op & 0xffff0000) != 0x3c000000)
1356 break;
1357
1358 pc = pc + 4;
e17a4113 1359 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1360 /* [possibly ori 0,0,<some immediate>] */
1361 if ((op & 0xffff0000) == 0x60000000)
1362 {
1363 pc = pc + 4;
e17a4113 1364 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1365 }
1366 /* add 0,12,0 */
1367 if (op != 0x7c0c0214)
1368 break;
1369
1370 /* cmpw 0,12,0 */
1371 pc = pc + 4;
e17a4113 1372 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1373 if (op != 0x7c0c0000)
1374 break;
1375
1376 /* beq 0,<disp> */
1377 pc = pc + 4;
e17a4113 1378 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1379 if ((op & 0xff9f0001) != 0x41820000)
1380 break;
1381
1382 /* addi 12,12,-<some immediate> */
1383 pc = pc + 4;
e17a4113 1384 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1385 if ((op & 0xffff0000) != 0x398c0000)
1386 break;
1387
1388 /* stw 0,0(12) */
1389 pc = pc + 4;
e17a4113 1390 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1391 if (op != 0x900c0000)
1392 break;
1393
1394 /* b <disp> */
1395 pc = pc + 4;
e17a4113 1396 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1397 if ((op & 0xfc000001) != 0x48000000)
1398 break;
1399
1400 /* [possibly one last probe: stw 0,<some immediate>(12)] */
1401 pc = pc + 4;
e17a4113 1402 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1403 if ((op & 0xffff0000) == 0x900c0000)
1404 {
1405 pc = pc + 4;
e17a4113 1406 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1407 }
1408
1409 /* We found a valid stack-check sequence, return the new PC. */
1410 return pc;
1411 }
1412
1413 /* Third sequence: No probe; instead, a comparizon between the stack size
1414 limit (saved in a run-time global variable) and the current stack
1415 pointer:
1416
1417 addi 0,1,-<some immediate>
1418 lis 12,__gnat_stack_limit@ha
1419 lwz 12,__gnat_stack_limit@l(12)
1420 twllt 0,12
1421
1422 or, with a small variant in the case of a bigger stack frame:
1423 addis 0,1,<some immediate>
1424 addic 0,0,-<some immediate>
1425 lis 12,__gnat_stack_limit@ha
1426 lwz 12,__gnat_stack_limit@l(12)
1427 twllt 0,12
1428 */
1429 while (1)
1430 {
1431 /* addi 0,1,-<some immediate> */
1432 if ((op & 0xffff0000) != 0x38010000)
1433 {
1434 /* small stack frame variant not recognized; try the
1435 big stack frame variant: */
1436
1437 /* addis 0,1,<some immediate> */
1438 if ((op & 0xffff0000) != 0x3c010000)
1439 break;
1440
1441 /* addic 0,0,-<some immediate> */
1442 pc = pc + 4;
e17a4113 1443 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1444 if ((op & 0xffff0000) != 0x30000000)
1445 break;
1446 }
1447
1448 /* lis 12,<some immediate> */
1449 pc = pc + 4;
e17a4113 1450 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1451 if ((op & 0xffff0000) != 0x3d800000)
1452 break;
1453
1454 /* lwz 12,<some immediate>(12) */
1455 pc = pc + 4;
e17a4113 1456 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1457 if ((op & 0xffff0000) != 0x818c0000)
1458 break;
1459
1460 /* twllt 0,12 */
1461 pc = pc + 4;
e17a4113 1462 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1463 if ((op & 0xfffffffe) != 0x7c406008)
1464 break;
1465
1466 /* We found a valid stack-check sequence, return the new PC. */
1467 return pc;
1468 }
1469
1470 /* No stack check code in our prologue, return the start_pc. */
1471 return start_pc;
1472}
1473
6a16c029
TJB		 1474/* return pc value after skipping a function prologue and also return
1475 information about a function frame.
1476
1477 in struct rs6000_framedata fdata:
1478 - frameless is TRUE, if function does not have a frame.
1479 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1480 - offset is the initial size of this stack frame --- the amount by
1481 which we decrement the sp to allocate the frame.
1482 - saved_gpr is the number of the first saved gpr.
1483 - saved_fpr is the number of the first saved fpr.
1484 - saved_vr is the number of the first saved vr.
1485 - saved_ev is the number of the first saved ev.
1486 - alloca_reg is the number of the register used for alloca() handling.
1487 Otherwise -1.
1488 - gpr_offset is the offset of the first saved gpr from the previous frame.
1489 - fpr_offset is the offset of the first saved fpr from the previous frame.
1490 - vr_offset is the offset of the first saved vr from the previous frame.
1491 - ev_offset is the offset of the first saved ev from the previous frame.
1492 - lr_offset is the offset of the saved lr
1493 - cr_offset is the offset of the saved cr
1494 - vrsave_offset is the offset of the saved vrsave register
1495 */
1496
7a78ae4e 1497static CORE_ADDR
be8626e0
MD		 1498skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc,
1499 struct rs6000_framedata *fdata)
c906108c
SS		 1500{
1501 CORE_ADDR orig_pc = pc;
55d05f3b 1502 CORE_ADDR last_prologue_pc = pc;
6be8bc0c 1503 CORE_ADDR li_found_pc = 0;
50fd1280 1504 gdb_byte buf[4];
c906108c
SS		 1505 unsigned long op;
1506 long offset = 0;
6be8bc0c 1507 long vr_saved_offset = 0;
482ca3f5
KB		 1508 int lr_reg = -1;
1509 int cr_reg = -1;
6be8bc0c 1510 int vr_reg = -1;
96ff0de4
EZ		 1511 int ev_reg = -1;
1512 long ev_offset = 0;
6be8bc0c 1513 int vrsave_reg = -1;
c906108c
SS		 1514 int reg;
1515 int framep = 0;
1516 int minimal_toc_loaded = 0;
ddb20c56 1517 int prev_insn_was_prologue_insn = 1;
55d05f3b 1518 int num_skip_non_prologue_insns = 0;
773df3e5 1519 int r0_contains_arg = 0;
be8626e0
MD		 1520 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch);
1521 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 1522 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
c906108c 1523
ddb20c56 1524 memset (fdata, 0, sizeof (struct rs6000_framedata));
c906108c
SS		 1525 fdata->saved_gpr = -1;
1526 fdata->saved_fpr = -1;
6be8bc0c 1527 fdata->saved_vr = -1;
96ff0de4 1528 fdata->saved_ev = -1;
c906108c
SS		 1529 fdata->alloca_reg = -1;
1530 fdata->frameless = 1;
1531 fdata->nosavedpc = 1;
46a9b8ed 1532 fdata->lr_register = -1;
c906108c 1533
e17a4113 1534 pc = rs6000_skip_stack_check (gdbarch, pc);
de9f48f0
JG		 1535 if (pc >= lim_pc)
1536 pc = lim_pc;
1537
55d05f3b 1538 for (;; pc += 4)
c906108c 1539 {
ddb20c56
KB		 1540 /* Sometimes it isn't clear if an instruction is a prologue
1541 instruction or not. When we encounter one of these ambiguous
1542 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1543 Otherwise, we'll assume that it really is a prologue instruction. */
1544 if (prev_insn_was_prologue_insn)
1545 last_prologue_pc = pc;
55d05f3b
KB		 1546
1547 /* Stop scanning if we've hit the limit. */
4e463ff5 1548 if (pc >= lim_pc)
55d05f3b
KB		 1549 break;
1550
ddb20c56
KB		 1551 prev_insn_was_prologue_insn = 1;
1552
55d05f3b 1553 /* Fetch the instruction and convert it to an integer. */
ddb20c56
KB		 1554 if (target_read_memory (pc, buf, 4))
1555 break;
e17a4113 1556 op = extract_unsigned_integer (buf, 4, byte_order);
c906108c 1557
c5aa993b
JM		 1558 if ((op & 0xfc1fffff) == 0x7c0802a6)
1559 { /* mflr Rx */
43b1ab88
AC		 1560 /* Since shared library / PIC code, which needs to get its
1561 address at runtime, can appear to save more than one link
1562 register vis:
1563
1564 *INDENT-OFF*
1565 stwu r1,-304(r1)
1566 mflr r3
1567 bl 0xff570d0 (blrl)
1568 stw r30,296(r1)
1569 mflr r30
1570 stw r31,300(r1)
1571 stw r3,308(r1);
1572 ...
1573 *INDENT-ON*
1574
1575 remember just the first one, but skip over additional
1576 ones. */
721d14ba 1577 if (lr_reg == -1)
46a9b8ed 1578 lr_reg = (op & 0x03e00000) >> 21;
773df3e5
JB		 1579 if (lr_reg == 0)
1580 r0_contains_arg = 0;
c5aa993b 1581 continue;
c5aa993b
JM		 1582 }
1583 else if ((op & 0xfc1fffff) == 0x7c000026)
1584 { /* mfcr Rx */
98f08d3d 1585 cr_reg = (op & 0x03e00000);
773df3e5
JB		 1586 if (cr_reg == 0)
1587 r0_contains_arg = 0;
c5aa993b 1588 continue;
c906108c 1589
c906108c 1590 }
c5aa993b
JM		 1591 else if ((op & 0xfc1f0000) == 0xd8010000)
1592 { /* stfd Rx,NUM(r1) */
1593 reg = GET_SRC_REG (op);
1594 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1595 {
1596 fdata->saved_fpr = reg;
1597 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1598 }
1599 continue;
c906108c 1600
c5aa993b
JM		 1601 }
1602 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
7a78ae4e
ND		 1603 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1604 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1605 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
c5aa993b
JM		 1606 {
1607
1608 reg = GET_SRC_REG (op);
46a9b8ed
DJ		 1609 if ((op & 0xfc1f0000) == 0xbc010000)
1610 fdata->gpr_mask |= ~((1U << reg) - 1);
1611 else
1612 fdata->gpr_mask |= 1U << reg;
c5aa993b
JM		 1613 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1614 {
1615 fdata->saved_gpr = reg;
7a78ae4e 1616 if ((op & 0xfc1f0003) == 0xf8010000)
98f08d3d 1617 op &= ~3UL;
c5aa993b
JM		 1618 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1619 }
1620 continue;
c906108c 1621
ddb20c56
KB		 1622 }
1623 else if ((op & 0xffff0000) == 0x60000000)
1624 {
96ff0de4 1625 /* nop */
ddb20c56
KB		 1626 /* Allow nops in the prologue, but do not consider them to
1627 be part of the prologue unless followed by other prologue
1628 instructions. */
1629 prev_insn_was_prologue_insn = 0;
1630 continue;
1631
c906108c 1632 }
c5aa993b
JM		 1633 else if ((op & 0xffff0000) == 0x3c000000)
1634 { /* addis 0,0,NUM, used
1635 for >= 32k frames */
1636 fdata->offset = (op & 0x0000ffff) << 16;
1637 fdata->frameless = 0;
773df3e5 1638 r0_contains_arg = 0;
c5aa993b
JM		 1639 continue;
1640
1641 }
1642 else if ((op & 0xffff0000) == 0x60000000)
1643 { /* ori 0,0,NUM, 2nd ha
1644 lf of >= 32k frames */
1645 fdata->offset |= (op & 0x0000ffff);
1646 fdata->frameless = 0;
773df3e5 1647 r0_contains_arg = 0;
c5aa993b
JM		 1648 continue;
1649
1650 }
be723e22 1651 else if (lr_reg >= 0 &&
98f08d3d
KB		 1652 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1653 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1654 /* stw Rx, NUM(r1) */
1655 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1656 /* stwu Rx, NUM(r1) */
1657 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1658 { /* where Rx == lr */
1659 fdata->lr_offset = offset;
c5aa993b 1660 fdata->nosavedpc = 0;
be723e22
MS		 1661 /* Invalidate lr_reg, but don't set it to -1.
1662 That would mean that it had never been set. */
1663 lr_reg = -2;
98f08d3d
KB		 1664 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1665 (op & 0xfc000000) == 0x90000000) /* stw */
1666 {
1667 /* Does not update r1, so add displacement to lr_offset. */
1668 fdata->lr_offset += SIGNED_SHORT (op);
1669 }
c5aa993b
JM		 1670 continue;
1671
1672 }
be723e22 1673 else if (cr_reg >= 0 &&
98f08d3d
KB		 1674 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1675 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1676 /* stw Rx, NUM(r1) */
1677 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1678 /* stwu Rx, NUM(r1) */
1679 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1680 { /* where Rx == cr */
1681 fdata->cr_offset = offset;
be723e22
MS		 1682 /* Invalidate cr_reg, but don't set it to -1.
1683 That would mean that it had never been set. */
1684 cr_reg = -2;
98f08d3d
KB		 1685 if ((op & 0xfc000003) == 0xf8000000 ||
1686 (op & 0xfc000000) == 0x90000000)
1687 {
1688 /* Does not update r1, so add displacement to cr_offset. */
1689 fdata->cr_offset += SIGNED_SHORT (op);
1690 }
c5aa993b
JM		 1691 continue;
1692
1693 }
721d14ba
DJ		 1694 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1695 {
1696 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1697 prediction bits. If the LR has already been saved, we can
1698 skip it. */
1699 continue;
1700 }
c5aa993b
JM		 1701 else if (op == 0x48000005)
1702 { /* bl .+4 used in
1703 -mrelocatable */
46a9b8ed 1704 fdata->used_bl = 1;
c5aa993b
JM		 1705 continue;
1706
1707 }
1708 else if (op == 0x48000004)
1709 { /* b .+4 (xlc) */
1710 break;
1711
c5aa993b 1712 }
6be8bc0c
EZ		 1713 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1714 in V.4 -mminimal-toc */
c5aa993b
JM		 1715 (op & 0xffff0000) == 0x3bde0000)
1716 { /* addi 30,30,foo@l */
1717 continue;
c906108c 1718
c5aa993b
JM		 1719 }
1720 else if ((op & 0xfc000001) == 0x48000001)
1721 { /* bl foo,
1722 to save fprs??? */
c906108c 1723
c5aa993b 1724 fdata->frameless = 0;
3c77c82a
DJ		 1725
1726 /* If the return address has already been saved, we can skip
1727 calls to blrl (for PIC). */
e17a4113 1728 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op, byte_order))
46a9b8ed
DJ		 1729 {
1730 fdata->used_bl = 1;
1731 continue;
1732 }
3c77c82a 1733
6be8bc0c 1734 /* Don't skip over the subroutine call if it is not within
ebd98106
FF		 1735 the first three instructions of the prologue and either
1736 we have no line table information or the line info tells
1737 us that the subroutine call is not part of the line
1738 associated with the prologue. */
c5aa993b 1739 if ((pc - orig_pc) > 8)
ebd98106
FF		 1740 {
1741 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1742 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1743
1744 if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line))
1745 break;
1746 }
c5aa993b 1747
e17a4113 1748 op = read_memory_integer (pc + 4, 4, byte_order);
c5aa993b 1749
6be8bc0c
EZ		 1750 /* At this point, make sure this is not a trampoline
1751 function (a function that simply calls another functions,
1752 and nothing else). If the next is not a nop, this branch
1753 was part of the function prologue. */
c5aa993b
JM		 1754
1755 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1756 break; /* don't skip over
1757 this branch */
c5aa993b 1758
46a9b8ed
DJ		 1759 fdata->used_bl = 1;
1760 continue;
c5aa993b 1761 }
98f08d3d
KB		 1762 /* update stack pointer */
1763 else if ((op & 0xfc1f0000) == 0x94010000)
1764 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
c5aa993b
JM		 1765 fdata->frameless = 0;
1766 fdata->offset = SIGNED_SHORT (op);
1767 offset = fdata->offset;
1768 continue;
c5aa993b 1769 }
98f08d3d
KB		 1770 else if ((op & 0xfc1f016a) == 0x7c01016e)
1771 { /* stwux rX,r1,rY */
1772 /* no way to figure out what r1 is going to be */
1773 fdata->frameless = 0;
1774 offset = fdata->offset;
1775 continue;
1776 }
1777 else if ((op & 0xfc1f0003) == 0xf8010001)
1778 { /* stdu rX,NUM(r1) */
1779 fdata->frameless = 0;
1780 fdata->offset = SIGNED_SHORT (op & ~3UL);
1781 offset = fdata->offset;
1782 continue;
1783 }
1784 else if ((op & 0xfc1f016a) == 0x7c01016a)
1785 { /* stdux rX,r1,rY */
1786 /* no way to figure out what r1 is going to be */
c5aa993b
JM		 1787 fdata->frameless = 0;
1788 offset = fdata->offset;
1789 continue;
c5aa993b 1790 }
7313566f
FF		 1791 else if ((op & 0xffff0000) == 0x38210000)
1792 { /* addi r1,r1,SIMM */
1793 fdata->frameless = 0;
1794 fdata->offset += SIGNED_SHORT (op);
1795 offset = fdata->offset;
1796 continue;
1797 }
4e463ff5
DJ		 1798 /* Load up minimal toc pointer. Do not treat an epilogue restore
1799 of r31 as a minimal TOC load. */
98f08d3d
KB		 1800 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1801 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
4e463ff5 1802 && !framep
c5aa993b 1803 && !minimal_toc_loaded)
98f08d3d 1804 {
c5aa993b
JM		 1805 minimal_toc_loaded = 1;
1806 continue;
1807
f6077098
KB		 1808 /* move parameters from argument registers to local variable
1809 registers */
1810 }
1811 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1812 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1813 (((op >> 21) & 31) <= 10) &&
96ff0de4 1814 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
f6077098
KB		 1815 {
1816 continue;
1817
c5aa993b
JM		 1818 /* store parameters in stack */
1819 }
e802b915 1820 /* Move parameters from argument registers to temporary register. */
773df3e5 1821 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
e802b915 1822 {
c5aa993b
JM		 1823 continue;
1824
1825 /* Set up frame pointer */
1826 }
1827 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1828 || op == 0x7c3f0b78)
1829 { /* mr r31, r1 */
1830 fdata->frameless = 0;
1831 framep = 1;
6f99cb26 1832 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
c5aa993b
JM		 1833 continue;
1834
1835 /* Another way to set up the frame pointer. */
1836 }
1837 else if ((op & 0xfc1fffff) == 0x38010000)
1838 { /* addi rX, r1, 0x0 */
1839 fdata->frameless = 0;
1840 framep = 1;
6f99cb26
AC		 1841 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1842 + ((op & ~0x38010000) >> 21));
c5aa993b 1843 continue;
c5aa993b 1844 }
6be8bc0c
EZ		 1845 /* AltiVec related instructions. */
1846 /* Store the vrsave register (spr 256) in another register for
1847 later manipulation, or load a register into the vrsave
1848 register. 2 instructions are used: mfvrsave and
1849 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1850 and mtspr SPR256, Rn. */
1851 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1852 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1853 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1854 {
1855 vrsave_reg = GET_SRC_REG (op);
1856 continue;
1857 }
1858 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1859 {
1860 continue;
1861 }
1862 /* Store the register where vrsave was saved to onto the stack:
1863 rS is the register where vrsave was stored in a previous
1864 instruction. */
1865 /* 100100 sssss 00001 dddddddd dddddddd */
1866 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1867 {
1868 if (vrsave_reg == GET_SRC_REG (op))
1869 {
1870 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1871 vrsave_reg = -1;
1872 }
1873 continue;
1874 }
1875 /* Compute the new value of vrsave, by modifying the register
1876 where vrsave was saved to. */
1877 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1878 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1879 {
1880 continue;
1881 }
1882 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1883 in a pair of insns to save the vector registers on the
1884 stack. */
1885 /* 001110 00000 00000 iiii iiii iiii iiii */
96ff0de4
EZ		 1886 /* 001110 01110 00000 iiii iiii iiii iiii */
1887 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1888 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
6be8bc0c 1889 {
773df3e5
JB		 1890 if ((op & 0xffff0000) == 0x38000000)
1891 r0_contains_arg = 0;
6be8bc0c
EZ		 1892 li_found_pc = pc;
1893 vr_saved_offset = SIGNED_SHORT (op);
773df3e5
JB		 1894
1895 /* This insn by itself is not part of the prologue, unless
1896 if part of the pair of insns mentioned above. So do not
1897 record this insn as part of the prologue yet. */
1898 prev_insn_was_prologue_insn = 0;
6be8bc0c
EZ		 1899 }
1900 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1901 /* 011111 sssss 11111 00000 00111001110 */
1902 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1903 {
1904 if (pc == (li_found_pc + 4))
1905 {
1906 vr_reg = GET_SRC_REG (op);
1907 /* If this is the first vector reg to be saved, or if
1908 it has a lower number than others previously seen,
1909 reupdate the frame info. */
1910 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1911 {
1912 fdata->saved_vr = vr_reg;
1913 fdata->vr_offset = vr_saved_offset + offset;
1914 }
1915 vr_saved_offset = -1;
1916 vr_reg = -1;
1917 li_found_pc = 0;
1918 }
1919 }
1920 /* End AltiVec related instructions. */
96ff0de4
EZ		 1921
1922 /* Start BookE related instructions. */
1923 /* Store gen register S at (r31+uimm).
1924 Any register less than r13 is volatile, so we don't care. */
1925 /* 000100 sssss 11111 iiiii 01100100001 */
1926 else if (arch_info->mach == bfd_mach_ppc_e500
1927 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1928 {
1929 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1930 {
1931 unsigned int imm;
1932 ev_reg = GET_SRC_REG (op);
1933 imm = (op >> 11) & 0x1f;
1934 ev_offset = imm * 8;
1935 /* If this is the first vector reg to be saved, or if
1936 it has a lower number than others previously seen,
1937 reupdate the frame info. */
1938 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1939 {
1940 fdata->saved_ev = ev_reg;
1941 fdata->ev_offset = ev_offset + offset;
1942 }
1943 }
1944 continue;
1945 }
1946 /* Store gen register rS at (r1+rB). */
1947 /* 000100 sssss 00001 bbbbb 01100100000 */
1948 else if (arch_info->mach == bfd_mach_ppc_e500
1949 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1950 {
1951 if (pc == (li_found_pc + 4))
1952 {
1953 ev_reg = GET_SRC_REG (op);
1954 /* If this is the first vector reg to be saved, or if
1955 it has a lower number than others previously seen,
1956 reupdate the frame info. */
1957 /* We know the contents of rB from the previous instruction. */
1958 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1959 {
1960 fdata->saved_ev = ev_reg;
1961 fdata->ev_offset = vr_saved_offset + offset;
1962 }
1963 vr_saved_offset = -1;
1964 ev_reg = -1;
1965 li_found_pc = 0;
1966 }
1967 continue;
1968 }
1969 /* Store gen register r31 at (rA+uimm). */
1970 /* 000100 11111 aaaaa iiiii 01100100001 */
1971 else if (arch_info->mach == bfd_mach_ppc_e500
1972 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1973 {
1974 /* Wwe know that the source register is 31 already, but
1975 it can't hurt to compute it. */
1976 ev_reg = GET_SRC_REG (op);
1977 ev_offset = ((op >> 11) & 0x1f) * 8;
1978 /* If this is the first vector reg to be saved, or if
1979 it has a lower number than others previously seen,
1980 reupdate the frame info. */
1981 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1982 {
1983 fdata->saved_ev = ev_reg;
1984 fdata->ev_offset = ev_offset + offset;
1985 }
1986
1987 continue;
1988 }
1989 /* Store gen register S at (r31+r0).
1990 Store param on stack when offset from SP bigger than 4 bytes. */
1991 /* 000100 sssss 11111 00000 01100100000 */
1992 else if (arch_info->mach == bfd_mach_ppc_e500
1993 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1994 {
1995 if (pc == (li_found_pc + 4))
1996 {
1997 if ((op & 0x03e00000) >= 0x01a00000)
1998 {
1999 ev_reg = GET_SRC_REG (op);
2000 /* If this is the first vector reg to be saved, or if
2001 it has a lower number than others previously seen,
2002 reupdate the frame info. */
2003 /* We know the contents of r0 from the previous
2004 instruction. */
2005 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
2006 {
2007 fdata->saved_ev = ev_reg;
2008 fdata->ev_offset = vr_saved_offset + offset;
2009 }
2010 ev_reg = -1;
2011 }
2012 vr_saved_offset = -1;
2013 li_found_pc = 0;
2014 continue;
2015 }
2016 }
2017 /* End BookE related instructions. */
2018
c5aa993b
JM		 2019 else
2020 {
46a9b8ed
DJ		 2021 unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1);
2022
55d05f3b
KB		 2023 /* Not a recognized prologue instruction.
2024 Handle optimizer code motions into the prologue by continuing
2025 the search if we have no valid frame yet or if the return
46a9b8ed
DJ		 2026 address is not yet saved in the frame. Also skip instructions
2027 if some of the GPRs expected to be saved are not yet saved. */
2028 if (fdata->frameless == 0 && fdata->nosavedpc == 0
2029 && (fdata->gpr_mask & all_mask) == all_mask)
55d05f3b
KB		 2030 break;
2031
2032 if (op == 0x4e800020 /* blr */
2033 || op == 0x4e800420) /* bctr */
2034 /* Do not scan past epilogue in frameless functions or
2035 trampolines. */
2036 break;
2037 if ((op & 0xf4000000) == 0x40000000) /* bxx */
64366f1c 2038 /* Never skip branches. */
55d05f3b
KB		 2039 break;
2040
2041 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
2042 /* Do not scan too many insns, scanning insns is expensive with
2043 remote targets. */
2044 break;
2045
2046 /* Continue scanning. */
2047 prev_insn_was_prologue_insn = 0;
2048 continue;
c5aa993b 2049 }
c906108c
SS		 2050 }
2051
2052#if 0
2053/* I have problems with skipping over __main() that I need to address
2054 * sometime. Previously, I used to use misc_function_vector which
2055 * didn't work as well as I wanted to be. -MGO */
2056
2057 /* If the first thing after skipping a prolog is a branch to a function,
2058 this might be a call to an initializer in main(), introduced by gcc2.
64366f1c 2059 We'd like to skip over it as well. Fortunately, xlc does some extra
c906108c 2060 work before calling a function right after a prologue, thus we can
64366f1c 2061 single out such gcc2 behaviour. */
c906108c 2062
c906108c 2063
c5aa993b
JM		 2064 if ((op & 0xfc000001) == 0x48000001)
2065 { /* bl foo, an initializer function? */
e17a4113 2066 op = read_memory_integer (pc + 4, 4, byte_order);
c5aa993b
JM		 2067
2068 if (op == 0x4def7b82)
2069 { /* cror 0xf, 0xf, 0xf (nop) */
c906108c 2070
64366f1c
EZ		 2071 /* Check and see if we are in main. If so, skip over this
2072 initializer function as well. */
c906108c 2073
c5aa993b 2074 tmp = find_pc_misc_function (pc);
6314a349
AC		 2075 if (tmp >= 0
2076 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
c5aa993b
JM		 2077 return pc + 8;
2078 }
c906108c 2079 }
c906108c 2080#endif /* 0 */
c5aa993b 2081
46a9b8ed
DJ		 2082 if (pc == lim_pc && lr_reg >= 0)
2083 fdata->lr_register = lr_reg;
2084
c5aa993b 2085 fdata->offset = -fdata->offset;
ddb20c56 2086 return last_prologue_pc;
c906108c
SS		 2087}
2088
7a78ae4e 2089static CORE_ADDR
4a7622d1 2090rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
c906108c 2091{
4a7622d1
UW		 2092 struct rs6000_framedata frame;
2093 CORE_ADDR limit_pc, func_addr;
c906108c 2094
4a7622d1
UW		 2095 /* See if we can determine the end of the prologue via the symbol table.
2096 If so, then return either PC, or the PC after the prologue, whichever
2097 is greater. */
2098 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
c5aa993b 2099 {
d80b854b
UW		 2100 CORE_ADDR post_prologue_pc
2101 = skip_prologue_using_sal (gdbarch, func_addr);
4a7622d1
UW		 2102 if (post_prologue_pc != 0)
2103 return max (pc, post_prologue_pc);
c906108c 2104 }
c906108c 2105
4a7622d1
UW		 2106 /* Can't determine prologue from the symbol table, need to examine
2107 instructions. */
c906108c 2108
4a7622d1
UW		 2109 /* Find an upper limit on the function prologue using the debug
2110 information. If the debug information could not be used to provide
2111 that bound, then use an arbitrary large number as the upper bound. */
d80b854b 2112 limit_pc = skip_prologue_using_sal (gdbarch, pc);
4a7622d1
UW		 2113 if (limit_pc == 0)
2114 limit_pc = pc + 100; /* Magic. */
794a477a 2115
4a7622d1
UW		 2116 pc = skip_prologue (gdbarch, pc, limit_pc, &frame);
2117 return pc;
c906108c 2118}
c906108c 2119
8ab3d180
KB		 2120/* When compiling for EABI, some versions of GCC emit a call to __eabi
2121 in the prologue of main().
2122
2123 The function below examines the code pointed at by PC and checks to
2124 see if it corresponds to a call to __eabi. If so, it returns the
2125 address of the instruction following that call. Otherwise, it simply
2126 returns PC. */
2127
63807e1d 2128static CORE_ADDR
8ab3d180
KB		 2129rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2130{
e17a4113 2131 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8ab3d180
KB		 2132 gdb_byte buf[4];
2133 unsigned long op;
2134
2135 if (target_read_memory (pc, buf, 4))
2136 return pc;
e17a4113 2137 op = extract_unsigned_integer (buf, 4, byte_order);
8ab3d180
KB		 2138
2139 if ((op & BL_MASK) == BL_INSTRUCTION)
2140 {
2141 CORE_ADDR displ = op & BL_DISPLACEMENT_MASK;
2142 CORE_ADDR call_dest = pc + 4 + displ;
2143 struct minimal_symbol *s = lookup_minimal_symbol_by_pc (call_dest);
2144
2145 /* We check for ___eabi (three leading underscores) in addition
2146 to __eabi in case the GCC option "-fleading-underscore" was
2147 used to compile the program. */
2148 if (s != NULL
2149 && SYMBOL_LINKAGE_NAME (s) != NULL
2150 && (strcmp (SYMBOL_LINKAGE_NAME (s), "__eabi") == 0
2151 || strcmp (SYMBOL_LINKAGE_NAME (s), "___eabi") == 0))
2152 pc += 4;
2153 }
2154 return pc;
2155}
383f0f5b 2156
4a7622d1
UW		 2157/* All the ABI's require 16 byte alignment. */
2158static CORE_ADDR
2159rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2160{
2161 return (addr & -16);
c906108c
SS		 2162}
2163
977adac5
ND		 2164/* Return whether handle_inferior_event() should proceed through code
2165 starting at PC in function NAME when stepping.
2166
2167 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2168 handle memory references that are too distant to fit in instructions
2169 generated by the compiler. For example, if 'foo' in the following
2170 instruction:
2171
2172 lwz r9,foo(r2)
2173
2174 is greater than 32767, the linker might replace the lwz with a branch to
2175 somewhere in @FIX1 that does the load in 2 instructions and then branches
2176 back to where execution should continue.
2177
2178 GDB should silently step over @FIX code, just like AIX dbx does.
2ec664f5
MS		 2179 Unfortunately, the linker uses the "b" instruction for the
2180 branches, meaning that the link register doesn't get set.
2181 Therefore, GDB's usual step_over_function () mechanism won't work.
977adac5 2182
e76f05fa
UW		 2183 Instead, use the gdbarch_skip_trampoline_code and
2184 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2ec664f5 2185 @FIX code. */
977adac5 2186
63807e1d 2187static int
e17a4113
UW		 2188rs6000_in_solib_return_trampoline (struct gdbarch *gdbarch,
2189 CORE_ADDR pc, char *name)
977adac5
ND		 2190{
2191 return name && !strncmp (name, "@FIX", 4);
2192}
2193
2194/* Skip code that the user doesn't want to see when stepping:
2195
2196 1. Indirect function calls use a piece of trampoline code to do context
2197 switching, i.e. to set the new TOC table. Skip such code if we are on
2198 its first instruction (as when we have single-stepped to here).
2199
2200 2. Skip shared library trampoline code (which is different from
c906108c 2201 indirect function call trampolines).
977adac5
ND		 2202
2203 3. Skip bigtoc fixup code.
2204
c906108c 2205 Result is desired PC to step until, or NULL if we are not in
977adac5 2206 code that should be skipped. */
c906108c 2207
63807e1d 2208static CORE_ADDR
52f729a7 2209rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
c906108c 2210{
e17a4113
UW		 2211 struct gdbarch *gdbarch = get_frame_arch (frame);
2212 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2213 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
52f0bd74 2214 unsigned int ii, op;
977adac5 2215 int rel;
c906108c 2216 CORE_ADDR solib_target_pc;
977adac5 2217 struct minimal_symbol *msymbol;
c906108c 2218
c5aa993b
JM		 2219 static unsigned trampoline_code[] =
2220 {
2221 0x800b0000, /* l r0,0x0(r11) */
2222 0x90410014, /* st r2,0x14(r1) */
2223 0x7c0903a6, /* mtctr r0 */
2224 0x804b0004, /* l r2,0x4(r11) */
2225 0x816b0008, /* l r11,0x8(r11) */
2226 0x4e800420, /* bctr */
2227 0x4e800020, /* br */
2228 0
c906108c
SS		 2229 };
2230
977adac5
ND		 2231 /* Check for bigtoc fixup code. */
2232 msymbol = lookup_minimal_symbol_by_pc (pc);
2ec664f5 2233 if (msymbol
e17a4113
UW		 2234 && rs6000_in_solib_return_trampoline (gdbarch, pc,
2235 SYMBOL_LINKAGE_NAME (msymbol)))
977adac5
ND		 2236 {
2237 /* Double-check that the third instruction from PC is relative "b". */
e17a4113 2238 op = read_memory_integer (pc + 8, 4, byte_order);
977adac5
ND		 2239 if ((op & 0xfc000003) == 0x48000000)
2240 {
2241 /* Extract bits 6-29 as a signed 24-bit relative word address and
2242 add it to the containing PC. */
2243 rel = ((int)(op << 6) >> 6);
2244 return pc + 8 + rel;
2245 }
2246 }
2247
c906108c 2248 /* If pc is in a shared library trampoline, return its target. */
52f729a7 2249 solib_target_pc = find_solib_trampoline_target (frame, pc);
c906108c
SS		 2250 if (solib_target_pc)
2251 return solib_target_pc;
2252
c5aa993b
JM		 2253 for (ii = 0; trampoline_code[ii]; ++ii)
2254 {
e17a4113 2255 op = read_memory_integer (pc + (ii * 4), 4, byte_order);
c5aa993b
JM		 2256 if (op != trampoline_code[ii])
2257 return 0;
2258 }
52f729a7 2259 ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination addr */
e17a4113 2260 pc = read_memory_unsigned_integer (ii, tdep->wordsize, byte_order);
c906108c
SS		 2261 return pc;
2262}
2263
794ac428
UW		 2264/* ISA-specific vector types. */
2265
2266static struct type *
2267rs6000_builtin_type_vec64 (struct gdbarch *gdbarch)
2268{
2269 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2270
2271 if (!tdep->ppc_builtin_type_vec64)
2272 {
df4df182
UW		 2273 const struct builtin_type *bt = builtin_type (gdbarch);
2274
794ac428
UW		 2275 /* The type we're building is this: */
2276#if 0
2277 union __gdb_builtin_type_vec64
2278 {
2279 int64_t uint64;
2280 float v2_float[2];
2281 int32_t v2_int32[2];
2282 int16_t v4_int16[4];
2283 int8_t v8_int8[8];
2284 };
2285#endif
2286
2287 struct type *t;
2288
e9bb382b
UW		 2289 t = arch_composite_type (gdbarch,
2290 "__ppc_builtin_type_vec64", TYPE_CODE_UNION);
df4df182 2291 append_composite_type_field (t, "uint64", bt->builtin_int64);
794ac428 2292 append_composite_type_field (t, "v2_float",
df4df182 2293 init_vector_type (bt->builtin_float, 2));
794ac428 2294 append_composite_type_field (t, "v2_int32",
df4df182 2295 init_vector_type (bt->builtin_int32, 2));
794ac428 2296 append_composite_type_field (t, "v4_int16",
df4df182 2297 init_vector_type (bt->builtin_int16, 4));
794ac428 2298 append_composite_type_field (t, "v8_int8",
df4df182 2299 init_vector_type (bt->builtin_int8, 8));
794ac428 2300
876cecd0 2301 TYPE_VECTOR (t) = 1;
794ac428
UW		 2302 TYPE_NAME (t) = "ppc_builtin_type_vec64";
2303 tdep->ppc_builtin_type_vec64 = t;
2304 }
2305
2306 return tdep->ppc_builtin_type_vec64;
2307}
2308
604c2f83
LM		 2309/* Vector 128 type. */
2310
2311static struct type *
2312rs6000_builtin_type_vec128 (struct gdbarch *gdbarch)
2313{
2314 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2315
2316 if (!tdep->ppc_builtin_type_vec128)
2317 {
df4df182
UW		 2318 const struct builtin_type *bt = builtin_type (gdbarch);
2319
604c2f83
LM		 2320 /* The type we're building is this
2321
2322 type = union __ppc_builtin_type_vec128 {
2323 uint128_t uint128;
db9f5df8 2324 double v2_double[2];
604c2f83
LM		 2325 float v4_float[4];
2326 int32_t v4_int32[4];
2327 int16_t v8_int16[8];
2328 int8_t v16_int8[16];
2329 }
2330 */
2331
2332 struct type *t;
2333
e9bb382b
UW		 2334 t = arch_composite_type (gdbarch,
2335 "__ppc_builtin_type_vec128", TYPE_CODE_UNION);
df4df182 2336 append_composite_type_field (t, "uint128", bt->builtin_uint128);
db9f5df8
UW		 2337 append_composite_type_field (t, "v2_double",
2338 init_vector_type (bt->builtin_double, 2));
604c2f83 2339 append_composite_type_field (t, "v4_float",
df4df182 2340 init_vector_type (bt->builtin_float, 4));
604c2f83 2341 append_composite_type_field (t, "v4_int32",
df4df182 2342 init_vector_type (bt->builtin_int32, 4));
604c2f83 2343 append_composite_type_field (t, "v8_int16",
df4df182 2344 init_vector_type (bt->builtin_int16, 8));
604c2f83 2345 append_composite_type_field (t, "v16_int8",
df4df182 2346 init_vector_type (bt->builtin_int8, 16));
604c2f83 2347
803e1097 2348 TYPE_VECTOR (t) = 1;
604c2f83
LM		 2349 TYPE_NAME (t) = "ppc_builtin_type_vec128";
2350 tdep->ppc_builtin_type_vec128 = t;
2351 }
2352
2353 return tdep->ppc_builtin_type_vec128;
2354}
2355
7cc46491
DJ		 2356/* Return the name of register number REGNO, or the empty string if it
2357 is an anonymous register. */
7a78ae4e 2358
fa88f677 2359static const char *
d93859e2 2360rs6000_register_name (struct gdbarch *gdbarch, int regno)
7a78ae4e 2361{
d93859e2 2362 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7a78ae4e 2363
7cc46491
DJ		 2364 /* The upper half "registers" have names in the XML description,
2365 but we present only the low GPRs and the full 64-bit registers
2366 to the user. */
2367 if (tdep->ppc_ev0_upper_regnum >= 0
2368 && tdep->ppc_ev0_upper_regnum <= regno
2369 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
2370 return "";
2371
604c2f83
LM		 2372 /* Hide the upper halves of the vs0~vs31 registers. */
2373 if (tdep->ppc_vsr0_regnum >= 0
2374 && tdep->ppc_vsr0_upper_regnum <= regno
2375 && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs)
2376 return "";
2377
7cc46491 2378 /* Check if the SPE pseudo registers are available. */
5a9e69ba 2379 if (IS_SPE_PSEUDOREG (tdep, regno))
7cc46491
DJ		 2380 {
2381 static const char *const spe_regnames[] = {
2382 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2383 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2384 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2385 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2386 };
2387 return spe_regnames[regno - tdep->ppc_ev0_regnum];
2388 }
2389
f949c649
TJB		 2390 /* Check if the decimal128 pseudo-registers are available. */
2391 if (IS_DFP_PSEUDOREG (tdep, regno))
2392 {
2393 static const char *const dfp128_regnames[] = {
2394 "dl0", "dl1", "dl2", "dl3",
2395 "dl4", "dl5", "dl6", "dl7",
2396 "dl8", "dl9", "dl10", "dl11",
2397 "dl12", "dl13", "dl14", "dl15"
2398 };
2399 return dfp128_regnames[regno - tdep->ppc_dl0_regnum];
2400 }
2401
604c2f83
LM		 2402 /* Check if this is a VSX pseudo-register. */
2403 if (IS_VSX_PSEUDOREG (tdep, regno))
2404 {
2405 static const char *const vsx_regnames[] = {
2406 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2407 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2408 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2409 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2410 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2411 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2412 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2413 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2414 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2415 };
2416 return vsx_regnames[regno - tdep->ppc_vsr0_regnum];
2417 }
2418
2419 /* Check if the this is a Extended FP pseudo-register. */
2420 if (IS_EFP_PSEUDOREG (tdep, regno))
2421 {
2422 static const char *const efpr_regnames[] = {
2423 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2424 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2425 "f46", "f47", "f48", "f49", "f50", "f51",
2426 "f52", "f53", "f54", "f55", "f56", "f57",
2427 "f58", "f59", "f60", "f61", "f62", "f63"
2428 };
2429 return efpr_regnames[regno - tdep->ppc_efpr0_regnum];
2430 }
2431
d93859e2 2432 return tdesc_register_name (gdbarch, regno);
7a78ae4e
ND		 2433}
2434
7cc46491
DJ		 2435/* Return the GDB type object for the "standard" data type of data in
2436 register N. */
7a78ae4e
ND		 2437
2438static struct type *
7cc46491 2439rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
7a78ae4e 2440{
691d145a 2441 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7a78ae4e 2442
7cc46491 2443 /* These are the only pseudo-registers we support. */
f949c649 2444 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
604c2f83
LM		 2445 || IS_DFP_PSEUDOREG (tdep, regnum)
2446 || IS_VSX_PSEUDOREG (tdep, regnum)
2447 || IS_EFP_PSEUDOREG (tdep, regnum));
7cc46491 2448
f949c649
TJB		 2449 /* These are the e500 pseudo-registers. */
2450 if (IS_SPE_PSEUDOREG (tdep, regnum))
2451 return rs6000_builtin_type_vec64 (gdbarch);
604c2f83
LM		 2452 else if (IS_DFP_PSEUDOREG (tdep, regnum))
2453 /* PPC decimal128 pseudo-registers. */
f949c649 2454 return builtin_type (gdbarch)->builtin_declong;
604c2f83
LM		 2455 else if (IS_VSX_PSEUDOREG (tdep, regnum))
2456 /* POWER7 VSX pseudo-registers. */
2457 return rs6000_builtin_type_vec128 (gdbarch);
2458 else
2459 /* POWER7 Extended FP pseudo-registers. */
2460 return builtin_type (gdbarch)->builtin_double;
7a78ae4e
ND		 2461}
2462
c44ca51c
AC		 2463/* Is REGNUM a member of REGGROUP? */
2464static int
7cc46491
DJ		 2465rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2466 struct reggroup *group)
c44ca51c
AC		 2467{
2468 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
c44ca51c 2469
7cc46491 2470 /* These are the only pseudo-registers we support. */
f949c649 2471 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
604c2f83
LM		 2472 || IS_DFP_PSEUDOREG (tdep, regnum)
2473 || IS_VSX_PSEUDOREG (tdep, regnum)
2474 || IS_EFP_PSEUDOREG (tdep, regnum));
c44ca51c 2475
604c2f83
LM		 2476 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2477 if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum))
f949c649 2478 return group == all_reggroup || group == vector_reggroup;
7cc46491 2479 else
604c2f83 2480 /* PPC decimal128 or Extended FP pseudo-registers. */
f949c649 2481 return group == all_reggroup || group == float_reggroup;
c44ca51c
AC		 2482}
2483
691d145a 2484/* The register format for RS/6000 floating point registers is always
64366f1c 2485 double, we need a conversion if the memory format is float. */
7a78ae4e
ND		 2486
2487static int
0abe36f5
MD		 2488rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum,
2489 struct type *type)
7a78ae4e 2490{
0abe36f5 2491 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7cc46491
DJ		 2492
2493 return (tdep->ppc_fp0_regnum >= 0
2494 && regnum >= tdep->ppc_fp0_regnum
2495 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs
2496 && TYPE_CODE (type) == TYPE_CODE_FLT
0dfff4cb
UW		 2497 && TYPE_LENGTH (type)
2498 != TYPE_LENGTH (builtin_type (gdbarch)->builtin_double));
7a78ae4e
ND		 2499}
2500
7a78ae4e 2501static void
691d145a
JB		 2502rs6000_register_to_value (struct frame_info *frame,
2503 int regnum,
2504 struct type *type,
50fd1280 2505 gdb_byte *to)
7a78ae4e 2506{
0dfff4cb 2507 struct gdbarch *gdbarch = get_frame_arch (frame);
50fd1280 2508 gdb_byte from[MAX_REGISTER_SIZE];
691d145a 2509
691d145a 2510 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
7a78ae4e 2511
691d145a 2512 get_frame_register (frame, regnum, from);
0dfff4cb
UW		 2513 convert_typed_floating (from, builtin_type (gdbarch)->builtin_double,
2514 to, type);
691d145a 2515}
7a292a7a 2516
7a78ae4e 2517static void
691d145a
JB		 2518rs6000_value_to_register (struct frame_info *frame,
2519 int regnum,
2520 struct type *type,
50fd1280 2521 const gdb_byte *from)
7a78ae4e 2522{
0dfff4cb 2523 struct gdbarch *gdbarch = get_frame_arch (frame);
50fd1280 2524 gdb_byte to[MAX_REGISTER_SIZE];
691d145a 2525
691d145a
JB		 2526 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2527
0dfff4cb
UW		 2528 convert_typed_floating (from, type,
2529 to, builtin_type (gdbarch)->builtin_double);
691d145a 2530 put_frame_register (frame, regnum, to);
7a78ae4e 2531}
c906108c 2532
6ced10dd
JB		 2533/* Move SPE vector register values between a 64-bit buffer and the two
2534 32-bit raw register halves in a regcache. This function handles
2535 both splitting a 64-bit value into two 32-bit halves, and joining
2536 two halves into a whole 64-bit value, depending on the function
2537 passed as the MOVE argument.
2538
2539 EV_REG must be the number of an SPE evN vector register --- a
2540 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2541 64-bit buffer.
2542
2543 Call MOVE once for each 32-bit half of that register, passing
2544 REGCACHE, the number of the raw register corresponding to that
2545 half, and the address of the appropriate half of BUFFER.
2546
2547 For example, passing 'regcache_raw_read' as the MOVE function will
2548 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2549 'regcache_raw_supply' will supply the contents of BUFFER to the
2550 appropriate pair of raw registers in REGCACHE.
2551
2552 You may need to cast away some 'const' qualifiers when passing
2553 MOVE, since this function can't tell at compile-time which of
2554 REGCACHE or BUFFER is acting as the source of the data. If C had
2555 co-variant type qualifiers, ... */
2556static void
2557e500_move_ev_register (void (*move) (struct regcache *regcache,
50fd1280 2558 int regnum, gdb_byte *buf),
6ced10dd 2559 struct regcache *regcache, int ev_reg,
50fd1280 2560 gdb_byte *buffer)
6ced10dd
JB		 2561{
2562 struct gdbarch *arch = get_regcache_arch (regcache);
2563 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2564 int reg_index;
50fd1280 2565 gdb_byte *byte_buffer = buffer;
6ced10dd 2566
5a9e69ba 2567 gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg));
6ced10dd
JB		 2568
2569 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2570
8b164abb 2571 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
6ced10dd
JB		 2572 {
2573 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
2574 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
2575 }
2576 else
2577 {
2578 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2579 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
2580 }
2581}
2582
c8001721
EZ		 2583static void
2584e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
50fd1280 2585 int reg_nr, gdb_byte *buffer)
f949c649
TJB		 2586{
2587 e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
2588}
2589
2590static void
2591e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2592 int reg_nr, const gdb_byte *buffer)
2593{
2594 e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *))
2595 regcache_raw_write,
2596 regcache, reg_nr, (gdb_byte *) buffer);
2597}
2598
604c2f83 2599/* Read method for DFP pseudo-registers. */
f949c649 2600static void
604c2f83 2601dfp_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
f949c649
TJB		 2602 int reg_nr, gdb_byte *buffer)
2603{
2604 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2605 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2606
2607 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2608 {
2609 /* Read two FP registers to form a whole dl register. */
2610 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2611 2 * reg_index, buffer);
2612 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2613 2 * reg_index + 1, buffer + 8);
2614 }
2615 else
2616 {
2617 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2618 2 * reg_index + 1, buffer + 8);
2619 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2620 2 * reg_index, buffer);
2621 }
2622}
2623
604c2f83 2624/* Write method for DFP pseudo-registers. */
f949c649 2625static void
604c2f83 2626dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
f949c649
TJB		 2627 int reg_nr, const gdb_byte *buffer)
2628{
2629 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2630 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2631
2632 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2633 {
2634 /* Write each half of the dl register into a separate
2635 FP register. */
2636 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2637 2 * reg_index, buffer);
2638 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2639 2 * reg_index + 1, buffer + 8);
2640 }
2641 else
2642 {
2643 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2644 2 * reg_index + 1, buffer + 8);
2645 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2646 2 * reg_index, buffer);
2647 }
2648}
2649
604c2f83
LM		 2650/* Read method for POWER7 VSX pseudo-registers. */
2651static void
2652vsx_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2653 int reg_nr, gdb_byte *buffer)
2654{
2655 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2656 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2657
2658 /* Read the portion that overlaps the VMX registers. */
2659 if (reg_index > 31)
2660 regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2661 reg_index - 32, buffer);
2662 else
2663 /* Read the portion that overlaps the FPR registers. */
2664 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2665 {
2666 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2667 reg_index, buffer);
2668 regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2669 reg_index, buffer + 8);
2670 }
2671 else
2672 {
2673 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2674 reg_index, buffer + 8);
2675 regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2676 reg_index, buffer);
2677 }
2678}
2679
2680/* Write method for POWER7 VSX pseudo-registers. */
2681static void
2682vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2683 int reg_nr, const gdb_byte *buffer)
2684{
2685 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2686 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2687
2688 /* Write the portion that overlaps the VMX registers. */
2689 if (reg_index > 31)
2690 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2691 reg_index - 32, buffer);
2692 else
2693 /* Write the portion that overlaps the FPR registers. */
2694 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2695 {
2696 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2697 reg_index, buffer);
2698 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2699 reg_index, buffer + 8);
2700 }
2701 else
2702 {
2703 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2704 reg_index, buffer + 8);
2705 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2706 reg_index, buffer);
2707 }
2708}
2709
2710/* Read method for POWER7 Extended FP pseudo-registers. */
2711static void
2712efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2713 int reg_nr, gdb_byte *buffer)
2714{
2715 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2716 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2717
2718 /* Read the portion that overlaps the VMX registers. */
2719 regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2720 reg_index, buffer);
2721}
2722
2723/* Write method for POWER7 Extended FP pseudo-registers. */
2724static void
2725efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2726 int reg_nr, const gdb_byte *buffer)
2727{
2728 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2729 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2730
2731 /* Write the portion that overlaps the VMX registers. */
2732 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2733 reg_index, buffer);
2734}
2735
f949c649
TJB		 2736static void
2737rs6000_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2738 int reg_nr, gdb_byte *buffer)
c8001721 2739{
6ced10dd 2740 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
c8001721
EZ		 2741 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2742
6ced10dd 2743 gdb_assert (regcache_arch == gdbarch);
f949c649 2744
5a9e69ba 2745 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
f949c649
TJB		 2746 e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2747 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
604c2f83
LM		 2748 dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2749 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2750 vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2751 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2752 efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
6ced10dd 2753 else
a44bddec 2754 internal_error (__FILE__, __LINE__,
f949c649
TJB		 2755 _("rs6000_pseudo_register_read: "
2756 "called on unexpected register '%s' (%d)"),
2757 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
c8001721
EZ		 2758}
2759
2760static void
f949c649
TJB		 2761rs6000_pseudo_register_write (struct gdbarch *gdbarch,
2762 struct regcache *regcache,
2763 int reg_nr, const gdb_byte *buffer)
c8001721 2764{
6ced10dd 2765 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
c8001721
EZ		 2766 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2767
6ced10dd 2768 gdb_assert (regcache_arch == gdbarch);
f949c649 2769
5a9e69ba 2770 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
f949c649
TJB		 2771 e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2772 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
604c2f83
LM		 2773 dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2774 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2775 vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2776 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2777 efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
6ced10dd 2778 else
a44bddec 2779 internal_error (__FILE__, __LINE__,
f949c649
TJB		 2780 _("rs6000_pseudo_register_write: "
2781 "called on unexpected register '%s' (%d)"),
2782 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
6ced10dd
JB		 2783}
2784
18ed0c4e 2785/* Convert a DBX STABS register number to a GDB register number. */
c8001721 2786static int
d3f73121 2787rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
c8001721 2788{
d3f73121 2789 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
c8001721 2790
9f744501
JB		 2791 if (0 <= num && num <= 31)
2792 return tdep->ppc_gp0_regnum + num;
2793 else if (32 <= num && num <= 63)
383f0f5b
JB		 2794 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2795 specifies registers the architecture doesn't have? Our
2796 callers don't check the value we return. */
366f009f 2797 return tdep->ppc_fp0_regnum + (num - 32);
18ed0c4e
JB		 2798 else if (77 <= num && num <= 108)
2799 return tdep->ppc_vr0_regnum + (num - 77);
9f744501
JB		 2800 else if (1200 <= num && num < 1200 + 32)
2801 return tdep->ppc_ev0_regnum + (num - 1200);
2802 else
2803 switch (num)
2804 {
2805 case 64:
2806 return tdep->ppc_mq_regnum;
2807 case 65:
2808 return tdep->ppc_lr_regnum;
2809 case 66:
2810 return tdep->ppc_ctr_regnum;
2811 case 76:
2812 return tdep->ppc_xer_regnum;
2813 case 109:
2814 return tdep->ppc_vrsave_regnum;
18ed0c4e
JB		 2815 case 110:
2816 return tdep->ppc_vrsave_regnum - 1; /* vscr */
867e2dc5 2817 case 111:
18ed0c4e 2818 return tdep->ppc_acc_regnum;
867e2dc5 2819 case 112:
18ed0c4e 2820 return tdep->ppc_spefscr_regnum;
9f744501
JB		 2821 default:
2822 return num;
2823 }
18ed0c4e 2824}
9f744501 2825
9f744501 2826
18ed0c4e
JB		 2827/* Convert a Dwarf 2 register number to a GDB register number. */
2828static int
d3f73121 2829rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
18ed0c4e 2830{
d3f73121 2831 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9f744501 2832
18ed0c4e
JB		 2833 if (0 <= num && num <= 31)
2834 return tdep->ppc_gp0_regnum + num;
2835 else if (32 <= num && num <= 63)
2836 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2837 specifies registers the architecture doesn't have? Our
2838 callers don't check the value we return. */
2839 return tdep->ppc_fp0_regnum + (num - 32);
2840 else if (1124 <= num && num < 1124 + 32)
2841 return tdep->ppc_vr0_regnum + (num - 1124);
2842 else if (1200 <= num && num < 1200 + 32)
2843 return tdep->ppc_ev0_regnum + (num - 1200);
2844 else
2845 switch (num)
2846 {
a489f789
AS		 2847 case 64:
2848 return tdep->ppc_cr_regnum;
18ed0c4e
JB		 2849 case 67:
2850 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2851 case 99:
2852 return tdep->ppc_acc_regnum;
2853 case 100:
2854 return tdep->ppc_mq_regnum;
2855 case 101:
2856 return tdep->ppc_xer_regnum;
2857 case 108:
2858 return tdep->ppc_lr_regnum;
2859 case 109:
2860 return tdep->ppc_ctr_regnum;
2861 case 356:
2862 return tdep->ppc_vrsave_regnum;
2863 case 612:
2864 return tdep->ppc_spefscr_regnum;
2865 default:
2866 return num;
2867 }
2188cbdd
EZ		 2868}
2869
4fc771b8
DJ		 2870/* Translate a .eh_frame register to DWARF register, or adjust a
2871 .debug_frame register. */
2872
2873static int
2874rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
2875{
2876 /* GCC releases before 3.4 use GCC internal register numbering in
2877 .debug_frame (and .debug_info, et cetera). The numbering is
2878 different from the standard SysV numbering for everything except
2879 for GPRs and FPRs. We can not detect this problem in most cases
2880 - to get accurate debug info for variables living in lr, ctr, v0,
2881 et cetera, use a newer version of GCC. But we must detect
2882 one important case - lr is in column 65 in .debug_frame output,
2883 instead of 108.
2884
2885 GCC 3.4, and the "hammer" branch, have a related problem. They
2886 record lr register saves in .debug_frame as 108, but still record
2887 the return column as 65. We fix that up too.
2888
2889 We can do this because 65 is assigned to fpsr, and GCC never
2890 generates debug info referring to it. To add support for
2891 handwritten debug info that restores fpsr, we would need to add a
2892 producer version check to this. */
2893 if (!eh_frame_p)
2894 {
2895 if (num == 65)
2896 return 108;
2897 else
2898 return num;
2899 }
2900
2901 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2902 internal register numbering; translate that to the standard DWARF2
2903 register numbering. */
2904 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */
2905 return num;
2906 else if (68 <= num && num <= 75) /* cr0-cr8 */
2907 return num - 68 + 86;
2908 else if (77 <= num && num <= 108) /* vr0-vr31 */
2909 return num - 77 + 1124;
2910 else
2911 switch (num)
2912 {
2913 case 64: /* mq */
2914 return 100;
2915 case 65: /* lr */
2916 return 108;
2917 case 66: /* ctr */
2918 return 109;
2919 case 76: /* xer */
2920 return 101;
2921 case 109: /* vrsave */
2922 return 356;
2923 case 110: /* vscr */
2924 return 67;
2925 case 111: /* spe_acc */
2926 return 99;
2927 case 112: /* spefscr */
2928 return 612;
2929 default:
2930 return num;
2931 }
2932}
c906108c 2933\f
c5aa993b 2934
7a78ae4e 2935/* Handling the various POWER/PowerPC variants. */
c906108c 2936
c906108c 2937/* Information about a particular processor variant. */
7a78ae4e 2938
c906108c 2939struct variant
c5aa993b
JM		 2940 {
2941 /* Name of this variant. */
2942 char *name;
c906108c 2943
c5aa993b
JM		 2944 /* English description of the variant. */
2945 char *description;
c906108c 2946
64366f1c 2947 /* bfd_arch_info.arch corresponding to variant. */
7a78ae4e
ND		 2948 enum bfd_architecture arch;
2949
64366f1c 2950 /* bfd_arch_info.mach corresponding to variant. */
7a78ae4e
ND		 2951 unsigned long mach;
2952
7cc46491
DJ		 2953 /* Target description for this variant. */
2954 struct target_desc **tdesc;
c5aa993b 2955 };
c906108c 2956
489461e2 2957static struct variant variants[] =
c906108c 2958{
7a78ae4e 2959 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
7284e1be 2960 bfd_mach_ppc, &tdesc_powerpc_altivec32},
7a78ae4e 2961 {"power", "POWER user-level", bfd_arch_rs6000,
7cc46491 2962 bfd_mach_rs6k, &tdesc_rs6000},
7a78ae4e 2963 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
7cc46491 2964 bfd_mach_ppc_403, &tdesc_powerpc_403},
4d09ffea
MS		 2965 {"405", "IBM PowerPC 405", bfd_arch_powerpc,
2966 bfd_mach_ppc_405, &tdesc_powerpc_405},
7a78ae4e 2967 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
7cc46491 2968 bfd_mach_ppc_601, &tdesc_powerpc_601},
7a78ae4e 2969 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
7cc46491 2970 bfd_mach_ppc_602, &tdesc_powerpc_602},
7a78ae4e 2971 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
7cc46491 2972 bfd_mach_ppc_603, &tdesc_powerpc_603},
7a78ae4e 2973 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
7cc46491 2974 604, &tdesc_powerpc_604},
7a78ae4e 2975 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
7cc46491 2976 bfd_mach_ppc_403gc, &tdesc_powerpc_403gc},
7a78ae4e 2977 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
7cc46491 2978 bfd_mach_ppc_505, &tdesc_powerpc_505},
7a78ae4e 2979 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
7cc46491 2980 bfd_mach_ppc_860, &tdesc_powerpc_860},
7a78ae4e 2981 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
7cc46491 2982 bfd_mach_ppc_750, &tdesc_powerpc_750},
1fcc0bb8 2983 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
7cc46491 2984 bfd_mach_ppc_7400, &tdesc_powerpc_7400},
c8001721 2985 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
7cc46491 2986 bfd_mach_ppc_e500, &tdesc_powerpc_e500},
7a78ae4e 2987
5d57ee30
KB		 2988 /* 64-bit */
2989 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
7284e1be 2990 bfd_mach_ppc64, &tdesc_powerpc_altivec64},
7a78ae4e 2991 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
7cc46491 2992 bfd_mach_ppc_620, &tdesc_powerpc_64},
5d57ee30 2993 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
7cc46491 2994 bfd_mach_ppc_630, &tdesc_powerpc_64},
7a78ae4e 2995 {"a35", "PowerPC A35", bfd_arch_powerpc,
7cc46491 2996 bfd_mach_ppc_a35, &tdesc_powerpc_64},
5d57ee30 2997 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
7cc46491 2998 bfd_mach_ppc_rs64ii, &tdesc_powerpc_64},
5d57ee30 2999 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
7cc46491 3000 bfd_mach_ppc_rs64iii, &tdesc_powerpc_64},
5d57ee30 3001
64366f1c 3002 /* FIXME: I haven't checked the register sets of the following. */
7a78ae4e 3003 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
7cc46491 3004 bfd_mach_rs6k_rs1, &tdesc_rs6000},
7a78ae4e 3005 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
7cc46491 3006 bfd_mach_rs6k_rsc, &tdesc_rs6000},
7a78ae4e 3007 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
7cc46491 3008 bfd_mach_rs6k_rs2, &tdesc_rs6000},
7a78ae4e 3009
7cc46491 3010 {0, 0, 0, 0, 0}
c906108c
SS		 3011};
3012
7a78ae4e 3013/* Return the variant corresponding to architecture ARCH and machine number
64366f1c 3014 MACH. If no such variant exists, return null. */
c906108c 3015
7a78ae4e
ND		 3016static const struct variant *
3017find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
c906108c 3018{
7a78ae4e 3019 const struct variant *v;
c5aa993b 3020
7a78ae4e
ND		 3021 for (v = variants; v->name; v++)
3022 if (arch == v->arch && mach == v->mach)
3023 return v;
c906108c 3024
7a78ae4e 3025 return NULL;
c906108c 3026}
9364a0ef
EZ		 3027
3028static int
3029gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
3030{
ee4f0f76 3031 if (!info->disassembler_options)
e52d5016
NF		 3032 {
3033 /* When debugging E500 binaries and disassembling code containing
3034 E500-specific (SPE) instructions, one sometimes sees AltiVec
3035 instructions instead. The opcode spaces for SPE instructions
3036 and AltiVec instructions overlap, and specifiying the "any" cpu
3037 looks for AltiVec instructions first. If we know we're
3038 debugging an E500 binary, however, we can specify the "e500x2"
3039 cpu and get much more sane disassembly output. */
3040 if (info->mach == bfd_mach_ppc_e500)
3041 info->disassembler_options = "e500x2";
3042 else
3043 info->disassembler_options = "any";
3044 }
ee4f0f76 3045
40887e1a 3046 if (info->endian == BFD_ENDIAN_BIG)
9364a0ef
EZ		 3047 return print_insn_big_powerpc (memaddr, info);
3048 else
3049 return print_insn_little_powerpc (memaddr, info);
3050}
7a78ae4e 3051\f
61a65099
KB		 3052static CORE_ADDR
3053rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
3054{
3e8c568d 3055 return frame_unwind_register_unsigned (next_frame,
8b164abb 3056 gdbarch_pc_regnum (gdbarch));
61a65099
KB		 3057}
3058
3059static struct frame_id
1af5d7ce 3060rs6000_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
61a65099 3061{
1af5d7ce
UW		 3062 return frame_id_build (get_frame_register_unsigned
3063 (this_frame, gdbarch_sp_regnum (gdbarch)),
3064 get_frame_pc (this_frame));
61a65099
KB		 3065}
3066
3067struct rs6000_frame_cache
3068{
3069 CORE_ADDR base;
3070 CORE_ADDR initial_sp;
3071 struct trad_frame_saved_reg *saved_regs;
3072};
3073
3074static struct rs6000_frame_cache *
1af5d7ce 3075rs6000_frame_cache (struct frame_info *this_frame, void **this_cache)
61a65099
KB		 3076{
3077 struct rs6000_frame_cache *cache;
1af5d7ce 3078 struct gdbarch *gdbarch = get_frame_arch (this_frame);
61a65099 3079 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 3080 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
61a65099
KB		 3081 struct rs6000_framedata fdata;
3082 int wordsize = tdep->wordsize;
e10b1c4c 3083 CORE_ADDR func, pc;
61a65099
KB		 3084
3085 if ((*this_cache) != NULL)
3086 return (*this_cache);
3087 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
3088 (*this_cache) = cache;
1af5d7ce 3089 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
61a65099 3090
1af5d7ce
UW		 3091 func = get_frame_func (this_frame);
3092 pc = get_frame_pc (this_frame);
be8626e0 3093 skip_prologue (gdbarch, func, pc, &fdata);
e10b1c4c
DJ		 3094
3095 /* Figure out the parent's stack pointer. */
3096
3097 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3098 address of the current frame. Things might be easier if the
3099 ->frame pointed to the outer-most address of the frame. In
3100 the mean time, the address of the prev frame is used as the
3101 base address of this frame. */
1af5d7ce
UW		 3102 cache->base = get_frame_register_unsigned
3103 (this_frame, gdbarch_sp_regnum (gdbarch));
e10b1c4c
DJ		 3104
3105 /* If the function appears to be frameless, check a couple of likely
3106 indicators that we have simply failed to find the frame setup.
3107 Two common cases of this are missing symbols (i.e.
ef02daa9 3108 get_frame_func returns the wrong address or 0), and assembly
e10b1c4c
DJ		 3109 stubs which have a fast exit path but set up a frame on the slow
3110 path.
3111
3112 If the LR appears to return to this function, then presume that
3113 we have an ABI compliant frame that we failed to find. */
3114 if (fdata.frameless && fdata.lr_offset == 0)
61a65099 3115 {
e10b1c4c
DJ		 3116 CORE_ADDR saved_lr;
3117 int make_frame = 0;
3118
1af5d7ce 3119 saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum);
e10b1c4c
DJ		 3120 if (func == 0 && saved_lr == pc)
3121 make_frame = 1;
3122 else if (func != 0)
3123 {
3124 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
3125 if (func == saved_func)
3126 make_frame = 1;
3127 }
3128
3129 if (make_frame)
3130 {
3131 fdata.frameless = 0;
de6a76fd 3132 fdata.lr_offset = tdep->lr_frame_offset;
e10b1c4c 3133 }
61a65099 3134 }
e10b1c4c
DJ		 3135
3136 if (!fdata.frameless)
3137 /* Frameless really means stackless. */
e17a4113
UW		 3138 cache->base
3139 = read_memory_unsigned_integer (cache->base, wordsize, byte_order);
e10b1c4c 3140
3e8c568d 3141 trad_frame_set_value (cache->saved_regs,
8b164abb 3142 gdbarch_sp_regnum (gdbarch), cache->base);
61a65099
KB		 3143
3144 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3145 All fpr's from saved_fpr to fp31 are saved. */
3146
3147 if (fdata.saved_fpr >= 0)
3148 {
3149 int i;
3150 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
383f0f5b
JB		 3151
3152 /* If skip_prologue says floating-point registers were saved,
3153 but the current architecture has no floating-point registers,
3154 then that's strange. But we have no indices to even record
3155 the addresses under, so we just ignore it. */
3156 if (ppc_floating_point_unit_p (gdbarch))
063715bf 3157 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
383f0f5b
JB		 3158 {
3159 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3160 fpr_addr += 8;
3161 }
61a65099
KB		 3162 }
3163
3164 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
46a9b8ed
DJ		 3165 All gpr's from saved_gpr to gpr31 are saved (except during the
3166 prologue). */
61a65099
KB		 3167
3168 if (fdata.saved_gpr >= 0)
3169 {
3170 int i;
3171 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
063715bf 3172 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
61a65099 3173 {
46a9b8ed
DJ		 3174 if (fdata.gpr_mask & (1U << i))
3175 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
61a65099
KB		 3176 gpr_addr += wordsize;
3177 }
3178 }
3179
3180 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3181 All vr's from saved_vr to vr31 are saved. */
3182 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3183 {
3184 if (fdata.saved_vr >= 0)
3185 {
3186 int i;
3187 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3188 for (i = fdata.saved_vr; i < 32; i++)
3189 {
3190 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3191 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3192 }
3193 }
3194 }
3195
3196 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3197 All vr's from saved_ev to ev31 are saved. ????? */
5a9e69ba 3198 if (tdep->ppc_ev0_regnum != -1)
61a65099
KB		 3199 {
3200 if (fdata.saved_ev >= 0)
3201 {
3202 int i;
3203 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
063715bf 3204 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
61a65099
KB		 3205 {
3206 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3207 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
3208 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3209 }
3210 }
3211 }
3212
3213 /* If != 0, fdata.cr_offset is the offset from the frame that
3214 holds the CR. */
3215 if (fdata.cr_offset != 0)
3216 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
3217
3218 /* If != 0, fdata.lr_offset is the offset from the frame that
3219 holds the LR. */
3220 if (fdata.lr_offset != 0)
3221 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
46a9b8ed
DJ		 3222 else if (fdata.lr_register != -1)
3223 cache->saved_regs[tdep->ppc_lr_regnum].realreg = fdata.lr_register;
61a65099 3224 /* The PC is found in the link register. */
8b164abb 3225 cache->saved_regs[gdbarch_pc_regnum (gdbarch)] =
3e8c568d 3226 cache->saved_regs[tdep->ppc_lr_regnum];
61a65099
KB		 3227
3228 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3229 holds the VRSAVE. */
3230 if (fdata.vrsave_offset != 0)
3231 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
3232
3233 if (fdata.alloca_reg < 0)
3234 /* If no alloca register used, then fi->frame is the value of the
3235 %sp for this frame, and it is good enough. */
1af5d7ce
UW		 3236 cache->initial_sp
3237 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
61a65099 3238 else
1af5d7ce
UW		 3239 cache->initial_sp
3240 = get_frame_register_unsigned (this_frame, fdata.alloca_reg);
61a65099
KB		 3241
3242 return cache;
3243}
3244
3245static void
1af5d7ce 3246rs6000_frame_this_id (struct frame_info *this_frame, void **this_cache,
61a65099
KB		 3247 struct frame_id *this_id)
3248{
1af5d7ce 3249 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099 3250 this_cache);
5b197912
UW		 3251 /* This marks the outermost frame. */
3252 if (info->base == 0)
3253 return;
3254
1af5d7ce 3255 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
61a65099
KB		 3256}
3257
1af5d7ce
UW		 3258static struct value *
3259rs6000_frame_prev_register (struct frame_info *this_frame,
3260 void **this_cache, int regnum)
61a65099 3261{
1af5d7ce 3262 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099 3263 this_cache);
1af5d7ce 3264 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
61a65099
KB		 3265}
3266
3267static const struct frame_unwind rs6000_frame_unwind =
3268{
3269 NORMAL_FRAME,
3270 rs6000_frame_this_id,
1af5d7ce
UW		 3271 rs6000_frame_prev_register,
3272 NULL,
3273 default_frame_sniffer
61a65099 3274};
61a65099
KB		 3275\f
3276
3277static CORE_ADDR
1af5d7ce 3278rs6000_frame_base_address (struct frame_info *this_frame, void **this_cache)
61a65099 3279{
1af5d7ce 3280 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099
KB		 3281 this_cache);
3282 return info->initial_sp;
3283}
3284
3285static const struct frame_base rs6000_frame_base = {
3286 &rs6000_frame_unwind,
3287 rs6000_frame_base_address,
3288 rs6000_frame_base_address,
3289 rs6000_frame_base_address
3290};
3291
3292static const struct frame_base *
1af5d7ce 3293rs6000_frame_base_sniffer (struct frame_info *this_frame)
61a65099
KB		 3294{
3295 return &rs6000_frame_base;
3296}
3297
9274a07c
LM		 3298/* DWARF-2 frame support. Used to handle the detection of
3299 clobbered registers during function calls. */
3300
3301static void
3302ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3303 struct dwarf2_frame_state_reg *reg,
4a4e5149 3304 struct frame_info *this_frame)
9274a07c
LM		 3305{
3306 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3307
3308 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3309 non-volatile registers. We will use the same code for both. */
3310
3311 /* Call-saved GP registers. */
3312 if ((regnum >= tdep->ppc_gp0_regnum + 14
3313 && regnum <= tdep->ppc_gp0_regnum + 31)
3314 || (regnum == tdep->ppc_gp0_regnum + 1))
3315 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3316
3317 /* Call-clobbered GP registers. */
3318 if ((regnum >= tdep->ppc_gp0_regnum + 3
3319 && regnum <= tdep->ppc_gp0_regnum + 12)
3320 || (regnum == tdep->ppc_gp0_regnum))
3321 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3322
3323 /* Deal with FP registers, if supported. */
3324 if (tdep->ppc_fp0_regnum >= 0)
3325 {
3326 /* Call-saved FP registers. */
3327 if ((regnum >= tdep->ppc_fp0_regnum + 14
3328 && regnum <= tdep->ppc_fp0_regnum + 31))
3329 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3330
3331 /* Call-clobbered FP registers. */
3332 if ((regnum >= tdep->ppc_fp0_regnum
3333 && regnum <= tdep->ppc_fp0_regnum + 13))
3334 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3335 }
3336
3337 /* Deal with ALTIVEC registers, if supported. */
3338 if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0)
3339 {
3340 /* Call-saved Altivec registers. */
3341 if ((regnum >= tdep->ppc_vr0_regnum + 20
3342 && regnum <= tdep->ppc_vr0_regnum + 31)
3343 || regnum == tdep->ppc_vrsave_regnum)
3344 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3345
3346 /* Call-clobbered Altivec registers. */
3347 if ((regnum >= tdep->ppc_vr0_regnum
3348 && regnum <= tdep->ppc_vr0_regnum + 19))
3349 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3350 }
3351
3352 /* Handle PC register and Stack Pointer correctly. */
40a6adc1 3353 if (regnum == gdbarch_pc_regnum (gdbarch))
9274a07c 3354 reg->how = DWARF2_FRAME_REG_RA;
40a6adc1 3355 else if (regnum == gdbarch_sp_regnum (gdbarch))
9274a07c
LM		 3356 reg->how = DWARF2_FRAME_REG_CFA;
3357}
3358
3359
74af9197
NF		 3360/* Return true if a .gnu_attributes section exists in BFD and it
3361 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3362 section exists in BFD and it indicates that SPE extensions are in
3363 use. Check the .gnu.attributes section first, as the binary might be
3364 compiled for SPE, but not actually using SPE instructions. */
3365
3366static int
3367bfd_uses_spe_extensions (bfd *abfd)
3368{
3369 asection *sect;
3370 gdb_byte *contents = NULL;
3371 bfd_size_type size;
3372 gdb_byte *ptr;
3373 int success = 0;
3374 int vector_abi;
3375
3376 if (!abfd)
3377 return 0;
3378
3379 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3380 could be using the SPE vector abi without actually using any spe
3381 bits whatsoever. But it's close enough for now. */
3382 vector_abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_GNU,
3383 Tag_GNU_Power_ABI_Vector);
3384 if (vector_abi == 3)
3385 return 1;
3386
3387 sect = bfd_get_section_by_name (abfd, ".PPC.EMB.apuinfo");
3388 if (!sect)
3389 return 0;
3390
3391 size = bfd_get_section_size (sect);
3392 contents = xmalloc (size);
3393 if (!bfd_get_section_contents (abfd, sect, contents, 0, size))
3394 {
3395 xfree (contents);
3396 return 0;
3397 }
3398
3399 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3400
3401 struct {
3402 uint32 name_len;
3403 uint32 data_len;
3404 uint32 type;
3405 char name[name_len rounded up to 4-byte alignment];
3406 char data[data_len];
3407 };
3408
3409 Technically, there's only supposed to be one such structure in a
3410 given apuinfo section, but the linker is not always vigilant about
3411 merging apuinfo sections from input files. Just go ahead and parse
3412 them all, exiting early when we discover the binary uses SPE
3413 insns.
3414
3415 It's not specified in what endianness the information in this
3416 section is stored. Assume that it's the endianness of the BFD. */
3417 ptr = contents;
3418 while (1)
3419 {
3420 unsigned int name_len;
3421 unsigned int data_len;
3422 unsigned int type;
3423
3424 /* If we can't read the first three fields, we're done. */
3425 if (size < 12)
3426 break;
3427
3428 name_len = bfd_get_32 (abfd, ptr);
3429 name_len = (name_len + 3) & ~3U; /* Round to 4 bytes. */
3430 data_len = bfd_get_32 (abfd, ptr + 4);
3431 type = bfd_get_32 (abfd, ptr + 8);
3432 ptr += 12;
3433
3434 /* The name must be "APUinfo\0". */
3435 if (name_len != 8
3436 && strcmp ((const char *) ptr, "APUinfo") != 0)
3437 break;
3438 ptr += name_len;
3439
3440 /* The type must be 2. */
3441 if (type != 2)
3442 break;
3443
3444 /* The data is stored as a series of uint32. The upper half of
3445 each uint32 indicates the particular APU used and the lower
3446 half indicates the revision of that APU. We just care about
3447 the upper half. */
3448
3449 /* Not 4-byte quantities. */
3450 if (data_len & 3U)
3451 break;
3452
3453 while (data_len)
3454 {
3455 unsigned int apuinfo = bfd_get_32 (abfd, ptr);
3456 unsigned int apu = apuinfo >> 16;
3457 ptr += 4;
3458 data_len -= 4;
3459
3460 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3461 either. */
3462 if (apu == 0x100 || apu == 0x101)
3463 {
3464 success = 1;
3465 data_len = 0;
3466 }
3467 }
3468
3469 if (success)
3470 break;
3471 }
3472
3473 xfree (contents);
3474 return success;
3475}
3476
7a78ae4e
ND		 3477/* Initialize the current architecture based on INFO. If possible, re-use an
3478 architecture from ARCHES, which is a list of architectures already created
3479 during this debugging session.
c906108c 3480
7a78ae4e 3481 Called e.g. at program startup, when reading a core file, and when reading
64366f1c 3482 a binary file. */
c906108c 3483
7a78ae4e
ND		 3484static struct gdbarch *
3485rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3486{
3487 struct gdbarch *gdbarch;
3488 struct gdbarch_tdep *tdep;
7cc46491 3489 int wordsize, from_xcoff_exec, from_elf_exec;
7a78ae4e
ND		 3490 enum bfd_architecture arch;
3491 unsigned long mach;
3492 bfd abfd;
5bf1c677 3493 asection *sect;
55eddb0f
DJ		 3494 enum auto_boolean soft_float_flag = powerpc_soft_float_global;
3495 int soft_float;
3496 enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
604c2f83
LM		 3497 int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0,
3498 have_vsx = 0;
7cc46491
DJ		 3499 int tdesc_wordsize = -1;
3500 const struct target_desc *tdesc = info.target_desc;
3501 struct tdesc_arch_data *tdesc_data = NULL;
f949c649 3502 int num_pseudoregs = 0;
604c2f83 3503 int cur_reg;
7a78ae4e 3504
f4d9bade
UW		 3505 /* INFO may refer to a binary that is not of the PowerPC architecture,
3506 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
3507 In this case, we must not attempt to infer properties of the (PowerPC
3508 side) of the target system from properties of that executable. Trust
3509 the target description instead. */
3510 if (info.abfd
3511 && bfd_get_arch (info.abfd) != bfd_arch_powerpc
3512 && bfd_get_arch (info.abfd) != bfd_arch_rs6000)
3513 info.abfd = NULL;
3514
9aa1e687 3515 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
7a78ae4e
ND		 3516 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3517
9aa1e687
KB		 3518 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3519 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3520
e712c1cf 3521 /* Check word size. If INFO is from a binary file, infer it from
64366f1c 3522 that, else choose a likely default. */
9aa1e687 3523 if (from_xcoff_exec)
c906108c 3524 {
11ed25ac 3525 if (bfd_xcoff_is_xcoff64 (info.abfd))
7a78ae4e
ND		 3526 wordsize = 8;
3527 else
3528 wordsize = 4;
c906108c 3529 }
9aa1e687
KB		 3530 else if (from_elf_exec)
3531 {
3532 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3533 wordsize = 8;
3534 else
3535 wordsize = 4;
3536 }
7cc46491
DJ		 3537 else if (tdesc_has_registers (tdesc))
3538 wordsize = -1;
c906108c 3539 else
7a78ae4e 3540 {
27b15785
KB		 3541 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3542 wordsize = info.bfd_arch_info->bits_per_word /
3543 info.bfd_arch_info->bits_per_byte;
3544 else
3545 wordsize = 4;
7a78ae4e 3546 }
c906108c 3547
475bbd17
JB		 3548 /* Get the architecture and machine from the BFD. */
3549 arch = info.bfd_arch_info->arch;
3550 mach = info.bfd_arch_info->mach;
5bf1c677
EZ		 3551
3552 /* For e500 executables, the apuinfo section is of help here. Such
3553 section contains the identifier and revision number of each
3554 Application-specific Processing Unit that is present on the
3555 chip. The content of the section is determined by the assembler
3556 which looks at each instruction and determines which unit (and
74af9197
NF		 3557 which version of it) can execute it. Grovel through the section
3558 looking for relevant e500 APUs. */
5bf1c677 3559
74af9197 3560 if (bfd_uses_spe_extensions (info.abfd))
5bf1c677 3561 {
74af9197
NF		 3562 arch = info.bfd_arch_info->arch;
3563 mach = bfd_mach_ppc_e500;
3564 bfd_default_set_arch_mach (&abfd, arch, mach);
3565 info.bfd_arch_info = bfd_get_arch_info (&abfd);
5bf1c677
EZ		 3566 }
3567
7cc46491
DJ		 3568 /* Find a default target description which describes our register
3569 layout, if we do not already have one. */
3570 if (! tdesc_has_registers (tdesc))
3571 {
3572 const struct variant *v;
3573
3574 /* Choose variant. */
3575 v = find_variant_by_arch (arch, mach);
3576 if (!v)
3577 return NULL;
3578
3579 tdesc = *v->tdesc;
3580 }
3581
3582 gdb_assert (tdesc_has_registers (tdesc));
3583
3584 /* Check any target description for validity. */
3585 if (tdesc_has_registers (tdesc))
3586 {
3587 static const char *const gprs[] = {
3588 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3589 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3590 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3591 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3592 };
3593 static const char *const segment_regs[] = {
3594 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
3595 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
3596 };
3597 const struct tdesc_feature *feature;
3598 int i, valid_p;
3599 static const char *const msr_names[] = { "msr", "ps" };
3600 static const char *const cr_names[] = { "cr", "cnd" };
3601 static const char *const ctr_names[] = { "ctr", "cnt" };
3602
3603 feature = tdesc_find_feature (tdesc,
3604 "org.gnu.gdb.power.core");
3605 if (feature == NULL)
3606 return NULL;
3607
3608 tdesc_data = tdesc_data_alloc ();
3609
3610 valid_p = 1;
3611 for (i = 0; i < ppc_num_gprs; i++)
3612 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]);
3613 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM,
3614 "pc");
3615 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM,
3616 "lr");
3617 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM,
3618 "xer");
3619
3620 /* Allow alternate names for these registers, to accomodate GDB's
3621 historic naming. */
3622 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3623 PPC_MSR_REGNUM, msr_names);
3624 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3625 PPC_CR_REGNUM, cr_names);
3626 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3627 PPC_CTR_REGNUM, ctr_names);
3628
3629 if (!valid_p)
3630 {
3631 tdesc_data_cleanup (tdesc_data);
3632 return NULL;
3633 }
3634
3635 have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM,
3636 "mq");
3637
3638 tdesc_wordsize = tdesc_register_size (feature, "pc") / 8;
3639 if (wordsize == -1)
3640 wordsize = tdesc_wordsize;
3641
3642 feature = tdesc_find_feature (tdesc,
3643 "org.gnu.gdb.power.fpu");
3644 if (feature != NULL)
3645 {
3646 static const char *const fprs[] = {
3647 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
3648 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
3649 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
3650 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
3651 };
3652 valid_p = 1;
3653 for (i = 0; i < ppc_num_fprs; i++)
3654 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3655 PPC_F0_REGNUM + i, fprs[i]);
3656 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3657 PPC_FPSCR_REGNUM, "fpscr");
3658
3659 if (!valid_p)
3660 {
3661 tdesc_data_cleanup (tdesc_data);
3662 return NULL;
3663 }
3664 have_fpu = 1;
3665 }
3666 else
3667 have_fpu = 0;
3668
f949c649
TJB		 3669 /* The DFP pseudo-registers will be available when there are floating
3670 point registers. */
3671 have_dfp = have_fpu;
3672
7cc46491
DJ		 3673 feature = tdesc_find_feature (tdesc,
3674 "org.gnu.gdb.power.altivec");
3675 if (feature != NULL)
3676 {
3677 static const char *const vector_regs[] = {
3678 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
3679 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
3680 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
3681 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
3682 };
3683
3684 valid_p = 1;
3685 for (i = 0; i < ppc_num_gprs; i++)
3686 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3687 PPC_VR0_REGNUM + i,
3688 vector_regs[i]);
3689 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3690 PPC_VSCR_REGNUM, "vscr");
3691 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3692 PPC_VRSAVE_REGNUM, "vrsave");
3693
3694 if (have_spe || !valid_p)
3695 {
3696 tdesc_data_cleanup (tdesc_data);
3697 return NULL;
3698 }
3699 have_altivec = 1;
3700 }
3701 else
3702 have_altivec = 0;
3703
604c2f83
LM		 3704 /* Check for POWER7 VSX registers support. */
3705 feature = tdesc_find_feature (tdesc,
3706 "org.gnu.gdb.power.vsx");
3707
3708 if (feature != NULL)
3709 {
3710 static const char *const vsx_regs[] = {
3711 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
3712 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
3713 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
3714 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
3715 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
3716 "vs30h", "vs31h"
3717 };
3718
3719 valid_p = 1;
3720
3721 for (i = 0; i < ppc_num_vshrs; i++)
3722 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3723 PPC_VSR0_UPPER_REGNUM + i,
3724 vsx_regs[i]);
3725 if (!valid_p)
3726 {
3727 tdesc_data_cleanup (tdesc_data);
3728 return NULL;
3729 }
3730
3731 have_vsx = 1;
3732 }
3733 else
3734 have_vsx = 0;
3735
7cc46491
DJ		 3736 /* On machines supporting the SPE APU, the general-purpose registers
3737 are 64 bits long. There are SIMD vector instructions to treat them
3738 as pairs of floats, but the rest of the instruction set treats them
3739 as 32-bit registers, and only operates on their lower halves.
3740
3741 In the GDB regcache, we treat their high and low halves as separate
3742 registers. The low halves we present as the general-purpose
3743 registers, and then we have pseudo-registers that stitch together
3744 the upper and lower halves and present them as pseudo-registers.
3745
3746 Thus, the target description is expected to supply the upper
3747 halves separately. */
3748
3749 feature = tdesc_find_feature (tdesc,
3750 "org.gnu.gdb.power.spe");
3751 if (feature != NULL)
3752 {
3753 static const char *const upper_spe[] = {
3754 "ev0h", "ev1h", "ev2h", "ev3h",
3755 "ev4h", "ev5h", "ev6h", "ev7h",
3756 "ev8h", "ev9h", "ev10h", "ev11h",
3757 "ev12h", "ev13h", "ev14h", "ev15h",
3758 "ev16h", "ev17h", "ev18h", "ev19h",
3759 "ev20h", "ev21h", "ev22h", "ev23h",
3760 "ev24h", "ev25h", "ev26h", "ev27h",
3761 "ev28h", "ev29h", "ev30h", "ev31h"
3762 };
3763
3764 valid_p = 1;
3765 for (i = 0; i < ppc_num_gprs; i++)
3766 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3767 PPC_SPE_UPPER_GP0_REGNUM + i,
3768 upper_spe[i]);
3769 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3770 PPC_SPE_ACC_REGNUM, "acc");
3771 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3772 PPC_SPE_FSCR_REGNUM, "spefscr");
3773
3774 if (have_mq || have_fpu || !valid_p)
3775 {
3776 tdesc_data_cleanup (tdesc_data);
3777 return NULL;
3778 }
3779 have_spe = 1;
3780 }
3781 else
3782 have_spe = 0;
3783 }
3784
3785 /* If we have a 64-bit binary on a 32-bit target, complain. Also
3786 complain for a 32-bit binary on a 64-bit target; we do not yet
3787 support that. For instance, the 32-bit ABI routines expect
3788 32-bit GPRs.
3789
3790 As long as there isn't an explicit target description, we'll
3791 choose one based on the BFD architecture and get a word size
3792 matching the binary (probably powerpc:common or
3793 powerpc:common64). So there is only trouble if a 64-bit target
3794 supplies a 64-bit description while debugging a 32-bit
3795 binary. */
3796 if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize)
3797 {
3798 tdesc_data_cleanup (tdesc_data);
3799 return NULL;
3800 }
3801
55eddb0f
DJ		 3802#ifdef HAVE_ELF
3803 if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec)
3804 {
3805 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3806 Tag_GNU_Power_ABI_FP))
3807 {
3808 case 1:
3809 soft_float_flag = AUTO_BOOLEAN_FALSE;
3810 break;
3811 case 2:
3812 soft_float_flag = AUTO_BOOLEAN_TRUE;
3813 break;
3814 default:
3815 break;
3816 }
3817 }
3818
3819 if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec)
3820 {
3821 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3822 Tag_GNU_Power_ABI_Vector))
3823 {
3824 case 1:
3825 vector_abi = POWERPC_VEC_GENERIC;
3826 break;
3827 case 2:
3828 vector_abi = POWERPC_VEC_ALTIVEC;
3829 break;
3830 case 3:
3831 vector_abi = POWERPC_VEC_SPE;
3832 break;
3833 default:
3834 break;
3835 }
3836 }
3837#endif
3838
3839 if (soft_float_flag == AUTO_BOOLEAN_TRUE)
3840 soft_float = 1;
3841 else if (soft_float_flag == AUTO_BOOLEAN_FALSE)
3842 soft_float = 0;
3843 else
3844 soft_float = !have_fpu;
3845
3846 /* If we have a hard float binary or setting but no floating point
3847 registers, downgrade to soft float anyway. We're still somewhat
3848 useful in this scenario. */
3849 if (!soft_float && !have_fpu)
3850 soft_float = 1;
3851
3852 /* Similarly for vector registers. */
3853 if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec)
3854 vector_abi = POWERPC_VEC_GENERIC;
3855
3856 if (vector_abi == POWERPC_VEC_SPE && !have_spe)
3857 vector_abi = POWERPC_VEC_GENERIC;
3858
3859 if (vector_abi == POWERPC_VEC_AUTO)
3860 {
3861 if (have_altivec)
3862 vector_abi = POWERPC_VEC_ALTIVEC;
3863 else if (have_spe)
3864 vector_abi = POWERPC_VEC_SPE;
3865 else
3866 vector_abi = POWERPC_VEC_GENERIC;
3867 }
3868
3869 /* Do not limit the vector ABI based on available hardware, since we
3870 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
3871
7cc46491
DJ		 3872 /* Find a candidate among extant architectures. */
3873 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3874 arches != NULL;
3875 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3876 {
3877 /* Word size in the various PowerPC bfd_arch_info structs isn't
3878 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3879 separate word size check. */
3880 tdep = gdbarch_tdep (arches->gdbarch);
55eddb0f
DJ		 3881 if (tdep && tdep->soft_float != soft_float)
3882 continue;
3883 if (tdep && tdep->vector_abi != vector_abi)
3884 continue;
7cc46491
DJ		 3885 if (tdep && tdep->wordsize == wordsize)
3886 {
3887 if (tdesc_data != NULL)
3888 tdesc_data_cleanup (tdesc_data);
3889 return arches->gdbarch;
3890 }
3891 }
3892
3893 /* None found, create a new architecture from INFO, whose bfd_arch_info
3894 validity depends on the source:
3895 - executable useless
3896 - rs6000_host_arch() good
3897 - core file good
3898 - "set arch" trust blindly
3899 - GDB startup useless but harmless */
3900
3901 tdep = XCALLOC (1, struct gdbarch_tdep);
3902 tdep->wordsize = wordsize;
55eddb0f
DJ		 3903 tdep->soft_float = soft_float;
3904 tdep->vector_abi = vector_abi;
7cc46491 3905
7a78ae4e 3906 gdbarch = gdbarch_alloc (&info, tdep);
7a78ae4e 3907
7cc46491
DJ		 3908 tdep->ppc_gp0_regnum = PPC_R0_REGNUM;
3909 tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2;
3910 tdep->ppc_ps_regnum = PPC_MSR_REGNUM;
3911 tdep->ppc_cr_regnum = PPC_CR_REGNUM;
3912 tdep->ppc_lr_regnum = PPC_LR_REGNUM;
3913 tdep->ppc_ctr_regnum = PPC_CTR_REGNUM;
3914 tdep->ppc_xer_regnum = PPC_XER_REGNUM;
3915 tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1;
3916
3917 tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1;
3918 tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1;
604c2f83 3919 tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1;
7cc46491
DJ		 3920 tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1;
3921 tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1;
3922 tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1;
3923 tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1;
3924 tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
3925
3926 set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
3927 set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3928 set_gdbarch_deprecated_fp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3929 set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum);
9f643768 3930 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
7cc46491
DJ		 3931
3932 /* The XML specification for PowerPC sensibly calls the MSR "msr".
3933 GDB traditionally called it "ps", though, so let GDB add an
3934 alias. */
3935 set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum);
3936
4a7622d1 3937 if (wordsize == 8)
05580c65 3938 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
afd48b75 3939 else
4a7622d1 3940 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
c8001721 3941
baffbae0
JB		 3942 /* Set lr_frame_offset. */
3943 if (wordsize == 8)
3944 tdep->lr_frame_offset = 16;
baffbae0 3945 else
4a7622d1 3946 tdep->lr_frame_offset = 4;
baffbae0 3947
604c2f83 3948 if (have_spe || have_dfp || have_vsx)
7cc46491 3949 {
f949c649
TJB		 3950 set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read);
3951 set_gdbarch_pseudo_register_write (gdbarch, rs6000_pseudo_register_write);
7cc46491 3952 }
1fcc0bb8 3953
e0d24f8d
WZ		 3954 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3955
56a6dfb9 3956 /* Select instruction printer. */
708ff411 3957 if (arch == bfd_arch_rs6000)
9364a0ef 3958 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
56a6dfb9 3959 else
9364a0ef 3960 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
7495d1dc 3961
5a9e69ba 3962 set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS);
f949c649
TJB		 3963
3964 if (have_spe)
3965 num_pseudoregs += 32;
3966 if (have_dfp)
3967 num_pseudoregs += 16;
604c2f83
LM		 3968 if (have_vsx)
3969 /* Include both VSX and Extended FP registers. */
3970 num_pseudoregs += 96;
f949c649
TJB		 3971
3972 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs);
7a78ae4e
ND		 3973
3974 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3975 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3976 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3977 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3978 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3979 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3980 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4a7622d1 3981 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
4e409299 3982 set_gdbarch_char_signed (gdbarch, 0);
7a78ae4e 3983
11269d7e 3984 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
4a7622d1 3985 if (wordsize == 8)
8b148df9
AC		 3986 /* PPC64 SYSV. */
3987 set_gdbarch_frame_red_zone_size (gdbarch, 288);
7a78ae4e 3988
691d145a
JB		 3989 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
3990 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
3991 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
3992
18ed0c4e
JB		 3993 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
3994 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
d217aaed 3995
4a7622d1 3996 if (wordsize == 4)
77b2b6d4 3997 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
4a7622d1 3998 else if (wordsize == 8)
8be9034a 3999 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
7a78ae4e 4000
7a78ae4e 4001 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
0d1243d9 4002 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
8ab3d180 4003 set_gdbarch_skip_main_prologue (gdbarch, rs6000_skip_main_prologue);
0d1243d9 4004
7a78ae4e 4005 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
7a78ae4e
ND		 4006 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
4007
203c3895
UW		 4008 /* The value of symbols of type N_SO and N_FUN maybe null when
4009 it shouldn't be. */
4010 set_gdbarch_sofun_address_maybe_missing (gdbarch, 1);
4011
ce5eab59 4012 /* Handles single stepping of atomic sequences. */
4a7622d1 4013 set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence);
ce5eab59 4014
7a78ae4e
ND		 4015 /* Not sure on this. FIXMEmgo */
4016 set_gdbarch_frame_args_skip (gdbarch, 8);
4017
143985b7
AF		 4018 /* Helpers for function argument information. */
4019 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
4020
6f7f3f0d
UW		 4021 /* Trampoline. */
4022 set_gdbarch_in_solib_return_trampoline
4023 (gdbarch, rs6000_in_solib_return_trampoline);
4024 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code);
4025
4fc771b8 4026 /* Hook in the DWARF CFI frame unwinder. */
1af5d7ce 4027 dwarf2_append_unwinders (gdbarch);
4fc771b8
DJ		 4028 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum);
4029
9274a07c
LM		 4030 /* Frame handling. */
4031 dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg);
4032
2454a024
UW		 4033 /* Setup displaced stepping. */
4034 set_gdbarch_displaced_step_copy_insn (gdbarch,
4035 simple_displaced_step_copy_insn);
99e40580
UW		 4036 set_gdbarch_displaced_step_hw_singlestep (gdbarch,
4037 ppc_displaced_step_hw_singlestep);
2454a024
UW		 4038 set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup);
4039 set_gdbarch_displaced_step_free_closure (gdbarch,
4040 simple_displaced_step_free_closure);
4041 set_gdbarch_displaced_step_location (gdbarch,
4042 displaced_step_at_entry_point);
4043
4044 set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE);
4045
7b112f9c 4046 /* Hook in ABI-specific overrides, if they have been registered. */
8a4c2d24
UW		 4047 info.target_desc = tdesc;
4048 info.tdep_info = (void *) tdesc_data;
4be87837 4049 gdbarch_init_osabi (info, gdbarch);
7b112f9c 4050
61a65099
KB		 4051 switch (info.osabi)
4052 {
f5aecab8 4053 case GDB_OSABI_LINUX:
61a65099
KB		 4054 case GDB_OSABI_NETBSD_AOUT:
4055 case GDB_OSABI_NETBSD_ELF:
4056 case GDB_OSABI_UNKNOWN:
61a65099 4057 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
1af5d7ce
UW		 4058 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
4059 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
61a65099
KB		 4060 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
4061 break;
4062 default:
61a65099 4063 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
81332287
KB		 4064
4065 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
1af5d7ce
UW		 4066 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
4067 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
81332287 4068 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
61a65099
KB		 4069 }
4070
7cc46491
DJ		 4071 set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type);
4072 set_tdesc_pseudo_register_reggroup_p (gdbarch,
4073 rs6000_pseudo_register_reggroup_p);
4074 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
4075
4076 /* Override the normal target description method to make the SPE upper
4077 halves anonymous. */
4078 set_gdbarch_register_name (gdbarch, rs6000_register_name);
4079
604c2f83
LM		 4080 /* Choose register numbers for all supported pseudo-registers. */
4081 tdep->ppc_ev0_regnum = -1;
4082 tdep->ppc_dl0_regnum = -1;
4083 tdep->ppc_vsr0_regnum = -1;
4084 tdep->ppc_efpr0_regnum = -1;
9f643768 4085
604c2f83
LM		 4086 cur_reg = gdbarch_num_regs (gdbarch);
4087
4088 if (have_spe)
4089 {
4090 tdep->ppc_ev0_regnum = cur_reg;
4091 cur_reg += 32;
4092 }
4093 if (have_dfp)
4094 {
4095 tdep->ppc_dl0_regnum = cur_reg;
4096 cur_reg += 16;
4097 }
4098 if (have_vsx)
4099 {
4100 tdep->ppc_vsr0_regnum = cur_reg;
4101 cur_reg += 64;
4102 tdep->ppc_efpr0_regnum = cur_reg;
4103 cur_reg += 32;
4104 }
f949c649 4105
604c2f83
LM		 4106 gdb_assert (gdbarch_num_regs (gdbarch)
4107 + gdbarch_num_pseudo_regs (gdbarch) == cur_reg);
f949c649 4108
7a78ae4e 4109 return gdbarch;
c906108c
SS		 4110}
4111
7b112f9c 4112static void
8b164abb 4113rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
7b112f9c 4114{
8b164abb 4115 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7b112f9c
JT		 4116
4117 if (tdep == NULL)
4118 return;
4119
4be87837 4120 /* FIXME: Dump gdbarch_tdep. */
7b112f9c
JT		 4121}
4122
55eddb0f
DJ		 4123/* PowerPC-specific commands. */
4124
4125static void
4126set_powerpc_command (char *args, int from_tty)
4127{
4128 printf_unfiltered (_("\
4129\"set powerpc\" must be followed by an appropriate subcommand.\n"));
4130 help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout);
4131}
4132
4133static void
4134show_powerpc_command (char *args, int from_tty)
4135{
4136 cmd_show_list (showpowerpccmdlist, from_tty, "");
4137}
4138
4139static void
4140powerpc_set_soft_float (char *args, int from_tty,
4141 struct cmd_list_element *c)
4142{
4143 struct gdbarch_info info;
4144
4145 /* Update the architecture. */
4146 gdbarch_info_init (&info);
4147 if (!gdbarch_update_p (info))
4148 internal_error (__FILE__, __LINE__, "could not update architecture");
4149}
4150
4151static void
4152powerpc_set_vector_abi (char *args, int from_tty,
4153 struct cmd_list_element *c)
4154{
4155 struct gdbarch_info info;
4156 enum powerpc_vector_abi vector_abi;
4157
4158 for (vector_abi = POWERPC_VEC_AUTO;
4159 vector_abi != POWERPC_VEC_LAST;
4160 vector_abi++)
4161 if (strcmp (powerpc_vector_abi_string,
4162 powerpc_vector_strings[vector_abi]) == 0)
4163 {
4164 powerpc_vector_abi_global = vector_abi;
4165 break;
4166 }
4167
4168 if (vector_abi == POWERPC_VEC_LAST)
4169 internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."),
4170 powerpc_vector_abi_string);
4171
4172 /* Update the architecture. */
4173 gdbarch_info_init (&info);
4174 if (!gdbarch_update_p (info))
4175 internal_error (__FILE__, __LINE__, "could not update architecture");
4176}
4177
c906108c
SS		 4178/* Initialization code. */
4179
a78f21af 4180extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
b9362cc7 4181
c906108c 4182void
fba45db2 4183_initialize_rs6000_tdep (void)
c906108c 4184{
7b112f9c
JT		 4185 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
4186 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
7cc46491
DJ		 4187
4188 /* Initialize the standard target descriptions. */
4189 initialize_tdesc_powerpc_32 ();
7284e1be 4190 initialize_tdesc_powerpc_altivec32 ();
604c2f83 4191 initialize_tdesc_powerpc_vsx32 ();
7cc46491
DJ		 4192 initialize_tdesc_powerpc_403 ();
4193 initialize_tdesc_powerpc_403gc ();
4d09ffea 4194 initialize_tdesc_powerpc_405 ();
7cc46491
DJ		 4195 initialize_tdesc_powerpc_505 ();
4196 initialize_tdesc_powerpc_601 ();
4197 initialize_tdesc_powerpc_602 ();
4198 initialize_tdesc_powerpc_603 ();
4199 initialize_tdesc_powerpc_604 ();
4200 initialize_tdesc_powerpc_64 ();
7284e1be 4201 initialize_tdesc_powerpc_altivec64 ();
604c2f83 4202 initialize_tdesc_powerpc_vsx64 ();
7cc46491
DJ		 4203 initialize_tdesc_powerpc_7400 ();
4204 initialize_tdesc_powerpc_750 ();
4205 initialize_tdesc_powerpc_860 ();
4206 initialize_tdesc_powerpc_e500 ();
4207 initialize_tdesc_rs6000 ();
55eddb0f
DJ		 4208
4209 /* Add root prefix command for all "set powerpc"/"show powerpc"
4210 commands. */
4211 add_prefix_cmd ("powerpc", no_class, set_powerpc_command,
4212 _("Various PowerPC-specific commands."),
4213 &setpowerpccmdlist, "set powerpc ", 0, &setlist);
4214
4215 add_prefix_cmd ("powerpc", no_class, show_powerpc_command,
4216 _("Various PowerPC-specific commands."),
4217 &showpowerpccmdlist, "show powerpc ", 0, &showlist);
4218
4219 /* Add a command to allow the user to force the ABI. */
4220 add_setshow_auto_boolean_cmd ("soft-float", class_support,
4221 &powerpc_soft_float_global,
4222 _("Set whether to use a soft-float ABI."),
4223 _("Show whether to use a soft-float ABI."),
4224 NULL,
4225 powerpc_set_soft_float, NULL,
4226 &setpowerpccmdlist, &showpowerpccmdlist);
4227
4228 add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings,
4229 &powerpc_vector_abi_string,
4230 _("Set the vector ABI."),
4231 _("Show the vector ABI."),
4232 NULL, powerpc_set_vector_abi, NULL,
4233 &setpowerpccmdlist, &showpowerpccmdlist);
c906108c 4234}
GDB Binutils - Deliverables
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