projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
2009-01-30 Julian Brown <julian@codesourcery.com>
[deliverable/binutils-gdb.git] / gdb / rs6000-tdep.c
CommitLineData
c906108c 1/* Target-dependent code for GDB, the GNU debugger.
7aea86e6 2
6aba47ca 3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
0fb0cc75 4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
721d14ba 5 Free Software Foundation, Inc.
c906108c 6
c5aa993b 7 This file is part of GDB.
c906108c 8
c5aa993b
JM		 9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
c5aa993b 12 (at your option) any later version.
c906108c 13
c5aa993b
JM		 14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
c906108c 18
c5aa993b 19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c
SS		 21
22#include "defs.h"
23#include "frame.h"
24#include "inferior.h"
25#include "symtab.h"
26#include "target.h"
27#include "gdbcore.h"
28#include "gdbcmd.h"
c906108c 29#include "objfiles.h"
7a78ae4e 30#include "arch-utils.h"
4e052eda 31#include "regcache.h"
d195bc9f 32#include "regset.h"
d16aafd8 33#include "doublest.h"
fd0407d6 34#include "value.h"
1fcc0bb8 35#include "parser-defs.h"
4be87837 36#include "osabi.h"
7d9b040b 37#include "infcall.h"
9f643768
JB		 38#include "sim-regno.h"
39#include "gdb/sim-ppc.h"
6ced10dd 40#include "reggroups.h"
4fc771b8 41#include "dwarf2-frame.h"
7cc46491
DJ		 42#include "target-descriptions.h"
43#include "user-regs.h"
7a78ae4e 44
2fccf04a 45#include "libbfd.h" /* for bfd_default_set_arch_mach */
7a78ae4e 46#include "coff/internal.h" /* for libcoff.h */
2fccf04a 47#include "libcoff.h" /* for xcoff_data */
11ed25ac
KB		 48#include "coff/xcoff.h"
49#include "libxcoff.h"
7a78ae4e 50
9aa1e687 51#include "elf-bfd.h"
55eddb0f 52#include "elf/ppc.h"
7a78ae4e 53
6ded7999 54#include "solib-svr4.h"
9aa1e687 55#include "ppc-tdep.h"
7a78ae4e 56
338ef23d 57#include "gdb_assert.h"
a89aa300 58#include "dis-asm.h"
338ef23d 59
61a65099
KB		 60#include "trad-frame.h"
61#include "frame-unwind.h"
62#include "frame-base.h"
63
7cc46491 64#include "features/rs6000/powerpc-32.c"
7284e1be 65#include "features/rs6000/powerpc-altivec32.c"
604c2f83 66#include "features/rs6000/powerpc-vsx32.c"
7cc46491
DJ		 67#include "features/rs6000/powerpc-403.c"
68#include "features/rs6000/powerpc-403gc.c"
69#include "features/rs6000/powerpc-505.c"
70#include "features/rs6000/powerpc-601.c"
71#include "features/rs6000/powerpc-602.c"
72#include "features/rs6000/powerpc-603.c"
73#include "features/rs6000/powerpc-604.c"
74#include "features/rs6000/powerpc-64.c"
7284e1be 75#include "features/rs6000/powerpc-altivec64.c"
604c2f83 76#include "features/rs6000/powerpc-vsx64.c"
7cc46491
DJ		 77#include "features/rs6000/powerpc-7400.c"
78#include "features/rs6000/powerpc-750.c"
79#include "features/rs6000/powerpc-860.c"
80#include "features/rs6000/powerpc-e500.c"
81#include "features/rs6000/rs6000.c"
82
5a9e69ba
TJB		 83/* Determine if regnum is an SPE pseudo-register. */
84#define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
85 && (regnum) >= (tdep)->ppc_ev0_regnum \
86 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
87
f949c649
TJB		 88/* Determine if regnum is a decimal float pseudo-register. */
89#define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
90 && (regnum) >= (tdep)->ppc_dl0_regnum \
91 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
92
604c2f83
LM		 93/* Determine if regnum is a POWER7 VSX register. */
94#define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
95 && (regnum) >= (tdep)->ppc_vsr0_regnum \
96 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
97
98/* Determine if regnum is a POWER7 Extended FP register. */
99#define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
100 && (regnum) >= (tdep)->ppc_efpr0_regnum \
101 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_fprs)
102
55eddb0f
DJ		 103/* The list of available "set powerpc ..." and "show powerpc ..."
104 commands. */
105static struct cmd_list_element *setpowerpccmdlist = NULL;
106static struct cmd_list_element *showpowerpccmdlist = NULL;
107
108static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO;
109
110/* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
111static const char *powerpc_vector_strings[] =
112{
113 "auto",
114 "generic",
115 "altivec",
116 "spe",
117 NULL
118};
119
120/* A variable that can be configured by the user. */
121static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO;
122static const char *powerpc_vector_abi_string = "auto";
123
7a78ae4e
ND		 124/* To be used by skip_prologue. */
125
126struct rs6000_framedata
127 {
128 int offset; /* total size of frame --- the distance
129 by which we decrement sp to allocate
130 the frame */
131 int saved_gpr; /* smallest # of saved gpr */
46a9b8ed 132 unsigned int gpr_mask; /* Each bit is an individual saved GPR. */
7a78ae4e 133 int saved_fpr; /* smallest # of saved fpr */
6be8bc0c 134 int saved_vr; /* smallest # of saved vr */
96ff0de4 135 int saved_ev; /* smallest # of saved ev */
7a78ae4e
ND		 136 int alloca_reg; /* alloca register number (frame ptr) */
137 char frameless; /* true if frameless functions. */
138 char nosavedpc; /* true if pc not saved. */
46a9b8ed 139 char used_bl; /* true if link register clobbered */
7a78ae4e
ND		 140 int gpr_offset; /* offset of saved gprs from prev sp */
141 int fpr_offset; /* offset of saved fprs from prev sp */
6be8bc0c 142 int vr_offset; /* offset of saved vrs from prev sp */
96ff0de4 143 int ev_offset; /* offset of saved evs from prev sp */
7a78ae4e 144 int lr_offset; /* offset of saved lr */
46a9b8ed 145 int lr_register; /* register of saved lr, if trustworthy */
7a78ae4e 146 int cr_offset; /* offset of saved cr */
6be8bc0c 147 int vrsave_offset; /* offset of saved vrsave register */
7a78ae4e
ND		 148 };
149
c906108c 150
604c2f83
LM		 151/* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
152int
153vsx_register_p (struct gdbarch *gdbarch, int regno)
154{
155 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
156 if (tdep->ppc_vsr0_regnum < 0)
157 return 0;
158 else
159 return (regno >= tdep->ppc_vsr0_upper_regnum && regno
160 <= tdep->ppc_vsr0_upper_regnum + 31);
161}
162
64b84175
KB		 163/* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
164int
be8626e0 165altivec_register_p (struct gdbarch *gdbarch, int regno)
64b84175 166{
be8626e0 167 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
64b84175
KB		 168 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
169 return 0;
170 else
171 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
172}
173
383f0f5b 174
867e2dc5
JB		 175/* Return true if REGNO is an SPE register, false otherwise. */
176int
be8626e0 177spe_register_p (struct gdbarch *gdbarch, int regno)
867e2dc5 178{
be8626e0 179 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
867e2dc5
JB		 180
181 /* Is it a reference to EV0 -- EV31, and do we have those? */
5a9e69ba 182 if (IS_SPE_PSEUDOREG (tdep, regno))
867e2dc5
JB		 183 return 1;
184
6ced10dd
JB		 185 /* Is it a reference to one of the raw upper GPR halves? */
186 if (tdep->ppc_ev0_upper_regnum >= 0
187 && tdep->ppc_ev0_upper_regnum <= regno
188 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
189 return 1;
190
867e2dc5
JB		 191 /* Is it a reference to the 64-bit accumulator, and do we have that? */
192 if (tdep->ppc_acc_regnum >= 0
193 && tdep->ppc_acc_regnum == regno)
194 return 1;
195
196 /* Is it a reference to the SPE floating-point status and control register,
197 and do we have that? */
198 if (tdep->ppc_spefscr_regnum >= 0
199 && tdep->ppc_spefscr_regnum == regno)
200 return 1;
201
202 return 0;
203}
204
205
383f0f5b
JB		 206/* Return non-zero if the architecture described by GDBARCH has
207 floating-point registers (f0 --- f31 and fpscr). */
0a613259
AC		 208int
209ppc_floating_point_unit_p (struct gdbarch *gdbarch)
210{
383f0f5b
JB		 211 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
212
213 return (tdep->ppc_fp0_regnum >= 0
214 && tdep->ppc_fpscr_regnum >= 0);
0a613259 215}
9f643768 216
604c2f83
LM		 217/* Return non-zero if the architecture described by GDBARCH has
218 VSX registers (vsr0 --- vsr63). */
219int
220ppc_vsx_support_p (struct gdbarch *gdbarch)
221{
222 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
223
224 return tdep->ppc_vsr0_regnum >= 0;
225}
226
06caf7d2
CES		 227/* Return non-zero if the architecture described by GDBARCH has
228 Altivec registers (vr0 --- vr31, vrsave and vscr). */
229int
230ppc_altivec_support_p (struct gdbarch *gdbarch)
231{
232 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
233
234 return (tdep->ppc_vr0_regnum >= 0
235 && tdep->ppc_vrsave_regnum >= 0);
236}
09991fa0
JB		 237
238/* Check that TABLE[GDB_REGNO] is not already initialized, and then
239 set it to SIM_REGNO.
240
241 This is a helper function for init_sim_regno_table, constructing
242 the table mapping GDB register numbers to sim register numbers; we
243 initialize every element in that table to -1 before we start
244 filling it in. */
9f643768
JB		 245static void
246set_sim_regno (int *table, int gdb_regno, int sim_regno)
247{
248 /* Make sure we don't try to assign any given GDB register a sim
249 register number more than once. */
250 gdb_assert (table[gdb_regno] == -1);
251 table[gdb_regno] = sim_regno;
252}
253
09991fa0
JB		 254
255/* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
256 numbers to simulator register numbers, based on the values placed
257 in the ARCH->tdep->ppc_foo_regnum members. */
9f643768
JB		 258static void
259init_sim_regno_table (struct gdbarch *arch)
260{
261 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
7cc46491 262 int total_regs = gdbarch_num_regs (arch);
9f643768
JB		 263 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
264 int i;
7cc46491
DJ		 265 static const char *const segment_regs[] = {
266 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
267 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
268 };
9f643768
JB		 269
270 /* Presume that all registers not explicitly mentioned below are
271 unavailable from the sim. */
272 for (i = 0; i < total_regs; i++)
273 sim_regno[i] = -1;
274
275 /* General-purpose registers. */
276 for (i = 0; i < ppc_num_gprs; i++)
277 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
278
279 /* Floating-point registers. */
280 if (tdep->ppc_fp0_regnum >= 0)
281 for (i = 0; i < ppc_num_fprs; i++)
282 set_sim_regno (sim_regno,
283 tdep->ppc_fp0_regnum + i,
284 sim_ppc_f0_regnum + i);
285 if (tdep->ppc_fpscr_regnum >= 0)
286 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
287
288 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
289 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
290 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
291
292 /* Segment registers. */
7cc46491
DJ		 293 for (i = 0; i < ppc_num_srs; i++)
294 {
295 int gdb_regno;
296
297 gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1);
298 if (gdb_regno >= 0)
299 set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i);
300 }
9f643768
JB		 301
302 /* Altivec registers. */
303 if (tdep->ppc_vr0_regnum >= 0)
304 {
305 for (i = 0; i < ppc_num_vrs; i++)
306 set_sim_regno (sim_regno,
307 tdep->ppc_vr0_regnum + i,
308 sim_ppc_vr0_regnum + i);
309
310 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
311 we can treat this more like the other cases. */
312 set_sim_regno (sim_regno,
313 tdep->ppc_vr0_regnum + ppc_num_vrs,
314 sim_ppc_vscr_regnum);
315 }
316 /* vsave is a special-purpose register, so the code below handles it. */
317
318 /* SPE APU (E500) registers. */
6ced10dd
JB		 319 if (tdep->ppc_ev0_upper_regnum >= 0)
320 for (i = 0; i < ppc_num_gprs; i++)
321 set_sim_regno (sim_regno,
322 tdep->ppc_ev0_upper_regnum + i,
323 sim_ppc_rh0_regnum + i);
9f643768
JB		 324 if (tdep->ppc_acc_regnum >= 0)
325 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
326 /* spefscr is a special-purpose register, so the code below handles it. */
327
7cc46491 328#ifdef WITH_SIM
9f643768
JB		 329 /* Now handle all special-purpose registers. Verify that they
330 haven't mistakenly been assigned numbers by any of the above
7cc46491
DJ		 331 code. */
332 for (i = 0; i < sim_ppc_num_sprs; i++)
333 {
334 const char *spr_name = sim_spr_register_name (i);
335 int gdb_regno = -1;
336
337 if (spr_name != NULL)
338 gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1);
339
340 if (gdb_regno != -1)
341 set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i);
342 }
343#endif
9f643768
JB		 344
345 /* Drop the initialized array into place. */
346 tdep->sim_regno = sim_regno;
347}
348
09991fa0
JB		 349
350/* Given a GDB register number REG, return the corresponding SIM
351 register number. */
9f643768 352static int
e7faf938 353rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg)
9f643768 354{
e7faf938 355 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9f643768
JB		 356 int sim_regno;
357
7cc46491 358 if (tdep->sim_regno == NULL)
e7faf938 359 init_sim_regno_table (gdbarch);
7cc46491 360
f57d151a 361 gdb_assert (0 <= reg
e7faf938
MD		 362 && reg <= gdbarch_num_regs (gdbarch)
363 + gdbarch_num_pseudo_regs (gdbarch));
9f643768
JB		 364 sim_regno = tdep->sim_regno[reg];
365
366 if (sim_regno >= 0)
367 return sim_regno;
368 else
369 return LEGACY_SIM_REGNO_IGNORE;
370}
371
d195bc9f
MK		 372\f
373
374/* Register set support functions. */
375
f2db237a
AM		 376/* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
377 Write the register to REGCACHE. */
378
7284e1be 379void
d195bc9f 380ppc_supply_reg (struct regcache *regcache, int regnum,
f2db237a 381 const gdb_byte *regs, size_t offset, int regsize)
d195bc9f
MK		 382{
383 if (regnum != -1 && offset != -1)
f2db237a
AM		 384 {
385 if (regsize > 4)
386 {
387 struct gdbarch *gdbarch = get_regcache_arch (regcache);
388 int gdb_regsize = register_size (gdbarch, regnum);
389 if (gdb_regsize < regsize
390 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
391 offset += regsize - gdb_regsize;
392 }
393 regcache_raw_supply (regcache, regnum, regs + offset);
394 }
d195bc9f
MK		 395}
396
f2db237a
AM		 397/* Read register REGNUM from REGCACHE and store to REGS + OFFSET
398 in a field REGSIZE wide. Zero pad as necessary. */
399
7284e1be 400void
d195bc9f 401ppc_collect_reg (const struct regcache *regcache, int regnum,
f2db237a 402 gdb_byte *regs, size_t offset, int regsize)
d195bc9f
MK		 403{
404 if (regnum != -1 && offset != -1)
f2db237a
AM		 405 {
406 if (regsize > 4)
407 {
408 struct gdbarch *gdbarch = get_regcache_arch (regcache);
409 int gdb_regsize = register_size (gdbarch, regnum);
410 if (gdb_regsize < regsize)
411 {
412 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
413 {
414 memset (regs + offset, 0, regsize - gdb_regsize);
415 offset += regsize - gdb_regsize;
416 }
417 else
418 memset (regs + offset + regsize - gdb_regsize, 0,
419 regsize - gdb_regsize);
420 }
421 }
422 regcache_raw_collect (regcache, regnum, regs + offset);
423 }
d195bc9f
MK		 424}
425
f2db237a
AM		 426static int
427ppc_greg_offset (struct gdbarch *gdbarch,
428 struct gdbarch_tdep *tdep,
429 const struct ppc_reg_offsets *offsets,
430 int regnum,
431 int *regsize)
432{
433 *regsize = offsets->gpr_size;
434 if (regnum >= tdep->ppc_gp0_regnum
435 && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs)
436 return (offsets->r0_offset
437 + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size);
438
439 if (regnum == gdbarch_pc_regnum (gdbarch))
440 return offsets->pc_offset;
441
442 if (regnum == tdep->ppc_ps_regnum)
443 return offsets->ps_offset;
444
445 if (regnum == tdep->ppc_lr_regnum)
446 return offsets->lr_offset;
447
448 if (regnum == tdep->ppc_ctr_regnum)
449 return offsets->ctr_offset;
450
451 *regsize = offsets->xr_size;
452 if (regnum == tdep->ppc_cr_regnum)
453 return offsets->cr_offset;
454
455 if (regnum == tdep->ppc_xer_regnum)
456 return offsets->xer_offset;
457
458 if (regnum == tdep->ppc_mq_regnum)
459 return offsets->mq_offset;
460
461 return -1;
462}
463
464static int
465ppc_fpreg_offset (struct gdbarch_tdep *tdep,
466 const struct ppc_reg_offsets *offsets,
467 int regnum)
468{
469 if (regnum >= tdep->ppc_fp0_regnum
470 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs)
471 return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8;
472
473 if (regnum == tdep->ppc_fpscr_regnum)
474 return offsets->fpscr_offset;
475
476 return -1;
477}
478
06caf7d2
CES		 479static int
480ppc_vrreg_offset (struct gdbarch_tdep *tdep,
481 const struct ppc_reg_offsets *offsets,
482 int regnum)
483{
484 if (regnum >= tdep->ppc_vr0_regnum
485 && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs)
486 return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16;
487
488 if (regnum == tdep->ppc_vrsave_regnum - 1)
489 return offsets->vscr_offset;
490
491 if (regnum == tdep->ppc_vrsave_regnum)
492 return offsets->vrsave_offset;
493
494 return -1;
495}
496
d195bc9f
MK		 497/* Supply register REGNUM in the general-purpose register set REGSET
498 from the buffer specified by GREGS and LEN to register cache
499 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
500
501void
502ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
503 int regnum, const void *gregs, size_t len)
504{
505 struct gdbarch *gdbarch = get_regcache_arch (regcache);
506 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
507 const struct ppc_reg_offsets *offsets = regset->descr;
508 size_t offset;
f2db237a 509 int regsize;
d195bc9f 510
f2db237a 511 if (regnum == -1)
d195bc9f 512 {
f2db237a
AM		 513 int i;
514 int gpr_size = offsets->gpr_size;
515
516 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
517 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
518 i++, offset += gpr_size)
519 ppc_supply_reg (regcache, i, gregs, offset, gpr_size);
520
521 ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch),
522 gregs, offsets->pc_offset, gpr_size);
523 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
524 gregs, offsets->ps_offset, gpr_size);
525 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
526 gregs, offsets->lr_offset, gpr_size);
527 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
528 gregs, offsets->ctr_offset, gpr_size);
529 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
530 gregs, offsets->cr_offset, offsets->xr_size);
531 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
532 gregs, offsets->xer_offset, offsets->xr_size);
533 ppc_supply_reg (regcache, tdep->ppc_mq_regnum,
534 gregs, offsets->mq_offset, offsets->xr_size);
535 return;
d195bc9f
MK		 536 }
537
f2db237a
AM		 538 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
539 ppc_supply_reg (regcache, regnum, gregs, offset, regsize);
d195bc9f
MK		 540}
541
542/* Supply register REGNUM in the floating-point register set REGSET
543 from the buffer specified by FPREGS and LEN to register cache
544 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
545
546void
547ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
548 int regnum, const void *fpregs, size_t len)
549{
550 struct gdbarch *gdbarch = get_regcache_arch (regcache);
f2db237a
AM		 551 struct gdbarch_tdep *tdep;
552 const struct ppc_reg_offsets *offsets;
d195bc9f 553 size_t offset;
d195bc9f 554
f2db237a
AM		 555 if (!ppc_floating_point_unit_p (gdbarch))
556 return;
383f0f5b 557
f2db237a
AM		 558 tdep = gdbarch_tdep (gdbarch);
559 offsets = regset->descr;
560 if (regnum == -1)
d195bc9f 561 {
f2db237a
AM		 562 int i;
563
564 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
565 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
566 i++, offset += 8)
567 ppc_supply_reg (regcache, i, fpregs, offset, 8);
568
569 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
570 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
571 return;
d195bc9f
MK		 572 }
573
f2db237a
AM		 574 offset = ppc_fpreg_offset (tdep, offsets, regnum);
575 ppc_supply_reg (regcache, regnum, fpregs, offset,
576 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
d195bc9f
MK		 577}
578
604c2f83
LM		 579/* Supply register REGNUM in the VSX register set REGSET
580 from the buffer specified by VSXREGS and LEN to register cache
581 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
582
583void
584ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache,
585 int regnum, const void *vsxregs, size_t len)
586{
587 struct gdbarch *gdbarch = get_regcache_arch (regcache);
588 struct gdbarch_tdep *tdep;
589
590 if (!ppc_vsx_support_p (gdbarch))
591 return;
592
593 tdep = gdbarch_tdep (gdbarch);
594
595 if (regnum == -1)
596 {
597 int i;
598
599 for (i = tdep->ppc_vsr0_upper_regnum;
600 i < tdep->ppc_vsr0_upper_regnum + 32;
601 i++)
602 ppc_supply_reg (regcache, i, vsxregs, 0, 8);
603
604 return;
605 }
606 else
607 ppc_supply_reg (regcache, regnum, vsxregs, 0, 8);
608}
609
06caf7d2
CES		 610/* Supply register REGNUM in the Altivec register set REGSET
611 from the buffer specified by VRREGS and LEN to register cache
612 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
613
614void
615ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache,
616 int regnum, const void *vrregs, size_t len)
617{
618 struct gdbarch *gdbarch = get_regcache_arch (regcache);
619 struct gdbarch_tdep *tdep;
620 const struct ppc_reg_offsets *offsets;
621 size_t offset;
622
623 if (!ppc_altivec_support_p (gdbarch))
624 return;
625
626 tdep = gdbarch_tdep (gdbarch);
627 offsets = regset->descr;
628 if (regnum == -1)
629 {
630 int i;
631
632 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
633 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
634 i++, offset += 16)
635 ppc_supply_reg (regcache, i, vrregs, offset, 16);
636
637 ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
638 vrregs, offsets->vscr_offset, 4);
639
640 ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum,
641 vrregs, offsets->vrsave_offset, 4);
642 return;
643 }
644
645 offset = ppc_vrreg_offset (tdep, offsets, regnum);
646 if (regnum != tdep->ppc_vrsave_regnum
647 && regnum != tdep->ppc_vrsave_regnum - 1)
648 ppc_supply_reg (regcache, regnum, vrregs, offset, 16);
649 else
650 ppc_supply_reg (regcache, regnum,
651 vrregs, offset, 4);
652}
653
d195bc9f 654/* Collect register REGNUM in the general-purpose register set
f2db237a 655 REGSET from register cache REGCACHE into the buffer specified by
d195bc9f
MK		 656 GREGS and LEN. If REGNUM is -1, do this for all registers in
657 REGSET. */
658
659void
660ppc_collect_gregset (const struct regset *regset,
661 const struct regcache *regcache,
662 int regnum, void *gregs, size_t len)
663{
664 struct gdbarch *gdbarch = get_regcache_arch (regcache);
665 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
666 const struct ppc_reg_offsets *offsets = regset->descr;
667 size_t offset;
f2db237a 668 int regsize;
d195bc9f 669
f2db237a 670 if (regnum == -1)
d195bc9f 671 {
f2db237a
AM		 672 int i;
673 int gpr_size = offsets->gpr_size;
674
675 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
676 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
677 i++, offset += gpr_size)
678 ppc_collect_reg (regcache, i, gregs, offset, gpr_size);
679
680 ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch),
681 gregs, offsets->pc_offset, gpr_size);
682 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
683 gregs, offsets->ps_offset, gpr_size);
684 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
685 gregs, offsets->lr_offset, gpr_size);
686 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
687 gregs, offsets->ctr_offset, gpr_size);
688 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
689 gregs, offsets->cr_offset, offsets->xr_size);
690 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
691 gregs, offsets->xer_offset, offsets->xr_size);
692 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
693 gregs, offsets->mq_offset, offsets->xr_size);
694 return;
d195bc9f
MK		 695 }
696
f2db237a
AM		 697 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
698 ppc_collect_reg (regcache, regnum, gregs, offset, regsize);
d195bc9f
MK		 699}
700
701/* Collect register REGNUM in the floating-point register set
f2db237a 702 REGSET from register cache REGCACHE into the buffer specified by
d195bc9f
MK		 703 FPREGS and LEN. If REGNUM is -1, do this for all registers in
704 REGSET. */
705
706void
707ppc_collect_fpregset (const struct regset *regset,
708 const struct regcache *regcache,
709 int regnum, void *fpregs, size_t len)
710{
711 struct gdbarch *gdbarch = get_regcache_arch (regcache);
f2db237a
AM		 712 struct gdbarch_tdep *tdep;
713 const struct ppc_reg_offsets *offsets;
d195bc9f 714 size_t offset;
d195bc9f 715
f2db237a
AM		 716 if (!ppc_floating_point_unit_p (gdbarch))
717 return;
383f0f5b 718
f2db237a
AM		 719 tdep = gdbarch_tdep (gdbarch);
720 offsets = regset->descr;
721 if (regnum == -1)
d195bc9f 722 {
f2db237a
AM		 723 int i;
724
725 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
726 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
727 i++, offset += 8)
728 ppc_collect_reg (regcache, i, fpregs, offset, 8);
729
730 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
731 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
732 return;
d195bc9f
MK		 733 }
734
f2db237a
AM		 735 offset = ppc_fpreg_offset (tdep, offsets, regnum);
736 ppc_collect_reg (regcache, regnum, fpregs, offset,
737 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
d195bc9f 738}
06caf7d2 739
604c2f83
LM		 740/* Collect register REGNUM in the VSX register set
741 REGSET from register cache REGCACHE into the buffer specified by
742 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
743 REGSET. */
744
745void
746ppc_collect_vsxregset (const struct regset *regset,
747 const struct regcache *regcache,
748 int regnum, void *vsxregs, size_t len)
749{
750 struct gdbarch *gdbarch = get_regcache_arch (regcache);
751 struct gdbarch_tdep *tdep;
752
753 if (!ppc_vsx_support_p (gdbarch))
754 return;
755
756 tdep = gdbarch_tdep (gdbarch);
757
758 if (regnum == -1)
759 {
760 int i;
761
762 for (i = tdep->ppc_vsr0_upper_regnum;
763 i < tdep->ppc_vsr0_upper_regnum + 32;
764 i++)
765 ppc_collect_reg (regcache, i, vsxregs, 0, 8);
766
767 return;
768 }
769 else
770 ppc_collect_reg (regcache, regnum, vsxregs, 0, 8);
771}
772
773
06caf7d2
CES		 774/* Collect register REGNUM in the Altivec register set
775 REGSET from register cache REGCACHE into the buffer specified by
776 VRREGS and LEN. If REGNUM is -1, do this for all registers in
777 REGSET. */
778
779void
780ppc_collect_vrregset (const struct regset *regset,
781 const struct regcache *regcache,
782 int regnum, void *vrregs, size_t len)
783{
784 struct gdbarch *gdbarch = get_regcache_arch (regcache);
785 struct gdbarch_tdep *tdep;
786 const struct ppc_reg_offsets *offsets;
787 size_t offset;
788
789 if (!ppc_altivec_support_p (gdbarch))
790 return;
791
792 tdep = gdbarch_tdep (gdbarch);
793 offsets = regset->descr;
794 if (regnum == -1)
795 {
796 int i;
797
798 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
799 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
800 i++, offset += 16)
801 ppc_collect_reg (regcache, i, vrregs, offset, 16);
802
803 ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
804 vrregs, offsets->vscr_offset, 4);
805
806 ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum,
807 vrregs, offsets->vrsave_offset, 4);
808 return;
809 }
810
811 offset = ppc_vrreg_offset (tdep, offsets, regnum);
812 if (regnum != tdep->ppc_vrsave_regnum
813 && regnum != tdep->ppc_vrsave_regnum - 1)
814 ppc_collect_reg (regcache, regnum, vrregs, offset, 16);
815 else
816 ppc_collect_reg (regcache, regnum,
817 vrregs, offset, 4);
818}
d195bc9f 819\f
0a613259 820
0d1243d9
PG		 821static int
822insn_changes_sp_or_jumps (unsigned long insn)
823{
824 int opcode = (insn >> 26) & 0x03f;
825 int sd = (insn >> 21) & 0x01f;
826 int a = (insn >> 16) & 0x01f;
827 int subcode = (insn >> 1) & 0x3ff;
828
829 /* Changes the stack pointer. */
830
831 /* NOTE: There are many ways to change the value of a given register.
832 The ways below are those used when the register is R1, the SP,
833 in a funtion's epilogue. */
834
835 if (opcode == 31 && subcode == 444 && a == 1)
836 return 1; /* mr R1,Rn */
837 if (opcode == 14 && sd == 1)
838 return 1; /* addi R1,Rn,simm */
839 if (opcode == 58 && sd == 1)
840 return 1; /* ld R1,ds(Rn) */
841
842 /* Transfers control. */
843
844 if (opcode == 18)
845 return 1; /* b */
846 if (opcode == 16)
847 return 1; /* bc */
848 if (opcode == 19 && subcode == 16)
849 return 1; /* bclr */
850 if (opcode == 19 && subcode == 528)
851 return 1; /* bcctr */
852
853 return 0;
854}
855
856/* Return true if we are in the function's epilogue, i.e. after the
857 instruction that destroyed the function's stack frame.
858
859 1) scan forward from the point of execution:
860 a) If you find an instruction that modifies the stack pointer
861 or transfers control (except a return), execution is not in
862 an epilogue, return.
863 b) Stop scanning if you find a return instruction or reach the
864 end of the function or reach the hard limit for the size of
865 an epilogue.
866 2) scan backward from the point of execution:
867 a) If you find an instruction that modifies the stack pointer,
868 execution *is* in an epilogue, return.
869 b) Stop scanning if you reach an instruction that transfers
870 control or the beginning of the function or reach the hard
871 limit for the size of an epilogue. */
872
873static int
874rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
875{
46a9b8ed 876 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
0d1243d9
PG		 877 bfd_byte insn_buf[PPC_INSN_SIZE];
878 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
879 unsigned long insn;
880 struct frame_info *curfrm;
881
882 /* Find the search limits based on function boundaries and hard limit. */
883
884 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
885 return 0;
886
887 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
888 if (epilogue_start < func_start) epilogue_start = func_start;
889
890 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
891 if (epilogue_end > func_end) epilogue_end = func_end;
892
893 curfrm = get_current_frame ();
894
895 /* Scan forward until next 'blr'. */
896
897 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
898 {
899 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
900 return 0;
4e463ff5 901 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE);
0d1243d9
PG		 902 if (insn == 0x4e800020)
903 break;
46a9b8ed
DJ		 904 /* Assume a bctr is a tail call unless it points strictly within
905 this function. */
906 if (insn == 0x4e800420)
907 {
908 CORE_ADDR ctr = get_frame_register_unsigned (curfrm,
909 tdep->ppc_ctr_regnum);
910 if (ctr > func_start && ctr < func_end)
911 return 0;
912 else
913 break;
914 }
0d1243d9
PG		 915 if (insn_changes_sp_or_jumps (insn))
916 return 0;
917 }
918
919 /* Scan backward until adjustment to stack pointer (R1). */
920
921 for (scan_pc = pc - PPC_INSN_SIZE;
922 scan_pc >= epilogue_start;
923 scan_pc -= PPC_INSN_SIZE)
924 {
925 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
926 return 0;
4e463ff5 927 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE);
0d1243d9
PG		 928 if (insn_changes_sp_or_jumps (insn))
929 return 1;
930 }
931
932 return 0;
933}
934
143985b7 935/* Get the ith function argument for the current function. */
b9362cc7 936static CORE_ADDR
143985b7
AF		 937rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
938 struct type *type)
939{
50fd1280 940 return get_frame_register_unsigned (frame, 3 + argi);
143985b7
AF		 941}
942
c906108c
SS		 943/* Sequence of bytes for breakpoint instruction. */
944
f4f9705a 945const static unsigned char *
67d57894
MD		 946rs6000_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
947 int *bp_size)
c906108c 948{
aaab4dba
AC		 949 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
950 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
c906108c 951 *bp_size = 4;
67d57894 952 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
c906108c
SS		 953 return big_breakpoint;
954 else
955 return little_breakpoint;
956}
957
f74c6cad
LM		 958/* Instruction masks for displaced stepping. */
959#define BRANCH_MASK 0xfc000000
960#define BP_MASK 0xFC0007FE
961#define B_INSN 0x48000000
962#define BC_INSN 0x40000000
963#define BXL_INSN 0x4c000000
964#define BP_INSN 0x7C000008
965
966/* Fix up the state of registers and memory after having single-stepped
967 a displaced instruction. */
968void
969ppc_displaced_step_fixup (struct gdbarch *gdbarch,
970 struct displaced_step_closure *closure,
971 CORE_ADDR from, CORE_ADDR to,
972 struct regcache *regs)
973{
974 /* Since we use simple_displaced_step_copy_insn, our closure is a
975 copy of the instruction. */
976 ULONGEST insn = extract_unsigned_integer ((gdb_byte *) closure,
977 PPC_INSN_SIZE);
978 ULONGEST opcode = 0;
979 /* Offset for non PC-relative instructions. */
980 LONGEST offset = PPC_INSN_SIZE;
981
982 opcode = insn & BRANCH_MASK;
983
984 if (debug_displaced)
985 fprintf_unfiltered (gdb_stdlog,
986 "displaced: (ppc) fixup (0x%s, 0x%s)\n",
987 paddr_nz (from), paddr_nz (to));
988
989
990 /* Handle PC-relative branch instructions. */
991 if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN)
992 {
a4fafde3 993 ULONGEST current_pc;
f74c6cad
LM		 994
995 /* Read the current PC value after the instruction has been executed
996 in a displaced location. Calculate the offset to be applied to the
997 original PC value before the displaced stepping. */
998 regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch),
999 &current_pc);
1000 offset = current_pc - to;
1001
1002 if (opcode != BXL_INSN)
1003 {
1004 /* Check for AA bit indicating whether this is an absolute
1005 addressing or PC-relative (1: absolute, 0: relative). */
1006 if (!(insn & 0x2))
1007 {
1008 /* PC-relative addressing is being used in the branch. */
1009 if (debug_displaced)
1010 fprintf_unfiltered
1011 (gdb_stdlog,
1012 "displaced: (ppc) branch instruction: 0x%s\n"
1013 "displaced: (ppc) adjusted PC from 0x%s to 0x%s\n",
1014 paddr_nz (insn), paddr_nz (current_pc),
1015 paddr_nz (from + offset));
1016
1017 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1018 from + offset);
1019 }
1020 }
1021 else
1022 {
1023 /* If we're here, it means we have a branch to LR or CTR. If the
1024 branch was taken, the offset is probably greater than 4 (the next
1025 instruction), so it's safe to assume that an offset of 4 means we
1026 did not take the branch. */
1027 if (offset == PPC_INSN_SIZE)
1028 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1029 from + PPC_INSN_SIZE);
1030 }
1031
1032 /* Check for LK bit indicating whether we should set the link
1033 register to point to the next instruction
1034 (1: Set, 0: Don't set). */
1035 if (insn & 0x1)
1036 {
1037 /* Link register needs to be set to the next instruction's PC. */
1038 regcache_cooked_write_unsigned (regs,
1039 gdbarch_tdep (gdbarch)->ppc_lr_regnum,
1040 from + PPC_INSN_SIZE);
1041 if (debug_displaced)
1042 fprintf_unfiltered (gdb_stdlog,
1043 "displaced: (ppc) adjusted LR to 0x%s\n",
1044 paddr_nz (from + PPC_INSN_SIZE));
1045
1046 }
1047 }
1048 /* Check for breakpoints in the inferior. If we've found one, place the PC
1049 right at the breakpoint instruction. */
1050 else if ((insn & BP_MASK) == BP_INSN)
1051 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from);
1052 else
1053 /* Handle any other instructions that do not fit in the categories above. */
1054 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1055 from + offset);
1056}
c906108c 1057
ce5eab59
UW		 1058/* Instruction masks used during single-stepping of atomic sequences. */
1059#define LWARX_MASK 0xfc0007fe
1060#define LWARX_INSTRUCTION 0x7c000028
1061#define LDARX_INSTRUCTION 0x7c0000A8
1062#define STWCX_MASK 0xfc0007ff
1063#define STWCX_INSTRUCTION 0x7c00012d
1064#define STDCX_INSTRUCTION 0x7c0001ad
ce5eab59
UW		 1065
1066/* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1067 instruction and ending with a STWCX/STDCX instruction. If such a sequence
1068 is found, attempt to step through it. A breakpoint is placed at the end of
1069 the sequence. */
1070
4a7622d1
UW		 1071int
1072ppc_deal_with_atomic_sequence (struct frame_info *frame)
ce5eab59 1073{
0b1b3e42 1074 CORE_ADDR pc = get_frame_pc (frame);
ce5eab59
UW		 1075 CORE_ADDR breaks[2] = {-1, -1};
1076 CORE_ADDR loc = pc;
24d45690 1077 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
ce5eab59
UW		 1078 int insn = read_memory_integer (loc, PPC_INSN_SIZE);
1079 int insn_count;
1080 int index;
1081 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
1082 const int atomic_sequence_length = 16; /* Instruction sequence length. */
24d45690 1083 int opcode; /* Branch instruction's OPcode. */
ce5eab59
UW		 1084 int bc_insn_count = 0; /* Conditional branch instruction count. */
1085
1086 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1087 if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
1088 && (insn & LWARX_MASK) != LDARX_INSTRUCTION)
1089 return 0;
1090
1091 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1092 instructions. */
1093 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
1094 {
1095 loc += PPC_INSN_SIZE;
1096 insn = read_memory_integer (loc, PPC_INSN_SIZE);
1097
1098 /* Assume that there is at most one conditional branch in the atomic
1099 sequence. If a conditional branch is found, put a breakpoint in
1100 its destination address. */
f74c6cad 1101 if ((insn & BRANCH_MASK) == BC_INSN)
ce5eab59 1102 {
4a7622d1
UW		 1103 int immediate = ((insn & ~3) << 16) >> 16;
1104 int absolute = ((insn >> 1) & 1);
1105
ce5eab59
UW		 1106 if (bc_insn_count >= 1)
1107 return 0; /* More than one conditional branch found, fallback
1108 to the standard single-step code. */
4a7622d1
UW		 1109
1110 if (absolute)
1111 breaks[1] = immediate;
1112 else
1113 breaks[1] = pc + immediate;
1114
1115 bc_insn_count++;
1116 last_breakpoint++;
ce5eab59
UW		 1117 }
1118
1119 if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
1120 || (insn & STWCX_MASK) == STDCX_INSTRUCTION)
1121 break;
1122 }
1123
1124 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1125 if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
1126 && (insn & STWCX_MASK) != STDCX_INSTRUCTION)
1127 return 0;
1128
24d45690 1129 closing_insn = loc;
ce5eab59
UW		 1130 loc += PPC_INSN_SIZE;
1131 insn = read_memory_integer (loc, PPC_INSN_SIZE);
1132
1133 /* Insert a breakpoint right after the end of the atomic sequence. */
1134 breaks[0] = loc;
1135
24d45690
UW		 1136 /* Check for duplicated breakpoints. Check also for a breakpoint
1137 placed (branch instruction's destination) at the stwcx/stdcx
1138 instruction, this resets the reservation and take us back to the
1139 lwarx/ldarx instruction at the beginning of the atomic sequence. */
1140 if (last_breakpoint && ((breaks[1] == breaks[0])
1141 || (breaks[1] == closing_insn)))
ce5eab59
UW		 1142 last_breakpoint = 0;
1143
1144 /* Effectively inserts the breakpoints. */
1145 for (index = 0; index <= last_breakpoint; index++)
1146 insert_single_step_breakpoint (breaks[index]);
1147
1148 return 1;
1149}
1150
c906108c 1151
c906108c
SS		 1152#define SIGNED_SHORT(x) \
1153 ((sizeof (short) == 2) \
1154 ? ((int)(short)(x)) \
1155 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1156
1157#define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1158
55d05f3b
KB		 1159/* Limit the number of skipped non-prologue instructions, as the examining
1160 of the prologue is expensive. */
1161static int max_skip_non_prologue_insns = 10;
1162
773df3e5
JB		 1163/* Return nonzero if the given instruction OP can be part of the prologue
1164 of a function and saves a parameter on the stack. FRAMEP should be
1165 set if one of the previous instructions in the function has set the
1166 Frame Pointer. */
1167
1168static int
1169store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
1170{
1171 /* Move parameters from argument registers to temporary register. */
1172 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1173 {
1174 /* Rx must be scratch register r0. */
1175 const int rx_regno = (op >> 16) & 31;
1176 /* Ry: Only r3 - r10 are used for parameter passing. */
1177 const int ry_regno = GET_SRC_REG (op);
1178
1179 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
1180 {
1181 *r0_contains_arg = 1;
1182 return 1;
1183 }
1184 else
1185 return 0;
1186 }
1187
1188 /* Save a General Purpose Register on stack. */
1189
1190 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1191 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1192 {
1193 /* Rx: Only r3 - r10 are used for parameter passing. */
1194 const int rx_regno = GET_SRC_REG (op);
1195
1196 return (rx_regno >= 3 && rx_regno <= 10);
1197 }
1198
1199 /* Save a General Purpose Register on stack via the Frame Pointer. */
1200
1201 if (framep &&
1202 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1203 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1204 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1205 {
1206 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1207 However, the compiler sometimes uses r0 to hold an argument. */
1208 const int rx_regno = GET_SRC_REG (op);
1209
1210 return ((rx_regno >= 3 && rx_regno <= 10)
1211 || (rx_regno == 0 && *r0_contains_arg));
1212 }
1213
1214 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1215 {
1216 /* Only f2 - f8 are used for parameter passing. */
1217 const int src_regno = GET_SRC_REG (op);
1218
1219 return (src_regno >= 2 && src_regno <= 8);
1220 }
1221
1222 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1223 {
1224 /* Only f2 - f8 are used for parameter passing. */
1225 const int src_regno = GET_SRC_REG (op);
1226
1227 return (src_regno >= 2 && src_regno <= 8);
1228 }
1229
1230 /* Not an insn that saves a parameter on stack. */
1231 return 0;
1232}
55d05f3b 1233
3c77c82a
DJ		 1234/* Assuming that INSN is a "bl" instruction located at PC, return
1235 nonzero if the destination of the branch is a "blrl" instruction.
1236
1237 This sequence is sometimes found in certain function prologues.
1238 It allows the function to load the LR register with a value that
1239 they can use to access PIC data using PC-relative offsets. */
1240
1241static int
1242bl_to_blrl_insn_p (CORE_ADDR pc, int insn)
1243{
0b1b3e42
UW		 1244 CORE_ADDR dest;
1245 int immediate;
1246 int absolute;
3c77c82a
DJ		 1247 int dest_insn;
1248
0b1b3e42
UW		 1249 absolute = (int) ((insn >> 1) & 1);
1250 immediate = ((insn & ~3) << 6) >> 6;
1251 if (absolute)
1252 dest = immediate;
1253 else
1254 dest = pc + immediate;
1255
3c77c82a
DJ		 1256 dest_insn = read_memory_integer (dest, 4);
1257 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
1258 return 1;
1259
1260 return 0;
1261}
1262
8ab3d180
KB		 1263/* Masks for decoding a branch-and-link (bl) instruction.
1264
1265 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1266 The former is anded with the opcode in question; if the result of
1267 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1268 question is a ``bl'' instruction.
1269
1270 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1271 the branch displacement. */
1272
1273#define BL_MASK 0xfc000001
1274#define BL_INSTRUCTION 0x48000001
1275#define BL_DISPLACEMENT_MASK 0x03fffffc
1276
de9f48f0
JG		 1277static unsigned long
1278rs6000_fetch_instruction (const CORE_ADDR pc)
1279{
1280 gdb_byte buf[4];
1281 unsigned long op;
1282
1283 /* Fetch the instruction and convert it to an integer. */
1284 if (target_read_memory (pc, buf, 4))
1285 return 0;
1286 op = extract_unsigned_integer (buf, 4);
1287
1288 return op;
1289}
1290
1291/* GCC generates several well-known sequences of instructions at the begining
1292 of each function prologue when compiling with -fstack-check. If one of
1293 such sequences starts at START_PC, then return the address of the
1294 instruction immediately past this sequence. Otherwise, return START_PC. */
1295
1296static CORE_ADDR
1297rs6000_skip_stack_check (const CORE_ADDR start_pc)
1298{
1299 CORE_ADDR pc = start_pc;
1300 unsigned long op = rs6000_fetch_instruction (pc);
1301
1302 /* First possible sequence: A small number of probes.
1303 stw 0, -<some immediate>(1)
1304 [repeat this instruction any (small) number of times]
1305 */
1306
1307 if ((op & 0xffff0000) == 0x90010000)
1308 {
1309 while ((op & 0xffff0000) == 0x90010000)
1310 {
1311 pc = pc + 4;
1312 op = rs6000_fetch_instruction (pc);
1313 }
1314 return pc;
1315 }
1316
1317 /* Second sequence: A probing loop.
1318 addi 12,1,-<some immediate>
1319 lis 0,-<some immediate>
1320 [possibly ori 0,0,<some immediate>]
1321 add 0,12,0
1322 cmpw 0,12,0
1323 beq 0,<disp>
1324 addi 12,12,-<some immediate>
1325 stw 0,0(12)
1326 b <disp>
1327 [possibly one last probe: stw 0,<some immediate>(12)]
1328 */
1329
1330 while (1)
1331 {
1332 /* addi 12,1,-<some immediate> */
1333 if ((op & 0xffff0000) != 0x39810000)
1334 break;
1335
1336 /* lis 0,-<some immediate> */
1337 pc = pc + 4;
1338 op = rs6000_fetch_instruction (pc);
1339 if ((op & 0xffff0000) != 0x3c000000)
1340 break;
1341
1342 pc = pc + 4;
1343 op = rs6000_fetch_instruction (pc);
1344 /* [possibly ori 0,0,<some immediate>] */
1345 if ((op & 0xffff0000) == 0x60000000)
1346 {
1347 pc = pc + 4;
1348 op = rs6000_fetch_instruction (pc);
1349 }
1350 /* add 0,12,0 */
1351 if (op != 0x7c0c0214)
1352 break;
1353
1354 /* cmpw 0,12,0 */
1355 pc = pc + 4;
1356 op = rs6000_fetch_instruction (pc);
1357 if (op != 0x7c0c0000)
1358 break;
1359
1360 /* beq 0,<disp> */
1361 pc = pc + 4;
1362 op = rs6000_fetch_instruction (pc);
1363 if ((op & 0xff9f0001) != 0x41820000)
1364 break;
1365
1366 /* addi 12,12,-<some immediate> */
1367 pc = pc + 4;
1368 op = rs6000_fetch_instruction (pc);
1369 if ((op & 0xffff0000) != 0x398c0000)
1370 break;
1371
1372 /* stw 0,0(12) */
1373 pc = pc + 4;
1374 op = rs6000_fetch_instruction (pc);
1375 if (op != 0x900c0000)
1376 break;
1377
1378 /* b <disp> */
1379 pc = pc + 4;
1380 op = rs6000_fetch_instruction (pc);
1381 if ((op & 0xfc000001) != 0x48000000)
1382 break;
1383
1384 /* [possibly one last probe: stw 0,<some immediate>(12)] */
1385 pc = pc + 4;
1386 op = rs6000_fetch_instruction (pc);
1387 if ((op & 0xffff0000) == 0x900c0000)
1388 {
1389 pc = pc + 4;
1390 op = rs6000_fetch_instruction (pc);
1391 }
1392
1393 /* We found a valid stack-check sequence, return the new PC. */
1394 return pc;
1395 }
1396
1397 /* Third sequence: No probe; instead, a comparizon between the stack size
1398 limit (saved in a run-time global variable) and the current stack
1399 pointer:
1400
1401 addi 0,1,-<some immediate>
1402 lis 12,__gnat_stack_limit@ha
1403 lwz 12,__gnat_stack_limit@l(12)
1404 twllt 0,12
1405
1406 or, with a small variant in the case of a bigger stack frame:
1407 addis 0,1,<some immediate>
1408 addic 0,0,-<some immediate>
1409 lis 12,__gnat_stack_limit@ha
1410 lwz 12,__gnat_stack_limit@l(12)
1411 twllt 0,12
1412 */
1413 while (1)
1414 {
1415 /* addi 0,1,-<some immediate> */
1416 if ((op & 0xffff0000) != 0x38010000)
1417 {
1418 /* small stack frame variant not recognized; try the
1419 big stack frame variant: */
1420
1421 /* addis 0,1,<some immediate> */
1422 if ((op & 0xffff0000) != 0x3c010000)
1423 break;
1424
1425 /* addic 0,0,-<some immediate> */
1426 pc = pc + 4;
1427 op = rs6000_fetch_instruction (pc);
1428 if ((op & 0xffff0000) != 0x30000000)
1429 break;
1430 }
1431
1432 /* lis 12,<some immediate> */
1433 pc = pc + 4;
1434 op = rs6000_fetch_instruction (pc);
1435 if ((op & 0xffff0000) != 0x3d800000)
1436 break;
1437
1438 /* lwz 12,<some immediate>(12) */
1439 pc = pc + 4;
1440 op = rs6000_fetch_instruction (pc);
1441 if ((op & 0xffff0000) != 0x818c0000)
1442 break;
1443
1444 /* twllt 0,12 */
1445 pc = pc + 4;
1446 op = rs6000_fetch_instruction (pc);
1447 if ((op & 0xfffffffe) != 0x7c406008)
1448 break;
1449
1450 /* We found a valid stack-check sequence, return the new PC. */
1451 return pc;
1452 }
1453
1454 /* No stack check code in our prologue, return the start_pc. */
1455 return start_pc;
1456}
1457
6a16c029
TJB		 1458/* return pc value after skipping a function prologue and also return
1459 information about a function frame.
1460
1461 in struct rs6000_framedata fdata:
1462 - frameless is TRUE, if function does not have a frame.
1463 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1464 - offset is the initial size of this stack frame --- the amount by
1465 which we decrement the sp to allocate the frame.
1466 - saved_gpr is the number of the first saved gpr.
1467 - saved_fpr is the number of the first saved fpr.
1468 - saved_vr is the number of the first saved vr.
1469 - saved_ev is the number of the first saved ev.
1470 - alloca_reg is the number of the register used for alloca() handling.
1471 Otherwise -1.
1472 - gpr_offset is the offset of the first saved gpr from the previous frame.
1473 - fpr_offset is the offset of the first saved fpr from the previous frame.
1474 - vr_offset is the offset of the first saved vr from the previous frame.
1475 - ev_offset is the offset of the first saved ev from the previous frame.
1476 - lr_offset is the offset of the saved lr
1477 - cr_offset is the offset of the saved cr
1478 - vrsave_offset is the offset of the saved vrsave register
1479 */
1480
7a78ae4e 1481static CORE_ADDR
be8626e0
MD		 1482skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc,
1483 struct rs6000_framedata *fdata)
c906108c
SS		 1484{
1485 CORE_ADDR orig_pc = pc;
55d05f3b 1486 CORE_ADDR last_prologue_pc = pc;
6be8bc0c 1487 CORE_ADDR li_found_pc = 0;
50fd1280 1488 gdb_byte buf[4];
c906108c
SS		 1489 unsigned long op;
1490 long offset = 0;
6be8bc0c 1491 long vr_saved_offset = 0;
482ca3f5
KB		 1492 int lr_reg = -1;
1493 int cr_reg = -1;
6be8bc0c 1494 int vr_reg = -1;
96ff0de4
EZ		 1495 int ev_reg = -1;
1496 long ev_offset = 0;
6be8bc0c 1497 int vrsave_reg = -1;
c906108c
SS		 1498 int reg;
1499 int framep = 0;
1500 int minimal_toc_loaded = 0;
ddb20c56 1501 int prev_insn_was_prologue_insn = 1;
55d05f3b 1502 int num_skip_non_prologue_insns = 0;
773df3e5 1503 int r0_contains_arg = 0;
be8626e0
MD		 1504 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch);
1505 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
c906108c 1506
ddb20c56 1507 memset (fdata, 0, sizeof (struct rs6000_framedata));
c906108c
SS		 1508 fdata->saved_gpr = -1;
1509 fdata->saved_fpr = -1;
6be8bc0c 1510 fdata->saved_vr = -1;
96ff0de4 1511 fdata->saved_ev = -1;
c906108c
SS		 1512 fdata->alloca_reg = -1;
1513 fdata->frameless = 1;
1514 fdata->nosavedpc = 1;
46a9b8ed 1515 fdata->lr_register = -1;
c906108c 1516
de9f48f0
JG		 1517 pc = rs6000_skip_stack_check (pc);
1518 if (pc >= lim_pc)
1519 pc = lim_pc;
1520
55d05f3b 1521 for (;; pc += 4)
c906108c 1522 {
ddb20c56
KB		 1523 /* Sometimes it isn't clear if an instruction is a prologue
1524 instruction or not. When we encounter one of these ambiguous
1525 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1526 Otherwise, we'll assume that it really is a prologue instruction. */
1527 if (prev_insn_was_prologue_insn)
1528 last_prologue_pc = pc;
55d05f3b
KB		 1529
1530 /* Stop scanning if we've hit the limit. */
4e463ff5 1531 if (pc >= lim_pc)
55d05f3b
KB		 1532 break;
1533
ddb20c56
KB		 1534 prev_insn_was_prologue_insn = 1;
1535
55d05f3b 1536 /* Fetch the instruction and convert it to an integer. */
ddb20c56
KB		 1537 if (target_read_memory (pc, buf, 4))
1538 break;
4e463ff5 1539 op = extract_unsigned_integer (buf, 4);
c906108c 1540
c5aa993b
JM		 1541 if ((op & 0xfc1fffff) == 0x7c0802a6)
1542 { /* mflr Rx */
43b1ab88
AC		 1543 /* Since shared library / PIC code, which needs to get its
1544 address at runtime, can appear to save more than one link
1545 register vis:
1546
1547 *INDENT-OFF*
1548 stwu r1,-304(r1)
1549 mflr r3
1550 bl 0xff570d0 (blrl)
1551 stw r30,296(r1)
1552 mflr r30
1553 stw r31,300(r1)
1554 stw r3,308(r1);
1555 ...
1556 *INDENT-ON*
1557
1558 remember just the first one, but skip over additional
1559 ones. */
721d14ba 1560 if (lr_reg == -1)
46a9b8ed 1561 lr_reg = (op & 0x03e00000) >> 21;
773df3e5
JB		 1562 if (lr_reg == 0)
1563 r0_contains_arg = 0;
c5aa993b 1564 continue;
c5aa993b
JM		 1565 }
1566 else if ((op & 0xfc1fffff) == 0x7c000026)
1567 { /* mfcr Rx */
98f08d3d 1568 cr_reg = (op & 0x03e00000);
773df3e5
JB		 1569 if (cr_reg == 0)
1570 r0_contains_arg = 0;
c5aa993b 1571 continue;
c906108c 1572
c906108c 1573 }
c5aa993b
JM		 1574 else if ((op & 0xfc1f0000) == 0xd8010000)
1575 { /* stfd Rx,NUM(r1) */
1576 reg = GET_SRC_REG (op);
1577 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1578 {
1579 fdata->saved_fpr = reg;
1580 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1581 }
1582 continue;
c906108c 1583
c5aa993b
JM		 1584 }
1585 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
7a78ae4e
ND		 1586 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1587 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1588 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
c5aa993b
JM		 1589 {
1590
1591 reg = GET_SRC_REG (op);
46a9b8ed
DJ		 1592 if ((op & 0xfc1f0000) == 0xbc010000)
1593 fdata->gpr_mask |= ~((1U << reg) - 1);
1594 else
1595 fdata->gpr_mask |= 1U << reg;
c5aa993b
JM		 1596 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1597 {
1598 fdata->saved_gpr = reg;
7a78ae4e 1599 if ((op & 0xfc1f0003) == 0xf8010000)
98f08d3d 1600 op &= ~3UL;
c5aa993b
JM		 1601 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1602 }
1603 continue;
c906108c 1604
ddb20c56
KB		 1605 }
1606 else if ((op & 0xffff0000) == 0x60000000)
1607 {
96ff0de4 1608 /* nop */
ddb20c56
KB		 1609 /* Allow nops in the prologue, but do not consider them to
1610 be part of the prologue unless followed by other prologue
1611 instructions. */
1612 prev_insn_was_prologue_insn = 0;
1613 continue;
1614
c906108c 1615 }
c5aa993b
JM		 1616 else if ((op & 0xffff0000) == 0x3c000000)
1617 { /* addis 0,0,NUM, used
1618 for >= 32k frames */
1619 fdata->offset = (op & 0x0000ffff) << 16;
1620 fdata->frameless = 0;
773df3e5 1621 r0_contains_arg = 0;
c5aa993b
JM		 1622 continue;
1623
1624 }
1625 else if ((op & 0xffff0000) == 0x60000000)
1626 { /* ori 0,0,NUM, 2nd ha
1627 lf of >= 32k frames */
1628 fdata->offset |= (op & 0x0000ffff);
1629 fdata->frameless = 0;
773df3e5 1630 r0_contains_arg = 0;
c5aa993b
JM		 1631 continue;
1632
1633 }
be723e22 1634 else if (lr_reg >= 0 &&
98f08d3d
KB		 1635 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1636 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1637 /* stw Rx, NUM(r1) */
1638 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1639 /* stwu Rx, NUM(r1) */
1640 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1641 { /* where Rx == lr */
1642 fdata->lr_offset = offset;
c5aa993b 1643 fdata->nosavedpc = 0;
be723e22
MS		 1644 /* Invalidate lr_reg, but don't set it to -1.
1645 That would mean that it had never been set. */
1646 lr_reg = -2;
98f08d3d
KB		 1647 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1648 (op & 0xfc000000) == 0x90000000) /* stw */
1649 {
1650 /* Does not update r1, so add displacement to lr_offset. */
1651 fdata->lr_offset += SIGNED_SHORT (op);
1652 }
c5aa993b
JM		 1653 continue;
1654
1655 }
be723e22 1656 else if (cr_reg >= 0 &&
98f08d3d
KB		 1657 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1658 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1659 /* stw Rx, NUM(r1) */
1660 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1661 /* stwu Rx, NUM(r1) */
1662 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1663 { /* where Rx == cr */
1664 fdata->cr_offset = offset;
be723e22
MS		 1665 /* Invalidate cr_reg, but don't set it to -1.
1666 That would mean that it had never been set. */
1667 cr_reg = -2;
98f08d3d
KB		 1668 if ((op & 0xfc000003) == 0xf8000000 ||
1669 (op & 0xfc000000) == 0x90000000)
1670 {
1671 /* Does not update r1, so add displacement to cr_offset. */
1672 fdata->cr_offset += SIGNED_SHORT (op);
1673 }
c5aa993b
JM		 1674 continue;
1675
1676 }
721d14ba
DJ		 1677 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1678 {
1679 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1680 prediction bits. If the LR has already been saved, we can
1681 skip it. */
1682 continue;
1683 }
c5aa993b
JM		 1684 else if (op == 0x48000005)
1685 { /* bl .+4 used in
1686 -mrelocatable */
46a9b8ed 1687 fdata->used_bl = 1;
c5aa993b
JM		 1688 continue;
1689
1690 }
1691 else if (op == 0x48000004)
1692 { /* b .+4 (xlc) */
1693 break;
1694
c5aa993b 1695 }
6be8bc0c
EZ		 1696 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1697 in V.4 -mminimal-toc */
c5aa993b
JM		 1698 (op & 0xffff0000) == 0x3bde0000)
1699 { /* addi 30,30,foo@l */
1700 continue;
c906108c 1701
c5aa993b
JM		 1702 }
1703 else if ((op & 0xfc000001) == 0x48000001)
1704 { /* bl foo,
1705 to save fprs??? */
c906108c 1706
c5aa993b 1707 fdata->frameless = 0;
3c77c82a
DJ		 1708
1709 /* If the return address has already been saved, we can skip
1710 calls to blrl (for PIC). */
1711 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op))
46a9b8ed
DJ		 1712 {
1713 fdata->used_bl = 1;
1714 continue;
1715 }
3c77c82a 1716
6be8bc0c 1717 /* Don't skip over the subroutine call if it is not within
ebd98106
FF		 1718 the first three instructions of the prologue and either
1719 we have no line table information or the line info tells
1720 us that the subroutine call is not part of the line
1721 associated with the prologue. */
c5aa993b 1722 if ((pc - orig_pc) > 8)
ebd98106
FF		 1723 {
1724 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1725 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1726
1727 if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line))
1728 break;
1729 }
c5aa993b
JM		 1730
1731 op = read_memory_integer (pc + 4, 4);
1732
6be8bc0c
EZ		 1733 /* At this point, make sure this is not a trampoline
1734 function (a function that simply calls another functions,
1735 and nothing else). If the next is not a nop, this branch
1736 was part of the function prologue. */
c5aa993b
JM		 1737
1738 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1739 break; /* don't skip over
1740 this branch */
c5aa993b 1741
46a9b8ed
DJ		 1742 fdata->used_bl = 1;
1743 continue;
c5aa993b 1744 }
98f08d3d
KB		 1745 /* update stack pointer */
1746 else if ((op & 0xfc1f0000) == 0x94010000)
1747 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
c5aa993b
JM		 1748 fdata->frameless = 0;
1749 fdata->offset = SIGNED_SHORT (op);
1750 offset = fdata->offset;
1751 continue;
c5aa993b 1752 }
98f08d3d
KB		 1753 else if ((op & 0xfc1f016a) == 0x7c01016e)
1754 { /* stwux rX,r1,rY */
1755 /* no way to figure out what r1 is going to be */
1756 fdata->frameless = 0;
1757 offset = fdata->offset;
1758 continue;
1759 }
1760 else if ((op & 0xfc1f0003) == 0xf8010001)
1761 { /* stdu rX,NUM(r1) */
1762 fdata->frameless = 0;
1763 fdata->offset = SIGNED_SHORT (op & ~3UL);
1764 offset = fdata->offset;
1765 continue;
1766 }
1767 else if ((op & 0xfc1f016a) == 0x7c01016a)
1768 { /* stdux rX,r1,rY */
1769 /* no way to figure out what r1 is going to be */
c5aa993b
JM		 1770 fdata->frameless = 0;
1771 offset = fdata->offset;
1772 continue;
c5aa993b 1773 }
7313566f
FF		 1774 else if ((op & 0xffff0000) == 0x38210000)
1775 { /* addi r1,r1,SIMM */
1776 fdata->frameless = 0;
1777 fdata->offset += SIGNED_SHORT (op);
1778 offset = fdata->offset;
1779 continue;
1780 }
4e463ff5
DJ		 1781 /* Load up minimal toc pointer. Do not treat an epilogue restore
1782 of r31 as a minimal TOC load. */
98f08d3d
KB		 1783 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1784 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
4e463ff5 1785 && !framep
c5aa993b 1786 && !minimal_toc_loaded)
98f08d3d 1787 {
c5aa993b
JM		 1788 minimal_toc_loaded = 1;
1789 continue;
1790
f6077098
KB		 1791 /* move parameters from argument registers to local variable
1792 registers */
1793 }
1794 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1795 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1796 (((op >> 21) & 31) <= 10) &&
96ff0de4 1797 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
f6077098
KB		 1798 {
1799 continue;
1800
c5aa993b
JM		 1801 /* store parameters in stack */
1802 }
e802b915 1803 /* Move parameters from argument registers to temporary register. */
773df3e5 1804 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
e802b915 1805 {
c5aa993b
JM		 1806 continue;
1807
1808 /* Set up frame pointer */
1809 }
1810 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1811 || op == 0x7c3f0b78)
1812 { /* mr r31, r1 */
1813 fdata->frameless = 0;
1814 framep = 1;
6f99cb26 1815 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
c5aa993b
JM		 1816 continue;
1817
1818 /* Another way to set up the frame pointer. */
1819 }
1820 else if ((op & 0xfc1fffff) == 0x38010000)
1821 { /* addi rX, r1, 0x0 */
1822 fdata->frameless = 0;
1823 framep = 1;
6f99cb26
AC		 1824 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1825 + ((op & ~0x38010000) >> 21));
c5aa993b 1826 continue;
c5aa993b 1827 }
6be8bc0c
EZ		 1828 /* AltiVec related instructions. */
1829 /* Store the vrsave register (spr 256) in another register for
1830 later manipulation, or load a register into the vrsave
1831 register. 2 instructions are used: mfvrsave and
1832 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1833 and mtspr SPR256, Rn. */
1834 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1835 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1836 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1837 {
1838 vrsave_reg = GET_SRC_REG (op);
1839 continue;
1840 }
1841 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1842 {
1843 continue;
1844 }
1845 /* Store the register where vrsave was saved to onto the stack:
1846 rS is the register where vrsave was stored in a previous
1847 instruction. */
1848 /* 100100 sssss 00001 dddddddd dddddddd */
1849 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1850 {
1851 if (vrsave_reg == GET_SRC_REG (op))
1852 {
1853 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1854 vrsave_reg = -1;
1855 }
1856 continue;
1857 }
1858 /* Compute the new value of vrsave, by modifying the register
1859 where vrsave was saved to. */
1860 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1861 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1862 {
1863 continue;
1864 }
1865 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1866 in a pair of insns to save the vector registers on the
1867 stack. */
1868 /* 001110 00000 00000 iiii iiii iiii iiii */
96ff0de4
EZ		 1869 /* 001110 01110 00000 iiii iiii iiii iiii */
1870 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1871 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
6be8bc0c 1872 {
773df3e5
JB		 1873 if ((op & 0xffff0000) == 0x38000000)
1874 r0_contains_arg = 0;
6be8bc0c
EZ		 1875 li_found_pc = pc;
1876 vr_saved_offset = SIGNED_SHORT (op);
773df3e5
JB		 1877
1878 /* This insn by itself is not part of the prologue, unless
1879 if part of the pair of insns mentioned above. So do not
1880 record this insn as part of the prologue yet. */
1881 prev_insn_was_prologue_insn = 0;
6be8bc0c
EZ		 1882 }
1883 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1884 /* 011111 sssss 11111 00000 00111001110 */
1885 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1886 {
1887 if (pc == (li_found_pc + 4))
1888 {
1889 vr_reg = GET_SRC_REG (op);
1890 /* If this is the first vector reg to be saved, or if
1891 it has a lower number than others previously seen,
1892 reupdate the frame info. */
1893 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1894 {
1895 fdata->saved_vr = vr_reg;
1896 fdata->vr_offset = vr_saved_offset + offset;
1897 }
1898 vr_saved_offset = -1;
1899 vr_reg = -1;
1900 li_found_pc = 0;
1901 }
1902 }
1903 /* End AltiVec related instructions. */
96ff0de4
EZ		 1904
1905 /* Start BookE related instructions. */
1906 /* Store gen register S at (r31+uimm).
1907 Any register less than r13 is volatile, so we don't care. */
1908 /* 000100 sssss 11111 iiiii 01100100001 */
1909 else if (arch_info->mach == bfd_mach_ppc_e500
1910 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1911 {
1912 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1913 {
1914 unsigned int imm;
1915 ev_reg = GET_SRC_REG (op);
1916 imm = (op >> 11) & 0x1f;
1917 ev_offset = imm * 8;
1918 /* If this is the first vector reg to be saved, or if
1919 it has a lower number than others previously seen,
1920 reupdate the frame info. */
1921 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1922 {
1923 fdata->saved_ev = ev_reg;
1924 fdata->ev_offset = ev_offset + offset;
1925 }
1926 }
1927 continue;
1928 }
1929 /* Store gen register rS at (r1+rB). */
1930 /* 000100 sssss 00001 bbbbb 01100100000 */
1931 else if (arch_info->mach == bfd_mach_ppc_e500
1932 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1933 {
1934 if (pc == (li_found_pc + 4))
1935 {
1936 ev_reg = GET_SRC_REG (op);
1937 /* If this is the first vector reg to be saved, or if
1938 it has a lower number than others previously seen,
1939 reupdate the frame info. */
1940 /* We know the contents of rB from the previous instruction. */
1941 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1942 {
1943 fdata->saved_ev = ev_reg;
1944 fdata->ev_offset = vr_saved_offset + offset;
1945 }
1946 vr_saved_offset = -1;
1947 ev_reg = -1;
1948 li_found_pc = 0;
1949 }
1950 continue;
1951 }
1952 /* Store gen register r31 at (rA+uimm). */
1953 /* 000100 11111 aaaaa iiiii 01100100001 */
1954 else if (arch_info->mach == bfd_mach_ppc_e500
1955 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1956 {
1957 /* Wwe know that the source register is 31 already, but
1958 it can't hurt to compute it. */
1959 ev_reg = GET_SRC_REG (op);
1960 ev_offset = ((op >> 11) & 0x1f) * 8;
1961 /* If this is the first vector reg to be saved, or if
1962 it has a lower number than others previously seen,
1963 reupdate the frame info. */
1964 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1965 {
1966 fdata->saved_ev = ev_reg;
1967 fdata->ev_offset = ev_offset + offset;
1968 }
1969
1970 continue;
1971 }
1972 /* Store gen register S at (r31+r0).
1973 Store param on stack when offset from SP bigger than 4 bytes. */
1974 /* 000100 sssss 11111 00000 01100100000 */
1975 else if (arch_info->mach == bfd_mach_ppc_e500
1976 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1977 {
1978 if (pc == (li_found_pc + 4))
1979 {
1980 if ((op & 0x03e00000) >= 0x01a00000)
1981 {
1982 ev_reg = GET_SRC_REG (op);
1983 /* If this is the first vector reg to be saved, or if
1984 it has a lower number than others previously seen,
1985 reupdate the frame info. */
1986 /* We know the contents of r0 from the previous
1987 instruction. */
1988 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1989 {
1990 fdata->saved_ev = ev_reg;
1991 fdata->ev_offset = vr_saved_offset + offset;
1992 }
1993 ev_reg = -1;
1994 }
1995 vr_saved_offset = -1;
1996 li_found_pc = 0;
1997 continue;
1998 }
1999 }
2000 /* End BookE related instructions. */
2001
c5aa993b
JM		 2002 else
2003 {
46a9b8ed
DJ		 2004 unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1);
2005
55d05f3b
KB		 2006 /* Not a recognized prologue instruction.
2007 Handle optimizer code motions into the prologue by continuing
2008 the search if we have no valid frame yet or if the return
46a9b8ed
DJ		 2009 address is not yet saved in the frame. Also skip instructions
2010 if some of the GPRs expected to be saved are not yet saved. */
2011 if (fdata->frameless == 0 && fdata->nosavedpc == 0
2012 && (fdata->gpr_mask & all_mask) == all_mask)
55d05f3b
KB		 2013 break;
2014
2015 if (op == 0x4e800020 /* blr */
2016 || op == 0x4e800420) /* bctr */
2017 /* Do not scan past epilogue in frameless functions or
2018 trampolines. */
2019 break;
2020 if ((op & 0xf4000000) == 0x40000000) /* bxx */
64366f1c 2021 /* Never skip branches. */
55d05f3b
KB		 2022 break;
2023
2024 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
2025 /* Do not scan too many insns, scanning insns is expensive with
2026 remote targets. */
2027 break;
2028
2029 /* Continue scanning. */
2030 prev_insn_was_prologue_insn = 0;
2031 continue;
c5aa993b 2032 }
c906108c
SS		 2033 }
2034
2035#if 0
2036/* I have problems with skipping over __main() that I need to address
2037 * sometime. Previously, I used to use misc_function_vector which
2038 * didn't work as well as I wanted to be. -MGO */
2039
2040 /* If the first thing after skipping a prolog is a branch to a function,
2041 this might be a call to an initializer in main(), introduced by gcc2.
64366f1c 2042 We'd like to skip over it as well. Fortunately, xlc does some extra
c906108c 2043 work before calling a function right after a prologue, thus we can
64366f1c 2044 single out such gcc2 behaviour. */
c906108c 2045
c906108c 2046
c5aa993b
JM		 2047 if ((op & 0xfc000001) == 0x48000001)
2048 { /* bl foo, an initializer function? */
2049 op = read_memory_integer (pc + 4, 4);
2050
2051 if (op == 0x4def7b82)
2052 { /* cror 0xf, 0xf, 0xf (nop) */
c906108c 2053
64366f1c
EZ		 2054 /* Check and see if we are in main. If so, skip over this
2055 initializer function as well. */
c906108c 2056
c5aa993b 2057 tmp = find_pc_misc_function (pc);
6314a349
AC		 2058 if (tmp >= 0
2059 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
c5aa993b
JM		 2060 return pc + 8;
2061 }
c906108c 2062 }
c906108c 2063#endif /* 0 */
c5aa993b 2064
46a9b8ed
DJ		 2065 if (pc == lim_pc && lr_reg >= 0)
2066 fdata->lr_register = lr_reg;
2067
c5aa993b 2068 fdata->offset = -fdata->offset;
ddb20c56 2069 return last_prologue_pc;
c906108c
SS		 2070}
2071
7a78ae4e 2072static CORE_ADDR
4a7622d1 2073rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
c906108c 2074{
4a7622d1
UW		 2075 struct rs6000_framedata frame;
2076 CORE_ADDR limit_pc, func_addr;
c906108c 2077
4a7622d1
UW		 2078 /* See if we can determine the end of the prologue via the symbol table.
2079 If so, then return either PC, or the PC after the prologue, whichever
2080 is greater. */
2081 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
c5aa993b 2082 {
4a7622d1
UW		 2083 CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr);
2084 if (post_prologue_pc != 0)
2085 return max (pc, post_prologue_pc);
c906108c 2086 }
c906108c 2087
4a7622d1
UW		 2088 /* Can't determine prologue from the symbol table, need to examine
2089 instructions. */
c906108c 2090
4a7622d1
UW		 2091 /* Find an upper limit on the function prologue using the debug
2092 information. If the debug information could not be used to provide
2093 that bound, then use an arbitrary large number as the upper bound. */
2094 limit_pc = skip_prologue_using_sal (pc);
2095 if (limit_pc == 0)
2096 limit_pc = pc + 100; /* Magic. */
794a477a 2097
4a7622d1
UW		 2098 pc = skip_prologue (gdbarch, pc, limit_pc, &frame);
2099 return pc;
c906108c 2100}
c906108c 2101
8ab3d180
KB		 2102/* When compiling for EABI, some versions of GCC emit a call to __eabi
2103 in the prologue of main().
2104
2105 The function below examines the code pointed at by PC and checks to
2106 see if it corresponds to a call to __eabi. If so, it returns the
2107 address of the instruction following that call. Otherwise, it simply
2108 returns PC. */
2109
2110CORE_ADDR
2111rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2112{
2113 gdb_byte buf[4];
2114 unsigned long op;
2115
2116 if (target_read_memory (pc, buf, 4))
2117 return pc;
2118 op = extract_unsigned_integer (buf, 4);
2119
2120 if ((op & BL_MASK) == BL_INSTRUCTION)
2121 {
2122 CORE_ADDR displ = op & BL_DISPLACEMENT_MASK;
2123 CORE_ADDR call_dest = pc + 4 + displ;
2124 struct minimal_symbol *s = lookup_minimal_symbol_by_pc (call_dest);
2125
2126 /* We check for ___eabi (three leading underscores) in addition
2127 to __eabi in case the GCC option "-fleading-underscore" was
2128 used to compile the program. */
2129 if (s != NULL
2130 && SYMBOL_LINKAGE_NAME (s) != NULL
2131 && (strcmp (SYMBOL_LINKAGE_NAME (s), "__eabi") == 0
2132 || strcmp (SYMBOL_LINKAGE_NAME (s), "___eabi") == 0))
2133 pc += 4;
2134 }
2135 return pc;
2136}
383f0f5b 2137
4a7622d1
UW		 2138/* All the ABI's require 16 byte alignment. */
2139static CORE_ADDR
2140rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2141{
2142 return (addr & -16);
c906108c
SS		 2143}
2144
977adac5
ND		 2145/* Return whether handle_inferior_event() should proceed through code
2146 starting at PC in function NAME when stepping.
2147
2148 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2149 handle memory references that are too distant to fit in instructions
2150 generated by the compiler. For example, if 'foo' in the following
2151 instruction:
2152
2153 lwz r9,foo(r2)
2154
2155 is greater than 32767, the linker might replace the lwz with a branch to
2156 somewhere in @FIX1 that does the load in 2 instructions and then branches
2157 back to where execution should continue.
2158
2159 GDB should silently step over @FIX code, just like AIX dbx does.
2ec664f5
MS		 2160 Unfortunately, the linker uses the "b" instruction for the
2161 branches, meaning that the link register doesn't get set.
2162 Therefore, GDB's usual step_over_function () mechanism won't work.
977adac5 2163
e76f05fa
UW		 2164 Instead, use the gdbarch_skip_trampoline_code and
2165 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2ec664f5 2166 @FIX code. */
977adac5
ND		 2167
2168int
2169rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
2170{
2171 return name && !strncmp (name, "@FIX", 4);
2172}
2173
2174/* Skip code that the user doesn't want to see when stepping:
2175
2176 1. Indirect function calls use a piece of trampoline code to do context
2177 switching, i.e. to set the new TOC table. Skip such code if we are on
2178 its first instruction (as when we have single-stepped to here).
2179
2180 2. Skip shared library trampoline code (which is different from
c906108c 2181 indirect function call trampolines).
977adac5
ND		 2182
2183 3. Skip bigtoc fixup code.
2184
c906108c 2185 Result is desired PC to step until, or NULL if we are not in
977adac5 2186 code that should be skipped. */
c906108c
SS		 2187
2188CORE_ADDR
52f729a7 2189rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
c906108c 2190{
4a7622d1 2191 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
52f0bd74 2192 unsigned int ii, op;
977adac5 2193 int rel;
c906108c 2194 CORE_ADDR solib_target_pc;
977adac5 2195 struct minimal_symbol *msymbol;
c906108c 2196
c5aa993b
JM		 2197 static unsigned trampoline_code[] =
2198 {
2199 0x800b0000, /* l r0,0x0(r11) */
2200 0x90410014, /* st r2,0x14(r1) */
2201 0x7c0903a6, /* mtctr r0 */
2202 0x804b0004, /* l r2,0x4(r11) */
2203 0x816b0008, /* l r11,0x8(r11) */
2204 0x4e800420, /* bctr */
2205 0x4e800020, /* br */
2206 0
c906108c
SS		 2207 };
2208
977adac5
ND		 2209 /* Check for bigtoc fixup code. */
2210 msymbol = lookup_minimal_symbol_by_pc (pc);
2ec664f5 2211 if (msymbol
4a7622d1 2212 && rs6000_in_solib_return_trampoline (pc, SYMBOL_LINKAGE_NAME (msymbol)))
977adac5
ND		 2213 {
2214 /* Double-check that the third instruction from PC is relative "b". */
2215 op = read_memory_integer (pc + 8, 4);
2216 if ((op & 0xfc000003) == 0x48000000)
2217 {
2218 /* Extract bits 6-29 as a signed 24-bit relative word address and
2219 add it to the containing PC. */
2220 rel = ((int)(op << 6) >> 6);
2221 return pc + 8 + rel;
2222 }
2223 }
2224
c906108c 2225 /* If pc is in a shared library trampoline, return its target. */
52f729a7 2226 solib_target_pc = find_solib_trampoline_target (frame, pc);
c906108c
SS		 2227 if (solib_target_pc)
2228 return solib_target_pc;
2229
c5aa993b
JM		 2230 for (ii = 0; trampoline_code[ii]; ++ii)
2231 {
2232 op = read_memory_integer (pc + (ii * 4), 4);
2233 if (op != trampoline_code[ii])
2234 return 0;
2235 }
52f729a7 2236 ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination addr */
4a7622d1 2237 pc = read_memory_unsigned_integer (ii, tdep->wordsize); /* (r11) value */
c906108c
SS		 2238 return pc;
2239}
2240
794ac428
UW		 2241/* ISA-specific vector types. */
2242
2243static struct type *
2244rs6000_builtin_type_vec64 (struct gdbarch *gdbarch)
2245{
2246 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2247
2248 if (!tdep->ppc_builtin_type_vec64)
2249 {
2250 /* The type we're building is this: */
2251#if 0
2252 union __gdb_builtin_type_vec64
2253 {
2254 int64_t uint64;
2255 float v2_float[2];
2256 int32_t v2_int32[2];
2257 int16_t v4_int16[4];
2258 int8_t v8_int8[8];
2259 };
2260#endif
2261
2262 struct type *t;
2263
2264 t = init_composite_type ("__ppc_builtin_type_vec64", TYPE_CODE_UNION);
2265 append_composite_type_field (t, "uint64", builtin_type_int64);
2266 append_composite_type_field (t, "v2_float",
0dfff4cb
UW		 2267 init_vector_type (builtin_type (gdbarch)
2268 ->builtin_float, 2));
794ac428
UW		 2269 append_composite_type_field (t, "v2_int32",
2270 init_vector_type (builtin_type_int32, 2));
2271 append_composite_type_field (t, "v4_int16",
2272 init_vector_type (builtin_type_int16, 4));
2273 append_composite_type_field (t, "v8_int8",
2274 init_vector_type (builtin_type_int8, 8));
2275
876cecd0 2276 TYPE_VECTOR (t) = 1;
794ac428
UW		 2277 TYPE_NAME (t) = "ppc_builtin_type_vec64";
2278 tdep->ppc_builtin_type_vec64 = t;
2279 }
2280
2281 return tdep->ppc_builtin_type_vec64;
2282}
2283
604c2f83
LM		 2284/* Vector 128 type. */
2285
2286static struct type *
2287rs6000_builtin_type_vec128 (struct gdbarch *gdbarch)
2288{
2289 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2290
2291 if (!tdep->ppc_builtin_type_vec128)
2292 {
2293 /* The type we're building is this
2294
2295 type = union __ppc_builtin_type_vec128 {
2296 uint128_t uint128;
2297 float v4_float[4];
2298 int32_t v4_int32[4];
2299 int16_t v8_int16[8];
2300 int8_t v16_int8[16];
2301 }
2302 */
2303
2304 struct type *t;
2305
2306 t = init_composite_type ("__ppc_builtin_type_vec128", TYPE_CODE_UNION);
2307 append_composite_type_field (t, "uint128", builtin_type_uint128);
2308 append_composite_type_field (t, "v4_float",
2309 init_vector_type (builtin_type (gdbarch)->builtin_float, 4));
2310 append_composite_type_field (t, "v4_int32",
2311 init_vector_type (builtin_type_int32, 4));
2312 append_composite_type_field (t, "v8_int16",
2313 init_vector_type (builtin_type_int16, 8));
2314 append_composite_type_field (t, "v16_int8",
2315 init_vector_type (builtin_type_int8, 16));
2316
803e1097 2317 TYPE_VECTOR (t) = 1;
604c2f83
LM		 2318 TYPE_NAME (t) = "ppc_builtin_type_vec128";
2319 tdep->ppc_builtin_type_vec128 = t;
2320 }
2321
2322 return tdep->ppc_builtin_type_vec128;
2323}
2324
7cc46491
DJ		 2325/* Return the name of register number REGNO, or the empty string if it
2326 is an anonymous register. */
7a78ae4e 2327
fa88f677 2328static const char *
d93859e2 2329rs6000_register_name (struct gdbarch *gdbarch, int regno)
7a78ae4e 2330{
d93859e2 2331 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7a78ae4e 2332
7cc46491
DJ		 2333 /* The upper half "registers" have names in the XML description,
2334 but we present only the low GPRs and the full 64-bit registers
2335 to the user. */
2336 if (tdep->ppc_ev0_upper_regnum >= 0
2337 && tdep->ppc_ev0_upper_regnum <= regno
2338 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
2339 return "";
2340
604c2f83
LM		 2341 /* Hide the upper halves of the vs0~vs31 registers. */
2342 if (tdep->ppc_vsr0_regnum >= 0
2343 && tdep->ppc_vsr0_upper_regnum <= regno
2344 && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs)
2345 return "";
2346
7cc46491 2347 /* Check if the SPE pseudo registers are available. */
5a9e69ba 2348 if (IS_SPE_PSEUDOREG (tdep, regno))
7cc46491
DJ		 2349 {
2350 static const char *const spe_regnames[] = {
2351 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2352 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2353 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2354 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2355 };
2356 return spe_regnames[regno - tdep->ppc_ev0_regnum];
2357 }
2358
f949c649
TJB		 2359 /* Check if the decimal128 pseudo-registers are available. */
2360 if (IS_DFP_PSEUDOREG (tdep, regno))
2361 {
2362 static const char *const dfp128_regnames[] = {
2363 "dl0", "dl1", "dl2", "dl3",
2364 "dl4", "dl5", "dl6", "dl7",
2365 "dl8", "dl9", "dl10", "dl11",
2366 "dl12", "dl13", "dl14", "dl15"
2367 };
2368 return dfp128_regnames[regno - tdep->ppc_dl0_regnum];
2369 }
2370
604c2f83
LM		 2371 /* Check if this is a VSX pseudo-register. */
2372 if (IS_VSX_PSEUDOREG (tdep, regno))
2373 {
2374 static const char *const vsx_regnames[] = {
2375 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2376 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2377 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2378 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2379 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2380 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2381 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2382 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2383 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2384 };
2385 return vsx_regnames[regno - tdep->ppc_vsr0_regnum];
2386 }
2387
2388 /* Check if the this is a Extended FP pseudo-register. */
2389 if (IS_EFP_PSEUDOREG (tdep, regno))
2390 {
2391 static const char *const efpr_regnames[] = {
2392 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2393 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2394 "f46", "f47", "f48", "f49", "f50", "f51",
2395 "f52", "f53", "f54", "f55", "f56", "f57",
2396 "f58", "f59", "f60", "f61", "f62", "f63"
2397 };
2398 return efpr_regnames[regno - tdep->ppc_efpr0_regnum];
2399 }
2400
d93859e2 2401 return tdesc_register_name (gdbarch, regno);
7a78ae4e
ND		 2402}
2403
7cc46491
DJ		 2404/* Return the GDB type object for the "standard" data type of data in
2405 register N. */
7a78ae4e
ND		 2406
2407static struct type *
7cc46491 2408rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
7a78ae4e 2409{
691d145a 2410 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7a78ae4e 2411
7cc46491 2412 /* These are the only pseudo-registers we support. */
f949c649 2413 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
604c2f83
LM		 2414 || IS_DFP_PSEUDOREG (tdep, regnum)
2415 || IS_VSX_PSEUDOREG (tdep, regnum)
2416 || IS_EFP_PSEUDOREG (tdep, regnum));
7cc46491 2417
f949c649
TJB		 2418 /* These are the e500 pseudo-registers. */
2419 if (IS_SPE_PSEUDOREG (tdep, regnum))
2420 return rs6000_builtin_type_vec64 (gdbarch);
604c2f83
LM		 2421 else if (IS_DFP_PSEUDOREG (tdep, regnum))
2422 /* PPC decimal128 pseudo-registers. */
f949c649 2423 return builtin_type (gdbarch)->builtin_declong;
604c2f83
LM		 2424 else if (IS_VSX_PSEUDOREG (tdep, regnum))
2425 /* POWER7 VSX pseudo-registers. */
2426 return rs6000_builtin_type_vec128 (gdbarch);
2427 else
2428 /* POWER7 Extended FP pseudo-registers. */
2429 return builtin_type (gdbarch)->builtin_double;
7a78ae4e
ND		 2430}
2431
c44ca51c
AC		 2432/* Is REGNUM a member of REGGROUP? */
2433static int
7cc46491
DJ		 2434rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2435 struct reggroup *group)
c44ca51c
AC		 2436{
2437 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
c44ca51c 2438
7cc46491 2439 /* These are the only pseudo-registers we support. */
f949c649 2440 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
604c2f83
LM		 2441 || IS_DFP_PSEUDOREG (tdep, regnum)
2442 || IS_VSX_PSEUDOREG (tdep, regnum)
2443 || IS_EFP_PSEUDOREG (tdep, regnum));
c44ca51c 2444
604c2f83
LM		 2445 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2446 if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum))
f949c649 2447 return group == all_reggroup || group == vector_reggroup;
7cc46491 2448 else
604c2f83 2449 /* PPC decimal128 or Extended FP pseudo-registers. */
f949c649 2450 return group == all_reggroup || group == float_reggroup;
c44ca51c
AC		 2451}
2452
691d145a 2453/* The register format for RS/6000 floating point registers is always
64366f1c 2454 double, we need a conversion if the memory format is float. */
7a78ae4e
ND		 2455
2456static int
0abe36f5
MD		 2457rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum,
2458 struct type *type)
7a78ae4e 2459{
0abe36f5 2460 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7cc46491
DJ		 2461
2462 return (tdep->ppc_fp0_regnum >= 0
2463 && regnum >= tdep->ppc_fp0_regnum
2464 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs
2465 && TYPE_CODE (type) == TYPE_CODE_FLT
0dfff4cb
UW		 2466 && TYPE_LENGTH (type)
2467 != TYPE_LENGTH (builtin_type (gdbarch)->builtin_double));
7a78ae4e
ND		 2468}
2469
7a78ae4e 2470static void
691d145a
JB		 2471rs6000_register_to_value (struct frame_info *frame,
2472 int regnum,
2473 struct type *type,
50fd1280 2474 gdb_byte *to)
7a78ae4e 2475{
0dfff4cb 2476 struct gdbarch *gdbarch = get_frame_arch (frame);
50fd1280 2477 gdb_byte from[MAX_REGISTER_SIZE];
691d145a 2478
691d145a 2479 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
7a78ae4e 2480
691d145a 2481 get_frame_register (frame, regnum, from);
0dfff4cb
UW		 2482 convert_typed_floating (from, builtin_type (gdbarch)->builtin_double,
2483 to, type);
691d145a 2484}
7a292a7a 2485
7a78ae4e 2486static void
691d145a
JB		 2487rs6000_value_to_register (struct frame_info *frame,
2488 int regnum,
2489 struct type *type,
50fd1280 2490 const gdb_byte *from)
7a78ae4e 2491{
0dfff4cb 2492 struct gdbarch *gdbarch = get_frame_arch (frame);
50fd1280 2493 gdb_byte to[MAX_REGISTER_SIZE];
691d145a 2494
691d145a
JB		 2495 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2496
0dfff4cb
UW		 2497 convert_typed_floating (from, type,
2498 to, builtin_type (gdbarch)->builtin_double);
691d145a 2499 put_frame_register (frame, regnum, to);
7a78ae4e 2500}
c906108c 2501
6ced10dd
JB		 2502/* Move SPE vector register values between a 64-bit buffer and the two
2503 32-bit raw register halves in a regcache. This function handles
2504 both splitting a 64-bit value into two 32-bit halves, and joining
2505 two halves into a whole 64-bit value, depending on the function
2506 passed as the MOVE argument.
2507
2508 EV_REG must be the number of an SPE evN vector register --- a
2509 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2510 64-bit buffer.
2511
2512 Call MOVE once for each 32-bit half of that register, passing
2513 REGCACHE, the number of the raw register corresponding to that
2514 half, and the address of the appropriate half of BUFFER.
2515
2516 For example, passing 'regcache_raw_read' as the MOVE function will
2517 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2518 'regcache_raw_supply' will supply the contents of BUFFER to the
2519 appropriate pair of raw registers in REGCACHE.
2520
2521 You may need to cast away some 'const' qualifiers when passing
2522 MOVE, since this function can't tell at compile-time which of
2523 REGCACHE or BUFFER is acting as the source of the data. If C had
2524 co-variant type qualifiers, ... */
2525static void
2526e500_move_ev_register (void (*move) (struct regcache *regcache,
50fd1280 2527 int regnum, gdb_byte *buf),
6ced10dd 2528 struct regcache *regcache, int ev_reg,
50fd1280 2529 gdb_byte *buffer)
6ced10dd
JB		 2530{
2531 struct gdbarch *arch = get_regcache_arch (regcache);
2532 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2533 int reg_index;
50fd1280 2534 gdb_byte *byte_buffer = buffer;
6ced10dd 2535
5a9e69ba 2536 gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg));
6ced10dd
JB		 2537
2538 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2539
8b164abb 2540 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
6ced10dd
JB		 2541 {
2542 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
2543 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
2544 }
2545 else
2546 {
2547 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2548 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
2549 }
2550}
2551
c8001721
EZ		 2552static void
2553e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
50fd1280 2554 int reg_nr, gdb_byte *buffer)
f949c649
TJB		 2555{
2556 e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
2557}
2558
2559static void
2560e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2561 int reg_nr, const gdb_byte *buffer)
2562{
2563 e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *))
2564 regcache_raw_write,
2565 regcache, reg_nr, (gdb_byte *) buffer);
2566}
2567
604c2f83 2568/* Read method for DFP pseudo-registers. */
f949c649 2569static void
604c2f83 2570dfp_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
f949c649
TJB		 2571 int reg_nr, gdb_byte *buffer)
2572{
2573 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2574 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2575
2576 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2577 {
2578 /* Read two FP registers to form a whole dl register. */
2579 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2580 2 * reg_index, buffer);
2581 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2582 2 * reg_index + 1, buffer + 8);
2583 }
2584 else
2585 {
2586 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2587 2 * reg_index + 1, buffer + 8);
2588 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2589 2 * reg_index, buffer);
2590 }
2591}
2592
604c2f83 2593/* Write method for DFP pseudo-registers. */
f949c649 2594static void
604c2f83 2595dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
f949c649
TJB		 2596 int reg_nr, const gdb_byte *buffer)
2597{
2598 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2599 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2600
2601 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2602 {
2603 /* Write each half of the dl register into a separate
2604 FP register. */
2605 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2606 2 * reg_index, buffer);
2607 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2608 2 * reg_index + 1, buffer + 8);
2609 }
2610 else
2611 {
2612 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2613 2 * reg_index + 1, buffer + 8);
2614 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2615 2 * reg_index, buffer);
2616 }
2617}
2618
604c2f83
LM		 2619/* Read method for POWER7 VSX pseudo-registers. */
2620static void
2621vsx_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2622 int reg_nr, gdb_byte *buffer)
2623{
2624 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2625 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2626
2627 /* Read the portion that overlaps the VMX registers. */
2628 if (reg_index > 31)
2629 regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2630 reg_index - 32, buffer);
2631 else
2632 /* Read the portion that overlaps the FPR registers. */
2633 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2634 {
2635 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2636 reg_index, buffer);
2637 regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2638 reg_index, buffer + 8);
2639 }
2640 else
2641 {
2642 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2643 reg_index, buffer + 8);
2644 regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2645 reg_index, buffer);
2646 }
2647}
2648
2649/* Write method for POWER7 VSX pseudo-registers. */
2650static void
2651vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2652 int reg_nr, const gdb_byte *buffer)
2653{
2654 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2655 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2656
2657 /* Write the portion that overlaps the VMX registers. */
2658 if (reg_index > 31)
2659 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2660 reg_index - 32, buffer);
2661 else
2662 /* Write the portion that overlaps the FPR registers. */
2663 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2664 {
2665 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2666 reg_index, buffer);
2667 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2668 reg_index, buffer + 8);
2669 }
2670 else
2671 {
2672 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2673 reg_index, buffer + 8);
2674 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2675 reg_index, buffer);
2676 }
2677}
2678
2679/* Read method for POWER7 Extended FP pseudo-registers. */
2680static void
2681efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2682 int reg_nr, gdb_byte *buffer)
2683{
2684 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2685 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2686
2687 /* Read the portion that overlaps the VMX registers. */
2688 regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2689 reg_index, buffer);
2690}
2691
2692/* Write method for POWER7 Extended FP pseudo-registers. */
2693static void
2694efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2695 int reg_nr, const gdb_byte *buffer)
2696{
2697 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2698 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2699
2700 /* Write the portion that overlaps the VMX registers. */
2701 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2702 reg_index, buffer);
2703}
2704
f949c649
TJB		 2705static void
2706rs6000_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2707 int reg_nr, gdb_byte *buffer)
c8001721 2708{
6ced10dd 2709 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
c8001721
EZ		 2710 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2711
6ced10dd 2712 gdb_assert (regcache_arch == gdbarch);
f949c649 2713
5a9e69ba 2714 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
f949c649
TJB		 2715 e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2716 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
604c2f83
LM		 2717 dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2718 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2719 vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2720 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2721 efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
6ced10dd 2722 else
a44bddec 2723 internal_error (__FILE__, __LINE__,
f949c649
TJB		 2724 _("rs6000_pseudo_register_read: "
2725 "called on unexpected register '%s' (%d)"),
2726 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
c8001721
EZ		 2727}
2728
2729static void
f949c649
TJB		 2730rs6000_pseudo_register_write (struct gdbarch *gdbarch,
2731 struct regcache *regcache,
2732 int reg_nr, const gdb_byte *buffer)
c8001721 2733{
6ced10dd 2734 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
c8001721
EZ		 2735 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2736
6ced10dd 2737 gdb_assert (regcache_arch == gdbarch);
f949c649 2738
5a9e69ba 2739 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
f949c649
TJB		 2740 e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2741 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
604c2f83
LM		 2742 dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2743 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2744 vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2745 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2746 efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
6ced10dd 2747 else
a44bddec 2748 internal_error (__FILE__, __LINE__,
f949c649
TJB		 2749 _("rs6000_pseudo_register_write: "
2750 "called on unexpected register '%s' (%d)"),
2751 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
6ced10dd
JB		 2752}
2753
18ed0c4e 2754/* Convert a DBX STABS register number to a GDB register number. */
c8001721 2755static int
d3f73121 2756rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
c8001721 2757{
d3f73121 2758 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
c8001721 2759
9f744501
JB		 2760 if (0 <= num && num <= 31)
2761 return tdep->ppc_gp0_regnum + num;
2762 else if (32 <= num && num <= 63)
383f0f5b
JB		 2763 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2764 specifies registers the architecture doesn't have? Our
2765 callers don't check the value we return. */
366f009f 2766 return tdep->ppc_fp0_regnum + (num - 32);
18ed0c4e
JB		 2767 else if (77 <= num && num <= 108)
2768 return tdep->ppc_vr0_regnum + (num - 77);
9f744501
JB		 2769 else if (1200 <= num && num < 1200 + 32)
2770 return tdep->ppc_ev0_regnum + (num - 1200);
2771 else
2772 switch (num)
2773 {
2774 case 64:
2775 return tdep->ppc_mq_regnum;
2776 case 65:
2777 return tdep->ppc_lr_regnum;
2778 case 66:
2779 return tdep->ppc_ctr_regnum;
2780 case 76:
2781 return tdep->ppc_xer_regnum;
2782 case 109:
2783 return tdep->ppc_vrsave_regnum;
18ed0c4e
JB		 2784 case 110:
2785 return tdep->ppc_vrsave_regnum - 1; /* vscr */
867e2dc5 2786 case 111:
18ed0c4e 2787 return tdep->ppc_acc_regnum;
867e2dc5 2788 case 112:
18ed0c4e 2789 return tdep->ppc_spefscr_regnum;
9f744501
JB		 2790 default:
2791 return num;
2792 }
18ed0c4e 2793}
9f744501 2794
9f744501 2795
18ed0c4e
JB		 2796/* Convert a Dwarf 2 register number to a GDB register number. */
2797static int
d3f73121 2798rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
18ed0c4e 2799{
d3f73121 2800 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9f744501 2801
18ed0c4e
JB		 2802 if (0 <= num && num <= 31)
2803 return tdep->ppc_gp0_regnum + num;
2804 else if (32 <= num && num <= 63)
2805 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2806 specifies registers the architecture doesn't have? Our
2807 callers don't check the value we return. */
2808 return tdep->ppc_fp0_regnum + (num - 32);
2809 else if (1124 <= num && num < 1124 + 32)
2810 return tdep->ppc_vr0_regnum + (num - 1124);
2811 else if (1200 <= num && num < 1200 + 32)
2812 return tdep->ppc_ev0_regnum + (num - 1200);
2813 else
2814 switch (num)
2815 {
a489f789
AS		 2816 case 64:
2817 return tdep->ppc_cr_regnum;
18ed0c4e
JB		 2818 case 67:
2819 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2820 case 99:
2821 return tdep->ppc_acc_regnum;
2822 case 100:
2823 return tdep->ppc_mq_regnum;
2824 case 101:
2825 return tdep->ppc_xer_regnum;
2826 case 108:
2827 return tdep->ppc_lr_regnum;
2828 case 109:
2829 return tdep->ppc_ctr_regnum;
2830 case 356:
2831 return tdep->ppc_vrsave_regnum;
2832 case 612:
2833 return tdep->ppc_spefscr_regnum;
2834 default:
2835 return num;
2836 }
2188cbdd
EZ		 2837}
2838
4fc771b8
DJ		 2839/* Translate a .eh_frame register to DWARF register, or adjust a
2840 .debug_frame register. */
2841
2842static int
2843rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
2844{
2845 /* GCC releases before 3.4 use GCC internal register numbering in
2846 .debug_frame (and .debug_info, et cetera). The numbering is
2847 different from the standard SysV numbering for everything except
2848 for GPRs and FPRs. We can not detect this problem in most cases
2849 - to get accurate debug info for variables living in lr, ctr, v0,
2850 et cetera, use a newer version of GCC. But we must detect
2851 one important case - lr is in column 65 in .debug_frame output,
2852 instead of 108.
2853
2854 GCC 3.4, and the "hammer" branch, have a related problem. They
2855 record lr register saves in .debug_frame as 108, but still record
2856 the return column as 65. We fix that up too.
2857
2858 We can do this because 65 is assigned to fpsr, and GCC never
2859 generates debug info referring to it. To add support for
2860 handwritten debug info that restores fpsr, we would need to add a
2861 producer version check to this. */
2862 if (!eh_frame_p)
2863 {
2864 if (num == 65)
2865 return 108;
2866 else
2867 return num;
2868 }
2869
2870 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2871 internal register numbering; translate that to the standard DWARF2
2872 register numbering. */
2873 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */
2874 return num;
2875 else if (68 <= num && num <= 75) /* cr0-cr8 */
2876 return num - 68 + 86;
2877 else if (77 <= num && num <= 108) /* vr0-vr31 */
2878 return num - 77 + 1124;
2879 else
2880 switch (num)
2881 {
2882 case 64: /* mq */
2883 return 100;
2884 case 65: /* lr */
2885 return 108;
2886 case 66: /* ctr */
2887 return 109;
2888 case 76: /* xer */
2889 return 101;
2890 case 109: /* vrsave */
2891 return 356;
2892 case 110: /* vscr */
2893 return 67;
2894 case 111: /* spe_acc */
2895 return 99;
2896 case 112: /* spefscr */
2897 return 612;
2898 default:
2899 return num;
2900 }
2901}
c906108c 2902\f
c5aa993b 2903
7a78ae4e 2904/* Handling the various POWER/PowerPC variants. */
c906108c 2905
c906108c 2906/* Information about a particular processor variant. */
7a78ae4e 2907
c906108c 2908struct variant
c5aa993b
JM		 2909 {
2910 /* Name of this variant. */
2911 char *name;
c906108c 2912
c5aa993b
JM		 2913 /* English description of the variant. */
2914 char *description;
c906108c 2915
64366f1c 2916 /* bfd_arch_info.arch corresponding to variant. */
7a78ae4e
ND		 2917 enum bfd_architecture arch;
2918
64366f1c 2919 /* bfd_arch_info.mach corresponding to variant. */
7a78ae4e
ND		 2920 unsigned long mach;
2921
7cc46491
DJ		 2922 /* Target description for this variant. */
2923 struct target_desc **tdesc;
c5aa993b 2924 };
c906108c 2925
489461e2 2926static struct variant variants[] =
c906108c 2927{
7a78ae4e 2928 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
7284e1be 2929 bfd_mach_ppc, &tdesc_powerpc_altivec32},
7a78ae4e 2930 {"power", "POWER user-level", bfd_arch_rs6000,
7cc46491 2931 bfd_mach_rs6k, &tdesc_rs6000},
7a78ae4e 2932 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
7cc46491 2933 bfd_mach_ppc_403, &tdesc_powerpc_403},
7a78ae4e 2934 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
7cc46491 2935 bfd_mach_ppc_601, &tdesc_powerpc_601},
7a78ae4e 2936 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
7cc46491 2937 bfd_mach_ppc_602, &tdesc_powerpc_602},
7a78ae4e 2938 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
7cc46491 2939 bfd_mach_ppc_603, &tdesc_powerpc_603},
7a78ae4e 2940 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
7cc46491 2941 604, &tdesc_powerpc_604},
7a78ae4e 2942 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
7cc46491 2943 bfd_mach_ppc_403gc, &tdesc_powerpc_403gc},
7a78ae4e 2944 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
7cc46491 2945 bfd_mach_ppc_505, &tdesc_powerpc_505},
7a78ae4e 2946 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
7cc46491 2947 bfd_mach_ppc_860, &tdesc_powerpc_860},
7a78ae4e 2948 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
7cc46491 2949 bfd_mach_ppc_750, &tdesc_powerpc_750},
1fcc0bb8 2950 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
7cc46491 2951 bfd_mach_ppc_7400, &tdesc_powerpc_7400},
c8001721 2952 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
7cc46491 2953 bfd_mach_ppc_e500, &tdesc_powerpc_e500},
7a78ae4e 2954
5d57ee30
KB		 2955 /* 64-bit */
2956 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
7284e1be 2957 bfd_mach_ppc64, &tdesc_powerpc_altivec64},
7a78ae4e 2958 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
7cc46491 2959 bfd_mach_ppc_620, &tdesc_powerpc_64},
5d57ee30 2960 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
7cc46491 2961 bfd_mach_ppc_630, &tdesc_powerpc_64},
7a78ae4e 2962 {"a35", "PowerPC A35", bfd_arch_powerpc,
7cc46491 2963 bfd_mach_ppc_a35, &tdesc_powerpc_64},
5d57ee30 2964 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
7cc46491 2965 bfd_mach_ppc_rs64ii, &tdesc_powerpc_64},
5d57ee30 2966 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
7cc46491 2967 bfd_mach_ppc_rs64iii, &tdesc_powerpc_64},
5d57ee30 2968
64366f1c 2969 /* FIXME: I haven't checked the register sets of the following. */
7a78ae4e 2970 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
7cc46491 2971 bfd_mach_rs6k_rs1, &tdesc_rs6000},
7a78ae4e 2972 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
7cc46491 2973 bfd_mach_rs6k_rsc, &tdesc_rs6000},
7a78ae4e 2974 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
7cc46491 2975 bfd_mach_rs6k_rs2, &tdesc_rs6000},
7a78ae4e 2976
7cc46491 2977 {0, 0, 0, 0, 0}
c906108c
SS		 2978};
2979
7a78ae4e 2980/* Return the variant corresponding to architecture ARCH and machine number
64366f1c 2981 MACH. If no such variant exists, return null. */
c906108c 2982
7a78ae4e
ND		 2983static const struct variant *
2984find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
c906108c 2985{
7a78ae4e 2986 const struct variant *v;
c5aa993b 2987
7a78ae4e
ND		 2988 for (v = variants; v->name; v++)
2989 if (arch == v->arch && mach == v->mach)
2990 return v;
c906108c 2991
7a78ae4e 2992 return NULL;
c906108c 2993}
9364a0ef
EZ		 2994
2995static int
2996gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
2997{
ee4f0f76
DJ		 2998 if (!info->disassembler_options)
2999 info->disassembler_options = "any";
3000
40887e1a 3001 if (info->endian == BFD_ENDIAN_BIG)
9364a0ef
EZ		 3002 return print_insn_big_powerpc (memaddr, info);
3003 else
3004 return print_insn_little_powerpc (memaddr, info);
3005}
7a78ae4e 3006\f
61a65099
KB		 3007static CORE_ADDR
3008rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
3009{
3e8c568d 3010 return frame_unwind_register_unsigned (next_frame,
8b164abb 3011 gdbarch_pc_regnum (gdbarch));
61a65099
KB		 3012}
3013
3014static struct frame_id
1af5d7ce 3015rs6000_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
61a65099 3016{
1af5d7ce
UW		 3017 return frame_id_build (get_frame_register_unsigned
3018 (this_frame, gdbarch_sp_regnum (gdbarch)),
3019 get_frame_pc (this_frame));
61a65099
KB		 3020}
3021
3022struct rs6000_frame_cache
3023{
3024 CORE_ADDR base;
3025 CORE_ADDR initial_sp;
3026 struct trad_frame_saved_reg *saved_regs;
3027};
3028
3029static struct rs6000_frame_cache *
1af5d7ce 3030rs6000_frame_cache (struct frame_info *this_frame, void **this_cache)
61a65099
KB		 3031{
3032 struct rs6000_frame_cache *cache;
1af5d7ce 3033 struct gdbarch *gdbarch = get_frame_arch (this_frame);
61a65099
KB		 3034 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3035 struct rs6000_framedata fdata;
3036 int wordsize = tdep->wordsize;
e10b1c4c 3037 CORE_ADDR func, pc;
61a65099
KB		 3038
3039 if ((*this_cache) != NULL)
3040 return (*this_cache);
3041 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
3042 (*this_cache) = cache;
1af5d7ce 3043 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
61a65099 3044
1af5d7ce
UW		 3045 func = get_frame_func (this_frame);
3046 pc = get_frame_pc (this_frame);
be8626e0 3047 skip_prologue (gdbarch, func, pc, &fdata);
e10b1c4c
DJ		 3048
3049 /* Figure out the parent's stack pointer. */
3050
3051 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3052 address of the current frame. Things might be easier if the
3053 ->frame pointed to the outer-most address of the frame. In
3054 the mean time, the address of the prev frame is used as the
3055 base address of this frame. */
1af5d7ce
UW		 3056 cache->base = get_frame_register_unsigned
3057 (this_frame, gdbarch_sp_regnum (gdbarch));
e10b1c4c
DJ		 3058
3059 /* If the function appears to be frameless, check a couple of likely
3060 indicators that we have simply failed to find the frame setup.
3061 Two common cases of this are missing symbols (i.e.
ef02daa9 3062 get_frame_func returns the wrong address or 0), and assembly
e10b1c4c
DJ		 3063 stubs which have a fast exit path but set up a frame on the slow
3064 path.
3065
3066 If the LR appears to return to this function, then presume that
3067 we have an ABI compliant frame that we failed to find. */
3068 if (fdata.frameless && fdata.lr_offset == 0)
61a65099 3069 {
e10b1c4c
DJ		 3070 CORE_ADDR saved_lr;
3071 int make_frame = 0;
3072
1af5d7ce 3073 saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum);
e10b1c4c
DJ		 3074 if (func == 0 && saved_lr == pc)
3075 make_frame = 1;
3076 else if (func != 0)
3077 {
3078 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
3079 if (func == saved_func)
3080 make_frame = 1;
3081 }
3082
3083 if (make_frame)
3084 {
3085 fdata.frameless = 0;
de6a76fd 3086 fdata.lr_offset = tdep->lr_frame_offset;
e10b1c4c 3087 }
61a65099 3088 }
e10b1c4c
DJ		 3089
3090 if (!fdata.frameless)
3091 /* Frameless really means stackless. */
4a7622d1 3092 cache->base = read_memory_unsigned_integer (cache->base, wordsize);
e10b1c4c 3093
3e8c568d 3094 trad_frame_set_value (cache->saved_regs,
8b164abb 3095 gdbarch_sp_regnum (gdbarch), cache->base);
61a65099
KB		 3096
3097 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3098 All fpr's from saved_fpr to fp31 are saved. */
3099
3100 if (fdata.saved_fpr >= 0)
3101 {
3102 int i;
3103 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
383f0f5b
JB		 3104
3105 /* If skip_prologue says floating-point registers were saved,
3106 but the current architecture has no floating-point registers,
3107 then that's strange. But we have no indices to even record
3108 the addresses under, so we just ignore it. */
3109 if (ppc_floating_point_unit_p (gdbarch))
063715bf 3110 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
383f0f5b
JB		 3111 {
3112 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3113 fpr_addr += 8;
3114 }
61a65099
KB		 3115 }
3116
3117 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
46a9b8ed
DJ		 3118 All gpr's from saved_gpr to gpr31 are saved (except during the
3119 prologue). */
61a65099
KB		 3120
3121 if (fdata.saved_gpr >= 0)
3122 {
3123 int i;
3124 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
063715bf 3125 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
61a65099 3126 {
46a9b8ed
DJ		 3127 if (fdata.gpr_mask & (1U << i))
3128 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
61a65099
KB		 3129 gpr_addr += wordsize;
3130 }
3131 }
3132
3133 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3134 All vr's from saved_vr to vr31 are saved. */
3135 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3136 {
3137 if (fdata.saved_vr >= 0)
3138 {
3139 int i;
3140 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3141 for (i = fdata.saved_vr; i < 32; i++)
3142 {
3143 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3144 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3145 }
3146 }
3147 }
3148
3149 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3150 All vr's from saved_ev to ev31 are saved. ????? */
5a9e69ba 3151 if (tdep->ppc_ev0_regnum != -1)
61a65099
KB		 3152 {
3153 if (fdata.saved_ev >= 0)
3154 {
3155 int i;
3156 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
063715bf 3157 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
61a65099
KB		 3158 {
3159 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3160 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
3161 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3162 }
3163 }
3164 }
3165
3166 /* If != 0, fdata.cr_offset is the offset from the frame that
3167 holds the CR. */
3168 if (fdata.cr_offset != 0)
3169 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
3170
3171 /* If != 0, fdata.lr_offset is the offset from the frame that
3172 holds the LR. */
3173 if (fdata.lr_offset != 0)
3174 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
46a9b8ed
DJ		 3175 else if (fdata.lr_register != -1)
3176 cache->saved_regs[tdep->ppc_lr_regnum].realreg = fdata.lr_register;
61a65099 3177 /* The PC is found in the link register. */
8b164abb 3178 cache->saved_regs[gdbarch_pc_regnum (gdbarch)] =
3e8c568d 3179 cache->saved_regs[tdep->ppc_lr_regnum];
61a65099
KB		 3180
3181 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3182 holds the VRSAVE. */
3183 if (fdata.vrsave_offset != 0)
3184 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
3185
3186 if (fdata.alloca_reg < 0)
3187 /* If no alloca register used, then fi->frame is the value of the
3188 %sp for this frame, and it is good enough. */
1af5d7ce
UW		 3189 cache->initial_sp
3190 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
61a65099 3191 else
1af5d7ce
UW		 3192 cache->initial_sp
3193 = get_frame_register_unsigned (this_frame, fdata.alloca_reg);
61a65099
KB		 3194
3195 return cache;
3196}
3197
3198static void
1af5d7ce 3199rs6000_frame_this_id (struct frame_info *this_frame, void **this_cache,
61a65099
KB		 3200 struct frame_id *this_id)
3201{
1af5d7ce 3202 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099 3203 this_cache);
5b197912
UW		 3204 /* This marks the outermost frame. */
3205 if (info->base == 0)
3206 return;
3207
1af5d7ce 3208 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
61a65099
KB		 3209}
3210
1af5d7ce
UW		 3211static struct value *
3212rs6000_frame_prev_register (struct frame_info *this_frame,
3213 void **this_cache, int regnum)
61a65099 3214{
1af5d7ce 3215 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099 3216 this_cache);
1af5d7ce 3217 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
61a65099
KB		 3218}
3219
3220static const struct frame_unwind rs6000_frame_unwind =
3221{
3222 NORMAL_FRAME,
3223 rs6000_frame_this_id,
1af5d7ce
UW		 3224 rs6000_frame_prev_register,
3225 NULL,
3226 default_frame_sniffer
61a65099 3227};
61a65099
KB		 3228\f
3229
3230static CORE_ADDR
1af5d7ce 3231rs6000_frame_base_address (struct frame_info *this_frame, void **this_cache)
61a65099 3232{
1af5d7ce 3233 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099
KB		 3234 this_cache);
3235 return info->initial_sp;
3236}
3237
3238static const struct frame_base rs6000_frame_base = {
3239 &rs6000_frame_unwind,
3240 rs6000_frame_base_address,
3241 rs6000_frame_base_address,
3242 rs6000_frame_base_address
3243};
3244
3245static const struct frame_base *
1af5d7ce 3246rs6000_frame_base_sniffer (struct frame_info *this_frame)
61a65099
KB		 3247{
3248 return &rs6000_frame_base;
3249}
3250
9274a07c
LM		 3251/* DWARF-2 frame support. Used to handle the detection of
3252 clobbered registers during function calls. */
3253
3254static void
3255ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3256 struct dwarf2_frame_state_reg *reg,
4a4e5149 3257 struct frame_info *this_frame)
9274a07c
LM		 3258{
3259 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3260
3261 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3262 non-volatile registers. We will use the same code for both. */
3263
3264 /* Call-saved GP registers. */
3265 if ((regnum >= tdep->ppc_gp0_regnum + 14
3266 && regnum <= tdep->ppc_gp0_regnum + 31)
3267 || (regnum == tdep->ppc_gp0_regnum + 1))
3268 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3269
3270 /* Call-clobbered GP registers. */
3271 if ((regnum >= tdep->ppc_gp0_regnum + 3
3272 && regnum <= tdep->ppc_gp0_regnum + 12)
3273 || (regnum == tdep->ppc_gp0_regnum))
3274 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3275
3276 /* Deal with FP registers, if supported. */
3277 if (tdep->ppc_fp0_regnum >= 0)
3278 {
3279 /* Call-saved FP registers. */
3280 if ((regnum >= tdep->ppc_fp0_regnum + 14
3281 && regnum <= tdep->ppc_fp0_regnum + 31))
3282 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3283
3284 /* Call-clobbered FP registers. */
3285 if ((regnum >= tdep->ppc_fp0_regnum
3286 && regnum <= tdep->ppc_fp0_regnum + 13))
3287 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3288 }
3289
3290 /* Deal with ALTIVEC registers, if supported. */
3291 if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0)
3292 {
3293 /* Call-saved Altivec registers. */
3294 if ((regnum >= tdep->ppc_vr0_regnum + 20
3295 && regnum <= tdep->ppc_vr0_regnum + 31)
3296 || regnum == tdep->ppc_vrsave_regnum)
3297 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3298
3299 /* Call-clobbered Altivec registers. */
3300 if ((regnum >= tdep->ppc_vr0_regnum
3301 && regnum <= tdep->ppc_vr0_regnum + 19))
3302 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3303 }
3304
3305 /* Handle PC register and Stack Pointer correctly. */
40a6adc1 3306 if (regnum == gdbarch_pc_regnum (gdbarch))
9274a07c 3307 reg->how = DWARF2_FRAME_REG_RA;
40a6adc1 3308 else if (regnum == gdbarch_sp_regnum (gdbarch))
9274a07c
LM		 3309 reg->how = DWARF2_FRAME_REG_CFA;
3310}
3311
3312
7a78ae4e
ND		 3313/* Initialize the current architecture based on INFO. If possible, re-use an
3314 architecture from ARCHES, which is a list of architectures already created
3315 during this debugging session.
c906108c 3316
7a78ae4e 3317 Called e.g. at program startup, when reading a core file, and when reading
64366f1c 3318 a binary file. */
c906108c 3319
7a78ae4e
ND		 3320static struct gdbarch *
3321rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3322{
3323 struct gdbarch *gdbarch;
3324 struct gdbarch_tdep *tdep;
7cc46491 3325 int wordsize, from_xcoff_exec, from_elf_exec;
7a78ae4e
ND		 3326 enum bfd_architecture arch;
3327 unsigned long mach;
3328 bfd abfd;
5bf1c677 3329 asection *sect;
55eddb0f
DJ		 3330 enum auto_boolean soft_float_flag = powerpc_soft_float_global;
3331 int soft_float;
3332 enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
604c2f83
LM		 3333 int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0,
3334 have_vsx = 0;
7cc46491
DJ		 3335 int tdesc_wordsize = -1;
3336 const struct target_desc *tdesc = info.target_desc;
3337 struct tdesc_arch_data *tdesc_data = NULL;
f949c649 3338 int num_pseudoregs = 0;
604c2f83 3339 int cur_reg;
7a78ae4e 3340
9aa1e687 3341 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
7a78ae4e
ND		 3342 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3343
9aa1e687
KB		 3344 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3345 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3346
e712c1cf 3347 /* Check word size. If INFO is from a binary file, infer it from
64366f1c 3348 that, else choose a likely default. */
9aa1e687 3349 if (from_xcoff_exec)
c906108c 3350 {
11ed25ac 3351 if (bfd_xcoff_is_xcoff64 (info.abfd))
7a78ae4e
ND		 3352 wordsize = 8;
3353 else
3354 wordsize = 4;
c906108c 3355 }
9aa1e687
KB		 3356 else if (from_elf_exec)
3357 {
3358 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3359 wordsize = 8;
3360 else
3361 wordsize = 4;
3362 }
7cc46491
DJ		 3363 else if (tdesc_has_registers (tdesc))
3364 wordsize = -1;
c906108c 3365 else
7a78ae4e 3366 {
27b15785
KB		 3367 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3368 wordsize = info.bfd_arch_info->bits_per_word /
3369 info.bfd_arch_info->bits_per_byte;
3370 else
3371 wordsize = 4;
7a78ae4e 3372 }
c906108c 3373
475bbd17
JB		 3374 /* Get the architecture and machine from the BFD. */
3375 arch = info.bfd_arch_info->arch;
3376 mach = info.bfd_arch_info->mach;
5bf1c677
EZ		 3377
3378 /* For e500 executables, the apuinfo section is of help here. Such
3379 section contains the identifier and revision number of each
3380 Application-specific Processing Unit that is present on the
3381 chip. The content of the section is determined by the assembler
3382 which looks at each instruction and determines which unit (and
3383 which version of it) can execute it. In our case we just look for
3384 the existance of the section. */
3385
3386 if (info.abfd)
3387 {
3388 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
3389 if (sect)
3390 {
3391 arch = info.bfd_arch_info->arch;
3392 mach = bfd_mach_ppc_e500;
3393 bfd_default_set_arch_mach (&abfd, arch, mach);
3394 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3395 }
3396 }
3397
7cc46491
DJ		 3398 /* Find a default target description which describes our register
3399 layout, if we do not already have one. */
3400 if (! tdesc_has_registers (tdesc))
3401 {
3402 const struct variant *v;
3403
3404 /* Choose variant. */
3405 v = find_variant_by_arch (arch, mach);
3406 if (!v)
3407 return NULL;
3408
3409 tdesc = *v->tdesc;
3410 }
3411
3412 gdb_assert (tdesc_has_registers (tdesc));
3413
3414 /* Check any target description for validity. */
3415 if (tdesc_has_registers (tdesc))
3416 {
3417 static const char *const gprs[] = {
3418 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3419 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3420 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3421 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3422 };
3423 static const char *const segment_regs[] = {
3424 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
3425 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
3426 };
3427 const struct tdesc_feature *feature;
3428 int i, valid_p;
3429 static const char *const msr_names[] = { "msr", "ps" };
3430 static const char *const cr_names[] = { "cr", "cnd" };
3431 static const char *const ctr_names[] = { "ctr", "cnt" };
3432
3433 feature = tdesc_find_feature (tdesc,
3434 "org.gnu.gdb.power.core");
3435 if (feature == NULL)
3436 return NULL;
3437
3438 tdesc_data = tdesc_data_alloc ();
3439
3440 valid_p = 1;
3441 for (i = 0; i < ppc_num_gprs; i++)
3442 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]);
3443 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM,
3444 "pc");
3445 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM,
3446 "lr");
3447 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM,
3448 "xer");
3449
3450 /* Allow alternate names for these registers, to accomodate GDB's
3451 historic naming. */
3452 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3453 PPC_MSR_REGNUM, msr_names);
3454 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3455 PPC_CR_REGNUM, cr_names);
3456 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3457 PPC_CTR_REGNUM, ctr_names);
3458
3459 if (!valid_p)
3460 {
3461 tdesc_data_cleanup (tdesc_data);
3462 return NULL;
3463 }
3464
3465 have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM,
3466 "mq");
3467
3468 tdesc_wordsize = tdesc_register_size (feature, "pc") / 8;
3469 if (wordsize == -1)
3470 wordsize = tdesc_wordsize;
3471
3472 feature = tdesc_find_feature (tdesc,
3473 "org.gnu.gdb.power.fpu");
3474 if (feature != NULL)
3475 {
3476 static const char *const fprs[] = {
3477 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
3478 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
3479 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
3480 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
3481 };
3482 valid_p = 1;
3483 for (i = 0; i < ppc_num_fprs; i++)
3484 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3485 PPC_F0_REGNUM + i, fprs[i]);
3486 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3487 PPC_FPSCR_REGNUM, "fpscr");
3488
3489 if (!valid_p)
3490 {
3491 tdesc_data_cleanup (tdesc_data);
3492 return NULL;
3493 }
3494 have_fpu = 1;
3495 }
3496 else
3497 have_fpu = 0;
3498
f949c649
TJB		 3499 /* The DFP pseudo-registers will be available when there are floating
3500 point registers. */
3501 have_dfp = have_fpu;
3502
7cc46491
DJ		 3503 feature = tdesc_find_feature (tdesc,
3504 "org.gnu.gdb.power.altivec");
3505 if (feature != NULL)
3506 {
3507 static const char *const vector_regs[] = {
3508 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
3509 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
3510 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
3511 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
3512 };
3513
3514 valid_p = 1;
3515 for (i = 0; i < ppc_num_gprs; i++)
3516 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3517 PPC_VR0_REGNUM + i,
3518 vector_regs[i]);
3519 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3520 PPC_VSCR_REGNUM, "vscr");
3521 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3522 PPC_VRSAVE_REGNUM, "vrsave");
3523
3524 if (have_spe || !valid_p)
3525 {
3526 tdesc_data_cleanup (tdesc_data);
3527 return NULL;
3528 }
3529 have_altivec = 1;
3530 }
3531 else
3532 have_altivec = 0;
3533
604c2f83
LM		 3534 /* Check for POWER7 VSX registers support. */
3535 feature = tdesc_find_feature (tdesc,
3536 "org.gnu.gdb.power.vsx");
3537
3538 if (feature != NULL)
3539 {
3540 static const char *const vsx_regs[] = {
3541 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
3542 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
3543 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
3544 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
3545 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
3546 "vs30h", "vs31h"
3547 };
3548
3549 valid_p = 1;
3550
3551 for (i = 0; i < ppc_num_vshrs; i++)
3552 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3553 PPC_VSR0_UPPER_REGNUM + i,
3554 vsx_regs[i]);
3555 if (!valid_p)
3556 {
3557 tdesc_data_cleanup (tdesc_data);
3558 return NULL;
3559 }
3560
3561 have_vsx = 1;
3562 }
3563 else
3564 have_vsx = 0;
3565
7cc46491
DJ		 3566 /* On machines supporting the SPE APU, the general-purpose registers
3567 are 64 bits long. There are SIMD vector instructions to treat them
3568 as pairs of floats, but the rest of the instruction set treats them
3569 as 32-bit registers, and only operates on their lower halves.
3570
3571 In the GDB regcache, we treat their high and low halves as separate
3572 registers. The low halves we present as the general-purpose
3573 registers, and then we have pseudo-registers that stitch together
3574 the upper and lower halves and present them as pseudo-registers.
3575
3576 Thus, the target description is expected to supply the upper
3577 halves separately. */
3578
3579 feature = tdesc_find_feature (tdesc,
3580 "org.gnu.gdb.power.spe");
3581 if (feature != NULL)
3582 {
3583 static const char *const upper_spe[] = {
3584 "ev0h", "ev1h", "ev2h", "ev3h",
3585 "ev4h", "ev5h", "ev6h", "ev7h",
3586 "ev8h", "ev9h", "ev10h", "ev11h",
3587 "ev12h", "ev13h", "ev14h", "ev15h",
3588 "ev16h", "ev17h", "ev18h", "ev19h",
3589 "ev20h", "ev21h", "ev22h", "ev23h",
3590 "ev24h", "ev25h", "ev26h", "ev27h",
3591 "ev28h", "ev29h", "ev30h", "ev31h"
3592 };
3593
3594 valid_p = 1;
3595 for (i = 0; i < ppc_num_gprs; i++)
3596 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3597 PPC_SPE_UPPER_GP0_REGNUM + i,
3598 upper_spe[i]);
3599 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3600 PPC_SPE_ACC_REGNUM, "acc");
3601 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3602 PPC_SPE_FSCR_REGNUM, "spefscr");
3603
3604 if (have_mq || have_fpu || !valid_p)
3605 {
3606 tdesc_data_cleanup (tdesc_data);
3607 return NULL;
3608 }
3609 have_spe = 1;
3610 }
3611 else
3612 have_spe = 0;
3613 }
3614
3615 /* If we have a 64-bit binary on a 32-bit target, complain. Also
3616 complain for a 32-bit binary on a 64-bit target; we do not yet
3617 support that. For instance, the 32-bit ABI routines expect
3618 32-bit GPRs.
3619
3620 As long as there isn't an explicit target description, we'll
3621 choose one based on the BFD architecture and get a word size
3622 matching the binary (probably powerpc:common or
3623 powerpc:common64). So there is only trouble if a 64-bit target
3624 supplies a 64-bit description while debugging a 32-bit
3625 binary. */
3626 if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize)
3627 {
3628 tdesc_data_cleanup (tdesc_data);
3629 return NULL;
3630 }
3631
55eddb0f
DJ		 3632#ifdef HAVE_ELF
3633 if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec)
3634 {
3635 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3636 Tag_GNU_Power_ABI_FP))
3637 {
3638 case 1:
3639 soft_float_flag = AUTO_BOOLEAN_FALSE;
3640 break;
3641 case 2:
3642 soft_float_flag = AUTO_BOOLEAN_TRUE;
3643 break;
3644 default:
3645 break;
3646 }
3647 }
3648
3649 if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec)
3650 {
3651 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3652 Tag_GNU_Power_ABI_Vector))
3653 {
3654 case 1:
3655 vector_abi = POWERPC_VEC_GENERIC;
3656 break;
3657 case 2:
3658 vector_abi = POWERPC_VEC_ALTIVEC;
3659 break;
3660 case 3:
3661 vector_abi = POWERPC_VEC_SPE;
3662 break;
3663 default:
3664 break;
3665 }
3666 }
3667#endif
3668
3669 if (soft_float_flag == AUTO_BOOLEAN_TRUE)
3670 soft_float = 1;
3671 else if (soft_float_flag == AUTO_BOOLEAN_FALSE)
3672 soft_float = 0;
3673 else
3674 soft_float = !have_fpu;
3675
3676 /* If we have a hard float binary or setting but no floating point
3677 registers, downgrade to soft float anyway. We're still somewhat
3678 useful in this scenario. */
3679 if (!soft_float && !have_fpu)
3680 soft_float = 1;
3681
3682 /* Similarly for vector registers. */
3683 if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec)
3684 vector_abi = POWERPC_VEC_GENERIC;
3685
3686 if (vector_abi == POWERPC_VEC_SPE && !have_spe)
3687 vector_abi = POWERPC_VEC_GENERIC;
3688
3689 if (vector_abi == POWERPC_VEC_AUTO)
3690 {
3691 if (have_altivec)
3692 vector_abi = POWERPC_VEC_ALTIVEC;
3693 else if (have_spe)
3694 vector_abi = POWERPC_VEC_SPE;
3695 else
3696 vector_abi = POWERPC_VEC_GENERIC;
3697 }
3698
3699 /* Do not limit the vector ABI based on available hardware, since we
3700 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
3701
7cc46491
DJ		 3702 /* Find a candidate among extant architectures. */
3703 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3704 arches != NULL;
3705 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3706 {
3707 /* Word size in the various PowerPC bfd_arch_info structs isn't
3708 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3709 separate word size check. */
3710 tdep = gdbarch_tdep (arches->gdbarch);
55eddb0f
DJ		 3711 if (tdep && tdep->soft_float != soft_float)
3712 continue;
3713 if (tdep && tdep->vector_abi != vector_abi)
3714 continue;
7cc46491
DJ		 3715 if (tdep && tdep->wordsize == wordsize)
3716 {
3717 if (tdesc_data != NULL)
3718 tdesc_data_cleanup (tdesc_data);
3719 return arches->gdbarch;
3720 }
3721 }
3722
3723 /* None found, create a new architecture from INFO, whose bfd_arch_info
3724 validity depends on the source:
3725 - executable useless
3726 - rs6000_host_arch() good
3727 - core file good
3728 - "set arch" trust blindly
3729 - GDB startup useless but harmless */
3730
3731 tdep = XCALLOC (1, struct gdbarch_tdep);
3732 tdep->wordsize = wordsize;
55eddb0f
DJ		 3733 tdep->soft_float = soft_float;
3734 tdep->vector_abi = vector_abi;
7cc46491 3735
7a78ae4e 3736 gdbarch = gdbarch_alloc (&info, tdep);
7a78ae4e 3737
7cc46491
DJ		 3738 tdep->ppc_gp0_regnum = PPC_R0_REGNUM;
3739 tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2;
3740 tdep->ppc_ps_regnum = PPC_MSR_REGNUM;
3741 tdep->ppc_cr_regnum = PPC_CR_REGNUM;
3742 tdep->ppc_lr_regnum = PPC_LR_REGNUM;
3743 tdep->ppc_ctr_regnum = PPC_CTR_REGNUM;
3744 tdep->ppc_xer_regnum = PPC_XER_REGNUM;
3745 tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1;
3746
3747 tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1;
3748 tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1;
604c2f83 3749 tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1;
7cc46491
DJ		 3750 tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1;
3751 tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1;
3752 tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1;
3753 tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1;
3754 tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
3755
3756 set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
3757 set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3758 set_gdbarch_deprecated_fp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3759 set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum);
9f643768 3760 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
7cc46491
DJ		 3761
3762 /* The XML specification for PowerPC sensibly calls the MSR "msr".
3763 GDB traditionally called it "ps", though, so let GDB add an
3764 alias. */
3765 set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum);
3766
4a7622d1 3767 if (wordsize == 8)
05580c65 3768 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
afd48b75 3769 else
4a7622d1 3770 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
c8001721 3771
baffbae0
JB		 3772 /* Set lr_frame_offset. */
3773 if (wordsize == 8)
3774 tdep->lr_frame_offset = 16;
baffbae0 3775 else
4a7622d1 3776 tdep->lr_frame_offset = 4;
baffbae0 3777
604c2f83 3778 if (have_spe || have_dfp || have_vsx)
7cc46491 3779 {
f949c649
TJB		 3780 set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read);
3781 set_gdbarch_pseudo_register_write (gdbarch, rs6000_pseudo_register_write);
7cc46491 3782 }
1fcc0bb8 3783
e0d24f8d
WZ		 3784 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3785
56a6dfb9 3786 /* Select instruction printer. */
708ff411 3787 if (arch == bfd_arch_rs6000)
9364a0ef 3788 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
56a6dfb9 3789 else
9364a0ef 3790 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
7495d1dc 3791
5a9e69ba 3792 set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS);
f949c649
TJB		 3793
3794 if (have_spe)
3795 num_pseudoregs += 32;
3796 if (have_dfp)
3797 num_pseudoregs += 16;
604c2f83
LM		 3798 if (have_vsx)
3799 /* Include both VSX and Extended FP registers. */
3800 num_pseudoregs += 96;
f949c649
TJB		 3801
3802 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs);
7a78ae4e
ND		 3803
3804 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3805 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3806 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3807 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3808 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3809 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3810 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4a7622d1 3811 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
4e409299 3812 set_gdbarch_char_signed (gdbarch, 0);
7a78ae4e 3813
11269d7e 3814 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
4a7622d1 3815 if (wordsize == 8)
8b148df9
AC		 3816 /* PPC64 SYSV. */
3817 set_gdbarch_frame_red_zone_size (gdbarch, 288);
7a78ae4e 3818
691d145a
JB		 3819 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
3820 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
3821 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
3822
18ed0c4e
JB		 3823 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
3824 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
d217aaed 3825
4a7622d1 3826 if (wordsize == 4)
77b2b6d4 3827 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
4a7622d1 3828 else if (wordsize == 8)
8be9034a 3829 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
7a78ae4e 3830
7a78ae4e 3831 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
0d1243d9 3832 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
8ab3d180 3833 set_gdbarch_skip_main_prologue (gdbarch, rs6000_skip_main_prologue);
0d1243d9 3834
7a78ae4e 3835 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
7a78ae4e
ND		 3836 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
3837
203c3895
UW		 3838 /* The value of symbols of type N_SO and N_FUN maybe null when
3839 it shouldn't be. */
3840 set_gdbarch_sofun_address_maybe_missing (gdbarch, 1);
3841
ce5eab59 3842 /* Handles single stepping of atomic sequences. */
4a7622d1 3843 set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence);
ce5eab59 3844
7a78ae4e
ND		 3845 /* Not sure on this. FIXMEmgo */
3846 set_gdbarch_frame_args_skip (gdbarch, 8);
3847
143985b7
AF		 3848 /* Helpers for function argument information. */
3849 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
3850
6f7f3f0d
UW		 3851 /* Trampoline. */
3852 set_gdbarch_in_solib_return_trampoline
3853 (gdbarch, rs6000_in_solib_return_trampoline);
3854 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code);
3855
4fc771b8 3856 /* Hook in the DWARF CFI frame unwinder. */
1af5d7ce 3857 dwarf2_append_unwinders (gdbarch);
4fc771b8
DJ		 3858 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum);
3859
9274a07c
LM		 3860 /* Frame handling. */
3861 dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg);
3862
2454a024
UW		 3863 /* Setup displaced stepping. */
3864 set_gdbarch_displaced_step_copy_insn (gdbarch,
3865 simple_displaced_step_copy_insn);
3866 set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup);
3867 set_gdbarch_displaced_step_free_closure (gdbarch,
3868 simple_displaced_step_free_closure);
3869 set_gdbarch_displaced_step_location (gdbarch,
3870 displaced_step_at_entry_point);
3871
3872 set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE);
3873
7b112f9c 3874 /* Hook in ABI-specific overrides, if they have been registered. */
8a4c2d24
UW		 3875 info.target_desc = tdesc;
3876 info.tdep_info = (void *) tdesc_data;
4be87837 3877 gdbarch_init_osabi (info, gdbarch);
7b112f9c 3878
61a65099
KB		 3879 switch (info.osabi)
3880 {
f5aecab8 3881 case GDB_OSABI_LINUX:
61a65099
KB		 3882 case GDB_OSABI_NETBSD_AOUT:
3883 case GDB_OSABI_NETBSD_ELF:
3884 case GDB_OSABI_UNKNOWN:
61a65099 3885 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
1af5d7ce
UW		 3886 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
3887 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
61a65099
KB		 3888 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3889 break;
3890 default:
61a65099 3891 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
81332287
KB		 3892
3893 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
1af5d7ce
UW		 3894 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
3895 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
81332287 3896 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
61a65099
KB		 3897 }
3898
7cc46491
DJ		 3899 set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type);
3900 set_tdesc_pseudo_register_reggroup_p (gdbarch,
3901 rs6000_pseudo_register_reggroup_p);
3902 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3903
3904 /* Override the normal target description method to make the SPE upper
3905 halves anonymous. */
3906 set_gdbarch_register_name (gdbarch, rs6000_register_name);
3907
604c2f83
LM		 3908 /* Choose register numbers for all supported pseudo-registers. */
3909 tdep->ppc_ev0_regnum = -1;
3910 tdep->ppc_dl0_regnum = -1;
3911 tdep->ppc_vsr0_regnum = -1;
3912 tdep->ppc_efpr0_regnum = -1;
9f643768 3913
604c2f83
LM		 3914 cur_reg = gdbarch_num_regs (gdbarch);
3915
3916 if (have_spe)
3917 {
3918 tdep->ppc_ev0_regnum = cur_reg;
3919 cur_reg += 32;
3920 }
3921 if (have_dfp)
3922 {
3923 tdep->ppc_dl0_regnum = cur_reg;
3924 cur_reg += 16;
3925 }
3926 if (have_vsx)
3927 {
3928 tdep->ppc_vsr0_regnum = cur_reg;
3929 cur_reg += 64;
3930 tdep->ppc_efpr0_regnum = cur_reg;
3931 cur_reg += 32;
3932 }
f949c649 3933
604c2f83
LM		 3934 gdb_assert (gdbarch_num_regs (gdbarch)
3935 + gdbarch_num_pseudo_regs (gdbarch) == cur_reg);
f949c649 3936
7a78ae4e 3937 return gdbarch;
c906108c
SS		 3938}
3939
7b112f9c 3940static void
8b164abb 3941rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
7b112f9c 3942{
8b164abb 3943 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7b112f9c
JT		 3944
3945 if (tdep == NULL)
3946 return;
3947
4be87837 3948 /* FIXME: Dump gdbarch_tdep. */
7b112f9c
JT		 3949}
3950
55eddb0f
DJ		 3951/* PowerPC-specific commands. */
3952
3953static void
3954set_powerpc_command (char *args, int from_tty)
3955{
3956 printf_unfiltered (_("\
3957\"set powerpc\" must be followed by an appropriate subcommand.\n"));
3958 help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout);
3959}
3960
3961static void
3962show_powerpc_command (char *args, int from_tty)
3963{
3964 cmd_show_list (showpowerpccmdlist, from_tty, "");
3965}
3966
3967static void
3968powerpc_set_soft_float (char *args, int from_tty,
3969 struct cmd_list_element *c)
3970{
3971 struct gdbarch_info info;
3972
3973 /* Update the architecture. */
3974 gdbarch_info_init (&info);
3975 if (!gdbarch_update_p (info))
3976 internal_error (__FILE__, __LINE__, "could not update architecture");
3977}
3978
3979static void
3980powerpc_set_vector_abi (char *args, int from_tty,
3981 struct cmd_list_element *c)
3982{
3983 struct gdbarch_info info;
3984 enum powerpc_vector_abi vector_abi;
3985
3986 for (vector_abi = POWERPC_VEC_AUTO;
3987 vector_abi != POWERPC_VEC_LAST;
3988 vector_abi++)
3989 if (strcmp (powerpc_vector_abi_string,
3990 powerpc_vector_strings[vector_abi]) == 0)
3991 {
3992 powerpc_vector_abi_global = vector_abi;
3993 break;
3994 }
3995
3996 if (vector_abi == POWERPC_VEC_LAST)
3997 internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."),
3998 powerpc_vector_abi_string);
3999
4000 /* Update the architecture. */
4001 gdbarch_info_init (&info);
4002 if (!gdbarch_update_p (info))
4003 internal_error (__FILE__, __LINE__, "could not update architecture");
4004}
4005
c906108c
SS		 4006/* Initialization code. */
4007
a78f21af 4008extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
b9362cc7 4009
c906108c 4010void
fba45db2 4011_initialize_rs6000_tdep (void)
c906108c 4012{
7b112f9c
JT		 4013 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
4014 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
7cc46491
DJ		 4015
4016 /* Initialize the standard target descriptions. */
4017 initialize_tdesc_powerpc_32 ();
7284e1be 4018 initialize_tdesc_powerpc_altivec32 ();
604c2f83 4019 initialize_tdesc_powerpc_vsx32 ();
7cc46491
DJ		 4020 initialize_tdesc_powerpc_403 ();
4021 initialize_tdesc_powerpc_403gc ();
4022 initialize_tdesc_powerpc_505 ();
4023 initialize_tdesc_powerpc_601 ();
4024 initialize_tdesc_powerpc_602 ();
4025 initialize_tdesc_powerpc_603 ();
4026 initialize_tdesc_powerpc_604 ();
4027 initialize_tdesc_powerpc_64 ();
7284e1be 4028 initialize_tdesc_powerpc_altivec64 ();
604c2f83 4029 initialize_tdesc_powerpc_vsx64 ();
7cc46491
DJ		 4030 initialize_tdesc_powerpc_7400 ();
4031 initialize_tdesc_powerpc_750 ();
4032 initialize_tdesc_powerpc_860 ();
4033 initialize_tdesc_powerpc_e500 ();
4034 initialize_tdesc_rs6000 ();
55eddb0f
DJ		 4035
4036 /* Add root prefix command for all "set powerpc"/"show powerpc"
4037 commands. */
4038 add_prefix_cmd ("powerpc", no_class, set_powerpc_command,
4039 _("Various PowerPC-specific commands."),
4040 &setpowerpccmdlist, "set powerpc ", 0, &setlist);
4041
4042 add_prefix_cmd ("powerpc", no_class, show_powerpc_command,
4043 _("Various PowerPC-specific commands."),
4044 &showpowerpccmdlist, "show powerpc ", 0, &showlist);
4045
4046 /* Add a command to allow the user to force the ABI. */
4047 add_setshow_auto_boolean_cmd ("soft-float", class_support,
4048 &powerpc_soft_float_global,
4049 _("Set whether to use a soft-float ABI."),
4050 _("Show whether to use a soft-float ABI."),
4051 NULL,
4052 powerpc_set_soft_float, NULL,
4053 &setpowerpccmdlist, &showpowerpccmdlist);
4054
4055 add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings,
4056 &powerpc_vector_abi_string,
4057 _("Set the vector ABI."),
4058 _("Show the vector ABI."),
4059 NULL, powerpc_set_vector_abi, NULL,
4060 &setpowerpccmdlist, &showpowerpccmdlist);
c906108c 4061}
GDB Binutils - Deliverables
This page took 1.07125 seconds and 4 git commands to generate.