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[deliverable/binutils-gdb.git] / gdb / rs6000-tdep.c
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c906108c 1/* Target-dependent code for GDB, the GNU debugger.
7aea86e6 2
28e7fd62 3 Copyright (C) 1986-2013 Free Software Foundation, Inc.
c906108c 4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM		 7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
c5aa993b 10 (at your option) any later version.
c906108c 11
c5aa993b
JM		 12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b 17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c
SS		 19
20#include "defs.h"
21#include "frame.h"
22#include "inferior.h"
23#include "symtab.h"
24#include "target.h"
25#include "gdbcore.h"
26#include "gdbcmd.h"
c906108c 27#include "objfiles.h"
7a78ae4e 28#include "arch-utils.h"
4e052eda 29#include "regcache.h"
d195bc9f 30#include "regset.h"
d16aafd8 31#include "doublest.h"
fd0407d6 32#include "value.h"
1fcc0bb8 33#include "parser-defs.h"
4be87837 34#include "osabi.h"
7d9b040b 35#include "infcall.h"
9f643768
JB		 36#include "sim-regno.h"
37#include "gdb/sim-ppc.h"
6ced10dd 38#include "reggroups.h"
4fc771b8 39#include "dwarf2-frame.h"
7cc46491
DJ		 40#include "target-descriptions.h"
41#include "user-regs.h"
7a78ae4e 42
2fccf04a 43#include "libbfd.h" /* for bfd_default_set_arch_mach */
7a78ae4e 44#include "coff/internal.h" /* for libcoff.h */
2fccf04a 45#include "libcoff.h" /* for xcoff_data */
11ed25ac
KB		 46#include "coff/xcoff.h"
47#include "libxcoff.h"
7a78ae4e 48
9aa1e687 49#include "elf-bfd.h"
55eddb0f 50#include "elf/ppc.h"
7a78ae4e 51
6ded7999 52#include "solib-svr4.h"
9aa1e687 53#include "ppc-tdep.h"
debb1f09 54#include "ppc-ravenscar-thread.h"
7a78ae4e 55
338ef23d 56#include "gdb_assert.h"
a89aa300 57#include "dis-asm.h"
338ef23d 58
61a65099
KB		 59#include "trad-frame.h"
60#include "frame-unwind.h"
61#include "frame-base.h"
62
7cc46491 63#include "features/rs6000/powerpc-32.c"
7284e1be 64#include "features/rs6000/powerpc-altivec32.c"
604c2f83 65#include "features/rs6000/powerpc-vsx32.c"
7cc46491
DJ		 66#include "features/rs6000/powerpc-403.c"
67#include "features/rs6000/powerpc-403gc.c"
4d09ffea 68#include "features/rs6000/powerpc-405.c"
7cc46491
DJ		 69#include "features/rs6000/powerpc-505.c"
70#include "features/rs6000/powerpc-601.c"
71#include "features/rs6000/powerpc-602.c"
72#include "features/rs6000/powerpc-603.c"
73#include "features/rs6000/powerpc-604.c"
74#include "features/rs6000/powerpc-64.c"
7284e1be 75#include "features/rs6000/powerpc-altivec64.c"
604c2f83 76#include "features/rs6000/powerpc-vsx64.c"
7cc46491
DJ		 77#include "features/rs6000/powerpc-7400.c"
78#include "features/rs6000/powerpc-750.c"
79#include "features/rs6000/powerpc-860.c"
80#include "features/rs6000/powerpc-e500.c"
81#include "features/rs6000/rs6000.c"
82
5a9e69ba
TJB		 83/* Determine if regnum is an SPE pseudo-register. */
84#define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
85 && (regnum) >= (tdep)->ppc_ev0_regnum \
86 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
87
f949c649
TJB		 88/* Determine if regnum is a decimal float pseudo-register. */
89#define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
90 && (regnum) >= (tdep)->ppc_dl0_regnum \
91 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
92
604c2f83
LM		 93/* Determine if regnum is a POWER7 VSX register. */
94#define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
95 && (regnum) >= (tdep)->ppc_vsr0_regnum \
96 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
97
98/* Determine if regnum is a POWER7 Extended FP register. */
99#define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
100 && (regnum) >= (tdep)->ppc_efpr0_regnum \
d9492458 101 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
604c2f83 102
55eddb0f
DJ		 103/* The list of available "set powerpc ..." and "show powerpc ..."
104 commands. */
105static struct cmd_list_element *setpowerpccmdlist = NULL;
106static struct cmd_list_element *showpowerpccmdlist = NULL;
107
108static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO;
109
110/* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
40478521 111static const char *const powerpc_vector_strings[] =
55eddb0f
DJ		 112{
113 "auto",
114 "generic",
115 "altivec",
116 "spe",
117 NULL
118};
119
120/* A variable that can be configured by the user. */
121static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO;
122static const char *powerpc_vector_abi_string = "auto";
123
0df8b418 124/* To be used by skip_prologue. */
7a78ae4e
ND		 125
126struct rs6000_framedata
127 {
128 int offset; /* total size of frame --- the distance
129 by which we decrement sp to allocate
130 the frame */
131 int saved_gpr; /* smallest # of saved gpr */
46a9b8ed 132 unsigned int gpr_mask; /* Each bit is an individual saved GPR. */
7a78ae4e 133 int saved_fpr; /* smallest # of saved fpr */
6be8bc0c 134 int saved_vr; /* smallest # of saved vr */
96ff0de4 135 int saved_ev; /* smallest # of saved ev */
7a78ae4e 136 int alloca_reg; /* alloca register number (frame ptr) */
0df8b418
MS		 137 char frameless; /* true if frameless functions. */
138 char nosavedpc; /* true if pc not saved. */
46a9b8ed 139 char used_bl; /* true if link register clobbered */
7a78ae4e
ND		 140 int gpr_offset; /* offset of saved gprs from prev sp */
141 int fpr_offset; /* offset of saved fprs from prev sp */
6be8bc0c 142 int vr_offset; /* offset of saved vrs from prev sp */
96ff0de4 143 int ev_offset; /* offset of saved evs from prev sp */
7a78ae4e 144 int lr_offset; /* offset of saved lr */
46a9b8ed 145 int lr_register; /* register of saved lr, if trustworthy */
7a78ae4e 146 int cr_offset; /* offset of saved cr */
6be8bc0c 147 int vrsave_offset; /* offset of saved vrsave register */
7a78ae4e
ND		 148 };
149
c906108c 150
604c2f83
LM		 151/* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
152int
153vsx_register_p (struct gdbarch *gdbarch, int regno)
154{
155 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
156 if (tdep->ppc_vsr0_regnum < 0)
157 return 0;
158 else
159 return (regno >= tdep->ppc_vsr0_upper_regnum && regno
160 <= tdep->ppc_vsr0_upper_regnum + 31);
161}
162
64b84175
KB		 163/* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
164int
be8626e0 165altivec_register_p (struct gdbarch *gdbarch, int regno)
64b84175 166{
be8626e0 167 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
64b84175
KB		 168 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
169 return 0;
170 else
171 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
172}
173
383f0f5b 174
867e2dc5
JB		 175/* Return true if REGNO is an SPE register, false otherwise. */
176int
be8626e0 177spe_register_p (struct gdbarch *gdbarch, int regno)
867e2dc5 178{
be8626e0 179 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
867e2dc5
JB		 180
181 /* Is it a reference to EV0 -- EV31, and do we have those? */
5a9e69ba 182 if (IS_SPE_PSEUDOREG (tdep, regno))
867e2dc5
JB		 183 return 1;
184
6ced10dd
JB		 185 /* Is it a reference to one of the raw upper GPR halves? */
186 if (tdep->ppc_ev0_upper_regnum >= 0
187 && tdep->ppc_ev0_upper_regnum <= regno
188 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
189 return 1;
190
867e2dc5
JB		 191 /* Is it a reference to the 64-bit accumulator, and do we have that? */
192 if (tdep->ppc_acc_regnum >= 0
193 && tdep->ppc_acc_regnum == regno)
194 return 1;
195
196 /* Is it a reference to the SPE floating-point status and control register,
197 and do we have that? */
198 if (tdep->ppc_spefscr_regnum >= 0
199 && tdep->ppc_spefscr_regnum == regno)
200 return 1;
201
202 return 0;
203}
204
205
383f0f5b
JB		 206/* Return non-zero if the architecture described by GDBARCH has
207 floating-point registers (f0 --- f31 and fpscr). */
0a613259
AC		 208int
209ppc_floating_point_unit_p (struct gdbarch *gdbarch)
210{
383f0f5b
JB		 211 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
212
213 return (tdep->ppc_fp0_regnum >= 0
214 && tdep->ppc_fpscr_regnum >= 0);
0a613259 215}
9f643768 216
604c2f83
LM		 217/* Return non-zero if the architecture described by GDBARCH has
218 VSX registers (vsr0 --- vsr63). */
63807e1d 219static int
604c2f83
LM		 220ppc_vsx_support_p (struct gdbarch *gdbarch)
221{
222 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
223
224 return tdep->ppc_vsr0_regnum >= 0;
225}
226
06caf7d2
CES		 227/* Return non-zero if the architecture described by GDBARCH has
228 Altivec registers (vr0 --- vr31, vrsave and vscr). */
229int
230ppc_altivec_support_p (struct gdbarch *gdbarch)
231{
232 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
233
234 return (tdep->ppc_vr0_regnum >= 0
235 && tdep->ppc_vrsave_regnum >= 0);
236}
09991fa0
JB		 237
238/* Check that TABLE[GDB_REGNO] is not already initialized, and then
239 set it to SIM_REGNO.
240
241 This is a helper function for init_sim_regno_table, constructing
242 the table mapping GDB register numbers to sim register numbers; we
243 initialize every element in that table to -1 before we start
244 filling it in. */
9f643768
JB		 245static void
246set_sim_regno (int *table, int gdb_regno, int sim_regno)
247{
248 /* Make sure we don't try to assign any given GDB register a sim
249 register number more than once. */
250 gdb_assert (table[gdb_regno] == -1);
251 table[gdb_regno] = sim_regno;
252}
253
09991fa0
JB		 254
255/* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
256 numbers to simulator register numbers, based on the values placed
257 in the ARCH->tdep->ppc_foo_regnum members. */
9f643768
JB		 258static void
259init_sim_regno_table (struct gdbarch *arch)
260{
261 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
7cc46491 262 int total_regs = gdbarch_num_regs (arch);
9f643768
JB		 263 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
264 int i;
7cc46491
DJ		 265 static const char *const segment_regs[] = {
266 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
267 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
268 };
9f643768
JB		 269
270 /* Presume that all registers not explicitly mentioned below are
271 unavailable from the sim. */
272 for (i = 0; i < total_regs; i++)
273 sim_regno[i] = -1;
274
275 /* General-purpose registers. */
276 for (i = 0; i < ppc_num_gprs; i++)
277 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
278
279 /* Floating-point registers. */
280 if (tdep->ppc_fp0_regnum >= 0)
281 for (i = 0; i < ppc_num_fprs; i++)
282 set_sim_regno (sim_regno,
283 tdep->ppc_fp0_regnum + i,
284 sim_ppc_f0_regnum + i);
285 if (tdep->ppc_fpscr_regnum >= 0)
286 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
287
288 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
289 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
290 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
291
292 /* Segment registers. */
7cc46491
DJ		 293 for (i = 0; i < ppc_num_srs; i++)
294 {
295 int gdb_regno;
296
297 gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1);
298 if (gdb_regno >= 0)
299 set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i);
300 }
9f643768
JB		 301
302 /* Altivec registers. */
303 if (tdep->ppc_vr0_regnum >= 0)
304 {
305 for (i = 0; i < ppc_num_vrs; i++)
306 set_sim_regno (sim_regno,
307 tdep->ppc_vr0_regnum + i,
308 sim_ppc_vr0_regnum + i);
309
310 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
311 we can treat this more like the other cases. */
312 set_sim_regno (sim_regno,
313 tdep->ppc_vr0_regnum + ppc_num_vrs,
314 sim_ppc_vscr_regnum);
315 }
316 /* vsave is a special-purpose register, so the code below handles it. */
317
318 /* SPE APU (E500) registers. */
6ced10dd
JB		 319 if (tdep->ppc_ev0_upper_regnum >= 0)
320 for (i = 0; i < ppc_num_gprs; i++)
321 set_sim_regno (sim_regno,
322 tdep->ppc_ev0_upper_regnum + i,
323 sim_ppc_rh0_regnum + i);
9f643768
JB		 324 if (tdep->ppc_acc_regnum >= 0)
325 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
326 /* spefscr is a special-purpose register, so the code below handles it. */
327
7cc46491 328#ifdef WITH_SIM
9f643768
JB		 329 /* Now handle all special-purpose registers. Verify that they
330 haven't mistakenly been assigned numbers by any of the above
7cc46491
DJ		 331 code. */
332 for (i = 0; i < sim_ppc_num_sprs; i++)
333 {
334 const char *spr_name = sim_spr_register_name (i);
335 int gdb_regno = -1;
336
337 if (spr_name != NULL)
338 gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1);
339
340 if (gdb_regno != -1)
341 set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i);
342 }
343#endif
9f643768
JB		 344
345 /* Drop the initialized array into place. */
346 tdep->sim_regno = sim_regno;
347}
348
09991fa0
JB		 349
350/* Given a GDB register number REG, return the corresponding SIM
351 register number. */
9f643768 352static int
e7faf938 353rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg)
9f643768 354{
e7faf938 355 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9f643768
JB		 356 int sim_regno;
357
7cc46491 358 if (tdep->sim_regno == NULL)
e7faf938 359 init_sim_regno_table (gdbarch);
7cc46491 360
f57d151a 361 gdb_assert (0 <= reg
e7faf938
MD		 362 && reg <= gdbarch_num_regs (gdbarch)
363 + gdbarch_num_pseudo_regs (gdbarch));
9f643768
JB		 364 sim_regno = tdep->sim_regno[reg];
365
366 if (sim_regno >= 0)
367 return sim_regno;
368 else
369 return LEGACY_SIM_REGNO_IGNORE;
370}
371
d195bc9f
MK		 372\f
373
374/* Register set support functions. */
375
f2db237a
AM		 376/* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
377 Write the register to REGCACHE. */
378
7284e1be 379void
d195bc9f 380ppc_supply_reg (struct regcache *regcache, int regnum,
f2db237a 381 const gdb_byte *regs, size_t offset, int regsize)
d195bc9f
MK		 382{
383 if (regnum != -1 && offset != -1)
f2db237a
AM		 384 {
385 if (regsize > 4)
386 {
387 struct gdbarch *gdbarch = get_regcache_arch (regcache);
388 int gdb_regsize = register_size (gdbarch, regnum);
389 if (gdb_regsize < regsize
390 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
391 offset += regsize - gdb_regsize;
392 }
393 regcache_raw_supply (regcache, regnum, regs + offset);
394 }
d195bc9f
MK		 395}
396
f2db237a
AM		 397/* Read register REGNUM from REGCACHE and store to REGS + OFFSET
398 in a field REGSIZE wide. Zero pad as necessary. */
399
7284e1be 400void
d195bc9f 401ppc_collect_reg (const struct regcache *regcache, int regnum,
f2db237a 402 gdb_byte *regs, size_t offset, int regsize)
d195bc9f
MK		 403{
404 if (regnum != -1 && offset != -1)
f2db237a
AM		 405 {
406 if (regsize > 4)
407 {
408 struct gdbarch *gdbarch = get_regcache_arch (regcache);
409 int gdb_regsize = register_size (gdbarch, regnum);
410 if (gdb_regsize < regsize)
411 {
412 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
413 {
414 memset (regs + offset, 0, regsize - gdb_regsize);
415 offset += regsize - gdb_regsize;
416 }
417 else
418 memset (regs + offset + regsize - gdb_regsize, 0,
419 regsize - gdb_regsize);
420 }
421 }
422 regcache_raw_collect (regcache, regnum, regs + offset);
423 }
d195bc9f
MK		 424}
425
f2db237a
AM		 426static int
427ppc_greg_offset (struct gdbarch *gdbarch,
428 struct gdbarch_tdep *tdep,
429 const struct ppc_reg_offsets *offsets,
430 int regnum,
431 int *regsize)
432{
433 *regsize = offsets->gpr_size;
434 if (regnum >= tdep->ppc_gp0_regnum
435 && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs)
436 return (offsets->r0_offset
437 + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size);
438
439 if (regnum == gdbarch_pc_regnum (gdbarch))
440 return offsets->pc_offset;
441
442 if (regnum == tdep->ppc_ps_regnum)
443 return offsets->ps_offset;
444
445 if (regnum == tdep->ppc_lr_regnum)
446 return offsets->lr_offset;
447
448 if (regnum == tdep->ppc_ctr_regnum)
449 return offsets->ctr_offset;
450
451 *regsize = offsets->xr_size;
452 if (regnum == tdep->ppc_cr_regnum)
453 return offsets->cr_offset;
454
455 if (regnum == tdep->ppc_xer_regnum)
456 return offsets->xer_offset;
457
458 if (regnum == tdep->ppc_mq_regnum)
459 return offsets->mq_offset;
460
461 return -1;
462}
463
464static int
465ppc_fpreg_offset (struct gdbarch_tdep *tdep,
466 const struct ppc_reg_offsets *offsets,
467 int regnum)
468{
469 if (regnum >= tdep->ppc_fp0_regnum
470 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs)
471 return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8;
472
473 if (regnum == tdep->ppc_fpscr_regnum)
474 return offsets->fpscr_offset;
475
476 return -1;
477}
478
06caf7d2
CES		 479static int
480ppc_vrreg_offset (struct gdbarch_tdep *tdep,
481 const struct ppc_reg_offsets *offsets,
482 int regnum)
483{
484 if (regnum >= tdep->ppc_vr0_regnum
485 && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs)
486 return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16;
487
488 if (regnum == tdep->ppc_vrsave_regnum - 1)
489 return offsets->vscr_offset;
490
491 if (regnum == tdep->ppc_vrsave_regnum)
492 return offsets->vrsave_offset;
493
494 return -1;
495}
496
d195bc9f
MK		 497/* Supply register REGNUM in the general-purpose register set REGSET
498 from the buffer specified by GREGS and LEN to register cache
499 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
500
501void
502ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
503 int regnum, const void *gregs, size_t len)
504{
505 struct gdbarch *gdbarch = get_regcache_arch (regcache);
506 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
507 const struct ppc_reg_offsets *offsets = regset->descr;
508 size_t offset;
f2db237a 509 int regsize;
d195bc9f 510
f2db237a 511 if (regnum == -1)
d195bc9f 512 {
f2db237a
AM		 513 int i;
514 int gpr_size = offsets->gpr_size;
515
516 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
517 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
518 i++, offset += gpr_size)
519 ppc_supply_reg (regcache, i, gregs, offset, gpr_size);
520
521 ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch),
522 gregs, offsets->pc_offset, gpr_size);
523 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
524 gregs, offsets->ps_offset, gpr_size);
525 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
526 gregs, offsets->lr_offset, gpr_size);
527 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
528 gregs, offsets->ctr_offset, gpr_size);
529 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
530 gregs, offsets->cr_offset, offsets->xr_size);
531 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
532 gregs, offsets->xer_offset, offsets->xr_size);
533 ppc_supply_reg (regcache, tdep->ppc_mq_regnum,
534 gregs, offsets->mq_offset, offsets->xr_size);
535 return;
d195bc9f
MK		 536 }
537
f2db237a
AM		 538 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
539 ppc_supply_reg (regcache, regnum, gregs, offset, regsize);
d195bc9f
MK		 540}
541
542/* Supply register REGNUM in the floating-point register set REGSET
543 from the buffer specified by FPREGS and LEN to register cache
544 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
545
546void
547ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
548 int regnum, const void *fpregs, size_t len)
549{
550 struct gdbarch *gdbarch = get_regcache_arch (regcache);
f2db237a
AM		 551 struct gdbarch_tdep *tdep;
552 const struct ppc_reg_offsets *offsets;
d195bc9f 553 size_t offset;
d195bc9f 554
f2db237a
AM		 555 if (!ppc_floating_point_unit_p (gdbarch))
556 return;
383f0f5b 557
f2db237a
AM		 558 tdep = gdbarch_tdep (gdbarch);
559 offsets = regset->descr;
560 if (regnum == -1)
d195bc9f 561 {
f2db237a
AM		 562 int i;
563
564 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
565 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
566 i++, offset += 8)
567 ppc_supply_reg (regcache, i, fpregs, offset, 8);
568
569 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
570 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
571 return;
d195bc9f
MK		 572 }
573
f2db237a
AM		 574 offset = ppc_fpreg_offset (tdep, offsets, regnum);
575 ppc_supply_reg (regcache, regnum, fpregs, offset,
576 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
d195bc9f
MK		 577}
578
604c2f83
LM		 579/* Supply register REGNUM in the VSX register set REGSET
580 from the buffer specified by VSXREGS and LEN to register cache
581 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
582
583void
584ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache,
585 int regnum, const void *vsxregs, size_t len)
586{
587 struct gdbarch *gdbarch = get_regcache_arch (regcache);
588 struct gdbarch_tdep *tdep;
589
590 if (!ppc_vsx_support_p (gdbarch))
591 return;
592
593 tdep = gdbarch_tdep (gdbarch);
594
595 if (regnum == -1)
596 {
597 int i;
598
599 for (i = tdep->ppc_vsr0_upper_regnum;
600 i < tdep->ppc_vsr0_upper_regnum + 32;
601 i++)
602 ppc_supply_reg (regcache, i, vsxregs, 0, 8);
603
604 return;
605 }
606 else
607 ppc_supply_reg (regcache, regnum, vsxregs, 0, 8);
608}
609
06caf7d2
CES		 610/* Supply register REGNUM in the Altivec register set REGSET
611 from the buffer specified by VRREGS and LEN to register cache
612 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
613
614void
615ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache,
616 int regnum, const void *vrregs, size_t len)
617{
618 struct gdbarch *gdbarch = get_regcache_arch (regcache);
619 struct gdbarch_tdep *tdep;
620 const struct ppc_reg_offsets *offsets;
621 size_t offset;
622
623 if (!ppc_altivec_support_p (gdbarch))
624 return;
625
626 tdep = gdbarch_tdep (gdbarch);
627 offsets = regset->descr;
628 if (regnum == -1)
629 {
630 int i;
631
632 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
633 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
634 i++, offset += 16)
635 ppc_supply_reg (regcache, i, vrregs, offset, 16);
636
637 ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
638 vrregs, offsets->vscr_offset, 4);
639
640 ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum,
641 vrregs, offsets->vrsave_offset, 4);
642 return;
643 }
644
645 offset = ppc_vrreg_offset (tdep, offsets, regnum);
646 if (regnum != tdep->ppc_vrsave_regnum
647 && regnum != tdep->ppc_vrsave_regnum - 1)
648 ppc_supply_reg (regcache, regnum, vrregs, offset, 16);
649 else
650 ppc_supply_reg (regcache, regnum,
651 vrregs, offset, 4);
652}
653
d195bc9f 654/* Collect register REGNUM in the general-purpose register set
f2db237a 655 REGSET from register cache REGCACHE into the buffer specified by
d195bc9f
MK		 656 GREGS and LEN. If REGNUM is -1, do this for all registers in
657 REGSET. */
658
659void
660ppc_collect_gregset (const struct regset *regset,
661 const struct regcache *regcache,
662 int regnum, void *gregs, size_t len)
663{
664 struct gdbarch *gdbarch = get_regcache_arch (regcache);
665 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
666 const struct ppc_reg_offsets *offsets = regset->descr;
667 size_t offset;
f2db237a 668 int regsize;
d195bc9f 669
f2db237a 670 if (regnum == -1)
d195bc9f 671 {
f2db237a
AM		 672 int i;
673 int gpr_size = offsets->gpr_size;
674
675 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
676 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
677 i++, offset += gpr_size)
678 ppc_collect_reg (regcache, i, gregs, offset, gpr_size);
679
680 ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch),
681 gregs, offsets->pc_offset, gpr_size);
682 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
683 gregs, offsets->ps_offset, gpr_size);
684 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
685 gregs, offsets->lr_offset, gpr_size);
686 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
687 gregs, offsets->ctr_offset, gpr_size);
688 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
689 gregs, offsets->cr_offset, offsets->xr_size);
690 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
691 gregs, offsets->xer_offset, offsets->xr_size);
692 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
693 gregs, offsets->mq_offset, offsets->xr_size);
694 return;
d195bc9f
MK		 695 }
696
f2db237a
AM		 697 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
698 ppc_collect_reg (regcache, regnum, gregs, offset, regsize);
d195bc9f
MK		 699}
700
701/* Collect register REGNUM in the floating-point register set
f2db237a 702 REGSET from register cache REGCACHE into the buffer specified by
d195bc9f
MK		 703 FPREGS and LEN. If REGNUM is -1, do this for all registers in
704 REGSET. */
705
706void
707ppc_collect_fpregset (const struct regset *regset,
708 const struct regcache *regcache,
709 int regnum, void *fpregs, size_t len)
710{
711 struct gdbarch *gdbarch = get_regcache_arch (regcache);
f2db237a
AM		 712 struct gdbarch_tdep *tdep;
713 const struct ppc_reg_offsets *offsets;
d195bc9f 714 size_t offset;
d195bc9f 715
f2db237a
AM		 716 if (!ppc_floating_point_unit_p (gdbarch))
717 return;
383f0f5b 718
f2db237a
AM		 719 tdep = gdbarch_tdep (gdbarch);
720 offsets = regset->descr;
721 if (regnum == -1)
d195bc9f 722 {
f2db237a
AM		 723 int i;
724
725 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
726 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
727 i++, offset += 8)
728 ppc_collect_reg (regcache, i, fpregs, offset, 8);
729
730 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
731 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
732 return;
d195bc9f
MK		 733 }
734
f2db237a
AM		 735 offset = ppc_fpreg_offset (tdep, offsets, regnum);
736 ppc_collect_reg (regcache, regnum, fpregs, offset,
737 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
d195bc9f 738}
06caf7d2 739
604c2f83
LM		 740/* Collect register REGNUM in the VSX register set
741 REGSET from register cache REGCACHE into the buffer specified by
742 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
743 REGSET. */
744
745void
746ppc_collect_vsxregset (const struct regset *regset,
747 const struct regcache *regcache,
748 int regnum, void *vsxregs, size_t len)
749{
750 struct gdbarch *gdbarch = get_regcache_arch (regcache);
751 struct gdbarch_tdep *tdep;
752
753 if (!ppc_vsx_support_p (gdbarch))
754 return;
755
756 tdep = gdbarch_tdep (gdbarch);
757
758 if (regnum == -1)
759 {
760 int i;
761
762 for (i = tdep->ppc_vsr0_upper_regnum;
763 i < tdep->ppc_vsr0_upper_regnum + 32;
764 i++)
765 ppc_collect_reg (regcache, i, vsxregs, 0, 8);
766
767 return;
768 }
769 else
770 ppc_collect_reg (regcache, regnum, vsxregs, 0, 8);
771}
772
773
06caf7d2
CES		 774/* Collect register REGNUM in the Altivec register set
775 REGSET from register cache REGCACHE into the buffer specified by
776 VRREGS and LEN. If REGNUM is -1, do this for all registers in
777 REGSET. */
778
779void
780ppc_collect_vrregset (const struct regset *regset,
781 const struct regcache *regcache,
782 int regnum, void *vrregs, size_t len)
783{
784 struct gdbarch *gdbarch = get_regcache_arch (regcache);
785 struct gdbarch_tdep *tdep;
786 const struct ppc_reg_offsets *offsets;
787 size_t offset;
788
789 if (!ppc_altivec_support_p (gdbarch))
790 return;
791
792 tdep = gdbarch_tdep (gdbarch);
793 offsets = regset->descr;
794 if (regnum == -1)
795 {
796 int i;
797
798 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
799 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
800 i++, offset += 16)
801 ppc_collect_reg (regcache, i, vrregs, offset, 16);
802
803 ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
804 vrregs, offsets->vscr_offset, 4);
805
806 ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum,
807 vrregs, offsets->vrsave_offset, 4);
808 return;
809 }
810
811 offset = ppc_vrreg_offset (tdep, offsets, regnum);
812 if (regnum != tdep->ppc_vrsave_regnum
813 && regnum != tdep->ppc_vrsave_regnum - 1)
814 ppc_collect_reg (regcache, regnum, vrregs, offset, 16);
815 else
816 ppc_collect_reg (regcache, regnum,
817 vrregs, offset, 4);
818}
d195bc9f 819\f
0a613259 820
0d1243d9
PG		 821static int
822insn_changes_sp_or_jumps (unsigned long insn)
823{
824 int opcode = (insn >> 26) & 0x03f;
825 int sd = (insn >> 21) & 0x01f;
826 int a = (insn >> 16) & 0x01f;
827 int subcode = (insn >> 1) & 0x3ff;
828
829 /* Changes the stack pointer. */
830
831 /* NOTE: There are many ways to change the value of a given register.
832 The ways below are those used when the register is R1, the SP,
833 in a funtion's epilogue. */
834
835 if (opcode == 31 && subcode == 444 && a == 1)
836 return 1; /* mr R1,Rn */
837 if (opcode == 14 && sd == 1)
838 return 1; /* addi R1,Rn,simm */
839 if (opcode == 58 && sd == 1)
840 return 1; /* ld R1,ds(Rn) */
841
842 /* Transfers control. */
843
844 if (opcode == 18)
845 return 1; /* b */
846 if (opcode == 16)
847 return 1; /* bc */
848 if (opcode == 19 && subcode == 16)
849 return 1; /* bclr */
850 if (opcode == 19 && subcode == 528)
851 return 1; /* bcctr */
852
853 return 0;
854}
855
856/* Return true if we are in the function's epilogue, i.e. after the
857 instruction that destroyed the function's stack frame.
858
859 1) scan forward from the point of execution:
860 a) If you find an instruction that modifies the stack pointer
861 or transfers control (except a return), execution is not in
862 an epilogue, return.
863 b) Stop scanning if you find a return instruction or reach the
864 end of the function or reach the hard limit for the size of
865 an epilogue.
866 2) scan backward from the point of execution:
867 a) If you find an instruction that modifies the stack pointer,
868 execution *is* in an epilogue, return.
869 b) Stop scanning if you reach an instruction that transfers
870 control or the beginning of the function or reach the hard
871 limit for the size of an epilogue. */
872
873static int
874rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
875{
46a9b8ed 876 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 877 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
0d1243d9
PG		 878 bfd_byte insn_buf[PPC_INSN_SIZE];
879 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
880 unsigned long insn;
881 struct frame_info *curfrm;
882
883 /* Find the search limits based on function boundaries and hard limit. */
884
885 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
886 return 0;
887
888 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
889 if (epilogue_start < func_start) epilogue_start = func_start;
890
891 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
892 if (epilogue_end > func_end) epilogue_end = func_end;
893
894 curfrm = get_current_frame ();
895
896 /* Scan forward until next 'blr'. */
897
898 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
899 {
900 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
901 return 0;
e17a4113 902 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
0d1243d9
PG		 903 if (insn == 0x4e800020)
904 break;
46a9b8ed
DJ		 905 /* Assume a bctr is a tail call unless it points strictly within
906 this function. */
907 if (insn == 0x4e800420)
908 {
909 CORE_ADDR ctr = get_frame_register_unsigned (curfrm,
910 tdep->ppc_ctr_regnum);
911 if (ctr > func_start && ctr < func_end)
912 return 0;
913 else
914 break;
915 }
0d1243d9
PG		 916 if (insn_changes_sp_or_jumps (insn))
917 return 0;
918 }
919
920 /* Scan backward until adjustment to stack pointer (R1). */
921
922 for (scan_pc = pc - PPC_INSN_SIZE;
923 scan_pc >= epilogue_start;
924 scan_pc -= PPC_INSN_SIZE)
925 {
926 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
927 return 0;
e17a4113 928 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
0d1243d9
PG		 929 if (insn_changes_sp_or_jumps (insn))
930 return 1;
931 }
932
933 return 0;
934}
935
143985b7 936/* Get the ith function argument for the current function. */
b9362cc7 937static CORE_ADDR
143985b7
AF		 938rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
939 struct type *type)
940{
50fd1280 941 return get_frame_register_unsigned (frame, 3 + argi);
143985b7
AF		 942}
943
c906108c
SS		 944/* Sequence of bytes for breakpoint instruction. */
945
44d100c3 946static const unsigned char *
67d57894
MD		 947rs6000_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
948 int *bp_size)
c906108c 949{
aaab4dba
AC		 950 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
951 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
c906108c 952 *bp_size = 4;
67d57894 953 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
c906108c
SS		 954 return big_breakpoint;
955 else
956 return little_breakpoint;
957}
958
f74c6cad
LM		 959/* Instruction masks for displaced stepping. */
960#define BRANCH_MASK 0xfc000000
961#define BP_MASK 0xFC0007FE
962#define B_INSN 0x48000000
963#define BC_INSN 0x40000000
964#define BXL_INSN 0x4c000000
965#define BP_INSN 0x7C000008
966
967/* Fix up the state of registers and memory after having single-stepped
968 a displaced instruction. */
63807e1d 969static void
f74c6cad 970ppc_displaced_step_fixup (struct gdbarch *gdbarch,
63807e1d
PA		 971 struct displaced_step_closure *closure,
972 CORE_ADDR from, CORE_ADDR to,
973 struct regcache *regs)
f74c6cad 974{
e17a4113 975 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
f74c6cad
LM		 976 /* Since we use simple_displaced_step_copy_insn, our closure is a
977 copy of the instruction. */
978 ULONGEST insn = extract_unsigned_integer ((gdb_byte *) closure,
e17a4113 979 PPC_INSN_SIZE, byte_order);
f74c6cad
LM		 980 ULONGEST opcode = 0;
981 /* Offset for non PC-relative instructions. */
982 LONGEST offset = PPC_INSN_SIZE;
983
984 opcode = insn & BRANCH_MASK;
985
986 if (debug_displaced)
987 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 988 "displaced: (ppc) fixup (%s, %s)\n",
989 paddress (gdbarch, from), paddress (gdbarch, to));
f74c6cad
LM		 990
991
992 /* Handle PC-relative branch instructions. */
993 if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN)
994 {
a4fafde3 995 ULONGEST current_pc;
f74c6cad
LM		 996
997 /* Read the current PC value after the instruction has been executed
998 in a displaced location. Calculate the offset to be applied to the
999 original PC value before the displaced stepping. */
1000 regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1001 &current_pc);
1002 offset = current_pc - to;
1003
1004 if (opcode != BXL_INSN)
1005 {
1006 /* Check for AA bit indicating whether this is an absolute
1007 addressing or PC-relative (1: absolute, 0: relative). */
1008 if (!(insn & 0x2))
1009 {
1010 /* PC-relative addressing is being used in the branch. */
1011 if (debug_displaced)
1012 fprintf_unfiltered
1013 (gdb_stdlog,
5af949e3
UW		 1014 "displaced: (ppc) branch instruction: %s\n"
1015 "displaced: (ppc) adjusted PC from %s to %s\n",
1016 paddress (gdbarch, insn), paddress (gdbarch, current_pc),
1017 paddress (gdbarch, from + offset));
f74c6cad 1018
0df8b418
MS		 1019 regcache_cooked_write_unsigned (regs,
1020 gdbarch_pc_regnum (gdbarch),
f74c6cad
LM		 1021 from + offset);
1022 }
1023 }
1024 else
1025 {
1026 /* If we're here, it means we have a branch to LR or CTR. If the
1027 branch was taken, the offset is probably greater than 4 (the next
1028 instruction), so it's safe to assume that an offset of 4 means we
1029 did not take the branch. */
1030 if (offset == PPC_INSN_SIZE)
1031 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1032 from + PPC_INSN_SIZE);
1033 }
1034
1035 /* Check for LK bit indicating whether we should set the link
1036 register to point to the next instruction
1037 (1: Set, 0: Don't set). */
1038 if (insn & 0x1)
1039 {
1040 /* Link register needs to be set to the next instruction's PC. */
1041 regcache_cooked_write_unsigned (regs,
1042 gdbarch_tdep (gdbarch)->ppc_lr_regnum,
1043 from + PPC_INSN_SIZE);
1044 if (debug_displaced)
1045 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 1046 "displaced: (ppc) adjusted LR to %s\n",
1047 paddress (gdbarch, from + PPC_INSN_SIZE));
f74c6cad
LM		 1048
1049 }
1050 }
1051 /* Check for breakpoints in the inferior. If we've found one, place the PC
1052 right at the breakpoint instruction. */
1053 else if ((insn & BP_MASK) == BP_INSN)
1054 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from);
1055 else
1056 /* Handle any other instructions that do not fit in the categories above. */
1057 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1058 from + offset);
1059}
c906108c 1060
99e40580
UW		 1061/* Always use hardware single-stepping to execute the
1062 displaced instruction. */
1063static int
1064ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
1065 struct displaced_step_closure *closure)
1066{
1067 return 1;
1068}
1069
ce5eab59
UW		 1070/* Instruction masks used during single-stepping of atomic sequences. */
1071#define LWARX_MASK 0xfc0007fe
1072#define LWARX_INSTRUCTION 0x7c000028
1073#define LDARX_INSTRUCTION 0x7c0000A8
1074#define STWCX_MASK 0xfc0007ff
1075#define STWCX_INSTRUCTION 0x7c00012d
1076#define STDCX_INSTRUCTION 0x7c0001ad
ce5eab59
UW		 1077
1078/* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1079 instruction and ending with a STWCX/STDCX instruction. If such a sequence
1080 is found, attempt to step through it. A breakpoint is placed at the end of
1081 the sequence. */
1082
4a7622d1
UW		 1083int
1084ppc_deal_with_atomic_sequence (struct frame_info *frame)
ce5eab59 1085{
a6d9a66e 1086 struct gdbarch *gdbarch = get_frame_arch (frame);
6c95b8df 1087 struct address_space *aspace = get_frame_address_space (frame);
e17a4113 1088 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
0b1b3e42 1089 CORE_ADDR pc = get_frame_pc (frame);
ce5eab59
UW		 1090 CORE_ADDR breaks[2] = {-1, -1};
1091 CORE_ADDR loc = pc;
24d45690 1092 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
e17a4113 1093 int insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
ce5eab59
UW		 1094 int insn_count;
1095 int index;
1096 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
1097 const int atomic_sequence_length = 16; /* Instruction sequence length. */
24d45690 1098 int opcode; /* Branch instruction's OPcode. */
ce5eab59
UW		 1099 int bc_insn_count = 0; /* Conditional branch instruction count. */
1100
1101 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1102 if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
1103 && (insn & LWARX_MASK) != LDARX_INSTRUCTION)
1104 return 0;
1105
1106 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1107 instructions. */
1108 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
1109 {
1110 loc += PPC_INSN_SIZE;
e17a4113 1111 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
ce5eab59
UW		 1112
1113 /* Assume that there is at most one conditional branch in the atomic
1114 sequence. If a conditional branch is found, put a breakpoint in
1115 its destination address. */
f74c6cad 1116 if ((insn & BRANCH_MASK) == BC_INSN)
ce5eab59 1117 {
a3769e0c
AM		 1118 int immediate = ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1119 int absolute = insn & 2;
4a7622d1 1120
ce5eab59
UW		 1121 if (bc_insn_count >= 1)
1122 return 0; /* More than one conditional branch found, fallback
1123 to the standard single-step code. */
4a7622d1
UW		 1124
1125 if (absolute)
1126 breaks[1] = immediate;
1127 else
a3769e0c 1128 breaks[1] = loc + immediate;
4a7622d1
UW		 1129
1130 bc_insn_count++;
1131 last_breakpoint++;
ce5eab59
UW		 1132 }
1133
1134 if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
1135 || (insn & STWCX_MASK) == STDCX_INSTRUCTION)
1136 break;
1137 }
1138
1139 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1140 if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
1141 && (insn & STWCX_MASK) != STDCX_INSTRUCTION)
1142 return 0;
1143
24d45690 1144 closing_insn = loc;
ce5eab59 1145 loc += PPC_INSN_SIZE;
e17a4113 1146 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
ce5eab59
UW		 1147
1148 /* Insert a breakpoint right after the end of the atomic sequence. */
1149 breaks[0] = loc;
1150
24d45690 1151 /* Check for duplicated breakpoints. Check also for a breakpoint
a3769e0c
AM		 1152 placed (branch instruction's destination) anywhere in sequence. */
1153 if (last_breakpoint
1154 && (breaks[1] == breaks[0]
1155 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
ce5eab59
UW		 1156 last_breakpoint = 0;
1157
1158 /* Effectively inserts the breakpoints. */
1159 for (index = 0; index <= last_breakpoint; index++)
6c95b8df 1160 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
ce5eab59
UW		 1161
1162 return 1;
1163}
1164
c906108c 1165
c906108c
SS		 1166#define SIGNED_SHORT(x) \
1167 ((sizeof (short) == 2) \
1168 ? ((int)(short)(x)) \
1169 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1170
1171#define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1172
55d05f3b
KB		 1173/* Limit the number of skipped non-prologue instructions, as the examining
1174 of the prologue is expensive. */
1175static int max_skip_non_prologue_insns = 10;
1176
773df3e5
JB		 1177/* Return nonzero if the given instruction OP can be part of the prologue
1178 of a function and saves a parameter on the stack. FRAMEP should be
1179 set if one of the previous instructions in the function has set the
1180 Frame Pointer. */
1181
1182static int
1183store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
1184{
1185 /* Move parameters from argument registers to temporary register. */
1186 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1187 {
1188 /* Rx must be scratch register r0. */
1189 const int rx_regno = (op >> 16) & 31;
1190 /* Ry: Only r3 - r10 are used for parameter passing. */
1191 const int ry_regno = GET_SRC_REG (op);
1192
1193 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
1194 {
1195 *r0_contains_arg = 1;
1196 return 1;
1197 }
1198 else
1199 return 0;
1200 }
1201
1202 /* Save a General Purpose Register on stack. */
1203
1204 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1205 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1206 {
1207 /* Rx: Only r3 - r10 are used for parameter passing. */
1208 const int rx_regno = GET_SRC_REG (op);
1209
1210 return (rx_regno >= 3 && rx_regno <= 10);
1211 }
1212
1213 /* Save a General Purpose Register on stack via the Frame Pointer. */
1214
1215 if (framep &&
1216 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1217 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1218 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1219 {
1220 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1221 However, the compiler sometimes uses r0 to hold an argument. */
1222 const int rx_regno = GET_SRC_REG (op);
1223
1224 return ((rx_regno >= 3 && rx_regno <= 10)
1225 || (rx_regno == 0 && *r0_contains_arg));
1226 }
1227
1228 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1229 {
1230 /* Only f2 - f8 are used for parameter passing. */
1231 const int src_regno = GET_SRC_REG (op);
1232
1233 return (src_regno >= 2 && src_regno <= 8);
1234 }
1235
1236 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1237 {
1238 /* Only f2 - f8 are used for parameter passing. */
1239 const int src_regno = GET_SRC_REG (op);
1240
1241 return (src_regno >= 2 && src_regno <= 8);
1242 }
1243
1244 /* Not an insn that saves a parameter on stack. */
1245 return 0;
1246}
55d05f3b 1247
3c77c82a
DJ		 1248/* Assuming that INSN is a "bl" instruction located at PC, return
1249 nonzero if the destination of the branch is a "blrl" instruction.
1250
1251 This sequence is sometimes found in certain function prologues.
1252 It allows the function to load the LR register with a value that
1253 they can use to access PIC data using PC-relative offsets. */
1254
1255static int
e17a4113 1256bl_to_blrl_insn_p (CORE_ADDR pc, int insn, enum bfd_endian byte_order)
3c77c82a 1257{
0b1b3e42
UW		 1258 CORE_ADDR dest;
1259 int immediate;
1260 int absolute;
3c77c82a
DJ		 1261 int dest_insn;
1262
0b1b3e42
UW		 1263 absolute = (int) ((insn >> 1) & 1);
1264 immediate = ((insn & ~3) << 6) >> 6;
1265 if (absolute)
1266 dest = immediate;
1267 else
1268 dest = pc + immediate;
1269
e17a4113 1270 dest_insn = read_memory_integer (dest, 4, byte_order);
3c77c82a
DJ		 1271 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
1272 return 1;
1273
1274 return 0;
1275}
1276
0df8b418 1277/* Masks for decoding a branch-and-link (bl) instruction.
8ab3d180
KB		 1278
1279 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1280 The former is anded with the opcode in question; if the result of
1281 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1282 question is a ``bl'' instruction.
1283
1284 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1285 the branch displacement. */
1286
1287#define BL_MASK 0xfc000001
1288#define BL_INSTRUCTION 0x48000001
1289#define BL_DISPLACEMENT_MASK 0x03fffffc
1290
de9f48f0 1291static unsigned long
e17a4113 1292rs6000_fetch_instruction (struct gdbarch *gdbarch, const CORE_ADDR pc)
de9f48f0 1293{
e17a4113 1294 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
de9f48f0
JG		 1295 gdb_byte buf[4];
1296 unsigned long op;
1297
1298 /* Fetch the instruction and convert it to an integer. */
1299 if (target_read_memory (pc, buf, 4))
1300 return 0;
e17a4113 1301 op = extract_unsigned_integer (buf, 4, byte_order);
de9f48f0
JG		 1302
1303 return op;
1304}
1305
1306/* GCC generates several well-known sequences of instructions at the begining
1307 of each function prologue when compiling with -fstack-check. If one of
1308 such sequences starts at START_PC, then return the address of the
1309 instruction immediately past this sequence. Otherwise, return START_PC. */
1310
1311static CORE_ADDR
e17a4113 1312rs6000_skip_stack_check (struct gdbarch *gdbarch, const CORE_ADDR start_pc)
de9f48f0
JG		 1313{
1314 CORE_ADDR pc = start_pc;
e17a4113 1315 unsigned long op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1316
1317 /* First possible sequence: A small number of probes.
1318 stw 0, -<some immediate>(1)
0df8b418 1319 [repeat this instruction any (small) number of times]. */
de9f48f0
JG		 1320
1321 if ((op & 0xffff0000) == 0x90010000)
1322 {
1323 while ((op & 0xffff0000) == 0x90010000)
1324 {
1325 pc = pc + 4;
e17a4113 1326 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1327 }
1328 return pc;
1329 }
1330
1331 /* Second sequence: A probing loop.
1332 addi 12,1,-<some immediate>
1333 lis 0,-<some immediate>
1334 [possibly ori 0,0,<some immediate>]
1335 add 0,12,0
1336 cmpw 0,12,0
1337 beq 0,<disp>
1338 addi 12,12,-<some immediate>
1339 stw 0,0(12)
1340 b <disp>
0df8b418 1341 [possibly one last probe: stw 0,<some immediate>(12)]. */
de9f48f0
JG		 1342
1343 while (1)
1344 {
1345 /* addi 12,1,-<some immediate> */
1346 if ((op & 0xffff0000) != 0x39810000)
1347 break;
1348
1349 /* lis 0,-<some immediate> */
1350 pc = pc + 4;
e17a4113 1351 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1352 if ((op & 0xffff0000) != 0x3c000000)
1353 break;
1354
1355 pc = pc + 4;
e17a4113 1356 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1357 /* [possibly ori 0,0,<some immediate>] */
1358 if ((op & 0xffff0000) == 0x60000000)
1359 {
1360 pc = pc + 4;
e17a4113 1361 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1362 }
1363 /* add 0,12,0 */
1364 if (op != 0x7c0c0214)
1365 break;
1366
1367 /* cmpw 0,12,0 */
1368 pc = pc + 4;
e17a4113 1369 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1370 if (op != 0x7c0c0000)
1371 break;
1372
1373 /* beq 0,<disp> */
1374 pc = pc + 4;
e17a4113 1375 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1376 if ((op & 0xff9f0001) != 0x41820000)
1377 break;
1378
1379 /* addi 12,12,-<some immediate> */
1380 pc = pc + 4;
e17a4113 1381 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1382 if ((op & 0xffff0000) != 0x398c0000)
1383 break;
1384
1385 /* stw 0,0(12) */
1386 pc = pc + 4;
e17a4113 1387 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1388 if (op != 0x900c0000)
1389 break;
1390
1391 /* b <disp> */
1392 pc = pc + 4;
e17a4113 1393 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1394 if ((op & 0xfc000001) != 0x48000000)
1395 break;
1396
0df8b418 1397 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
de9f48f0 1398 pc = pc + 4;
e17a4113 1399 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1400 if ((op & 0xffff0000) == 0x900c0000)
1401 {
1402 pc = pc + 4;
e17a4113 1403 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1404 }
1405
1406 /* We found a valid stack-check sequence, return the new PC. */
1407 return pc;
1408 }
1409
1410 /* Third sequence: No probe; instead, a comparizon between the stack size
1411 limit (saved in a run-time global variable) and the current stack
1412 pointer:
1413
1414 addi 0,1,-<some immediate>
1415 lis 12,__gnat_stack_limit@ha
1416 lwz 12,__gnat_stack_limit@l(12)
1417 twllt 0,12
1418
1419 or, with a small variant in the case of a bigger stack frame:
1420 addis 0,1,<some immediate>
1421 addic 0,0,-<some immediate>
1422 lis 12,__gnat_stack_limit@ha
1423 lwz 12,__gnat_stack_limit@l(12)
1424 twllt 0,12
1425 */
1426 while (1)
1427 {
1428 /* addi 0,1,-<some immediate> */
1429 if ((op & 0xffff0000) != 0x38010000)
1430 {
1431 /* small stack frame variant not recognized; try the
1432 big stack frame variant: */
1433
1434 /* addis 0,1,<some immediate> */
1435 if ((op & 0xffff0000) != 0x3c010000)
1436 break;
1437
1438 /* addic 0,0,-<some immediate> */
1439 pc = pc + 4;
e17a4113 1440 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1441 if ((op & 0xffff0000) != 0x30000000)
1442 break;
1443 }
1444
1445 /* lis 12,<some immediate> */
1446 pc = pc + 4;
e17a4113 1447 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1448 if ((op & 0xffff0000) != 0x3d800000)
1449 break;
1450
1451 /* lwz 12,<some immediate>(12) */
1452 pc = pc + 4;
e17a4113 1453 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1454 if ((op & 0xffff0000) != 0x818c0000)
1455 break;
1456
1457 /* twllt 0,12 */
1458 pc = pc + 4;
e17a4113 1459 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1460 if ((op & 0xfffffffe) != 0x7c406008)
1461 break;
1462
1463 /* We found a valid stack-check sequence, return the new PC. */
1464 return pc;
1465 }
1466
1467 /* No stack check code in our prologue, return the start_pc. */
1468 return start_pc;
1469}
1470
6a16c029
TJB		 1471/* return pc value after skipping a function prologue and also return
1472 information about a function frame.
1473
1474 in struct rs6000_framedata fdata:
1475 - frameless is TRUE, if function does not have a frame.
1476 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1477 - offset is the initial size of this stack frame --- the amount by
1478 which we decrement the sp to allocate the frame.
1479 - saved_gpr is the number of the first saved gpr.
1480 - saved_fpr is the number of the first saved fpr.
1481 - saved_vr is the number of the first saved vr.
1482 - saved_ev is the number of the first saved ev.
1483 - alloca_reg is the number of the register used for alloca() handling.
1484 Otherwise -1.
1485 - gpr_offset is the offset of the first saved gpr from the previous frame.
1486 - fpr_offset is the offset of the first saved fpr from the previous frame.
1487 - vr_offset is the offset of the first saved vr from the previous frame.
1488 - ev_offset is the offset of the first saved ev from the previous frame.
1489 - lr_offset is the offset of the saved lr
1490 - cr_offset is the offset of the saved cr
0df8b418 1491 - vrsave_offset is the offset of the saved vrsave register. */
6a16c029 1492
7a78ae4e 1493static CORE_ADDR
be8626e0
MD		 1494skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc,
1495 struct rs6000_framedata *fdata)
c906108c
SS		 1496{
1497 CORE_ADDR orig_pc = pc;
55d05f3b 1498 CORE_ADDR last_prologue_pc = pc;
6be8bc0c 1499 CORE_ADDR li_found_pc = 0;
50fd1280 1500 gdb_byte buf[4];
c906108c
SS		 1501 unsigned long op;
1502 long offset = 0;
6be8bc0c 1503 long vr_saved_offset = 0;
482ca3f5
KB		 1504 int lr_reg = -1;
1505 int cr_reg = -1;
6be8bc0c 1506 int vr_reg = -1;
96ff0de4
EZ		 1507 int ev_reg = -1;
1508 long ev_offset = 0;
6be8bc0c 1509 int vrsave_reg = -1;
c906108c
SS		 1510 int reg;
1511 int framep = 0;
1512 int minimal_toc_loaded = 0;
ddb20c56 1513 int prev_insn_was_prologue_insn = 1;
55d05f3b 1514 int num_skip_non_prologue_insns = 0;
773df3e5 1515 int r0_contains_arg = 0;
be8626e0
MD		 1516 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch);
1517 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 1518 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
c906108c 1519
ddb20c56 1520 memset (fdata, 0, sizeof (struct rs6000_framedata));
c906108c
SS		 1521 fdata->saved_gpr = -1;
1522 fdata->saved_fpr = -1;
6be8bc0c 1523 fdata->saved_vr = -1;
96ff0de4 1524 fdata->saved_ev = -1;
c906108c
SS		 1525 fdata->alloca_reg = -1;
1526 fdata->frameless = 1;
1527 fdata->nosavedpc = 1;
46a9b8ed 1528 fdata->lr_register = -1;
c906108c 1529
e17a4113 1530 pc = rs6000_skip_stack_check (gdbarch, pc);
de9f48f0
JG		 1531 if (pc >= lim_pc)
1532 pc = lim_pc;
1533
55d05f3b 1534 for (;; pc += 4)
c906108c 1535 {
ddb20c56
KB		 1536 /* Sometimes it isn't clear if an instruction is a prologue
1537 instruction or not. When we encounter one of these ambiguous
1538 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
0df8b418 1539 Otherwise, we'll assume that it really is a prologue instruction. */
ddb20c56
KB		 1540 if (prev_insn_was_prologue_insn)
1541 last_prologue_pc = pc;
55d05f3b
KB		 1542
1543 /* Stop scanning if we've hit the limit. */
4e463ff5 1544 if (pc >= lim_pc)
55d05f3b
KB		 1545 break;
1546
ddb20c56
KB		 1547 prev_insn_was_prologue_insn = 1;
1548
55d05f3b 1549 /* Fetch the instruction and convert it to an integer. */
ddb20c56
KB		 1550 if (target_read_memory (pc, buf, 4))
1551 break;
e17a4113 1552 op = extract_unsigned_integer (buf, 4, byte_order);
c906108c 1553
c5aa993b
JM		 1554 if ((op & 0xfc1fffff) == 0x7c0802a6)
1555 { /* mflr Rx */
43b1ab88
AC		 1556 /* Since shared library / PIC code, which needs to get its
1557 address at runtime, can appear to save more than one link
1558 register vis:
1559
1560 *INDENT-OFF*
1561 stwu r1,-304(r1)
1562 mflr r3
1563 bl 0xff570d0 (blrl)
1564 stw r30,296(r1)
1565 mflr r30
1566 stw r31,300(r1)
1567 stw r3,308(r1);
1568 ...
1569 *INDENT-ON*
1570
1571 remember just the first one, but skip over additional
1572 ones. */
721d14ba 1573 if (lr_reg == -1)
46a9b8ed 1574 lr_reg = (op & 0x03e00000) >> 21;
773df3e5
JB		 1575 if (lr_reg == 0)
1576 r0_contains_arg = 0;
c5aa993b 1577 continue;
c5aa993b
JM		 1578 }
1579 else if ((op & 0xfc1fffff) == 0x7c000026)
1580 { /* mfcr Rx */
98f08d3d 1581 cr_reg = (op & 0x03e00000);
773df3e5
JB		 1582 if (cr_reg == 0)
1583 r0_contains_arg = 0;
c5aa993b 1584 continue;
c906108c 1585
c906108c 1586 }
c5aa993b
JM		 1587 else if ((op & 0xfc1f0000) == 0xd8010000)
1588 { /* stfd Rx,NUM(r1) */
1589 reg = GET_SRC_REG (op);
1590 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1591 {
1592 fdata->saved_fpr = reg;
1593 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1594 }
1595 continue;
c906108c 1596
c5aa993b
JM		 1597 }
1598 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
7a78ae4e
ND		 1599 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1600 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1601 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
c5aa993b
JM		 1602 {
1603
1604 reg = GET_SRC_REG (op);
46a9b8ed
DJ		 1605 if ((op & 0xfc1f0000) == 0xbc010000)
1606 fdata->gpr_mask |= ~((1U << reg) - 1);
1607 else
1608 fdata->gpr_mask |= 1U << reg;
c5aa993b
JM		 1609 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1610 {
1611 fdata->saved_gpr = reg;
7a78ae4e 1612 if ((op & 0xfc1f0003) == 0xf8010000)
98f08d3d 1613 op &= ~3UL;
c5aa993b
JM		 1614 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1615 }
1616 continue;
c906108c 1617
ddb20c56
KB		 1618 }
1619 else if ((op & 0xffff0000) == 0x60000000)
1620 {
96ff0de4 1621 /* nop */
ddb20c56
KB		 1622 /* Allow nops in the prologue, but do not consider them to
1623 be part of the prologue unless followed by other prologue
0df8b418 1624 instructions. */
ddb20c56
KB		 1625 prev_insn_was_prologue_insn = 0;
1626 continue;
1627
c906108c 1628 }
c5aa993b
JM		 1629 else if ((op & 0xffff0000) == 0x3c000000)
1630 { /* addis 0,0,NUM, used
1631 for >= 32k frames */
1632 fdata->offset = (op & 0x0000ffff) << 16;
1633 fdata->frameless = 0;
773df3e5 1634 r0_contains_arg = 0;
c5aa993b
JM		 1635 continue;
1636
1637 }
1638 else if ((op & 0xffff0000) == 0x60000000)
1639 { /* ori 0,0,NUM, 2nd ha
1640 lf of >= 32k frames */
1641 fdata->offset |= (op & 0x0000ffff);
1642 fdata->frameless = 0;
773df3e5 1643 r0_contains_arg = 0;
c5aa993b
JM		 1644 continue;
1645
1646 }
be723e22 1647 else if (lr_reg >= 0 &&
98f08d3d
KB		 1648 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1649 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1650 /* stw Rx, NUM(r1) */
1651 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1652 /* stwu Rx, NUM(r1) */
1653 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1654 { /* where Rx == lr */
1655 fdata->lr_offset = offset;
c5aa993b 1656 fdata->nosavedpc = 0;
be723e22
MS		 1657 /* Invalidate lr_reg, but don't set it to -1.
1658 That would mean that it had never been set. */
1659 lr_reg = -2;
98f08d3d
KB		 1660 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1661 (op & 0xfc000000) == 0x90000000) /* stw */
1662 {
1663 /* Does not update r1, so add displacement to lr_offset. */
1664 fdata->lr_offset += SIGNED_SHORT (op);
1665 }
c5aa993b
JM		 1666 continue;
1667
1668 }
be723e22 1669 else if (cr_reg >= 0 &&
98f08d3d
KB		 1670 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1671 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1672 /* stw Rx, NUM(r1) */
1673 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1674 /* stwu Rx, NUM(r1) */
1675 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1676 { /* where Rx == cr */
1677 fdata->cr_offset = offset;
be723e22
MS		 1678 /* Invalidate cr_reg, but don't set it to -1.
1679 That would mean that it had never been set. */
1680 cr_reg = -2;
98f08d3d
KB		 1681 if ((op & 0xfc000003) == 0xf8000000 ||
1682 (op & 0xfc000000) == 0x90000000)
1683 {
1684 /* Does not update r1, so add displacement to cr_offset. */
1685 fdata->cr_offset += SIGNED_SHORT (op);
1686 }
c5aa993b
JM		 1687 continue;
1688
1689 }
721d14ba
DJ		 1690 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1691 {
1692 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1693 prediction bits. If the LR has already been saved, we can
1694 skip it. */
1695 continue;
1696 }
c5aa993b
JM		 1697 else if (op == 0x48000005)
1698 { /* bl .+4 used in
1699 -mrelocatable */
46a9b8ed 1700 fdata->used_bl = 1;
c5aa993b
JM		 1701 continue;
1702
1703 }
1704 else if (op == 0x48000004)
1705 { /* b .+4 (xlc) */
1706 break;
1707
c5aa993b 1708 }
6be8bc0c
EZ		 1709 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1710 in V.4 -mminimal-toc */
c5aa993b
JM		 1711 (op & 0xffff0000) == 0x3bde0000)
1712 { /* addi 30,30,foo@l */
1713 continue;
c906108c 1714
c5aa993b
JM		 1715 }
1716 else if ((op & 0xfc000001) == 0x48000001)
1717 { /* bl foo,
0df8b418 1718 to save fprs??? */
c906108c 1719
c5aa993b 1720 fdata->frameless = 0;
3c77c82a
DJ		 1721
1722 /* If the return address has already been saved, we can skip
1723 calls to blrl (for PIC). */
e17a4113 1724 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op, byte_order))
46a9b8ed
DJ		 1725 {
1726 fdata->used_bl = 1;
1727 continue;
1728 }
3c77c82a 1729
6be8bc0c 1730 /* Don't skip over the subroutine call if it is not within
ebd98106
FF		 1731 the first three instructions of the prologue and either
1732 we have no line table information or the line info tells
1733 us that the subroutine call is not part of the line
1734 associated with the prologue. */
c5aa993b 1735 if ((pc - orig_pc) > 8)
ebd98106
FF		 1736 {
1737 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1738 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1739
0df8b418
MS		 1740 if ((prologue_sal.line == 0)
1741 || (prologue_sal.line != this_sal.line))
ebd98106
FF		 1742 break;
1743 }
c5aa993b 1744
e17a4113 1745 op = read_memory_integer (pc + 4, 4, byte_order);
c5aa993b 1746
6be8bc0c
EZ		 1747 /* At this point, make sure this is not a trampoline
1748 function (a function that simply calls another functions,
1749 and nothing else). If the next is not a nop, this branch
0df8b418 1750 was part of the function prologue. */
c5aa993b
JM		 1751
1752 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
0df8b418
MS		 1753 break; /* Don't skip over
1754 this branch. */
c5aa993b 1755
46a9b8ed
DJ		 1756 fdata->used_bl = 1;
1757 continue;
c5aa993b 1758 }
98f08d3d
KB		 1759 /* update stack pointer */
1760 else if ((op & 0xfc1f0000) == 0x94010000)
1761 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
c5aa993b
JM		 1762 fdata->frameless = 0;
1763 fdata->offset = SIGNED_SHORT (op);
1764 offset = fdata->offset;
1765 continue;
c5aa993b 1766 }
98f08d3d
KB		 1767 else if ((op & 0xfc1f016a) == 0x7c01016e)
1768 { /* stwux rX,r1,rY */
0df8b418 1769 /* No way to figure out what r1 is going to be. */
98f08d3d
KB		 1770 fdata->frameless = 0;
1771 offset = fdata->offset;
1772 continue;
1773 }
1774 else if ((op & 0xfc1f0003) == 0xf8010001)
1775 { /* stdu rX,NUM(r1) */
1776 fdata->frameless = 0;
1777 fdata->offset = SIGNED_SHORT (op & ~3UL);
1778 offset = fdata->offset;
1779 continue;
1780 }
1781 else if ((op & 0xfc1f016a) == 0x7c01016a)
1782 { /* stdux rX,r1,rY */
0df8b418 1783 /* No way to figure out what r1 is going to be. */
c5aa993b
JM		 1784 fdata->frameless = 0;
1785 offset = fdata->offset;
1786 continue;
c5aa993b 1787 }
7313566f
FF		 1788 else if ((op & 0xffff0000) == 0x38210000)
1789 { /* addi r1,r1,SIMM */
1790 fdata->frameless = 0;
1791 fdata->offset += SIGNED_SHORT (op);
1792 offset = fdata->offset;
1793 continue;
1794 }
4e463ff5
DJ		 1795 /* Load up minimal toc pointer. Do not treat an epilogue restore
1796 of r31 as a minimal TOC load. */
0df8b418
MS		 1797 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1798 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
4e463ff5 1799 && !framep
c5aa993b 1800 && !minimal_toc_loaded)
98f08d3d 1801 {
c5aa993b
JM		 1802 minimal_toc_loaded = 1;
1803 continue;
1804
f6077098
KB		 1805 /* move parameters from argument registers to local variable
1806 registers */
1807 }
1808 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1809 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1810 (((op >> 21) & 31) <= 10) &&
0df8b418
MS		 1811 ((long) ((op >> 16) & 31)
1812 >= fdata->saved_gpr)) /* Rx: local var reg */
f6077098
KB		 1813 {
1814 continue;
1815
c5aa993b
JM		 1816 /* store parameters in stack */
1817 }
e802b915 1818 /* Move parameters from argument registers to temporary register. */
773df3e5 1819 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
e802b915 1820 {
c5aa993b
JM		 1821 continue;
1822
1823 /* Set up frame pointer */
1824 }
76219d77
JB		 1825 else if (op == 0x603d0000) /* oril r29, r1, 0x0 */
1826 {
1827 fdata->frameless = 0;
1828 framep = 1;
1829 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 29);
1830 continue;
1831
1832 /* Another way to set up the frame pointer. */
1833 }
c5aa993b
JM		 1834 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1835 || op == 0x7c3f0b78)
1836 { /* mr r31, r1 */
1837 fdata->frameless = 0;
1838 framep = 1;
6f99cb26 1839 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
c5aa993b
JM		 1840 continue;
1841
1842 /* Another way to set up the frame pointer. */
1843 }
1844 else if ((op & 0xfc1fffff) == 0x38010000)
1845 { /* addi rX, r1, 0x0 */
1846 fdata->frameless = 0;
1847 framep = 1;
6f99cb26
AC		 1848 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1849 + ((op & ~0x38010000) >> 21));
c5aa993b 1850 continue;
c5aa993b 1851 }
6be8bc0c
EZ		 1852 /* AltiVec related instructions. */
1853 /* Store the vrsave register (spr 256) in another register for
1854 later manipulation, or load a register into the vrsave
1855 register. 2 instructions are used: mfvrsave and
1856 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1857 and mtspr SPR256, Rn. */
1858 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1859 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1860 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1861 {
1862 vrsave_reg = GET_SRC_REG (op);
1863 continue;
1864 }
1865 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1866 {
1867 continue;
1868 }
1869 /* Store the register where vrsave was saved to onto the stack:
1870 rS is the register where vrsave was stored in a previous
1871 instruction. */
1872 /* 100100 sssss 00001 dddddddd dddddddd */
1873 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1874 {
1875 if (vrsave_reg == GET_SRC_REG (op))
1876 {
1877 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1878 vrsave_reg = -1;
1879 }
1880 continue;
1881 }
1882 /* Compute the new value of vrsave, by modifying the register
1883 where vrsave was saved to. */
1884 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1885 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1886 {
1887 continue;
1888 }
1889 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1890 in a pair of insns to save the vector registers on the
1891 stack. */
1892 /* 001110 00000 00000 iiii iiii iiii iiii */
96ff0de4
EZ		 1893 /* 001110 01110 00000 iiii iiii iiii iiii */
1894 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1895 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
6be8bc0c 1896 {
773df3e5
JB		 1897 if ((op & 0xffff0000) == 0x38000000)
1898 r0_contains_arg = 0;
6be8bc0c
EZ		 1899 li_found_pc = pc;
1900 vr_saved_offset = SIGNED_SHORT (op);
773df3e5
JB		 1901
1902 /* This insn by itself is not part of the prologue, unless
0df8b418 1903 if part of the pair of insns mentioned above. So do not
773df3e5
JB		 1904 record this insn as part of the prologue yet. */
1905 prev_insn_was_prologue_insn = 0;
6be8bc0c
EZ		 1906 }
1907 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1908 /* 011111 sssss 11111 00000 00111001110 */
1909 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1910 {
1911 if (pc == (li_found_pc + 4))
1912 {
1913 vr_reg = GET_SRC_REG (op);
1914 /* If this is the first vector reg to be saved, or if
1915 it has a lower number than others previously seen,
1916 reupdate the frame info. */
1917 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1918 {
1919 fdata->saved_vr = vr_reg;
1920 fdata->vr_offset = vr_saved_offset + offset;
1921 }
1922 vr_saved_offset = -1;
1923 vr_reg = -1;
1924 li_found_pc = 0;
1925 }
1926 }
1927 /* End AltiVec related instructions. */
96ff0de4
EZ		 1928
1929 /* Start BookE related instructions. */
1930 /* Store gen register S at (r31+uimm).
1931 Any register less than r13 is volatile, so we don't care. */
1932 /* 000100 sssss 11111 iiiii 01100100001 */
1933 else if (arch_info->mach == bfd_mach_ppc_e500
1934 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1935 {
1936 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1937 {
1938 unsigned int imm;
1939 ev_reg = GET_SRC_REG (op);
1940 imm = (op >> 11) & 0x1f;
1941 ev_offset = imm * 8;
1942 /* If this is the first vector reg to be saved, or if
1943 it has a lower number than others previously seen,
1944 reupdate the frame info. */
1945 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1946 {
1947 fdata->saved_ev = ev_reg;
1948 fdata->ev_offset = ev_offset + offset;
1949 }
1950 }
1951 continue;
1952 }
1953 /* Store gen register rS at (r1+rB). */
1954 /* 000100 sssss 00001 bbbbb 01100100000 */
1955 else if (arch_info->mach == bfd_mach_ppc_e500
1956 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1957 {
1958 if (pc == (li_found_pc + 4))
1959 {
1960 ev_reg = GET_SRC_REG (op);
1961 /* If this is the first vector reg to be saved, or if
1962 it has a lower number than others previously seen,
1963 reupdate the frame info. */
1964 /* We know the contents of rB from the previous instruction. */
1965 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1966 {
1967 fdata->saved_ev = ev_reg;
1968 fdata->ev_offset = vr_saved_offset + offset;
1969 }
1970 vr_saved_offset = -1;
1971 ev_reg = -1;
1972 li_found_pc = 0;
1973 }
1974 continue;
1975 }
1976 /* Store gen register r31 at (rA+uimm). */
1977 /* 000100 11111 aaaaa iiiii 01100100001 */
1978 else if (arch_info->mach == bfd_mach_ppc_e500
1979 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1980 {
1981 /* Wwe know that the source register is 31 already, but
1982 it can't hurt to compute it. */
1983 ev_reg = GET_SRC_REG (op);
1984 ev_offset = ((op >> 11) & 0x1f) * 8;
1985 /* If this is the first vector reg to be saved, or if
1986 it has a lower number than others previously seen,
1987 reupdate the frame info. */
1988 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1989 {
1990 fdata->saved_ev = ev_reg;
1991 fdata->ev_offset = ev_offset + offset;
1992 }
1993
1994 continue;
1995 }
1996 /* Store gen register S at (r31+r0).
1997 Store param on stack when offset from SP bigger than 4 bytes. */
1998 /* 000100 sssss 11111 00000 01100100000 */
1999 else if (arch_info->mach == bfd_mach_ppc_e500
2000 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2001 {
2002 if (pc == (li_found_pc + 4))
2003 {
2004 if ((op & 0x03e00000) >= 0x01a00000)
2005 {
2006 ev_reg = GET_SRC_REG (op);
2007 /* If this is the first vector reg to be saved, or if
2008 it has a lower number than others previously seen,
2009 reupdate the frame info. */
2010 /* We know the contents of r0 from the previous
2011 instruction. */
2012 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
2013 {
2014 fdata->saved_ev = ev_reg;
2015 fdata->ev_offset = vr_saved_offset + offset;
2016 }
2017 ev_reg = -1;
2018 }
2019 vr_saved_offset = -1;
2020 li_found_pc = 0;
2021 continue;
2022 }
2023 }
2024 /* End BookE related instructions. */
2025
c5aa993b
JM		 2026 else
2027 {
46a9b8ed
DJ		 2028 unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1);
2029
55d05f3b
KB		 2030 /* Not a recognized prologue instruction.
2031 Handle optimizer code motions into the prologue by continuing
2032 the search if we have no valid frame yet or if the return
46a9b8ed
DJ		 2033 address is not yet saved in the frame. Also skip instructions
2034 if some of the GPRs expected to be saved are not yet saved. */
2035 if (fdata->frameless == 0 && fdata->nosavedpc == 0
2036 && (fdata->gpr_mask & all_mask) == all_mask)
55d05f3b
KB		 2037 break;
2038
2039 if (op == 0x4e800020 /* blr */
2040 || op == 0x4e800420) /* bctr */
2041 /* Do not scan past epilogue in frameless functions or
2042 trampolines. */
2043 break;
2044 if ((op & 0xf4000000) == 0x40000000) /* bxx */
64366f1c 2045 /* Never skip branches. */
55d05f3b
KB		 2046 break;
2047
2048 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
2049 /* Do not scan too many insns, scanning insns is expensive with
2050 remote targets. */
2051 break;
2052
2053 /* Continue scanning. */
2054 prev_insn_was_prologue_insn = 0;
2055 continue;
c5aa993b 2056 }
c906108c
SS		 2057 }
2058
2059#if 0
2060/* I have problems with skipping over __main() that I need to address
0df8b418 2061 * sometime. Previously, I used to use misc_function_vector which
c906108c
SS		 2062 * didn't work as well as I wanted to be. -MGO */
2063
2064 /* If the first thing after skipping a prolog is a branch to a function,
2065 this might be a call to an initializer in main(), introduced by gcc2.
64366f1c 2066 We'd like to skip over it as well. Fortunately, xlc does some extra
c906108c 2067 work before calling a function right after a prologue, thus we can
64366f1c 2068 single out such gcc2 behaviour. */
c906108c 2069
c906108c 2070
c5aa993b 2071 if ((op & 0xfc000001) == 0x48000001)
0df8b418 2072 { /* bl foo, an initializer function? */
e17a4113 2073 op = read_memory_integer (pc + 4, 4, byte_order);
c5aa993b
JM		 2074
2075 if (op == 0x4def7b82)
2076 { /* cror 0xf, 0xf, 0xf (nop) */
c906108c 2077
64366f1c
EZ		 2078 /* Check and see if we are in main. If so, skip over this
2079 initializer function as well. */
c906108c 2080
c5aa993b 2081 tmp = find_pc_misc_function (pc);
6314a349
AC		 2082 if (tmp >= 0
2083 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
c5aa993b
JM		 2084 return pc + 8;
2085 }
c906108c 2086 }
c906108c 2087#endif /* 0 */
c5aa993b 2088
46a9b8ed
DJ		 2089 if (pc == lim_pc && lr_reg >= 0)
2090 fdata->lr_register = lr_reg;
2091
c5aa993b 2092 fdata->offset = -fdata->offset;
ddb20c56 2093 return last_prologue_pc;
c906108c
SS		 2094}
2095
7a78ae4e 2096static CORE_ADDR
4a7622d1 2097rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
c906108c 2098{
4a7622d1 2099 struct rs6000_framedata frame;
e3acb115 2100 CORE_ADDR limit_pc, func_addr, func_end_addr = 0;
c906108c 2101
4a7622d1
UW		 2102 /* See if we can determine the end of the prologue via the symbol table.
2103 If so, then return either PC, or the PC after the prologue, whichever
2104 is greater. */
e3acb115 2105 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr))
c5aa993b 2106 {
d80b854b
UW		 2107 CORE_ADDR post_prologue_pc
2108 = skip_prologue_using_sal (gdbarch, func_addr);
4a7622d1
UW		 2109 if (post_prologue_pc != 0)
2110 return max (pc, post_prologue_pc);
c906108c 2111 }
c906108c 2112
4a7622d1
UW		 2113 /* Can't determine prologue from the symbol table, need to examine
2114 instructions. */
c906108c 2115
4a7622d1
UW		 2116 /* Find an upper limit on the function prologue using the debug
2117 information. If the debug information could not be used to provide
2118 that bound, then use an arbitrary large number as the upper bound. */
d80b854b 2119 limit_pc = skip_prologue_using_sal (gdbarch, pc);
4a7622d1
UW		 2120 if (limit_pc == 0)
2121 limit_pc = pc + 100; /* Magic. */
794a477a 2122
e3acb115
JB		 2123 /* Do not allow limit_pc to be past the function end, if we know
2124 where that end is... */
2125 if (func_end_addr && limit_pc > func_end_addr)
2126 limit_pc = func_end_addr;
2127
4a7622d1
UW		 2128 pc = skip_prologue (gdbarch, pc, limit_pc, &frame);
2129 return pc;
c906108c 2130}
c906108c 2131
8ab3d180
KB		 2132/* When compiling for EABI, some versions of GCC emit a call to __eabi
2133 in the prologue of main().
2134
2135 The function below examines the code pointed at by PC and checks to
2136 see if it corresponds to a call to __eabi. If so, it returns the
2137 address of the instruction following that call. Otherwise, it simply
2138 returns PC. */
2139
63807e1d 2140static CORE_ADDR
8ab3d180
KB		 2141rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2142{
e17a4113 2143 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8ab3d180
KB		 2144 gdb_byte buf[4];
2145 unsigned long op;
2146
2147 if (target_read_memory (pc, buf, 4))
2148 return pc;
e17a4113 2149 op = extract_unsigned_integer (buf, 4, byte_order);
8ab3d180
KB		 2150
2151 if ((op & BL_MASK) == BL_INSTRUCTION)
2152 {
2153 CORE_ADDR displ = op & BL_DISPLACEMENT_MASK;
2154 CORE_ADDR call_dest = pc + 4 + displ;
7cbd4a93 2155 struct bound_minimal_symbol s = lookup_minimal_symbol_by_pc (call_dest);
8ab3d180
KB		 2156
2157 /* We check for ___eabi (three leading underscores) in addition
2158 to __eabi in case the GCC option "-fleading-underscore" was
2159 used to compile the program. */
7cbd4a93
TT		 2160 if (s.minsym != NULL
2161 && SYMBOL_LINKAGE_NAME (s.minsym) != NULL
2162 && (strcmp (SYMBOL_LINKAGE_NAME (s.minsym), "__eabi") == 0
2163 || strcmp (SYMBOL_LINKAGE_NAME (s.minsym), "___eabi") == 0))
8ab3d180
KB		 2164 pc += 4;
2165 }
2166 return pc;
2167}
383f0f5b 2168
4a7622d1
UW		 2169/* All the ABI's require 16 byte alignment. */
2170static CORE_ADDR
2171rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2172{
2173 return (addr & -16);
c906108c
SS		 2174}
2175
977adac5
ND		 2176/* Return whether handle_inferior_event() should proceed through code
2177 starting at PC in function NAME when stepping.
2178
2179 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2180 handle memory references that are too distant to fit in instructions
2181 generated by the compiler. For example, if 'foo' in the following
2182 instruction:
2183
2184 lwz r9,foo(r2)
2185
2186 is greater than 32767, the linker might replace the lwz with a branch to
2187 somewhere in @FIX1 that does the load in 2 instructions and then branches
2188 back to where execution should continue.
2189
2190 GDB should silently step over @FIX code, just like AIX dbx does.
2ec664f5
MS		 2191 Unfortunately, the linker uses the "b" instruction for the
2192 branches, meaning that the link register doesn't get set.
2193 Therefore, GDB's usual step_over_function () mechanism won't work.
977adac5 2194
e76f05fa
UW		 2195 Instead, use the gdbarch_skip_trampoline_code and
2196 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2ec664f5 2197 @FIX code. */
977adac5 2198
63807e1d 2199static int
e17a4113 2200rs6000_in_solib_return_trampoline (struct gdbarch *gdbarch,
2c02bd72 2201 CORE_ADDR pc, const char *name)
977adac5
ND		 2202{
2203 return name && !strncmp (name, "@FIX", 4);
2204}
2205
2206/* Skip code that the user doesn't want to see when stepping:
2207
2208 1. Indirect function calls use a piece of trampoline code to do context
2209 switching, i.e. to set the new TOC table. Skip such code if we are on
2210 its first instruction (as when we have single-stepped to here).
2211
2212 2. Skip shared library trampoline code (which is different from
c906108c 2213 indirect function call trampolines).
977adac5
ND		 2214
2215 3. Skip bigtoc fixup code.
2216
c906108c 2217 Result is desired PC to step until, or NULL if we are not in
977adac5 2218 code that should be skipped. */
c906108c 2219
63807e1d 2220static CORE_ADDR
52f729a7 2221rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
c906108c 2222{
e17a4113
UW		 2223 struct gdbarch *gdbarch = get_frame_arch (frame);
2224 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2225 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
52f0bd74 2226 unsigned int ii, op;
977adac5 2227 int rel;
c906108c 2228 CORE_ADDR solib_target_pc;
7cbd4a93 2229 struct bound_minimal_symbol msymbol;
c906108c 2230
c5aa993b
JM		 2231 static unsigned trampoline_code[] =
2232 {
2233 0x800b0000, /* l r0,0x0(r11) */
2234 0x90410014, /* st r2,0x14(r1) */
2235 0x7c0903a6, /* mtctr r0 */
2236 0x804b0004, /* l r2,0x4(r11) */
2237 0x816b0008, /* l r11,0x8(r11) */
2238 0x4e800420, /* bctr */
2239 0x4e800020, /* br */
2240 0
c906108c
SS		 2241 };
2242
977adac5
ND		 2243 /* Check for bigtoc fixup code. */
2244 msymbol = lookup_minimal_symbol_by_pc (pc);
7cbd4a93 2245 if (msymbol.minsym
e17a4113 2246 && rs6000_in_solib_return_trampoline (gdbarch, pc,
7cbd4a93 2247 SYMBOL_LINKAGE_NAME (msymbol.minsym)))
977adac5
ND		 2248 {
2249 /* Double-check that the third instruction from PC is relative "b". */
e17a4113 2250 op = read_memory_integer (pc + 8, 4, byte_order);
977adac5
ND		 2251 if ((op & 0xfc000003) == 0x48000000)
2252 {
2253 /* Extract bits 6-29 as a signed 24-bit relative word address and
2254 add it to the containing PC. */
2255 rel = ((int)(op << 6) >> 6);
2256 return pc + 8 + rel;
2257 }
2258 }
2259
c906108c 2260 /* If pc is in a shared library trampoline, return its target. */
52f729a7 2261 solib_target_pc = find_solib_trampoline_target (frame, pc);
c906108c
SS		 2262 if (solib_target_pc)
2263 return solib_target_pc;
2264
c5aa993b
JM		 2265 for (ii = 0; trampoline_code[ii]; ++ii)
2266 {
e17a4113 2267 op = read_memory_integer (pc + (ii * 4), 4, byte_order);
c5aa993b
JM		 2268 if (op != trampoline_code[ii])
2269 return 0;
2270 }
0df8b418
MS		 2271 ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination
2272 addr. */
e17a4113 2273 pc = read_memory_unsigned_integer (ii, tdep->wordsize, byte_order);
c906108c
SS		 2274 return pc;
2275}
2276
794ac428
UW		 2277/* ISA-specific vector types. */
2278
2279static struct type *
2280rs6000_builtin_type_vec64 (struct gdbarch *gdbarch)
2281{
2282 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2283
2284 if (!tdep->ppc_builtin_type_vec64)
2285 {
df4df182
UW		 2286 const struct builtin_type *bt = builtin_type (gdbarch);
2287
794ac428
UW		 2288 /* The type we're building is this: */
2289#if 0
2290 union __gdb_builtin_type_vec64
2291 {
2292 int64_t uint64;
2293 float v2_float[2];
2294 int32_t v2_int32[2];
2295 int16_t v4_int16[4];
2296 int8_t v8_int8[8];
2297 };
2298#endif
2299
2300 struct type *t;
2301
e9bb382b
UW		 2302 t = arch_composite_type (gdbarch,
2303 "__ppc_builtin_type_vec64", TYPE_CODE_UNION);
df4df182 2304 append_composite_type_field (t, "uint64", bt->builtin_int64);
794ac428 2305 append_composite_type_field (t, "v2_float",
df4df182 2306 init_vector_type (bt->builtin_float, 2));
794ac428 2307 append_composite_type_field (t, "v2_int32",
df4df182 2308 init_vector_type (bt->builtin_int32, 2));
794ac428 2309 append_composite_type_field (t, "v4_int16",
df4df182 2310 init_vector_type (bt->builtin_int16, 4));
794ac428 2311 append_composite_type_field (t, "v8_int8",
df4df182 2312 init_vector_type (bt->builtin_int8, 8));
794ac428 2313
876cecd0 2314 TYPE_VECTOR (t) = 1;
794ac428
UW		 2315 TYPE_NAME (t) = "ppc_builtin_type_vec64";
2316 tdep->ppc_builtin_type_vec64 = t;
2317 }
2318
2319 return tdep->ppc_builtin_type_vec64;
2320}
2321
604c2f83
LM		 2322/* Vector 128 type. */
2323
2324static struct type *
2325rs6000_builtin_type_vec128 (struct gdbarch *gdbarch)
2326{
2327 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2328
2329 if (!tdep->ppc_builtin_type_vec128)
2330 {
df4df182
UW		 2331 const struct builtin_type *bt = builtin_type (gdbarch);
2332
604c2f83
LM		 2333 /* The type we're building is this
2334
2335 type = union __ppc_builtin_type_vec128 {
2336 uint128_t uint128;
db9f5df8 2337 double v2_double[2];
604c2f83
LM		 2338 float v4_float[4];
2339 int32_t v4_int32[4];
2340 int16_t v8_int16[8];
2341 int8_t v16_int8[16];
2342 }
2343 */
2344
2345 struct type *t;
2346
e9bb382b
UW		 2347 t = arch_composite_type (gdbarch,
2348 "__ppc_builtin_type_vec128", TYPE_CODE_UNION);
df4df182 2349 append_composite_type_field (t, "uint128", bt->builtin_uint128);
db9f5df8
UW		 2350 append_composite_type_field (t, "v2_double",
2351 init_vector_type (bt->builtin_double, 2));
604c2f83 2352 append_composite_type_field (t, "v4_float",
df4df182 2353 init_vector_type (bt->builtin_float, 4));
604c2f83 2354 append_composite_type_field (t, "v4_int32",
df4df182 2355 init_vector_type (bt->builtin_int32, 4));
604c2f83 2356 append_composite_type_field (t, "v8_int16",
df4df182 2357 init_vector_type (bt->builtin_int16, 8));
604c2f83 2358 append_composite_type_field (t, "v16_int8",
df4df182 2359 init_vector_type (bt->builtin_int8, 16));
604c2f83 2360
803e1097 2361 TYPE_VECTOR (t) = 1;
604c2f83
LM		 2362 TYPE_NAME (t) = "ppc_builtin_type_vec128";
2363 tdep->ppc_builtin_type_vec128 = t;
2364 }
2365
2366 return tdep->ppc_builtin_type_vec128;
2367}
2368
7cc46491
DJ		 2369/* Return the name of register number REGNO, or the empty string if it
2370 is an anonymous register. */
7a78ae4e 2371
fa88f677 2372static const char *
d93859e2 2373rs6000_register_name (struct gdbarch *gdbarch, int regno)
7a78ae4e 2374{
d93859e2 2375 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7a78ae4e 2376
7cc46491
DJ		 2377 /* The upper half "registers" have names in the XML description,
2378 but we present only the low GPRs and the full 64-bit registers
2379 to the user. */
2380 if (tdep->ppc_ev0_upper_regnum >= 0
2381 && tdep->ppc_ev0_upper_regnum <= regno
2382 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
2383 return "";
2384
604c2f83
LM		 2385 /* Hide the upper halves of the vs0~vs31 registers. */
2386 if (tdep->ppc_vsr0_regnum >= 0
2387 && tdep->ppc_vsr0_upper_regnum <= regno
2388 && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs)
2389 return "";
2390
7cc46491 2391 /* Check if the SPE pseudo registers are available. */
5a9e69ba 2392 if (IS_SPE_PSEUDOREG (tdep, regno))
7cc46491
DJ		 2393 {
2394 static const char *const spe_regnames[] = {
2395 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2396 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2397 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2398 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2399 };
2400 return spe_regnames[regno - tdep->ppc_ev0_regnum];
2401 }
2402
f949c649
TJB		 2403 /* Check if the decimal128 pseudo-registers are available. */
2404 if (IS_DFP_PSEUDOREG (tdep, regno))
2405 {
2406 static const char *const dfp128_regnames[] = {
2407 "dl0", "dl1", "dl2", "dl3",
2408 "dl4", "dl5", "dl6", "dl7",
2409 "dl8", "dl9", "dl10", "dl11",
2410 "dl12", "dl13", "dl14", "dl15"
2411 };
2412 return dfp128_regnames[regno - tdep->ppc_dl0_regnum];
2413 }
2414
604c2f83
LM		 2415 /* Check if this is a VSX pseudo-register. */
2416 if (IS_VSX_PSEUDOREG (tdep, regno))
2417 {
2418 static const char *const vsx_regnames[] = {
2419 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2420 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2421 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2422 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2423 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2424 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2425 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2426 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2427 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2428 };
2429 return vsx_regnames[regno - tdep->ppc_vsr0_regnum];
2430 }
2431
2432 /* Check if the this is a Extended FP pseudo-register. */
2433 if (IS_EFP_PSEUDOREG (tdep, regno))
2434 {
2435 static const char *const efpr_regnames[] = {
2436 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2437 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2438 "f46", "f47", "f48", "f49", "f50", "f51",
2439 "f52", "f53", "f54", "f55", "f56", "f57",
2440 "f58", "f59", "f60", "f61", "f62", "f63"
2441 };
2442 return efpr_regnames[regno - tdep->ppc_efpr0_regnum];
2443 }
2444
d93859e2 2445 return tdesc_register_name (gdbarch, regno);
7a78ae4e
ND		 2446}
2447
7cc46491
DJ		 2448/* Return the GDB type object for the "standard" data type of data in
2449 register N. */
7a78ae4e
ND		 2450
2451static struct type *
7cc46491 2452rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
7a78ae4e 2453{
691d145a 2454 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7a78ae4e 2455
7cc46491 2456 /* These are the only pseudo-registers we support. */
f949c649 2457 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
604c2f83
LM		 2458 || IS_DFP_PSEUDOREG (tdep, regnum)
2459 || IS_VSX_PSEUDOREG (tdep, regnum)
2460 || IS_EFP_PSEUDOREG (tdep, regnum));
7cc46491 2461
f949c649
TJB		 2462 /* These are the e500 pseudo-registers. */
2463 if (IS_SPE_PSEUDOREG (tdep, regnum))
2464 return rs6000_builtin_type_vec64 (gdbarch);
604c2f83
LM		 2465 else if (IS_DFP_PSEUDOREG (tdep, regnum))
2466 /* PPC decimal128 pseudo-registers. */
f949c649 2467 return builtin_type (gdbarch)->builtin_declong;
604c2f83
LM		 2468 else if (IS_VSX_PSEUDOREG (tdep, regnum))
2469 /* POWER7 VSX pseudo-registers. */
2470 return rs6000_builtin_type_vec128 (gdbarch);
2471 else
2472 /* POWER7 Extended FP pseudo-registers. */
2473 return builtin_type (gdbarch)->builtin_double;
7a78ae4e
ND		 2474}
2475
c44ca51c
AC		 2476/* Is REGNUM a member of REGGROUP? */
2477static int
7cc46491
DJ		 2478rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2479 struct reggroup *group)
c44ca51c
AC		 2480{
2481 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
c44ca51c 2482
7cc46491 2483 /* These are the only pseudo-registers we support. */
f949c649 2484 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
604c2f83
LM		 2485 || IS_DFP_PSEUDOREG (tdep, regnum)
2486 || IS_VSX_PSEUDOREG (tdep, regnum)
2487 || IS_EFP_PSEUDOREG (tdep, regnum));
c44ca51c 2488
604c2f83
LM		 2489 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2490 if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum))
f949c649 2491 return group == all_reggroup || group == vector_reggroup;
7cc46491 2492 else
604c2f83 2493 /* PPC decimal128 or Extended FP pseudo-registers. */
f949c649 2494 return group == all_reggroup || group == float_reggroup;
c44ca51c
AC		 2495}
2496
691d145a 2497/* The register format for RS/6000 floating point registers is always
64366f1c 2498 double, we need a conversion if the memory format is float. */
7a78ae4e
ND		 2499
2500static int
0abe36f5
MD		 2501rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum,
2502 struct type *type)
7a78ae4e 2503{
0abe36f5 2504 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7cc46491
DJ		 2505
2506 return (tdep->ppc_fp0_regnum >= 0
2507 && regnum >= tdep->ppc_fp0_regnum
2508 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs
2509 && TYPE_CODE (type) == TYPE_CODE_FLT
0dfff4cb
UW		 2510 && TYPE_LENGTH (type)
2511 != TYPE_LENGTH (builtin_type (gdbarch)->builtin_double));
7a78ae4e
ND		 2512}
2513
8dccd430 2514static int
691d145a
JB		 2515rs6000_register_to_value (struct frame_info *frame,
2516 int regnum,
2517 struct type *type,
8dccd430
PA		 2518 gdb_byte *to,
2519 int *optimizedp, int *unavailablep)
7a78ae4e 2520{
0dfff4cb 2521 struct gdbarch *gdbarch = get_frame_arch (frame);
50fd1280 2522 gdb_byte from[MAX_REGISTER_SIZE];
691d145a 2523
691d145a 2524 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
7a78ae4e 2525
8dccd430
PA		 2526 if (!get_frame_register_bytes (frame, regnum, 0,
2527 register_size (gdbarch, regnum),
2528 from, optimizedp, unavailablep))
2529 return 0;
2530
0dfff4cb
UW		 2531 convert_typed_floating (from, builtin_type (gdbarch)->builtin_double,
2532 to, type);
8dccd430
PA		 2533 *optimizedp = *unavailablep = 0;
2534 return 1;
691d145a 2535}
7a292a7a 2536
7a78ae4e 2537static void
691d145a
JB		 2538rs6000_value_to_register (struct frame_info *frame,
2539 int regnum,
2540 struct type *type,
50fd1280 2541 const gdb_byte *from)
7a78ae4e 2542{
0dfff4cb 2543 struct gdbarch *gdbarch = get_frame_arch (frame);
50fd1280 2544 gdb_byte to[MAX_REGISTER_SIZE];
691d145a 2545
691d145a
JB		 2546 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2547
0dfff4cb
UW		 2548 convert_typed_floating (from, type,
2549 to, builtin_type (gdbarch)->builtin_double);
691d145a 2550 put_frame_register (frame, regnum, to);
7a78ae4e 2551}
c906108c 2552
05d1431c
PA		 2553 /* The type of a function that moves the value of REG between CACHE
2554 or BUF --- in either direction. */
2555typedef enum register_status (*move_ev_register_func) (struct regcache *,
2556 int, void *);
2557
6ced10dd
JB		 2558/* Move SPE vector register values between a 64-bit buffer and the two
2559 32-bit raw register halves in a regcache. This function handles
2560 both splitting a 64-bit value into two 32-bit halves, and joining
2561 two halves into a whole 64-bit value, depending on the function
2562 passed as the MOVE argument.
2563
2564 EV_REG must be the number of an SPE evN vector register --- a
2565 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2566 64-bit buffer.
2567
2568 Call MOVE once for each 32-bit half of that register, passing
2569 REGCACHE, the number of the raw register corresponding to that
2570 half, and the address of the appropriate half of BUFFER.
2571
2572 For example, passing 'regcache_raw_read' as the MOVE function will
2573 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2574 'regcache_raw_supply' will supply the contents of BUFFER to the
2575 appropriate pair of raw registers in REGCACHE.
2576
2577 You may need to cast away some 'const' qualifiers when passing
2578 MOVE, since this function can't tell at compile-time which of
2579 REGCACHE or BUFFER is acting as the source of the data. If C had
2580 co-variant type qualifiers, ... */
05d1431c
PA		 2581
2582static enum register_status
2583e500_move_ev_register (move_ev_register_func move,
2584 struct regcache *regcache, int ev_reg, void *buffer)
6ced10dd
JB		 2585{
2586 struct gdbarch *arch = get_regcache_arch (regcache);
2587 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2588 int reg_index;
50fd1280 2589 gdb_byte *byte_buffer = buffer;
05d1431c 2590 enum register_status status;
6ced10dd 2591
5a9e69ba 2592 gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg));
6ced10dd
JB		 2593
2594 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2595
8b164abb 2596 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
6ced10dd 2597 {
05d1431c
PA		 2598 status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index,
2599 byte_buffer);
2600 if (status == REG_VALID)
2601 status = move (regcache, tdep->ppc_gp0_regnum + reg_index,
2602 byte_buffer + 4);
6ced10dd
JB		 2603 }
2604 else
2605 {
05d1431c
PA		 2606 status = move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2607 if (status == REG_VALID)
2608 status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index,
2609 byte_buffer + 4);
6ced10dd 2610 }
05d1431c
PA		 2611
2612 return status;
6ced10dd
JB		 2613}
2614
05d1431c
PA		 2615static enum register_status
2616do_regcache_raw_read (struct regcache *regcache, int regnum, void *buffer)
2617{
2618 return regcache_raw_read (regcache, regnum, buffer);
2619}
2620
2621static enum register_status
2622do_regcache_raw_write (struct regcache *regcache, int regnum, void *buffer)
2623{
2624 regcache_raw_write (regcache, regnum, buffer);
2625
2626 return REG_VALID;
2627}
2628
2629static enum register_status
c8001721 2630e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
50fd1280 2631 int reg_nr, gdb_byte *buffer)
f949c649 2632{
05d1431c 2633 return e500_move_ev_register (do_regcache_raw_read, regcache, reg_nr, buffer);
f949c649
TJB		 2634}
2635
2636static void
2637e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2638 int reg_nr, const gdb_byte *buffer)
2639{
05d1431c
PA		 2640 e500_move_ev_register (do_regcache_raw_write, regcache,
2641 reg_nr, (void *) buffer);
f949c649
TJB		 2642}
2643
604c2f83 2644/* Read method for DFP pseudo-registers. */
05d1431c 2645static enum register_status
604c2f83 2646dfp_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
f949c649
TJB		 2647 int reg_nr, gdb_byte *buffer)
2648{
2649 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2650 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
05d1431c 2651 enum register_status status;
f949c649
TJB		 2652
2653 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2654 {
2655 /* Read two FP registers to form a whole dl register. */
05d1431c
PA		 2656 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2657 2 * reg_index, buffer);
2658 if (status == REG_VALID)
2659 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2660 2 * reg_index + 1, buffer + 8);
f949c649
TJB		 2661 }
2662 else
2663 {
05d1431c
PA		 2664 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2665 2 * reg_index + 1, buffer + 8);
2666 if (status == REG_VALID)
2667 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2668 2 * reg_index, buffer);
f949c649 2669 }
05d1431c
PA		 2670
2671 return status;
f949c649
TJB		 2672}
2673
604c2f83 2674/* Write method for DFP pseudo-registers. */
f949c649 2675static void
604c2f83 2676dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
f949c649
TJB		 2677 int reg_nr, const gdb_byte *buffer)
2678{
2679 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2680 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2681
2682 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2683 {
2684 /* Write each half of the dl register into a separate
2685 FP register. */
2686 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2687 2 * reg_index, buffer);
2688 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2689 2 * reg_index + 1, buffer + 8);
2690 }
2691 else
2692 {
2693 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2694 2 * reg_index + 1, buffer + 8);
2695 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2696 2 * reg_index, buffer);
2697 }
2698}
2699
604c2f83 2700/* Read method for POWER7 VSX pseudo-registers. */
05d1431c 2701static enum register_status
604c2f83
LM		 2702vsx_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2703 int reg_nr, gdb_byte *buffer)
2704{
2705 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2706 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
05d1431c 2707 enum register_status status;
604c2f83
LM		 2708
2709 /* Read the portion that overlaps the VMX registers. */
2710 if (reg_index > 31)
05d1431c
PA		 2711 status = regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2712 reg_index - 32, buffer);
604c2f83
LM		 2713 else
2714 /* Read the portion that overlaps the FPR registers. */
2715 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2716 {
05d1431c
PA		 2717 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2718 reg_index, buffer);
2719 if (status == REG_VALID)
2720 status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2721 reg_index, buffer + 8);
604c2f83
LM		 2722 }
2723 else
2724 {
05d1431c
PA		 2725 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2726 reg_index, buffer + 8);
2727 if (status == REG_VALID)
2728 status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2729 reg_index, buffer);
604c2f83 2730 }
05d1431c
PA		 2731
2732 return status;
604c2f83
LM		 2733}
2734
2735/* Write method for POWER7 VSX pseudo-registers. */
2736static void
2737vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2738 int reg_nr, const gdb_byte *buffer)
2739{
2740 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2741 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2742
2743 /* Write the portion that overlaps the VMX registers. */
2744 if (reg_index > 31)
2745 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2746 reg_index - 32, buffer);
2747 else
2748 /* Write the portion that overlaps the FPR registers. */
2749 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2750 {
2751 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2752 reg_index, buffer);
2753 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2754 reg_index, buffer + 8);
2755 }
2756 else
2757 {
2758 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2759 reg_index, buffer + 8);
2760 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2761 reg_index, buffer);
2762 }
2763}
2764
2765/* Read method for POWER7 Extended FP pseudo-registers. */
05d1431c 2766static enum register_status
604c2f83
LM		 2767efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2768 int reg_nr, gdb_byte *buffer)
2769{
2770 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2771 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2772
d9492458 2773 /* Read the portion that overlaps the VMX register. */
05d1431c
PA		 2774 return regcache_raw_read_part (regcache, tdep->ppc_vr0_regnum + reg_index, 0,
2775 register_size (gdbarch, reg_nr), buffer);
604c2f83
LM		 2776}
2777
2778/* Write method for POWER7 Extended FP pseudo-registers. */
2779static void
2780efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2781 int reg_nr, const gdb_byte *buffer)
2782{
2783 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2784 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2785
d9492458
TJB		 2786 /* Write the portion that overlaps the VMX register. */
2787 regcache_raw_write_part (regcache, tdep->ppc_vr0_regnum + reg_index, 0,
2788 register_size (gdbarch, reg_nr), buffer);
604c2f83
LM		 2789}
2790
05d1431c 2791static enum register_status
0df8b418
MS		 2792rs6000_pseudo_register_read (struct gdbarch *gdbarch,
2793 struct regcache *regcache,
f949c649 2794 int reg_nr, gdb_byte *buffer)
c8001721 2795{
6ced10dd 2796 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
c8001721
EZ		 2797 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2798
6ced10dd 2799 gdb_assert (regcache_arch == gdbarch);
f949c649 2800
5a9e69ba 2801 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
05d1431c 2802 return e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
f949c649 2803 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
05d1431c 2804 return dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
604c2f83 2805 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
05d1431c 2806 return vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
604c2f83 2807 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
05d1431c 2808 return efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
6ced10dd 2809 else
a44bddec 2810 internal_error (__FILE__, __LINE__,
f949c649
TJB		 2811 _("rs6000_pseudo_register_read: "
2812 "called on unexpected register '%s' (%d)"),
2813 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
c8001721
EZ		 2814}
2815
2816static void
f949c649
TJB		 2817rs6000_pseudo_register_write (struct gdbarch *gdbarch,
2818 struct regcache *regcache,
2819 int reg_nr, const gdb_byte *buffer)
c8001721 2820{
6ced10dd 2821 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
c8001721
EZ		 2822 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2823
6ced10dd 2824 gdb_assert (regcache_arch == gdbarch);
f949c649 2825
5a9e69ba 2826 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
f949c649
TJB		 2827 e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2828 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
604c2f83
LM		 2829 dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2830 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2831 vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2832 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2833 efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
6ced10dd 2834 else
a44bddec 2835 internal_error (__FILE__, __LINE__,
f949c649
TJB		 2836 _("rs6000_pseudo_register_write: "
2837 "called on unexpected register '%s' (%d)"),
2838 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
6ced10dd
JB		 2839}
2840
18ed0c4e 2841/* Convert a DBX STABS register number to a GDB register number. */
c8001721 2842static int
d3f73121 2843rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
c8001721 2844{
d3f73121 2845 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
c8001721 2846
9f744501
JB		 2847 if (0 <= num && num <= 31)
2848 return tdep->ppc_gp0_regnum + num;
2849 else if (32 <= num && num <= 63)
383f0f5b
JB		 2850 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2851 specifies registers the architecture doesn't have? Our
2852 callers don't check the value we return. */
366f009f 2853 return tdep->ppc_fp0_regnum + (num - 32);
18ed0c4e
JB		 2854 else if (77 <= num && num <= 108)
2855 return tdep->ppc_vr0_regnum + (num - 77);
9f744501 2856 else if (1200 <= num && num < 1200 + 32)
e1ec1b42 2857 return tdep->ppc_ev0_upper_regnum + (num - 1200);
9f744501
JB		 2858 else
2859 switch (num)
2860 {
2861 case 64:
2862 return tdep->ppc_mq_regnum;
2863 case 65:
2864 return tdep->ppc_lr_regnum;
2865 case 66:
2866 return tdep->ppc_ctr_regnum;
2867 case 76:
2868 return tdep->ppc_xer_regnum;
2869 case 109:
2870 return tdep->ppc_vrsave_regnum;
18ed0c4e
JB		 2871 case 110:
2872 return tdep->ppc_vrsave_regnum - 1; /* vscr */
867e2dc5 2873 case 111:
18ed0c4e 2874 return tdep->ppc_acc_regnum;
867e2dc5 2875 case 112:
18ed0c4e 2876 return tdep->ppc_spefscr_regnum;
9f744501
JB		 2877 default:
2878 return num;
2879 }
18ed0c4e 2880}
9f744501 2881
9f744501 2882
18ed0c4e
JB		 2883/* Convert a Dwarf 2 register number to a GDB register number. */
2884static int
d3f73121 2885rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
18ed0c4e 2886{
d3f73121 2887 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9f744501 2888
18ed0c4e
JB		 2889 if (0 <= num && num <= 31)
2890 return tdep->ppc_gp0_regnum + num;
2891 else if (32 <= num && num <= 63)
2892 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2893 specifies registers the architecture doesn't have? Our
2894 callers don't check the value we return. */
2895 return tdep->ppc_fp0_regnum + (num - 32);
2896 else if (1124 <= num && num < 1124 + 32)
2897 return tdep->ppc_vr0_regnum + (num - 1124);
2898 else if (1200 <= num && num < 1200 + 32)
e1ec1b42 2899 return tdep->ppc_ev0_upper_regnum + (num - 1200);
18ed0c4e
JB		 2900 else
2901 switch (num)
2902 {
a489f789
AS		 2903 case 64:
2904 return tdep->ppc_cr_regnum;
18ed0c4e
JB		 2905 case 67:
2906 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2907 case 99:
2908 return tdep->ppc_acc_regnum;
2909 case 100:
2910 return tdep->ppc_mq_regnum;
2911 case 101:
2912 return tdep->ppc_xer_regnum;
2913 case 108:
2914 return tdep->ppc_lr_regnum;
2915 case 109:
2916 return tdep->ppc_ctr_regnum;
2917 case 356:
2918 return tdep->ppc_vrsave_regnum;
2919 case 612:
2920 return tdep->ppc_spefscr_regnum;
2921 default:
2922 return num;
2923 }
2188cbdd
EZ		 2924}
2925
4fc771b8
DJ		 2926/* Translate a .eh_frame register to DWARF register, or adjust a
2927 .debug_frame register. */
2928
2929static int
2930rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
2931{
2932 /* GCC releases before 3.4 use GCC internal register numbering in
2933 .debug_frame (and .debug_info, et cetera). The numbering is
2934 different from the standard SysV numbering for everything except
2935 for GPRs and FPRs. We can not detect this problem in most cases
2936 - to get accurate debug info for variables living in lr, ctr, v0,
2937 et cetera, use a newer version of GCC. But we must detect
2938 one important case - lr is in column 65 in .debug_frame output,
2939 instead of 108.
2940
2941 GCC 3.4, and the "hammer" branch, have a related problem. They
2942 record lr register saves in .debug_frame as 108, but still record
2943 the return column as 65. We fix that up too.
2944
2945 We can do this because 65 is assigned to fpsr, and GCC never
2946 generates debug info referring to it. To add support for
2947 handwritten debug info that restores fpsr, we would need to add a
2948 producer version check to this. */
2949 if (!eh_frame_p)
2950 {
2951 if (num == 65)
2952 return 108;
2953 else
2954 return num;
2955 }
2956
2957 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2958 internal register numbering; translate that to the standard DWARF2
2959 register numbering. */
2960 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */
2961 return num;
2962 else if (68 <= num && num <= 75) /* cr0-cr8 */
2963 return num - 68 + 86;
2964 else if (77 <= num && num <= 108) /* vr0-vr31 */
2965 return num - 77 + 1124;
2966 else
2967 switch (num)
2968 {
2969 case 64: /* mq */
2970 return 100;
2971 case 65: /* lr */
2972 return 108;
2973 case 66: /* ctr */
2974 return 109;
2975 case 76: /* xer */
2976 return 101;
2977 case 109: /* vrsave */
2978 return 356;
2979 case 110: /* vscr */
2980 return 67;
2981 case 111: /* spe_acc */
2982 return 99;
2983 case 112: /* spefscr */
2984 return 612;
2985 default:
2986 return num;
2987 }
2988}
c906108c 2989\f
c5aa993b 2990
7a78ae4e 2991/* Handling the various POWER/PowerPC variants. */
c906108c 2992
c906108c 2993/* Information about a particular processor variant. */
7a78ae4e 2994
c906108c 2995struct variant
c5aa993b
JM		 2996 {
2997 /* Name of this variant. */
2998 char *name;
c906108c 2999
c5aa993b
JM		 3000 /* English description of the variant. */
3001 char *description;
c906108c 3002
64366f1c 3003 /* bfd_arch_info.arch corresponding to variant. */
7a78ae4e
ND		 3004 enum bfd_architecture arch;
3005
64366f1c 3006 /* bfd_arch_info.mach corresponding to variant. */
7a78ae4e
ND		 3007 unsigned long mach;
3008
7cc46491
DJ		 3009 /* Target description for this variant. */
3010 struct target_desc **tdesc;
c5aa993b 3011 };
c906108c 3012
489461e2 3013static struct variant variants[] =
c906108c 3014{
7a78ae4e 3015 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
7284e1be 3016 bfd_mach_ppc, &tdesc_powerpc_altivec32},
7a78ae4e 3017 {"power", "POWER user-level", bfd_arch_rs6000,
7cc46491 3018 bfd_mach_rs6k, &tdesc_rs6000},
7a78ae4e 3019 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
7cc46491 3020 bfd_mach_ppc_403, &tdesc_powerpc_403},
4d09ffea
MS		 3021 {"405", "IBM PowerPC 405", bfd_arch_powerpc,
3022 bfd_mach_ppc_405, &tdesc_powerpc_405},
7a78ae4e 3023 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
7cc46491 3024 bfd_mach_ppc_601, &tdesc_powerpc_601},
7a78ae4e 3025 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
7cc46491 3026 bfd_mach_ppc_602, &tdesc_powerpc_602},
7a78ae4e 3027 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
7cc46491 3028 bfd_mach_ppc_603, &tdesc_powerpc_603},
7a78ae4e 3029 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
7cc46491 3030 604, &tdesc_powerpc_604},
7a78ae4e 3031 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
7cc46491 3032 bfd_mach_ppc_403gc, &tdesc_powerpc_403gc},
7a78ae4e 3033 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
7cc46491 3034 bfd_mach_ppc_505, &tdesc_powerpc_505},
7a78ae4e 3035 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
7cc46491 3036 bfd_mach_ppc_860, &tdesc_powerpc_860},
7a78ae4e 3037 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
7cc46491 3038 bfd_mach_ppc_750, &tdesc_powerpc_750},
1fcc0bb8 3039 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
7cc46491 3040 bfd_mach_ppc_7400, &tdesc_powerpc_7400},
c8001721 3041 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
7cc46491 3042 bfd_mach_ppc_e500, &tdesc_powerpc_e500},
7a78ae4e 3043
5d57ee30
KB		 3044 /* 64-bit */
3045 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
7284e1be 3046 bfd_mach_ppc64, &tdesc_powerpc_altivec64},
7a78ae4e 3047 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
7cc46491 3048 bfd_mach_ppc_620, &tdesc_powerpc_64},
5d57ee30 3049 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
7cc46491 3050 bfd_mach_ppc_630, &tdesc_powerpc_64},
7a78ae4e 3051 {"a35", "PowerPC A35", bfd_arch_powerpc,
7cc46491 3052 bfd_mach_ppc_a35, &tdesc_powerpc_64},
5d57ee30 3053 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
7cc46491 3054 bfd_mach_ppc_rs64ii, &tdesc_powerpc_64},
5d57ee30 3055 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
7cc46491 3056 bfd_mach_ppc_rs64iii, &tdesc_powerpc_64},
5d57ee30 3057
64366f1c 3058 /* FIXME: I haven't checked the register sets of the following. */
7a78ae4e 3059 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
7cc46491 3060 bfd_mach_rs6k_rs1, &tdesc_rs6000},
7a78ae4e 3061 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
7cc46491 3062 bfd_mach_rs6k_rsc, &tdesc_rs6000},
7a78ae4e 3063 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
7cc46491 3064 bfd_mach_rs6k_rs2, &tdesc_rs6000},
7a78ae4e 3065
7cc46491 3066 {0, 0, 0, 0, 0}
c906108c
SS		 3067};
3068
7a78ae4e 3069/* Return the variant corresponding to architecture ARCH and machine number
64366f1c 3070 MACH. If no such variant exists, return null. */
c906108c 3071
7a78ae4e
ND		 3072static const struct variant *
3073find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
c906108c 3074{
7a78ae4e 3075 const struct variant *v;
c5aa993b 3076
7a78ae4e
ND		 3077 for (v = variants; v->name; v++)
3078 if (arch == v->arch && mach == v->mach)
3079 return v;
c906108c 3080
7a78ae4e 3081 return NULL;
c906108c 3082}
9364a0ef
EZ		 3083
3084static int
3085gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
3086{
40887e1a 3087 if (info->endian == BFD_ENDIAN_BIG)
9364a0ef
EZ		 3088 return print_insn_big_powerpc (memaddr, info);
3089 else
3090 return print_insn_little_powerpc (memaddr, info);
3091}
7a78ae4e 3092\f
61a65099
KB		 3093static CORE_ADDR
3094rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
3095{
3e8c568d 3096 return frame_unwind_register_unsigned (next_frame,
8b164abb 3097 gdbarch_pc_regnum (gdbarch));
61a65099
KB		 3098}
3099
3100static struct frame_id
1af5d7ce 3101rs6000_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
61a65099 3102{
1af5d7ce
UW		 3103 return frame_id_build (get_frame_register_unsigned
3104 (this_frame, gdbarch_sp_regnum (gdbarch)),
3105 get_frame_pc (this_frame));
61a65099
KB		 3106}
3107
3108struct rs6000_frame_cache
3109{
3110 CORE_ADDR base;
3111 CORE_ADDR initial_sp;
3112 struct trad_frame_saved_reg *saved_regs;
3113};
3114
3115static struct rs6000_frame_cache *
1af5d7ce 3116rs6000_frame_cache (struct frame_info *this_frame, void **this_cache)
61a65099
KB		 3117{
3118 struct rs6000_frame_cache *cache;
1af5d7ce 3119 struct gdbarch *gdbarch = get_frame_arch (this_frame);
61a65099 3120 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 3121 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
61a65099
KB		 3122 struct rs6000_framedata fdata;
3123 int wordsize = tdep->wordsize;
e10b1c4c 3124 CORE_ADDR func, pc;
61a65099
KB		 3125
3126 if ((*this_cache) != NULL)
3127 return (*this_cache);
3128 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
3129 (*this_cache) = cache;
1af5d7ce 3130 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
61a65099 3131
1af5d7ce
UW		 3132 func = get_frame_func (this_frame);
3133 pc = get_frame_pc (this_frame);
be8626e0 3134 skip_prologue (gdbarch, func, pc, &fdata);
e10b1c4c
DJ		 3135
3136 /* Figure out the parent's stack pointer. */
3137
3138 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3139 address of the current frame. Things might be easier if the
3140 ->frame pointed to the outer-most address of the frame. In
3141 the mean time, the address of the prev frame is used as the
3142 base address of this frame. */
1af5d7ce
UW		 3143 cache->base = get_frame_register_unsigned
3144 (this_frame, gdbarch_sp_regnum (gdbarch));
e10b1c4c
DJ		 3145
3146 /* If the function appears to be frameless, check a couple of likely
3147 indicators that we have simply failed to find the frame setup.
3148 Two common cases of this are missing symbols (i.e.
ef02daa9 3149 get_frame_func returns the wrong address or 0), and assembly
e10b1c4c
DJ		 3150 stubs which have a fast exit path but set up a frame on the slow
3151 path.
3152
3153 If the LR appears to return to this function, then presume that
3154 we have an ABI compliant frame that we failed to find. */
3155 if (fdata.frameless && fdata.lr_offset == 0)
61a65099 3156 {
e10b1c4c
DJ		 3157 CORE_ADDR saved_lr;
3158 int make_frame = 0;
3159
1af5d7ce 3160 saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum);
e10b1c4c
DJ		 3161 if (func == 0 && saved_lr == pc)
3162 make_frame = 1;
3163 else if (func != 0)
3164 {
3165 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
3166 if (func == saved_func)
3167 make_frame = 1;
3168 }
3169
3170 if (make_frame)
3171 {
3172 fdata.frameless = 0;
de6a76fd 3173 fdata.lr_offset = tdep->lr_frame_offset;
e10b1c4c 3174 }
61a65099 3175 }
e10b1c4c
DJ		 3176
3177 if (!fdata.frameless)
3178 /* Frameless really means stackless. */
e17a4113
UW		 3179 cache->base
3180 = read_memory_unsigned_integer (cache->base, wordsize, byte_order);
e10b1c4c 3181
3e8c568d 3182 trad_frame_set_value (cache->saved_regs,
8b164abb 3183 gdbarch_sp_regnum (gdbarch), cache->base);
61a65099
KB		 3184
3185 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3186 All fpr's from saved_fpr to fp31 are saved. */
3187
3188 if (fdata.saved_fpr >= 0)
3189 {
3190 int i;
3191 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
383f0f5b
JB		 3192
3193 /* If skip_prologue says floating-point registers were saved,
3194 but the current architecture has no floating-point registers,
3195 then that's strange. But we have no indices to even record
3196 the addresses under, so we just ignore it. */
3197 if (ppc_floating_point_unit_p (gdbarch))
063715bf 3198 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
383f0f5b
JB		 3199 {
3200 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3201 fpr_addr += 8;
3202 }
61a65099
KB		 3203 }
3204
3205 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
46a9b8ed
DJ		 3206 All gpr's from saved_gpr to gpr31 are saved (except during the
3207 prologue). */
61a65099
KB		 3208
3209 if (fdata.saved_gpr >= 0)
3210 {
3211 int i;
3212 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
063715bf 3213 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
61a65099 3214 {
46a9b8ed
DJ		 3215 if (fdata.gpr_mask & (1U << i))
3216 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
61a65099
KB		 3217 gpr_addr += wordsize;
3218 }
3219 }
3220
3221 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3222 All vr's from saved_vr to vr31 are saved. */
3223 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3224 {
3225 if (fdata.saved_vr >= 0)
3226 {
3227 int i;
3228 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3229 for (i = fdata.saved_vr; i < 32; i++)
3230 {
3231 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3232 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3233 }
3234 }
3235 }
3236
3237 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
0df8b418 3238 All vr's from saved_ev to ev31 are saved. ????? */
5a9e69ba 3239 if (tdep->ppc_ev0_regnum != -1)
61a65099
KB		 3240 {
3241 if (fdata.saved_ev >= 0)
3242 {
3243 int i;
3244 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
063715bf 3245 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
61a65099
KB		 3246 {
3247 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3248 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
3249 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3250 }
3251 }
3252 }
3253
3254 /* If != 0, fdata.cr_offset is the offset from the frame that
3255 holds the CR. */
3256 if (fdata.cr_offset != 0)
0df8b418
MS		 3257 cache->saved_regs[tdep->ppc_cr_regnum].addr
3258 = cache->base + fdata.cr_offset;
61a65099
KB		 3259
3260 /* If != 0, fdata.lr_offset is the offset from the frame that
3261 holds the LR. */
3262 if (fdata.lr_offset != 0)
0df8b418
MS		 3263 cache->saved_regs[tdep->ppc_lr_regnum].addr
3264 = cache->base + fdata.lr_offset;
46a9b8ed
DJ		 3265 else if (fdata.lr_register != -1)
3266 cache->saved_regs[tdep->ppc_lr_regnum].realreg = fdata.lr_register;
61a65099 3267 /* The PC is found in the link register. */
8b164abb 3268 cache->saved_regs[gdbarch_pc_regnum (gdbarch)] =
3e8c568d 3269 cache->saved_regs[tdep->ppc_lr_regnum];
61a65099
KB		 3270
3271 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3272 holds the VRSAVE. */
3273 if (fdata.vrsave_offset != 0)
0df8b418
MS		 3274 cache->saved_regs[tdep->ppc_vrsave_regnum].addr
3275 = cache->base + fdata.vrsave_offset;
61a65099
KB		 3276
3277 if (fdata.alloca_reg < 0)
3278 /* If no alloca register used, then fi->frame is the value of the
3279 %sp for this frame, and it is good enough. */
1af5d7ce
UW		 3280 cache->initial_sp
3281 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
61a65099 3282 else
1af5d7ce
UW		 3283 cache->initial_sp
3284 = get_frame_register_unsigned (this_frame, fdata.alloca_reg);
61a65099
KB		 3285
3286 return cache;
3287}
3288
3289static void
1af5d7ce 3290rs6000_frame_this_id (struct frame_info *this_frame, void **this_cache,
61a65099
KB		 3291 struct frame_id *this_id)
3292{
1af5d7ce 3293 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099 3294 this_cache);
5b197912
UW		 3295 /* This marks the outermost frame. */
3296 if (info->base == 0)
3297 return;
3298
1af5d7ce 3299 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
61a65099
KB		 3300}
3301
1af5d7ce
UW		 3302static struct value *
3303rs6000_frame_prev_register (struct frame_info *this_frame,
3304 void **this_cache, int regnum)
61a65099 3305{
1af5d7ce 3306 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099 3307 this_cache);
1af5d7ce 3308 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
61a65099
KB		 3309}
3310
3311static const struct frame_unwind rs6000_frame_unwind =
3312{
3313 NORMAL_FRAME,
8fbca658 3314 default_frame_unwind_stop_reason,
61a65099 3315 rs6000_frame_this_id,
1af5d7ce
UW		 3316 rs6000_frame_prev_register,
3317 NULL,
3318 default_frame_sniffer
61a65099 3319};
61a65099
KB		 3320\f
3321
3322static CORE_ADDR
1af5d7ce 3323rs6000_frame_base_address (struct frame_info *this_frame, void **this_cache)
61a65099 3324{
1af5d7ce 3325 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099
KB		 3326 this_cache);
3327 return info->initial_sp;
3328}
3329
3330static const struct frame_base rs6000_frame_base = {
3331 &rs6000_frame_unwind,
3332 rs6000_frame_base_address,
3333 rs6000_frame_base_address,
3334 rs6000_frame_base_address
3335};
3336
3337static const struct frame_base *
1af5d7ce 3338rs6000_frame_base_sniffer (struct frame_info *this_frame)
61a65099
KB		 3339{
3340 return &rs6000_frame_base;
3341}
3342
9274a07c
LM		 3343/* DWARF-2 frame support. Used to handle the detection of
3344 clobbered registers during function calls. */
3345
3346static void
3347ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3348 struct dwarf2_frame_state_reg *reg,
4a4e5149 3349 struct frame_info *this_frame)
9274a07c
LM		 3350{
3351 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3352
3353 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3354 non-volatile registers. We will use the same code for both. */
3355
3356 /* Call-saved GP registers. */
3357 if ((regnum >= tdep->ppc_gp0_regnum + 14
3358 && regnum <= tdep->ppc_gp0_regnum + 31)
3359 || (regnum == tdep->ppc_gp0_regnum + 1))
3360 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3361
3362 /* Call-clobbered GP registers. */
3363 if ((regnum >= tdep->ppc_gp0_regnum + 3
3364 && regnum <= tdep->ppc_gp0_regnum + 12)
3365 || (regnum == tdep->ppc_gp0_regnum))
3366 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3367
3368 /* Deal with FP registers, if supported. */
3369 if (tdep->ppc_fp0_regnum >= 0)
3370 {
3371 /* Call-saved FP registers. */
3372 if ((regnum >= tdep->ppc_fp0_regnum + 14
3373 && regnum <= tdep->ppc_fp0_regnum + 31))
3374 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3375
3376 /* Call-clobbered FP registers. */
3377 if ((regnum >= tdep->ppc_fp0_regnum
3378 && regnum <= tdep->ppc_fp0_regnum + 13))
3379 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3380 }
3381
3382 /* Deal with ALTIVEC registers, if supported. */
3383 if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0)
3384 {
3385 /* Call-saved Altivec registers. */
3386 if ((regnum >= tdep->ppc_vr0_regnum + 20
3387 && regnum <= tdep->ppc_vr0_regnum + 31)
3388 || regnum == tdep->ppc_vrsave_regnum)
3389 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3390
3391 /* Call-clobbered Altivec registers. */
3392 if ((regnum >= tdep->ppc_vr0_regnum
3393 && regnum <= tdep->ppc_vr0_regnum + 19))
3394 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3395 }
3396
3397 /* Handle PC register and Stack Pointer correctly. */
40a6adc1 3398 if (regnum == gdbarch_pc_regnum (gdbarch))
9274a07c 3399 reg->how = DWARF2_FRAME_REG_RA;
40a6adc1 3400 else if (regnum == gdbarch_sp_regnum (gdbarch))
9274a07c
LM		 3401 reg->how = DWARF2_FRAME_REG_CFA;
3402}
3403
3404
74af9197
NF		 3405/* Return true if a .gnu_attributes section exists in BFD and it
3406 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3407 section exists in BFD and it indicates that SPE extensions are in
3408 use. Check the .gnu.attributes section first, as the binary might be
3409 compiled for SPE, but not actually using SPE instructions. */
3410
3411static int
3412bfd_uses_spe_extensions (bfd *abfd)
3413{
3414 asection *sect;
3415 gdb_byte *contents = NULL;
3416 bfd_size_type size;
3417 gdb_byte *ptr;
3418 int success = 0;
3419 int vector_abi;
3420
3421 if (!abfd)
3422 return 0;
3423
50a99728 3424#ifdef HAVE_ELF
74af9197
NF		 3425 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3426 could be using the SPE vector abi without actually using any spe
3427 bits whatsoever. But it's close enough for now. */
3428 vector_abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_GNU,
3429 Tag_GNU_Power_ABI_Vector);
3430 if (vector_abi == 3)
3431 return 1;
50a99728 3432#endif
74af9197
NF		 3433
3434 sect = bfd_get_section_by_name (abfd, ".PPC.EMB.apuinfo");
3435 if (!sect)
3436 return 0;
3437
3438 size = bfd_get_section_size (sect);
3439 contents = xmalloc (size);
3440 if (!bfd_get_section_contents (abfd, sect, contents, 0, size))
3441 {
3442 xfree (contents);
3443 return 0;
3444 }
3445
3446 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3447
3448 struct {
3449 uint32 name_len;
3450 uint32 data_len;
3451 uint32 type;
3452 char name[name_len rounded up to 4-byte alignment];
3453 char data[data_len];
3454 };
3455
3456 Technically, there's only supposed to be one such structure in a
3457 given apuinfo section, but the linker is not always vigilant about
3458 merging apuinfo sections from input files. Just go ahead and parse
3459 them all, exiting early when we discover the binary uses SPE
3460 insns.
3461
3462 It's not specified in what endianness the information in this
3463 section is stored. Assume that it's the endianness of the BFD. */
3464 ptr = contents;
3465 while (1)
3466 {
3467 unsigned int name_len;
3468 unsigned int data_len;
3469 unsigned int type;
3470
3471 /* If we can't read the first three fields, we're done. */
3472 if (size < 12)
3473 break;
3474
3475 name_len = bfd_get_32 (abfd, ptr);
3476 name_len = (name_len + 3) & ~3U; /* Round to 4 bytes. */
3477 data_len = bfd_get_32 (abfd, ptr + 4);
3478 type = bfd_get_32 (abfd, ptr + 8);
3479 ptr += 12;
3480
3481 /* The name must be "APUinfo\0". */
3482 if (name_len != 8
3483 && strcmp ((const char *) ptr, "APUinfo") != 0)
3484 break;
3485 ptr += name_len;
3486
3487 /* The type must be 2. */
3488 if (type != 2)
3489 break;
3490
3491 /* The data is stored as a series of uint32. The upper half of
3492 each uint32 indicates the particular APU used and the lower
3493 half indicates the revision of that APU. We just care about
3494 the upper half. */
3495
3496 /* Not 4-byte quantities. */
3497 if (data_len & 3U)
3498 break;
3499
3500 while (data_len)
3501 {
3502 unsigned int apuinfo = bfd_get_32 (abfd, ptr);
3503 unsigned int apu = apuinfo >> 16;
3504 ptr += 4;
3505 data_len -= 4;
3506
3507 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3508 either. */
3509 if (apu == 0x100 || apu == 0x101)
3510 {
3511 success = 1;
3512 data_len = 0;
3513 }
3514 }
3515
3516 if (success)
3517 break;
3518 }
3519
3520 xfree (contents);
3521 return success;
3522}
3523
7a78ae4e
ND		 3524/* Initialize the current architecture based on INFO. If possible, re-use an
3525 architecture from ARCHES, which is a list of architectures already created
3526 during this debugging session.
c906108c 3527
7a78ae4e 3528 Called e.g. at program startup, when reading a core file, and when reading
64366f1c 3529 a binary file. */
c906108c 3530
7a78ae4e
ND		 3531static struct gdbarch *
3532rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3533{
3534 struct gdbarch *gdbarch;
3535 struct gdbarch_tdep *tdep;
7cc46491 3536 int wordsize, from_xcoff_exec, from_elf_exec;
7a78ae4e
ND		 3537 enum bfd_architecture arch;
3538 unsigned long mach;
3539 bfd abfd;
55eddb0f
DJ		 3540 enum auto_boolean soft_float_flag = powerpc_soft_float_global;
3541 int soft_float;
3542 enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
604c2f83
LM		 3543 int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0,
3544 have_vsx = 0;
7cc46491
DJ		 3545 int tdesc_wordsize = -1;
3546 const struct target_desc *tdesc = info.target_desc;
3547 struct tdesc_arch_data *tdesc_data = NULL;
f949c649 3548 int num_pseudoregs = 0;
604c2f83 3549 int cur_reg;
7a78ae4e 3550
f4d9bade
UW		 3551 /* INFO may refer to a binary that is not of the PowerPC architecture,
3552 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
3553 In this case, we must not attempt to infer properties of the (PowerPC
3554 side) of the target system from properties of that executable. Trust
3555 the target description instead. */
3556 if (info.abfd
3557 && bfd_get_arch (info.abfd) != bfd_arch_powerpc
3558 && bfd_get_arch (info.abfd) != bfd_arch_rs6000)
3559 info.abfd = NULL;
3560
9aa1e687 3561 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
7a78ae4e
ND		 3562 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3563
9aa1e687
KB		 3564 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3565 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3566
e712c1cf 3567 /* Check word size. If INFO is from a binary file, infer it from
64366f1c 3568 that, else choose a likely default. */
9aa1e687 3569 if (from_xcoff_exec)
c906108c 3570 {
11ed25ac 3571 if (bfd_xcoff_is_xcoff64 (info.abfd))
7a78ae4e
ND		 3572 wordsize = 8;
3573 else
3574 wordsize = 4;
c906108c 3575 }
9aa1e687
KB		 3576 else if (from_elf_exec)
3577 {
3578 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3579 wordsize = 8;
3580 else
3581 wordsize = 4;
3582 }
7cc46491
DJ		 3583 else if (tdesc_has_registers (tdesc))
3584 wordsize = -1;
c906108c 3585 else
7a78ae4e 3586 {
27b15785
KB		 3587 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3588 wordsize = info.bfd_arch_info->bits_per_word /
3589 info.bfd_arch_info->bits_per_byte;
3590 else
3591 wordsize = 4;
7a78ae4e 3592 }
c906108c 3593
475bbd17
JB		 3594 /* Get the architecture and machine from the BFD. */
3595 arch = info.bfd_arch_info->arch;
3596 mach = info.bfd_arch_info->mach;
5bf1c677
EZ		 3597
3598 /* For e500 executables, the apuinfo section is of help here. Such
3599 section contains the identifier and revision number of each
3600 Application-specific Processing Unit that is present on the
3601 chip. The content of the section is determined by the assembler
3602 which looks at each instruction and determines which unit (and
74af9197
NF		 3603 which version of it) can execute it. Grovel through the section
3604 looking for relevant e500 APUs. */
5bf1c677 3605
74af9197 3606 if (bfd_uses_spe_extensions (info.abfd))
5bf1c677 3607 {
74af9197
NF		 3608 arch = info.bfd_arch_info->arch;
3609 mach = bfd_mach_ppc_e500;
3610 bfd_default_set_arch_mach (&abfd, arch, mach);
3611 info.bfd_arch_info = bfd_get_arch_info (&abfd);
5bf1c677
EZ		 3612 }
3613
7cc46491
DJ		 3614 /* Find a default target description which describes our register
3615 layout, if we do not already have one. */
3616 if (! tdesc_has_registers (tdesc))
3617 {
3618 const struct variant *v;
3619
3620 /* Choose variant. */
3621 v = find_variant_by_arch (arch, mach);
3622 if (!v)
3623 return NULL;
3624
3625 tdesc = *v->tdesc;
3626 }
3627
3628 gdb_assert (tdesc_has_registers (tdesc));
3629
3630 /* Check any target description for validity. */
3631 if (tdesc_has_registers (tdesc))
3632 {
3633 static const char *const gprs[] = {
3634 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3635 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3636 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3637 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3638 };
3639 static const char *const segment_regs[] = {
3640 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
3641 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
3642 };
3643 const struct tdesc_feature *feature;
3644 int i, valid_p;
3645 static const char *const msr_names[] = { "msr", "ps" };
3646 static const char *const cr_names[] = { "cr", "cnd" };
3647 static const char *const ctr_names[] = { "ctr", "cnt" };
3648
3649 feature = tdesc_find_feature (tdesc,
3650 "org.gnu.gdb.power.core");
3651 if (feature == NULL)
3652 return NULL;
3653
3654 tdesc_data = tdesc_data_alloc ();
3655
3656 valid_p = 1;
3657 for (i = 0; i < ppc_num_gprs; i++)
3658 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]);
3659 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM,
3660 "pc");
3661 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM,
3662 "lr");
3663 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM,
3664 "xer");
3665
3666 /* Allow alternate names for these registers, to accomodate GDB's
3667 historic naming. */
3668 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3669 PPC_MSR_REGNUM, msr_names);
3670 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3671 PPC_CR_REGNUM, cr_names);
3672 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3673 PPC_CTR_REGNUM, ctr_names);
3674
3675 if (!valid_p)
3676 {
3677 tdesc_data_cleanup (tdesc_data);
3678 return NULL;
3679 }
3680
3681 have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM,
3682 "mq");
3683
3684 tdesc_wordsize = tdesc_register_size (feature, "pc") / 8;
3685 if (wordsize == -1)
3686 wordsize = tdesc_wordsize;
3687
3688 feature = tdesc_find_feature (tdesc,
3689 "org.gnu.gdb.power.fpu");
3690 if (feature != NULL)
3691 {
3692 static const char *const fprs[] = {
3693 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
3694 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
3695 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
3696 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
3697 };
3698 valid_p = 1;
3699 for (i = 0; i < ppc_num_fprs; i++)
3700 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3701 PPC_F0_REGNUM + i, fprs[i]);
3702 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3703 PPC_FPSCR_REGNUM, "fpscr");
3704
3705 if (!valid_p)
3706 {
3707 tdesc_data_cleanup (tdesc_data);
3708 return NULL;
3709 }
3710 have_fpu = 1;
3711 }
3712 else
3713 have_fpu = 0;
3714
f949c649
TJB		 3715 /* The DFP pseudo-registers will be available when there are floating
3716 point registers. */
3717 have_dfp = have_fpu;
3718
7cc46491
DJ		 3719 feature = tdesc_find_feature (tdesc,
3720 "org.gnu.gdb.power.altivec");
3721 if (feature != NULL)
3722 {
3723 static const char *const vector_regs[] = {
3724 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
3725 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
3726 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
3727 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
3728 };
3729
3730 valid_p = 1;
3731 for (i = 0; i < ppc_num_gprs; i++)
3732 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3733 PPC_VR0_REGNUM + i,
3734 vector_regs[i]);
3735 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3736 PPC_VSCR_REGNUM, "vscr");
3737 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3738 PPC_VRSAVE_REGNUM, "vrsave");
3739
3740 if (have_spe || !valid_p)
3741 {
3742 tdesc_data_cleanup (tdesc_data);
3743 return NULL;
3744 }
3745 have_altivec = 1;
3746 }
3747 else
3748 have_altivec = 0;
3749
604c2f83
LM		 3750 /* Check for POWER7 VSX registers support. */
3751 feature = tdesc_find_feature (tdesc,
3752 "org.gnu.gdb.power.vsx");
3753
3754 if (feature != NULL)
3755 {
3756 static const char *const vsx_regs[] = {
3757 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
3758 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
3759 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
3760 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
3761 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
3762 "vs30h", "vs31h"
3763 };
3764
3765 valid_p = 1;
3766
3767 for (i = 0; i < ppc_num_vshrs; i++)
3768 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3769 PPC_VSR0_UPPER_REGNUM + i,
3770 vsx_regs[i]);
3771 if (!valid_p)
3772 {
3773 tdesc_data_cleanup (tdesc_data);
3774 return NULL;
3775 }
3776
3777 have_vsx = 1;
3778 }
3779 else
3780 have_vsx = 0;
3781
7cc46491
DJ		 3782 /* On machines supporting the SPE APU, the general-purpose registers
3783 are 64 bits long. There are SIMD vector instructions to treat them
3784 as pairs of floats, but the rest of the instruction set treats them
3785 as 32-bit registers, and only operates on their lower halves.
3786
3787 In the GDB regcache, we treat their high and low halves as separate
3788 registers. The low halves we present as the general-purpose
3789 registers, and then we have pseudo-registers that stitch together
3790 the upper and lower halves and present them as pseudo-registers.
3791
3792 Thus, the target description is expected to supply the upper
3793 halves separately. */
3794
3795 feature = tdesc_find_feature (tdesc,
3796 "org.gnu.gdb.power.spe");
3797 if (feature != NULL)
3798 {
3799 static const char *const upper_spe[] = {
3800 "ev0h", "ev1h", "ev2h", "ev3h",
3801 "ev4h", "ev5h", "ev6h", "ev7h",
3802 "ev8h", "ev9h", "ev10h", "ev11h",
3803 "ev12h", "ev13h", "ev14h", "ev15h",
3804 "ev16h", "ev17h", "ev18h", "ev19h",
3805 "ev20h", "ev21h", "ev22h", "ev23h",
3806 "ev24h", "ev25h", "ev26h", "ev27h",
3807 "ev28h", "ev29h", "ev30h", "ev31h"
3808 };
3809
3810 valid_p = 1;
3811 for (i = 0; i < ppc_num_gprs; i++)
3812 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3813 PPC_SPE_UPPER_GP0_REGNUM + i,
3814 upper_spe[i]);
3815 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3816 PPC_SPE_ACC_REGNUM, "acc");
3817 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3818 PPC_SPE_FSCR_REGNUM, "spefscr");
3819
3820 if (have_mq || have_fpu || !valid_p)
3821 {
3822 tdesc_data_cleanup (tdesc_data);
3823 return NULL;
3824 }
3825 have_spe = 1;
3826 }
3827 else
3828 have_spe = 0;
3829 }
3830
3831 /* If we have a 64-bit binary on a 32-bit target, complain. Also
3832 complain for a 32-bit binary on a 64-bit target; we do not yet
3833 support that. For instance, the 32-bit ABI routines expect
3834 32-bit GPRs.
3835
3836 As long as there isn't an explicit target description, we'll
3837 choose one based on the BFD architecture and get a word size
3838 matching the binary (probably powerpc:common or
3839 powerpc:common64). So there is only trouble if a 64-bit target
3840 supplies a 64-bit description while debugging a 32-bit
3841 binary. */
3842 if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize)
3843 {
3844 tdesc_data_cleanup (tdesc_data);
3845 return NULL;
3846 }
3847
55eddb0f
DJ		 3848#ifdef HAVE_ELF
3849 if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec)
3850 {
3851 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3852 Tag_GNU_Power_ABI_FP))
3853 {
3854 case 1:
3855 soft_float_flag = AUTO_BOOLEAN_FALSE;
3856 break;
3857 case 2:
3858 soft_float_flag = AUTO_BOOLEAN_TRUE;
3859 break;
3860 default:
3861 break;
3862 }
3863 }
3864
3865 if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec)
3866 {
3867 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3868 Tag_GNU_Power_ABI_Vector))
3869 {
3870 case 1:
3871 vector_abi = POWERPC_VEC_GENERIC;
3872 break;
3873 case 2:
3874 vector_abi = POWERPC_VEC_ALTIVEC;
3875 break;
3876 case 3:
3877 vector_abi = POWERPC_VEC_SPE;
3878 break;
3879 default:
3880 break;
3881 }
3882 }
3883#endif
3884
3885 if (soft_float_flag == AUTO_BOOLEAN_TRUE)
3886 soft_float = 1;
3887 else if (soft_float_flag == AUTO_BOOLEAN_FALSE)
3888 soft_float = 0;
3889 else
3890 soft_float = !have_fpu;
3891
3892 /* If we have a hard float binary or setting but no floating point
3893 registers, downgrade to soft float anyway. We're still somewhat
3894 useful in this scenario. */
3895 if (!soft_float && !have_fpu)
3896 soft_float = 1;
3897
3898 /* Similarly for vector registers. */
3899 if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec)
3900 vector_abi = POWERPC_VEC_GENERIC;
3901
3902 if (vector_abi == POWERPC_VEC_SPE && !have_spe)
3903 vector_abi = POWERPC_VEC_GENERIC;
3904
3905 if (vector_abi == POWERPC_VEC_AUTO)
3906 {
3907 if (have_altivec)
3908 vector_abi = POWERPC_VEC_ALTIVEC;
3909 else if (have_spe)
3910 vector_abi = POWERPC_VEC_SPE;
3911 else
3912 vector_abi = POWERPC_VEC_GENERIC;
3913 }
3914
3915 /* Do not limit the vector ABI based on available hardware, since we
3916 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
3917
7cc46491
DJ		 3918 /* Find a candidate among extant architectures. */
3919 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3920 arches != NULL;
3921 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3922 {
3923 /* Word size in the various PowerPC bfd_arch_info structs isn't
3924 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3925 separate word size check. */
3926 tdep = gdbarch_tdep (arches->gdbarch);
55eddb0f
DJ		 3927 if (tdep && tdep->soft_float != soft_float)
3928 continue;
3929 if (tdep && tdep->vector_abi != vector_abi)
3930 continue;
7cc46491
DJ		 3931 if (tdep && tdep->wordsize == wordsize)
3932 {
3933 if (tdesc_data != NULL)
3934 tdesc_data_cleanup (tdesc_data);
3935 return arches->gdbarch;
3936 }
3937 }
3938
3939 /* None found, create a new architecture from INFO, whose bfd_arch_info
3940 validity depends on the source:
3941 - executable useless
3942 - rs6000_host_arch() good
3943 - core file good
3944 - "set arch" trust blindly
3945 - GDB startup useless but harmless */
3946
3947 tdep = XCALLOC (1, struct gdbarch_tdep);
3948 tdep->wordsize = wordsize;
55eddb0f
DJ		 3949 tdep->soft_float = soft_float;
3950 tdep->vector_abi = vector_abi;
7cc46491 3951
7a78ae4e 3952 gdbarch = gdbarch_alloc (&info, tdep);
7a78ae4e 3953
7cc46491
DJ		 3954 tdep->ppc_gp0_regnum = PPC_R0_REGNUM;
3955 tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2;
3956 tdep->ppc_ps_regnum = PPC_MSR_REGNUM;
3957 tdep->ppc_cr_regnum = PPC_CR_REGNUM;
3958 tdep->ppc_lr_regnum = PPC_LR_REGNUM;
3959 tdep->ppc_ctr_regnum = PPC_CTR_REGNUM;
3960 tdep->ppc_xer_regnum = PPC_XER_REGNUM;
3961 tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1;
3962
3963 tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1;
3964 tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1;
604c2f83 3965 tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1;
7cc46491
DJ		 3966 tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1;
3967 tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1;
3968 tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1;
3969 tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1;
3970 tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
3971
3972 set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
3973 set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3974 set_gdbarch_deprecated_fp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3975 set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum);
9f643768 3976 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
7cc46491
DJ		 3977
3978 /* The XML specification for PowerPC sensibly calls the MSR "msr".
3979 GDB traditionally called it "ps", though, so let GDB add an
3980 alias. */
3981 set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum);
3982
4a7622d1 3983 if (wordsize == 8)
05580c65 3984 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
afd48b75 3985 else
4a7622d1 3986 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
c8001721 3987
baffbae0
JB		 3988 /* Set lr_frame_offset. */
3989 if (wordsize == 8)
3990 tdep->lr_frame_offset = 16;
baffbae0 3991 else
4a7622d1 3992 tdep->lr_frame_offset = 4;
baffbae0 3993
604c2f83 3994 if (have_spe || have_dfp || have_vsx)
7cc46491 3995 {
f949c649 3996 set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read);
0df8b418
MS		 3997 set_gdbarch_pseudo_register_write (gdbarch,
3998 rs6000_pseudo_register_write);
7cc46491 3999 }
1fcc0bb8 4000
e0d24f8d
WZ		 4001 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
4002
56a6dfb9 4003 /* Select instruction printer. */
708ff411 4004 if (arch == bfd_arch_rs6000)
9364a0ef 4005 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
56a6dfb9 4006 else
9364a0ef 4007 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
7495d1dc 4008
5a9e69ba 4009 set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS);
f949c649
TJB		 4010
4011 if (have_spe)
4012 num_pseudoregs += 32;
4013 if (have_dfp)
4014 num_pseudoregs += 16;
604c2f83
LM		 4015 if (have_vsx)
4016 /* Include both VSX and Extended FP registers. */
4017 num_pseudoregs += 96;
f949c649
TJB		 4018
4019 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs);
7a78ae4e
ND		 4020
4021 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
4022 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
4023 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4024 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
4025 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4026 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4027 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4a7622d1 4028 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
4e409299 4029 set_gdbarch_char_signed (gdbarch, 0);
7a78ae4e 4030
11269d7e 4031 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
4a7622d1 4032 if (wordsize == 8)
8b148df9
AC		 4033 /* PPC64 SYSV. */
4034 set_gdbarch_frame_red_zone_size (gdbarch, 288);
7a78ae4e 4035
691d145a
JB		 4036 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
4037 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
4038 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
4039
18ed0c4e
JB		 4040 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
4041 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
d217aaed 4042
4a7622d1 4043 if (wordsize == 4)
77b2b6d4 4044 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
4a7622d1 4045 else if (wordsize == 8)
8be9034a 4046 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
7a78ae4e 4047
7a78ae4e 4048 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
0d1243d9 4049 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
8ab3d180 4050 set_gdbarch_skip_main_prologue (gdbarch, rs6000_skip_main_prologue);
0d1243d9 4051
7a78ae4e 4052 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
7a78ae4e
ND		 4053 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
4054
203c3895 4055 /* The value of symbols of type N_SO and N_FUN maybe null when
0df8b418 4056 it shouldn't be. */
203c3895
UW		 4057 set_gdbarch_sofun_address_maybe_missing (gdbarch, 1);
4058
ce5eab59 4059 /* Handles single stepping of atomic sequences. */
4a7622d1 4060 set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence);
ce5eab59 4061
0df8b418 4062 /* Not sure on this. FIXMEmgo */
7a78ae4e
ND		 4063 set_gdbarch_frame_args_skip (gdbarch, 8);
4064
143985b7
AF		 4065 /* Helpers for function argument information. */
4066 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
4067
6f7f3f0d
UW		 4068 /* Trampoline. */
4069 set_gdbarch_in_solib_return_trampoline
4070 (gdbarch, rs6000_in_solib_return_trampoline);
4071 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code);
4072
4fc771b8 4073 /* Hook in the DWARF CFI frame unwinder. */
1af5d7ce 4074 dwarf2_append_unwinders (gdbarch);
4fc771b8
DJ		 4075 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum);
4076
9274a07c
LM		 4077 /* Frame handling. */
4078 dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg);
4079
2454a024
UW		 4080 /* Setup displaced stepping. */
4081 set_gdbarch_displaced_step_copy_insn (gdbarch,
4082 simple_displaced_step_copy_insn);
99e40580
UW		 4083 set_gdbarch_displaced_step_hw_singlestep (gdbarch,
4084 ppc_displaced_step_hw_singlestep);
2454a024
UW		 4085 set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup);
4086 set_gdbarch_displaced_step_free_closure (gdbarch,
4087 simple_displaced_step_free_closure);
4088 set_gdbarch_displaced_step_location (gdbarch,
4089 displaced_step_at_entry_point);
4090
4091 set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE);
4092
7b112f9c 4093 /* Hook in ABI-specific overrides, if they have been registered. */
8a4c2d24
UW		 4094 info.target_desc = tdesc;
4095 info.tdep_info = (void *) tdesc_data;
4be87837 4096 gdbarch_init_osabi (info, gdbarch);
7b112f9c 4097
61a65099
KB		 4098 switch (info.osabi)
4099 {
f5aecab8 4100 case GDB_OSABI_LINUX:
61a65099
KB		 4101 case GDB_OSABI_NETBSD_AOUT:
4102 case GDB_OSABI_NETBSD_ELF:
4103 case GDB_OSABI_UNKNOWN:
61a65099 4104 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
1af5d7ce
UW		 4105 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
4106 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
61a65099
KB		 4107 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
4108 break;
4109 default:
61a65099 4110 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
81332287
KB		 4111
4112 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
1af5d7ce
UW		 4113 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
4114 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
81332287 4115 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
61a65099
KB		 4116 }
4117
7cc46491
DJ		 4118 set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type);
4119 set_tdesc_pseudo_register_reggroup_p (gdbarch,
4120 rs6000_pseudo_register_reggroup_p);
4121 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
4122
4123 /* Override the normal target description method to make the SPE upper
4124 halves anonymous. */
4125 set_gdbarch_register_name (gdbarch, rs6000_register_name);
4126
604c2f83
LM		 4127 /* Choose register numbers for all supported pseudo-registers. */
4128 tdep->ppc_ev0_regnum = -1;
4129 tdep->ppc_dl0_regnum = -1;
4130 tdep->ppc_vsr0_regnum = -1;
4131 tdep->ppc_efpr0_regnum = -1;
9f643768 4132
604c2f83
LM		 4133 cur_reg = gdbarch_num_regs (gdbarch);
4134
4135 if (have_spe)
4136 {
4137 tdep->ppc_ev0_regnum = cur_reg;
4138 cur_reg += 32;
4139 }
4140 if (have_dfp)
4141 {
4142 tdep->ppc_dl0_regnum = cur_reg;
4143 cur_reg += 16;
4144 }
4145 if (have_vsx)
4146 {
4147 tdep->ppc_vsr0_regnum = cur_reg;
4148 cur_reg += 64;
4149 tdep->ppc_efpr0_regnum = cur_reg;
4150 cur_reg += 32;
4151 }
f949c649 4152
604c2f83
LM		 4153 gdb_assert (gdbarch_num_regs (gdbarch)
4154 + gdbarch_num_pseudo_regs (gdbarch) == cur_reg);
f949c649 4155
debb1f09
JB		 4156 /* Register the ravenscar_arch_ops. */
4157 if (mach == bfd_mach_ppc_e500)
4158 register_e500_ravenscar_ops (gdbarch);
4159 else
4160 register_ppc_ravenscar_ops (gdbarch);
4161
7a78ae4e 4162 return gdbarch;
c906108c
SS		 4163}
4164
7b112f9c 4165static void
8b164abb 4166rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
7b112f9c 4167{
8b164abb 4168 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7b112f9c
JT		 4169
4170 if (tdep == NULL)
4171 return;
4172
4be87837 4173 /* FIXME: Dump gdbarch_tdep. */
7b112f9c
JT		 4174}
4175
55eddb0f
DJ		 4176/* PowerPC-specific commands. */
4177
4178static void
4179set_powerpc_command (char *args, int from_tty)
4180{
4181 printf_unfiltered (_("\
4182\"set powerpc\" must be followed by an appropriate subcommand.\n"));
4183 help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout);
4184}
4185
4186static void
4187show_powerpc_command (char *args, int from_tty)
4188{
4189 cmd_show_list (showpowerpccmdlist, from_tty, "");
4190}
4191
4192static void
4193powerpc_set_soft_float (char *args, int from_tty,
4194 struct cmd_list_element *c)
4195{
4196 struct gdbarch_info info;
4197
4198 /* Update the architecture. */
4199 gdbarch_info_init (&info);
4200 if (!gdbarch_update_p (info))
9b20d036 4201 internal_error (__FILE__, __LINE__, _("could not update architecture"));
55eddb0f
DJ		 4202}
4203
4204static void
4205powerpc_set_vector_abi (char *args, int from_tty,
4206 struct cmd_list_element *c)
4207{
4208 struct gdbarch_info info;
4209 enum powerpc_vector_abi vector_abi;
4210
4211 for (vector_abi = POWERPC_VEC_AUTO;
4212 vector_abi != POWERPC_VEC_LAST;
4213 vector_abi++)
4214 if (strcmp (powerpc_vector_abi_string,
4215 powerpc_vector_strings[vector_abi]) == 0)
4216 {
4217 powerpc_vector_abi_global = vector_abi;
4218 break;
4219 }
4220
4221 if (vector_abi == POWERPC_VEC_LAST)
4222 internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."),
4223 powerpc_vector_abi_string);
4224
4225 /* Update the architecture. */
4226 gdbarch_info_init (&info);
4227 if (!gdbarch_update_p (info))
9b20d036 4228 internal_error (__FILE__, __LINE__, _("could not update architecture"));
55eddb0f
DJ		 4229}
4230
e09342b5
TJB		 4231/* Show the current setting of the exact watchpoints flag. */
4232
4233static void
4234show_powerpc_exact_watchpoints (struct ui_file *file, int from_tty,
4235 struct cmd_list_element *c,
4236 const char *value)
4237{
4238 fprintf_filtered (file, _("Use of exact watchpoints is %s.\n"), value);
4239}
4240
845d4708 4241/* Read a PPC instruction from memory. */
d78489bf
AT		 4242
4243static unsigned int
845d4708 4244read_insn (struct frame_info *frame, CORE_ADDR pc)
d78489bf 4245{
845d4708
AM		 4246 struct gdbarch *gdbarch = get_frame_arch (frame);
4247 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4248
4249 return read_memory_unsigned_integer (pc, 4, byte_order);
d78489bf
AT		 4250}
4251
4252/* Return non-zero if the instructions at PC match the series
4253 described in PATTERN, or zero otherwise. PATTERN is an array of
4254 'struct ppc_insn_pattern' objects, terminated by an entry whose
4255 mask is zero.
4256
4257 When the match is successful, fill INSN[i] with what PATTERN[i]
4258 matched. If PATTERN[i] is optional, and the instruction wasn't
4259 present, set INSN[i] to 0 (which is not a valid PPC instruction).
4260 INSN should have as many elements as PATTERN. Note that, if
4261 PATTERN contains optional instructions which aren't present in
4262 memory, then INSN will have holes, so INSN[i] isn't necessarily the
4263 i'th instruction in memory. */
4264
4265int
845d4708
AM		 4266ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc,
4267 struct ppc_insn_pattern *pattern,
4268 unsigned int *insns)
d78489bf
AT		 4269{
4270 int i;
845d4708 4271 unsigned int insn;
d78489bf 4272
845d4708 4273 for (i = 0, insn = 0; pattern[i].mask; i++)
d78489bf 4274 {
845d4708
AM		 4275 if (insn == 0)
4276 insn = read_insn (frame, pc);
4277 insns[i] = 0;
4278 if ((insn & pattern[i].mask) == pattern[i].data)
4279 {
4280 insns[i] = insn;
4281 pc += 4;
4282 insn = 0;
4283 }
4284 else if (!pattern[i].optional)
d78489bf
AT		 4285 return 0;
4286 }
4287
4288 return 1;
4289}
4290
4291/* Return the 'd' field of the d-form instruction INSN, properly
4292 sign-extended. */
4293
4294CORE_ADDR
4295ppc_insn_d_field (unsigned int insn)
4296{
4297 return ((((CORE_ADDR) insn & 0xffff) ^ 0x8000) - 0x8000);
4298}
4299
4300/* Return the 'ds' field of the ds-form instruction INSN, with the two
4301 zero bits concatenated at the right, and properly
4302 sign-extended. */
4303
4304CORE_ADDR
4305ppc_insn_ds_field (unsigned int insn)
4306{
4307 return ((((CORE_ADDR) insn & 0xfffc) ^ 0x8000) - 0x8000);
4308}
4309
c906108c
SS		 4310/* Initialization code. */
4311
0df8b418
MS		 4312/* -Wmissing-prototypes */
4313extern initialize_file_ftype _initialize_rs6000_tdep;
b9362cc7 4314
c906108c 4315void
fba45db2 4316_initialize_rs6000_tdep (void)
c906108c 4317{
7b112f9c
JT		 4318 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
4319 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
7cc46491
DJ		 4320
4321 /* Initialize the standard target descriptions. */
4322 initialize_tdesc_powerpc_32 ();
7284e1be 4323 initialize_tdesc_powerpc_altivec32 ();
604c2f83 4324 initialize_tdesc_powerpc_vsx32 ();
7cc46491
DJ		 4325 initialize_tdesc_powerpc_403 ();
4326 initialize_tdesc_powerpc_403gc ();
4d09ffea 4327 initialize_tdesc_powerpc_405 ();
7cc46491
DJ		 4328 initialize_tdesc_powerpc_505 ();
4329 initialize_tdesc_powerpc_601 ();
4330 initialize_tdesc_powerpc_602 ();
4331 initialize_tdesc_powerpc_603 ();
4332 initialize_tdesc_powerpc_604 ();
4333 initialize_tdesc_powerpc_64 ();
7284e1be 4334 initialize_tdesc_powerpc_altivec64 ();
604c2f83 4335 initialize_tdesc_powerpc_vsx64 ();
7cc46491
DJ		 4336 initialize_tdesc_powerpc_7400 ();
4337 initialize_tdesc_powerpc_750 ();
4338 initialize_tdesc_powerpc_860 ();
4339 initialize_tdesc_powerpc_e500 ();
4340 initialize_tdesc_rs6000 ();
55eddb0f
DJ		 4341
4342 /* Add root prefix command for all "set powerpc"/"show powerpc"
4343 commands. */
4344 add_prefix_cmd ("powerpc", no_class, set_powerpc_command,
4345 _("Various PowerPC-specific commands."),
4346 &setpowerpccmdlist, "set powerpc ", 0, &setlist);
4347
4348 add_prefix_cmd ("powerpc", no_class, show_powerpc_command,
4349 _("Various PowerPC-specific commands."),
4350 &showpowerpccmdlist, "show powerpc ", 0, &showlist);
4351
4352 /* Add a command to allow the user to force the ABI. */
4353 add_setshow_auto_boolean_cmd ("soft-float", class_support,
4354 &powerpc_soft_float_global,
4355 _("Set whether to use a soft-float ABI."),
4356 _("Show whether to use a soft-float ABI."),
4357 NULL,
4358 powerpc_set_soft_float, NULL,
4359 &setpowerpccmdlist, &showpowerpccmdlist);
4360
4361 add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings,
4362 &powerpc_vector_abi_string,
4363 _("Set the vector ABI."),
4364 _("Show the vector ABI."),
4365 NULL, powerpc_set_vector_abi, NULL,
4366 &setpowerpccmdlist, &showpowerpccmdlist);
e09342b5
TJB		 4367
4368 add_setshow_boolean_cmd ("exact-watchpoints", class_support,
4369 &target_exact_watchpoints,
4370 _("\
4371Set whether to use just one debug register for watchpoints on scalars."),
4372 _("\
4373Show whether to use just one debug register for watchpoints on scalars."),
4374 _("\
4375If true, GDB will use only one debug register when watching a variable of\n\
4376scalar type, thus assuming that the variable is accessed through the address\n\
4377of its first byte."),
4378 NULL, show_powerpc_exact_watchpoints,
4379 &setpowerpccmdlist, &showpowerpccmdlist);
c906108c 4380}
GDB Binutils - Deliverables
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