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Further fix the documentation in struct quick_symbol_functions
[deliverable/binutils-gdb.git] / gdb / rs6000-tdep.c
CommitLineData
c906108c 1/* Target-dependent code for GDB, the GNU debugger.
7aea86e6 2
6aba47ca 3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4c38e0a4 4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
7b6bb8da 5 2010, 2011 Free Software Foundation, Inc.
c906108c 6
c5aa993b 7 This file is part of GDB.
c906108c 8
c5aa993b
JM		 9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
c5aa993b 12 (at your option) any later version.
c906108c 13
c5aa993b
JM		 14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
c906108c 18
c5aa993b 19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c
SS		 21
22#include "defs.h"
23#include "frame.h"
24#include "inferior.h"
25#include "symtab.h"
26#include "target.h"
27#include "gdbcore.h"
28#include "gdbcmd.h"
c906108c 29#include "objfiles.h"
7a78ae4e 30#include "arch-utils.h"
4e052eda 31#include "regcache.h"
d195bc9f 32#include "regset.h"
d16aafd8 33#include "doublest.h"
fd0407d6 34#include "value.h"
1fcc0bb8 35#include "parser-defs.h"
4be87837 36#include "osabi.h"
7d9b040b 37#include "infcall.h"
9f643768
JB		 38#include "sim-regno.h"
39#include "gdb/sim-ppc.h"
6ced10dd 40#include "reggroups.h"
4fc771b8 41#include "dwarf2-frame.h"
7cc46491
DJ		 42#include "target-descriptions.h"
43#include "user-regs.h"
7a78ae4e 44
2fccf04a 45#include "libbfd.h" /* for bfd_default_set_arch_mach */
7a78ae4e 46#include "coff/internal.h" /* for libcoff.h */
2fccf04a 47#include "libcoff.h" /* for xcoff_data */
11ed25ac
KB		 48#include "coff/xcoff.h"
49#include "libxcoff.h"
7a78ae4e 50
9aa1e687 51#include "elf-bfd.h"
55eddb0f 52#include "elf/ppc.h"
7a78ae4e 53
6ded7999 54#include "solib-svr4.h"
9aa1e687 55#include "ppc-tdep.h"
7a78ae4e 56
338ef23d 57#include "gdb_assert.h"
a89aa300 58#include "dis-asm.h"
338ef23d 59
61a65099
KB		 60#include "trad-frame.h"
61#include "frame-unwind.h"
62#include "frame-base.h"
63
7cc46491 64#include "features/rs6000/powerpc-32.c"
7284e1be 65#include "features/rs6000/powerpc-altivec32.c"
604c2f83 66#include "features/rs6000/powerpc-vsx32.c"
7cc46491
DJ		 67#include "features/rs6000/powerpc-403.c"
68#include "features/rs6000/powerpc-403gc.c"
4d09ffea 69#include "features/rs6000/powerpc-405.c"
7cc46491
DJ		 70#include "features/rs6000/powerpc-505.c"
71#include "features/rs6000/powerpc-601.c"
72#include "features/rs6000/powerpc-602.c"
73#include "features/rs6000/powerpc-603.c"
74#include "features/rs6000/powerpc-604.c"
75#include "features/rs6000/powerpc-64.c"
7284e1be 76#include "features/rs6000/powerpc-altivec64.c"
604c2f83 77#include "features/rs6000/powerpc-vsx64.c"
7cc46491
DJ		 78#include "features/rs6000/powerpc-7400.c"
79#include "features/rs6000/powerpc-750.c"
80#include "features/rs6000/powerpc-860.c"
81#include "features/rs6000/powerpc-e500.c"
82#include "features/rs6000/rs6000.c"
83
5a9e69ba
TJB		 84/* Determine if regnum is an SPE pseudo-register. */
85#define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
86 && (regnum) >= (tdep)->ppc_ev0_regnum \
87 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
88
f949c649
TJB		 89/* Determine if regnum is a decimal float pseudo-register. */
90#define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_dl0_regnum \
92 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
93
604c2f83
LM		 94/* Determine if regnum is a POWER7 VSX register. */
95#define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_vsr0_regnum \
97 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
98
99/* Determine if regnum is a POWER7 Extended FP register. */
100#define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
101 && (regnum) >= (tdep)->ppc_efpr0_regnum \
d9492458 102 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
604c2f83 103
55eddb0f
DJ		 104/* The list of available "set powerpc ..." and "show powerpc ..."
105 commands. */
106static struct cmd_list_element *setpowerpccmdlist = NULL;
107static struct cmd_list_element *showpowerpccmdlist = NULL;
108
109static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO;
110
111/* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
112static const char *powerpc_vector_strings[] =
113{
114 "auto",
115 "generic",
116 "altivec",
117 "spe",
118 NULL
119};
120
121/* A variable that can be configured by the user. */
122static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO;
123static const char *powerpc_vector_abi_string = "auto";
124
0df8b418 125/* To be used by skip_prologue. */
7a78ae4e
ND		 126
127struct rs6000_framedata
128 {
129 int offset; /* total size of frame --- the distance
130 by which we decrement sp to allocate
131 the frame */
132 int saved_gpr; /* smallest # of saved gpr */
46a9b8ed 133 unsigned int gpr_mask; /* Each bit is an individual saved GPR. */
7a78ae4e 134 int saved_fpr; /* smallest # of saved fpr */
6be8bc0c 135 int saved_vr; /* smallest # of saved vr */
96ff0de4 136 int saved_ev; /* smallest # of saved ev */
7a78ae4e 137 int alloca_reg; /* alloca register number (frame ptr) */
0df8b418
MS		 138 char frameless; /* true if frameless functions. */
139 char nosavedpc; /* true if pc not saved. */
46a9b8ed 140 char used_bl; /* true if link register clobbered */
7a78ae4e
ND		 141 int gpr_offset; /* offset of saved gprs from prev sp */
142 int fpr_offset; /* offset of saved fprs from prev sp */
6be8bc0c 143 int vr_offset; /* offset of saved vrs from prev sp */
96ff0de4 144 int ev_offset; /* offset of saved evs from prev sp */
7a78ae4e 145 int lr_offset; /* offset of saved lr */
46a9b8ed 146 int lr_register; /* register of saved lr, if trustworthy */
7a78ae4e 147 int cr_offset; /* offset of saved cr */
6be8bc0c 148 int vrsave_offset; /* offset of saved vrsave register */
7a78ae4e
ND		 149 };
150
c906108c 151
604c2f83
LM		 152/* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
153int
154vsx_register_p (struct gdbarch *gdbarch, int regno)
155{
156 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
157 if (tdep->ppc_vsr0_regnum < 0)
158 return 0;
159 else
160 return (regno >= tdep->ppc_vsr0_upper_regnum && regno
161 <= tdep->ppc_vsr0_upper_regnum + 31);
162}
163
64b84175
KB		 164/* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
165int
be8626e0 166altivec_register_p (struct gdbarch *gdbarch, int regno)
64b84175 167{
be8626e0 168 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
64b84175
KB		 169 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
170 return 0;
171 else
172 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
173}
174
383f0f5b 175
867e2dc5
JB		 176/* Return true if REGNO is an SPE register, false otherwise. */
177int
be8626e0 178spe_register_p (struct gdbarch *gdbarch, int regno)
867e2dc5 179{
be8626e0 180 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
867e2dc5
JB		 181
182 /* Is it a reference to EV0 -- EV31, and do we have those? */
5a9e69ba 183 if (IS_SPE_PSEUDOREG (tdep, regno))
867e2dc5
JB		 184 return 1;
185
6ced10dd
JB		 186 /* Is it a reference to one of the raw upper GPR halves? */
187 if (tdep->ppc_ev0_upper_regnum >= 0
188 && tdep->ppc_ev0_upper_regnum <= regno
189 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
190 return 1;
191
867e2dc5
JB		 192 /* Is it a reference to the 64-bit accumulator, and do we have that? */
193 if (tdep->ppc_acc_regnum >= 0
194 && tdep->ppc_acc_regnum == regno)
195 return 1;
196
197 /* Is it a reference to the SPE floating-point status and control register,
198 and do we have that? */
199 if (tdep->ppc_spefscr_regnum >= 0
200 && tdep->ppc_spefscr_regnum == regno)
201 return 1;
202
203 return 0;
204}
205
206
383f0f5b
JB		 207/* Return non-zero if the architecture described by GDBARCH has
208 floating-point registers (f0 --- f31 and fpscr). */
0a613259
AC		 209int
210ppc_floating_point_unit_p (struct gdbarch *gdbarch)
211{
383f0f5b
JB		 212 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
213
214 return (tdep->ppc_fp0_regnum >= 0
215 && tdep->ppc_fpscr_regnum >= 0);
0a613259 216}
9f643768 217
604c2f83
LM		 218/* Return non-zero if the architecture described by GDBARCH has
219 VSX registers (vsr0 --- vsr63). */
63807e1d 220static int
604c2f83
LM		 221ppc_vsx_support_p (struct gdbarch *gdbarch)
222{
223 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
224
225 return tdep->ppc_vsr0_regnum >= 0;
226}
227
06caf7d2
CES		 228/* Return non-zero if the architecture described by GDBARCH has
229 Altivec registers (vr0 --- vr31, vrsave and vscr). */
230int
231ppc_altivec_support_p (struct gdbarch *gdbarch)
232{
233 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
234
235 return (tdep->ppc_vr0_regnum >= 0
236 && tdep->ppc_vrsave_regnum >= 0);
237}
09991fa0
JB		 238
239/* Check that TABLE[GDB_REGNO] is not already initialized, and then
240 set it to SIM_REGNO.
241
242 This is a helper function for init_sim_regno_table, constructing
243 the table mapping GDB register numbers to sim register numbers; we
244 initialize every element in that table to -1 before we start
245 filling it in. */
9f643768
JB		 246static void
247set_sim_regno (int *table, int gdb_regno, int sim_regno)
248{
249 /* Make sure we don't try to assign any given GDB register a sim
250 register number more than once. */
251 gdb_assert (table[gdb_regno] == -1);
252 table[gdb_regno] = sim_regno;
253}
254
09991fa0
JB		 255
256/* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
257 numbers to simulator register numbers, based on the values placed
258 in the ARCH->tdep->ppc_foo_regnum members. */
9f643768
JB		 259static void
260init_sim_regno_table (struct gdbarch *arch)
261{
262 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
7cc46491 263 int total_regs = gdbarch_num_regs (arch);
9f643768
JB		 264 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
265 int i;
7cc46491
DJ		 266 static const char *const segment_regs[] = {
267 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
268 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
269 };
9f643768
JB		 270
271 /* Presume that all registers not explicitly mentioned below are
272 unavailable from the sim. */
273 for (i = 0; i < total_regs; i++)
274 sim_regno[i] = -1;
275
276 /* General-purpose registers. */
277 for (i = 0; i < ppc_num_gprs; i++)
278 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
279
280 /* Floating-point registers. */
281 if (tdep->ppc_fp0_regnum >= 0)
282 for (i = 0; i < ppc_num_fprs; i++)
283 set_sim_regno (sim_regno,
284 tdep->ppc_fp0_regnum + i,
285 sim_ppc_f0_regnum + i);
286 if (tdep->ppc_fpscr_regnum >= 0)
287 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
288
289 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
290 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
291 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
292
293 /* Segment registers. */
7cc46491
DJ		 294 for (i = 0; i < ppc_num_srs; i++)
295 {
296 int gdb_regno;
297
298 gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1);
299 if (gdb_regno >= 0)
300 set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i);
301 }
9f643768
JB		 302
303 /* Altivec registers. */
304 if (tdep->ppc_vr0_regnum >= 0)
305 {
306 for (i = 0; i < ppc_num_vrs; i++)
307 set_sim_regno (sim_regno,
308 tdep->ppc_vr0_regnum + i,
309 sim_ppc_vr0_regnum + i);
310
311 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
312 we can treat this more like the other cases. */
313 set_sim_regno (sim_regno,
314 tdep->ppc_vr0_regnum + ppc_num_vrs,
315 sim_ppc_vscr_regnum);
316 }
317 /* vsave is a special-purpose register, so the code below handles it. */
318
319 /* SPE APU (E500) registers. */
6ced10dd
JB		 320 if (tdep->ppc_ev0_upper_regnum >= 0)
321 for (i = 0; i < ppc_num_gprs; i++)
322 set_sim_regno (sim_regno,
323 tdep->ppc_ev0_upper_regnum + i,
324 sim_ppc_rh0_regnum + i);
9f643768
JB		 325 if (tdep->ppc_acc_regnum >= 0)
326 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
327 /* spefscr is a special-purpose register, so the code below handles it. */
328
7cc46491 329#ifdef WITH_SIM
9f643768
JB		 330 /* Now handle all special-purpose registers. Verify that they
331 haven't mistakenly been assigned numbers by any of the above
7cc46491
DJ		 332 code. */
333 for (i = 0; i < sim_ppc_num_sprs; i++)
334 {
335 const char *spr_name = sim_spr_register_name (i);
336 int gdb_regno = -1;
337
338 if (spr_name != NULL)
339 gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1);
340
341 if (gdb_regno != -1)
342 set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i);
343 }
344#endif
9f643768
JB		 345
346 /* Drop the initialized array into place. */
347 tdep->sim_regno = sim_regno;
348}
349
09991fa0
JB		 350
351/* Given a GDB register number REG, return the corresponding SIM
352 register number. */
9f643768 353static int
e7faf938 354rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg)
9f643768 355{
e7faf938 356 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9f643768
JB		 357 int sim_regno;
358
7cc46491 359 if (tdep->sim_regno == NULL)
e7faf938 360 init_sim_regno_table (gdbarch);
7cc46491 361
f57d151a 362 gdb_assert (0 <= reg
e7faf938
MD		 363 && reg <= gdbarch_num_regs (gdbarch)
364 + gdbarch_num_pseudo_regs (gdbarch));
9f643768
JB		 365 sim_regno = tdep->sim_regno[reg];
366
367 if (sim_regno >= 0)
368 return sim_regno;
369 else
370 return LEGACY_SIM_REGNO_IGNORE;
371}
372
d195bc9f
MK		 373\f
374
375/* Register set support functions. */
376
f2db237a
AM		 377/* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
378 Write the register to REGCACHE. */
379
7284e1be 380void
d195bc9f 381ppc_supply_reg (struct regcache *regcache, int regnum,
f2db237a 382 const gdb_byte *regs, size_t offset, int regsize)
d195bc9f
MK		 383{
384 if (regnum != -1 && offset != -1)
f2db237a
AM		 385 {
386 if (regsize > 4)
387 {
388 struct gdbarch *gdbarch = get_regcache_arch (regcache);
389 int gdb_regsize = register_size (gdbarch, regnum);
390 if (gdb_regsize < regsize
391 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
392 offset += regsize - gdb_regsize;
393 }
394 regcache_raw_supply (regcache, regnum, regs + offset);
395 }
d195bc9f
MK		 396}
397
f2db237a
AM		 398/* Read register REGNUM from REGCACHE and store to REGS + OFFSET
399 in a field REGSIZE wide. Zero pad as necessary. */
400
7284e1be 401void
d195bc9f 402ppc_collect_reg (const struct regcache *regcache, int regnum,
f2db237a 403 gdb_byte *regs, size_t offset, int regsize)
d195bc9f
MK		 404{
405 if (regnum != -1 && offset != -1)
f2db237a
AM		 406 {
407 if (regsize > 4)
408 {
409 struct gdbarch *gdbarch = get_regcache_arch (regcache);
410 int gdb_regsize = register_size (gdbarch, regnum);
411 if (gdb_regsize < regsize)
412 {
413 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
414 {
415 memset (regs + offset, 0, regsize - gdb_regsize);
416 offset += regsize - gdb_regsize;
417 }
418 else
419 memset (regs + offset + regsize - gdb_regsize, 0,
420 regsize - gdb_regsize);
421 }
422 }
423 regcache_raw_collect (regcache, regnum, regs + offset);
424 }
d195bc9f
MK		 425}
426
f2db237a
AM		 427static int
428ppc_greg_offset (struct gdbarch *gdbarch,
429 struct gdbarch_tdep *tdep,
430 const struct ppc_reg_offsets *offsets,
431 int regnum,
432 int *regsize)
433{
434 *regsize = offsets->gpr_size;
435 if (regnum >= tdep->ppc_gp0_regnum
436 && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs)
437 return (offsets->r0_offset
438 + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size);
439
440 if (regnum == gdbarch_pc_regnum (gdbarch))
441 return offsets->pc_offset;
442
443 if (regnum == tdep->ppc_ps_regnum)
444 return offsets->ps_offset;
445
446 if (regnum == tdep->ppc_lr_regnum)
447 return offsets->lr_offset;
448
449 if (regnum == tdep->ppc_ctr_regnum)
450 return offsets->ctr_offset;
451
452 *regsize = offsets->xr_size;
453 if (regnum == tdep->ppc_cr_regnum)
454 return offsets->cr_offset;
455
456 if (regnum == tdep->ppc_xer_regnum)
457 return offsets->xer_offset;
458
459 if (regnum == tdep->ppc_mq_regnum)
460 return offsets->mq_offset;
461
462 return -1;
463}
464
465static int
466ppc_fpreg_offset (struct gdbarch_tdep *tdep,
467 const struct ppc_reg_offsets *offsets,
468 int regnum)
469{
470 if (regnum >= tdep->ppc_fp0_regnum
471 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs)
472 return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8;
473
474 if (regnum == tdep->ppc_fpscr_regnum)
475 return offsets->fpscr_offset;
476
477 return -1;
478}
479
06caf7d2
CES		 480static int
481ppc_vrreg_offset (struct gdbarch_tdep *tdep,
482 const struct ppc_reg_offsets *offsets,
483 int regnum)
484{
485 if (regnum >= tdep->ppc_vr0_regnum
486 && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs)
487 return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16;
488
489 if (regnum == tdep->ppc_vrsave_regnum - 1)
490 return offsets->vscr_offset;
491
492 if (regnum == tdep->ppc_vrsave_regnum)
493 return offsets->vrsave_offset;
494
495 return -1;
496}
497
d195bc9f
MK		 498/* Supply register REGNUM in the general-purpose register set REGSET
499 from the buffer specified by GREGS and LEN to register cache
500 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
501
502void
503ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
504 int regnum, const void *gregs, size_t len)
505{
506 struct gdbarch *gdbarch = get_regcache_arch (regcache);
507 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
508 const struct ppc_reg_offsets *offsets = regset->descr;
509 size_t offset;
f2db237a 510 int regsize;
d195bc9f 511
f2db237a 512 if (regnum == -1)
d195bc9f 513 {
f2db237a
AM		 514 int i;
515 int gpr_size = offsets->gpr_size;
516
517 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
518 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
519 i++, offset += gpr_size)
520 ppc_supply_reg (regcache, i, gregs, offset, gpr_size);
521
522 ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch),
523 gregs, offsets->pc_offset, gpr_size);
524 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
525 gregs, offsets->ps_offset, gpr_size);
526 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
527 gregs, offsets->lr_offset, gpr_size);
528 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
529 gregs, offsets->ctr_offset, gpr_size);
530 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
531 gregs, offsets->cr_offset, offsets->xr_size);
532 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
533 gregs, offsets->xer_offset, offsets->xr_size);
534 ppc_supply_reg (regcache, tdep->ppc_mq_regnum,
535 gregs, offsets->mq_offset, offsets->xr_size);
536 return;
d195bc9f
MK		 537 }
538
f2db237a
AM		 539 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
540 ppc_supply_reg (regcache, regnum, gregs, offset, regsize);
d195bc9f
MK		 541}
542
543/* Supply register REGNUM in the floating-point register set REGSET
544 from the buffer specified by FPREGS and LEN to register cache
545 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
546
547void
548ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
549 int regnum, const void *fpregs, size_t len)
550{
551 struct gdbarch *gdbarch = get_regcache_arch (regcache);
f2db237a
AM		 552 struct gdbarch_tdep *tdep;
553 const struct ppc_reg_offsets *offsets;
d195bc9f 554 size_t offset;
d195bc9f 555
f2db237a
AM		 556 if (!ppc_floating_point_unit_p (gdbarch))
557 return;
383f0f5b 558
f2db237a
AM		 559 tdep = gdbarch_tdep (gdbarch);
560 offsets = regset->descr;
561 if (regnum == -1)
d195bc9f 562 {
f2db237a
AM		 563 int i;
564
565 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
566 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
567 i++, offset += 8)
568 ppc_supply_reg (regcache, i, fpregs, offset, 8);
569
570 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
571 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
572 return;
d195bc9f
MK		 573 }
574
f2db237a
AM		 575 offset = ppc_fpreg_offset (tdep, offsets, regnum);
576 ppc_supply_reg (regcache, regnum, fpregs, offset,
577 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
d195bc9f
MK		 578}
579
604c2f83
LM		 580/* Supply register REGNUM in the VSX register set REGSET
581 from the buffer specified by VSXREGS and LEN to register cache
582 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
583
584void
585ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache,
586 int regnum, const void *vsxregs, size_t len)
587{
588 struct gdbarch *gdbarch = get_regcache_arch (regcache);
589 struct gdbarch_tdep *tdep;
590
591 if (!ppc_vsx_support_p (gdbarch))
592 return;
593
594 tdep = gdbarch_tdep (gdbarch);
595
596 if (regnum == -1)
597 {
598 int i;
599
600 for (i = tdep->ppc_vsr0_upper_regnum;
601 i < tdep->ppc_vsr0_upper_regnum + 32;
602 i++)
603 ppc_supply_reg (regcache, i, vsxregs, 0, 8);
604
605 return;
606 }
607 else
608 ppc_supply_reg (regcache, regnum, vsxregs, 0, 8);
609}
610
06caf7d2
CES		 611/* Supply register REGNUM in the Altivec register set REGSET
612 from the buffer specified by VRREGS and LEN to register cache
613 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
614
615void
616ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache,
617 int regnum, const void *vrregs, size_t len)
618{
619 struct gdbarch *gdbarch = get_regcache_arch (regcache);
620 struct gdbarch_tdep *tdep;
621 const struct ppc_reg_offsets *offsets;
622 size_t offset;
623
624 if (!ppc_altivec_support_p (gdbarch))
625 return;
626
627 tdep = gdbarch_tdep (gdbarch);
628 offsets = regset->descr;
629 if (regnum == -1)
630 {
631 int i;
632
633 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
634 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
635 i++, offset += 16)
636 ppc_supply_reg (regcache, i, vrregs, offset, 16);
637
638 ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
639 vrregs, offsets->vscr_offset, 4);
640
641 ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum,
642 vrregs, offsets->vrsave_offset, 4);
643 return;
644 }
645
646 offset = ppc_vrreg_offset (tdep, offsets, regnum);
647 if (regnum != tdep->ppc_vrsave_regnum
648 && regnum != tdep->ppc_vrsave_regnum - 1)
649 ppc_supply_reg (regcache, regnum, vrregs, offset, 16);
650 else
651 ppc_supply_reg (regcache, regnum,
652 vrregs, offset, 4);
653}
654
d195bc9f 655/* Collect register REGNUM in the general-purpose register set
f2db237a 656 REGSET from register cache REGCACHE into the buffer specified by
d195bc9f
MK		 657 GREGS and LEN. If REGNUM is -1, do this for all registers in
658 REGSET. */
659
660void
661ppc_collect_gregset (const struct regset *regset,
662 const struct regcache *regcache,
663 int regnum, void *gregs, size_t len)
664{
665 struct gdbarch *gdbarch = get_regcache_arch (regcache);
666 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
667 const struct ppc_reg_offsets *offsets = regset->descr;
668 size_t offset;
f2db237a 669 int regsize;
d195bc9f 670
f2db237a 671 if (regnum == -1)
d195bc9f 672 {
f2db237a
AM		 673 int i;
674 int gpr_size = offsets->gpr_size;
675
676 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
677 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
678 i++, offset += gpr_size)
679 ppc_collect_reg (regcache, i, gregs, offset, gpr_size);
680
681 ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch),
682 gregs, offsets->pc_offset, gpr_size);
683 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
684 gregs, offsets->ps_offset, gpr_size);
685 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
686 gregs, offsets->lr_offset, gpr_size);
687 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
688 gregs, offsets->ctr_offset, gpr_size);
689 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
690 gregs, offsets->cr_offset, offsets->xr_size);
691 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
692 gregs, offsets->xer_offset, offsets->xr_size);
693 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
694 gregs, offsets->mq_offset, offsets->xr_size);
695 return;
d195bc9f
MK		 696 }
697
f2db237a
AM		 698 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
699 ppc_collect_reg (regcache, regnum, gregs, offset, regsize);
d195bc9f
MK		 700}
701
702/* Collect register REGNUM in the floating-point register set
f2db237a 703 REGSET from register cache REGCACHE into the buffer specified by
d195bc9f
MK		 704 FPREGS and LEN. If REGNUM is -1, do this for all registers in
705 REGSET. */
706
707void
708ppc_collect_fpregset (const struct regset *regset,
709 const struct regcache *regcache,
710 int regnum, void *fpregs, size_t len)
711{
712 struct gdbarch *gdbarch = get_regcache_arch (regcache);
f2db237a
AM		 713 struct gdbarch_tdep *tdep;
714 const struct ppc_reg_offsets *offsets;
d195bc9f 715 size_t offset;
d195bc9f 716
f2db237a
AM		 717 if (!ppc_floating_point_unit_p (gdbarch))
718 return;
383f0f5b 719
f2db237a
AM		 720 tdep = gdbarch_tdep (gdbarch);
721 offsets = regset->descr;
722 if (regnum == -1)
d195bc9f 723 {
f2db237a
AM		 724 int i;
725
726 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
727 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
728 i++, offset += 8)
729 ppc_collect_reg (regcache, i, fpregs, offset, 8);
730
731 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
732 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
733 return;
d195bc9f
MK		 734 }
735
f2db237a
AM		 736 offset = ppc_fpreg_offset (tdep, offsets, regnum);
737 ppc_collect_reg (regcache, regnum, fpregs, offset,
738 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
d195bc9f 739}
06caf7d2 740
604c2f83
LM		 741/* Collect register REGNUM in the VSX register set
742 REGSET from register cache REGCACHE into the buffer specified by
743 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
744 REGSET. */
745
746void
747ppc_collect_vsxregset (const struct regset *regset,
748 const struct regcache *regcache,
749 int regnum, void *vsxregs, size_t len)
750{
751 struct gdbarch *gdbarch = get_regcache_arch (regcache);
752 struct gdbarch_tdep *tdep;
753
754 if (!ppc_vsx_support_p (gdbarch))
755 return;
756
757 tdep = gdbarch_tdep (gdbarch);
758
759 if (regnum == -1)
760 {
761 int i;
762
763 for (i = tdep->ppc_vsr0_upper_regnum;
764 i < tdep->ppc_vsr0_upper_regnum + 32;
765 i++)
766 ppc_collect_reg (regcache, i, vsxregs, 0, 8);
767
768 return;
769 }
770 else
771 ppc_collect_reg (regcache, regnum, vsxregs, 0, 8);
772}
773
774
06caf7d2
CES		 775/* Collect register REGNUM in the Altivec register set
776 REGSET from register cache REGCACHE into the buffer specified by
777 VRREGS and LEN. If REGNUM is -1, do this for all registers in
778 REGSET. */
779
780void
781ppc_collect_vrregset (const struct regset *regset,
782 const struct regcache *regcache,
783 int regnum, void *vrregs, size_t len)
784{
785 struct gdbarch *gdbarch = get_regcache_arch (regcache);
786 struct gdbarch_tdep *tdep;
787 const struct ppc_reg_offsets *offsets;
788 size_t offset;
789
790 if (!ppc_altivec_support_p (gdbarch))
791 return;
792
793 tdep = gdbarch_tdep (gdbarch);
794 offsets = regset->descr;
795 if (regnum == -1)
796 {
797 int i;
798
799 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
800 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
801 i++, offset += 16)
802 ppc_collect_reg (regcache, i, vrregs, offset, 16);
803
804 ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
805 vrregs, offsets->vscr_offset, 4);
806
807 ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum,
808 vrregs, offsets->vrsave_offset, 4);
809 return;
810 }
811
812 offset = ppc_vrreg_offset (tdep, offsets, regnum);
813 if (regnum != tdep->ppc_vrsave_regnum
814 && regnum != tdep->ppc_vrsave_regnum - 1)
815 ppc_collect_reg (regcache, regnum, vrregs, offset, 16);
816 else
817 ppc_collect_reg (regcache, regnum,
818 vrregs, offset, 4);
819}
d195bc9f 820\f
0a613259 821
0d1243d9
PG		 822static int
823insn_changes_sp_or_jumps (unsigned long insn)
824{
825 int opcode = (insn >> 26) & 0x03f;
826 int sd = (insn >> 21) & 0x01f;
827 int a = (insn >> 16) & 0x01f;
828 int subcode = (insn >> 1) & 0x3ff;
829
830 /* Changes the stack pointer. */
831
832 /* NOTE: There are many ways to change the value of a given register.
833 The ways below are those used when the register is R1, the SP,
834 in a funtion's epilogue. */
835
836 if (opcode == 31 && subcode == 444 && a == 1)
837 return 1; /* mr R1,Rn */
838 if (opcode == 14 && sd == 1)
839 return 1; /* addi R1,Rn,simm */
840 if (opcode == 58 && sd == 1)
841 return 1; /* ld R1,ds(Rn) */
842
843 /* Transfers control. */
844
845 if (opcode == 18)
846 return 1; /* b */
847 if (opcode == 16)
848 return 1; /* bc */
849 if (opcode == 19 && subcode == 16)
850 return 1; /* bclr */
851 if (opcode == 19 && subcode == 528)
852 return 1; /* bcctr */
853
854 return 0;
855}
856
857/* Return true if we are in the function's epilogue, i.e. after the
858 instruction that destroyed the function's stack frame.
859
860 1) scan forward from the point of execution:
861 a) If you find an instruction that modifies the stack pointer
862 or transfers control (except a return), execution is not in
863 an epilogue, return.
864 b) Stop scanning if you find a return instruction or reach the
865 end of the function or reach the hard limit for the size of
866 an epilogue.
867 2) scan backward from the point of execution:
868 a) If you find an instruction that modifies the stack pointer,
869 execution *is* in an epilogue, return.
870 b) Stop scanning if you reach an instruction that transfers
871 control or the beginning of the function or reach the hard
872 limit for the size of an epilogue. */
873
874static int
875rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
876{
46a9b8ed 877 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 878 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
0d1243d9
PG		 879 bfd_byte insn_buf[PPC_INSN_SIZE];
880 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
881 unsigned long insn;
882 struct frame_info *curfrm;
883
884 /* Find the search limits based on function boundaries and hard limit. */
885
886 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
887 return 0;
888
889 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
890 if (epilogue_start < func_start) epilogue_start = func_start;
891
892 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
893 if (epilogue_end > func_end) epilogue_end = func_end;
894
895 curfrm = get_current_frame ();
896
897 /* Scan forward until next 'blr'. */
898
899 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
900 {
901 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
902 return 0;
e17a4113 903 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
0d1243d9
PG		 904 if (insn == 0x4e800020)
905 break;
46a9b8ed
DJ		 906 /* Assume a bctr is a tail call unless it points strictly within
907 this function. */
908 if (insn == 0x4e800420)
909 {
910 CORE_ADDR ctr = get_frame_register_unsigned (curfrm,
911 tdep->ppc_ctr_regnum);
912 if (ctr > func_start && ctr < func_end)
913 return 0;
914 else
915 break;
916 }
0d1243d9
PG		 917 if (insn_changes_sp_or_jumps (insn))
918 return 0;
919 }
920
921 /* Scan backward until adjustment to stack pointer (R1). */
922
923 for (scan_pc = pc - PPC_INSN_SIZE;
924 scan_pc >= epilogue_start;
925 scan_pc -= PPC_INSN_SIZE)
926 {
927 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
928 return 0;
e17a4113 929 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
0d1243d9
PG		 930 if (insn_changes_sp_or_jumps (insn))
931 return 1;
932 }
933
934 return 0;
935}
936
143985b7 937/* Get the ith function argument for the current function. */
b9362cc7 938static CORE_ADDR
143985b7
AF		 939rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
940 struct type *type)
941{
50fd1280 942 return get_frame_register_unsigned (frame, 3 + argi);
143985b7
AF		 943}
944
c906108c
SS		 945/* Sequence of bytes for breakpoint instruction. */
946
f4f9705a 947const static unsigned char *
67d57894
MD		 948rs6000_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
949 int *bp_size)
c906108c 950{
aaab4dba
AC		 951 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
952 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
c906108c 953 *bp_size = 4;
67d57894 954 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
c906108c
SS		 955 return big_breakpoint;
956 else
957 return little_breakpoint;
958}
959
f74c6cad
LM		 960/* Instruction masks for displaced stepping. */
961#define BRANCH_MASK 0xfc000000
962#define BP_MASK 0xFC0007FE
963#define B_INSN 0x48000000
964#define BC_INSN 0x40000000
965#define BXL_INSN 0x4c000000
966#define BP_INSN 0x7C000008
967
968/* Fix up the state of registers and memory after having single-stepped
969 a displaced instruction. */
63807e1d 970static void
f74c6cad 971ppc_displaced_step_fixup (struct gdbarch *gdbarch,
63807e1d
PA		 972 struct displaced_step_closure *closure,
973 CORE_ADDR from, CORE_ADDR to,
974 struct regcache *regs)
f74c6cad 975{
e17a4113 976 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
f74c6cad
LM		 977 /* Since we use simple_displaced_step_copy_insn, our closure is a
978 copy of the instruction. */
979 ULONGEST insn = extract_unsigned_integer ((gdb_byte *) closure,
e17a4113 980 PPC_INSN_SIZE, byte_order);
f74c6cad
LM		 981 ULONGEST opcode = 0;
982 /* Offset for non PC-relative instructions. */
983 LONGEST offset = PPC_INSN_SIZE;
984
985 opcode = insn & BRANCH_MASK;
986
987 if (debug_displaced)
988 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 989 "displaced: (ppc) fixup (%s, %s)\n",
990 paddress (gdbarch, from), paddress (gdbarch, to));
f74c6cad
LM		 991
992
993 /* Handle PC-relative branch instructions. */
994 if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN)
995 {
a4fafde3 996 ULONGEST current_pc;
f74c6cad
LM		 997
998 /* Read the current PC value after the instruction has been executed
999 in a displaced location. Calculate the offset to be applied to the
1000 original PC value before the displaced stepping. */
1001 regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1002 &current_pc);
1003 offset = current_pc - to;
1004
1005 if (opcode != BXL_INSN)
1006 {
1007 /* Check for AA bit indicating whether this is an absolute
1008 addressing or PC-relative (1: absolute, 0: relative). */
1009 if (!(insn & 0x2))
1010 {
1011 /* PC-relative addressing is being used in the branch. */
1012 if (debug_displaced)
1013 fprintf_unfiltered
1014 (gdb_stdlog,
5af949e3
UW		 1015 "displaced: (ppc) branch instruction: %s\n"
1016 "displaced: (ppc) adjusted PC from %s to %s\n",
1017 paddress (gdbarch, insn), paddress (gdbarch, current_pc),
1018 paddress (gdbarch, from + offset));
f74c6cad 1019
0df8b418
MS		 1020 regcache_cooked_write_unsigned (regs,
1021 gdbarch_pc_regnum (gdbarch),
f74c6cad
LM		 1022 from + offset);
1023 }
1024 }
1025 else
1026 {
1027 /* If we're here, it means we have a branch to LR or CTR. If the
1028 branch was taken, the offset is probably greater than 4 (the next
1029 instruction), so it's safe to assume that an offset of 4 means we
1030 did not take the branch. */
1031 if (offset == PPC_INSN_SIZE)
1032 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1033 from + PPC_INSN_SIZE);
1034 }
1035
1036 /* Check for LK bit indicating whether we should set the link
1037 register to point to the next instruction
1038 (1: Set, 0: Don't set). */
1039 if (insn & 0x1)
1040 {
1041 /* Link register needs to be set to the next instruction's PC. */
1042 regcache_cooked_write_unsigned (regs,
1043 gdbarch_tdep (gdbarch)->ppc_lr_regnum,
1044 from + PPC_INSN_SIZE);
1045 if (debug_displaced)
1046 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 1047 "displaced: (ppc) adjusted LR to %s\n",
1048 paddress (gdbarch, from + PPC_INSN_SIZE));
f74c6cad
LM		 1049
1050 }
1051 }
1052 /* Check for breakpoints in the inferior. If we've found one, place the PC
1053 right at the breakpoint instruction. */
1054 else if ((insn & BP_MASK) == BP_INSN)
1055 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from);
1056 else
1057 /* Handle any other instructions that do not fit in the categories above. */
1058 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1059 from + offset);
1060}
c906108c 1061
99e40580
UW		 1062/* Always use hardware single-stepping to execute the
1063 displaced instruction. */
1064static int
1065ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
1066 struct displaced_step_closure *closure)
1067{
1068 return 1;
1069}
1070
ce5eab59
UW		 1071/* Instruction masks used during single-stepping of atomic sequences. */
1072#define LWARX_MASK 0xfc0007fe
1073#define LWARX_INSTRUCTION 0x7c000028
1074#define LDARX_INSTRUCTION 0x7c0000A8
1075#define STWCX_MASK 0xfc0007ff
1076#define STWCX_INSTRUCTION 0x7c00012d
1077#define STDCX_INSTRUCTION 0x7c0001ad
ce5eab59
UW		 1078
1079/* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1080 instruction and ending with a STWCX/STDCX instruction. If such a sequence
1081 is found, attempt to step through it. A breakpoint is placed at the end of
1082 the sequence. */
1083
4a7622d1
UW		 1084int
1085ppc_deal_with_atomic_sequence (struct frame_info *frame)
ce5eab59 1086{
a6d9a66e 1087 struct gdbarch *gdbarch = get_frame_arch (frame);
6c95b8df 1088 struct address_space *aspace = get_frame_address_space (frame);
e17a4113 1089 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
0b1b3e42 1090 CORE_ADDR pc = get_frame_pc (frame);
ce5eab59
UW		 1091 CORE_ADDR breaks[2] = {-1, -1};
1092 CORE_ADDR loc = pc;
24d45690 1093 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
e17a4113 1094 int insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
ce5eab59
UW		 1095 int insn_count;
1096 int index;
1097 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
1098 const int atomic_sequence_length = 16; /* Instruction sequence length. */
24d45690 1099 int opcode; /* Branch instruction's OPcode. */
ce5eab59
UW		 1100 int bc_insn_count = 0; /* Conditional branch instruction count. */
1101
1102 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1103 if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
1104 && (insn & LWARX_MASK) != LDARX_INSTRUCTION)
1105 return 0;
1106
1107 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1108 instructions. */
1109 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
1110 {
1111 loc += PPC_INSN_SIZE;
e17a4113 1112 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
ce5eab59
UW		 1113
1114 /* Assume that there is at most one conditional branch in the atomic
1115 sequence. If a conditional branch is found, put a breakpoint in
1116 its destination address. */
f74c6cad 1117 if ((insn & BRANCH_MASK) == BC_INSN)
ce5eab59 1118 {
a3769e0c
AM		 1119 int immediate = ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1120 int absolute = insn & 2;
4a7622d1 1121
ce5eab59
UW		 1122 if (bc_insn_count >= 1)
1123 return 0; /* More than one conditional branch found, fallback
1124 to the standard single-step code. */
4a7622d1
UW		 1125
1126 if (absolute)
1127 breaks[1] = immediate;
1128 else
a3769e0c 1129 breaks[1] = loc + immediate;
4a7622d1
UW		 1130
1131 bc_insn_count++;
1132 last_breakpoint++;
ce5eab59
UW		 1133 }
1134
1135 if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
1136 || (insn & STWCX_MASK) == STDCX_INSTRUCTION)
1137 break;
1138 }
1139
1140 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1141 if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
1142 && (insn & STWCX_MASK) != STDCX_INSTRUCTION)
1143 return 0;
1144
24d45690 1145 closing_insn = loc;
ce5eab59 1146 loc += PPC_INSN_SIZE;
e17a4113 1147 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
ce5eab59
UW		 1148
1149 /* Insert a breakpoint right after the end of the atomic sequence. */
1150 breaks[0] = loc;
1151
24d45690 1152 /* Check for duplicated breakpoints. Check also for a breakpoint
a3769e0c
AM		 1153 placed (branch instruction's destination) anywhere in sequence. */
1154 if (last_breakpoint
1155 && (breaks[1] == breaks[0]
1156 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
ce5eab59
UW		 1157 last_breakpoint = 0;
1158
1159 /* Effectively inserts the breakpoints. */
1160 for (index = 0; index <= last_breakpoint; index++)
6c95b8df 1161 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
ce5eab59
UW		 1162
1163 return 1;
1164}
1165
c906108c 1166
c906108c
SS		 1167#define SIGNED_SHORT(x) \
1168 ((sizeof (short) == 2) \
1169 ? ((int)(short)(x)) \
1170 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1171
1172#define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1173
55d05f3b
KB		 1174/* Limit the number of skipped non-prologue instructions, as the examining
1175 of the prologue is expensive. */
1176static int max_skip_non_prologue_insns = 10;
1177
773df3e5
JB		 1178/* Return nonzero if the given instruction OP can be part of the prologue
1179 of a function and saves a parameter on the stack. FRAMEP should be
1180 set if one of the previous instructions in the function has set the
1181 Frame Pointer. */
1182
1183static int
1184store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
1185{
1186 /* Move parameters from argument registers to temporary register. */
1187 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1188 {
1189 /* Rx must be scratch register r0. */
1190 const int rx_regno = (op >> 16) & 31;
1191 /* Ry: Only r3 - r10 are used for parameter passing. */
1192 const int ry_regno = GET_SRC_REG (op);
1193
1194 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
1195 {
1196 *r0_contains_arg = 1;
1197 return 1;
1198 }
1199 else
1200 return 0;
1201 }
1202
1203 /* Save a General Purpose Register on stack. */
1204
1205 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1206 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1207 {
1208 /* Rx: Only r3 - r10 are used for parameter passing. */
1209 const int rx_regno = GET_SRC_REG (op);
1210
1211 return (rx_regno >= 3 && rx_regno <= 10);
1212 }
1213
1214 /* Save a General Purpose Register on stack via the Frame Pointer. */
1215
1216 if (framep &&
1217 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1218 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1219 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1220 {
1221 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1222 However, the compiler sometimes uses r0 to hold an argument. */
1223 const int rx_regno = GET_SRC_REG (op);
1224
1225 return ((rx_regno >= 3 && rx_regno <= 10)
1226 || (rx_regno == 0 && *r0_contains_arg));
1227 }
1228
1229 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1230 {
1231 /* Only f2 - f8 are used for parameter passing. */
1232 const int src_regno = GET_SRC_REG (op);
1233
1234 return (src_regno >= 2 && src_regno <= 8);
1235 }
1236
1237 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1238 {
1239 /* Only f2 - f8 are used for parameter passing. */
1240 const int src_regno = GET_SRC_REG (op);
1241
1242 return (src_regno >= 2 && src_regno <= 8);
1243 }
1244
1245 /* Not an insn that saves a parameter on stack. */
1246 return 0;
1247}
55d05f3b 1248
3c77c82a
DJ		 1249/* Assuming that INSN is a "bl" instruction located at PC, return
1250 nonzero if the destination of the branch is a "blrl" instruction.
1251
1252 This sequence is sometimes found in certain function prologues.
1253 It allows the function to load the LR register with a value that
1254 they can use to access PIC data using PC-relative offsets. */
1255
1256static int
e17a4113 1257bl_to_blrl_insn_p (CORE_ADDR pc, int insn, enum bfd_endian byte_order)
3c77c82a 1258{
0b1b3e42
UW		 1259 CORE_ADDR dest;
1260 int immediate;
1261 int absolute;
3c77c82a
DJ		 1262 int dest_insn;
1263
0b1b3e42
UW		 1264 absolute = (int) ((insn >> 1) & 1);
1265 immediate = ((insn & ~3) << 6) >> 6;
1266 if (absolute)
1267 dest = immediate;
1268 else
1269 dest = pc + immediate;
1270
e17a4113 1271 dest_insn = read_memory_integer (dest, 4, byte_order);
3c77c82a
DJ		 1272 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
1273 return 1;
1274
1275 return 0;
1276}
1277
0df8b418 1278/* Masks for decoding a branch-and-link (bl) instruction.
8ab3d180
KB		 1279
1280 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1281 The former is anded with the opcode in question; if the result of
1282 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1283 question is a ``bl'' instruction.
1284
1285 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1286 the branch displacement. */
1287
1288#define BL_MASK 0xfc000001
1289#define BL_INSTRUCTION 0x48000001
1290#define BL_DISPLACEMENT_MASK 0x03fffffc
1291
de9f48f0 1292static unsigned long
e17a4113 1293rs6000_fetch_instruction (struct gdbarch *gdbarch, const CORE_ADDR pc)
de9f48f0 1294{
e17a4113 1295 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
de9f48f0
JG		 1296 gdb_byte buf[4];
1297 unsigned long op;
1298
1299 /* Fetch the instruction and convert it to an integer. */
1300 if (target_read_memory (pc, buf, 4))
1301 return 0;
e17a4113 1302 op = extract_unsigned_integer (buf, 4, byte_order);
de9f48f0
JG		 1303
1304 return op;
1305}
1306
1307/* GCC generates several well-known sequences of instructions at the begining
1308 of each function prologue when compiling with -fstack-check. If one of
1309 such sequences starts at START_PC, then return the address of the
1310 instruction immediately past this sequence. Otherwise, return START_PC. */
1311
1312static CORE_ADDR
e17a4113 1313rs6000_skip_stack_check (struct gdbarch *gdbarch, const CORE_ADDR start_pc)
de9f48f0
JG		 1314{
1315 CORE_ADDR pc = start_pc;
e17a4113 1316 unsigned long op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1317
1318 /* First possible sequence: A small number of probes.
1319 stw 0, -<some immediate>(1)
0df8b418 1320 [repeat this instruction any (small) number of times]. */
de9f48f0
JG		 1321
1322 if ((op & 0xffff0000) == 0x90010000)
1323 {
1324 while ((op & 0xffff0000) == 0x90010000)
1325 {
1326 pc = pc + 4;
e17a4113 1327 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1328 }
1329 return pc;
1330 }
1331
1332 /* Second sequence: A probing loop.
1333 addi 12,1,-<some immediate>
1334 lis 0,-<some immediate>
1335 [possibly ori 0,0,<some immediate>]
1336 add 0,12,0
1337 cmpw 0,12,0
1338 beq 0,<disp>
1339 addi 12,12,-<some immediate>
1340 stw 0,0(12)
1341 b <disp>
0df8b418 1342 [possibly one last probe: stw 0,<some immediate>(12)]. */
de9f48f0
JG		 1343
1344 while (1)
1345 {
1346 /* addi 12,1,-<some immediate> */
1347 if ((op & 0xffff0000) != 0x39810000)
1348 break;
1349
1350 /* lis 0,-<some immediate> */
1351 pc = pc + 4;
e17a4113 1352 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1353 if ((op & 0xffff0000) != 0x3c000000)
1354 break;
1355
1356 pc = pc + 4;
e17a4113 1357 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1358 /* [possibly ori 0,0,<some immediate>] */
1359 if ((op & 0xffff0000) == 0x60000000)
1360 {
1361 pc = pc + 4;
e17a4113 1362 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1363 }
1364 /* add 0,12,0 */
1365 if (op != 0x7c0c0214)
1366 break;
1367
1368 /* cmpw 0,12,0 */
1369 pc = pc + 4;
e17a4113 1370 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1371 if (op != 0x7c0c0000)
1372 break;
1373
1374 /* beq 0,<disp> */
1375 pc = pc + 4;
e17a4113 1376 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1377 if ((op & 0xff9f0001) != 0x41820000)
1378 break;
1379
1380 /* addi 12,12,-<some immediate> */
1381 pc = pc + 4;
e17a4113 1382 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1383 if ((op & 0xffff0000) != 0x398c0000)
1384 break;
1385
1386 /* stw 0,0(12) */
1387 pc = pc + 4;
e17a4113 1388 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1389 if (op != 0x900c0000)
1390 break;
1391
1392 /* b <disp> */
1393 pc = pc + 4;
e17a4113 1394 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1395 if ((op & 0xfc000001) != 0x48000000)
1396 break;
1397
0df8b418 1398 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
de9f48f0 1399 pc = pc + 4;
e17a4113 1400 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1401 if ((op & 0xffff0000) == 0x900c0000)
1402 {
1403 pc = pc + 4;
e17a4113 1404 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1405 }
1406
1407 /* We found a valid stack-check sequence, return the new PC. */
1408 return pc;
1409 }
1410
1411 /* Third sequence: No probe; instead, a comparizon between the stack size
1412 limit (saved in a run-time global variable) and the current stack
1413 pointer:
1414
1415 addi 0,1,-<some immediate>
1416 lis 12,__gnat_stack_limit@ha
1417 lwz 12,__gnat_stack_limit@l(12)
1418 twllt 0,12
1419
1420 or, with a small variant in the case of a bigger stack frame:
1421 addis 0,1,<some immediate>
1422 addic 0,0,-<some immediate>
1423 lis 12,__gnat_stack_limit@ha
1424 lwz 12,__gnat_stack_limit@l(12)
1425 twllt 0,12
1426 */
1427 while (1)
1428 {
1429 /* addi 0,1,-<some immediate> */
1430 if ((op & 0xffff0000) != 0x38010000)
1431 {
1432 /* small stack frame variant not recognized; try the
1433 big stack frame variant: */
1434
1435 /* addis 0,1,<some immediate> */
1436 if ((op & 0xffff0000) != 0x3c010000)
1437 break;
1438
1439 /* addic 0,0,-<some immediate> */
1440 pc = pc + 4;
e17a4113 1441 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1442 if ((op & 0xffff0000) != 0x30000000)
1443 break;
1444 }
1445
1446 /* lis 12,<some immediate> */
1447 pc = pc + 4;
e17a4113 1448 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1449 if ((op & 0xffff0000) != 0x3d800000)
1450 break;
1451
1452 /* lwz 12,<some immediate>(12) */
1453 pc = pc + 4;
e17a4113 1454 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1455 if ((op & 0xffff0000) != 0x818c0000)
1456 break;
1457
1458 /* twllt 0,12 */
1459 pc = pc + 4;
e17a4113 1460 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1461 if ((op & 0xfffffffe) != 0x7c406008)
1462 break;
1463
1464 /* We found a valid stack-check sequence, return the new PC. */
1465 return pc;
1466 }
1467
1468 /* No stack check code in our prologue, return the start_pc. */
1469 return start_pc;
1470}
1471
6a16c029
TJB		 1472/* return pc value after skipping a function prologue and also return
1473 information about a function frame.
1474
1475 in struct rs6000_framedata fdata:
1476 - frameless is TRUE, if function does not have a frame.
1477 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1478 - offset is the initial size of this stack frame --- the amount by
1479 which we decrement the sp to allocate the frame.
1480 - saved_gpr is the number of the first saved gpr.
1481 - saved_fpr is the number of the first saved fpr.
1482 - saved_vr is the number of the first saved vr.
1483 - saved_ev is the number of the first saved ev.
1484 - alloca_reg is the number of the register used for alloca() handling.
1485 Otherwise -1.
1486 - gpr_offset is the offset of the first saved gpr from the previous frame.
1487 - fpr_offset is the offset of the first saved fpr from the previous frame.
1488 - vr_offset is the offset of the first saved vr from the previous frame.
1489 - ev_offset is the offset of the first saved ev from the previous frame.
1490 - lr_offset is the offset of the saved lr
1491 - cr_offset is the offset of the saved cr
0df8b418 1492 - vrsave_offset is the offset of the saved vrsave register. */
6a16c029 1493
7a78ae4e 1494static CORE_ADDR
be8626e0
MD		 1495skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc,
1496 struct rs6000_framedata *fdata)
c906108c
SS		 1497{
1498 CORE_ADDR orig_pc = pc;
55d05f3b 1499 CORE_ADDR last_prologue_pc = pc;
6be8bc0c 1500 CORE_ADDR li_found_pc = 0;
50fd1280 1501 gdb_byte buf[4];
c906108c
SS		 1502 unsigned long op;
1503 long offset = 0;
6be8bc0c 1504 long vr_saved_offset = 0;
482ca3f5
KB		 1505 int lr_reg = -1;
1506 int cr_reg = -1;
6be8bc0c 1507 int vr_reg = -1;
96ff0de4
EZ		 1508 int ev_reg = -1;
1509 long ev_offset = 0;
6be8bc0c 1510 int vrsave_reg = -1;
c906108c
SS		 1511 int reg;
1512 int framep = 0;
1513 int minimal_toc_loaded = 0;
ddb20c56 1514 int prev_insn_was_prologue_insn = 1;
55d05f3b 1515 int num_skip_non_prologue_insns = 0;
773df3e5 1516 int r0_contains_arg = 0;
be8626e0
MD		 1517 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch);
1518 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 1519 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
c906108c 1520
ddb20c56 1521 memset (fdata, 0, sizeof (struct rs6000_framedata));
c906108c
SS		 1522 fdata->saved_gpr = -1;
1523 fdata->saved_fpr = -1;
6be8bc0c 1524 fdata->saved_vr = -1;
96ff0de4 1525 fdata->saved_ev = -1;
c906108c
SS		 1526 fdata->alloca_reg = -1;
1527 fdata->frameless = 1;
1528 fdata->nosavedpc = 1;
46a9b8ed 1529 fdata->lr_register = -1;
c906108c 1530
e17a4113 1531 pc = rs6000_skip_stack_check (gdbarch, pc);
de9f48f0
JG		 1532 if (pc >= lim_pc)
1533 pc = lim_pc;
1534
55d05f3b 1535 for (;; pc += 4)
c906108c 1536 {
ddb20c56
KB		 1537 /* Sometimes it isn't clear if an instruction is a prologue
1538 instruction or not. When we encounter one of these ambiguous
1539 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
0df8b418 1540 Otherwise, we'll assume that it really is a prologue instruction. */
ddb20c56
KB		 1541 if (prev_insn_was_prologue_insn)
1542 last_prologue_pc = pc;
55d05f3b
KB		 1543
1544 /* Stop scanning if we've hit the limit. */
4e463ff5 1545 if (pc >= lim_pc)
55d05f3b
KB		 1546 break;
1547
ddb20c56
KB		 1548 prev_insn_was_prologue_insn = 1;
1549
55d05f3b 1550 /* Fetch the instruction and convert it to an integer. */
ddb20c56
KB		 1551 if (target_read_memory (pc, buf, 4))
1552 break;
e17a4113 1553 op = extract_unsigned_integer (buf, 4, byte_order);
c906108c 1554
c5aa993b
JM		 1555 if ((op & 0xfc1fffff) == 0x7c0802a6)
1556 { /* mflr Rx */
43b1ab88
AC		 1557 /* Since shared library / PIC code, which needs to get its
1558 address at runtime, can appear to save more than one link
1559 register vis:
1560
1561 *INDENT-OFF*
1562 stwu r1,-304(r1)
1563 mflr r3
1564 bl 0xff570d0 (blrl)
1565 stw r30,296(r1)
1566 mflr r30
1567 stw r31,300(r1)
1568 stw r3,308(r1);
1569 ...
1570 *INDENT-ON*
1571
1572 remember just the first one, but skip over additional
1573 ones. */
721d14ba 1574 if (lr_reg == -1)
46a9b8ed 1575 lr_reg = (op & 0x03e00000) >> 21;
773df3e5
JB		 1576 if (lr_reg == 0)
1577 r0_contains_arg = 0;
c5aa993b 1578 continue;
c5aa993b
JM		 1579 }
1580 else if ((op & 0xfc1fffff) == 0x7c000026)
1581 { /* mfcr Rx */
98f08d3d 1582 cr_reg = (op & 0x03e00000);
773df3e5
JB		 1583 if (cr_reg == 0)
1584 r0_contains_arg = 0;
c5aa993b 1585 continue;
c906108c 1586
c906108c 1587 }
c5aa993b
JM		 1588 else if ((op & 0xfc1f0000) == 0xd8010000)
1589 { /* stfd Rx,NUM(r1) */
1590 reg = GET_SRC_REG (op);
1591 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1592 {
1593 fdata->saved_fpr = reg;
1594 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1595 }
1596 continue;
c906108c 1597
c5aa993b
JM		 1598 }
1599 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
7a78ae4e
ND		 1600 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1601 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1602 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
c5aa993b
JM		 1603 {
1604
1605 reg = GET_SRC_REG (op);
46a9b8ed
DJ		 1606 if ((op & 0xfc1f0000) == 0xbc010000)
1607 fdata->gpr_mask |= ~((1U << reg) - 1);
1608 else
1609 fdata->gpr_mask |= 1U << reg;
c5aa993b
JM		 1610 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1611 {
1612 fdata->saved_gpr = reg;
7a78ae4e 1613 if ((op & 0xfc1f0003) == 0xf8010000)
98f08d3d 1614 op &= ~3UL;
c5aa993b
JM		 1615 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1616 }
1617 continue;
c906108c 1618
ddb20c56
KB		 1619 }
1620 else if ((op & 0xffff0000) == 0x60000000)
1621 {
96ff0de4 1622 /* nop */
ddb20c56
KB		 1623 /* Allow nops in the prologue, but do not consider them to
1624 be part of the prologue unless followed by other prologue
0df8b418 1625 instructions. */
ddb20c56
KB		 1626 prev_insn_was_prologue_insn = 0;
1627 continue;
1628
c906108c 1629 }
c5aa993b
JM		 1630 else if ((op & 0xffff0000) == 0x3c000000)
1631 { /* addis 0,0,NUM, used
1632 for >= 32k frames */
1633 fdata->offset = (op & 0x0000ffff) << 16;
1634 fdata->frameless = 0;
773df3e5 1635 r0_contains_arg = 0;
c5aa993b
JM		 1636 continue;
1637
1638 }
1639 else if ((op & 0xffff0000) == 0x60000000)
1640 { /* ori 0,0,NUM, 2nd ha
1641 lf of >= 32k frames */
1642 fdata->offset |= (op & 0x0000ffff);
1643 fdata->frameless = 0;
773df3e5 1644 r0_contains_arg = 0;
c5aa993b
JM		 1645 continue;
1646
1647 }
be723e22 1648 else if (lr_reg >= 0 &&
98f08d3d
KB		 1649 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1650 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1651 /* stw Rx, NUM(r1) */
1652 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1653 /* stwu Rx, NUM(r1) */
1654 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1655 { /* where Rx == lr */
1656 fdata->lr_offset = offset;
c5aa993b 1657 fdata->nosavedpc = 0;
be723e22
MS		 1658 /* Invalidate lr_reg, but don't set it to -1.
1659 That would mean that it had never been set. */
1660 lr_reg = -2;
98f08d3d
KB		 1661 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1662 (op & 0xfc000000) == 0x90000000) /* stw */
1663 {
1664 /* Does not update r1, so add displacement to lr_offset. */
1665 fdata->lr_offset += SIGNED_SHORT (op);
1666 }
c5aa993b
JM		 1667 continue;
1668
1669 }
be723e22 1670 else if (cr_reg >= 0 &&
98f08d3d
KB		 1671 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1672 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1673 /* stw Rx, NUM(r1) */
1674 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1675 /* stwu Rx, NUM(r1) */
1676 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1677 { /* where Rx == cr */
1678 fdata->cr_offset = offset;
be723e22
MS		 1679 /* Invalidate cr_reg, but don't set it to -1.
1680 That would mean that it had never been set. */
1681 cr_reg = -2;
98f08d3d
KB		 1682 if ((op & 0xfc000003) == 0xf8000000 ||
1683 (op & 0xfc000000) == 0x90000000)
1684 {
1685 /* Does not update r1, so add displacement to cr_offset. */
1686 fdata->cr_offset += SIGNED_SHORT (op);
1687 }
c5aa993b
JM		 1688 continue;
1689
1690 }
721d14ba
DJ		 1691 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1692 {
1693 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1694 prediction bits. If the LR has already been saved, we can
1695 skip it. */
1696 continue;
1697 }
c5aa993b
JM		 1698 else if (op == 0x48000005)
1699 { /* bl .+4 used in
1700 -mrelocatable */
46a9b8ed 1701 fdata->used_bl = 1;
c5aa993b
JM		 1702 continue;
1703
1704 }
1705 else if (op == 0x48000004)
1706 { /* b .+4 (xlc) */
1707 break;
1708
c5aa993b 1709 }
6be8bc0c
EZ		 1710 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1711 in V.4 -mminimal-toc */
c5aa993b
JM		 1712 (op & 0xffff0000) == 0x3bde0000)
1713 { /* addi 30,30,foo@l */
1714 continue;
c906108c 1715
c5aa993b
JM		 1716 }
1717 else if ((op & 0xfc000001) == 0x48000001)
1718 { /* bl foo,
0df8b418 1719 to save fprs??? */
c906108c 1720
c5aa993b 1721 fdata->frameless = 0;
3c77c82a
DJ		 1722
1723 /* If the return address has already been saved, we can skip
1724 calls to blrl (for PIC). */
e17a4113 1725 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op, byte_order))
46a9b8ed
DJ		 1726 {
1727 fdata->used_bl = 1;
1728 continue;
1729 }
3c77c82a 1730
6be8bc0c 1731 /* Don't skip over the subroutine call if it is not within
ebd98106
FF		 1732 the first three instructions of the prologue and either
1733 we have no line table information or the line info tells
1734 us that the subroutine call is not part of the line
1735 associated with the prologue. */
c5aa993b 1736 if ((pc - orig_pc) > 8)
ebd98106
FF		 1737 {
1738 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1739 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1740
0df8b418
MS		 1741 if ((prologue_sal.line == 0)
1742 || (prologue_sal.line != this_sal.line))
ebd98106
FF		 1743 break;
1744 }
c5aa993b 1745
e17a4113 1746 op = read_memory_integer (pc + 4, 4, byte_order);
c5aa993b 1747
6be8bc0c
EZ		 1748 /* At this point, make sure this is not a trampoline
1749 function (a function that simply calls another functions,
1750 and nothing else). If the next is not a nop, this branch
0df8b418 1751 was part of the function prologue. */
c5aa993b
JM		 1752
1753 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
0df8b418
MS		 1754 break; /* Don't skip over
1755 this branch. */
c5aa993b 1756
46a9b8ed
DJ		 1757 fdata->used_bl = 1;
1758 continue;
c5aa993b 1759 }
98f08d3d
KB		 1760 /* update stack pointer */
1761 else if ((op & 0xfc1f0000) == 0x94010000)
1762 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
c5aa993b
JM		 1763 fdata->frameless = 0;
1764 fdata->offset = SIGNED_SHORT (op);
1765 offset = fdata->offset;
1766 continue;
c5aa993b 1767 }
98f08d3d
KB		 1768 else if ((op & 0xfc1f016a) == 0x7c01016e)
1769 { /* stwux rX,r1,rY */
0df8b418 1770 /* No way to figure out what r1 is going to be. */
98f08d3d
KB		 1771 fdata->frameless = 0;
1772 offset = fdata->offset;
1773 continue;
1774 }
1775 else if ((op & 0xfc1f0003) == 0xf8010001)
1776 { /* stdu rX,NUM(r1) */
1777 fdata->frameless = 0;
1778 fdata->offset = SIGNED_SHORT (op & ~3UL);
1779 offset = fdata->offset;
1780 continue;
1781 }
1782 else if ((op & 0xfc1f016a) == 0x7c01016a)
1783 { /* stdux rX,r1,rY */
0df8b418 1784 /* No way to figure out what r1 is going to be. */
c5aa993b
JM		 1785 fdata->frameless = 0;
1786 offset = fdata->offset;
1787 continue;
c5aa993b 1788 }
7313566f
FF		 1789 else if ((op & 0xffff0000) == 0x38210000)
1790 { /* addi r1,r1,SIMM */
1791 fdata->frameless = 0;
1792 fdata->offset += SIGNED_SHORT (op);
1793 offset = fdata->offset;
1794 continue;
1795 }
4e463ff5
DJ		 1796 /* Load up minimal toc pointer. Do not treat an epilogue restore
1797 of r31 as a minimal TOC load. */
0df8b418
MS		 1798 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1799 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
4e463ff5 1800 && !framep
c5aa993b 1801 && !minimal_toc_loaded)
98f08d3d 1802 {
c5aa993b
JM		 1803 minimal_toc_loaded = 1;
1804 continue;
1805
f6077098
KB		 1806 /* move parameters from argument registers to local variable
1807 registers */
1808 }
1809 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1810 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1811 (((op >> 21) & 31) <= 10) &&
0df8b418
MS		 1812 ((long) ((op >> 16) & 31)
1813 >= fdata->saved_gpr)) /* Rx: local var reg */
f6077098
KB		 1814 {
1815 continue;
1816
c5aa993b
JM		 1817 /* store parameters in stack */
1818 }
e802b915 1819 /* Move parameters from argument registers to temporary register. */
773df3e5 1820 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
e802b915 1821 {
c5aa993b
JM		 1822 continue;
1823
1824 /* Set up frame pointer */
1825 }
1826 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1827 || op == 0x7c3f0b78)
1828 { /* mr r31, r1 */
1829 fdata->frameless = 0;
1830 framep = 1;
6f99cb26 1831 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
c5aa993b
JM		 1832 continue;
1833
1834 /* Another way to set up the frame pointer. */
1835 }
1836 else if ((op & 0xfc1fffff) == 0x38010000)
1837 { /* addi rX, r1, 0x0 */
1838 fdata->frameless = 0;
1839 framep = 1;
6f99cb26
AC		 1840 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1841 + ((op & ~0x38010000) >> 21));
c5aa993b 1842 continue;
c5aa993b 1843 }
6be8bc0c
EZ		 1844 /* AltiVec related instructions. */
1845 /* Store the vrsave register (spr 256) in another register for
1846 later manipulation, or load a register into the vrsave
1847 register. 2 instructions are used: mfvrsave and
1848 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1849 and mtspr SPR256, Rn. */
1850 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1851 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1852 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1853 {
1854 vrsave_reg = GET_SRC_REG (op);
1855 continue;
1856 }
1857 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1858 {
1859 continue;
1860 }
1861 /* Store the register where vrsave was saved to onto the stack:
1862 rS is the register where vrsave was stored in a previous
1863 instruction. */
1864 /* 100100 sssss 00001 dddddddd dddddddd */
1865 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1866 {
1867 if (vrsave_reg == GET_SRC_REG (op))
1868 {
1869 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1870 vrsave_reg = -1;
1871 }
1872 continue;
1873 }
1874 /* Compute the new value of vrsave, by modifying the register
1875 where vrsave was saved to. */
1876 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1877 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1878 {
1879 continue;
1880 }
1881 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1882 in a pair of insns to save the vector registers on the
1883 stack. */
1884 /* 001110 00000 00000 iiii iiii iiii iiii */
96ff0de4
EZ		 1885 /* 001110 01110 00000 iiii iiii iiii iiii */
1886 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1887 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
6be8bc0c 1888 {
773df3e5
JB		 1889 if ((op & 0xffff0000) == 0x38000000)
1890 r0_contains_arg = 0;
6be8bc0c
EZ		 1891 li_found_pc = pc;
1892 vr_saved_offset = SIGNED_SHORT (op);
773df3e5
JB		 1893
1894 /* This insn by itself is not part of the prologue, unless
0df8b418 1895 if part of the pair of insns mentioned above. So do not
773df3e5
JB		 1896 record this insn as part of the prologue yet. */
1897 prev_insn_was_prologue_insn = 0;
6be8bc0c
EZ		 1898 }
1899 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1900 /* 011111 sssss 11111 00000 00111001110 */
1901 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1902 {
1903 if (pc == (li_found_pc + 4))
1904 {
1905 vr_reg = GET_SRC_REG (op);
1906 /* If this is the first vector reg to be saved, or if
1907 it has a lower number than others previously seen,
1908 reupdate the frame info. */
1909 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1910 {
1911 fdata->saved_vr = vr_reg;
1912 fdata->vr_offset = vr_saved_offset + offset;
1913 }
1914 vr_saved_offset = -1;
1915 vr_reg = -1;
1916 li_found_pc = 0;
1917 }
1918 }
1919 /* End AltiVec related instructions. */
96ff0de4
EZ		 1920
1921 /* Start BookE related instructions. */
1922 /* Store gen register S at (r31+uimm).
1923 Any register less than r13 is volatile, so we don't care. */
1924 /* 000100 sssss 11111 iiiii 01100100001 */
1925 else if (arch_info->mach == bfd_mach_ppc_e500
1926 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1927 {
1928 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1929 {
1930 unsigned int imm;
1931 ev_reg = GET_SRC_REG (op);
1932 imm = (op >> 11) & 0x1f;
1933 ev_offset = imm * 8;
1934 /* If this is the first vector reg to be saved, or if
1935 it has a lower number than others previously seen,
1936 reupdate the frame info. */
1937 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1938 {
1939 fdata->saved_ev = ev_reg;
1940 fdata->ev_offset = ev_offset + offset;
1941 }
1942 }
1943 continue;
1944 }
1945 /* Store gen register rS at (r1+rB). */
1946 /* 000100 sssss 00001 bbbbb 01100100000 */
1947 else if (arch_info->mach == bfd_mach_ppc_e500
1948 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1949 {
1950 if (pc == (li_found_pc + 4))
1951 {
1952 ev_reg = GET_SRC_REG (op);
1953 /* If this is the first vector reg to be saved, or if
1954 it has a lower number than others previously seen,
1955 reupdate the frame info. */
1956 /* We know the contents of rB from the previous instruction. */
1957 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1958 {
1959 fdata->saved_ev = ev_reg;
1960 fdata->ev_offset = vr_saved_offset + offset;
1961 }
1962 vr_saved_offset = -1;
1963 ev_reg = -1;
1964 li_found_pc = 0;
1965 }
1966 continue;
1967 }
1968 /* Store gen register r31 at (rA+uimm). */
1969 /* 000100 11111 aaaaa iiiii 01100100001 */
1970 else if (arch_info->mach == bfd_mach_ppc_e500
1971 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1972 {
1973 /* Wwe know that the source register is 31 already, but
1974 it can't hurt to compute it. */
1975 ev_reg = GET_SRC_REG (op);
1976 ev_offset = ((op >> 11) & 0x1f) * 8;
1977 /* If this is the first vector reg to be saved, or if
1978 it has a lower number than others previously seen,
1979 reupdate the frame info. */
1980 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1981 {
1982 fdata->saved_ev = ev_reg;
1983 fdata->ev_offset = ev_offset + offset;
1984 }
1985
1986 continue;
1987 }
1988 /* Store gen register S at (r31+r0).
1989 Store param on stack when offset from SP bigger than 4 bytes. */
1990 /* 000100 sssss 11111 00000 01100100000 */
1991 else if (arch_info->mach == bfd_mach_ppc_e500
1992 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1993 {
1994 if (pc == (li_found_pc + 4))
1995 {
1996 if ((op & 0x03e00000) >= 0x01a00000)
1997 {
1998 ev_reg = GET_SRC_REG (op);
1999 /* If this is the first vector reg to be saved, or if
2000 it has a lower number than others previously seen,
2001 reupdate the frame info. */
2002 /* We know the contents of r0 from the previous
2003 instruction. */
2004 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
2005 {
2006 fdata->saved_ev = ev_reg;
2007 fdata->ev_offset = vr_saved_offset + offset;
2008 }
2009 ev_reg = -1;
2010 }
2011 vr_saved_offset = -1;
2012 li_found_pc = 0;
2013 continue;
2014 }
2015 }
2016 /* End BookE related instructions. */
2017
c5aa993b
JM		 2018 else
2019 {
46a9b8ed
DJ		 2020 unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1);
2021
55d05f3b
KB		 2022 /* Not a recognized prologue instruction.
2023 Handle optimizer code motions into the prologue by continuing
2024 the search if we have no valid frame yet or if the return
46a9b8ed
DJ		 2025 address is not yet saved in the frame. Also skip instructions
2026 if some of the GPRs expected to be saved are not yet saved. */
2027 if (fdata->frameless == 0 && fdata->nosavedpc == 0
2028 && (fdata->gpr_mask & all_mask) == all_mask)
55d05f3b
KB		 2029 break;
2030
2031 if (op == 0x4e800020 /* blr */
2032 || op == 0x4e800420) /* bctr */
2033 /* Do not scan past epilogue in frameless functions or
2034 trampolines. */
2035 break;
2036 if ((op & 0xf4000000) == 0x40000000) /* bxx */
64366f1c 2037 /* Never skip branches. */
55d05f3b
KB		 2038 break;
2039
2040 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
2041 /* Do not scan too many insns, scanning insns is expensive with
2042 remote targets. */
2043 break;
2044
2045 /* Continue scanning. */
2046 prev_insn_was_prologue_insn = 0;
2047 continue;
c5aa993b 2048 }
c906108c
SS		 2049 }
2050
2051#if 0
2052/* I have problems with skipping over __main() that I need to address
0df8b418 2053 * sometime. Previously, I used to use misc_function_vector which
c906108c
SS		 2054 * didn't work as well as I wanted to be. -MGO */
2055
2056 /* If the first thing after skipping a prolog is a branch to a function,
2057 this might be a call to an initializer in main(), introduced by gcc2.
64366f1c 2058 We'd like to skip over it as well. Fortunately, xlc does some extra
c906108c 2059 work before calling a function right after a prologue, thus we can
64366f1c 2060 single out such gcc2 behaviour. */
c906108c 2061
c906108c 2062
c5aa993b 2063 if ((op & 0xfc000001) == 0x48000001)
0df8b418 2064 { /* bl foo, an initializer function? */
e17a4113 2065 op = read_memory_integer (pc + 4, 4, byte_order);
c5aa993b
JM		 2066
2067 if (op == 0x4def7b82)
2068 { /* cror 0xf, 0xf, 0xf (nop) */
c906108c 2069
64366f1c
EZ		 2070 /* Check and see if we are in main. If so, skip over this
2071 initializer function as well. */
c906108c 2072
c5aa993b 2073 tmp = find_pc_misc_function (pc);
6314a349
AC		 2074 if (tmp >= 0
2075 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
c5aa993b
JM		 2076 return pc + 8;
2077 }
c906108c 2078 }
c906108c 2079#endif /* 0 */
c5aa993b 2080
46a9b8ed
DJ		 2081 if (pc == lim_pc && lr_reg >= 0)
2082 fdata->lr_register = lr_reg;
2083
c5aa993b 2084 fdata->offset = -fdata->offset;
ddb20c56 2085 return last_prologue_pc;
c906108c
SS		 2086}
2087
7a78ae4e 2088static CORE_ADDR
4a7622d1 2089rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
c906108c 2090{
4a7622d1 2091 struct rs6000_framedata frame;
e3acb115 2092 CORE_ADDR limit_pc, func_addr, func_end_addr = 0;
c906108c 2093
4a7622d1
UW		 2094 /* See if we can determine the end of the prologue via the symbol table.
2095 If so, then return either PC, or the PC after the prologue, whichever
2096 is greater. */
e3acb115 2097 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr))
c5aa993b 2098 {
d80b854b
UW		 2099 CORE_ADDR post_prologue_pc
2100 = skip_prologue_using_sal (gdbarch, func_addr);
4a7622d1
UW		 2101 if (post_prologue_pc != 0)
2102 return max (pc, post_prologue_pc);
c906108c 2103 }
c906108c 2104
4a7622d1
UW		 2105 /* Can't determine prologue from the symbol table, need to examine
2106 instructions. */
c906108c 2107
4a7622d1
UW		 2108 /* Find an upper limit on the function prologue using the debug
2109 information. If the debug information could not be used to provide
2110 that bound, then use an arbitrary large number as the upper bound. */
d80b854b 2111 limit_pc = skip_prologue_using_sal (gdbarch, pc);
4a7622d1
UW		 2112 if (limit_pc == 0)
2113 limit_pc = pc + 100; /* Magic. */
794a477a 2114
e3acb115
JB		 2115 /* Do not allow limit_pc to be past the function end, if we know
2116 where that end is... */
2117 if (func_end_addr && limit_pc > func_end_addr)
2118 limit_pc = func_end_addr;
2119
4a7622d1
UW		 2120 pc = skip_prologue (gdbarch, pc, limit_pc, &frame);
2121 return pc;
c906108c 2122}
c906108c 2123
8ab3d180
KB		 2124/* When compiling for EABI, some versions of GCC emit a call to __eabi
2125 in the prologue of main().
2126
2127 The function below examines the code pointed at by PC and checks to
2128 see if it corresponds to a call to __eabi. If so, it returns the
2129 address of the instruction following that call. Otherwise, it simply
2130 returns PC. */
2131
63807e1d 2132static CORE_ADDR
8ab3d180
KB		 2133rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2134{
e17a4113 2135 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8ab3d180
KB		 2136 gdb_byte buf[4];
2137 unsigned long op;
2138
2139 if (target_read_memory (pc, buf, 4))
2140 return pc;
e17a4113 2141 op = extract_unsigned_integer (buf, 4, byte_order);
8ab3d180
KB		 2142
2143 if ((op & BL_MASK) == BL_INSTRUCTION)
2144 {
2145 CORE_ADDR displ = op & BL_DISPLACEMENT_MASK;
2146 CORE_ADDR call_dest = pc + 4 + displ;
2147 struct minimal_symbol *s = lookup_minimal_symbol_by_pc (call_dest);
2148
2149 /* We check for ___eabi (three leading underscores) in addition
2150 to __eabi in case the GCC option "-fleading-underscore" was
2151 used to compile the program. */
2152 if (s != NULL
2153 && SYMBOL_LINKAGE_NAME (s) != NULL
2154 && (strcmp (SYMBOL_LINKAGE_NAME (s), "__eabi") == 0
2155 || strcmp (SYMBOL_LINKAGE_NAME (s), "___eabi") == 0))
2156 pc += 4;
2157 }
2158 return pc;
2159}
383f0f5b 2160
4a7622d1
UW		 2161/* All the ABI's require 16 byte alignment. */
2162static CORE_ADDR
2163rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2164{
2165 return (addr & -16);
c906108c
SS		 2166}
2167
977adac5
ND		 2168/* Return whether handle_inferior_event() should proceed through code
2169 starting at PC in function NAME when stepping.
2170
2171 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2172 handle memory references that are too distant to fit in instructions
2173 generated by the compiler. For example, if 'foo' in the following
2174 instruction:
2175
2176 lwz r9,foo(r2)
2177
2178 is greater than 32767, the linker might replace the lwz with a branch to
2179 somewhere in @FIX1 that does the load in 2 instructions and then branches
2180 back to where execution should continue.
2181
2182 GDB should silently step over @FIX code, just like AIX dbx does.
2ec664f5
MS		 2183 Unfortunately, the linker uses the "b" instruction for the
2184 branches, meaning that the link register doesn't get set.
2185 Therefore, GDB's usual step_over_function () mechanism won't work.
977adac5 2186
e76f05fa
UW		 2187 Instead, use the gdbarch_skip_trampoline_code and
2188 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2ec664f5 2189 @FIX code. */
977adac5 2190
63807e1d 2191static int
e17a4113
UW		 2192rs6000_in_solib_return_trampoline (struct gdbarch *gdbarch,
2193 CORE_ADDR pc, char *name)
977adac5
ND		 2194{
2195 return name && !strncmp (name, "@FIX", 4);
2196}
2197
2198/* Skip code that the user doesn't want to see when stepping:
2199
2200 1. Indirect function calls use a piece of trampoline code to do context
2201 switching, i.e. to set the new TOC table. Skip such code if we are on
2202 its first instruction (as when we have single-stepped to here).
2203
2204 2. Skip shared library trampoline code (which is different from
c906108c 2205 indirect function call trampolines).
977adac5
ND		 2206
2207 3. Skip bigtoc fixup code.
2208
c906108c 2209 Result is desired PC to step until, or NULL if we are not in
977adac5 2210 code that should be skipped. */
c906108c 2211
63807e1d 2212static CORE_ADDR
52f729a7 2213rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
c906108c 2214{
e17a4113
UW		 2215 struct gdbarch *gdbarch = get_frame_arch (frame);
2216 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2217 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
52f0bd74 2218 unsigned int ii, op;
977adac5 2219 int rel;
c906108c 2220 CORE_ADDR solib_target_pc;
977adac5 2221 struct minimal_symbol *msymbol;
c906108c 2222
c5aa993b
JM		 2223 static unsigned trampoline_code[] =
2224 {
2225 0x800b0000, /* l r0,0x0(r11) */
2226 0x90410014, /* st r2,0x14(r1) */
2227 0x7c0903a6, /* mtctr r0 */
2228 0x804b0004, /* l r2,0x4(r11) */
2229 0x816b0008, /* l r11,0x8(r11) */
2230 0x4e800420, /* bctr */
2231 0x4e800020, /* br */
2232 0
c906108c
SS		 2233 };
2234
977adac5
ND		 2235 /* Check for bigtoc fixup code. */
2236 msymbol = lookup_minimal_symbol_by_pc (pc);
2ec664f5 2237 if (msymbol
e17a4113
UW		 2238 && rs6000_in_solib_return_trampoline (gdbarch, pc,
2239 SYMBOL_LINKAGE_NAME (msymbol)))
977adac5
ND		 2240 {
2241 /* Double-check that the third instruction from PC is relative "b". */
e17a4113 2242 op = read_memory_integer (pc + 8, 4, byte_order);
977adac5
ND		 2243 if ((op & 0xfc000003) == 0x48000000)
2244 {
2245 /* Extract bits 6-29 as a signed 24-bit relative word address and
2246 add it to the containing PC. */
2247 rel = ((int)(op << 6) >> 6);
2248 return pc + 8 + rel;
2249 }
2250 }
2251
c906108c 2252 /* If pc is in a shared library trampoline, return its target. */
52f729a7 2253 solib_target_pc = find_solib_trampoline_target (frame, pc);
c906108c
SS		 2254 if (solib_target_pc)
2255 return solib_target_pc;
2256
c5aa993b
JM		 2257 for (ii = 0; trampoline_code[ii]; ++ii)
2258 {
e17a4113 2259 op = read_memory_integer (pc + (ii * 4), 4, byte_order);
c5aa993b
JM		 2260 if (op != trampoline_code[ii])
2261 return 0;
2262 }
0df8b418
MS		 2263 ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination
2264 addr. */
e17a4113 2265 pc = read_memory_unsigned_integer (ii, tdep->wordsize, byte_order);
c906108c
SS		 2266 return pc;
2267}
2268
794ac428
UW		 2269/* ISA-specific vector types. */
2270
2271static struct type *
2272rs6000_builtin_type_vec64 (struct gdbarch *gdbarch)
2273{
2274 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2275
2276 if (!tdep->ppc_builtin_type_vec64)
2277 {
df4df182
UW		 2278 const struct builtin_type *bt = builtin_type (gdbarch);
2279
794ac428
UW		 2280 /* The type we're building is this: */
2281#if 0
2282 union __gdb_builtin_type_vec64
2283 {
2284 int64_t uint64;
2285 float v2_float[2];
2286 int32_t v2_int32[2];
2287 int16_t v4_int16[4];
2288 int8_t v8_int8[8];
2289 };
2290#endif
2291
2292 struct type *t;
2293
e9bb382b
UW		 2294 t = arch_composite_type (gdbarch,
2295 "__ppc_builtin_type_vec64", TYPE_CODE_UNION);
df4df182 2296 append_composite_type_field (t, "uint64", bt->builtin_int64);
794ac428 2297 append_composite_type_field (t, "v2_float",
df4df182 2298 init_vector_type (bt->builtin_float, 2));
794ac428 2299 append_composite_type_field (t, "v2_int32",
df4df182 2300 init_vector_type (bt->builtin_int32, 2));
794ac428 2301 append_composite_type_field (t, "v4_int16",
df4df182 2302 init_vector_type (bt->builtin_int16, 4));
794ac428 2303 append_composite_type_field (t, "v8_int8",
df4df182 2304 init_vector_type (bt->builtin_int8, 8));
794ac428 2305
876cecd0 2306 TYPE_VECTOR (t) = 1;
794ac428
UW		 2307 TYPE_NAME (t) = "ppc_builtin_type_vec64";
2308 tdep->ppc_builtin_type_vec64 = t;
2309 }
2310
2311 return tdep->ppc_builtin_type_vec64;
2312}
2313
604c2f83
LM		 2314/* Vector 128 type. */
2315
2316static struct type *
2317rs6000_builtin_type_vec128 (struct gdbarch *gdbarch)
2318{
2319 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2320
2321 if (!tdep->ppc_builtin_type_vec128)
2322 {
df4df182
UW		 2323 const struct builtin_type *bt = builtin_type (gdbarch);
2324
604c2f83
LM		 2325 /* The type we're building is this
2326
2327 type = union __ppc_builtin_type_vec128 {
2328 uint128_t uint128;
db9f5df8 2329 double v2_double[2];
604c2f83
LM		 2330 float v4_float[4];
2331 int32_t v4_int32[4];
2332 int16_t v8_int16[8];
2333 int8_t v16_int8[16];
2334 }
2335 */
2336
2337 struct type *t;
2338
e9bb382b
UW		 2339 t = arch_composite_type (gdbarch,
2340 "__ppc_builtin_type_vec128", TYPE_CODE_UNION);
df4df182 2341 append_composite_type_field (t, "uint128", bt->builtin_uint128);
db9f5df8
UW		 2342 append_composite_type_field (t, "v2_double",
2343 init_vector_type (bt->builtin_double, 2));
604c2f83 2344 append_composite_type_field (t, "v4_float",
df4df182 2345 init_vector_type (bt->builtin_float, 4));
604c2f83 2346 append_composite_type_field (t, "v4_int32",
df4df182 2347 init_vector_type (bt->builtin_int32, 4));
604c2f83 2348 append_composite_type_field (t, "v8_int16",
df4df182 2349 init_vector_type (bt->builtin_int16, 8));
604c2f83 2350 append_composite_type_field (t, "v16_int8",
df4df182 2351 init_vector_type (bt->builtin_int8, 16));
604c2f83 2352
803e1097 2353 TYPE_VECTOR (t) = 1;
604c2f83
LM		 2354 TYPE_NAME (t) = "ppc_builtin_type_vec128";
2355 tdep->ppc_builtin_type_vec128 = t;
2356 }
2357
2358 return tdep->ppc_builtin_type_vec128;
2359}
2360
7cc46491
DJ		 2361/* Return the name of register number REGNO, or the empty string if it
2362 is an anonymous register. */
7a78ae4e 2363
fa88f677 2364static const char *
d93859e2 2365rs6000_register_name (struct gdbarch *gdbarch, int regno)
7a78ae4e 2366{
d93859e2 2367 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7a78ae4e 2368
7cc46491
DJ		 2369 /* The upper half "registers" have names in the XML description,
2370 but we present only the low GPRs and the full 64-bit registers
2371 to the user. */
2372 if (tdep->ppc_ev0_upper_regnum >= 0
2373 && tdep->ppc_ev0_upper_regnum <= regno
2374 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
2375 return "";
2376
604c2f83
LM		 2377 /* Hide the upper halves of the vs0~vs31 registers. */
2378 if (tdep->ppc_vsr0_regnum >= 0
2379 && tdep->ppc_vsr0_upper_regnum <= regno
2380 && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs)
2381 return "";
2382
7cc46491 2383 /* Check if the SPE pseudo registers are available. */
5a9e69ba 2384 if (IS_SPE_PSEUDOREG (tdep, regno))
7cc46491
DJ		 2385 {
2386 static const char *const spe_regnames[] = {
2387 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2388 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2389 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2390 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2391 };
2392 return spe_regnames[regno - tdep->ppc_ev0_regnum];
2393 }
2394
f949c649
TJB		 2395 /* Check if the decimal128 pseudo-registers are available. */
2396 if (IS_DFP_PSEUDOREG (tdep, regno))
2397 {
2398 static const char *const dfp128_regnames[] = {
2399 "dl0", "dl1", "dl2", "dl3",
2400 "dl4", "dl5", "dl6", "dl7",
2401 "dl8", "dl9", "dl10", "dl11",
2402 "dl12", "dl13", "dl14", "dl15"
2403 };
2404 return dfp128_regnames[regno - tdep->ppc_dl0_regnum];
2405 }
2406
604c2f83
LM		 2407 /* Check if this is a VSX pseudo-register. */
2408 if (IS_VSX_PSEUDOREG (tdep, regno))
2409 {
2410 static const char *const vsx_regnames[] = {
2411 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2412 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2413 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2414 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2415 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2416 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2417 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2418 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2419 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2420 };
2421 return vsx_regnames[regno - tdep->ppc_vsr0_regnum];
2422 }
2423
2424 /* Check if the this is a Extended FP pseudo-register. */
2425 if (IS_EFP_PSEUDOREG (tdep, regno))
2426 {
2427 static const char *const efpr_regnames[] = {
2428 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2429 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2430 "f46", "f47", "f48", "f49", "f50", "f51",
2431 "f52", "f53", "f54", "f55", "f56", "f57",
2432 "f58", "f59", "f60", "f61", "f62", "f63"
2433 };
2434 return efpr_regnames[regno - tdep->ppc_efpr0_regnum];
2435 }
2436
d93859e2 2437 return tdesc_register_name (gdbarch, regno);
7a78ae4e
ND		 2438}
2439
7cc46491
DJ		 2440/* Return the GDB type object for the "standard" data type of data in
2441 register N. */
7a78ae4e
ND		 2442
2443static struct type *
7cc46491 2444rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
7a78ae4e 2445{
691d145a 2446 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7a78ae4e 2447
7cc46491 2448 /* These are the only pseudo-registers we support. */
f949c649 2449 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
604c2f83
LM		 2450 || IS_DFP_PSEUDOREG (tdep, regnum)
2451 || IS_VSX_PSEUDOREG (tdep, regnum)
2452 || IS_EFP_PSEUDOREG (tdep, regnum));
7cc46491 2453
f949c649
TJB		 2454 /* These are the e500 pseudo-registers. */
2455 if (IS_SPE_PSEUDOREG (tdep, regnum))
2456 return rs6000_builtin_type_vec64 (gdbarch);
604c2f83
LM		 2457 else if (IS_DFP_PSEUDOREG (tdep, regnum))
2458 /* PPC decimal128 pseudo-registers. */
f949c649 2459 return builtin_type (gdbarch)->builtin_declong;
604c2f83
LM		 2460 else if (IS_VSX_PSEUDOREG (tdep, regnum))
2461 /* POWER7 VSX pseudo-registers. */
2462 return rs6000_builtin_type_vec128 (gdbarch);
2463 else
2464 /* POWER7 Extended FP pseudo-registers. */
2465 return builtin_type (gdbarch)->builtin_double;
7a78ae4e
ND		 2466}
2467
c44ca51c
AC		 2468/* Is REGNUM a member of REGGROUP? */
2469static int
7cc46491
DJ		 2470rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2471 struct reggroup *group)
c44ca51c
AC		 2472{
2473 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
c44ca51c 2474
7cc46491 2475 /* These are the only pseudo-registers we support. */
f949c649 2476 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
604c2f83
LM		 2477 || IS_DFP_PSEUDOREG (tdep, regnum)
2478 || IS_VSX_PSEUDOREG (tdep, regnum)
2479 || IS_EFP_PSEUDOREG (tdep, regnum));
c44ca51c 2480
604c2f83
LM		 2481 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2482 if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum))
f949c649 2483 return group == all_reggroup || group == vector_reggroup;
7cc46491 2484 else
604c2f83 2485 /* PPC decimal128 or Extended FP pseudo-registers. */
f949c649 2486 return group == all_reggroup || group == float_reggroup;
c44ca51c
AC		 2487}
2488
691d145a 2489/* The register format for RS/6000 floating point registers is always
64366f1c 2490 double, we need a conversion if the memory format is float. */
7a78ae4e
ND		 2491
2492static int
0abe36f5
MD		 2493rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum,
2494 struct type *type)
7a78ae4e 2495{
0abe36f5 2496 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7cc46491
DJ		 2497
2498 return (tdep->ppc_fp0_regnum >= 0
2499 && regnum >= tdep->ppc_fp0_regnum
2500 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs
2501 && TYPE_CODE (type) == TYPE_CODE_FLT
0dfff4cb
UW		 2502 && TYPE_LENGTH (type)
2503 != TYPE_LENGTH (builtin_type (gdbarch)->builtin_double));
7a78ae4e
ND		 2504}
2505
8dccd430 2506static int
691d145a
JB		 2507rs6000_register_to_value (struct frame_info *frame,
2508 int regnum,
2509 struct type *type,
8dccd430
PA		 2510 gdb_byte *to,
2511 int *optimizedp, int *unavailablep)
7a78ae4e 2512{
0dfff4cb 2513 struct gdbarch *gdbarch = get_frame_arch (frame);
50fd1280 2514 gdb_byte from[MAX_REGISTER_SIZE];
691d145a 2515
691d145a 2516 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
7a78ae4e 2517
8dccd430
PA		 2518 if (!get_frame_register_bytes (frame, regnum, 0,
2519 register_size (gdbarch, regnum),
2520 from, optimizedp, unavailablep))
2521 return 0;
2522
0dfff4cb
UW		 2523 convert_typed_floating (from, builtin_type (gdbarch)->builtin_double,
2524 to, type);
8dccd430
PA		 2525 *optimizedp = *unavailablep = 0;
2526 return 1;
691d145a 2527}
7a292a7a 2528
7a78ae4e 2529static void
691d145a
JB		 2530rs6000_value_to_register (struct frame_info *frame,
2531 int regnum,
2532 struct type *type,
50fd1280 2533 const gdb_byte *from)
7a78ae4e 2534{
0dfff4cb 2535 struct gdbarch *gdbarch = get_frame_arch (frame);
50fd1280 2536 gdb_byte to[MAX_REGISTER_SIZE];
691d145a 2537
691d145a
JB		 2538 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2539
0dfff4cb
UW		 2540 convert_typed_floating (from, type,
2541 to, builtin_type (gdbarch)->builtin_double);
691d145a 2542 put_frame_register (frame, regnum, to);
7a78ae4e 2543}
c906108c 2544
05d1431c
PA		 2545 /* The type of a function that moves the value of REG between CACHE
2546 or BUF --- in either direction. */
2547typedef enum register_status (*move_ev_register_func) (struct regcache *,
2548 int, void *);
2549
6ced10dd
JB		 2550/* Move SPE vector register values between a 64-bit buffer and the two
2551 32-bit raw register halves in a regcache. This function handles
2552 both splitting a 64-bit value into two 32-bit halves, and joining
2553 two halves into a whole 64-bit value, depending on the function
2554 passed as the MOVE argument.
2555
2556 EV_REG must be the number of an SPE evN vector register --- a
2557 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2558 64-bit buffer.
2559
2560 Call MOVE once for each 32-bit half of that register, passing
2561 REGCACHE, the number of the raw register corresponding to that
2562 half, and the address of the appropriate half of BUFFER.
2563
2564 For example, passing 'regcache_raw_read' as the MOVE function will
2565 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2566 'regcache_raw_supply' will supply the contents of BUFFER to the
2567 appropriate pair of raw registers in REGCACHE.
2568
2569 You may need to cast away some 'const' qualifiers when passing
2570 MOVE, since this function can't tell at compile-time which of
2571 REGCACHE or BUFFER is acting as the source of the data. If C had
2572 co-variant type qualifiers, ... */
05d1431c
PA		 2573
2574static enum register_status
2575e500_move_ev_register (move_ev_register_func move,
2576 struct regcache *regcache, int ev_reg, void *buffer)
6ced10dd
JB		 2577{
2578 struct gdbarch *arch = get_regcache_arch (regcache);
2579 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2580 int reg_index;
50fd1280 2581 gdb_byte *byte_buffer = buffer;
05d1431c 2582 enum register_status status;
6ced10dd 2583
5a9e69ba 2584 gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg));
6ced10dd
JB		 2585
2586 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2587
8b164abb 2588 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
6ced10dd 2589 {
05d1431c
PA		 2590 status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index,
2591 byte_buffer);
2592 if (status == REG_VALID)
2593 status = move (regcache, tdep->ppc_gp0_regnum + reg_index,
2594 byte_buffer + 4);
6ced10dd
JB		 2595 }
2596 else
2597 {
05d1431c
PA		 2598 status = move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2599 if (status == REG_VALID)
2600 status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index,
2601 byte_buffer + 4);
6ced10dd 2602 }
05d1431c
PA		 2603
2604 return status;
6ced10dd
JB		 2605}
2606
05d1431c
PA		 2607static enum register_status
2608do_regcache_raw_read (struct regcache *regcache, int regnum, void *buffer)
2609{
2610 return regcache_raw_read (regcache, regnum, buffer);
2611}
2612
2613static enum register_status
2614do_regcache_raw_write (struct regcache *regcache, int regnum, void *buffer)
2615{
2616 regcache_raw_write (regcache, regnum, buffer);
2617
2618 return REG_VALID;
2619}
2620
2621static enum register_status
c8001721 2622e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
50fd1280 2623 int reg_nr, gdb_byte *buffer)
f949c649 2624{
05d1431c 2625 return e500_move_ev_register (do_regcache_raw_read, regcache, reg_nr, buffer);
f949c649
TJB		 2626}
2627
2628static void
2629e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2630 int reg_nr, const gdb_byte *buffer)
2631{
05d1431c
PA		 2632 e500_move_ev_register (do_regcache_raw_write, regcache,
2633 reg_nr, (void *) buffer);
f949c649
TJB		 2634}
2635
604c2f83 2636/* Read method for DFP pseudo-registers. */
05d1431c 2637static enum register_status
604c2f83 2638dfp_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
f949c649
TJB		 2639 int reg_nr, gdb_byte *buffer)
2640{
2641 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2642 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
05d1431c 2643 enum register_status status;
f949c649
TJB		 2644
2645 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2646 {
2647 /* Read two FP registers to form a whole dl register. */
05d1431c
PA		 2648 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2649 2 * reg_index, buffer);
2650 if (status == REG_VALID)
2651 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2652 2 * reg_index + 1, buffer + 8);
f949c649
TJB		 2653 }
2654 else
2655 {
05d1431c
PA		 2656 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2657 2 * reg_index + 1, buffer + 8);
2658 if (status == REG_VALID)
2659 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2660 2 * reg_index, buffer);
f949c649 2661 }
05d1431c
PA		 2662
2663 return status;
f949c649
TJB		 2664}
2665
604c2f83 2666/* Write method for DFP pseudo-registers. */
f949c649 2667static void
604c2f83 2668dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
f949c649
TJB		 2669 int reg_nr, const gdb_byte *buffer)
2670{
2671 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2672 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2673
2674 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2675 {
2676 /* Write each half of the dl register into a separate
2677 FP register. */
2678 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2679 2 * reg_index, buffer);
2680 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2681 2 * reg_index + 1, buffer + 8);
2682 }
2683 else
2684 {
2685 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2686 2 * reg_index + 1, buffer + 8);
2687 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2688 2 * reg_index, buffer);
2689 }
2690}
2691
604c2f83 2692/* Read method for POWER7 VSX pseudo-registers. */
05d1431c 2693static enum register_status
604c2f83
LM		 2694vsx_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2695 int reg_nr, gdb_byte *buffer)
2696{
2697 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2698 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
05d1431c 2699 enum register_status status;
604c2f83
LM		 2700
2701 /* Read the portion that overlaps the VMX registers. */
2702 if (reg_index > 31)
05d1431c
PA		 2703 status = regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2704 reg_index - 32, buffer);
604c2f83
LM		 2705 else
2706 /* Read the portion that overlaps the FPR registers. */
2707 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2708 {
05d1431c
PA		 2709 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2710 reg_index, buffer);
2711 if (status == REG_VALID)
2712 status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2713 reg_index, buffer + 8);
604c2f83
LM		 2714 }
2715 else
2716 {
05d1431c
PA		 2717 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2718 reg_index, buffer + 8);
2719 if (status == REG_VALID)
2720 status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2721 reg_index, buffer);
604c2f83 2722 }
05d1431c
PA		 2723
2724 return status;
604c2f83
LM		 2725}
2726
2727/* Write method for POWER7 VSX pseudo-registers. */
2728static void
2729vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2730 int reg_nr, const gdb_byte *buffer)
2731{
2732 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2733 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2734
2735 /* Write the portion that overlaps the VMX registers. */
2736 if (reg_index > 31)
2737 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2738 reg_index - 32, buffer);
2739 else
2740 /* Write the portion that overlaps the FPR registers. */
2741 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2742 {
2743 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2744 reg_index, buffer);
2745 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2746 reg_index, buffer + 8);
2747 }
2748 else
2749 {
2750 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2751 reg_index, buffer + 8);
2752 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2753 reg_index, buffer);
2754 }
2755}
2756
2757/* Read method for POWER7 Extended FP pseudo-registers. */
05d1431c 2758static enum register_status
604c2f83
LM		 2759efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2760 int reg_nr, gdb_byte *buffer)
2761{
2762 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2763 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2764
d9492458 2765 /* Read the portion that overlaps the VMX register. */
05d1431c
PA		 2766 return regcache_raw_read_part (regcache, tdep->ppc_vr0_regnum + reg_index, 0,
2767 register_size (gdbarch, reg_nr), buffer);
604c2f83
LM		 2768}
2769
2770/* Write method for POWER7 Extended FP pseudo-registers. */
2771static void
2772efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2773 int reg_nr, const gdb_byte *buffer)
2774{
2775 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2776 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2777
d9492458
TJB		 2778 /* Write the portion that overlaps the VMX register. */
2779 regcache_raw_write_part (regcache, tdep->ppc_vr0_regnum + reg_index, 0,
2780 register_size (gdbarch, reg_nr), buffer);
604c2f83
LM		 2781}
2782
05d1431c 2783static enum register_status
0df8b418
MS		 2784rs6000_pseudo_register_read (struct gdbarch *gdbarch,
2785 struct regcache *regcache,
f949c649 2786 int reg_nr, gdb_byte *buffer)
c8001721 2787{
6ced10dd 2788 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
c8001721
EZ		 2789 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2790
6ced10dd 2791 gdb_assert (regcache_arch == gdbarch);
f949c649 2792
5a9e69ba 2793 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
05d1431c 2794 return e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
f949c649 2795 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
05d1431c 2796 return dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
604c2f83 2797 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
05d1431c 2798 return vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
604c2f83 2799 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
05d1431c 2800 return efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
6ced10dd 2801 else
a44bddec 2802 internal_error (__FILE__, __LINE__,
f949c649
TJB		 2803 _("rs6000_pseudo_register_read: "
2804 "called on unexpected register '%s' (%d)"),
2805 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
c8001721
EZ		 2806}
2807
2808static void
f949c649
TJB		 2809rs6000_pseudo_register_write (struct gdbarch *gdbarch,
2810 struct regcache *regcache,
2811 int reg_nr, const gdb_byte *buffer)
c8001721 2812{
6ced10dd 2813 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
c8001721
EZ		 2814 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2815
6ced10dd 2816 gdb_assert (regcache_arch == gdbarch);
f949c649 2817
5a9e69ba 2818 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
f949c649
TJB		 2819 e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2820 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
604c2f83
LM		 2821 dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2822 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2823 vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2824 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2825 efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
6ced10dd 2826 else
a44bddec 2827 internal_error (__FILE__, __LINE__,
f949c649
TJB		 2828 _("rs6000_pseudo_register_write: "
2829 "called on unexpected register '%s' (%d)"),
2830 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
6ced10dd
JB		 2831}
2832
18ed0c4e 2833/* Convert a DBX STABS register number to a GDB register number. */
c8001721 2834static int
d3f73121 2835rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
c8001721 2836{
d3f73121 2837 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
c8001721 2838
9f744501
JB		 2839 if (0 <= num && num <= 31)
2840 return tdep->ppc_gp0_regnum + num;
2841 else if (32 <= num && num <= 63)
383f0f5b
JB		 2842 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2843 specifies registers the architecture doesn't have? Our
2844 callers don't check the value we return. */
366f009f 2845 return tdep->ppc_fp0_regnum + (num - 32);
18ed0c4e
JB		 2846 else if (77 <= num && num <= 108)
2847 return tdep->ppc_vr0_regnum + (num - 77);
9f744501
JB		 2848 else if (1200 <= num && num < 1200 + 32)
2849 return tdep->ppc_ev0_regnum + (num - 1200);
2850 else
2851 switch (num)
2852 {
2853 case 64:
2854 return tdep->ppc_mq_regnum;
2855 case 65:
2856 return tdep->ppc_lr_regnum;
2857 case 66:
2858 return tdep->ppc_ctr_regnum;
2859 case 76:
2860 return tdep->ppc_xer_regnum;
2861 case 109:
2862 return tdep->ppc_vrsave_regnum;
18ed0c4e
JB		 2863 case 110:
2864 return tdep->ppc_vrsave_regnum - 1; /* vscr */
867e2dc5 2865 case 111:
18ed0c4e 2866 return tdep->ppc_acc_regnum;
867e2dc5 2867 case 112:
18ed0c4e 2868 return tdep->ppc_spefscr_regnum;
9f744501
JB		 2869 default:
2870 return num;
2871 }
18ed0c4e 2872}
9f744501 2873
9f744501 2874
18ed0c4e
JB		 2875/* Convert a Dwarf 2 register number to a GDB register number. */
2876static int
d3f73121 2877rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
18ed0c4e 2878{
d3f73121 2879 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9f744501 2880
18ed0c4e
JB		 2881 if (0 <= num && num <= 31)
2882 return tdep->ppc_gp0_regnum + num;
2883 else if (32 <= num && num <= 63)
2884 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2885 specifies registers the architecture doesn't have? Our
2886 callers don't check the value we return. */
2887 return tdep->ppc_fp0_regnum + (num - 32);
2888 else if (1124 <= num && num < 1124 + 32)
2889 return tdep->ppc_vr0_regnum + (num - 1124);
2890 else if (1200 <= num && num < 1200 + 32)
2891 return tdep->ppc_ev0_regnum + (num - 1200);
2892 else
2893 switch (num)
2894 {
a489f789
AS		 2895 case 64:
2896 return tdep->ppc_cr_regnum;
18ed0c4e
JB		 2897 case 67:
2898 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2899 case 99:
2900 return tdep->ppc_acc_regnum;
2901 case 100:
2902 return tdep->ppc_mq_regnum;
2903 case 101:
2904 return tdep->ppc_xer_regnum;
2905 case 108:
2906 return tdep->ppc_lr_regnum;
2907 case 109:
2908 return tdep->ppc_ctr_regnum;
2909 case 356:
2910 return tdep->ppc_vrsave_regnum;
2911 case 612:
2912 return tdep->ppc_spefscr_regnum;
2913 default:
2914 return num;
2915 }
2188cbdd
EZ		 2916}
2917
4fc771b8
DJ		 2918/* Translate a .eh_frame register to DWARF register, or adjust a
2919 .debug_frame register. */
2920
2921static int
2922rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
2923{
2924 /* GCC releases before 3.4 use GCC internal register numbering in
2925 .debug_frame (and .debug_info, et cetera). The numbering is
2926 different from the standard SysV numbering for everything except
2927 for GPRs and FPRs. We can not detect this problem in most cases
2928 - to get accurate debug info for variables living in lr, ctr, v0,
2929 et cetera, use a newer version of GCC. But we must detect
2930 one important case - lr is in column 65 in .debug_frame output,
2931 instead of 108.
2932
2933 GCC 3.4, and the "hammer" branch, have a related problem. They
2934 record lr register saves in .debug_frame as 108, but still record
2935 the return column as 65. We fix that up too.
2936
2937 We can do this because 65 is assigned to fpsr, and GCC never
2938 generates debug info referring to it. To add support for
2939 handwritten debug info that restores fpsr, we would need to add a
2940 producer version check to this. */
2941 if (!eh_frame_p)
2942 {
2943 if (num == 65)
2944 return 108;
2945 else
2946 return num;
2947 }
2948
2949 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2950 internal register numbering; translate that to the standard DWARF2
2951 register numbering. */
2952 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */
2953 return num;
2954 else if (68 <= num && num <= 75) /* cr0-cr8 */
2955 return num - 68 + 86;
2956 else if (77 <= num && num <= 108) /* vr0-vr31 */
2957 return num - 77 + 1124;
2958 else
2959 switch (num)
2960 {
2961 case 64: /* mq */
2962 return 100;
2963 case 65: /* lr */
2964 return 108;
2965 case 66: /* ctr */
2966 return 109;
2967 case 76: /* xer */
2968 return 101;
2969 case 109: /* vrsave */
2970 return 356;
2971 case 110: /* vscr */
2972 return 67;
2973 case 111: /* spe_acc */
2974 return 99;
2975 case 112: /* spefscr */
2976 return 612;
2977 default:
2978 return num;
2979 }
2980}
c906108c 2981\f
c5aa993b 2982
7a78ae4e 2983/* Handling the various POWER/PowerPC variants. */
c906108c 2984
c906108c 2985/* Information about a particular processor variant. */
7a78ae4e 2986
c906108c 2987struct variant
c5aa993b
JM		 2988 {
2989 /* Name of this variant. */
2990 char *name;
c906108c 2991
c5aa993b
JM		 2992 /* English description of the variant. */
2993 char *description;
c906108c 2994
64366f1c 2995 /* bfd_arch_info.arch corresponding to variant. */
7a78ae4e
ND		 2996 enum bfd_architecture arch;
2997
64366f1c 2998 /* bfd_arch_info.mach corresponding to variant. */
7a78ae4e
ND		 2999 unsigned long mach;
3000
7cc46491
DJ		 3001 /* Target description for this variant. */
3002 struct target_desc **tdesc;
c5aa993b 3003 };
c906108c 3004
489461e2 3005static struct variant variants[] =
c906108c 3006{
7a78ae4e 3007 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
7284e1be 3008 bfd_mach_ppc, &tdesc_powerpc_altivec32},
7a78ae4e 3009 {"power", "POWER user-level", bfd_arch_rs6000,
7cc46491 3010 bfd_mach_rs6k, &tdesc_rs6000},
7a78ae4e 3011 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
7cc46491 3012 bfd_mach_ppc_403, &tdesc_powerpc_403},
4d09ffea
MS		 3013 {"405", "IBM PowerPC 405", bfd_arch_powerpc,
3014 bfd_mach_ppc_405, &tdesc_powerpc_405},
7a78ae4e 3015 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
7cc46491 3016 bfd_mach_ppc_601, &tdesc_powerpc_601},
7a78ae4e 3017 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
7cc46491 3018 bfd_mach_ppc_602, &tdesc_powerpc_602},
7a78ae4e 3019 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
7cc46491 3020 bfd_mach_ppc_603, &tdesc_powerpc_603},
7a78ae4e 3021 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
7cc46491 3022 604, &tdesc_powerpc_604},
7a78ae4e 3023 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
7cc46491 3024 bfd_mach_ppc_403gc, &tdesc_powerpc_403gc},
7a78ae4e 3025 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
7cc46491 3026 bfd_mach_ppc_505, &tdesc_powerpc_505},
7a78ae4e 3027 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
7cc46491 3028 bfd_mach_ppc_860, &tdesc_powerpc_860},
7a78ae4e 3029 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
7cc46491 3030 bfd_mach_ppc_750, &tdesc_powerpc_750},
1fcc0bb8 3031 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
7cc46491 3032 bfd_mach_ppc_7400, &tdesc_powerpc_7400},
c8001721 3033 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
7cc46491 3034 bfd_mach_ppc_e500, &tdesc_powerpc_e500},
7a78ae4e 3035
5d57ee30
KB		 3036 /* 64-bit */
3037 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
7284e1be 3038 bfd_mach_ppc64, &tdesc_powerpc_altivec64},
7a78ae4e 3039 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
7cc46491 3040 bfd_mach_ppc_620, &tdesc_powerpc_64},
5d57ee30 3041 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
7cc46491 3042 bfd_mach_ppc_630, &tdesc_powerpc_64},
7a78ae4e 3043 {"a35", "PowerPC A35", bfd_arch_powerpc,
7cc46491 3044 bfd_mach_ppc_a35, &tdesc_powerpc_64},
5d57ee30 3045 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
7cc46491 3046 bfd_mach_ppc_rs64ii, &tdesc_powerpc_64},
5d57ee30 3047 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
7cc46491 3048 bfd_mach_ppc_rs64iii, &tdesc_powerpc_64},
5d57ee30 3049
64366f1c 3050 /* FIXME: I haven't checked the register sets of the following. */
7a78ae4e 3051 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
7cc46491 3052 bfd_mach_rs6k_rs1, &tdesc_rs6000},
7a78ae4e 3053 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
7cc46491 3054 bfd_mach_rs6k_rsc, &tdesc_rs6000},
7a78ae4e 3055 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
7cc46491 3056 bfd_mach_rs6k_rs2, &tdesc_rs6000},
7a78ae4e 3057
7cc46491 3058 {0, 0, 0, 0, 0}
c906108c
SS		 3059};
3060
7a78ae4e 3061/* Return the variant corresponding to architecture ARCH and machine number
64366f1c 3062 MACH. If no such variant exists, return null. */
c906108c 3063
7a78ae4e
ND		 3064static const struct variant *
3065find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
c906108c 3066{
7a78ae4e 3067 const struct variant *v;
c5aa993b 3068
7a78ae4e
ND		 3069 for (v = variants; v->name; v++)
3070 if (arch == v->arch && mach == v->mach)
3071 return v;
c906108c 3072
7a78ae4e 3073 return NULL;
c906108c 3074}
9364a0ef
EZ		 3075
3076static int
3077gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
3078{
ee4f0f76 3079 if (!info->disassembler_options)
e52d5016
NF		 3080 {
3081 /* When debugging E500 binaries and disassembling code containing
3082 E500-specific (SPE) instructions, one sometimes sees AltiVec
3083 instructions instead. The opcode spaces for SPE instructions
3084 and AltiVec instructions overlap, and specifiying the "any" cpu
3085 looks for AltiVec instructions first. If we know we're
3086 debugging an E500 binary, however, we can specify the "e500x2"
3087 cpu and get much more sane disassembly output. */
3088 if (info->mach == bfd_mach_ppc_e500)
3089 info->disassembler_options = "e500x2";
3090 else
3091 info->disassembler_options = "any";
3092 }
ee4f0f76 3093
40887e1a 3094 if (info->endian == BFD_ENDIAN_BIG)
9364a0ef
EZ		 3095 return print_insn_big_powerpc (memaddr, info);
3096 else
3097 return print_insn_little_powerpc (memaddr, info);
3098}
7a78ae4e 3099\f
61a65099
KB		 3100static CORE_ADDR
3101rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
3102{
3e8c568d 3103 return frame_unwind_register_unsigned (next_frame,
8b164abb 3104 gdbarch_pc_regnum (gdbarch));
61a65099
KB		 3105}
3106
3107static struct frame_id
1af5d7ce 3108rs6000_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
61a65099 3109{
1af5d7ce
UW		 3110 return frame_id_build (get_frame_register_unsigned
3111 (this_frame, gdbarch_sp_regnum (gdbarch)),
3112 get_frame_pc (this_frame));
61a65099
KB		 3113}
3114
3115struct rs6000_frame_cache
3116{
3117 CORE_ADDR base;
3118 CORE_ADDR initial_sp;
3119 struct trad_frame_saved_reg *saved_regs;
3120};
3121
3122static struct rs6000_frame_cache *
1af5d7ce 3123rs6000_frame_cache (struct frame_info *this_frame, void **this_cache)
61a65099
KB		 3124{
3125 struct rs6000_frame_cache *cache;
1af5d7ce 3126 struct gdbarch *gdbarch = get_frame_arch (this_frame);
61a65099 3127 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 3128 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
61a65099
KB		 3129 struct rs6000_framedata fdata;
3130 int wordsize = tdep->wordsize;
e10b1c4c 3131 CORE_ADDR func, pc;
61a65099
KB		 3132
3133 if ((*this_cache) != NULL)
3134 return (*this_cache);
3135 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
3136 (*this_cache) = cache;
1af5d7ce 3137 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
61a65099 3138
1af5d7ce
UW		 3139 func = get_frame_func (this_frame);
3140 pc = get_frame_pc (this_frame);
be8626e0 3141 skip_prologue (gdbarch, func, pc, &fdata);
e10b1c4c
DJ		 3142
3143 /* Figure out the parent's stack pointer. */
3144
3145 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3146 address of the current frame. Things might be easier if the
3147 ->frame pointed to the outer-most address of the frame. In
3148 the mean time, the address of the prev frame is used as the
3149 base address of this frame. */
1af5d7ce
UW		 3150 cache->base = get_frame_register_unsigned
3151 (this_frame, gdbarch_sp_regnum (gdbarch));
e10b1c4c
DJ		 3152
3153 /* If the function appears to be frameless, check a couple of likely
3154 indicators that we have simply failed to find the frame setup.
3155 Two common cases of this are missing symbols (i.e.
ef02daa9 3156 get_frame_func returns the wrong address or 0), and assembly
e10b1c4c
DJ		 3157 stubs which have a fast exit path but set up a frame on the slow
3158 path.
3159
3160 If the LR appears to return to this function, then presume that
3161 we have an ABI compliant frame that we failed to find. */
3162 if (fdata.frameless && fdata.lr_offset == 0)
61a65099 3163 {
e10b1c4c
DJ		 3164 CORE_ADDR saved_lr;
3165 int make_frame = 0;
3166
1af5d7ce 3167 saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum);
e10b1c4c
DJ		 3168 if (func == 0 && saved_lr == pc)
3169 make_frame = 1;
3170 else if (func != 0)
3171 {
3172 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
3173 if (func == saved_func)
3174 make_frame = 1;
3175 }
3176
3177 if (make_frame)
3178 {
3179 fdata.frameless = 0;
de6a76fd 3180 fdata.lr_offset = tdep->lr_frame_offset;
e10b1c4c 3181 }
61a65099 3182 }
e10b1c4c
DJ		 3183
3184 if (!fdata.frameless)
3185 /* Frameless really means stackless. */
e17a4113
UW		 3186 cache->base
3187 = read_memory_unsigned_integer (cache->base, wordsize, byte_order);
e10b1c4c 3188
3e8c568d 3189 trad_frame_set_value (cache->saved_regs,
8b164abb 3190 gdbarch_sp_regnum (gdbarch), cache->base);
61a65099
KB		 3191
3192 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3193 All fpr's from saved_fpr to fp31 are saved. */
3194
3195 if (fdata.saved_fpr >= 0)
3196 {
3197 int i;
3198 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
383f0f5b
JB		 3199
3200 /* If skip_prologue says floating-point registers were saved,
3201 but the current architecture has no floating-point registers,
3202 then that's strange. But we have no indices to even record
3203 the addresses under, so we just ignore it. */
3204 if (ppc_floating_point_unit_p (gdbarch))
063715bf 3205 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
383f0f5b
JB		 3206 {
3207 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3208 fpr_addr += 8;
3209 }
61a65099
KB		 3210 }
3211
3212 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
46a9b8ed
DJ		 3213 All gpr's from saved_gpr to gpr31 are saved (except during the
3214 prologue). */
61a65099
KB		 3215
3216 if (fdata.saved_gpr >= 0)
3217 {
3218 int i;
3219 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
063715bf 3220 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
61a65099 3221 {
46a9b8ed
DJ		 3222 if (fdata.gpr_mask & (1U << i))
3223 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
61a65099
KB		 3224 gpr_addr += wordsize;
3225 }
3226 }
3227
3228 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3229 All vr's from saved_vr to vr31 are saved. */
3230 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3231 {
3232 if (fdata.saved_vr >= 0)
3233 {
3234 int i;
3235 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3236 for (i = fdata.saved_vr; i < 32; i++)
3237 {
3238 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3239 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3240 }
3241 }
3242 }
3243
3244 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
0df8b418 3245 All vr's from saved_ev to ev31 are saved. ????? */
5a9e69ba 3246 if (tdep->ppc_ev0_regnum != -1)
61a65099
KB		 3247 {
3248 if (fdata.saved_ev >= 0)
3249 {
3250 int i;
3251 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
063715bf 3252 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
61a65099
KB		 3253 {
3254 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3255 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
3256 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3257 }
3258 }
3259 }
3260
3261 /* If != 0, fdata.cr_offset is the offset from the frame that
3262 holds the CR. */
3263 if (fdata.cr_offset != 0)
0df8b418
MS		 3264 cache->saved_regs[tdep->ppc_cr_regnum].addr
3265 = cache->base + fdata.cr_offset;
61a65099
KB		 3266
3267 /* If != 0, fdata.lr_offset is the offset from the frame that
3268 holds the LR. */
3269 if (fdata.lr_offset != 0)
0df8b418
MS		 3270 cache->saved_regs[tdep->ppc_lr_regnum].addr
3271 = cache->base + fdata.lr_offset;
46a9b8ed
DJ		 3272 else if (fdata.lr_register != -1)
3273 cache->saved_regs[tdep->ppc_lr_regnum].realreg = fdata.lr_register;
61a65099 3274 /* The PC is found in the link register. */
8b164abb 3275 cache->saved_regs[gdbarch_pc_regnum (gdbarch)] =
3e8c568d 3276 cache->saved_regs[tdep->ppc_lr_regnum];
61a65099
KB		 3277
3278 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3279 holds the VRSAVE. */
3280 if (fdata.vrsave_offset != 0)
0df8b418
MS		 3281 cache->saved_regs[tdep->ppc_vrsave_regnum].addr
3282 = cache->base + fdata.vrsave_offset;
61a65099
KB		 3283
3284 if (fdata.alloca_reg < 0)
3285 /* If no alloca register used, then fi->frame is the value of the
3286 %sp for this frame, and it is good enough. */
1af5d7ce
UW		 3287 cache->initial_sp
3288 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
61a65099 3289 else
1af5d7ce
UW		 3290 cache->initial_sp
3291 = get_frame_register_unsigned (this_frame, fdata.alloca_reg);
61a65099
KB		 3292
3293 return cache;
3294}
3295
3296static void
1af5d7ce 3297rs6000_frame_this_id (struct frame_info *this_frame, void **this_cache,
61a65099
KB		 3298 struct frame_id *this_id)
3299{
1af5d7ce 3300 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099 3301 this_cache);
5b197912
UW		 3302 /* This marks the outermost frame. */
3303 if (info->base == 0)
3304 return;
3305
1af5d7ce 3306 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
61a65099
KB		 3307}
3308
1af5d7ce
UW		 3309static struct value *
3310rs6000_frame_prev_register (struct frame_info *this_frame,
3311 void **this_cache, int regnum)
61a65099 3312{
1af5d7ce 3313 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099 3314 this_cache);
1af5d7ce 3315 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
61a65099
KB		 3316}
3317
3318static const struct frame_unwind rs6000_frame_unwind =
3319{
3320 NORMAL_FRAME,
8fbca658 3321 default_frame_unwind_stop_reason,
61a65099 3322 rs6000_frame_this_id,
1af5d7ce
UW		 3323 rs6000_frame_prev_register,
3324 NULL,
3325 default_frame_sniffer
61a65099 3326};
61a65099
KB		 3327\f
3328
3329static CORE_ADDR
1af5d7ce 3330rs6000_frame_base_address (struct frame_info *this_frame, void **this_cache)
61a65099 3331{
1af5d7ce 3332 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099
KB		 3333 this_cache);
3334 return info->initial_sp;
3335}
3336
3337static const struct frame_base rs6000_frame_base = {
3338 &rs6000_frame_unwind,
3339 rs6000_frame_base_address,
3340 rs6000_frame_base_address,
3341 rs6000_frame_base_address
3342};
3343
3344static const struct frame_base *
1af5d7ce 3345rs6000_frame_base_sniffer (struct frame_info *this_frame)
61a65099
KB		 3346{
3347 return &rs6000_frame_base;
3348}
3349
9274a07c
LM		 3350/* DWARF-2 frame support. Used to handle the detection of
3351 clobbered registers during function calls. */
3352
3353static void
3354ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3355 struct dwarf2_frame_state_reg *reg,
4a4e5149 3356 struct frame_info *this_frame)
9274a07c
LM		 3357{
3358 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3359
3360 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3361 non-volatile registers. We will use the same code for both. */
3362
3363 /* Call-saved GP registers. */
3364 if ((regnum >= tdep->ppc_gp0_regnum + 14
3365 && regnum <= tdep->ppc_gp0_regnum + 31)
3366 || (regnum == tdep->ppc_gp0_regnum + 1))
3367 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3368
3369 /* Call-clobbered GP registers. */
3370 if ((regnum >= tdep->ppc_gp0_regnum + 3
3371 && regnum <= tdep->ppc_gp0_regnum + 12)
3372 || (regnum == tdep->ppc_gp0_regnum))
3373 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3374
3375 /* Deal with FP registers, if supported. */
3376 if (tdep->ppc_fp0_regnum >= 0)
3377 {
3378 /* Call-saved FP registers. */
3379 if ((regnum >= tdep->ppc_fp0_regnum + 14
3380 && regnum <= tdep->ppc_fp0_regnum + 31))
3381 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3382
3383 /* Call-clobbered FP registers. */
3384 if ((regnum >= tdep->ppc_fp0_regnum
3385 && regnum <= tdep->ppc_fp0_regnum + 13))
3386 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3387 }
3388
3389 /* Deal with ALTIVEC registers, if supported. */
3390 if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0)
3391 {
3392 /* Call-saved Altivec registers. */
3393 if ((regnum >= tdep->ppc_vr0_regnum + 20
3394 && regnum <= tdep->ppc_vr0_regnum + 31)
3395 || regnum == tdep->ppc_vrsave_regnum)
3396 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3397
3398 /* Call-clobbered Altivec registers. */
3399 if ((regnum >= tdep->ppc_vr0_regnum
3400 && regnum <= tdep->ppc_vr0_regnum + 19))
3401 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3402 }
3403
3404 /* Handle PC register and Stack Pointer correctly. */
40a6adc1 3405 if (regnum == gdbarch_pc_regnum (gdbarch))
9274a07c 3406 reg->how = DWARF2_FRAME_REG_RA;
40a6adc1 3407 else if (regnum == gdbarch_sp_regnum (gdbarch))
9274a07c
LM		 3408 reg->how = DWARF2_FRAME_REG_CFA;
3409}
3410
3411
74af9197
NF		 3412/* Return true if a .gnu_attributes section exists in BFD and it
3413 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3414 section exists in BFD and it indicates that SPE extensions are in
3415 use. Check the .gnu.attributes section first, as the binary might be
3416 compiled for SPE, but not actually using SPE instructions. */
3417
3418static int
3419bfd_uses_spe_extensions (bfd *abfd)
3420{
3421 asection *sect;
3422 gdb_byte *contents = NULL;
3423 bfd_size_type size;
3424 gdb_byte *ptr;
3425 int success = 0;
3426 int vector_abi;
3427
3428 if (!abfd)
3429 return 0;
3430
50a99728 3431#ifdef HAVE_ELF
74af9197
NF		 3432 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3433 could be using the SPE vector abi without actually using any spe
3434 bits whatsoever. But it's close enough for now. */
3435 vector_abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_GNU,
3436 Tag_GNU_Power_ABI_Vector);
3437 if (vector_abi == 3)
3438 return 1;
50a99728 3439#endif
74af9197
NF		 3440
3441 sect = bfd_get_section_by_name (abfd, ".PPC.EMB.apuinfo");
3442 if (!sect)
3443 return 0;
3444
3445 size = bfd_get_section_size (sect);
3446 contents = xmalloc (size);
3447 if (!bfd_get_section_contents (abfd, sect, contents, 0, size))
3448 {
3449 xfree (contents);
3450 return 0;
3451 }
3452
3453 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3454
3455 struct {
3456 uint32 name_len;
3457 uint32 data_len;
3458 uint32 type;
3459 char name[name_len rounded up to 4-byte alignment];
3460 char data[data_len];
3461 };
3462
3463 Technically, there's only supposed to be one such structure in a
3464 given apuinfo section, but the linker is not always vigilant about
3465 merging apuinfo sections from input files. Just go ahead and parse
3466 them all, exiting early when we discover the binary uses SPE
3467 insns.
3468
3469 It's not specified in what endianness the information in this
3470 section is stored. Assume that it's the endianness of the BFD. */
3471 ptr = contents;
3472 while (1)
3473 {
3474 unsigned int name_len;
3475 unsigned int data_len;
3476 unsigned int type;
3477
3478 /* If we can't read the first three fields, we're done. */
3479 if (size < 12)
3480 break;
3481
3482 name_len = bfd_get_32 (abfd, ptr);
3483 name_len = (name_len + 3) & ~3U; /* Round to 4 bytes. */
3484 data_len = bfd_get_32 (abfd, ptr + 4);
3485 type = bfd_get_32 (abfd, ptr + 8);
3486 ptr += 12;
3487
3488 /* The name must be "APUinfo\0". */
3489 if (name_len != 8
3490 && strcmp ((const char *) ptr, "APUinfo") != 0)
3491 break;
3492 ptr += name_len;
3493
3494 /* The type must be 2. */
3495 if (type != 2)
3496 break;
3497
3498 /* The data is stored as a series of uint32. The upper half of
3499 each uint32 indicates the particular APU used and the lower
3500 half indicates the revision of that APU. We just care about
3501 the upper half. */
3502
3503 /* Not 4-byte quantities. */
3504 if (data_len & 3U)
3505 break;
3506
3507 while (data_len)
3508 {
3509 unsigned int apuinfo = bfd_get_32 (abfd, ptr);
3510 unsigned int apu = apuinfo >> 16;
3511 ptr += 4;
3512 data_len -= 4;
3513
3514 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3515 either. */
3516 if (apu == 0x100 || apu == 0x101)
3517 {
3518 success = 1;
3519 data_len = 0;
3520 }
3521 }
3522
3523 if (success)
3524 break;
3525 }
3526
3527 xfree (contents);
3528 return success;
3529}
3530
7a78ae4e
ND		 3531/* Initialize the current architecture based on INFO. If possible, re-use an
3532 architecture from ARCHES, which is a list of architectures already created
3533 during this debugging session.
c906108c 3534
7a78ae4e 3535 Called e.g. at program startup, when reading a core file, and when reading
64366f1c 3536 a binary file. */
c906108c 3537
7a78ae4e
ND		 3538static struct gdbarch *
3539rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3540{
3541 struct gdbarch *gdbarch;
3542 struct gdbarch_tdep *tdep;
7cc46491 3543 int wordsize, from_xcoff_exec, from_elf_exec;
7a78ae4e
ND		 3544 enum bfd_architecture arch;
3545 unsigned long mach;
3546 bfd abfd;
5bf1c677 3547 asection *sect;
55eddb0f
DJ		 3548 enum auto_boolean soft_float_flag = powerpc_soft_float_global;
3549 int soft_float;
3550 enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
604c2f83
LM		 3551 int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0,
3552 have_vsx = 0;
7cc46491
DJ		 3553 int tdesc_wordsize = -1;
3554 const struct target_desc *tdesc = info.target_desc;
3555 struct tdesc_arch_data *tdesc_data = NULL;
f949c649 3556 int num_pseudoregs = 0;
604c2f83 3557 int cur_reg;
7a78ae4e 3558
f4d9bade
UW		 3559 /* INFO may refer to a binary that is not of the PowerPC architecture,
3560 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
3561 In this case, we must not attempt to infer properties of the (PowerPC
3562 side) of the target system from properties of that executable. Trust
3563 the target description instead. */
3564 if (info.abfd
3565 && bfd_get_arch (info.abfd) != bfd_arch_powerpc
3566 && bfd_get_arch (info.abfd) != bfd_arch_rs6000)
3567 info.abfd = NULL;
3568
9aa1e687 3569 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
7a78ae4e
ND		 3570 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3571
9aa1e687
KB		 3572 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3573 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3574
e712c1cf 3575 /* Check word size. If INFO is from a binary file, infer it from
64366f1c 3576 that, else choose a likely default. */
9aa1e687 3577 if (from_xcoff_exec)
c906108c 3578 {
11ed25ac 3579 if (bfd_xcoff_is_xcoff64 (info.abfd))
7a78ae4e
ND		 3580 wordsize = 8;
3581 else
3582 wordsize = 4;
c906108c 3583 }
9aa1e687
KB		 3584 else if (from_elf_exec)
3585 {
3586 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3587 wordsize = 8;
3588 else
3589 wordsize = 4;
3590 }
7cc46491
DJ		 3591 else if (tdesc_has_registers (tdesc))
3592 wordsize = -1;
c906108c 3593 else
7a78ae4e 3594 {
27b15785
KB		 3595 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3596 wordsize = info.bfd_arch_info->bits_per_word /
3597 info.bfd_arch_info->bits_per_byte;
3598 else
3599 wordsize = 4;
7a78ae4e 3600 }
c906108c 3601
475bbd17
JB		 3602 /* Get the architecture and machine from the BFD. */
3603 arch = info.bfd_arch_info->arch;
3604 mach = info.bfd_arch_info->mach;
5bf1c677
EZ		 3605
3606 /* For e500 executables, the apuinfo section is of help here. Such
3607 section contains the identifier and revision number of each
3608 Application-specific Processing Unit that is present on the
3609 chip. The content of the section is determined by the assembler
3610 which looks at each instruction and determines which unit (and
74af9197
NF		 3611 which version of it) can execute it. Grovel through the section
3612 looking for relevant e500 APUs. */
5bf1c677 3613
74af9197 3614 if (bfd_uses_spe_extensions (info.abfd))
5bf1c677 3615 {
74af9197
NF		 3616 arch = info.bfd_arch_info->arch;
3617 mach = bfd_mach_ppc_e500;
3618 bfd_default_set_arch_mach (&abfd, arch, mach);
3619 info.bfd_arch_info = bfd_get_arch_info (&abfd);
5bf1c677
EZ		 3620 }
3621
7cc46491
DJ		 3622 /* Find a default target description which describes our register
3623 layout, if we do not already have one. */
3624 if (! tdesc_has_registers (tdesc))
3625 {
3626 const struct variant *v;
3627
3628 /* Choose variant. */
3629 v = find_variant_by_arch (arch, mach);
3630 if (!v)
3631 return NULL;
3632
3633 tdesc = *v->tdesc;
3634 }
3635
3636 gdb_assert (tdesc_has_registers (tdesc));
3637
3638 /* Check any target description for validity. */
3639 if (tdesc_has_registers (tdesc))
3640 {
3641 static const char *const gprs[] = {
3642 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3643 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3644 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3645 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3646 };
3647 static const char *const segment_regs[] = {
3648 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
3649 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
3650 };
3651 const struct tdesc_feature *feature;
3652 int i, valid_p;
3653 static const char *const msr_names[] = { "msr", "ps" };
3654 static const char *const cr_names[] = { "cr", "cnd" };
3655 static const char *const ctr_names[] = { "ctr", "cnt" };
3656
3657 feature = tdesc_find_feature (tdesc,
3658 "org.gnu.gdb.power.core");
3659 if (feature == NULL)
3660 return NULL;
3661
3662 tdesc_data = tdesc_data_alloc ();
3663
3664 valid_p = 1;
3665 for (i = 0; i < ppc_num_gprs; i++)
3666 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]);
3667 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM,
3668 "pc");
3669 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM,
3670 "lr");
3671 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM,
3672 "xer");
3673
3674 /* Allow alternate names for these registers, to accomodate GDB's
3675 historic naming. */
3676 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3677 PPC_MSR_REGNUM, msr_names);
3678 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3679 PPC_CR_REGNUM, cr_names);
3680 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3681 PPC_CTR_REGNUM, ctr_names);
3682
3683 if (!valid_p)
3684 {
3685 tdesc_data_cleanup (tdesc_data);
3686 return NULL;
3687 }
3688
3689 have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM,
3690 "mq");
3691
3692 tdesc_wordsize = tdesc_register_size (feature, "pc") / 8;
3693 if (wordsize == -1)
3694 wordsize = tdesc_wordsize;
3695
3696 feature = tdesc_find_feature (tdesc,
3697 "org.gnu.gdb.power.fpu");
3698 if (feature != NULL)
3699 {
3700 static const char *const fprs[] = {
3701 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
3702 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
3703 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
3704 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
3705 };
3706 valid_p = 1;
3707 for (i = 0; i < ppc_num_fprs; i++)
3708 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3709 PPC_F0_REGNUM + i, fprs[i]);
3710 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3711 PPC_FPSCR_REGNUM, "fpscr");
3712
3713 if (!valid_p)
3714 {
3715 tdesc_data_cleanup (tdesc_data);
3716 return NULL;
3717 }
3718 have_fpu = 1;
3719 }
3720 else
3721 have_fpu = 0;
3722
f949c649
TJB		 3723 /* The DFP pseudo-registers will be available when there are floating
3724 point registers. */
3725 have_dfp = have_fpu;
3726
7cc46491
DJ		 3727 feature = tdesc_find_feature (tdesc,
3728 "org.gnu.gdb.power.altivec");
3729 if (feature != NULL)
3730 {
3731 static const char *const vector_regs[] = {
3732 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
3733 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
3734 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
3735 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
3736 };
3737
3738 valid_p = 1;
3739 for (i = 0; i < ppc_num_gprs; i++)
3740 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3741 PPC_VR0_REGNUM + i,
3742 vector_regs[i]);
3743 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3744 PPC_VSCR_REGNUM, "vscr");
3745 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3746 PPC_VRSAVE_REGNUM, "vrsave");
3747
3748 if (have_spe || !valid_p)
3749 {
3750 tdesc_data_cleanup (tdesc_data);
3751 return NULL;
3752 }
3753 have_altivec = 1;
3754 }
3755 else
3756 have_altivec = 0;
3757
604c2f83
LM		 3758 /* Check for POWER7 VSX registers support. */
3759 feature = tdesc_find_feature (tdesc,
3760 "org.gnu.gdb.power.vsx");
3761
3762 if (feature != NULL)
3763 {
3764 static const char *const vsx_regs[] = {
3765 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
3766 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
3767 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
3768 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
3769 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
3770 "vs30h", "vs31h"
3771 };
3772
3773 valid_p = 1;
3774
3775 for (i = 0; i < ppc_num_vshrs; i++)
3776 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3777 PPC_VSR0_UPPER_REGNUM + i,
3778 vsx_regs[i]);
3779 if (!valid_p)
3780 {
3781 tdesc_data_cleanup (tdesc_data);
3782 return NULL;
3783 }
3784
3785 have_vsx = 1;
3786 }
3787 else
3788 have_vsx = 0;
3789
7cc46491
DJ		 3790 /* On machines supporting the SPE APU, the general-purpose registers
3791 are 64 bits long. There are SIMD vector instructions to treat them
3792 as pairs of floats, but the rest of the instruction set treats them
3793 as 32-bit registers, and only operates on their lower halves.
3794
3795 In the GDB regcache, we treat their high and low halves as separate
3796 registers. The low halves we present as the general-purpose
3797 registers, and then we have pseudo-registers that stitch together
3798 the upper and lower halves and present them as pseudo-registers.
3799
3800 Thus, the target description is expected to supply the upper
3801 halves separately. */
3802
3803 feature = tdesc_find_feature (tdesc,
3804 "org.gnu.gdb.power.spe");
3805 if (feature != NULL)
3806 {
3807 static const char *const upper_spe[] = {
3808 "ev0h", "ev1h", "ev2h", "ev3h",
3809 "ev4h", "ev5h", "ev6h", "ev7h",
3810 "ev8h", "ev9h", "ev10h", "ev11h",
3811 "ev12h", "ev13h", "ev14h", "ev15h",
3812 "ev16h", "ev17h", "ev18h", "ev19h",
3813 "ev20h", "ev21h", "ev22h", "ev23h",
3814 "ev24h", "ev25h", "ev26h", "ev27h",
3815 "ev28h", "ev29h", "ev30h", "ev31h"
3816 };
3817
3818 valid_p = 1;
3819 for (i = 0; i < ppc_num_gprs; i++)
3820 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3821 PPC_SPE_UPPER_GP0_REGNUM + i,
3822 upper_spe[i]);
3823 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3824 PPC_SPE_ACC_REGNUM, "acc");
3825 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3826 PPC_SPE_FSCR_REGNUM, "spefscr");
3827
3828 if (have_mq || have_fpu || !valid_p)
3829 {
3830 tdesc_data_cleanup (tdesc_data);
3831 return NULL;
3832 }
3833 have_spe = 1;
3834 }
3835 else
3836 have_spe = 0;
3837 }
3838
3839 /* If we have a 64-bit binary on a 32-bit target, complain. Also
3840 complain for a 32-bit binary on a 64-bit target; we do not yet
3841 support that. For instance, the 32-bit ABI routines expect
3842 32-bit GPRs.
3843
3844 As long as there isn't an explicit target description, we'll
3845 choose one based on the BFD architecture and get a word size
3846 matching the binary (probably powerpc:common or
3847 powerpc:common64). So there is only trouble if a 64-bit target
3848 supplies a 64-bit description while debugging a 32-bit
3849 binary. */
3850 if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize)
3851 {
3852 tdesc_data_cleanup (tdesc_data);
3853 return NULL;
3854 }
3855
55eddb0f
DJ		 3856#ifdef HAVE_ELF
3857 if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec)
3858 {
3859 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3860 Tag_GNU_Power_ABI_FP))
3861 {
3862 case 1:
3863 soft_float_flag = AUTO_BOOLEAN_FALSE;
3864 break;
3865 case 2:
3866 soft_float_flag = AUTO_BOOLEAN_TRUE;
3867 break;
3868 default:
3869 break;
3870 }
3871 }
3872
3873 if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec)
3874 {
3875 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3876 Tag_GNU_Power_ABI_Vector))
3877 {
3878 case 1:
3879 vector_abi = POWERPC_VEC_GENERIC;
3880 break;
3881 case 2:
3882 vector_abi = POWERPC_VEC_ALTIVEC;
3883 break;
3884 case 3:
3885 vector_abi = POWERPC_VEC_SPE;
3886 break;
3887 default:
3888 break;
3889 }
3890 }
3891#endif
3892
3893 if (soft_float_flag == AUTO_BOOLEAN_TRUE)
3894 soft_float = 1;
3895 else if (soft_float_flag == AUTO_BOOLEAN_FALSE)
3896 soft_float = 0;
3897 else
3898 soft_float = !have_fpu;
3899
3900 /* If we have a hard float binary or setting but no floating point
3901 registers, downgrade to soft float anyway. We're still somewhat
3902 useful in this scenario. */
3903 if (!soft_float && !have_fpu)
3904 soft_float = 1;
3905
3906 /* Similarly for vector registers. */
3907 if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec)
3908 vector_abi = POWERPC_VEC_GENERIC;
3909
3910 if (vector_abi == POWERPC_VEC_SPE && !have_spe)
3911 vector_abi = POWERPC_VEC_GENERIC;
3912
3913 if (vector_abi == POWERPC_VEC_AUTO)
3914 {
3915 if (have_altivec)
3916 vector_abi = POWERPC_VEC_ALTIVEC;
3917 else if (have_spe)
3918 vector_abi = POWERPC_VEC_SPE;
3919 else
3920 vector_abi = POWERPC_VEC_GENERIC;
3921 }
3922
3923 /* Do not limit the vector ABI based on available hardware, since we
3924 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
3925
7cc46491
DJ		 3926 /* Find a candidate among extant architectures. */
3927 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3928 arches != NULL;
3929 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3930 {
3931 /* Word size in the various PowerPC bfd_arch_info structs isn't
3932 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3933 separate word size check. */
3934 tdep = gdbarch_tdep (arches->gdbarch);
55eddb0f
DJ		 3935 if (tdep && tdep->soft_float != soft_float)
3936 continue;
3937 if (tdep && tdep->vector_abi != vector_abi)
3938 continue;
7cc46491
DJ		 3939 if (tdep && tdep->wordsize == wordsize)
3940 {
3941 if (tdesc_data != NULL)
3942 tdesc_data_cleanup (tdesc_data);
3943 return arches->gdbarch;
3944 }
3945 }
3946
3947 /* None found, create a new architecture from INFO, whose bfd_arch_info
3948 validity depends on the source:
3949 - executable useless
3950 - rs6000_host_arch() good
3951 - core file good
3952 - "set arch" trust blindly
3953 - GDB startup useless but harmless */
3954
3955 tdep = XCALLOC (1, struct gdbarch_tdep);
3956 tdep->wordsize = wordsize;
55eddb0f
DJ		 3957 tdep->soft_float = soft_float;
3958 tdep->vector_abi = vector_abi;
7cc46491 3959
7a78ae4e 3960 gdbarch = gdbarch_alloc (&info, tdep);
7a78ae4e 3961
7cc46491
DJ		 3962 tdep->ppc_gp0_regnum = PPC_R0_REGNUM;
3963 tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2;
3964 tdep->ppc_ps_regnum = PPC_MSR_REGNUM;
3965 tdep->ppc_cr_regnum = PPC_CR_REGNUM;
3966 tdep->ppc_lr_regnum = PPC_LR_REGNUM;
3967 tdep->ppc_ctr_regnum = PPC_CTR_REGNUM;
3968 tdep->ppc_xer_regnum = PPC_XER_REGNUM;
3969 tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1;
3970
3971 tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1;
3972 tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1;
604c2f83 3973 tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1;
7cc46491
DJ		 3974 tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1;
3975 tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1;
3976 tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1;
3977 tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1;
3978 tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
3979
3980 set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
3981 set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3982 set_gdbarch_deprecated_fp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3983 set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum);
9f643768 3984 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
7cc46491
DJ		 3985
3986 /* The XML specification for PowerPC sensibly calls the MSR "msr".
3987 GDB traditionally called it "ps", though, so let GDB add an
3988 alias. */
3989 set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum);
3990
4a7622d1 3991 if (wordsize == 8)
05580c65 3992 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
afd48b75 3993 else
4a7622d1 3994 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
c8001721 3995
baffbae0
JB		 3996 /* Set lr_frame_offset. */
3997 if (wordsize == 8)
3998 tdep->lr_frame_offset = 16;
baffbae0 3999 else
4a7622d1 4000 tdep->lr_frame_offset = 4;
baffbae0 4001
604c2f83 4002 if (have_spe || have_dfp || have_vsx)
7cc46491 4003 {
f949c649 4004 set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read);
0df8b418
MS		 4005 set_gdbarch_pseudo_register_write (gdbarch,
4006 rs6000_pseudo_register_write);
7cc46491 4007 }
1fcc0bb8 4008
e0d24f8d
WZ		 4009 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
4010
56a6dfb9 4011 /* Select instruction printer. */
708ff411 4012 if (arch == bfd_arch_rs6000)
9364a0ef 4013 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
56a6dfb9 4014 else
9364a0ef 4015 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
7495d1dc 4016
5a9e69ba 4017 set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS);
f949c649
TJB		 4018
4019 if (have_spe)
4020 num_pseudoregs += 32;
4021 if (have_dfp)
4022 num_pseudoregs += 16;
604c2f83
LM		 4023 if (have_vsx)
4024 /* Include both VSX and Extended FP registers. */
4025 num_pseudoregs += 96;
f949c649
TJB		 4026
4027 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs);
7a78ae4e
ND		 4028
4029 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
4030 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
4031 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4032 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
4033 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4034 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4035 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4a7622d1 4036 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
4e409299 4037 set_gdbarch_char_signed (gdbarch, 0);
7a78ae4e 4038
11269d7e 4039 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
4a7622d1 4040 if (wordsize == 8)
8b148df9
AC		 4041 /* PPC64 SYSV. */
4042 set_gdbarch_frame_red_zone_size (gdbarch, 288);
7a78ae4e 4043
691d145a
JB		 4044 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
4045 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
4046 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
4047
18ed0c4e
JB		 4048 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
4049 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
d217aaed 4050
4a7622d1 4051 if (wordsize == 4)
77b2b6d4 4052 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
4a7622d1 4053 else if (wordsize == 8)
8be9034a 4054 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
7a78ae4e 4055
7a78ae4e 4056 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
0d1243d9 4057 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
8ab3d180 4058 set_gdbarch_skip_main_prologue (gdbarch, rs6000_skip_main_prologue);
0d1243d9 4059
7a78ae4e 4060 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
7a78ae4e
ND		 4061 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
4062
203c3895 4063 /* The value of symbols of type N_SO and N_FUN maybe null when
0df8b418 4064 it shouldn't be. */
203c3895
UW		 4065 set_gdbarch_sofun_address_maybe_missing (gdbarch, 1);
4066
ce5eab59 4067 /* Handles single stepping of atomic sequences. */
4a7622d1 4068 set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence);
ce5eab59 4069
0df8b418 4070 /* Not sure on this. FIXMEmgo */
7a78ae4e
ND		 4071 set_gdbarch_frame_args_skip (gdbarch, 8);
4072
143985b7
AF		 4073 /* Helpers for function argument information. */
4074 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
4075
6f7f3f0d
UW		 4076 /* Trampoline. */
4077 set_gdbarch_in_solib_return_trampoline
4078 (gdbarch, rs6000_in_solib_return_trampoline);
4079 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code);
4080
4fc771b8 4081 /* Hook in the DWARF CFI frame unwinder. */
1af5d7ce 4082 dwarf2_append_unwinders (gdbarch);
4fc771b8
DJ		 4083 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum);
4084
9274a07c
LM		 4085 /* Frame handling. */
4086 dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg);
4087
2454a024
UW		 4088 /* Setup displaced stepping. */
4089 set_gdbarch_displaced_step_copy_insn (gdbarch,
4090 simple_displaced_step_copy_insn);
99e40580
UW		 4091 set_gdbarch_displaced_step_hw_singlestep (gdbarch,
4092 ppc_displaced_step_hw_singlestep);
2454a024
UW		 4093 set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup);
4094 set_gdbarch_displaced_step_free_closure (gdbarch,
4095 simple_displaced_step_free_closure);
4096 set_gdbarch_displaced_step_location (gdbarch,
4097 displaced_step_at_entry_point);
4098
4099 set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE);
4100
7b112f9c 4101 /* Hook in ABI-specific overrides, if they have been registered. */
8a4c2d24
UW		 4102 info.target_desc = tdesc;
4103 info.tdep_info = (void *) tdesc_data;
4be87837 4104 gdbarch_init_osabi (info, gdbarch);
7b112f9c 4105
61a65099
KB		 4106 switch (info.osabi)
4107 {
f5aecab8 4108 case GDB_OSABI_LINUX:
61a65099
KB		 4109 case GDB_OSABI_NETBSD_AOUT:
4110 case GDB_OSABI_NETBSD_ELF:
4111 case GDB_OSABI_UNKNOWN:
61a65099 4112 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
1af5d7ce
UW		 4113 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
4114 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
61a65099
KB		 4115 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
4116 break;
4117 default:
61a65099 4118 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
81332287
KB		 4119
4120 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
1af5d7ce
UW		 4121 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
4122 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
81332287 4123 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
61a65099
KB		 4124 }
4125
7cc46491
DJ		 4126 set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type);
4127 set_tdesc_pseudo_register_reggroup_p (gdbarch,
4128 rs6000_pseudo_register_reggroup_p);
4129 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
4130
4131 /* Override the normal target description method to make the SPE upper
4132 halves anonymous. */
4133 set_gdbarch_register_name (gdbarch, rs6000_register_name);
4134
604c2f83
LM		 4135 /* Choose register numbers for all supported pseudo-registers. */
4136 tdep->ppc_ev0_regnum = -1;
4137 tdep->ppc_dl0_regnum = -1;
4138 tdep->ppc_vsr0_regnum = -1;
4139 tdep->ppc_efpr0_regnum = -1;
9f643768 4140
604c2f83
LM		 4141 cur_reg = gdbarch_num_regs (gdbarch);
4142
4143 if (have_spe)
4144 {
4145 tdep->ppc_ev0_regnum = cur_reg;
4146 cur_reg += 32;
4147 }
4148 if (have_dfp)
4149 {
4150 tdep->ppc_dl0_regnum = cur_reg;
4151 cur_reg += 16;
4152 }
4153 if (have_vsx)
4154 {
4155 tdep->ppc_vsr0_regnum = cur_reg;
4156 cur_reg += 64;
4157 tdep->ppc_efpr0_regnum = cur_reg;
4158 cur_reg += 32;
4159 }
f949c649 4160
604c2f83
LM		 4161 gdb_assert (gdbarch_num_regs (gdbarch)
4162 + gdbarch_num_pseudo_regs (gdbarch) == cur_reg);
f949c649 4163
7a78ae4e 4164 return gdbarch;
c906108c
SS		 4165}
4166
7b112f9c 4167static void
8b164abb 4168rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
7b112f9c 4169{
8b164abb 4170 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7b112f9c
JT		 4171
4172 if (tdep == NULL)
4173 return;
4174
4be87837 4175 /* FIXME: Dump gdbarch_tdep. */
7b112f9c
JT		 4176}
4177
55eddb0f
DJ		 4178/* PowerPC-specific commands. */
4179
4180static void
4181set_powerpc_command (char *args, int from_tty)
4182{
4183 printf_unfiltered (_("\
4184\"set powerpc\" must be followed by an appropriate subcommand.\n"));
4185 help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout);
4186}
4187
4188static void
4189show_powerpc_command (char *args, int from_tty)
4190{
4191 cmd_show_list (showpowerpccmdlist, from_tty, "");
4192}
4193
4194static void
4195powerpc_set_soft_float (char *args, int from_tty,
4196 struct cmd_list_element *c)
4197{
4198 struct gdbarch_info info;
4199
4200 /* Update the architecture. */
4201 gdbarch_info_init (&info);
4202 if (!gdbarch_update_p (info))
9b20d036 4203 internal_error (__FILE__, __LINE__, _("could not update architecture"));
55eddb0f
DJ		 4204}
4205
4206static void
4207powerpc_set_vector_abi (char *args, int from_tty,
4208 struct cmd_list_element *c)
4209{
4210 struct gdbarch_info info;
4211 enum powerpc_vector_abi vector_abi;
4212
4213 for (vector_abi = POWERPC_VEC_AUTO;
4214 vector_abi != POWERPC_VEC_LAST;
4215 vector_abi++)
4216 if (strcmp (powerpc_vector_abi_string,
4217 powerpc_vector_strings[vector_abi]) == 0)
4218 {
4219 powerpc_vector_abi_global = vector_abi;
4220 break;
4221 }
4222
4223 if (vector_abi == POWERPC_VEC_LAST)
4224 internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."),
4225 powerpc_vector_abi_string);
4226
4227 /* Update the architecture. */
4228 gdbarch_info_init (&info);
4229 if (!gdbarch_update_p (info))
9b20d036 4230 internal_error (__FILE__, __LINE__, _("could not update architecture"));
55eddb0f
DJ		 4231}
4232
e09342b5
TJB		 4233/* Show the current setting of the exact watchpoints flag. */
4234
4235static void
4236show_powerpc_exact_watchpoints (struct ui_file *file, int from_tty,
4237 struct cmd_list_element *c,
4238 const char *value)
4239{
4240 fprintf_filtered (file, _("Use of exact watchpoints is %s.\n"), value);
4241}
4242
c906108c
SS		 4243/* Initialization code. */
4244
0df8b418
MS		 4245/* -Wmissing-prototypes */
4246extern initialize_file_ftype _initialize_rs6000_tdep;
b9362cc7 4247
c906108c 4248void
fba45db2 4249_initialize_rs6000_tdep (void)
c906108c 4250{
7b112f9c
JT		 4251 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
4252 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
7cc46491
DJ		 4253
4254 /* Initialize the standard target descriptions. */
4255 initialize_tdesc_powerpc_32 ();
7284e1be 4256 initialize_tdesc_powerpc_altivec32 ();
604c2f83 4257 initialize_tdesc_powerpc_vsx32 ();
7cc46491
DJ		 4258 initialize_tdesc_powerpc_403 ();
4259 initialize_tdesc_powerpc_403gc ();
4d09ffea 4260 initialize_tdesc_powerpc_405 ();
7cc46491
DJ		 4261 initialize_tdesc_powerpc_505 ();
4262 initialize_tdesc_powerpc_601 ();
4263 initialize_tdesc_powerpc_602 ();
4264 initialize_tdesc_powerpc_603 ();
4265 initialize_tdesc_powerpc_604 ();
4266 initialize_tdesc_powerpc_64 ();
7284e1be 4267 initialize_tdesc_powerpc_altivec64 ();
604c2f83 4268 initialize_tdesc_powerpc_vsx64 ();
7cc46491
DJ		 4269 initialize_tdesc_powerpc_7400 ();
4270 initialize_tdesc_powerpc_750 ();
4271 initialize_tdesc_powerpc_860 ();
4272 initialize_tdesc_powerpc_e500 ();
4273 initialize_tdesc_rs6000 ();
55eddb0f
DJ		 4274
4275 /* Add root prefix command for all "set powerpc"/"show powerpc"
4276 commands. */
4277 add_prefix_cmd ("powerpc", no_class, set_powerpc_command,
4278 _("Various PowerPC-specific commands."),
4279 &setpowerpccmdlist, "set powerpc ", 0, &setlist);
4280
4281 add_prefix_cmd ("powerpc", no_class, show_powerpc_command,
4282 _("Various PowerPC-specific commands."),
4283 &showpowerpccmdlist, "show powerpc ", 0, &showlist);
4284
4285 /* Add a command to allow the user to force the ABI. */
4286 add_setshow_auto_boolean_cmd ("soft-float", class_support,
4287 &powerpc_soft_float_global,
4288 _("Set whether to use a soft-float ABI."),
4289 _("Show whether to use a soft-float ABI."),
4290 NULL,
4291 powerpc_set_soft_float, NULL,
4292 &setpowerpccmdlist, &showpowerpccmdlist);
4293
4294 add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings,
4295 &powerpc_vector_abi_string,
4296 _("Set the vector ABI."),
4297 _("Show the vector ABI."),
4298 NULL, powerpc_set_vector_abi, NULL,
4299 &setpowerpccmdlist, &showpowerpccmdlist);
e09342b5
TJB		 4300
4301 add_setshow_boolean_cmd ("exact-watchpoints", class_support,
4302 &target_exact_watchpoints,
4303 _("\
4304Set whether to use just one debug register for watchpoints on scalars."),
4305 _("\
4306Show whether to use just one debug register for watchpoints on scalars."),
4307 _("\
4308If true, GDB will use only one debug register when watching a variable of\n\
4309scalar type, thus assuming that the variable is accessed through the address\n\
4310of its first byte."),
4311 NULL, show_powerpc_exact_watchpoints,
4312 &setpowerpccmdlist, &showpowerpccmdlist);
c906108c 4313}
GDB Binutils - Deliverables
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