Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for GDB, the GNU debugger. |
7aea86e6 AC |
2 | |
3 | Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, | |
4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software | |
5 | Foundation, Inc. | |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b JM |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 59 Temple Place - Suite 330, | |
22 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
23 | |
24 | #include "defs.h" | |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "symtab.h" | |
28 | #include "target.h" | |
29 | #include "gdbcore.h" | |
30 | #include "gdbcmd.h" | |
c906108c | 31 | #include "objfiles.h" |
7a78ae4e | 32 | #include "arch-utils.h" |
4e052eda | 33 | #include "regcache.h" |
d195bc9f | 34 | #include "regset.h" |
d16aafd8 | 35 | #include "doublest.h" |
fd0407d6 | 36 | #include "value.h" |
1fcc0bb8 | 37 | #include "parser-defs.h" |
4be87837 | 38 | #include "osabi.h" |
7d9b040b | 39 | #include "infcall.h" |
9f643768 JB |
40 | #include "sim-regno.h" |
41 | #include "gdb/sim-ppc.h" | |
6ced10dd | 42 | #include "reggroups.h" |
7a78ae4e | 43 | |
2fccf04a | 44 | #include "libbfd.h" /* for bfd_default_set_arch_mach */ |
7a78ae4e | 45 | #include "coff/internal.h" /* for libcoff.h */ |
2fccf04a | 46 | #include "libcoff.h" /* for xcoff_data */ |
11ed25ac KB |
47 | #include "coff/xcoff.h" |
48 | #include "libxcoff.h" | |
7a78ae4e | 49 | |
9aa1e687 | 50 | #include "elf-bfd.h" |
7a78ae4e | 51 | |
6ded7999 | 52 | #include "solib-svr4.h" |
9aa1e687 | 53 | #include "ppc-tdep.h" |
7a78ae4e | 54 | |
338ef23d | 55 | #include "gdb_assert.h" |
a89aa300 | 56 | #include "dis-asm.h" |
338ef23d | 57 | |
61a65099 KB |
58 | #include "trad-frame.h" |
59 | #include "frame-unwind.h" | |
60 | #include "frame-base.h" | |
61 | ||
7a78ae4e ND |
62 | /* If the kernel has to deliver a signal, it pushes a sigcontext |
63 | structure on the stack and then calls the signal handler, passing | |
64 | the address of the sigcontext in an argument register. Usually | |
65 | the signal handler doesn't save this register, so we have to | |
66 | access the sigcontext structure via an offset from the signal handler | |
67 | frame. | |
68 | The following constants were determined by experimentation on AIX 3.2. */ | |
69 | #define SIG_FRAME_PC_OFFSET 96 | |
70 | #define SIG_FRAME_LR_OFFSET 108 | |
71 | #define SIG_FRAME_FP_OFFSET 284 | |
72 | ||
7a78ae4e ND |
73 | /* To be used by skip_prologue. */ |
74 | ||
75 | struct rs6000_framedata | |
76 | { | |
77 | int offset; /* total size of frame --- the distance | |
78 | by which we decrement sp to allocate | |
79 | the frame */ | |
80 | int saved_gpr; /* smallest # of saved gpr */ | |
81 | int saved_fpr; /* smallest # of saved fpr */ | |
6be8bc0c | 82 | int saved_vr; /* smallest # of saved vr */ |
96ff0de4 | 83 | int saved_ev; /* smallest # of saved ev */ |
7a78ae4e ND |
84 | int alloca_reg; /* alloca register number (frame ptr) */ |
85 | char frameless; /* true if frameless functions. */ | |
86 | char nosavedpc; /* true if pc not saved. */ | |
87 | int gpr_offset; /* offset of saved gprs from prev sp */ | |
88 | int fpr_offset; /* offset of saved fprs from prev sp */ | |
6be8bc0c | 89 | int vr_offset; /* offset of saved vrs from prev sp */ |
96ff0de4 | 90 | int ev_offset; /* offset of saved evs from prev sp */ |
7a78ae4e ND |
91 | int lr_offset; /* offset of saved lr */ |
92 | int cr_offset; /* offset of saved cr */ | |
6be8bc0c | 93 | int vrsave_offset; /* offset of saved vrsave register */ |
7a78ae4e ND |
94 | }; |
95 | ||
96 | /* Description of a single register. */ | |
97 | ||
98 | struct reg | |
99 | { | |
100 | char *name; /* name of register */ | |
101 | unsigned char sz32; /* size on 32-bit arch, 0 if nonextant */ | |
102 | unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */ | |
103 | unsigned char fpr; /* whether register is floating-point */ | |
489461e2 | 104 | unsigned char pseudo; /* whether register is pseudo */ |
13ac140c JB |
105 | int spr_num; /* PowerPC SPR number, or -1 if not an SPR. |
106 | This is an ISA SPR number, not a GDB | |
107 | register number. */ | |
7a78ae4e ND |
108 | }; |
109 | ||
c906108c SS |
110 | /* Breakpoint shadows for the single step instructions will be kept here. */ |
111 | ||
c5aa993b JM |
112 | static struct sstep_breaks |
113 | { | |
114 | /* Address, or 0 if this is not in use. */ | |
115 | CORE_ADDR address; | |
116 | /* Shadow contents. */ | |
117 | char data[4]; | |
118 | } | |
119 | stepBreaks[2]; | |
c906108c SS |
120 | |
121 | /* Hook for determining the TOC address when calling functions in the | |
122 | inferior under AIX. The initialization code in rs6000-nat.c sets | |
123 | this hook to point to find_toc_address. */ | |
124 | ||
7a78ae4e ND |
125 | CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL; |
126 | ||
127 | /* Hook to set the current architecture when starting a child process. | |
128 | rs6000-nat.c sets this. */ | |
129 | ||
130 | void (*rs6000_set_host_arch_hook) (int) = NULL; | |
c906108c SS |
131 | |
132 | /* Static function prototypes */ | |
133 | ||
a14ed312 KB |
134 | static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc, |
135 | CORE_ADDR safety); | |
077276e8 KB |
136 | static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR, |
137 | struct rs6000_framedata *); | |
c906108c | 138 | |
64b84175 KB |
139 | /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ |
140 | int | |
141 | altivec_register_p (int regno) | |
142 | { | |
143 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
144 | if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) | |
145 | return 0; | |
146 | else | |
147 | return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); | |
148 | } | |
149 | ||
383f0f5b | 150 | |
867e2dc5 JB |
151 | /* Return true if REGNO is an SPE register, false otherwise. */ |
152 | int | |
153 | spe_register_p (int regno) | |
154 | { | |
155 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
156 | ||
157 | /* Is it a reference to EV0 -- EV31, and do we have those? */ | |
158 | if (tdep->ppc_ev0_regnum >= 0 | |
159 | && tdep->ppc_ev31_regnum >= 0 | |
160 | && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum) | |
161 | return 1; | |
162 | ||
6ced10dd JB |
163 | /* Is it a reference to one of the raw upper GPR halves? */ |
164 | if (tdep->ppc_ev0_upper_regnum >= 0 | |
165 | && tdep->ppc_ev0_upper_regnum <= regno | |
166 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
167 | return 1; | |
168 | ||
867e2dc5 JB |
169 | /* Is it a reference to the 64-bit accumulator, and do we have that? */ |
170 | if (tdep->ppc_acc_regnum >= 0 | |
171 | && tdep->ppc_acc_regnum == regno) | |
172 | return 1; | |
173 | ||
174 | /* Is it a reference to the SPE floating-point status and control register, | |
175 | and do we have that? */ | |
176 | if (tdep->ppc_spefscr_regnum >= 0 | |
177 | && tdep->ppc_spefscr_regnum == regno) | |
178 | return 1; | |
179 | ||
180 | return 0; | |
181 | } | |
182 | ||
183 | ||
383f0f5b JB |
184 | /* Return non-zero if the architecture described by GDBARCH has |
185 | floating-point registers (f0 --- f31 and fpscr). */ | |
0a613259 AC |
186 | int |
187 | ppc_floating_point_unit_p (struct gdbarch *gdbarch) | |
188 | { | |
383f0f5b JB |
189 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
190 | ||
191 | return (tdep->ppc_fp0_regnum >= 0 | |
192 | && tdep->ppc_fpscr_regnum >= 0); | |
0a613259 | 193 | } |
9f643768 JB |
194 | |
195 | static void | |
196 | set_sim_regno (int *table, int gdb_regno, int sim_regno) | |
197 | { | |
198 | /* Make sure we don't try to assign any given GDB register a sim | |
199 | register number more than once. */ | |
200 | gdb_assert (table[gdb_regno] == -1); | |
201 | table[gdb_regno] = sim_regno; | |
202 | } | |
203 | ||
204 | static void | |
205 | init_sim_regno_table (struct gdbarch *arch) | |
206 | { | |
207 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
208 | int total_regs = gdbarch_num_regs (arch) + gdbarch_num_pseudo_regs (arch); | |
209 | const struct reg *regs = tdep->regs; | |
210 | int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int); | |
211 | int i; | |
212 | ||
213 | /* Presume that all registers not explicitly mentioned below are | |
214 | unavailable from the sim. */ | |
215 | for (i = 0; i < total_regs; i++) | |
216 | sim_regno[i] = -1; | |
217 | ||
218 | /* General-purpose registers. */ | |
219 | for (i = 0; i < ppc_num_gprs; i++) | |
220 | set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i); | |
221 | ||
222 | /* Floating-point registers. */ | |
223 | if (tdep->ppc_fp0_regnum >= 0) | |
224 | for (i = 0; i < ppc_num_fprs; i++) | |
225 | set_sim_regno (sim_regno, | |
226 | tdep->ppc_fp0_regnum + i, | |
227 | sim_ppc_f0_regnum + i); | |
228 | if (tdep->ppc_fpscr_regnum >= 0) | |
229 | set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum); | |
230 | ||
231 | set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum); | |
232 | set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum); | |
233 | set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum); | |
234 | ||
235 | /* Segment registers. */ | |
236 | if (tdep->ppc_sr0_regnum >= 0) | |
237 | for (i = 0; i < ppc_num_srs; i++) | |
238 | set_sim_regno (sim_regno, | |
239 | tdep->ppc_sr0_regnum + i, | |
240 | sim_ppc_sr0_regnum + i); | |
241 | ||
242 | /* Altivec registers. */ | |
243 | if (tdep->ppc_vr0_regnum >= 0) | |
244 | { | |
245 | for (i = 0; i < ppc_num_vrs; i++) | |
246 | set_sim_regno (sim_regno, | |
247 | tdep->ppc_vr0_regnum + i, | |
248 | sim_ppc_vr0_regnum + i); | |
249 | ||
250 | /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum, | |
251 | we can treat this more like the other cases. */ | |
252 | set_sim_regno (sim_regno, | |
253 | tdep->ppc_vr0_regnum + ppc_num_vrs, | |
254 | sim_ppc_vscr_regnum); | |
255 | } | |
256 | /* vsave is a special-purpose register, so the code below handles it. */ | |
257 | ||
258 | /* SPE APU (E500) registers. */ | |
259 | if (tdep->ppc_ev0_regnum >= 0) | |
260 | for (i = 0; i < ppc_num_gprs; i++) | |
261 | set_sim_regno (sim_regno, | |
262 | tdep->ppc_ev0_regnum + i, | |
263 | sim_ppc_ev0_regnum + i); | |
6ced10dd JB |
264 | if (tdep->ppc_ev0_upper_regnum >= 0) |
265 | for (i = 0; i < ppc_num_gprs; i++) | |
266 | set_sim_regno (sim_regno, | |
267 | tdep->ppc_ev0_upper_regnum + i, | |
268 | sim_ppc_rh0_regnum + i); | |
9f643768 JB |
269 | if (tdep->ppc_acc_regnum >= 0) |
270 | set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum); | |
271 | /* spefscr is a special-purpose register, so the code below handles it. */ | |
272 | ||
273 | /* Now handle all special-purpose registers. Verify that they | |
274 | haven't mistakenly been assigned numbers by any of the above | |
275 | code). */ | |
276 | for (i = 0; i < total_regs; i++) | |
277 | if (regs[i].spr_num >= 0) | |
278 | set_sim_regno (sim_regno, i, regs[i].spr_num + sim_ppc_spr0_regnum); | |
279 | ||
280 | /* Drop the initialized array into place. */ | |
281 | tdep->sim_regno = sim_regno; | |
282 | } | |
283 | ||
284 | static int | |
285 | rs6000_register_sim_regno (int reg) | |
286 | { | |
287 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
288 | int sim_regno; | |
289 | ||
290 | gdb_assert (0 <= reg && reg <= NUM_REGS + NUM_PSEUDO_REGS); | |
291 | sim_regno = tdep->sim_regno[reg]; | |
292 | ||
293 | if (sim_regno >= 0) | |
294 | return sim_regno; | |
295 | else | |
296 | return LEGACY_SIM_REGNO_IGNORE; | |
297 | } | |
298 | ||
d195bc9f MK |
299 | \f |
300 | ||
301 | /* Register set support functions. */ | |
302 | ||
303 | static void | |
304 | ppc_supply_reg (struct regcache *regcache, int regnum, | |
305 | const char *regs, size_t offset) | |
306 | { | |
307 | if (regnum != -1 && offset != -1) | |
308 | regcache_raw_supply (regcache, regnum, regs + offset); | |
309 | } | |
310 | ||
311 | static void | |
312 | ppc_collect_reg (const struct regcache *regcache, int regnum, | |
313 | char *regs, size_t offset) | |
314 | { | |
315 | if (regnum != -1 && offset != -1) | |
316 | regcache_raw_collect (regcache, regnum, regs + offset); | |
317 | } | |
318 | ||
319 | /* Supply register REGNUM in the general-purpose register set REGSET | |
320 | from the buffer specified by GREGS and LEN to register cache | |
321 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
322 | ||
323 | void | |
324 | ppc_supply_gregset (const struct regset *regset, struct regcache *regcache, | |
325 | int regnum, const void *gregs, size_t len) | |
326 | { | |
327 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
328 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
329 | const struct ppc_reg_offsets *offsets = regset->descr; | |
330 | size_t offset; | |
331 | int i; | |
332 | ||
cdf2c5f5 | 333 | for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; |
063715bf | 334 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; |
cdf2c5f5 | 335 | i++, offset += 4) |
d195bc9f MK |
336 | { |
337 | if (regnum == -1 || regnum == i) | |
338 | ppc_supply_reg (regcache, i, gregs, offset); | |
339 | } | |
340 | ||
341 | if (regnum == -1 || regnum == PC_REGNUM) | |
342 | ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset); | |
343 | if (regnum == -1 || regnum == tdep->ppc_ps_regnum) | |
344 | ppc_supply_reg (regcache, tdep->ppc_ps_regnum, | |
345 | gregs, offsets->ps_offset); | |
346 | if (regnum == -1 || regnum == tdep->ppc_cr_regnum) | |
347 | ppc_supply_reg (regcache, tdep->ppc_cr_regnum, | |
348 | gregs, offsets->cr_offset); | |
349 | if (regnum == -1 || regnum == tdep->ppc_lr_regnum) | |
350 | ppc_supply_reg (regcache, tdep->ppc_lr_regnum, | |
351 | gregs, offsets->lr_offset); | |
352 | if (regnum == -1 || regnum == tdep->ppc_ctr_regnum) | |
353 | ppc_supply_reg (regcache, tdep->ppc_ctr_regnum, | |
354 | gregs, offsets->ctr_offset); | |
355 | if (regnum == -1 || regnum == tdep->ppc_xer_regnum) | |
356 | ppc_supply_reg (regcache, tdep->ppc_xer_regnum, | |
357 | gregs, offsets->cr_offset); | |
358 | if (regnum == -1 || regnum == tdep->ppc_mq_regnum) | |
359 | ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset); | |
360 | } | |
361 | ||
362 | /* Supply register REGNUM in the floating-point register set REGSET | |
363 | from the buffer specified by FPREGS and LEN to register cache | |
364 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
365 | ||
366 | void | |
367 | ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
368 | int regnum, const void *fpregs, size_t len) | |
369 | { | |
370 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
371 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
372 | const struct ppc_reg_offsets *offsets = regset->descr; | |
373 | size_t offset; | |
374 | int i; | |
375 | ||
383f0f5b JB |
376 | gdb_assert (ppc_floating_point_unit_p (gdbarch)); |
377 | ||
d195bc9f | 378 | offset = offsets->f0_offset; |
366f009f JB |
379 | for (i = tdep->ppc_fp0_regnum; |
380 | i < tdep->ppc_fp0_regnum + ppc_num_fprs; | |
381 | i++, offset += 4) | |
d195bc9f MK |
382 | { |
383 | if (regnum == -1 || regnum == i) | |
384 | ppc_supply_reg (regcache, i, fpregs, offset); | |
385 | } | |
386 | ||
387 | if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum) | |
388 | ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum, | |
389 | fpregs, offsets->fpscr_offset); | |
390 | } | |
391 | ||
392 | /* Collect register REGNUM in the general-purpose register set | |
393 | REGSET. from register cache REGCACHE into the buffer specified by | |
394 | GREGS and LEN. If REGNUM is -1, do this for all registers in | |
395 | REGSET. */ | |
396 | ||
397 | void | |
398 | ppc_collect_gregset (const struct regset *regset, | |
399 | const struct regcache *regcache, | |
400 | int regnum, void *gregs, size_t len) | |
401 | { | |
402 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
403 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
404 | const struct ppc_reg_offsets *offsets = regset->descr; | |
405 | size_t offset; | |
406 | int i; | |
407 | ||
408 | offset = offsets->r0_offset; | |
cdf2c5f5 | 409 | for (i = tdep->ppc_gp0_regnum; |
063715bf | 410 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; |
cdf2c5f5 | 411 | i++, offset += 4) |
d195bc9f MK |
412 | { |
413 | if (regnum == -1 || regnum == i) | |
2e56e9c1 | 414 | ppc_collect_reg (regcache, i, gregs, offset); |
d195bc9f MK |
415 | } |
416 | ||
417 | if (regnum == -1 || regnum == PC_REGNUM) | |
418 | ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset); | |
419 | if (regnum == -1 || regnum == tdep->ppc_ps_regnum) | |
420 | ppc_collect_reg (regcache, tdep->ppc_ps_regnum, | |
421 | gregs, offsets->ps_offset); | |
422 | if (regnum == -1 || regnum == tdep->ppc_cr_regnum) | |
423 | ppc_collect_reg (regcache, tdep->ppc_cr_regnum, | |
424 | gregs, offsets->cr_offset); | |
425 | if (regnum == -1 || regnum == tdep->ppc_lr_regnum) | |
426 | ppc_collect_reg (regcache, tdep->ppc_lr_regnum, | |
427 | gregs, offsets->lr_offset); | |
428 | if (regnum == -1 || regnum == tdep->ppc_ctr_regnum) | |
429 | ppc_collect_reg (regcache, tdep->ppc_ctr_regnum, | |
430 | gregs, offsets->ctr_offset); | |
431 | if (regnum == -1 || regnum == tdep->ppc_xer_regnum) | |
432 | ppc_collect_reg (regcache, tdep->ppc_xer_regnum, | |
433 | gregs, offsets->xer_offset); | |
434 | if (regnum == -1 || regnum == tdep->ppc_mq_regnum) | |
435 | ppc_collect_reg (regcache, tdep->ppc_mq_regnum, | |
436 | gregs, offsets->mq_offset); | |
437 | } | |
438 | ||
439 | /* Collect register REGNUM in the floating-point register set | |
440 | REGSET. from register cache REGCACHE into the buffer specified by | |
441 | FPREGS and LEN. If REGNUM is -1, do this for all registers in | |
442 | REGSET. */ | |
443 | ||
444 | void | |
445 | ppc_collect_fpregset (const struct regset *regset, | |
446 | const struct regcache *regcache, | |
447 | int regnum, void *fpregs, size_t len) | |
448 | { | |
449 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
450 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
451 | const struct ppc_reg_offsets *offsets = regset->descr; | |
452 | size_t offset; | |
453 | int i; | |
454 | ||
383f0f5b JB |
455 | gdb_assert (ppc_floating_point_unit_p (gdbarch)); |
456 | ||
d195bc9f | 457 | offset = offsets->f0_offset; |
366f009f JB |
458 | for (i = tdep->ppc_fp0_regnum; |
459 | i <= tdep->ppc_fp0_regnum + ppc_num_fprs; | |
460 | i++, offset += 4) | |
d195bc9f MK |
461 | { |
462 | if (regnum == -1 || regnum == i) | |
463 | ppc_collect_reg (regcache, regnum, fpregs, offset); | |
464 | } | |
465 | ||
466 | if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum) | |
467 | ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum, | |
468 | fpregs, offsets->fpscr_offset); | |
469 | } | |
470 | \f | |
0a613259 | 471 | |
7a78ae4e | 472 | /* Read a LEN-byte address from debugged memory address MEMADDR. */ |
c906108c | 473 | |
7a78ae4e ND |
474 | static CORE_ADDR |
475 | read_memory_addr (CORE_ADDR memaddr, int len) | |
476 | { | |
477 | return read_memory_unsigned_integer (memaddr, len); | |
478 | } | |
c906108c | 479 | |
7a78ae4e ND |
480 | static CORE_ADDR |
481 | rs6000_skip_prologue (CORE_ADDR pc) | |
b83266a0 SS |
482 | { |
483 | struct rs6000_framedata frame; | |
077276e8 | 484 | pc = skip_prologue (pc, 0, &frame); |
b83266a0 SS |
485 | return pc; |
486 | } | |
487 | ||
488 | ||
c906108c SS |
489 | /* Fill in fi->saved_regs */ |
490 | ||
491 | struct frame_extra_info | |
492 | { | |
493 | /* Functions calling alloca() change the value of the stack | |
494 | pointer. We need to use initial stack pointer (which is saved in | |
495 | r31 by gcc) in such cases. If a compiler emits traceback table, | |
496 | then we should use the alloca register specified in traceback | |
497 | table. FIXME. */ | |
c5aa993b | 498 | CORE_ADDR initial_sp; /* initial stack pointer. */ |
c906108c SS |
499 | }; |
500 | ||
143985b7 | 501 | /* Get the ith function argument for the current function. */ |
b9362cc7 | 502 | static CORE_ADDR |
143985b7 AF |
503 | rs6000_fetch_pointer_argument (struct frame_info *frame, int argi, |
504 | struct type *type) | |
505 | { | |
506 | CORE_ADDR addr; | |
7f5f525d | 507 | get_frame_register (frame, 3 + argi, &addr); |
143985b7 AF |
508 | return addr; |
509 | } | |
510 | ||
c906108c SS |
511 | /* Calculate the destination of a branch/jump. Return -1 if not a branch. */ |
512 | ||
513 | static CORE_ADDR | |
7a78ae4e | 514 | branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety) |
c906108c SS |
515 | { |
516 | CORE_ADDR dest; | |
517 | int immediate; | |
518 | int absolute; | |
519 | int ext_op; | |
520 | ||
521 | absolute = (int) ((instr >> 1) & 1); | |
522 | ||
c5aa993b JM |
523 | switch (opcode) |
524 | { | |
525 | case 18: | |
526 | immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */ | |
527 | if (absolute) | |
528 | dest = immediate; | |
529 | else | |
530 | dest = pc + immediate; | |
531 | break; | |
532 | ||
533 | case 16: | |
534 | immediate = ((instr & ~3) << 16) >> 16; /* br conditional */ | |
535 | if (absolute) | |
536 | dest = immediate; | |
537 | else | |
538 | dest = pc + immediate; | |
539 | break; | |
540 | ||
541 | case 19: | |
542 | ext_op = (instr >> 1) & 0x3ff; | |
543 | ||
544 | if (ext_op == 16) /* br conditional register */ | |
545 | { | |
2188cbdd | 546 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; |
c5aa993b JM |
547 | |
548 | /* If we are about to return from a signal handler, dest is | |
549 | something like 0x3c90. The current frame is a signal handler | |
550 | caller frame, upon completion of the sigreturn system call | |
551 | execution will return to the saved PC in the frame. */ | |
552 | if (dest < TEXT_SEGMENT_BASE) | |
553 | { | |
554 | struct frame_info *fi; | |
555 | ||
556 | fi = get_current_frame (); | |
557 | if (fi != NULL) | |
8b36eed8 | 558 | dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET, |
21283beb | 559 | gdbarch_tdep (current_gdbarch)->wordsize); |
c5aa993b JM |
560 | } |
561 | } | |
562 | ||
563 | else if (ext_op == 528) /* br cond to count reg */ | |
564 | { | |
2188cbdd | 565 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3; |
c5aa993b JM |
566 | |
567 | /* If we are about to execute a system call, dest is something | |
568 | like 0x22fc or 0x3b00. Upon completion the system call | |
569 | will return to the address in the link register. */ | |
570 | if (dest < TEXT_SEGMENT_BASE) | |
2188cbdd | 571 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; |
c5aa993b JM |
572 | } |
573 | else | |
574 | return -1; | |
575 | break; | |
c906108c | 576 | |
c5aa993b JM |
577 | default: |
578 | return -1; | |
579 | } | |
c906108c SS |
580 | return (dest < TEXT_SEGMENT_BASE) ? safety : dest; |
581 | } | |
582 | ||
583 | ||
584 | /* Sequence of bytes for breakpoint instruction. */ | |
585 | ||
f4f9705a | 586 | const static unsigned char * |
7a78ae4e | 587 | rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size) |
c906108c | 588 | { |
aaab4dba AC |
589 | static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 }; |
590 | static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d }; | |
c906108c | 591 | *bp_size = 4; |
d7449b42 | 592 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
593 | return big_breakpoint; |
594 | else | |
595 | return little_breakpoint; | |
596 | } | |
597 | ||
598 | ||
599 | /* AIX does not support PT_STEP. Simulate it. */ | |
600 | ||
601 | void | |
379d08a1 AC |
602 | rs6000_software_single_step (enum target_signal signal, |
603 | int insert_breakpoints_p) | |
c906108c | 604 | { |
7c40d541 KB |
605 | CORE_ADDR dummy; |
606 | int breakp_sz; | |
f4f9705a | 607 | const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz); |
c906108c SS |
608 | int ii, insn; |
609 | CORE_ADDR loc; | |
610 | CORE_ADDR breaks[2]; | |
611 | int opcode; | |
612 | ||
c5aa993b JM |
613 | if (insert_breakpoints_p) |
614 | { | |
c906108c | 615 | |
c5aa993b | 616 | loc = read_pc (); |
c906108c | 617 | |
c5aa993b | 618 | insn = read_memory_integer (loc, 4); |
c906108c | 619 | |
7c40d541 | 620 | breaks[0] = loc + breakp_sz; |
c5aa993b JM |
621 | opcode = insn >> 26; |
622 | breaks[1] = branch_dest (opcode, insn, loc, breaks[0]); | |
c906108c | 623 | |
c5aa993b JM |
624 | /* Don't put two breakpoints on the same address. */ |
625 | if (breaks[1] == breaks[0]) | |
626 | breaks[1] = -1; | |
c906108c | 627 | |
c5aa993b | 628 | stepBreaks[1].address = 0; |
c906108c | 629 | |
c5aa993b JM |
630 | for (ii = 0; ii < 2; ++ii) |
631 | { | |
c906108c | 632 | |
c5aa993b JM |
633 | /* ignore invalid breakpoint. */ |
634 | if (breaks[ii] == -1) | |
635 | continue; | |
7c40d541 | 636 | target_insert_breakpoint (breaks[ii], stepBreaks[ii].data); |
c5aa993b JM |
637 | stepBreaks[ii].address = breaks[ii]; |
638 | } | |
c906108c | 639 | |
c5aa993b JM |
640 | } |
641 | else | |
642 | { | |
c906108c | 643 | |
c5aa993b JM |
644 | /* remove step breakpoints. */ |
645 | for (ii = 0; ii < 2; ++ii) | |
646 | if (stepBreaks[ii].address != 0) | |
7c40d541 KB |
647 | target_remove_breakpoint (stepBreaks[ii].address, |
648 | stepBreaks[ii].data); | |
c5aa993b | 649 | } |
c906108c | 650 | errno = 0; /* FIXME, don't ignore errors! */ |
c5aa993b | 651 | /* What errors? {read,write}_memory call error(). */ |
c906108c SS |
652 | } |
653 | ||
654 | ||
655 | /* return pc value after skipping a function prologue and also return | |
656 | information about a function frame. | |
657 | ||
658 | in struct rs6000_framedata fdata: | |
c5aa993b JM |
659 | - frameless is TRUE, if function does not have a frame. |
660 | - nosavedpc is TRUE, if function does not save %pc value in its frame. | |
661 | - offset is the initial size of this stack frame --- the amount by | |
662 | which we decrement the sp to allocate the frame. | |
663 | - saved_gpr is the number of the first saved gpr. | |
664 | - saved_fpr is the number of the first saved fpr. | |
6be8bc0c | 665 | - saved_vr is the number of the first saved vr. |
96ff0de4 | 666 | - saved_ev is the number of the first saved ev. |
c5aa993b JM |
667 | - alloca_reg is the number of the register used for alloca() handling. |
668 | Otherwise -1. | |
669 | - gpr_offset is the offset of the first saved gpr from the previous frame. | |
670 | - fpr_offset is the offset of the first saved fpr from the previous frame. | |
6be8bc0c | 671 | - vr_offset is the offset of the first saved vr from the previous frame. |
96ff0de4 | 672 | - ev_offset is the offset of the first saved ev from the previous frame. |
c5aa993b JM |
673 | - lr_offset is the offset of the saved lr |
674 | - cr_offset is the offset of the saved cr | |
6be8bc0c | 675 | - vrsave_offset is the offset of the saved vrsave register |
c5aa993b | 676 | */ |
c906108c SS |
677 | |
678 | #define SIGNED_SHORT(x) \ | |
679 | ((sizeof (short) == 2) \ | |
680 | ? ((int)(short)(x)) \ | |
681 | : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) | |
682 | ||
683 | #define GET_SRC_REG(x) (((x) >> 21) & 0x1f) | |
684 | ||
55d05f3b KB |
685 | /* Limit the number of skipped non-prologue instructions, as the examining |
686 | of the prologue is expensive. */ | |
687 | static int max_skip_non_prologue_insns = 10; | |
688 | ||
689 | /* Given PC representing the starting address of a function, and | |
690 | LIM_PC which is the (sloppy) limit to which to scan when looking | |
691 | for a prologue, attempt to further refine this limit by using | |
692 | the line data in the symbol table. If successful, a better guess | |
693 | on where the prologue ends is returned, otherwise the previous | |
694 | value of lim_pc is returned. */ | |
634aa483 AC |
695 | |
696 | /* FIXME: cagney/2004-02-14: This function and logic have largely been | |
697 | superseded by skip_prologue_using_sal. */ | |
698 | ||
55d05f3b KB |
699 | static CORE_ADDR |
700 | refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc) | |
701 | { | |
702 | struct symtab_and_line prologue_sal; | |
703 | ||
704 | prologue_sal = find_pc_line (pc, 0); | |
705 | if (prologue_sal.line != 0) | |
706 | { | |
707 | int i; | |
708 | CORE_ADDR addr = prologue_sal.end; | |
709 | ||
710 | /* Handle the case in which compiler's optimizer/scheduler | |
711 | has moved instructions into the prologue. We scan ahead | |
712 | in the function looking for address ranges whose corresponding | |
713 | line number is less than or equal to the first one that we | |
714 | found for the function. (It can be less than when the | |
715 | scheduler puts a body instruction before the first prologue | |
716 | instruction.) */ | |
717 | for (i = 2 * max_skip_non_prologue_insns; | |
718 | i > 0 && (lim_pc == 0 || addr < lim_pc); | |
719 | i--) | |
720 | { | |
721 | struct symtab_and_line sal; | |
722 | ||
723 | sal = find_pc_line (addr, 0); | |
724 | if (sal.line == 0) | |
725 | break; | |
726 | if (sal.line <= prologue_sal.line | |
727 | && sal.symtab == prologue_sal.symtab) | |
728 | { | |
729 | prologue_sal = sal; | |
730 | } | |
731 | addr = sal.end; | |
732 | } | |
733 | ||
734 | if (lim_pc == 0 || prologue_sal.end < lim_pc) | |
735 | lim_pc = prologue_sal.end; | |
736 | } | |
737 | return lim_pc; | |
738 | } | |
739 | ||
773df3e5 JB |
740 | /* Return nonzero if the given instruction OP can be part of the prologue |
741 | of a function and saves a parameter on the stack. FRAMEP should be | |
742 | set if one of the previous instructions in the function has set the | |
743 | Frame Pointer. */ | |
744 | ||
745 | static int | |
746 | store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg) | |
747 | { | |
748 | /* Move parameters from argument registers to temporary register. */ | |
749 | if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */ | |
750 | { | |
751 | /* Rx must be scratch register r0. */ | |
752 | const int rx_regno = (op >> 16) & 31; | |
753 | /* Ry: Only r3 - r10 are used for parameter passing. */ | |
754 | const int ry_regno = GET_SRC_REG (op); | |
755 | ||
756 | if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10) | |
757 | { | |
758 | *r0_contains_arg = 1; | |
759 | return 1; | |
760 | } | |
761 | else | |
762 | return 0; | |
763 | } | |
764 | ||
765 | /* Save a General Purpose Register on stack. */ | |
766 | ||
767 | if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */ | |
768 | (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */ | |
769 | { | |
770 | /* Rx: Only r3 - r10 are used for parameter passing. */ | |
771 | const int rx_regno = GET_SRC_REG (op); | |
772 | ||
773 | return (rx_regno >= 3 && rx_regno <= 10); | |
774 | } | |
775 | ||
776 | /* Save a General Purpose Register on stack via the Frame Pointer. */ | |
777 | ||
778 | if (framep && | |
779 | ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */ | |
780 | (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */ | |
781 | (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */ | |
782 | { | |
783 | /* Rx: Usually, only r3 - r10 are used for parameter passing. | |
784 | However, the compiler sometimes uses r0 to hold an argument. */ | |
785 | const int rx_regno = GET_SRC_REG (op); | |
786 | ||
787 | return ((rx_regno >= 3 && rx_regno <= 10) | |
788 | || (rx_regno == 0 && *r0_contains_arg)); | |
789 | } | |
790 | ||
791 | if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ | |
792 | { | |
793 | /* Only f2 - f8 are used for parameter passing. */ | |
794 | const int src_regno = GET_SRC_REG (op); | |
795 | ||
796 | return (src_regno >= 2 && src_regno <= 8); | |
797 | } | |
798 | ||
799 | if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */ | |
800 | { | |
801 | /* Only f2 - f8 are used for parameter passing. */ | |
802 | const int src_regno = GET_SRC_REG (op); | |
803 | ||
804 | return (src_regno >= 2 && src_regno <= 8); | |
805 | } | |
806 | ||
807 | /* Not an insn that saves a parameter on stack. */ | |
808 | return 0; | |
809 | } | |
55d05f3b | 810 | |
7a78ae4e | 811 | static CORE_ADDR |
077276e8 | 812 | skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) |
c906108c SS |
813 | { |
814 | CORE_ADDR orig_pc = pc; | |
55d05f3b | 815 | CORE_ADDR last_prologue_pc = pc; |
6be8bc0c | 816 | CORE_ADDR li_found_pc = 0; |
c906108c SS |
817 | char buf[4]; |
818 | unsigned long op; | |
819 | long offset = 0; | |
6be8bc0c | 820 | long vr_saved_offset = 0; |
482ca3f5 KB |
821 | int lr_reg = -1; |
822 | int cr_reg = -1; | |
6be8bc0c | 823 | int vr_reg = -1; |
96ff0de4 EZ |
824 | int ev_reg = -1; |
825 | long ev_offset = 0; | |
6be8bc0c | 826 | int vrsave_reg = -1; |
c906108c SS |
827 | int reg; |
828 | int framep = 0; | |
829 | int minimal_toc_loaded = 0; | |
ddb20c56 | 830 | int prev_insn_was_prologue_insn = 1; |
55d05f3b | 831 | int num_skip_non_prologue_insns = 0; |
773df3e5 | 832 | int r0_contains_arg = 0; |
96ff0de4 | 833 | const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch); |
6f99cb26 | 834 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
96ff0de4 | 835 | |
55d05f3b KB |
836 | /* Attempt to find the end of the prologue when no limit is specified. |
837 | Note that refine_prologue_limit() has been written so that it may | |
838 | be used to "refine" the limits of non-zero PC values too, but this | |
839 | is only safe if we 1) trust the line information provided by the | |
840 | compiler and 2) iterate enough to actually find the end of the | |
841 | prologue. | |
842 | ||
843 | It may become a good idea at some point (for both performance and | |
844 | accuracy) to unconditionally call refine_prologue_limit(). But, | |
845 | until we can make a clear determination that this is beneficial, | |
846 | we'll play it safe and only use it to obtain a limit when none | |
847 | has been specified. */ | |
848 | if (lim_pc == 0) | |
849 | lim_pc = refine_prologue_limit (pc, lim_pc); | |
c906108c | 850 | |
ddb20c56 | 851 | memset (fdata, 0, sizeof (struct rs6000_framedata)); |
c906108c SS |
852 | fdata->saved_gpr = -1; |
853 | fdata->saved_fpr = -1; | |
6be8bc0c | 854 | fdata->saved_vr = -1; |
96ff0de4 | 855 | fdata->saved_ev = -1; |
c906108c SS |
856 | fdata->alloca_reg = -1; |
857 | fdata->frameless = 1; | |
858 | fdata->nosavedpc = 1; | |
859 | ||
55d05f3b | 860 | for (;; pc += 4) |
c906108c | 861 | { |
ddb20c56 KB |
862 | /* Sometimes it isn't clear if an instruction is a prologue |
863 | instruction or not. When we encounter one of these ambiguous | |
864 | cases, we'll set prev_insn_was_prologue_insn to 0 (false). | |
865 | Otherwise, we'll assume that it really is a prologue instruction. */ | |
866 | if (prev_insn_was_prologue_insn) | |
867 | last_prologue_pc = pc; | |
55d05f3b KB |
868 | |
869 | /* Stop scanning if we've hit the limit. */ | |
870 | if (lim_pc != 0 && pc >= lim_pc) | |
871 | break; | |
872 | ||
ddb20c56 KB |
873 | prev_insn_was_prologue_insn = 1; |
874 | ||
55d05f3b | 875 | /* Fetch the instruction and convert it to an integer. */ |
ddb20c56 KB |
876 | if (target_read_memory (pc, buf, 4)) |
877 | break; | |
878 | op = extract_signed_integer (buf, 4); | |
c906108c | 879 | |
c5aa993b JM |
880 | if ((op & 0xfc1fffff) == 0x7c0802a6) |
881 | { /* mflr Rx */ | |
43b1ab88 AC |
882 | /* Since shared library / PIC code, which needs to get its |
883 | address at runtime, can appear to save more than one link | |
884 | register vis: | |
885 | ||
886 | *INDENT-OFF* | |
887 | stwu r1,-304(r1) | |
888 | mflr r3 | |
889 | bl 0xff570d0 (blrl) | |
890 | stw r30,296(r1) | |
891 | mflr r30 | |
892 | stw r31,300(r1) | |
893 | stw r3,308(r1); | |
894 | ... | |
895 | *INDENT-ON* | |
896 | ||
897 | remember just the first one, but skip over additional | |
898 | ones. */ | |
899 | if (lr_reg < 0) | |
900 | lr_reg = (op & 0x03e00000); | |
773df3e5 JB |
901 | if (lr_reg == 0) |
902 | r0_contains_arg = 0; | |
c5aa993b | 903 | continue; |
c5aa993b JM |
904 | } |
905 | else if ((op & 0xfc1fffff) == 0x7c000026) | |
906 | { /* mfcr Rx */ | |
98f08d3d | 907 | cr_reg = (op & 0x03e00000); |
773df3e5 JB |
908 | if (cr_reg == 0) |
909 | r0_contains_arg = 0; | |
c5aa993b | 910 | continue; |
c906108c | 911 | |
c906108c | 912 | } |
c5aa993b JM |
913 | else if ((op & 0xfc1f0000) == 0xd8010000) |
914 | { /* stfd Rx,NUM(r1) */ | |
915 | reg = GET_SRC_REG (op); | |
916 | if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) | |
917 | { | |
918 | fdata->saved_fpr = reg; | |
919 | fdata->fpr_offset = SIGNED_SHORT (op) + offset; | |
920 | } | |
921 | continue; | |
c906108c | 922 | |
c5aa993b JM |
923 | } |
924 | else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ | |
7a78ae4e ND |
925 | (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ |
926 | (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ | |
927 | (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ | |
c5aa993b JM |
928 | { |
929 | ||
930 | reg = GET_SRC_REG (op); | |
931 | if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) | |
932 | { | |
933 | fdata->saved_gpr = reg; | |
7a78ae4e | 934 | if ((op & 0xfc1f0003) == 0xf8010000) |
98f08d3d | 935 | op &= ~3UL; |
c5aa993b JM |
936 | fdata->gpr_offset = SIGNED_SHORT (op) + offset; |
937 | } | |
938 | continue; | |
c906108c | 939 | |
ddb20c56 KB |
940 | } |
941 | else if ((op & 0xffff0000) == 0x60000000) | |
942 | { | |
96ff0de4 | 943 | /* nop */ |
ddb20c56 KB |
944 | /* Allow nops in the prologue, but do not consider them to |
945 | be part of the prologue unless followed by other prologue | |
946 | instructions. */ | |
947 | prev_insn_was_prologue_insn = 0; | |
948 | continue; | |
949 | ||
c906108c | 950 | } |
c5aa993b JM |
951 | else if ((op & 0xffff0000) == 0x3c000000) |
952 | { /* addis 0,0,NUM, used | |
953 | for >= 32k frames */ | |
954 | fdata->offset = (op & 0x0000ffff) << 16; | |
955 | fdata->frameless = 0; | |
773df3e5 | 956 | r0_contains_arg = 0; |
c5aa993b JM |
957 | continue; |
958 | ||
959 | } | |
960 | else if ((op & 0xffff0000) == 0x60000000) | |
961 | { /* ori 0,0,NUM, 2nd ha | |
962 | lf of >= 32k frames */ | |
963 | fdata->offset |= (op & 0x0000ffff); | |
964 | fdata->frameless = 0; | |
773df3e5 | 965 | r0_contains_arg = 0; |
c5aa993b JM |
966 | continue; |
967 | ||
968 | } | |
98f08d3d KB |
969 | else if (lr_reg != -1 && |
970 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ | |
971 | (((op & 0xffff0000) == (lr_reg | 0xf8010000)) || | |
972 | /* stw Rx, NUM(r1) */ | |
973 | ((op & 0xffff0000) == (lr_reg | 0x90010000)) || | |
974 | /* stwu Rx, NUM(r1) */ | |
975 | ((op & 0xffff0000) == (lr_reg | 0x94010000)))) | |
976 | { /* where Rx == lr */ | |
977 | fdata->lr_offset = offset; | |
c5aa993b JM |
978 | fdata->nosavedpc = 0; |
979 | lr_reg = 0; | |
98f08d3d KB |
980 | if ((op & 0xfc000003) == 0xf8000000 || /* std */ |
981 | (op & 0xfc000000) == 0x90000000) /* stw */ | |
982 | { | |
983 | /* Does not update r1, so add displacement to lr_offset. */ | |
984 | fdata->lr_offset += SIGNED_SHORT (op); | |
985 | } | |
c5aa993b JM |
986 | continue; |
987 | ||
988 | } | |
98f08d3d KB |
989 | else if (cr_reg != -1 && |
990 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ | |
991 | (((op & 0xffff0000) == (cr_reg | 0xf8010000)) || | |
992 | /* stw Rx, NUM(r1) */ | |
993 | ((op & 0xffff0000) == (cr_reg | 0x90010000)) || | |
994 | /* stwu Rx, NUM(r1) */ | |
995 | ((op & 0xffff0000) == (cr_reg | 0x94010000)))) | |
996 | { /* where Rx == cr */ | |
997 | fdata->cr_offset = offset; | |
c5aa993b | 998 | cr_reg = 0; |
98f08d3d KB |
999 | if ((op & 0xfc000003) == 0xf8000000 || |
1000 | (op & 0xfc000000) == 0x90000000) | |
1001 | { | |
1002 | /* Does not update r1, so add displacement to cr_offset. */ | |
1003 | fdata->cr_offset += SIGNED_SHORT (op); | |
1004 | } | |
c5aa993b JM |
1005 | continue; |
1006 | ||
1007 | } | |
1008 | else if (op == 0x48000005) | |
1009 | { /* bl .+4 used in | |
1010 | -mrelocatable */ | |
1011 | continue; | |
1012 | ||
1013 | } | |
1014 | else if (op == 0x48000004) | |
1015 | { /* b .+4 (xlc) */ | |
1016 | break; | |
1017 | ||
c5aa993b | 1018 | } |
6be8bc0c EZ |
1019 | else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used |
1020 | in V.4 -mminimal-toc */ | |
c5aa993b JM |
1021 | (op & 0xffff0000) == 0x3bde0000) |
1022 | { /* addi 30,30,foo@l */ | |
1023 | continue; | |
c906108c | 1024 | |
c5aa993b JM |
1025 | } |
1026 | else if ((op & 0xfc000001) == 0x48000001) | |
1027 | { /* bl foo, | |
1028 | to save fprs??? */ | |
c906108c | 1029 | |
c5aa993b | 1030 | fdata->frameless = 0; |
6be8bc0c EZ |
1031 | /* Don't skip over the subroutine call if it is not within |
1032 | the first three instructions of the prologue. */ | |
c5aa993b JM |
1033 | if ((pc - orig_pc) > 8) |
1034 | break; | |
1035 | ||
1036 | op = read_memory_integer (pc + 4, 4); | |
1037 | ||
6be8bc0c EZ |
1038 | /* At this point, make sure this is not a trampoline |
1039 | function (a function that simply calls another functions, | |
1040 | and nothing else). If the next is not a nop, this branch | |
1041 | was part of the function prologue. */ | |
c5aa993b JM |
1042 | |
1043 | if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ | |
1044 | break; /* don't skip over | |
1045 | this branch */ | |
1046 | continue; | |
1047 | ||
c5aa993b | 1048 | } |
98f08d3d KB |
1049 | /* update stack pointer */ |
1050 | else if ((op & 0xfc1f0000) == 0x94010000) | |
1051 | { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */ | |
c5aa993b JM |
1052 | fdata->frameless = 0; |
1053 | fdata->offset = SIGNED_SHORT (op); | |
1054 | offset = fdata->offset; | |
1055 | continue; | |
c5aa993b | 1056 | } |
98f08d3d KB |
1057 | else if ((op & 0xfc1f016a) == 0x7c01016e) |
1058 | { /* stwux rX,r1,rY */ | |
1059 | /* no way to figure out what r1 is going to be */ | |
1060 | fdata->frameless = 0; | |
1061 | offset = fdata->offset; | |
1062 | continue; | |
1063 | } | |
1064 | else if ((op & 0xfc1f0003) == 0xf8010001) | |
1065 | { /* stdu rX,NUM(r1) */ | |
1066 | fdata->frameless = 0; | |
1067 | fdata->offset = SIGNED_SHORT (op & ~3UL); | |
1068 | offset = fdata->offset; | |
1069 | continue; | |
1070 | } | |
1071 | else if ((op & 0xfc1f016a) == 0x7c01016a) | |
1072 | { /* stdux rX,r1,rY */ | |
1073 | /* no way to figure out what r1 is going to be */ | |
c5aa993b JM |
1074 | fdata->frameless = 0; |
1075 | offset = fdata->offset; | |
1076 | continue; | |
c5aa993b | 1077 | } |
98f08d3d KB |
1078 | /* Load up minimal toc pointer */ |
1079 | else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */ | |
1080 | (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */ | |
c5aa993b | 1081 | && !minimal_toc_loaded) |
98f08d3d | 1082 | { |
c5aa993b JM |
1083 | minimal_toc_loaded = 1; |
1084 | continue; | |
1085 | ||
f6077098 KB |
1086 | /* move parameters from argument registers to local variable |
1087 | registers */ | |
1088 | } | |
1089 | else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ | |
1090 | (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ | |
1091 | (((op >> 21) & 31) <= 10) && | |
96ff0de4 | 1092 | ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */ |
f6077098 KB |
1093 | { |
1094 | continue; | |
1095 | ||
c5aa993b JM |
1096 | /* store parameters in stack */ |
1097 | } | |
e802b915 | 1098 | /* Move parameters from argument registers to temporary register. */ |
773df3e5 | 1099 | else if (store_param_on_stack_p (op, framep, &r0_contains_arg)) |
e802b915 | 1100 | { |
c5aa993b JM |
1101 | continue; |
1102 | ||
1103 | /* Set up frame pointer */ | |
1104 | } | |
1105 | else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ | |
1106 | || op == 0x7c3f0b78) | |
1107 | { /* mr r31, r1 */ | |
1108 | fdata->frameless = 0; | |
1109 | framep = 1; | |
6f99cb26 | 1110 | fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); |
c5aa993b JM |
1111 | continue; |
1112 | ||
1113 | /* Another way to set up the frame pointer. */ | |
1114 | } | |
1115 | else if ((op & 0xfc1fffff) == 0x38010000) | |
1116 | { /* addi rX, r1, 0x0 */ | |
1117 | fdata->frameless = 0; | |
1118 | framep = 1; | |
6f99cb26 AC |
1119 | fdata->alloca_reg = (tdep->ppc_gp0_regnum |
1120 | + ((op & ~0x38010000) >> 21)); | |
c5aa993b | 1121 | continue; |
c5aa993b | 1122 | } |
6be8bc0c EZ |
1123 | /* AltiVec related instructions. */ |
1124 | /* Store the vrsave register (spr 256) in another register for | |
1125 | later manipulation, or load a register into the vrsave | |
1126 | register. 2 instructions are used: mfvrsave and | |
1127 | mtvrsave. They are shorthand notation for mfspr Rn, SPR256 | |
1128 | and mtspr SPR256, Rn. */ | |
1129 | /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 | |
1130 | mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ | |
1131 | else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ | |
1132 | { | |
1133 | vrsave_reg = GET_SRC_REG (op); | |
1134 | continue; | |
1135 | } | |
1136 | else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ | |
1137 | { | |
1138 | continue; | |
1139 | } | |
1140 | /* Store the register where vrsave was saved to onto the stack: | |
1141 | rS is the register where vrsave was stored in a previous | |
1142 | instruction. */ | |
1143 | /* 100100 sssss 00001 dddddddd dddddddd */ | |
1144 | else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ | |
1145 | { | |
1146 | if (vrsave_reg == GET_SRC_REG (op)) | |
1147 | { | |
1148 | fdata->vrsave_offset = SIGNED_SHORT (op) + offset; | |
1149 | vrsave_reg = -1; | |
1150 | } | |
1151 | continue; | |
1152 | } | |
1153 | /* Compute the new value of vrsave, by modifying the register | |
1154 | where vrsave was saved to. */ | |
1155 | else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ | |
1156 | || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ | |
1157 | { | |
1158 | continue; | |
1159 | } | |
1160 | /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first | |
1161 | in a pair of insns to save the vector registers on the | |
1162 | stack. */ | |
1163 | /* 001110 00000 00000 iiii iiii iiii iiii */ | |
96ff0de4 EZ |
1164 | /* 001110 01110 00000 iiii iiii iiii iiii */ |
1165 | else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ | |
1166 | || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ | |
6be8bc0c | 1167 | { |
773df3e5 JB |
1168 | if ((op & 0xffff0000) == 0x38000000) |
1169 | r0_contains_arg = 0; | |
6be8bc0c EZ |
1170 | li_found_pc = pc; |
1171 | vr_saved_offset = SIGNED_SHORT (op); | |
773df3e5 JB |
1172 | |
1173 | /* This insn by itself is not part of the prologue, unless | |
1174 | if part of the pair of insns mentioned above. So do not | |
1175 | record this insn as part of the prologue yet. */ | |
1176 | prev_insn_was_prologue_insn = 0; | |
6be8bc0c EZ |
1177 | } |
1178 | /* Store vector register S at (r31+r0) aligned to 16 bytes. */ | |
1179 | /* 011111 sssss 11111 00000 00111001110 */ | |
1180 | else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ | |
1181 | { | |
1182 | if (pc == (li_found_pc + 4)) | |
1183 | { | |
1184 | vr_reg = GET_SRC_REG (op); | |
1185 | /* If this is the first vector reg to be saved, or if | |
1186 | it has a lower number than others previously seen, | |
1187 | reupdate the frame info. */ | |
1188 | if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) | |
1189 | { | |
1190 | fdata->saved_vr = vr_reg; | |
1191 | fdata->vr_offset = vr_saved_offset + offset; | |
1192 | } | |
1193 | vr_saved_offset = -1; | |
1194 | vr_reg = -1; | |
1195 | li_found_pc = 0; | |
1196 | } | |
1197 | } | |
1198 | /* End AltiVec related instructions. */ | |
96ff0de4 EZ |
1199 | |
1200 | /* Start BookE related instructions. */ | |
1201 | /* Store gen register S at (r31+uimm). | |
1202 | Any register less than r13 is volatile, so we don't care. */ | |
1203 | /* 000100 sssss 11111 iiiii 01100100001 */ | |
1204 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1205 | && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ | |
1206 | { | |
1207 | if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ | |
1208 | { | |
1209 | unsigned int imm; | |
1210 | ev_reg = GET_SRC_REG (op); | |
1211 | imm = (op >> 11) & 0x1f; | |
1212 | ev_offset = imm * 8; | |
1213 | /* If this is the first vector reg to be saved, or if | |
1214 | it has a lower number than others previously seen, | |
1215 | reupdate the frame info. */ | |
1216 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1217 | { | |
1218 | fdata->saved_ev = ev_reg; | |
1219 | fdata->ev_offset = ev_offset + offset; | |
1220 | } | |
1221 | } | |
1222 | continue; | |
1223 | } | |
1224 | /* Store gen register rS at (r1+rB). */ | |
1225 | /* 000100 sssss 00001 bbbbb 01100100000 */ | |
1226 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1227 | && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ | |
1228 | { | |
1229 | if (pc == (li_found_pc + 4)) | |
1230 | { | |
1231 | ev_reg = GET_SRC_REG (op); | |
1232 | /* If this is the first vector reg to be saved, or if | |
1233 | it has a lower number than others previously seen, | |
1234 | reupdate the frame info. */ | |
1235 | /* We know the contents of rB from the previous instruction. */ | |
1236 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1237 | { | |
1238 | fdata->saved_ev = ev_reg; | |
1239 | fdata->ev_offset = vr_saved_offset + offset; | |
1240 | } | |
1241 | vr_saved_offset = -1; | |
1242 | ev_reg = -1; | |
1243 | li_found_pc = 0; | |
1244 | } | |
1245 | continue; | |
1246 | } | |
1247 | /* Store gen register r31 at (rA+uimm). */ | |
1248 | /* 000100 11111 aaaaa iiiii 01100100001 */ | |
1249 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1250 | && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ | |
1251 | { | |
1252 | /* Wwe know that the source register is 31 already, but | |
1253 | it can't hurt to compute it. */ | |
1254 | ev_reg = GET_SRC_REG (op); | |
1255 | ev_offset = ((op >> 11) & 0x1f) * 8; | |
1256 | /* If this is the first vector reg to be saved, or if | |
1257 | it has a lower number than others previously seen, | |
1258 | reupdate the frame info. */ | |
1259 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1260 | { | |
1261 | fdata->saved_ev = ev_reg; | |
1262 | fdata->ev_offset = ev_offset + offset; | |
1263 | } | |
1264 | ||
1265 | continue; | |
1266 | } | |
1267 | /* Store gen register S at (r31+r0). | |
1268 | Store param on stack when offset from SP bigger than 4 bytes. */ | |
1269 | /* 000100 sssss 11111 00000 01100100000 */ | |
1270 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1271 | && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ | |
1272 | { | |
1273 | if (pc == (li_found_pc + 4)) | |
1274 | { | |
1275 | if ((op & 0x03e00000) >= 0x01a00000) | |
1276 | { | |
1277 | ev_reg = GET_SRC_REG (op); | |
1278 | /* If this is the first vector reg to be saved, or if | |
1279 | it has a lower number than others previously seen, | |
1280 | reupdate the frame info. */ | |
1281 | /* We know the contents of r0 from the previous | |
1282 | instruction. */ | |
1283 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1284 | { | |
1285 | fdata->saved_ev = ev_reg; | |
1286 | fdata->ev_offset = vr_saved_offset + offset; | |
1287 | } | |
1288 | ev_reg = -1; | |
1289 | } | |
1290 | vr_saved_offset = -1; | |
1291 | li_found_pc = 0; | |
1292 | continue; | |
1293 | } | |
1294 | } | |
1295 | /* End BookE related instructions. */ | |
1296 | ||
c5aa993b JM |
1297 | else |
1298 | { | |
55d05f3b KB |
1299 | /* Not a recognized prologue instruction. |
1300 | Handle optimizer code motions into the prologue by continuing | |
1301 | the search if we have no valid frame yet or if the return | |
1302 | address is not yet saved in the frame. */ | |
1303 | if (fdata->frameless == 0 | |
1304 | && (lr_reg == -1 || fdata->nosavedpc == 0)) | |
1305 | break; | |
1306 | ||
1307 | if (op == 0x4e800020 /* blr */ | |
1308 | || op == 0x4e800420) /* bctr */ | |
1309 | /* Do not scan past epilogue in frameless functions or | |
1310 | trampolines. */ | |
1311 | break; | |
1312 | if ((op & 0xf4000000) == 0x40000000) /* bxx */ | |
64366f1c | 1313 | /* Never skip branches. */ |
55d05f3b KB |
1314 | break; |
1315 | ||
1316 | if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) | |
1317 | /* Do not scan too many insns, scanning insns is expensive with | |
1318 | remote targets. */ | |
1319 | break; | |
1320 | ||
1321 | /* Continue scanning. */ | |
1322 | prev_insn_was_prologue_insn = 0; | |
1323 | continue; | |
c5aa993b | 1324 | } |
c906108c SS |
1325 | } |
1326 | ||
1327 | #if 0 | |
1328 | /* I have problems with skipping over __main() that I need to address | |
1329 | * sometime. Previously, I used to use misc_function_vector which | |
1330 | * didn't work as well as I wanted to be. -MGO */ | |
1331 | ||
1332 | /* If the first thing after skipping a prolog is a branch to a function, | |
1333 | this might be a call to an initializer in main(), introduced by gcc2. | |
64366f1c | 1334 | We'd like to skip over it as well. Fortunately, xlc does some extra |
c906108c | 1335 | work before calling a function right after a prologue, thus we can |
64366f1c | 1336 | single out such gcc2 behaviour. */ |
c906108c | 1337 | |
c906108c | 1338 | |
c5aa993b JM |
1339 | if ((op & 0xfc000001) == 0x48000001) |
1340 | { /* bl foo, an initializer function? */ | |
1341 | op = read_memory_integer (pc + 4, 4); | |
1342 | ||
1343 | if (op == 0x4def7b82) | |
1344 | { /* cror 0xf, 0xf, 0xf (nop) */ | |
c906108c | 1345 | |
64366f1c EZ |
1346 | /* Check and see if we are in main. If so, skip over this |
1347 | initializer function as well. */ | |
c906108c | 1348 | |
c5aa993b | 1349 | tmp = find_pc_misc_function (pc); |
6314a349 AC |
1350 | if (tmp >= 0 |
1351 | && strcmp (misc_function_vector[tmp].name, main_name ()) == 0) | |
c5aa993b JM |
1352 | return pc + 8; |
1353 | } | |
c906108c | 1354 | } |
c906108c | 1355 | #endif /* 0 */ |
c5aa993b JM |
1356 | |
1357 | fdata->offset = -fdata->offset; | |
ddb20c56 | 1358 | return last_prologue_pc; |
c906108c SS |
1359 | } |
1360 | ||
1361 | ||
1362 | /************************************************************************* | |
f6077098 | 1363 | Support for creating pushing a dummy frame into the stack, and popping |
c906108c SS |
1364 | frames, etc. |
1365 | *************************************************************************/ | |
1366 | ||
c906108c | 1367 | |
11269d7e AC |
1368 | /* All the ABI's require 16 byte alignment. */ |
1369 | static CORE_ADDR | |
1370 | rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
1371 | { | |
1372 | return (addr & -16); | |
1373 | } | |
1374 | ||
7a78ae4e | 1375 | /* Pass the arguments in either registers, or in the stack. In RS/6000, |
c906108c SS |
1376 | the first eight words of the argument list (that might be less than |
1377 | eight parameters if some parameters occupy more than one word) are | |
7a78ae4e | 1378 | passed in r3..r10 registers. float and double parameters are |
64366f1c EZ |
1379 | passed in fpr's, in addition to that. Rest of the parameters if any |
1380 | are passed in user stack. There might be cases in which half of the | |
c906108c SS |
1381 | parameter is copied into registers, the other half is pushed into |
1382 | stack. | |
1383 | ||
7a78ae4e ND |
1384 | Stack must be aligned on 64-bit boundaries when synthesizing |
1385 | function calls. | |
1386 | ||
c906108c SS |
1387 | If the function is returning a structure, then the return address is passed |
1388 | in r3, then the first 7 words of the parameters can be passed in registers, | |
64366f1c | 1389 | starting from r4. */ |
c906108c | 1390 | |
7a78ae4e | 1391 | static CORE_ADDR |
7d9b040b | 1392 | rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
77b2b6d4 AC |
1393 | struct regcache *regcache, CORE_ADDR bp_addr, |
1394 | int nargs, struct value **args, CORE_ADDR sp, | |
1395 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 1396 | { |
7a41266b | 1397 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
1398 | int ii; |
1399 | int len = 0; | |
c5aa993b JM |
1400 | int argno; /* current argument number */ |
1401 | int argbytes; /* current argument byte */ | |
1402 | char tmp_buffer[50]; | |
1403 | int f_argno = 0; /* current floating point argno */ | |
21283beb | 1404 | int wordsize = gdbarch_tdep (current_gdbarch)->wordsize; |
7d9b040b | 1405 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
c906108c | 1406 | |
ea7c478f | 1407 | struct value *arg = 0; |
c906108c SS |
1408 | struct type *type; |
1409 | ||
1410 | CORE_ADDR saved_sp; | |
1411 | ||
383f0f5b JB |
1412 | /* The calling convention this function implements assumes the |
1413 | processor has floating-point registers. We shouldn't be using it | |
1414 | on PPC variants that lack them. */ | |
1415 | gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); | |
1416 | ||
64366f1c | 1417 | /* The first eight words of ther arguments are passed in registers. |
7a41266b AC |
1418 | Copy them appropriately. */ |
1419 | ii = 0; | |
1420 | ||
1421 | /* If the function is returning a `struct', then the first word | |
1422 | (which will be passed in r3) is used for struct return address. | |
1423 | In that case we should advance one word and start from r4 | |
1424 | register to copy parameters. */ | |
1425 | if (struct_return) | |
1426 | { | |
1427 | regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3, | |
1428 | struct_addr); | |
1429 | ii++; | |
1430 | } | |
c906108c SS |
1431 | |
1432 | /* | |
c5aa993b JM |
1433 | effectively indirect call... gcc does... |
1434 | ||
1435 | return_val example( float, int); | |
1436 | ||
1437 | eabi: | |
1438 | float in fp0, int in r3 | |
1439 | offset of stack on overflow 8/16 | |
1440 | for varargs, must go by type. | |
1441 | power open: | |
1442 | float in r3&r4, int in r5 | |
1443 | offset of stack on overflow different | |
1444 | both: | |
1445 | return in r3 or f0. If no float, must study how gcc emulates floats; | |
1446 | pay attention to arg promotion. | |
1447 | User may have to cast\args to handle promotion correctly | |
1448 | since gdb won't know if prototype supplied or not. | |
1449 | */ | |
c906108c | 1450 | |
c5aa993b JM |
1451 | for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii) |
1452 | { | |
3acba339 | 1453 | int reg_size = register_size (current_gdbarch, ii + 3); |
c5aa993b JM |
1454 | |
1455 | arg = args[argno]; | |
1456 | type = check_typedef (VALUE_TYPE (arg)); | |
1457 | len = TYPE_LENGTH (type); | |
1458 | ||
1459 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1460 | { | |
1461 | ||
64366f1c | 1462 | /* Floating point arguments are passed in fpr's, as well as gpr's. |
c5aa993b | 1463 | There are 13 fpr's reserved for passing parameters. At this point |
64366f1c | 1464 | there is no way we would run out of them. */ |
c5aa993b JM |
1465 | |
1466 | if (len > 8) | |
c2b6b4aa JB |
1467 | printf_unfiltered ("Fatal Error: a floating point parameter " |
1468 | "#%d with a size > 8 is found!\n", argno); | |
c5aa993b | 1469 | |
366f009f JB |
1470 | memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE |
1471 | (tdep->ppc_fp0_regnum + 1 + f_argno)], | |
c5aa993b JM |
1472 | VALUE_CONTENTS (arg), |
1473 | len); | |
1474 | ++f_argno; | |
1475 | } | |
1476 | ||
f6077098 | 1477 | if (len > reg_size) |
c5aa993b JM |
1478 | { |
1479 | ||
64366f1c | 1480 | /* Argument takes more than one register. */ |
c5aa993b JM |
1481 | while (argbytes < len) |
1482 | { | |
62700349 | 1483 | memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, |
524d7c18 | 1484 | reg_size); |
62700349 | 1485 | memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], |
c5aa993b | 1486 | ((char *) VALUE_CONTENTS (arg)) + argbytes, |
f6077098 KB |
1487 | (len - argbytes) > reg_size |
1488 | ? reg_size : len - argbytes); | |
1489 | ++ii, argbytes += reg_size; | |
c5aa993b JM |
1490 | |
1491 | if (ii >= 8) | |
1492 | goto ran_out_of_registers_for_arguments; | |
1493 | } | |
1494 | argbytes = 0; | |
1495 | --ii; | |
1496 | } | |
1497 | else | |
64366f1c EZ |
1498 | { |
1499 | /* Argument can fit in one register. No problem. */ | |
d7449b42 | 1500 | int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0; |
62700349 AC |
1501 | memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, reg_size); |
1502 | memcpy ((char *)&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)] + adj, | |
f6077098 | 1503 | VALUE_CONTENTS (arg), len); |
c5aa993b JM |
1504 | } |
1505 | ++argno; | |
c906108c | 1506 | } |
c906108c SS |
1507 | |
1508 | ran_out_of_registers_for_arguments: | |
1509 | ||
7a78ae4e | 1510 | saved_sp = read_sp (); |
cc9836a8 | 1511 | |
64366f1c | 1512 | /* Location for 8 parameters are always reserved. */ |
7a78ae4e | 1513 | sp -= wordsize * 8; |
f6077098 | 1514 | |
64366f1c | 1515 | /* Another six words for back chain, TOC register, link register, etc. */ |
7a78ae4e | 1516 | sp -= wordsize * 6; |
f6077098 | 1517 | |
64366f1c | 1518 | /* Stack pointer must be quadword aligned. */ |
7a78ae4e | 1519 | sp &= -16; |
c906108c | 1520 | |
64366f1c EZ |
1521 | /* If there are more arguments, allocate space for them in |
1522 | the stack, then push them starting from the ninth one. */ | |
c906108c | 1523 | |
c5aa993b JM |
1524 | if ((argno < nargs) || argbytes) |
1525 | { | |
1526 | int space = 0, jj; | |
c906108c | 1527 | |
c5aa993b JM |
1528 | if (argbytes) |
1529 | { | |
1530 | space += ((len - argbytes + 3) & -4); | |
1531 | jj = argno + 1; | |
1532 | } | |
1533 | else | |
1534 | jj = argno; | |
c906108c | 1535 | |
c5aa993b JM |
1536 | for (; jj < nargs; ++jj) |
1537 | { | |
ea7c478f | 1538 | struct value *val = args[jj]; |
c5aa993b JM |
1539 | space += ((TYPE_LENGTH (VALUE_TYPE (val))) + 3) & -4; |
1540 | } | |
c906108c | 1541 | |
64366f1c | 1542 | /* Add location required for the rest of the parameters. */ |
f6077098 | 1543 | space = (space + 15) & -16; |
c5aa993b | 1544 | sp -= space; |
c906108c | 1545 | |
7aea86e6 AC |
1546 | /* This is another instance we need to be concerned about |
1547 | securing our stack space. If we write anything underneath %sp | |
1548 | (r1), we might conflict with the kernel who thinks he is free | |
1549 | to use this area. So, update %sp first before doing anything | |
1550 | else. */ | |
1551 | ||
1552 | regcache_raw_write_signed (regcache, SP_REGNUM, sp); | |
1553 | ||
64366f1c EZ |
1554 | /* If the last argument copied into the registers didn't fit there |
1555 | completely, push the rest of it into stack. */ | |
c906108c | 1556 | |
c5aa993b JM |
1557 | if (argbytes) |
1558 | { | |
1559 | write_memory (sp + 24 + (ii * 4), | |
1560 | ((char *) VALUE_CONTENTS (arg)) + argbytes, | |
1561 | len - argbytes); | |
1562 | ++argno; | |
1563 | ii += ((len - argbytes + 3) & -4) / 4; | |
1564 | } | |
c906108c | 1565 | |
64366f1c | 1566 | /* Push the rest of the arguments into stack. */ |
c5aa993b JM |
1567 | for (; argno < nargs; ++argno) |
1568 | { | |
c906108c | 1569 | |
c5aa993b JM |
1570 | arg = args[argno]; |
1571 | type = check_typedef (VALUE_TYPE (arg)); | |
1572 | len = TYPE_LENGTH (type); | |
c906108c SS |
1573 | |
1574 | ||
64366f1c EZ |
1575 | /* Float types should be passed in fpr's, as well as in the |
1576 | stack. */ | |
c5aa993b JM |
1577 | if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13) |
1578 | { | |
c906108c | 1579 | |
c5aa993b | 1580 | if (len > 8) |
c2b6b4aa JB |
1581 | printf_unfiltered ("Fatal Error: a floating point parameter" |
1582 | " #%d with a size > 8 is found!\n", argno); | |
c906108c | 1583 | |
366f009f JB |
1584 | memcpy (&(deprecated_registers |
1585 | [DEPRECATED_REGISTER_BYTE | |
1586 | (tdep->ppc_fp0_regnum + 1 + f_argno)]), | |
c5aa993b JM |
1587 | VALUE_CONTENTS (arg), |
1588 | len); | |
1589 | ++f_argno; | |
1590 | } | |
c906108c | 1591 | |
c2b6b4aa JB |
1592 | write_memory (sp + 24 + (ii * 4), |
1593 | (char *) VALUE_CONTENTS (arg), | |
1594 | len); | |
c5aa993b JM |
1595 | ii += ((len + 3) & -4) / 4; |
1596 | } | |
c906108c | 1597 | } |
c906108c | 1598 | |
69517000 | 1599 | /* Set the stack pointer. According to the ABI, the SP is meant to |
7aea86e6 AC |
1600 | be set _before_ the corresponding stack space is used. On AIX, |
1601 | this even applies when the target has been completely stopped! | |
1602 | Not doing this can lead to conflicts with the kernel which thinks | |
1603 | that it still has control over this not-yet-allocated stack | |
1604 | region. */ | |
33a7c2fc AC |
1605 | regcache_raw_write_signed (regcache, SP_REGNUM, sp); |
1606 | ||
7aea86e6 AC |
1607 | /* Set back chain properly. */ |
1608 | store_unsigned_integer (tmp_buffer, 4, saved_sp); | |
1609 | write_memory (sp, tmp_buffer, 4); | |
1610 | ||
e56a0ecc AC |
1611 | /* Point the inferior function call's return address at the dummy's |
1612 | breakpoint. */ | |
1613 | regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr); | |
1614 | ||
794a477a AC |
1615 | /* Set the TOC register, get the value from the objfile reader |
1616 | which, in turn, gets it from the VMAP table. */ | |
1617 | if (rs6000_find_toc_address_hook != NULL) | |
1618 | { | |
1619 | CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr); | |
1620 | regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue); | |
1621 | } | |
1622 | ||
c906108c SS |
1623 | target_store_registers (-1); |
1624 | return sp; | |
1625 | } | |
c906108c | 1626 | |
b9ff3018 AC |
1627 | /* PowerOpen always puts structures in memory. Vectors, which were |
1628 | added later, do get returned in a register though. */ | |
1629 | ||
1630 | static int | |
1631 | rs6000_use_struct_convention (int gcc_p, struct type *value_type) | |
1632 | { | |
1633 | if ((TYPE_LENGTH (value_type) == 16 || TYPE_LENGTH (value_type) == 8) | |
1634 | && TYPE_VECTOR (value_type)) | |
1635 | return 0; | |
1636 | return 1; | |
1637 | } | |
1638 | ||
7a78ae4e ND |
1639 | static void |
1640 | rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf) | |
c906108c SS |
1641 | { |
1642 | int offset = 0; | |
ace1378a | 1643 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 1644 | |
383f0f5b JB |
1645 | /* The calling convention this function implements assumes the |
1646 | processor has floating-point registers. We shouldn't be using it | |
1647 | on PPC variants that lack them. */ | |
1648 | gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); | |
1649 | ||
c5aa993b JM |
1650 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT) |
1651 | { | |
c906108c | 1652 | |
c5aa993b JM |
1653 | /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes. |
1654 | We need to truncate the return value into float size (4 byte) if | |
64366f1c | 1655 | necessary. */ |
c906108c | 1656 | |
65951cd9 | 1657 | convert_typed_floating (®buf[DEPRECATED_REGISTER_BYTE |
366f009f | 1658 | (tdep->ppc_fp0_regnum + 1)], |
65951cd9 JG |
1659 | builtin_type_double, |
1660 | valbuf, | |
1661 | valtype); | |
c5aa993b | 1662 | } |
ace1378a EZ |
1663 | else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY |
1664 | && TYPE_LENGTH (valtype) == 16 | |
1665 | && TYPE_VECTOR (valtype)) | |
1666 | { | |
62700349 | 1667 | memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2), |
ace1378a EZ |
1668 | TYPE_LENGTH (valtype)); |
1669 | } | |
c5aa993b JM |
1670 | else |
1671 | { | |
1672 | /* return value is copied starting from r3. */ | |
d7449b42 | 1673 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
3acba339 AC |
1674 | && TYPE_LENGTH (valtype) < register_size (current_gdbarch, 3)) |
1675 | offset = register_size (current_gdbarch, 3) - TYPE_LENGTH (valtype); | |
c5aa993b JM |
1676 | |
1677 | memcpy (valbuf, | |
62700349 | 1678 | regbuf + DEPRECATED_REGISTER_BYTE (3) + offset, |
c906108c | 1679 | TYPE_LENGTH (valtype)); |
c906108c | 1680 | } |
c906108c SS |
1681 | } |
1682 | ||
977adac5 ND |
1683 | /* Return whether handle_inferior_event() should proceed through code |
1684 | starting at PC in function NAME when stepping. | |
1685 | ||
1686 | The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to | |
1687 | handle memory references that are too distant to fit in instructions | |
1688 | generated by the compiler. For example, if 'foo' in the following | |
1689 | instruction: | |
1690 | ||
1691 | lwz r9,foo(r2) | |
1692 | ||
1693 | is greater than 32767, the linker might replace the lwz with a branch to | |
1694 | somewhere in @FIX1 that does the load in 2 instructions and then branches | |
1695 | back to where execution should continue. | |
1696 | ||
1697 | GDB should silently step over @FIX code, just like AIX dbx does. | |
1698 | Unfortunately, the linker uses the "b" instruction for the branches, | |
1699 | meaning that the link register doesn't get set. Therefore, GDB's usual | |
1700 | step_over_function() mechanism won't work. | |
1701 | ||
1702 | Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks | |
1703 | in handle_inferior_event() to skip past @FIX code. */ | |
1704 | ||
1705 | int | |
1706 | rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name) | |
1707 | { | |
1708 | return name && !strncmp (name, "@FIX", 4); | |
1709 | } | |
1710 | ||
1711 | /* Skip code that the user doesn't want to see when stepping: | |
1712 | ||
1713 | 1. Indirect function calls use a piece of trampoline code to do context | |
1714 | switching, i.e. to set the new TOC table. Skip such code if we are on | |
1715 | its first instruction (as when we have single-stepped to here). | |
1716 | ||
1717 | 2. Skip shared library trampoline code (which is different from | |
c906108c | 1718 | indirect function call trampolines). |
977adac5 ND |
1719 | |
1720 | 3. Skip bigtoc fixup code. | |
1721 | ||
c906108c | 1722 | Result is desired PC to step until, or NULL if we are not in |
977adac5 | 1723 | code that should be skipped. */ |
c906108c SS |
1724 | |
1725 | CORE_ADDR | |
7a78ae4e | 1726 | rs6000_skip_trampoline_code (CORE_ADDR pc) |
c906108c | 1727 | { |
52f0bd74 | 1728 | unsigned int ii, op; |
977adac5 | 1729 | int rel; |
c906108c | 1730 | CORE_ADDR solib_target_pc; |
977adac5 | 1731 | struct minimal_symbol *msymbol; |
c906108c | 1732 | |
c5aa993b JM |
1733 | static unsigned trampoline_code[] = |
1734 | { | |
1735 | 0x800b0000, /* l r0,0x0(r11) */ | |
1736 | 0x90410014, /* st r2,0x14(r1) */ | |
1737 | 0x7c0903a6, /* mtctr r0 */ | |
1738 | 0x804b0004, /* l r2,0x4(r11) */ | |
1739 | 0x816b0008, /* l r11,0x8(r11) */ | |
1740 | 0x4e800420, /* bctr */ | |
1741 | 0x4e800020, /* br */ | |
1742 | 0 | |
c906108c SS |
1743 | }; |
1744 | ||
977adac5 ND |
1745 | /* Check for bigtoc fixup code. */ |
1746 | msymbol = lookup_minimal_symbol_by_pc (pc); | |
22abf04a | 1747 | if (msymbol && rs6000_in_solib_return_trampoline (pc, DEPRECATED_SYMBOL_NAME (msymbol))) |
977adac5 ND |
1748 | { |
1749 | /* Double-check that the third instruction from PC is relative "b". */ | |
1750 | op = read_memory_integer (pc + 8, 4); | |
1751 | if ((op & 0xfc000003) == 0x48000000) | |
1752 | { | |
1753 | /* Extract bits 6-29 as a signed 24-bit relative word address and | |
1754 | add it to the containing PC. */ | |
1755 | rel = ((int)(op << 6) >> 6); | |
1756 | return pc + 8 + rel; | |
1757 | } | |
1758 | } | |
1759 | ||
c906108c SS |
1760 | /* If pc is in a shared library trampoline, return its target. */ |
1761 | solib_target_pc = find_solib_trampoline_target (pc); | |
1762 | if (solib_target_pc) | |
1763 | return solib_target_pc; | |
1764 | ||
c5aa993b JM |
1765 | for (ii = 0; trampoline_code[ii]; ++ii) |
1766 | { | |
1767 | op = read_memory_integer (pc + (ii * 4), 4); | |
1768 | if (op != trampoline_code[ii]) | |
1769 | return 0; | |
1770 | } | |
1771 | ii = read_register (11); /* r11 holds destination addr */ | |
21283beb | 1772 | pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */ |
c906108c SS |
1773 | return pc; |
1774 | } | |
1775 | ||
7a78ae4e | 1776 | /* Return the size of register REG when words are WORDSIZE bytes long. If REG |
64366f1c | 1777 | isn't available with that word size, return 0. */ |
7a78ae4e ND |
1778 | |
1779 | static int | |
1780 | regsize (const struct reg *reg, int wordsize) | |
1781 | { | |
1782 | return wordsize == 8 ? reg->sz64 : reg->sz32; | |
1783 | } | |
1784 | ||
1785 | /* Return the name of register number N, or null if no such register exists | |
64366f1c | 1786 | in the current architecture. */ |
7a78ae4e | 1787 | |
fa88f677 | 1788 | static const char * |
7a78ae4e ND |
1789 | rs6000_register_name (int n) |
1790 | { | |
21283beb | 1791 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
1792 | const struct reg *reg = tdep->regs + n; |
1793 | ||
1794 | if (!regsize (reg, tdep->wordsize)) | |
1795 | return NULL; | |
1796 | return reg->name; | |
1797 | } | |
1798 | ||
7a78ae4e ND |
1799 | /* Return the GDB type object for the "standard" data type |
1800 | of data in register N. */ | |
1801 | ||
1802 | static struct type * | |
691d145a | 1803 | rs6000_register_type (struct gdbarch *gdbarch, int n) |
7a78ae4e | 1804 | { |
691d145a | 1805 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a78ae4e ND |
1806 | const struct reg *reg = tdep->regs + n; |
1807 | ||
1fcc0bb8 EZ |
1808 | if (reg->fpr) |
1809 | return builtin_type_double; | |
1810 | else | |
1811 | { | |
1812 | int size = regsize (reg, tdep->wordsize); | |
1813 | switch (size) | |
1814 | { | |
449a5da4 AC |
1815 | case 0: |
1816 | return builtin_type_int0; | |
1817 | case 4: | |
ed6edd9b | 1818 | return builtin_type_uint32; |
1fcc0bb8 | 1819 | case 8: |
c8001721 EZ |
1820 | if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum) |
1821 | return builtin_type_vec64; | |
1822 | else | |
ed6edd9b | 1823 | return builtin_type_uint64; |
1fcc0bb8 EZ |
1824 | break; |
1825 | case 16: | |
08cf96df | 1826 | return builtin_type_vec128; |
1fcc0bb8 EZ |
1827 | break; |
1828 | default: | |
449a5da4 AC |
1829 | internal_error (__FILE__, __LINE__, "Register %d size %d unknown", |
1830 | n, size); | |
1fcc0bb8 EZ |
1831 | } |
1832 | } | |
7a78ae4e ND |
1833 | } |
1834 | ||
691d145a | 1835 | /* The register format for RS/6000 floating point registers is always |
64366f1c | 1836 | double, we need a conversion if the memory format is float. */ |
7a78ae4e ND |
1837 | |
1838 | static int | |
691d145a | 1839 | rs6000_convert_register_p (int regnum, struct type *type) |
7a78ae4e | 1840 | { |
691d145a JB |
1841 | const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; |
1842 | ||
1843 | return (reg->fpr | |
1844 | && TYPE_CODE (type) == TYPE_CODE_FLT | |
1845 | && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double)); | |
7a78ae4e ND |
1846 | } |
1847 | ||
7a78ae4e | 1848 | static void |
691d145a JB |
1849 | rs6000_register_to_value (struct frame_info *frame, |
1850 | int regnum, | |
1851 | struct type *type, | |
1852 | void *to) | |
7a78ae4e | 1853 | { |
691d145a JB |
1854 | const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; |
1855 | char from[MAX_REGISTER_SIZE]; | |
1856 | ||
1857 | gdb_assert (reg->fpr); | |
1858 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); | |
7a78ae4e | 1859 | |
691d145a JB |
1860 | get_frame_register (frame, regnum, from); |
1861 | convert_typed_floating (from, builtin_type_double, to, type); | |
1862 | } | |
7a292a7a | 1863 | |
7a78ae4e | 1864 | static void |
691d145a JB |
1865 | rs6000_value_to_register (struct frame_info *frame, |
1866 | int regnum, | |
1867 | struct type *type, | |
1868 | const void *from) | |
7a78ae4e | 1869 | { |
691d145a JB |
1870 | const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; |
1871 | char to[MAX_REGISTER_SIZE]; | |
1872 | ||
1873 | gdb_assert (reg->fpr); | |
1874 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); | |
1875 | ||
1876 | convert_typed_floating (from, type, to, builtin_type_double); | |
1877 | put_frame_register (frame, regnum, to); | |
7a78ae4e | 1878 | } |
c906108c | 1879 | |
6ced10dd JB |
1880 | /* Move SPE vector register values between a 64-bit buffer and the two |
1881 | 32-bit raw register halves in a regcache. This function handles | |
1882 | both splitting a 64-bit value into two 32-bit halves, and joining | |
1883 | two halves into a whole 64-bit value, depending on the function | |
1884 | passed as the MOVE argument. | |
1885 | ||
1886 | EV_REG must be the number of an SPE evN vector register --- a | |
1887 | pseudoregister. REGCACHE must be a regcache, and BUFFER must be a | |
1888 | 64-bit buffer. | |
1889 | ||
1890 | Call MOVE once for each 32-bit half of that register, passing | |
1891 | REGCACHE, the number of the raw register corresponding to that | |
1892 | half, and the address of the appropriate half of BUFFER. | |
1893 | ||
1894 | For example, passing 'regcache_raw_read' as the MOVE function will | |
1895 | fill BUFFER with the full 64-bit contents of EV_REG. Or, passing | |
1896 | 'regcache_raw_supply' will supply the contents of BUFFER to the | |
1897 | appropriate pair of raw registers in REGCACHE. | |
1898 | ||
1899 | You may need to cast away some 'const' qualifiers when passing | |
1900 | MOVE, since this function can't tell at compile-time which of | |
1901 | REGCACHE or BUFFER is acting as the source of the data. If C had | |
1902 | co-variant type qualifiers, ... */ | |
1903 | static void | |
1904 | e500_move_ev_register (void (*move) (struct regcache *regcache, | |
1905 | int regnum, void *buf), | |
1906 | struct regcache *regcache, int ev_reg, | |
1907 | void *buffer) | |
1908 | { | |
1909 | struct gdbarch *arch = get_regcache_arch (regcache); | |
1910 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
1911 | int reg_index; | |
1912 | char *byte_buffer = buffer; | |
1913 | ||
1914 | gdb_assert (tdep->ppc_ev0_regnum <= ev_reg | |
1915 | && ev_reg < tdep->ppc_ev0_regnum + ppc_num_gprs); | |
1916 | ||
1917 | reg_index = ev_reg - tdep->ppc_ev0_regnum; | |
1918 | ||
1919 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1920 | { | |
1921 | move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer); | |
1922 | move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4); | |
1923 | } | |
1924 | else | |
1925 | { | |
1926 | move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer); | |
1927 | move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4); | |
1928 | } | |
1929 | } | |
1930 | ||
c8001721 EZ |
1931 | static void |
1932 | e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
1933 | int reg_nr, void *buffer) | |
1934 | { | |
6ced10dd | 1935 | struct gdbarch *regcache_arch = get_regcache_arch (regcache); |
c8001721 EZ |
1936 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1937 | ||
6ced10dd JB |
1938 | gdb_assert (regcache_arch == gdbarch); |
1939 | ||
1940 | if (tdep->ppc_ev0_regnum <= reg_nr | |
1941 | && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs) | |
1942 | e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer); | |
1943 | else | |
a44bddec JB |
1944 | internal_error (__FILE__, __LINE__, |
1945 | "e500_pseudo_register_read: " | |
1946 | "called on unexpected register '%s' (%d)", | |
1947 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); | |
c8001721 EZ |
1948 | } |
1949 | ||
1950 | static void | |
1951 | e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
1952 | int reg_nr, const void *buffer) | |
1953 | { | |
6ced10dd | 1954 | struct gdbarch *regcache_arch = get_regcache_arch (regcache); |
c8001721 EZ |
1955 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1956 | ||
6ced10dd JB |
1957 | gdb_assert (regcache_arch == gdbarch); |
1958 | ||
1959 | if (tdep->ppc_ev0_regnum <= reg_nr | |
1960 | && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs) | |
1961 | e500_move_ev_register ((void (*) (struct regcache *, int, void *)) | |
1962 | regcache_raw_write, | |
1963 | regcache, reg_nr, (void *) buffer); | |
1964 | else | |
a44bddec JB |
1965 | internal_error (__FILE__, __LINE__, |
1966 | "e500_pseudo_register_read: " | |
1967 | "called on unexpected register '%s' (%d)", | |
1968 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); | |
6ced10dd JB |
1969 | } |
1970 | ||
1971 | /* The E500 needs a custom reggroup function: it has anonymous raw | |
1972 | registers, and default_register_reggroup_p assumes that anonymous | |
1973 | registers are not members of any reggroup. */ | |
1974 | static int | |
1975 | e500_register_reggroup_p (struct gdbarch *gdbarch, | |
1976 | int regnum, | |
1977 | struct reggroup *group) | |
1978 | { | |
1979 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1980 | ||
1981 | /* The save and restore register groups need to include the | |
1982 | upper-half registers, even though they're anonymous. */ | |
1983 | if ((group == save_reggroup | |
1984 | || group == restore_reggroup) | |
1985 | && (tdep->ppc_ev0_upper_regnum <= regnum | |
1986 | && regnum < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)) | |
1987 | return 1; | |
1988 | ||
1989 | /* In all other regards, the default reggroup definition is fine. */ | |
1990 | return default_register_reggroup_p (gdbarch, regnum, group); | |
c8001721 EZ |
1991 | } |
1992 | ||
18ed0c4e | 1993 | /* Convert a DBX STABS register number to a GDB register number. */ |
c8001721 | 1994 | static int |
18ed0c4e | 1995 | rs6000_stab_reg_to_regnum (int num) |
c8001721 | 1996 | { |
9f744501 | 1997 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c8001721 | 1998 | |
9f744501 JB |
1999 | if (0 <= num && num <= 31) |
2000 | return tdep->ppc_gp0_regnum + num; | |
2001 | else if (32 <= num && num <= 63) | |
383f0f5b JB |
2002 | /* FIXME: jimb/2004-05-05: What should we do when the debug info |
2003 | specifies registers the architecture doesn't have? Our | |
2004 | callers don't check the value we return. */ | |
366f009f | 2005 | return tdep->ppc_fp0_regnum + (num - 32); |
18ed0c4e JB |
2006 | else if (77 <= num && num <= 108) |
2007 | return tdep->ppc_vr0_regnum + (num - 77); | |
9f744501 JB |
2008 | else if (1200 <= num && num < 1200 + 32) |
2009 | return tdep->ppc_ev0_regnum + (num - 1200); | |
2010 | else | |
2011 | switch (num) | |
2012 | { | |
2013 | case 64: | |
2014 | return tdep->ppc_mq_regnum; | |
2015 | case 65: | |
2016 | return tdep->ppc_lr_regnum; | |
2017 | case 66: | |
2018 | return tdep->ppc_ctr_regnum; | |
2019 | case 76: | |
2020 | return tdep->ppc_xer_regnum; | |
2021 | case 109: | |
2022 | return tdep->ppc_vrsave_regnum; | |
18ed0c4e JB |
2023 | case 110: |
2024 | return tdep->ppc_vrsave_regnum - 1; /* vscr */ | |
867e2dc5 | 2025 | case 111: |
18ed0c4e | 2026 | return tdep->ppc_acc_regnum; |
867e2dc5 | 2027 | case 112: |
18ed0c4e | 2028 | return tdep->ppc_spefscr_regnum; |
9f744501 JB |
2029 | default: |
2030 | return num; | |
2031 | } | |
18ed0c4e | 2032 | } |
9f744501 | 2033 | |
9f744501 | 2034 | |
18ed0c4e JB |
2035 | /* Convert a Dwarf 2 register number to a GDB register number. */ |
2036 | static int | |
2037 | rs6000_dwarf2_reg_to_regnum (int num) | |
2038 | { | |
2039 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
9f744501 | 2040 | |
18ed0c4e JB |
2041 | if (0 <= num && num <= 31) |
2042 | return tdep->ppc_gp0_regnum + num; | |
2043 | else if (32 <= num && num <= 63) | |
2044 | /* FIXME: jimb/2004-05-05: What should we do when the debug info | |
2045 | specifies registers the architecture doesn't have? Our | |
2046 | callers don't check the value we return. */ | |
2047 | return tdep->ppc_fp0_regnum + (num - 32); | |
2048 | else if (1124 <= num && num < 1124 + 32) | |
2049 | return tdep->ppc_vr0_regnum + (num - 1124); | |
2050 | else if (1200 <= num && num < 1200 + 32) | |
2051 | return tdep->ppc_ev0_regnum + (num - 1200); | |
2052 | else | |
2053 | switch (num) | |
2054 | { | |
2055 | case 67: | |
2056 | return tdep->ppc_vrsave_regnum - 1; /* vscr */ | |
2057 | case 99: | |
2058 | return tdep->ppc_acc_regnum; | |
2059 | case 100: | |
2060 | return tdep->ppc_mq_regnum; | |
2061 | case 101: | |
2062 | return tdep->ppc_xer_regnum; | |
2063 | case 108: | |
2064 | return tdep->ppc_lr_regnum; | |
2065 | case 109: | |
2066 | return tdep->ppc_ctr_regnum; | |
2067 | case 356: | |
2068 | return tdep->ppc_vrsave_regnum; | |
2069 | case 612: | |
2070 | return tdep->ppc_spefscr_regnum; | |
2071 | default: | |
2072 | return num; | |
2073 | } | |
2188cbdd EZ |
2074 | } |
2075 | ||
18ed0c4e | 2076 | |
7a78ae4e | 2077 | static void |
a3c001ce JB |
2078 | rs6000_store_return_value (struct type *type, |
2079 | struct regcache *regcache, | |
2080 | const void *valbuf) | |
7a78ae4e | 2081 | { |
a3c001ce JB |
2082 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
2083 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2084 | int regnum = -1; | |
ace1378a | 2085 | |
383f0f5b JB |
2086 | /* The calling convention this function implements assumes the |
2087 | processor has floating-point registers. We shouldn't be using it | |
2088 | on PPC variants that lack them. */ | |
a3c001ce | 2089 | gdb_assert (ppc_floating_point_unit_p (gdbarch)); |
383f0f5b | 2090 | |
7a78ae4e | 2091 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
7a78ae4e ND |
2092 | /* Floating point values are returned starting from FPR1 and up. |
2093 | Say a double_double_double type could be returned in | |
64366f1c | 2094 | FPR1/FPR2/FPR3 triple. */ |
a3c001ce | 2095 | regnum = tdep->ppc_fp0_regnum + 1; |
ace1378a EZ |
2096 | else if (TYPE_CODE (type) == TYPE_CODE_ARRAY) |
2097 | { | |
2098 | if (TYPE_LENGTH (type) == 16 | |
2099 | && TYPE_VECTOR (type)) | |
a3c001ce JB |
2100 | regnum = tdep->ppc_vr0_regnum + 2; |
2101 | else | |
a44bddec JB |
2102 | internal_error (__FILE__, __LINE__, |
2103 | "rs6000_store_return_value: " | |
2104 | "unexpected array return type"); | |
ace1378a | 2105 | } |
7a78ae4e | 2106 | else |
64366f1c | 2107 | /* Everything else is returned in GPR3 and up. */ |
a3c001ce JB |
2108 | regnum = tdep->ppc_gp0_regnum + 3; |
2109 | ||
2110 | { | |
2111 | size_t bytes_written = 0; | |
2112 | ||
2113 | while (bytes_written < TYPE_LENGTH (type)) | |
2114 | { | |
2115 | /* How much of this value can we write to this register? */ | |
2116 | size_t bytes_to_write = min (TYPE_LENGTH (type) - bytes_written, | |
2117 | register_size (gdbarch, regnum)); | |
2118 | regcache_cooked_write_part (regcache, regnum, | |
2119 | 0, bytes_to_write, | |
2120 | (char *) valbuf + bytes_written); | |
2121 | regnum++; | |
2122 | bytes_written += bytes_to_write; | |
2123 | } | |
2124 | } | |
7a78ae4e ND |
2125 | } |
2126 | ||
a3c001ce | 2127 | |
7a78ae4e ND |
2128 | /* Extract from an array REGBUF containing the (raw) register state |
2129 | the address in which a function should return its structure value, | |
2130 | as a CORE_ADDR (or an expression that can be used as one). */ | |
2131 | ||
2132 | static CORE_ADDR | |
11269d7e AC |
2133 | rs6000_extract_struct_value_address (struct regcache *regcache) |
2134 | { | |
2135 | /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior | |
2136 | function call GDB knows the address of the struct return value | |
2137 | and hence, should not need to call this function. Unfortunately, | |
e8a8712a AC |
2138 | the current call_function_by_hand() code only saves the most |
2139 | recent struct address leading to occasional calls. The code | |
2140 | should instead maintain a stack of such addresses (in the dummy | |
2141 | frame object). */ | |
11269d7e AC |
2142 | /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've |
2143 | really got no idea where the return value is being stored. While | |
2144 | r3, on function entry, contained the address it will have since | |
2145 | been reused (scratch) and hence wouldn't be valid */ | |
2146 | return 0; | |
7a78ae4e ND |
2147 | } |
2148 | ||
64366f1c | 2149 | /* Hook called when a new child process is started. */ |
7a78ae4e ND |
2150 | |
2151 | void | |
2152 | rs6000_create_inferior (int pid) | |
2153 | { | |
2154 | if (rs6000_set_host_arch_hook) | |
2155 | rs6000_set_host_arch_hook (pid); | |
c906108c SS |
2156 | } |
2157 | \f | |
e2d0e7eb | 2158 | /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG). |
7a78ae4e ND |
2159 | |
2160 | Usually a function pointer's representation is simply the address | |
2161 | of the function. On the RS/6000 however, a function pointer is | |
2162 | represented by a pointer to a TOC entry. This TOC entry contains | |
2163 | three words, the first word is the address of the function, the | |
2164 | second word is the TOC pointer (r2), and the third word is the | |
2165 | static chain value. Throughout GDB it is currently assumed that a | |
2166 | function pointer contains the address of the function, which is not | |
2167 | easy to fix. In addition, the conversion of a function address to | |
2168 | a function pointer would require allocation of a TOC entry in the | |
2169 | inferior's memory space, with all its drawbacks. To be able to | |
2170 | call C++ virtual methods in the inferior (which are called via | |
f517ea4e | 2171 | function pointers), find_function_addr uses this function to get the |
7a78ae4e ND |
2172 | function address from a function pointer. */ |
2173 | ||
f517ea4e PS |
2174 | /* Return real function address if ADDR (a function pointer) is in the data |
2175 | space and is therefore a special function pointer. */ | |
c906108c | 2176 | |
b9362cc7 | 2177 | static CORE_ADDR |
e2d0e7eb AC |
2178 | rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch, |
2179 | CORE_ADDR addr, | |
2180 | struct target_ops *targ) | |
c906108c SS |
2181 | { |
2182 | struct obj_section *s; | |
2183 | ||
2184 | s = find_pc_section (addr); | |
2185 | if (s && s->the_bfd_section->flags & SEC_CODE) | |
7a78ae4e | 2186 | return addr; |
c906108c | 2187 | |
7a78ae4e | 2188 | /* ADDR is in the data space, so it's a special function pointer. */ |
21283beb | 2189 | return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize); |
c906108c | 2190 | } |
c906108c | 2191 | \f |
c5aa993b | 2192 | |
7a78ae4e | 2193 | /* Handling the various POWER/PowerPC variants. */ |
c906108c SS |
2194 | |
2195 | ||
7a78ae4e ND |
2196 | /* The arrays here called registers_MUMBLE hold information about available |
2197 | registers. | |
c906108c SS |
2198 | |
2199 | For each family of PPC variants, I've tried to isolate out the | |
2200 | common registers and put them up front, so that as long as you get | |
2201 | the general family right, GDB will correctly identify the registers | |
2202 | common to that family. The common register sets are: | |
2203 | ||
2204 | For the 60x family: hid0 hid1 iabr dabr pir | |
2205 | ||
2206 | For the 505 and 860 family: eie eid nri | |
2207 | ||
2208 | For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi | |
c5aa993b JM |
2209 | tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1 |
2210 | pbu1 pbl2 pbu2 | |
c906108c SS |
2211 | |
2212 | Most of these register groups aren't anything formal. I arrived at | |
2213 | them by looking at the registers that occurred in more than one | |
6f5987a6 KB |
2214 | processor. |
2215 | ||
2216 | Note: kevinb/2002-04-30: Support for the fpscr register was added | |
2217 | during April, 2002. Slot 70 is being used for PowerPC and slot 71 | |
2218 | for Power. For PowerPC, slot 70 was unused and was already in the | |
2219 | PPC_UISA_SPRS which is ideally where fpscr should go. For Power, | |
2220 | slot 70 was being used for "mq", so the next available slot (71) | |
2221 | was chosen. It would have been nice to be able to make the | |
2222 | register numbers the same across processor cores, but this wasn't | |
2223 | possible without either 1) renumbering some registers for some | |
2224 | processors or 2) assigning fpscr to a really high slot that's | |
2225 | larger than any current register number. Doing (1) is bad because | |
2226 | existing stubs would break. Doing (2) is undesirable because it | |
2227 | would introduce a really large gap between fpscr and the rest of | |
2228 | the registers for most processors. */ | |
7a78ae4e | 2229 | |
64366f1c | 2230 | /* Convenience macros for populating register arrays. */ |
7a78ae4e | 2231 | |
64366f1c | 2232 | /* Within another macro, convert S to a string. */ |
7a78ae4e ND |
2233 | |
2234 | #define STR(s) #s | |
2235 | ||
2236 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems | |
64366f1c | 2237 | and 64 bits on 64-bit systems. */ |
13ac140c | 2238 | #define R(name) { STR(name), 4, 8, 0, 0, -1 } |
7a78ae4e ND |
2239 | |
2240 | /* Return a struct reg defining register NAME that's 32 bits on all | |
64366f1c | 2241 | systems. */ |
13ac140c | 2242 | #define R4(name) { STR(name), 4, 4, 0, 0, -1 } |
7a78ae4e ND |
2243 | |
2244 | /* Return a struct reg defining register NAME that's 64 bits on all | |
64366f1c | 2245 | systems. */ |
13ac140c | 2246 | #define R8(name) { STR(name), 8, 8, 0, 0, -1 } |
7a78ae4e | 2247 | |
1fcc0bb8 | 2248 | /* Return a struct reg defining register NAME that's 128 bits on all |
64366f1c | 2249 | systems. */ |
13ac140c | 2250 | #define R16(name) { STR(name), 16, 16, 0, 0, -1 } |
1fcc0bb8 | 2251 | |
64366f1c | 2252 | /* Return a struct reg defining floating-point register NAME. */ |
13ac140c | 2253 | #define F(name) { STR(name), 8, 8, 1, 0, -1 } |
489461e2 | 2254 | |
6ced10dd JB |
2255 | /* Return a struct reg defining a pseudo register NAME that is 64 bits |
2256 | long on all systems. */ | |
2257 | #define P8(name) { STR(name), 8, 8, 0, 1, -1 } | |
7a78ae4e ND |
2258 | |
2259 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit | |
64366f1c | 2260 | systems and that doesn't exist on 64-bit systems. */ |
13ac140c | 2261 | #define R32(name) { STR(name), 4, 0, 0, 0, -1 } |
7a78ae4e ND |
2262 | |
2263 | /* Return a struct reg defining register NAME that's 64 bits on 64-bit | |
64366f1c | 2264 | systems and that doesn't exist on 32-bit systems. */ |
13ac140c | 2265 | #define R64(name) { STR(name), 0, 8, 0, 0, -1 } |
7a78ae4e | 2266 | |
64366f1c | 2267 | /* Return a struct reg placeholder for a register that doesn't exist. */ |
13ac140c | 2268 | #define R0 { 0, 0, 0, 0, 0, -1 } |
7a78ae4e | 2269 | |
6ced10dd JB |
2270 | /* Return a struct reg defining an anonymous raw register that's 32 |
2271 | bits on all systems. */ | |
2272 | #define A4 { 0, 4, 4, 0, 0, -1 } | |
2273 | ||
13ac140c JB |
2274 | /* Return a struct reg defining an SPR named NAME that is 32 bits on |
2275 | 32-bit systems and 64 bits on 64-bit systems. */ | |
2276 | #define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name } | |
2277 | ||
2278 | /* Return a struct reg defining an SPR named NAME that is 32 bits on | |
2279 | all systems. */ | |
2280 | #define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name } | |
2281 | ||
2282 | /* Return a struct reg defining an SPR named NAME that is 32 bits on | |
2283 | all systems, and whose SPR number is NUMBER. */ | |
2284 | #define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) } | |
2285 | ||
2286 | /* Return a struct reg defining an SPR named NAME that's 64 bits on | |
2287 | 64-bit systems and that doesn't exist on 32-bit systems. */ | |
2288 | #define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name } | |
2289 | ||
7a78ae4e ND |
2290 | /* UISA registers common across all architectures, including POWER. */ |
2291 | ||
2292 | #define COMMON_UISA_REGS \ | |
2293 | /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ | |
2294 | /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ | |
2295 | /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ | |
2296 | /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ | |
2297 | /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \ | |
2298 | /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \ | |
2299 | /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \ | |
2300 | /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \ | |
2301 | /* 64 */ R(pc), R(ps) | |
2302 | ||
2303 | /* UISA-level SPRs for PowerPC. */ | |
2304 | #define PPC_UISA_SPRS \ | |
13ac140c | 2305 | /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr) |
7a78ae4e | 2306 | |
c8001721 EZ |
2307 | /* UISA-level SPRs for PowerPC without floating point support. */ |
2308 | #define PPC_UISA_NOFP_SPRS \ | |
13ac140c | 2309 | /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0 |
c8001721 | 2310 | |
7a78ae4e ND |
2311 | /* Segment registers, for PowerPC. */ |
2312 | #define PPC_SEGMENT_REGS \ | |
2313 | /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \ | |
2314 | /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \ | |
2315 | /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \ | |
2316 | /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15) | |
2317 | ||
2318 | /* OEA SPRs for PowerPC. */ | |
2319 | #define PPC_OEA_SPRS \ | |
13ac140c JB |
2320 | /* 87 */ S4(pvr), \ |
2321 | /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \ | |
2322 | /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \ | |
2323 | /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \ | |
2324 | /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \ | |
2325 | /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \ | |
2326 | /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \ | |
2327 | /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \ | |
2328 | /* 116 */ S4(dec), S(dabr), S4(ear) | |
7a78ae4e | 2329 | |
64366f1c | 2330 | /* AltiVec registers. */ |
1fcc0bb8 EZ |
2331 | #define PPC_ALTIVEC_REGS \ |
2332 | /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \ | |
2333 | /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \ | |
2334 | /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \ | |
2335 | /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \ | |
2336 | /*151*/R4(vscr), R4(vrsave) | |
2337 | ||
c8001721 | 2338 | |
6ced10dd JB |
2339 | /* On machines supporting the SPE APU, the general-purpose registers |
2340 | are 64 bits long. There are SIMD vector instructions to treat them | |
2341 | as pairs of floats, but the rest of the instruction set treats them | |
2342 | as 32-bit registers, and only operates on their lower halves. | |
2343 | ||
2344 | In the GDB regcache, we treat their high and low halves as separate | |
2345 | registers. The low halves we present as the general-purpose | |
2346 | registers, and then we have pseudo-registers that stitch together | |
2347 | the upper and lower halves and present them as pseudo-registers. */ | |
2348 | ||
2349 | /* SPE GPR lower halves --- raw registers. */ | |
2350 | #define PPC_SPE_GP_REGS \ | |
2351 | /* 0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7), \ | |
2352 | /* 8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \ | |
2353 | /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \ | |
2354 | /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31) | |
2355 | ||
2356 | /* SPE GPR upper halves --- anonymous raw registers. */ | |
2357 | #define PPC_SPE_UPPER_GP_REGS \ | |
2358 | /* 0 */ A4, A4, A4, A4, A4, A4, A4, A4, \ | |
2359 | /* 8 */ A4, A4, A4, A4, A4, A4, A4, A4, \ | |
2360 | /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4, \ | |
2361 | /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4 | |
2362 | ||
2363 | /* SPE GPR vector registers --- pseudo registers based on underlying | |
2364 | gprs and the anonymous upper half raw registers. */ | |
2365 | #define PPC_EV_PSEUDO_REGS \ | |
2366 | /* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \ | |
2367 | /* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\ | |
2368 | /*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\ | |
2369 | /*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31) | |
c8001721 | 2370 | |
7a78ae4e | 2371 | /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover |
64366f1c | 2372 | user-level SPR's. */ |
7a78ae4e | 2373 | static const struct reg registers_power[] = |
c906108c | 2374 | { |
7a78ae4e | 2375 | COMMON_UISA_REGS, |
13ac140c | 2376 | /* 66 */ R4(cnd), S(lr), S(cnt), S4(xer), S4(mq), |
e3f36dbd | 2377 | /* 71 */ R4(fpscr) |
c906108c SS |
2378 | }; |
2379 | ||
7a78ae4e | 2380 | /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only |
64366f1c | 2381 | view of the PowerPC. */ |
7a78ae4e | 2382 | static const struct reg registers_powerpc[] = |
c906108c | 2383 | { |
7a78ae4e | 2384 | COMMON_UISA_REGS, |
1fcc0bb8 EZ |
2385 | PPC_UISA_SPRS, |
2386 | PPC_ALTIVEC_REGS | |
c906108c SS |
2387 | }; |
2388 | ||
13ac140c JB |
2389 | /* IBM PowerPC 403. |
2390 | ||
2391 | Some notes about the "tcr" special-purpose register: | |
2392 | - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the | |
2393 | 403's programmable interval timer, fixed interval timer, and | |
2394 | watchdog timer. | |
2395 | - On the 602, SPR 984 is named "tcr", and it controls the 602's | |
2396 | watchdog timer, and nothing else. | |
2397 | ||
2398 | Some of the fields are similar between the two, but they're not | |
2399 | compatible with each other. Since the two variants have different | |
2400 | registers, with different numbers, but the same name, we can't | |
2401 | splice the register name to get the SPR number. */ | |
7a78ae4e | 2402 | static const struct reg registers_403[] = |
c5aa993b | 2403 | { |
7a78ae4e ND |
2404 | COMMON_UISA_REGS, |
2405 | PPC_UISA_SPRS, | |
2406 | PPC_SEGMENT_REGS, | |
2407 | PPC_OEA_SPRS, | |
13ac140c JB |
2408 | /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr), |
2409 | /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit), | |
2410 | /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3), | |
2411 | /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2), | |
2412 | /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr), | |
2413 | /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2) | |
c906108c SS |
2414 | }; |
2415 | ||
13ac140c JB |
2416 | /* IBM PowerPC 403GC. |
2417 | See the comments about 'tcr' for the 403, above. */ | |
7a78ae4e | 2418 | static const struct reg registers_403GC[] = |
c5aa993b | 2419 | { |
7a78ae4e ND |
2420 | COMMON_UISA_REGS, |
2421 | PPC_UISA_SPRS, | |
2422 | PPC_SEGMENT_REGS, | |
2423 | PPC_OEA_SPRS, | |
13ac140c JB |
2424 | /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr), |
2425 | /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit), | |
2426 | /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3), | |
2427 | /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2), | |
2428 | /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr), | |
2429 | /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2), | |
2430 | /* 143 */ S(zpr), S(pid), S(sgr), S(dcwr), | |
2431 | /* 147 */ S(tbhu), S(tblu) | |
c906108c SS |
2432 | }; |
2433 | ||
64366f1c | 2434 | /* Motorola PowerPC 505. */ |
7a78ae4e | 2435 | static const struct reg registers_505[] = |
c5aa993b | 2436 | { |
7a78ae4e ND |
2437 | COMMON_UISA_REGS, |
2438 | PPC_UISA_SPRS, | |
2439 | PPC_SEGMENT_REGS, | |
2440 | PPC_OEA_SPRS, | |
13ac140c | 2441 | /* 119 */ S(eie), S(eid), S(nri) |
c906108c SS |
2442 | }; |
2443 | ||
64366f1c | 2444 | /* Motorola PowerPC 860 or 850. */ |
7a78ae4e | 2445 | static const struct reg registers_860[] = |
c5aa993b | 2446 | { |
7a78ae4e ND |
2447 | COMMON_UISA_REGS, |
2448 | PPC_UISA_SPRS, | |
2449 | PPC_SEGMENT_REGS, | |
2450 | PPC_OEA_SPRS, | |
13ac140c JB |
2451 | /* 119 */ S(eie), S(eid), S(nri), S(cmpa), |
2452 | /* 123 */ S(cmpb), S(cmpc), S(cmpd), S(icr), | |
2453 | /* 127 */ S(der), S(counta), S(countb), S(cmpe), | |
2454 | /* 131 */ S(cmpf), S(cmpg), S(cmph), S(lctrl1), | |
2455 | /* 135 */ S(lctrl2), S(ictrl), S(bar), S(ic_cst), | |
2456 | /* 139 */ S(ic_adr), S(ic_dat), S(dc_cst), S(dc_adr), | |
2457 | /* 143 */ S(dc_dat), S(dpdr), S(dpir), S(immr), | |
2458 | /* 147 */ S(mi_ctr), S(mi_ap), S(mi_epn), S(mi_twc), | |
2459 | /* 151 */ S(mi_rpn), S(md_ctr), S(m_casid), S(md_ap), | |
2460 | /* 155 */ S(md_epn), S(m_twb), S(md_twc), S(md_rpn), | |
2461 | /* 159 */ S(m_tw), S(mi_dbcam), S(mi_dbram0), S(mi_dbram1), | |
2462 | /* 163 */ S(md_dbcam), S(md_dbram0), S(md_dbram1) | |
c906108c SS |
2463 | }; |
2464 | ||
7a78ae4e ND |
2465 | /* Motorola PowerPC 601. Note that the 601 has different register numbers |
2466 | for reading and writing RTCU and RTCL. However, how one reads and writes a | |
c906108c | 2467 | register is the stub's problem. */ |
7a78ae4e | 2468 | static const struct reg registers_601[] = |
c5aa993b | 2469 | { |
7a78ae4e ND |
2470 | COMMON_UISA_REGS, |
2471 | PPC_UISA_SPRS, | |
2472 | PPC_SEGMENT_REGS, | |
2473 | PPC_OEA_SPRS, | |
13ac140c JB |
2474 | /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), |
2475 | /* 123 */ S(pir), S(mq), S(rtcu), S(rtcl) | |
c906108c SS |
2476 | }; |
2477 | ||
13ac140c JB |
2478 | /* Motorola PowerPC 602. |
2479 | See the notes under the 403 about 'tcr'. */ | |
7a78ae4e | 2480 | static const struct reg registers_602[] = |
c5aa993b | 2481 | { |
7a78ae4e ND |
2482 | COMMON_UISA_REGS, |
2483 | PPC_UISA_SPRS, | |
2484 | PPC_SEGMENT_REGS, | |
2485 | PPC_OEA_SPRS, | |
13ac140c JB |
2486 | /* 119 */ S(hid0), S(hid1), S(iabr), R0, |
2487 | /* 123 */ R0, SN4(tcr, ppc_spr_602_tcr), S(ibr), S(esasrr), | |
2488 | /* 127 */ S(sebr), S(ser), S(sp), S(lt) | |
c906108c SS |
2489 | }; |
2490 | ||
64366f1c | 2491 | /* Motorola/IBM PowerPC 603 or 603e. */ |
7a78ae4e | 2492 | static const struct reg registers_603[] = |
c5aa993b | 2493 | { |
7a78ae4e ND |
2494 | COMMON_UISA_REGS, |
2495 | PPC_UISA_SPRS, | |
2496 | PPC_SEGMENT_REGS, | |
2497 | PPC_OEA_SPRS, | |
13ac140c JB |
2498 | /* 119 */ S(hid0), S(hid1), S(iabr), R0, |
2499 | /* 123 */ R0, S(dmiss), S(dcmp), S(hash1), | |
2500 | /* 127 */ S(hash2), S(imiss), S(icmp), S(rpa) | |
c906108c SS |
2501 | }; |
2502 | ||
64366f1c | 2503 | /* Motorola PowerPC 604 or 604e. */ |
7a78ae4e | 2504 | static const struct reg registers_604[] = |
c5aa993b | 2505 | { |
7a78ae4e ND |
2506 | COMMON_UISA_REGS, |
2507 | PPC_UISA_SPRS, | |
2508 | PPC_SEGMENT_REGS, | |
2509 | PPC_OEA_SPRS, | |
13ac140c JB |
2510 | /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), |
2511 | /* 123 */ S(pir), S(mmcr0), S(pmc1), S(pmc2), | |
2512 | /* 127 */ S(sia), S(sda) | |
c906108c SS |
2513 | }; |
2514 | ||
64366f1c | 2515 | /* Motorola/IBM PowerPC 750 or 740. */ |
7a78ae4e | 2516 | static const struct reg registers_750[] = |
c5aa993b | 2517 | { |
7a78ae4e ND |
2518 | COMMON_UISA_REGS, |
2519 | PPC_UISA_SPRS, | |
2520 | PPC_SEGMENT_REGS, | |
2521 | PPC_OEA_SPRS, | |
13ac140c JB |
2522 | /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), |
2523 | /* 123 */ R0, S(ummcr0), S(upmc1), S(upmc2), | |
2524 | /* 127 */ S(usia), S(ummcr1), S(upmc3), S(upmc4), | |
2525 | /* 131 */ S(mmcr0), S(pmc1), S(pmc2), S(sia), | |
2526 | /* 135 */ S(mmcr1), S(pmc3), S(pmc4), S(l2cr), | |
2527 | /* 139 */ S(ictc), S(thrm1), S(thrm2), S(thrm3) | |
c906108c SS |
2528 | }; |
2529 | ||
2530 | ||
64366f1c | 2531 | /* Motorola PowerPC 7400. */ |
1fcc0bb8 EZ |
2532 | static const struct reg registers_7400[] = |
2533 | { | |
2534 | /* gpr0-gpr31, fpr0-fpr31 */ | |
2535 | COMMON_UISA_REGS, | |
13c7b1ca | 2536 | /* cr, lr, ctr, xer, fpscr */ |
1fcc0bb8 EZ |
2537 | PPC_UISA_SPRS, |
2538 | /* sr0-sr15 */ | |
2539 | PPC_SEGMENT_REGS, | |
2540 | PPC_OEA_SPRS, | |
2541 | /* vr0-vr31, vrsave, vscr */ | |
2542 | PPC_ALTIVEC_REGS | |
2543 | /* FIXME? Add more registers? */ | |
2544 | }; | |
2545 | ||
c8001721 EZ |
2546 | /* Motorola e500. */ |
2547 | static const struct reg registers_e500[] = | |
2548 | { | |
6ced10dd JB |
2549 | /* 0 .. 31 */ PPC_SPE_GP_REGS, |
2550 | /* 32 .. 63 */ PPC_SPE_UPPER_GP_REGS, | |
2551 | /* 64 .. 65 */ R(pc), R(ps), | |
2552 | /* 66 .. 70 */ PPC_UISA_NOFP_SPRS, | |
2553 | /* 71 .. 72 */ R8(acc), S4(spefscr), | |
338ef23d AC |
2554 | /* NOTE: Add new registers here the end of the raw register |
2555 | list and just before the first pseudo register. */ | |
6ced10dd | 2556 | /* 73 .. 104 */ PPC_EV_PSEUDO_REGS |
c8001721 EZ |
2557 | }; |
2558 | ||
c906108c | 2559 | /* Information about a particular processor variant. */ |
7a78ae4e | 2560 | |
c906108c | 2561 | struct variant |
c5aa993b JM |
2562 | { |
2563 | /* Name of this variant. */ | |
2564 | char *name; | |
c906108c | 2565 | |
c5aa993b JM |
2566 | /* English description of the variant. */ |
2567 | char *description; | |
c906108c | 2568 | |
64366f1c | 2569 | /* bfd_arch_info.arch corresponding to variant. */ |
7a78ae4e ND |
2570 | enum bfd_architecture arch; |
2571 | ||
64366f1c | 2572 | /* bfd_arch_info.mach corresponding to variant. */ |
7a78ae4e ND |
2573 | unsigned long mach; |
2574 | ||
489461e2 EZ |
2575 | /* Number of real registers. */ |
2576 | int nregs; | |
2577 | ||
2578 | /* Number of pseudo registers. */ | |
2579 | int npregs; | |
2580 | ||
2581 | /* Number of total registers (the sum of nregs and npregs). */ | |
2582 | int num_tot_regs; | |
2583 | ||
c5aa993b JM |
2584 | /* Table of register names; registers[R] is the name of the register |
2585 | number R. */ | |
7a78ae4e | 2586 | const struct reg *regs; |
c5aa993b | 2587 | }; |
c906108c | 2588 | |
489461e2 EZ |
2589 | #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0])) |
2590 | ||
2591 | static int | |
2592 | num_registers (const struct reg *reg_list, int num_tot_regs) | |
2593 | { | |
2594 | int i; | |
2595 | int nregs = 0; | |
2596 | ||
2597 | for (i = 0; i < num_tot_regs; i++) | |
2598 | if (!reg_list[i].pseudo) | |
2599 | nregs++; | |
2600 | ||
2601 | return nregs; | |
2602 | } | |
2603 | ||
2604 | static int | |
2605 | num_pseudo_registers (const struct reg *reg_list, int num_tot_regs) | |
2606 | { | |
2607 | int i; | |
2608 | int npregs = 0; | |
2609 | ||
2610 | for (i = 0; i < num_tot_regs; i++) | |
2611 | if (reg_list[i].pseudo) | |
2612 | npregs ++; | |
2613 | ||
2614 | return npregs; | |
2615 | } | |
c906108c | 2616 | |
c906108c SS |
2617 | /* Information in this table comes from the following web sites: |
2618 | IBM: http://www.chips.ibm.com:80/products/embedded/ | |
2619 | Motorola: http://www.mot.com/SPS/PowerPC/ | |
2620 | ||
2621 | I'm sure I've got some of the variant descriptions not quite right. | |
2622 | Please report any inaccuracies you find to GDB's maintainer. | |
2623 | ||
2624 | If you add entries to this table, please be sure to allow the new | |
2625 | value as an argument to the --with-cpu flag, in configure.in. */ | |
2626 | ||
489461e2 | 2627 | static struct variant variants[] = |
c906108c | 2628 | { |
489461e2 | 2629 | |
7a78ae4e | 2630 | {"powerpc", "PowerPC user-level", bfd_arch_powerpc, |
489461e2 EZ |
2631 | bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc), |
2632 | registers_powerpc}, | |
7a78ae4e | 2633 | {"power", "POWER user-level", bfd_arch_rs6000, |
489461e2 EZ |
2634 | bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power), |
2635 | registers_power}, | |
7a78ae4e | 2636 | {"403", "IBM PowerPC 403", bfd_arch_powerpc, |
489461e2 EZ |
2637 | bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403), |
2638 | registers_403}, | |
7a78ae4e | 2639 | {"601", "Motorola PowerPC 601", bfd_arch_powerpc, |
489461e2 EZ |
2640 | bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601), |
2641 | registers_601}, | |
7a78ae4e | 2642 | {"602", "Motorola PowerPC 602", bfd_arch_powerpc, |
489461e2 EZ |
2643 | bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602), |
2644 | registers_602}, | |
7a78ae4e | 2645 | {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, |
489461e2 EZ |
2646 | bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603), |
2647 | registers_603}, | |
7a78ae4e | 2648 | {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, |
489461e2 EZ |
2649 | 604, -1, -1, tot_num_registers (registers_604), |
2650 | registers_604}, | |
7a78ae4e | 2651 | {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, |
489461e2 EZ |
2652 | bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC), |
2653 | registers_403GC}, | |
7a78ae4e | 2654 | {"505", "Motorola PowerPC 505", bfd_arch_powerpc, |
489461e2 EZ |
2655 | bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505), |
2656 | registers_505}, | |
7a78ae4e | 2657 | {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, |
489461e2 EZ |
2658 | bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860), |
2659 | registers_860}, | |
7a78ae4e | 2660 | {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, |
489461e2 EZ |
2661 | bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750), |
2662 | registers_750}, | |
1fcc0bb8 | 2663 | {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, |
489461e2 EZ |
2664 | bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400), |
2665 | registers_7400}, | |
c8001721 EZ |
2666 | {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, |
2667 | bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500), | |
2668 | registers_e500}, | |
7a78ae4e | 2669 | |
5d57ee30 KB |
2670 | /* 64-bit */ |
2671 | {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, | |
489461e2 EZ |
2672 | bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc), |
2673 | registers_powerpc}, | |
7a78ae4e | 2674 | {"620", "Motorola PowerPC 620", bfd_arch_powerpc, |
489461e2 EZ |
2675 | bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc), |
2676 | registers_powerpc}, | |
5d57ee30 | 2677 | {"630", "Motorola PowerPC 630", bfd_arch_powerpc, |
489461e2 EZ |
2678 | bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc), |
2679 | registers_powerpc}, | |
7a78ae4e | 2680 | {"a35", "PowerPC A35", bfd_arch_powerpc, |
489461e2 EZ |
2681 | bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc), |
2682 | registers_powerpc}, | |
5d57ee30 | 2683 | {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, |
489461e2 EZ |
2684 | bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc), |
2685 | registers_powerpc}, | |
5d57ee30 | 2686 | {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, |
489461e2 EZ |
2687 | bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc), |
2688 | registers_powerpc}, | |
5d57ee30 | 2689 | |
64366f1c | 2690 | /* FIXME: I haven't checked the register sets of the following. */ |
7a78ae4e | 2691 | {"rs1", "IBM POWER RS1", bfd_arch_rs6000, |
489461e2 EZ |
2692 | bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power), |
2693 | registers_power}, | |
7a78ae4e | 2694 | {"rsc", "IBM POWER RSC", bfd_arch_rs6000, |
489461e2 EZ |
2695 | bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power), |
2696 | registers_power}, | |
7a78ae4e | 2697 | {"rs2", "IBM POWER RS2", bfd_arch_rs6000, |
489461e2 EZ |
2698 | bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power), |
2699 | registers_power}, | |
7a78ae4e | 2700 | |
489461e2 | 2701 | {0, 0, 0, 0, 0, 0, 0, 0} |
c906108c SS |
2702 | }; |
2703 | ||
64366f1c | 2704 | /* Initialize the number of registers and pseudo registers in each variant. */ |
489461e2 EZ |
2705 | |
2706 | static void | |
2707 | init_variants (void) | |
2708 | { | |
2709 | struct variant *v; | |
2710 | ||
2711 | for (v = variants; v->name; v++) | |
2712 | { | |
2713 | if (v->nregs == -1) | |
2714 | v->nregs = num_registers (v->regs, v->num_tot_regs); | |
2715 | if (v->npregs == -1) | |
2716 | v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs); | |
2717 | } | |
2718 | } | |
c906108c | 2719 | |
7a78ae4e | 2720 | /* Return the variant corresponding to architecture ARCH and machine number |
64366f1c | 2721 | MACH. If no such variant exists, return null. */ |
c906108c | 2722 | |
7a78ae4e ND |
2723 | static const struct variant * |
2724 | find_variant_by_arch (enum bfd_architecture arch, unsigned long mach) | |
c906108c | 2725 | { |
7a78ae4e | 2726 | const struct variant *v; |
c5aa993b | 2727 | |
7a78ae4e ND |
2728 | for (v = variants; v->name; v++) |
2729 | if (arch == v->arch && mach == v->mach) | |
2730 | return v; | |
c906108c | 2731 | |
7a78ae4e | 2732 | return NULL; |
c906108c | 2733 | } |
9364a0ef EZ |
2734 | |
2735 | static int | |
2736 | gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info) | |
2737 | { | |
2738 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2739 | return print_insn_big_powerpc (memaddr, info); | |
2740 | else | |
2741 | return print_insn_little_powerpc (memaddr, info); | |
2742 | } | |
7a78ae4e | 2743 | \f |
61a65099 KB |
2744 | static CORE_ADDR |
2745 | rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2746 | { | |
2747 | return frame_unwind_register_unsigned (next_frame, PC_REGNUM); | |
2748 | } | |
2749 | ||
2750 | static struct frame_id | |
2751 | rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2752 | { | |
2753 | return frame_id_build (frame_unwind_register_unsigned (next_frame, | |
2754 | SP_REGNUM), | |
2755 | frame_pc_unwind (next_frame)); | |
2756 | } | |
2757 | ||
2758 | struct rs6000_frame_cache | |
2759 | { | |
2760 | CORE_ADDR base; | |
2761 | CORE_ADDR initial_sp; | |
2762 | struct trad_frame_saved_reg *saved_regs; | |
2763 | }; | |
2764 | ||
2765 | static struct rs6000_frame_cache * | |
2766 | rs6000_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2767 | { | |
2768 | struct rs6000_frame_cache *cache; | |
2769 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
2770 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2771 | struct rs6000_framedata fdata; | |
2772 | int wordsize = tdep->wordsize; | |
2773 | ||
2774 | if ((*this_cache) != NULL) | |
2775 | return (*this_cache); | |
2776 | cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); | |
2777 | (*this_cache) = cache; | |
2778 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
2779 | ||
2780 | skip_prologue (frame_func_unwind (next_frame), frame_pc_unwind (next_frame), | |
2781 | &fdata); | |
2782 | ||
2783 | /* If there were any saved registers, figure out parent's stack | |
2784 | pointer. */ | |
2785 | /* The following is true only if the frame doesn't have a call to | |
2786 | alloca(), FIXME. */ | |
2787 | ||
2788 | if (fdata.saved_fpr == 0 | |
2789 | && fdata.saved_gpr == 0 | |
2790 | && fdata.saved_vr == 0 | |
2791 | && fdata.saved_ev == 0 | |
2792 | && fdata.lr_offset == 0 | |
2793 | && fdata.cr_offset == 0 | |
2794 | && fdata.vr_offset == 0 | |
2795 | && fdata.ev_offset == 0) | |
2796 | cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
2797 | else | |
2798 | { | |
2799 | /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most | |
2800 | address of the current frame. Things might be easier if the | |
2801 | ->frame pointed to the outer-most address of the frame. In | |
2802 | the mean time, the address of the prev frame is used as the | |
2803 | base address of this frame. */ | |
2804 | cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
2805 | if (!fdata.frameless) | |
2806 | /* Frameless really means stackless. */ | |
2807 | cache->base = read_memory_addr (cache->base, wordsize); | |
2808 | } | |
2809 | trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base); | |
2810 | ||
2811 | /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr. | |
2812 | All fpr's from saved_fpr to fp31 are saved. */ | |
2813 | ||
2814 | if (fdata.saved_fpr >= 0) | |
2815 | { | |
2816 | int i; | |
2817 | CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset; | |
383f0f5b JB |
2818 | |
2819 | /* If skip_prologue says floating-point registers were saved, | |
2820 | but the current architecture has no floating-point registers, | |
2821 | then that's strange. But we have no indices to even record | |
2822 | the addresses under, so we just ignore it. */ | |
2823 | if (ppc_floating_point_unit_p (gdbarch)) | |
063715bf | 2824 | for (i = fdata.saved_fpr; i < ppc_num_fprs; i++) |
383f0f5b JB |
2825 | { |
2826 | cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr; | |
2827 | fpr_addr += 8; | |
2828 | } | |
61a65099 KB |
2829 | } |
2830 | ||
2831 | /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr. | |
2832 | All gpr's from saved_gpr to gpr31 are saved. */ | |
2833 | ||
2834 | if (fdata.saved_gpr >= 0) | |
2835 | { | |
2836 | int i; | |
2837 | CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset; | |
063715bf | 2838 | for (i = fdata.saved_gpr; i < ppc_num_gprs; i++) |
61a65099 KB |
2839 | { |
2840 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr; | |
2841 | gpr_addr += wordsize; | |
2842 | } | |
2843 | } | |
2844 | ||
2845 | /* if != -1, fdata.saved_vr is the smallest number of saved_vr. | |
2846 | All vr's from saved_vr to vr31 are saved. */ | |
2847 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
2848 | { | |
2849 | if (fdata.saved_vr >= 0) | |
2850 | { | |
2851 | int i; | |
2852 | CORE_ADDR vr_addr = cache->base + fdata.vr_offset; | |
2853 | for (i = fdata.saved_vr; i < 32; i++) | |
2854 | { | |
2855 | cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr; | |
2856 | vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum); | |
2857 | } | |
2858 | } | |
2859 | } | |
2860 | ||
2861 | /* if != -1, fdata.saved_ev is the smallest number of saved_ev. | |
2862 | All vr's from saved_ev to ev31 are saved. ????? */ | |
2863 | if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1) | |
2864 | { | |
2865 | if (fdata.saved_ev >= 0) | |
2866 | { | |
2867 | int i; | |
2868 | CORE_ADDR ev_addr = cache->base + fdata.ev_offset; | |
063715bf | 2869 | for (i = fdata.saved_ev; i < ppc_num_gprs; i++) |
61a65099 KB |
2870 | { |
2871 | cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr; | |
2872 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4; | |
2873 | ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum); | |
2874 | } | |
2875 | } | |
2876 | } | |
2877 | ||
2878 | /* If != 0, fdata.cr_offset is the offset from the frame that | |
2879 | holds the CR. */ | |
2880 | if (fdata.cr_offset != 0) | |
2881 | cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset; | |
2882 | ||
2883 | /* If != 0, fdata.lr_offset is the offset from the frame that | |
2884 | holds the LR. */ | |
2885 | if (fdata.lr_offset != 0) | |
2886 | cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset; | |
2887 | /* The PC is found in the link register. */ | |
2888 | cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum]; | |
2889 | ||
2890 | /* If != 0, fdata.vrsave_offset is the offset from the frame that | |
2891 | holds the VRSAVE. */ | |
2892 | if (fdata.vrsave_offset != 0) | |
2893 | cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset; | |
2894 | ||
2895 | if (fdata.alloca_reg < 0) | |
2896 | /* If no alloca register used, then fi->frame is the value of the | |
2897 | %sp for this frame, and it is good enough. */ | |
2898 | cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
2899 | else | |
2900 | cache->initial_sp = frame_unwind_register_unsigned (next_frame, | |
2901 | fdata.alloca_reg); | |
2902 | ||
2903 | return cache; | |
2904 | } | |
2905 | ||
2906 | static void | |
2907 | rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2908 | struct frame_id *this_id) | |
2909 | { | |
2910 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
2911 | this_cache); | |
2912 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
2913 | } | |
2914 | ||
2915 | static void | |
2916 | rs6000_frame_prev_register (struct frame_info *next_frame, | |
2917 | void **this_cache, | |
2918 | int regnum, int *optimizedp, | |
2919 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
2920 | int *realnump, void *valuep) | |
2921 | { | |
2922 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
2923 | this_cache); | |
1f67027d AC |
2924 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
2925 | optimizedp, lvalp, addrp, realnump, valuep); | |
61a65099 KB |
2926 | } |
2927 | ||
2928 | static const struct frame_unwind rs6000_frame_unwind = | |
2929 | { | |
2930 | NORMAL_FRAME, | |
2931 | rs6000_frame_this_id, | |
2932 | rs6000_frame_prev_register | |
2933 | }; | |
2934 | ||
2935 | static const struct frame_unwind * | |
2936 | rs6000_frame_sniffer (struct frame_info *next_frame) | |
2937 | { | |
2938 | return &rs6000_frame_unwind; | |
2939 | } | |
2940 | ||
2941 | \f | |
2942 | ||
2943 | static CORE_ADDR | |
2944 | rs6000_frame_base_address (struct frame_info *next_frame, | |
2945 | void **this_cache) | |
2946 | { | |
2947 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
2948 | this_cache); | |
2949 | return info->initial_sp; | |
2950 | } | |
2951 | ||
2952 | static const struct frame_base rs6000_frame_base = { | |
2953 | &rs6000_frame_unwind, | |
2954 | rs6000_frame_base_address, | |
2955 | rs6000_frame_base_address, | |
2956 | rs6000_frame_base_address | |
2957 | }; | |
2958 | ||
2959 | static const struct frame_base * | |
2960 | rs6000_frame_base_sniffer (struct frame_info *next_frame) | |
2961 | { | |
2962 | return &rs6000_frame_base; | |
2963 | } | |
2964 | ||
7a78ae4e ND |
2965 | /* Initialize the current architecture based on INFO. If possible, re-use an |
2966 | architecture from ARCHES, which is a list of architectures already created | |
2967 | during this debugging session. | |
c906108c | 2968 | |
7a78ae4e | 2969 | Called e.g. at program startup, when reading a core file, and when reading |
64366f1c | 2970 | a binary file. */ |
c906108c | 2971 | |
7a78ae4e ND |
2972 | static struct gdbarch * |
2973 | rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2974 | { | |
2975 | struct gdbarch *gdbarch; | |
2976 | struct gdbarch_tdep *tdep; | |
708ff411 | 2977 | int wordsize, from_xcoff_exec, from_elf_exec, i, off; |
7a78ae4e ND |
2978 | struct reg *regs; |
2979 | const struct variant *v; | |
2980 | enum bfd_architecture arch; | |
2981 | unsigned long mach; | |
2982 | bfd abfd; | |
7b112f9c | 2983 | int sysv_abi; |
5bf1c677 | 2984 | asection *sect; |
7a78ae4e | 2985 | |
9aa1e687 | 2986 | from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && |
7a78ae4e ND |
2987 | bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; |
2988 | ||
9aa1e687 KB |
2989 | from_elf_exec = info.abfd && info.abfd->format == bfd_object && |
2990 | bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
2991 | ||
2992 | sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
2993 | ||
e712c1cf | 2994 | /* Check word size. If INFO is from a binary file, infer it from |
64366f1c | 2995 | that, else choose a likely default. */ |
9aa1e687 | 2996 | if (from_xcoff_exec) |
c906108c | 2997 | { |
11ed25ac | 2998 | if (bfd_xcoff_is_xcoff64 (info.abfd)) |
7a78ae4e ND |
2999 | wordsize = 8; |
3000 | else | |
3001 | wordsize = 4; | |
c906108c | 3002 | } |
9aa1e687 KB |
3003 | else if (from_elf_exec) |
3004 | { | |
3005 | if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
3006 | wordsize = 8; | |
3007 | else | |
3008 | wordsize = 4; | |
3009 | } | |
c906108c | 3010 | else |
7a78ae4e | 3011 | { |
27b15785 KB |
3012 | if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) |
3013 | wordsize = info.bfd_arch_info->bits_per_word / | |
3014 | info.bfd_arch_info->bits_per_byte; | |
3015 | else | |
3016 | wordsize = 4; | |
7a78ae4e | 3017 | } |
c906108c | 3018 | |
64366f1c | 3019 | /* Find a candidate among extant architectures. */ |
7a78ae4e ND |
3020 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
3021 | arches != NULL; | |
3022 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
3023 | { | |
3024 | /* Word size in the various PowerPC bfd_arch_info structs isn't | |
3025 | meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform | |
64366f1c | 3026 | separate word size check. */ |
7a78ae4e | 3027 | tdep = gdbarch_tdep (arches->gdbarch); |
4be87837 | 3028 | if (tdep && tdep->wordsize == wordsize) |
7a78ae4e ND |
3029 | return arches->gdbarch; |
3030 | } | |
c906108c | 3031 | |
7a78ae4e ND |
3032 | /* None found, create a new architecture from INFO, whose bfd_arch_info |
3033 | validity depends on the source: | |
3034 | - executable useless | |
3035 | - rs6000_host_arch() good | |
3036 | - core file good | |
3037 | - "set arch" trust blindly | |
3038 | - GDB startup useless but harmless */ | |
c906108c | 3039 | |
9aa1e687 | 3040 | if (!from_xcoff_exec) |
c906108c | 3041 | { |
b732d07d | 3042 | arch = info.bfd_arch_info->arch; |
7a78ae4e | 3043 | mach = info.bfd_arch_info->mach; |
c906108c | 3044 | } |
7a78ae4e | 3045 | else |
c906108c | 3046 | { |
7a78ae4e | 3047 | arch = bfd_arch_powerpc; |
35cec841 | 3048 | bfd_default_set_arch_mach (&abfd, arch, 0); |
7a78ae4e | 3049 | info.bfd_arch_info = bfd_get_arch_info (&abfd); |
35cec841 | 3050 | mach = info.bfd_arch_info->mach; |
7a78ae4e ND |
3051 | } |
3052 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
3053 | tdep->wordsize = wordsize; | |
5bf1c677 EZ |
3054 | |
3055 | /* For e500 executables, the apuinfo section is of help here. Such | |
3056 | section contains the identifier and revision number of each | |
3057 | Application-specific Processing Unit that is present on the | |
3058 | chip. The content of the section is determined by the assembler | |
3059 | which looks at each instruction and determines which unit (and | |
3060 | which version of it) can execute it. In our case we just look for | |
3061 | the existance of the section. */ | |
3062 | ||
3063 | if (info.abfd) | |
3064 | { | |
3065 | sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo"); | |
3066 | if (sect) | |
3067 | { | |
3068 | arch = info.bfd_arch_info->arch; | |
3069 | mach = bfd_mach_ppc_e500; | |
3070 | bfd_default_set_arch_mach (&abfd, arch, mach); | |
3071 | info.bfd_arch_info = bfd_get_arch_info (&abfd); | |
3072 | } | |
3073 | } | |
3074 | ||
7a78ae4e | 3075 | gdbarch = gdbarch_alloc (&info, tdep); |
7a78ae4e | 3076 | |
489461e2 EZ |
3077 | /* Initialize the number of real and pseudo registers in each variant. */ |
3078 | init_variants (); | |
3079 | ||
64366f1c | 3080 | /* Choose variant. */ |
7a78ae4e ND |
3081 | v = find_variant_by_arch (arch, mach); |
3082 | if (!v) | |
dd47e6fd EZ |
3083 | return NULL; |
3084 | ||
7a78ae4e ND |
3085 | tdep->regs = v->regs; |
3086 | ||
2188cbdd | 3087 | tdep->ppc_gp0_regnum = 0; |
2188cbdd EZ |
3088 | tdep->ppc_toc_regnum = 2; |
3089 | tdep->ppc_ps_regnum = 65; | |
3090 | tdep->ppc_cr_regnum = 66; | |
3091 | tdep->ppc_lr_regnum = 67; | |
3092 | tdep->ppc_ctr_regnum = 68; | |
3093 | tdep->ppc_xer_regnum = 69; | |
3094 | if (v->mach == bfd_mach_ppc_601) | |
3095 | tdep->ppc_mq_regnum = 124; | |
708ff411 | 3096 | else if (arch == bfd_arch_rs6000) |
2188cbdd | 3097 | tdep->ppc_mq_regnum = 70; |
e3f36dbd KB |
3098 | else |
3099 | tdep->ppc_mq_regnum = -1; | |
366f009f | 3100 | tdep->ppc_fp0_regnum = 32; |
708ff411 | 3101 | tdep->ppc_fpscr_regnum = (arch == bfd_arch_rs6000) ? 71 : 70; |
f86a7158 | 3102 | tdep->ppc_sr0_regnum = 71; |
baffbae0 JB |
3103 | tdep->ppc_vr0_regnum = -1; |
3104 | tdep->ppc_vrsave_regnum = -1; | |
6ced10dd | 3105 | tdep->ppc_ev0_upper_regnum = -1; |
baffbae0 JB |
3106 | tdep->ppc_ev0_regnum = -1; |
3107 | tdep->ppc_ev31_regnum = -1; | |
867e2dc5 JB |
3108 | tdep->ppc_acc_regnum = -1; |
3109 | tdep->ppc_spefscr_regnum = -1; | |
2188cbdd | 3110 | |
c8001721 EZ |
3111 | set_gdbarch_pc_regnum (gdbarch, 64); |
3112 | set_gdbarch_sp_regnum (gdbarch, 1); | |
0ba6dca9 | 3113 | set_gdbarch_deprecated_fp_regnum (gdbarch, 1); |
9f643768 | 3114 | set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno); |
afd48b75 | 3115 | if (sysv_abi && wordsize == 8) |
05580c65 | 3116 | set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value); |
e754ae69 | 3117 | else if (sysv_abi && wordsize == 4) |
05580c65 | 3118 | set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value); |
afd48b75 AC |
3119 | else |
3120 | { | |
3121 | set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value); | |
a3c001ce | 3122 | set_gdbarch_store_return_value (gdbarch, rs6000_store_return_value); |
afd48b75 | 3123 | } |
c8001721 | 3124 | |
baffbae0 JB |
3125 | /* Set lr_frame_offset. */ |
3126 | if (wordsize == 8) | |
3127 | tdep->lr_frame_offset = 16; | |
3128 | else if (sysv_abi) | |
3129 | tdep->lr_frame_offset = 4; | |
3130 | else | |
3131 | tdep->lr_frame_offset = 8; | |
3132 | ||
f86a7158 JB |
3133 | if (v->arch == bfd_arch_rs6000) |
3134 | tdep->ppc_sr0_regnum = -1; | |
3135 | else if (v->arch == bfd_arch_powerpc) | |
1fcc0bb8 EZ |
3136 | switch (v->mach) |
3137 | { | |
3138 | case bfd_mach_ppc: | |
412b3060 | 3139 | tdep->ppc_sr0_regnum = -1; |
1fcc0bb8 EZ |
3140 | tdep->ppc_vr0_regnum = 71; |
3141 | tdep->ppc_vrsave_regnum = 104; | |
3142 | break; | |
3143 | case bfd_mach_ppc_7400: | |
3144 | tdep->ppc_vr0_regnum = 119; | |
54c2a1e6 | 3145 | tdep->ppc_vrsave_regnum = 152; |
c8001721 EZ |
3146 | break; |
3147 | case bfd_mach_ppc_e500: | |
c8001721 | 3148 | tdep->ppc_toc_regnum = -1; |
6ced10dd JB |
3149 | tdep->ppc_ev0_upper_regnum = 32; |
3150 | tdep->ppc_ev0_regnum = 73; | |
3151 | tdep->ppc_ev31_regnum = 104; | |
3152 | tdep->ppc_acc_regnum = 71; | |
3153 | tdep->ppc_spefscr_regnum = 72; | |
383f0f5b JB |
3154 | tdep->ppc_fp0_regnum = -1; |
3155 | tdep->ppc_fpscr_regnum = -1; | |
f86a7158 | 3156 | tdep->ppc_sr0_regnum = -1; |
c8001721 EZ |
3157 | set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read); |
3158 | set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write); | |
6ced10dd | 3159 | set_gdbarch_register_reggroup_p (gdbarch, e500_register_reggroup_p); |
1fcc0bb8 | 3160 | break; |
f86a7158 JB |
3161 | |
3162 | case bfd_mach_ppc64: | |
3163 | case bfd_mach_ppc_620: | |
3164 | case bfd_mach_ppc_630: | |
3165 | case bfd_mach_ppc_a35: | |
3166 | case bfd_mach_ppc_rs64ii: | |
3167 | case bfd_mach_ppc_rs64iii: | |
3168 | /* These processor's register sets don't have segment registers. */ | |
3169 | tdep->ppc_sr0_regnum = -1; | |
3170 | break; | |
1fcc0bb8 | 3171 | } |
f86a7158 JB |
3172 | else |
3173 | internal_error (__FILE__, __LINE__, | |
3174 | "rs6000_gdbarch_init: " | |
3175 | "received unexpected BFD 'arch' value"); | |
1fcc0bb8 | 3176 | |
338ef23d AC |
3177 | /* Sanity check on registers. */ |
3178 | gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0); | |
3179 | ||
56a6dfb9 | 3180 | /* Select instruction printer. */ |
708ff411 | 3181 | if (arch == bfd_arch_rs6000) |
9364a0ef | 3182 | set_gdbarch_print_insn (gdbarch, print_insn_rs6000); |
56a6dfb9 | 3183 | else |
9364a0ef | 3184 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc); |
7495d1dc | 3185 | |
7a78ae4e | 3186 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
7a78ae4e ND |
3187 | |
3188 | set_gdbarch_num_regs (gdbarch, v->nregs); | |
c8001721 | 3189 | set_gdbarch_num_pseudo_regs (gdbarch, v->npregs); |
7a78ae4e | 3190 | set_gdbarch_register_name (gdbarch, rs6000_register_name); |
691d145a | 3191 | set_gdbarch_register_type (gdbarch, rs6000_register_type); |
7a78ae4e ND |
3192 | |
3193 | set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
3194 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
3195 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
3196 | set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
3197 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
3198 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
3199 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
ab9fe00e KB |
3200 | if (sysv_abi) |
3201 | set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); | |
3202 | else | |
3203 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4e409299 | 3204 | set_gdbarch_char_signed (gdbarch, 0); |
7a78ae4e | 3205 | |
11269d7e | 3206 | set_gdbarch_frame_align (gdbarch, rs6000_frame_align); |
8b148df9 AC |
3207 | if (sysv_abi && wordsize == 8) |
3208 | /* PPC64 SYSV. */ | |
3209 | set_gdbarch_frame_red_zone_size (gdbarch, 288); | |
3210 | else if (!sysv_abi && wordsize == 4) | |
5bffac25 AC |
3211 | /* PowerOpen / AIX 32 bit. The saved area or red zone consists of |
3212 | 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes. | |
3213 | Problem is, 220 isn't frame (16 byte) aligned. Round it up to | |
3214 | 224. */ | |
3215 | set_gdbarch_frame_red_zone_size (gdbarch, 224); | |
7a78ae4e | 3216 | |
691d145a JB |
3217 | set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p); |
3218 | set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value); | |
3219 | set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register); | |
3220 | ||
18ed0c4e JB |
3221 | set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); |
3222 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum); | |
2ea5f656 KB |
3223 | /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments() |
3224 | is correct for the SysV ABI when the wordsize is 8, but I'm also | |
3225 | fairly certain that ppc_sysv_abi_push_arguments() will give even | |
3226 | worse results since it only works for 32-bit code. So, for the moment, | |
3227 | we're better off calling rs6000_push_arguments() since it works for | |
3228 | 64-bit code. At some point in the future, this matter needs to be | |
3229 | revisited. */ | |
3230 | if (sysv_abi && wordsize == 4) | |
77b2b6d4 | 3231 | set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call); |
8be9034a AC |
3232 | else if (sysv_abi && wordsize == 8) |
3233 | set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call); | |
9aa1e687 | 3234 | else |
77b2b6d4 | 3235 | set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call); |
7a78ae4e | 3236 | |
74055713 | 3237 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address); |
7a78ae4e ND |
3238 | |
3239 | set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); | |
3240 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
7a78ae4e ND |
3241 | set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc); |
3242 | ||
6066c3de AC |
3243 | /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN" |
3244 | for the descriptor and ".FN" for the entry-point -- a user | |
3245 | specifying "break FN" will unexpectedly end up with a breakpoint | |
3246 | on the descriptor and not the function. This architecture method | |
3247 | transforms any breakpoints on descriptors into breakpoints on the | |
3248 | corresponding entry point. */ | |
3249 | if (sysv_abi && wordsize == 8) | |
3250 | set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address); | |
3251 | ||
7a78ae4e ND |
3252 | /* Not sure on this. FIXMEmgo */ |
3253 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
3254 | ||
05580c65 | 3255 | if (!sysv_abi) |
b5622e8d | 3256 | set_gdbarch_deprecated_use_struct_convention (gdbarch, rs6000_use_struct_convention); |
8e0662df | 3257 | |
15813d3f AC |
3258 | if (!sysv_abi) |
3259 | { | |
3260 | /* Handle RS/6000 function pointers (which are really function | |
3261 | descriptors). */ | |
f517ea4e PS |
3262 | set_gdbarch_convert_from_func_ptr_addr (gdbarch, |
3263 | rs6000_convert_from_func_ptr_addr); | |
9aa1e687 | 3264 | } |
7a78ae4e | 3265 | |
143985b7 AF |
3266 | /* Helpers for function argument information. */ |
3267 | set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument); | |
3268 | ||
7b112f9c | 3269 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4be87837 | 3270 | gdbarch_init_osabi (info, gdbarch); |
7b112f9c | 3271 | |
61a65099 KB |
3272 | switch (info.osabi) |
3273 | { | |
3274 | case GDB_OSABI_NETBSD_AOUT: | |
3275 | case GDB_OSABI_NETBSD_ELF: | |
3276 | case GDB_OSABI_UNKNOWN: | |
3277 | case GDB_OSABI_LINUX: | |
3278 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); | |
3279 | frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); | |
3280 | set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); | |
3281 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); | |
3282 | break; | |
3283 | default: | |
61a65099 | 3284 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
81332287 KB |
3285 | |
3286 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); | |
3287 | frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); | |
3288 | set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); | |
3289 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); | |
61a65099 KB |
3290 | } |
3291 | ||
ef5200c1 AC |
3292 | if (from_xcoff_exec) |
3293 | { | |
3294 | /* NOTE: jimix/2003-06-09: This test should really check for | |
3295 | GDB_OSABI_AIX when that is defined and becomes | |
3296 | available. (Actually, once things are properly split apart, | |
3297 | the test goes away.) */ | |
3298 | /* RS6000/AIX does not support PT_STEP. Has to be simulated. */ | |
3299 | set_gdbarch_software_single_step (gdbarch, rs6000_software_single_step); | |
3300 | } | |
3301 | ||
9f643768 JB |
3302 | init_sim_regno_table (gdbarch); |
3303 | ||
7a78ae4e | 3304 | return gdbarch; |
c906108c SS |
3305 | } |
3306 | ||
7b112f9c JT |
3307 | static void |
3308 | rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
3309 | { | |
3310 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3311 | ||
3312 | if (tdep == NULL) | |
3313 | return; | |
3314 | ||
4be87837 | 3315 | /* FIXME: Dump gdbarch_tdep. */ |
7b112f9c JT |
3316 | } |
3317 | ||
1fcc0bb8 EZ |
3318 | static struct cmd_list_element *info_powerpc_cmdlist = NULL; |
3319 | ||
3320 | static void | |
3321 | rs6000_info_powerpc_command (char *args, int from_tty) | |
3322 | { | |
3323 | help_list (info_powerpc_cmdlist, "info powerpc ", class_info, gdb_stdout); | |
3324 | } | |
3325 | ||
c906108c SS |
3326 | /* Initialization code. */ |
3327 | ||
a78f21af | 3328 | extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */ |
b9362cc7 | 3329 | |
c906108c | 3330 | void |
fba45db2 | 3331 | _initialize_rs6000_tdep (void) |
c906108c | 3332 | { |
7b112f9c JT |
3333 | gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); |
3334 | gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); | |
1fcc0bb8 EZ |
3335 | |
3336 | /* Add root prefix command for "info powerpc" commands */ | |
3337 | add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command, | |
3338 | "Various POWERPC info specific commands.", | |
3339 | &info_powerpc_cmdlist, "info powerpc ", 0, &infolist); | |
c906108c | 3340 | } |