Add comment explaining ppc_linux_memory_remove_breakpoint ().
[deliverable/binutils-gdb.git] / gdb / rs6000-tdep.c
CommitLineData
c906108c 1/* Target-dependent code for GDB, the GNU debugger.
c877c8e6 2 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000
c906108c
SS
3 Free Software Foundation, Inc.
4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
c906108c 11
c5aa993b
JM
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b
JM
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
c906108c
SS
21
22#include "defs.h"
23#include "frame.h"
24#include "inferior.h"
25#include "symtab.h"
26#include "target.h"
27#include "gdbcore.h"
28#include "gdbcmd.h"
29#include "symfile.h"
30#include "objfiles.h"
31#include "xcoffsolib.h"
32
33extern int errno;
34
35/* Breakpoint shadows for the single step instructions will be kept here. */
36
c5aa993b
JM
37static struct sstep_breaks
38 {
39 /* Address, or 0 if this is not in use. */
40 CORE_ADDR address;
41 /* Shadow contents. */
42 char data[4];
43 }
44stepBreaks[2];
c906108c
SS
45
46/* Hook for determining the TOC address when calling functions in the
47 inferior under AIX. The initialization code in rs6000-nat.c sets
48 this hook to point to find_toc_address. */
49
50CORE_ADDR (*find_toc_address_hook) PARAMS ((CORE_ADDR)) = NULL;
51
52/* Static function prototypes */
53
c5aa993b
JM
54 static CORE_ADDR branch_dest PARAMS ((int opcode, int instr, CORE_ADDR pc,
55 CORE_ADDR safety));
c906108c 56
c5aa993b
JM
57 static void frame_get_saved_regs PARAMS ((struct frame_info * fi,
58 struct rs6000_framedata * fdatap));
c906108c 59
c5aa993b 60 static void pop_dummy_frame PARAMS ((void));
c906108c 61
c5aa993b 62 static CORE_ADDR frame_initial_stack_address PARAMS ((struct frame_info *));
c906108c 63
b83266a0
SS
64CORE_ADDR
65rs6000_skip_prologue (pc)
66 CORE_ADDR pc;
67{
68 struct rs6000_framedata frame;
69 pc = skip_prologue (pc, &frame);
70 return pc;
71}
72
73
c906108c
SS
74/* Fill in fi->saved_regs */
75
76struct frame_extra_info
77{
78 /* Functions calling alloca() change the value of the stack
79 pointer. We need to use initial stack pointer (which is saved in
80 r31 by gcc) in such cases. If a compiler emits traceback table,
81 then we should use the alloca register specified in traceback
82 table. FIXME. */
c5aa993b 83 CORE_ADDR initial_sp; /* initial stack pointer. */
c906108c
SS
84};
85
86void
87rs6000_init_extra_frame_info (fromleaf, fi)
88 int fromleaf;
89 struct frame_info *fi;
90{
c5aa993b 91 fi->extra_info = (struct frame_extra_info *)
c906108c
SS
92 frame_obstack_alloc (sizeof (struct frame_extra_info));
93 fi->extra_info->initial_sp = 0;
94 if (fi->next != (CORE_ADDR) 0
95 && fi->pc < TEXT_SEGMENT_BASE)
7a292a7a 96 /* We're in get_prev_frame */
c906108c
SS
97 /* and this is a special signal frame. */
98 /* (fi->pc will be some low address in the kernel, */
99 /* to which the signal handler returns). */
100 fi->signal_handler_caller = 1;
101}
102
103
104void
105rs6000_frame_init_saved_regs (fi)
106 struct frame_info *fi;
107{
108 frame_get_saved_regs (fi, NULL);
109}
110
111CORE_ADDR
112rs6000_frame_args_address (fi)
113 struct frame_info *fi;
114{
115 if (fi->extra_info->initial_sp != 0)
116 return fi->extra_info->initial_sp;
117 else
118 return frame_initial_stack_address (fi);
119}
120
121
122/* Calculate the destination of a branch/jump. Return -1 if not a branch. */
123
124static CORE_ADDR
125branch_dest (opcode, instr, pc, safety)
126 int opcode;
127 int instr;
128 CORE_ADDR pc;
129 CORE_ADDR safety;
130{
131 CORE_ADDR dest;
132 int immediate;
133 int absolute;
134 int ext_op;
135
136 absolute = (int) ((instr >> 1) & 1);
137
c5aa993b
JM
138 switch (opcode)
139 {
140 case 18:
141 immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */
142 if (absolute)
143 dest = immediate;
144 else
145 dest = pc + immediate;
146 break;
147
148 case 16:
149 immediate = ((instr & ~3) << 16) >> 16; /* br conditional */
150 if (absolute)
151 dest = immediate;
152 else
153 dest = pc + immediate;
154 break;
155
156 case 19:
157 ext_op = (instr >> 1) & 0x3ff;
158
159 if (ext_op == 16) /* br conditional register */
160 {
161 dest = read_register (LR_REGNUM) & ~3;
162
163 /* If we are about to return from a signal handler, dest is
164 something like 0x3c90. The current frame is a signal handler
165 caller frame, upon completion of the sigreturn system call
166 execution will return to the saved PC in the frame. */
167 if (dest < TEXT_SEGMENT_BASE)
168 {
169 struct frame_info *fi;
170
171 fi = get_current_frame ();
172 if (fi != NULL)
173 dest = read_memory_integer (fi->frame + SIG_FRAME_PC_OFFSET,
174 4);
175 }
176 }
177
178 else if (ext_op == 528) /* br cond to count reg */
179 {
180 dest = read_register (CTR_REGNUM) & ~3;
181
182 /* If we are about to execute a system call, dest is something
183 like 0x22fc or 0x3b00. Upon completion the system call
184 will return to the address in the link register. */
185 if (dest < TEXT_SEGMENT_BASE)
c906108c 186 dest = read_register (LR_REGNUM) & ~3;
c5aa993b
JM
187 }
188 else
189 return -1;
190 break;
c906108c 191
c5aa993b
JM
192 default:
193 return -1;
194 }
c906108c
SS
195 return (dest < TEXT_SEGMENT_BASE) ? safety : dest;
196}
197
198
199/* Sequence of bytes for breakpoint instruction. */
200
201#define BIG_BREAKPOINT { 0x7d, 0x82, 0x10, 0x08 }
202#define LITTLE_BREAKPOINT { 0x08, 0x10, 0x82, 0x7d }
203
204unsigned char *
205rs6000_breakpoint_from_pc (bp_addr, bp_size)
206 CORE_ADDR *bp_addr;
207 int *bp_size;
208{
209 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
210 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
211 *bp_size = 4;
212 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
213 return big_breakpoint;
214 else
215 return little_breakpoint;
216}
217
218
219/* AIX does not support PT_STEP. Simulate it. */
220
221void
222rs6000_software_single_step (signal, insert_breakpoints_p)
223 unsigned int signal;
224 int insert_breakpoints_p;
225{
226#define INSNLEN(OPCODE) 4
227
228 static char le_breakp[] = LITTLE_BREAKPOINT;
229 static char be_breakp[] = BIG_BREAKPOINT;
230 char *breakp = TARGET_BYTE_ORDER == BIG_ENDIAN ? be_breakp : le_breakp;
231 int ii, insn;
232 CORE_ADDR loc;
233 CORE_ADDR breaks[2];
234 int opcode;
235
c5aa993b
JM
236 if (insert_breakpoints_p)
237 {
c906108c 238
c5aa993b 239 loc = read_pc ();
c906108c 240
c5aa993b 241 insn = read_memory_integer (loc, 4);
c906108c 242
c5aa993b
JM
243 breaks[0] = loc + INSNLEN (insn);
244 opcode = insn >> 26;
245 breaks[1] = branch_dest (opcode, insn, loc, breaks[0]);
c906108c 246
c5aa993b
JM
247 /* Don't put two breakpoints on the same address. */
248 if (breaks[1] == breaks[0])
249 breaks[1] = -1;
c906108c 250
c5aa993b 251 stepBreaks[1].address = 0;
c906108c 252
c5aa993b
JM
253 for (ii = 0; ii < 2; ++ii)
254 {
c906108c 255
c5aa993b
JM
256 /* ignore invalid breakpoint. */
257 if (breaks[ii] == -1)
258 continue;
c906108c 259
c5aa993b 260 read_memory (breaks[ii], stepBreaks[ii].data, 4);
c906108c 261
c5aa993b
JM
262 write_memory (breaks[ii], breakp, 4);
263 stepBreaks[ii].address = breaks[ii];
264 }
c906108c 265
c5aa993b
JM
266 }
267 else
268 {
c906108c 269
c5aa993b
JM
270 /* remove step breakpoints. */
271 for (ii = 0; ii < 2; ++ii)
272 if (stepBreaks[ii].address != 0)
273 write_memory
274 (stepBreaks[ii].address, stepBreaks[ii].data, 4);
c906108c 275
c5aa993b 276 }
c906108c 277 errno = 0; /* FIXME, don't ignore errors! */
c5aa993b 278 /* What errors? {read,write}_memory call error(). */
c906108c
SS
279}
280
281
282/* return pc value after skipping a function prologue and also return
283 information about a function frame.
284
285 in struct rs6000_framedata fdata:
c5aa993b
JM
286 - frameless is TRUE, if function does not have a frame.
287 - nosavedpc is TRUE, if function does not save %pc value in its frame.
288 - offset is the initial size of this stack frame --- the amount by
289 which we decrement the sp to allocate the frame.
290 - saved_gpr is the number of the first saved gpr.
291 - saved_fpr is the number of the first saved fpr.
292 - alloca_reg is the number of the register used for alloca() handling.
293 Otherwise -1.
294 - gpr_offset is the offset of the first saved gpr from the previous frame.
295 - fpr_offset is the offset of the first saved fpr from the previous frame.
296 - lr_offset is the offset of the saved lr
297 - cr_offset is the offset of the saved cr
298 */
c906108c
SS
299
300#define SIGNED_SHORT(x) \
301 ((sizeof (short) == 2) \
302 ? ((int)(short)(x)) \
303 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
304
305#define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
306
307CORE_ADDR
308skip_prologue (pc, fdata)
309 CORE_ADDR pc;
c5aa993b 310 struct rs6000_framedata *fdata;
c906108c
SS
311{
312 CORE_ADDR orig_pc = pc;
313 char buf[4];
314 unsigned long op;
315 long offset = 0;
482ca3f5
KB
316 int lr_reg = -1;
317 int cr_reg = -1;
c906108c
SS
318 int reg;
319 int framep = 0;
320 int minimal_toc_loaded = 0;
321 static struct rs6000_framedata zero_frame;
322
323 *fdata = zero_frame;
324 fdata->saved_gpr = -1;
325 fdata->saved_fpr = -1;
326 fdata->alloca_reg = -1;
327 fdata->frameless = 1;
328 fdata->nosavedpc = 1;
329
330 if (target_read_memory (pc, buf, 4))
331 return pc; /* Can't access it -- assume no prologue. */
332
333 /* Assume that subsequent fetches can fail with low probability. */
334 pc -= 4;
335 for (;;)
336 {
337 pc += 4;
338 op = read_memory_integer (pc, 4);
339
c5aa993b
JM
340 if ((op & 0xfc1fffff) == 0x7c0802a6)
341 { /* mflr Rx */
342 lr_reg = (op & 0x03e00000) | 0x90010000;
343 continue;
c906108c 344
c5aa993b
JM
345 }
346 else if ((op & 0xfc1fffff) == 0x7c000026)
347 { /* mfcr Rx */
348 cr_reg = (op & 0x03e00000) | 0x90010000;
349 continue;
c906108c 350
c906108c 351 }
c5aa993b
JM
352 else if ((op & 0xfc1f0000) == 0xd8010000)
353 { /* stfd Rx,NUM(r1) */
354 reg = GET_SRC_REG (op);
355 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
356 {
357 fdata->saved_fpr = reg;
358 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
359 }
360 continue;
c906108c 361
c5aa993b
JM
362 }
363 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
364 ((op & 0xfc1f0000) == 0x90010000 && /* st rx,NUM(r1),
c906108c 365 rx >= r13 */
c5aa993b
JM
366 (op & 0x03e00000) >= 0x01a00000))
367 {
368
369 reg = GET_SRC_REG (op);
370 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
371 {
372 fdata->saved_gpr = reg;
373 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
374 }
375 continue;
c906108c 376
c906108c 377 }
c5aa993b
JM
378 else if ((op & 0xffff0000) == 0x3c000000)
379 { /* addis 0,0,NUM, used
380 for >= 32k frames */
381 fdata->offset = (op & 0x0000ffff) << 16;
382 fdata->frameless = 0;
383 continue;
384
385 }
386 else if ((op & 0xffff0000) == 0x60000000)
387 { /* ori 0,0,NUM, 2nd ha
388 lf of >= 32k frames */
389 fdata->offset |= (op & 0x0000ffff);
390 fdata->frameless = 0;
391 continue;
392
393 }
482ca3f5 394 else if (lr_reg != -1 && (op & 0xffff0000) == lr_reg)
c5aa993b
JM
395 { /* st Rx,NUM(r1)
396 where Rx == lr */
397 fdata->lr_offset = SIGNED_SHORT (op) + offset;
398 fdata->nosavedpc = 0;
399 lr_reg = 0;
400 continue;
401
402 }
482ca3f5 403 else if (cr_reg != -1 && (op & 0xffff0000) == cr_reg)
c5aa993b
JM
404 { /* st Rx,NUM(r1)
405 where Rx == cr */
406 fdata->cr_offset = SIGNED_SHORT (op) + offset;
407 cr_reg = 0;
408 continue;
409
410 }
411 else if (op == 0x48000005)
412 { /* bl .+4 used in
413 -mrelocatable */
414 continue;
415
416 }
417 else if (op == 0x48000004)
418 { /* b .+4 (xlc) */
419 break;
420
421 }
422 else if (((op & 0xffff0000) == 0x801e0000 || /* lwz 0,NUM(r30), used
c906108c 423 in V.4 -mrelocatable */
c5aa993b
JM
424 op == 0x7fc0f214) && /* add r30,r0,r30, used
425 in V.4 -mrelocatable */
426 lr_reg == 0x901e0000)
427 {
428 continue;
c906108c 429
c5aa993b
JM
430 }
431 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
c906108c 432 in V.4 -mminimal-toc */
c5aa993b
JM
433 (op & 0xffff0000) == 0x3bde0000)
434 { /* addi 30,30,foo@l */
435 continue;
c906108c 436
c5aa993b
JM
437 }
438 else if ((op & 0xfc000001) == 0x48000001)
439 { /* bl foo,
440 to save fprs??? */
c906108c 441
c5aa993b
JM
442 fdata->frameless = 0;
443 /* Don't skip over the subroutine call if it is not within the first
444 three instructions of the prologue. */
445 if ((pc - orig_pc) > 8)
446 break;
447
448 op = read_memory_integer (pc + 4, 4);
449
450 /* At this point, make sure this is not a trampoline function
451 (a function that simply calls another functions, and nothing else).
452 If the next is not a nop, this branch was part of the function
453 prologue. */
454
455 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
456 break; /* don't skip over
457 this branch */
458 continue;
459
460 /* update stack pointer */
461 }
462 else if ((op & 0xffff0000) == 0x94210000)
463 { /* stu r1,NUM(r1) */
464 fdata->frameless = 0;
465 fdata->offset = SIGNED_SHORT (op);
466 offset = fdata->offset;
467 continue;
468
469 }
470 else if (op == 0x7c21016e)
471 { /* stwux 1,1,0 */
472 fdata->frameless = 0;
473 offset = fdata->offset;
474 continue;
475
476 /* Load up minimal toc pointer */
477 }
478 else if ((op >> 22) == 0x20f
479 && !minimal_toc_loaded)
480 { /* l r31,... or l r30,... */
481 minimal_toc_loaded = 1;
482 continue;
483
f6077098
KB
484 /* move parameters from argument registers to local variable
485 registers */
486 }
487 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
488 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
489 (((op >> 21) & 31) <= 10) &&
490 (((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
491 {
492 continue;
493
c5aa993b
JM
494 /* store parameters in stack */
495 }
496 else if ((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
497 (op & 0xfc1f0000) == 0xd8010000 || /* stfd Rx,NUM(r1) */
498 (op & 0xfc1f0000) == 0xfc010000)
499 { /* frsp, fp?,NUM(r1) */
500 continue;
c906108c 501
c5aa993b
JM
502 /* store parameters in stack via frame pointer */
503 }
504 else if (framep &&
505 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r1) */
506 (op & 0xfc1f0000) == 0xd81f0000 || /* stfd Rx,NUM(r1) */
507 (op & 0xfc1f0000) == 0xfc1f0000))
508 { /* frsp, fp?,NUM(r1) */
509 continue;
510
511 /* Set up frame pointer */
512 }
513 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
514 || op == 0x7c3f0b78)
515 { /* mr r31, r1 */
516 fdata->frameless = 0;
517 framep = 1;
518 fdata->alloca_reg = 31;
519 continue;
520
521 /* Another way to set up the frame pointer. */
522 }
523 else if ((op & 0xfc1fffff) == 0x38010000)
524 { /* addi rX, r1, 0x0 */
525 fdata->frameless = 0;
526 framep = 1;
527 fdata->alloca_reg = (op & ~0x38010000) >> 21;
528 continue;
529
530 }
531 else
532 {
533 break;
534 }
c906108c
SS
535 }
536
537#if 0
538/* I have problems with skipping over __main() that I need to address
539 * sometime. Previously, I used to use misc_function_vector which
540 * didn't work as well as I wanted to be. -MGO */
541
542 /* If the first thing after skipping a prolog is a branch to a function,
543 this might be a call to an initializer in main(), introduced by gcc2.
544 We'd like to skip over it as well. Fortunately, xlc does some extra
545 work before calling a function right after a prologue, thus we can
546 single out such gcc2 behaviour. */
c906108c 547
c906108c 548
c5aa993b
JM
549 if ((op & 0xfc000001) == 0x48000001)
550 { /* bl foo, an initializer function? */
551 op = read_memory_integer (pc + 4, 4);
552
553 if (op == 0x4def7b82)
554 { /* cror 0xf, 0xf, 0xf (nop) */
c906108c 555
c5aa993b
JM
556 /* check and see if we are in main. If so, skip over this initializer
557 function as well. */
c906108c 558
c5aa993b
JM
559 tmp = find_pc_misc_function (pc);
560 if (tmp >= 0 && STREQ (misc_function_vector[tmp].name, "main"))
561 return pc + 8;
562 }
c906108c 563 }
c906108c 564#endif /* 0 */
c5aa993b
JM
565
566 fdata->offset = -fdata->offset;
c906108c
SS
567 return pc;
568}
569
570
571/*************************************************************************
f6077098 572 Support for creating pushing a dummy frame into the stack, and popping
c906108c
SS
573 frames, etc.
574*************************************************************************/
575
576/* The total size of dummy frame is 436, which is;
577
f6077098
KB
578 32 gpr's - 128 bytes
579 32 fpr's - 256 bytes
580 7 the rest - 28 bytes
581 callee's link area - 24 bytes
582 padding - 12 bytes
c906108c 583
f6077098
KB
584 Note that the last 24 bytes for the link area might not be necessary,
585 since it will be taken care of by push_arguments(). */
586
587#define DUMMY_FRAME_SIZE 448
c906108c
SS
588
589#define DUMMY_FRAME_ADDR_SIZE 10
590
591/* Make sure you initialize these in somewhere, in case gdb gives up what it
592 was debugging and starts debugging something else. FIXMEibm */
593
594static int dummy_frame_count = 0;
595static int dummy_frame_size = 0;
596static CORE_ADDR *dummy_frame_addr = 0;
597
598extern int stop_stack_dummy;
599
600/* push a dummy frame into stack, save all register. Currently we are saving
601 only gpr's and fpr's, which is not good enough! FIXMEmgo */
c5aa993b 602
c906108c
SS
603void
604push_dummy_frame ()
605{
606 /* stack pointer. */
607 CORE_ADDR sp;
608 /* Same thing, target byte order. */
609 char sp_targ[4];
610
611 /* link register. */
612 CORE_ADDR pc;
613 /* Same thing, target byte order. */
614 char pc_targ[4];
c5aa993b 615
c906108c
SS
616 /* Needed to figure out where to save the dummy link area.
617 FIXME: There should be an easier way to do this, no? tiemann 9/9/95. */
618 struct rs6000_framedata fdata;
619
620 int ii;
621
622 target_fetch_registers (-1);
623
c5aa993b
JM
624 if (dummy_frame_count >= dummy_frame_size)
625 {
626 dummy_frame_size += DUMMY_FRAME_ADDR_SIZE;
627 if (dummy_frame_addr)
628 dummy_frame_addr = (CORE_ADDR *) xrealloc
629 (dummy_frame_addr, sizeof (CORE_ADDR) * (dummy_frame_size));
630 else
631 dummy_frame_addr = (CORE_ADDR *)
632 xmalloc (sizeof (CORE_ADDR) * (dummy_frame_size));
633 }
634
635 sp = read_register (SP_REGNUM);
636 pc = read_register (PC_REGNUM);
c906108c
SS
637 store_address (pc_targ, 4, pc);
638
639 skip_prologue (get_pc_function_start (pc), &fdata);
640
c5aa993b 641 dummy_frame_addr[dummy_frame_count++] = sp;
c906108c
SS
642
643 /* Be careful! If the stack pointer is not decremented first, then kernel
644 thinks he is free to use the space underneath it. And kernel actually
645 uses that area for IPC purposes when executing ptrace(2) calls. So
646 before writing register values into the new frame, decrement and update
647 %sp first in order to secure your frame. */
648
649 /* FIXME: We don't check if the stack really has this much space.
650 This is a problem on the ppc simulator (which only grants one page
651 (4096 bytes) by default. */
652
c5aa993b 653 write_register (SP_REGNUM, sp - DUMMY_FRAME_SIZE);
c906108c
SS
654
655 /* gdb relies on the state of current_frame. We'd better update it,
656 otherwise things like do_registers_info() wouldn't work properly! */
657
658 flush_cached_frames ();
659
660 /* save program counter in link register's space. */
661 write_memory (sp + (fdata.lr_offset ? fdata.lr_offset : DEFAULT_LR_SAVE),
c5aa993b 662 pc_targ, 4);
c906108c
SS
663
664 /* save all floating point and general purpose registers here. */
665
666 /* fpr's, f0..f31 */
667 for (ii = 0; ii < 32; ++ii)
c5aa993b 668 write_memory (sp - 8 - (ii * 8), &registers[REGISTER_BYTE (31 - ii + FP0_REGNUM)], 8);
c906108c
SS
669
670 /* gpr's r0..r31 */
c5aa993b
JM
671 for (ii = 1; ii <= 32; ++ii)
672 write_memory (sp - 256 - (ii * 4), &registers[REGISTER_BYTE (32 - ii)], 4);
c906108c
SS
673
674 /* so far, 32*2 + 32 words = 384 bytes have been written.
675 7 extra registers in our register set: pc, ps, cnd, lr, cnt, xer, mq */
676
c5aa993b
JM
677 for (ii = 1; ii <= (LAST_UISA_SP_REGNUM - FIRST_UISA_SP_REGNUM + 1); ++ii)
678 {
679 write_memory (sp - 384 - (ii * 4),
680 &registers[REGISTER_BYTE (FPLAST_REGNUM + ii)], 4);
681 }
c906108c
SS
682
683 /* Save sp or so called back chain right here. */
684 store_address (sp_targ, 4, sp);
c5aa993b 685 write_memory (sp - DUMMY_FRAME_SIZE, sp_targ, 4);
c906108c
SS
686 sp -= DUMMY_FRAME_SIZE;
687
688 /* And finally, this is the back chain. */
c5aa993b 689 write_memory (sp + 8, pc_targ, 4);
c906108c
SS
690}
691
692
693/* Pop a dummy frame.
694
695 In rs6000 when we push a dummy frame, we save all of the registers. This
696 is usually done before user calls a function explicitly.
697
698 After a dummy frame is pushed, some instructions are copied into stack,
699 and stack pointer is decremented even more. Since we don't have a frame
700 pointer to get back to the parent frame of the dummy, we start having
701 trouble poping it. Therefore, we keep a dummy frame stack, keeping
702 addresses of dummy frames as such. When poping happens and when we
703 detect that was a dummy frame, we pop it back to its parent by using
704 dummy frame stack (`dummy_frame_addr' array).
705
c5aa993b
JM
706 FIXME: This whole concept is broken. You should be able to detect
707 a dummy stack frame *on the user's stack itself*. When you do,
708 then you know the format of that stack frame -- including its
709 saved SP register! There should *not* be a separate stack in the
710 GDB process that keeps track of these dummy frames! -- gnu@cygnus.com Aug92
c906108c 711 */
c5aa993b 712
c906108c
SS
713static void
714pop_dummy_frame ()
715{
716 CORE_ADDR sp, pc;
717 int ii;
c5aa993b 718 sp = dummy_frame_addr[--dummy_frame_count];
c906108c
SS
719
720 /* restore all fpr's. */
721 for (ii = 1; ii <= 32; ++ii)
c5aa993b 722 read_memory (sp - (ii * 8), &registers[REGISTER_BYTE (32 - ii + FP0_REGNUM)], 8);
c906108c
SS
723
724 /* restore all gpr's */
c5aa993b
JM
725 for (ii = 1; ii <= 32; ++ii)
726 {
727 read_memory (sp - 256 - (ii * 4), &registers[REGISTER_BYTE (32 - ii)], 4);
728 }
c906108c
SS
729
730 /* restore the rest of the registers. */
c5aa993b
JM
731 for (ii = 1; ii <= (LAST_UISA_SP_REGNUM - FIRST_UISA_SP_REGNUM + 1); ++ii)
732 read_memory (sp - 384 - (ii * 4),
733 &registers[REGISTER_BYTE (FPLAST_REGNUM + ii)], 4);
c906108c 734
c5aa993b
JM
735 read_memory (sp - (DUMMY_FRAME_SIZE - 8),
736 &registers[REGISTER_BYTE (PC_REGNUM)], 4);
c906108c
SS
737
738 /* when a dummy frame was being pushed, we had to decrement %sp first, in
739 order to secure astack space. Thus, saved %sp (or %r1) value, is not the
740 one we should restore. Change it with the one we need. */
741
c5aa993b 742 memcpy (&registers[REGISTER_BYTE (FP_REGNUM)], (char *) &sp, sizeof (int));
c906108c
SS
743
744 /* Now we can restore all registers. */
745
746 target_store_registers (-1);
747 pc = read_pc ();
748 flush_cached_frames ();
749}
750
751
752/* pop the innermost frame, go back to the caller. */
753
754void
755pop_frame ()
756{
c5aa993b 757 CORE_ADDR pc, lr, sp, prev_sp; /* %pc, %lr, %sp */
c906108c
SS
758 struct rs6000_framedata fdata;
759 struct frame_info *frame = get_current_frame ();
760 int addr, ii;
761
762 pc = read_pc ();
763 sp = FRAME_FP (frame);
764
765 if (stop_stack_dummy)
766 {
7a292a7a
SS
767 if (USE_GENERIC_DUMMY_FRAMES)
768 {
769 generic_pop_dummy_frame ();
770 flush_cached_frames ();
771 return;
772 }
773 else
774 {
c5aa993b 775 if (dummy_frame_count)
7a292a7a
SS
776 pop_dummy_frame ();
777 return;
778 }
c906108c
SS
779 }
780
781 /* Make sure that all registers are valid. */
782 read_register_bytes (0, NULL, REGISTER_BYTES);
783
784 /* figure out previous %pc value. If the function is frameless, it is
785 still in the link register, otherwise walk the frames and retrieve the
786 saved %pc value in the previous frame. */
787
788 addr = get_pc_function_start (frame->pc);
789 (void) skip_prologue (addr, &fdata);
790
791 if (fdata.frameless)
792 prev_sp = sp;
793 else
794 prev_sp = read_memory_integer (sp, 4);
795 if (fdata.lr_offset == 0)
796 lr = read_register (LR_REGNUM);
797 else
798 lr = read_memory_integer (prev_sp + fdata.lr_offset, 4);
799
800 /* reset %pc value. */
801 write_register (PC_REGNUM, lr);
802
803 /* reset register values if any was saved earlier. */
804
805 if (fdata.saved_gpr != -1)
806 {
807 addr = prev_sp + fdata.gpr_offset;
c5aa993b
JM
808 for (ii = fdata.saved_gpr; ii <= 31; ++ii)
809 {
810 read_memory (addr, &registers[REGISTER_BYTE (ii)], 4);
811 addr += 4;
812 }
c906108c
SS
813 }
814
815 if (fdata.saved_fpr != -1)
816 {
817 addr = prev_sp + fdata.fpr_offset;
c5aa993b
JM
818 for (ii = fdata.saved_fpr; ii <= 31; ++ii)
819 {
820 read_memory (addr, &registers[REGISTER_BYTE (ii + FP0_REGNUM)], 8);
821 addr += 8;
822 }
c906108c
SS
823 }
824
825 write_register (SP_REGNUM, prev_sp);
826 target_store_registers (-1);
827 flush_cached_frames ();
828}
829
830/* fixup the call sequence of a dummy function, with the real function address.
831 its argumets will be passed by gdb. */
832
833void
834rs6000_fix_call_dummy (dummyname, pc, fun, nargs, args, type, gcc_p)
835 char *dummyname;
836 CORE_ADDR pc;
837 CORE_ADDR fun;
838 int nargs;
839 value_ptr *args;
840 struct type *type;
841 int gcc_p;
842{
843#define TOC_ADDR_OFFSET 20
844#define TARGET_ADDR_OFFSET 28
845
846 int ii;
847 CORE_ADDR target_addr;
848
f6077098
KB
849 if (USE_GENERIC_DUMMY_FRAMES)
850 {
851 if (find_toc_address_hook != NULL)
852 {
853 CORE_ADDR tocvalue = (*find_toc_address_hook) (fun);
854 write_register (TOC_REGNUM, tocvalue);
855 }
856 }
857 else
c906108c 858 {
f6077098
KB
859 if (find_toc_address_hook != NULL)
860 {
861 CORE_ADDR tocvalue;
c906108c 862
f6077098
KB
863 tocvalue = (*find_toc_address_hook) (fun);
864 ii = *(int *) ((char *) dummyname + TOC_ADDR_OFFSET);
865 ii = (ii & 0xffff0000) | (tocvalue >> 16);
866 *(int *) ((char *) dummyname + TOC_ADDR_OFFSET) = ii;
c906108c 867
f6077098
KB
868 ii = *(int *) ((char *) dummyname + TOC_ADDR_OFFSET + 4);
869 ii = (ii & 0xffff0000) | (tocvalue & 0x0000ffff);
870 *(int *) ((char *) dummyname + TOC_ADDR_OFFSET + 4) = ii;
871 }
c906108c 872
f6077098
KB
873 target_addr = fun;
874 ii = *(int *) ((char *) dummyname + TARGET_ADDR_OFFSET);
875 ii = (ii & 0xffff0000) | (target_addr >> 16);
876 *(int *) ((char *) dummyname + TARGET_ADDR_OFFSET) = ii;
c906108c 877
f6077098
KB
878 ii = *(int *) ((char *) dummyname + TARGET_ADDR_OFFSET + 4);
879 ii = (ii & 0xffff0000) | (target_addr & 0x0000ffff);
880 *(int *) ((char *) dummyname + TARGET_ADDR_OFFSET + 4) = ii;
881 }
c906108c
SS
882}
883
884/* Pass the arguments in either registers, or in the stack. In RS6000,
885 the first eight words of the argument list (that might be less than
886 eight parameters if some parameters occupy more than one word) are
887 passed in r3..r11 registers. float and double parameters are
888 passed in fpr's, in addition to that. Rest of the parameters if any
889 are passed in user stack. There might be cases in which half of the
890 parameter is copied into registers, the other half is pushed into
891 stack.
892
893 If the function is returning a structure, then the return address is passed
894 in r3, then the first 7 words of the parameters can be passed in registers,
895 starting from r4. */
896
897CORE_ADDR
392a587b 898rs6000_push_arguments (nargs, args, sp, struct_return, struct_addr)
c906108c
SS
899 int nargs;
900 value_ptr *args;
901 CORE_ADDR sp;
902 int struct_return;
903 CORE_ADDR struct_addr;
904{
905 int ii;
906 int len = 0;
c5aa993b
JM
907 int argno; /* current argument number */
908 int argbytes; /* current argument byte */
909 char tmp_buffer[50];
910 int f_argno = 0; /* current floating point argno */
c906108c
SS
911
912 value_ptr arg = 0;
913 struct type *type;
914
915 CORE_ADDR saved_sp;
916
7a292a7a
SS
917 if (!USE_GENERIC_DUMMY_FRAMES)
918 {
919 if (dummy_frame_count <= 0)
920 printf_unfiltered ("FATAL ERROR -push_arguments()! frame not found!!\n");
921 }
c906108c
SS
922
923 /* The first eight words of ther arguments are passed in registers. Copy
924 them appropriately.
925
926 If the function is returning a `struct', then the first word (which
927 will be passed in r3) is used for struct return address. In that
928 case we should advance one word and start from r4 register to copy
929 parameters. */
930
c5aa993b 931 ii = struct_return ? 1 : 0;
c906108c
SS
932
933/*
c5aa993b
JM
934 effectively indirect call... gcc does...
935
936 return_val example( float, int);
937
938 eabi:
939 float in fp0, int in r3
940 offset of stack on overflow 8/16
941 for varargs, must go by type.
942 power open:
943 float in r3&r4, int in r5
944 offset of stack on overflow different
945 both:
946 return in r3 or f0. If no float, must study how gcc emulates floats;
947 pay attention to arg promotion.
948 User may have to cast\args to handle promotion correctly
949 since gdb won't know if prototype supplied or not.
950 */
c906108c 951
c5aa993b
JM
952 for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
953 {
f6077098 954 int reg_size = REGISTER_RAW_SIZE (ii + 3);
c5aa993b
JM
955
956 arg = args[argno];
957 type = check_typedef (VALUE_TYPE (arg));
958 len = TYPE_LENGTH (type);
959
960 if (TYPE_CODE (type) == TYPE_CODE_FLT)
961 {
962
963 /* floating point arguments are passed in fpr's, as well as gpr's.
964 There are 13 fpr's reserved for passing parameters. At this point
965 there is no way we would run out of them. */
966
967 if (len > 8)
968 printf_unfiltered (
969 "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno);
970
971 memcpy (&registers[REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)],
972 VALUE_CONTENTS (arg),
973 len);
974 ++f_argno;
975 }
976
f6077098 977 if (len > reg_size)
c5aa993b
JM
978 {
979
980 /* Argument takes more than one register. */
981 while (argbytes < len)
982 {
f6077098 983 memset (&registers[REGISTER_BYTE (ii + 3)], 0, reg_size);
c5aa993b
JM
984 memcpy (&registers[REGISTER_BYTE (ii + 3)],
985 ((char *) VALUE_CONTENTS (arg)) + argbytes,
f6077098
KB
986 (len - argbytes) > reg_size
987 ? reg_size : len - argbytes);
988 ++ii, argbytes += reg_size;
c5aa993b
JM
989
990 if (ii >= 8)
991 goto ran_out_of_registers_for_arguments;
992 }
993 argbytes = 0;
994 --ii;
995 }
996 else
997 { /* Argument can fit in one register. No problem. */
f6077098
KB
998 int adj = TARGET_BYTE_ORDER == BIG_ENDIAN ? reg_size - len : 0;
999 memset (&registers[REGISTER_BYTE (ii + 3)], 0, reg_size);
1000 memcpy ((char *)&registers[REGISTER_BYTE (ii + 3)] + adj,
1001 VALUE_CONTENTS (arg), len);
c5aa993b
JM
1002 }
1003 ++argno;
c906108c 1004 }
c906108c
SS
1005
1006ran_out_of_registers_for_arguments:
1007
7a292a7a
SS
1008 if (USE_GENERIC_DUMMY_FRAMES)
1009 {
1010 saved_sp = read_sp ();
f6077098
KB
1011#ifndef ELF_OBJECT_FORMAT
1012 /* location for 8 parameters are always reserved. */
1013 sp -= 4 * 8;
1014
1015 /* another six words for back chain, TOC register, link register, etc. */
1016 sp -= 24;
1017
1018 /* stack pointer must be quadword aligned */
1019 sp &= -16;
1020#endif
7a292a7a
SS
1021 }
1022 else
1023 {
1024 /* location for 8 parameters are always reserved. */
1025 sp -= 4 * 8;
1026
1027 /* another six words for back chain, TOC register, link register, etc. */
1028 sp -= 24;
f6077098
KB
1029
1030 /* stack pointer must be quadword aligned */
1031 sp &= -16;
7a292a7a 1032 }
c906108c 1033
c906108c
SS
1034 /* if there are more arguments, allocate space for them in
1035 the stack, then push them starting from the ninth one. */
1036
c5aa993b
JM
1037 if ((argno < nargs) || argbytes)
1038 {
1039 int space = 0, jj;
c906108c 1040
c5aa993b
JM
1041 if (argbytes)
1042 {
1043 space += ((len - argbytes + 3) & -4);
1044 jj = argno + 1;
1045 }
1046 else
1047 jj = argno;
c906108c 1048
c5aa993b
JM
1049 for (; jj < nargs; ++jj)
1050 {
1051 value_ptr val = args[jj];
1052 space += ((TYPE_LENGTH (VALUE_TYPE (val))) + 3) & -4;
1053 }
c906108c 1054
c5aa993b 1055 /* add location required for the rest of the parameters */
f6077098 1056 space = (space + 15) & -16;
c5aa993b 1057 sp -= space;
c906108c 1058
c5aa993b
JM
1059 /* This is another instance we need to be concerned about securing our
1060 stack space. If we write anything underneath %sp (r1), we might conflict
1061 with the kernel who thinks he is free to use this area. So, update %sp
1062 first before doing anything else. */
c906108c 1063
c5aa993b 1064 write_register (SP_REGNUM, sp);
c906108c 1065
c5aa993b
JM
1066 /* if the last argument copied into the registers didn't fit there
1067 completely, push the rest of it into stack. */
c906108c 1068
c5aa993b
JM
1069 if (argbytes)
1070 {
1071 write_memory (sp + 24 + (ii * 4),
1072 ((char *) VALUE_CONTENTS (arg)) + argbytes,
1073 len - argbytes);
1074 ++argno;
1075 ii += ((len - argbytes + 3) & -4) / 4;
1076 }
c906108c 1077
c5aa993b
JM
1078 /* push the rest of the arguments into stack. */
1079 for (; argno < nargs; ++argno)
1080 {
c906108c 1081
c5aa993b
JM
1082 arg = args[argno];
1083 type = check_typedef (VALUE_TYPE (arg));
1084 len = TYPE_LENGTH (type);
c906108c
SS
1085
1086
c5aa993b
JM
1087 /* float types should be passed in fpr's, as well as in the stack. */
1088 if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
1089 {
c906108c 1090
c5aa993b
JM
1091 if (len > 8)
1092 printf_unfiltered (
1093 "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno);
c906108c 1094
c5aa993b
JM
1095 memcpy (&registers[REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)],
1096 VALUE_CONTENTS (arg),
1097 len);
1098 ++f_argno;
1099 }
c906108c 1100
c5aa993b
JM
1101 write_memory (sp + 24 + (ii * 4), (char *) VALUE_CONTENTS (arg), len);
1102 ii += ((len + 3) & -4) / 4;
1103 }
c906108c 1104 }
c906108c
SS
1105 else
1106 /* Secure stack areas first, before doing anything else. */
1107 write_register (SP_REGNUM, sp);
1108
7a292a7a
SS
1109 if (!USE_GENERIC_DUMMY_FRAMES)
1110 {
1111 /* we want to copy 24 bytes of target's frame to dummy's frame,
c5aa993b
JM
1112 then set back chain to point to new frame. */
1113
1114 saved_sp = dummy_frame_addr[dummy_frame_count - 1];
7a292a7a
SS
1115 read_memory (saved_sp, tmp_buffer, 24);
1116 write_memory (sp, tmp_buffer, 24);
1117 }
c906108c
SS
1118
1119 /* set back chain properly */
1120 store_address (tmp_buffer, 4, saved_sp);
1121 write_memory (sp, tmp_buffer, 4);
1122
1123 target_store_registers (-1);
1124 return sp;
1125}
f6077098 1126/* #ifdef ELF_OBJECT_FORMAT */
c906108c
SS
1127
1128/* Function: ppc_push_return_address (pc, sp)
1129 Set up the return address for the inferior function call. */
1130
c5aa993b 1131CORE_ADDR
c906108c
SS
1132ppc_push_return_address (pc, sp)
1133 CORE_ADDR pc;
1134 CORE_ADDR sp;
1135{
1136 write_register (LR_REGNUM, CALL_DUMMY_ADDRESS ());
1137 return sp;
1138}
1139
f6077098 1140/* #endif */
c906108c
SS
1141
1142/* a given return value in `regbuf' with a type `valtype', extract and copy its
1143 value into `valbuf' */
1144
1145void
1146extract_return_value (valtype, regbuf, valbuf)
1147 struct type *valtype;
1148 char regbuf[REGISTER_BYTES];
1149 char *valbuf;
1150{
1151 int offset = 0;
1152
c5aa993b
JM
1153 if (TYPE_CODE (valtype) == TYPE_CODE_FLT)
1154 {
c906108c 1155
c5aa993b
JM
1156 double dd;
1157 float ff;
1158 /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes.
1159 We need to truncate the return value into float size (4 byte) if
1160 necessary. */
c906108c 1161
c5aa993b
JM
1162 if (TYPE_LENGTH (valtype) > 4) /* this is a double */
1163 memcpy (valbuf,
1164 &regbuf[REGISTER_BYTE (FP0_REGNUM + 1)],
1165 TYPE_LENGTH (valtype));
1166 else
1167 { /* float */
1168 memcpy (&dd, &regbuf[REGISTER_BYTE (FP0_REGNUM + 1)], 8);
1169 ff = (float) dd;
1170 memcpy (valbuf, &ff, sizeof (float));
1171 }
1172 }
1173 else
1174 {
1175 /* return value is copied starting from r3. */
1176 if (TARGET_BYTE_ORDER == BIG_ENDIAN
1177 && TYPE_LENGTH (valtype) < REGISTER_RAW_SIZE (3))
1178 offset = REGISTER_RAW_SIZE (3) - TYPE_LENGTH (valtype);
1179
1180 memcpy (valbuf,
1181 regbuf + REGISTER_BYTE (3) + offset,
c906108c 1182 TYPE_LENGTH (valtype));
c906108c 1183 }
c906108c
SS
1184}
1185
1186
1187/* keep structure return address in this variable.
1188 FIXME: This is a horrid kludge which should not be allowed to continue
1189 living. This only allows a single nested call to a structure-returning
1190 function. Come on, guys! -- gnu@cygnus.com, Aug 92 */
1191
1192CORE_ADDR rs6000_struct_return_address;
1193
1194
1195/* Indirect function calls use a piece of trampoline code to do context
1196 switching, i.e. to set the new TOC table. Skip such code if we are on
1197 its first instruction (as when we have single-stepped to here).
1198 Also skip shared library trampoline code (which is different from
1199 indirect function call trampolines).
1200 Result is desired PC to step until, or NULL if we are not in
1201 trampoline code. */
1202
1203CORE_ADDR
1204skip_trampoline_code (pc)
1205 CORE_ADDR pc;
1206{
1207 register unsigned int ii, op;
1208 CORE_ADDR solib_target_pc;
1209
c5aa993b
JM
1210 static unsigned trampoline_code[] =
1211 {
1212 0x800b0000, /* l r0,0x0(r11) */
1213 0x90410014, /* st r2,0x14(r1) */
1214 0x7c0903a6, /* mtctr r0 */
1215 0x804b0004, /* l r2,0x4(r11) */
1216 0x816b0008, /* l r11,0x8(r11) */
1217 0x4e800420, /* bctr */
1218 0x4e800020, /* br */
1219 0
c906108c
SS
1220 };
1221
1222 /* If pc is in a shared library trampoline, return its target. */
1223 solib_target_pc = find_solib_trampoline_target (pc);
1224 if (solib_target_pc)
1225 return solib_target_pc;
1226
c5aa993b
JM
1227 for (ii = 0; trampoline_code[ii]; ++ii)
1228 {
1229 op = read_memory_integer (pc + (ii * 4), 4);
1230 if (op != trampoline_code[ii])
1231 return 0;
1232 }
1233 ii = read_register (11); /* r11 holds destination addr */
1234 pc = read_memory_integer (ii, 4); /* (r11) value */
c906108c
SS
1235 return pc;
1236}
1237
1238/* Determines whether the function FI has a frame on the stack or not. */
1239
1240int
c877c8e6 1241rs6000_frameless_function_invocation (struct frame_info *fi)
c906108c
SS
1242{
1243 CORE_ADDR func_start;
1244 struct rs6000_framedata fdata;
1245
1246 /* Don't even think about framelessness except on the innermost frame
1247 or if the function was interrupted by a signal. */
1248 if (fi->next != NULL && !fi->next->signal_handler_caller)
1249 return 0;
c5aa993b 1250
c906108c
SS
1251 func_start = get_pc_function_start (fi->pc);
1252
1253 /* If we failed to find the start of the function, it is a mistake
1254 to inspect the instructions. */
1255
1256 if (!func_start)
1257 {
1258 /* A frame with a zero PC is usually created by dereferencing a NULL
c5aa993b
JM
1259 function pointer, normally causing an immediate core dump of the
1260 inferior. Mark function as frameless, as the inferior has no chance
1261 of setting up a stack frame. */
c906108c
SS
1262 if (fi->pc == 0)
1263 return 1;
1264 else
1265 return 0;
1266 }
1267
1268 (void) skip_prologue (func_start, &fdata);
1269 return fdata.frameless;
1270}
1271
1272/* Return the PC saved in a frame */
1273
1274unsigned long
c877c8e6 1275rs6000_frame_saved_pc (struct frame_info *fi)
c906108c
SS
1276{
1277 CORE_ADDR func_start;
1278 struct rs6000_framedata fdata;
1279
1280 if (fi->signal_handler_caller)
1281 return read_memory_integer (fi->frame + SIG_FRAME_PC_OFFSET, 4);
1282
7a292a7a
SS
1283 if (USE_GENERIC_DUMMY_FRAMES)
1284 {
1285 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
c5aa993b 1286 return generic_read_register_dummy (fi->pc, fi->frame, PC_REGNUM);
7a292a7a 1287 }
c906108c
SS
1288
1289 func_start = get_pc_function_start (fi->pc);
1290
1291 /* If we failed to find the start of the function, it is a mistake
1292 to inspect the instructions. */
1293 if (!func_start)
1294 return 0;
1295
1296 (void) skip_prologue (func_start, &fdata);
1297
1298 if (fdata.lr_offset == 0 && fi->next != NULL)
1299 {
1300 if (fi->next->signal_handler_caller)
1301 return read_memory_integer (fi->next->frame + SIG_FRAME_LR_OFFSET, 4);
1302 else
c877c8e6 1303 return read_memory_integer (FRAME_CHAIN (fi) + DEFAULT_LR_SAVE, 4);
c906108c
SS
1304 }
1305
1306 if (fdata.lr_offset == 0)
1307 return read_register (LR_REGNUM);
1308
c877c8e6 1309 return read_memory_integer (FRAME_CHAIN (fi) + fdata.lr_offset, 4);
c906108c
SS
1310}
1311
1312/* If saved registers of frame FI are not known yet, read and cache them.
1313 &FDATAP contains rs6000_framedata; TDATAP can be NULL,
1314 in which case the framedata are read. */
1315
1316static void
1317frame_get_saved_regs (fi, fdatap)
1318 struct frame_info *fi;
1319 struct rs6000_framedata *fdatap;
1320{
c5aa993b 1321 CORE_ADDR frame_addr;
c906108c
SS
1322 struct rs6000_framedata work_fdata;
1323
1324 if (fi->saved_regs)
1325 return;
c5aa993b 1326
c906108c
SS
1327 if (fdatap == NULL)
1328 {
1329 fdatap = &work_fdata;
1330 (void) skip_prologue (get_pc_function_start (fi->pc), fdatap);
1331 }
1332
1333 frame_saved_regs_zalloc (fi);
1334
1335 /* If there were any saved registers, figure out parent's stack
1336 pointer. */
1337 /* The following is true only if the frame doesn't have a call to
1338 alloca(), FIXME. */
1339
1340 if (fdatap->saved_fpr == 0 && fdatap->saved_gpr == 0
1341 && fdatap->lr_offset == 0 && fdatap->cr_offset == 0)
1342 frame_addr = 0;
1343 else if (fi->prev && fi->prev->frame)
1344 frame_addr = fi->prev->frame;
1345 else
1346 frame_addr = read_memory_integer (fi->frame, 4);
c5aa993b 1347
c906108c
SS
1348 /* if != -1, fdatap->saved_fpr is the smallest number of saved_fpr.
1349 All fpr's from saved_fpr to fp31 are saved. */
1350
1351 if (fdatap->saved_fpr >= 0)
1352 {
1353 int i;
1354 int fpr_offset = frame_addr + fdatap->fpr_offset;
1355 for (i = fdatap->saved_fpr; i < 32; i++)
1356 {
c5aa993b 1357 fi->saved_regs[FP0_REGNUM + i] = fpr_offset;
c906108c
SS
1358 fpr_offset += 8;
1359 }
1360 }
1361
1362 /* if != -1, fdatap->saved_gpr is the smallest number of saved_gpr.
1363 All gpr's from saved_gpr to gpr31 are saved. */
1364
1365 if (fdatap->saved_gpr >= 0)
1366 {
1367 int i;
1368 int gpr_offset = frame_addr + fdatap->gpr_offset;
1369 for (i = fdatap->saved_gpr; i < 32; i++)
1370 {
c5aa993b 1371 fi->saved_regs[i] = gpr_offset;
c906108c
SS
1372 gpr_offset += 4;
1373 }
1374 }
1375
1376 /* If != 0, fdatap->cr_offset is the offset from the frame that holds
1377 the CR. */
1378 if (fdatap->cr_offset != 0)
c5aa993b 1379 fi->saved_regs[CR_REGNUM] = frame_addr + fdatap->cr_offset;
c906108c
SS
1380
1381 /* If != 0, fdatap->lr_offset is the offset from the frame that holds
1382 the LR. */
1383 if (fdatap->lr_offset != 0)
c5aa993b 1384 fi->saved_regs[LR_REGNUM] = frame_addr + fdatap->lr_offset;
c906108c
SS
1385}
1386
1387/* Return the address of a frame. This is the inital %sp value when the frame
1388 was first allocated. For functions calling alloca(), it might be saved in
1389 an alloca register. */
1390
1391static CORE_ADDR
1392frame_initial_stack_address (fi)
1393 struct frame_info *fi;
1394{
1395 CORE_ADDR tmpaddr;
1396 struct rs6000_framedata fdata;
1397 struct frame_info *callee_fi;
1398
1399 /* if the initial stack pointer (frame address) of this frame is known,
1400 just return it. */
1401
1402 if (fi->extra_info->initial_sp)
1403 return fi->extra_info->initial_sp;
1404
1405 /* find out if this function is using an alloca register.. */
1406
1407 (void) skip_prologue (get_pc_function_start (fi->pc), &fdata);
1408
1409 /* if saved registers of this frame are not known yet, read and cache them. */
1410
1411 if (!fi->saved_regs)
1412 frame_get_saved_regs (fi, &fdata);
1413
1414 /* If no alloca register used, then fi->frame is the value of the %sp for
1415 this frame, and it is good enough. */
1416
1417 if (fdata.alloca_reg < 0)
1418 {
1419 fi->extra_info->initial_sp = fi->frame;
1420 return fi->extra_info->initial_sp;
1421 }
1422
1423 /* This function has an alloca register. If this is the top-most frame
1424 (with the lowest address), the value in alloca register is good. */
1425
1426 if (!fi->next)
c5aa993b 1427 return fi->extra_info->initial_sp = read_register (fdata.alloca_reg);
c906108c
SS
1428
1429 /* Otherwise, this is a caller frame. Callee has usually already saved
1430 registers, but there are exceptions (such as when the callee
1431 has no parameters). Find the address in which caller's alloca
1432 register is saved. */
1433
c5aa993b
JM
1434 for (callee_fi = fi->next; callee_fi; callee_fi = callee_fi->next)
1435 {
c906108c 1436
c5aa993b
JM
1437 if (!callee_fi->saved_regs)
1438 frame_get_saved_regs (callee_fi, NULL);
c906108c 1439
c5aa993b 1440 /* this is the address in which alloca register is saved. */
c906108c 1441
c5aa993b
JM
1442 tmpaddr = callee_fi->saved_regs[fdata.alloca_reg];
1443 if (tmpaddr)
1444 {
1445 fi->extra_info->initial_sp = read_memory_integer (tmpaddr, 4);
1446 return fi->extra_info->initial_sp;
1447 }
c906108c 1448
c5aa993b
JM
1449 /* Go look into deeper levels of the frame chain to see if any one of
1450 the callees has saved alloca register. */
1451 }
c906108c
SS
1452
1453 /* If alloca register was not saved, by the callee (or any of its callees)
1454 then the value in the register is still good. */
1455
1456 fi->extra_info->initial_sp = read_register (fdata.alloca_reg);
1457 return fi->extra_info->initial_sp;
1458}
1459
1460CORE_ADDR
1461rs6000_frame_chain (thisframe)
1462 struct frame_info *thisframe;
1463{
1464 CORE_ADDR fp;
1465
7a292a7a
SS
1466 if (USE_GENERIC_DUMMY_FRAMES)
1467 {
1468 if (PC_IN_CALL_DUMMY (thisframe->pc, thisframe->frame, thisframe->frame))
1469 return thisframe->frame; /* dummy frame same as caller's frame */
1470 }
c906108c 1471
c5aa993b 1472 if (inside_entry_file (thisframe->pc) ||
c906108c
SS
1473 thisframe->pc == entry_point_address ())
1474 return 0;
1475
1476 if (thisframe->signal_handler_caller)
1477 fp = read_memory_integer (thisframe->frame + SIG_FRAME_FP_OFFSET, 4);
1478 else if (thisframe->next != NULL
1479 && thisframe->next->signal_handler_caller
c877c8e6 1480 && FRAMELESS_FUNCTION_INVOCATION (thisframe))
c906108c
SS
1481 /* A frameless function interrupted by a signal did not change the
1482 frame pointer. */
1483 fp = FRAME_FP (thisframe);
1484 else
1485 fp = read_memory_integer ((thisframe)->frame, 4);
1486
7a292a7a
SS
1487 if (USE_GENERIC_DUMMY_FRAMES)
1488 {
1489 CORE_ADDR fpp, lr;
1490
1491 lr = read_register (LR_REGNUM);
1492 if (lr == entry_point_address ())
1493 if (fp != 0 && (fpp = read_memory_integer (fp, 4)) != 0)
1494 if (PC_IN_CALL_DUMMY (lr, fpp, fpp))
1495 return fpp;
1496 }
c906108c 1497
c906108c
SS
1498 return fp;
1499}
1500\f
1501/* Return nonzero if ADDR (a function pointer) is in the data space and
1502 is therefore a special function pointer. */
1503
1504int
1505is_magic_function_pointer (addr)
1506 CORE_ADDR addr;
1507{
1508 struct obj_section *s;
1509
1510 s = find_pc_section (addr);
1511 if (s && s->the_bfd_section->flags & SEC_CODE)
1512 return 0;
1513 else
1514 return 1;
1515}
1516
1517#ifdef GDB_TARGET_POWERPC
1518int
1519gdb_print_insn_powerpc (memaddr, info)
1520 bfd_vma memaddr;
1521 disassemble_info *info;
1522{
1523 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
1524 return print_insn_big_powerpc (memaddr, info);
1525 else
1526 return print_insn_little_powerpc (memaddr, info);
1527}
1528#endif
c906108c 1529\f
c5aa993b 1530
c906108c
SS
1531/* Handling the various PowerPC/RS6000 variants. */
1532
1533
1534/* The arrays here called register_names_MUMBLE hold names that
1535 the rs6000_register_name function returns.
1536
1537 For each family of PPC variants, I've tried to isolate out the
1538 common registers and put them up front, so that as long as you get
1539 the general family right, GDB will correctly identify the registers
1540 common to that family. The common register sets are:
1541
1542 For the 60x family: hid0 hid1 iabr dabr pir
1543
1544 For the 505 and 860 family: eie eid nri
1545
1546 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
c5aa993b
JM
1547 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
1548 pbu1 pbl2 pbu2
c906108c
SS
1549
1550 Most of these register groups aren't anything formal. I arrived at
1551 them by looking at the registers that occurred in more than one
1552 processor. */
1553
1554/* UISA register names common across all architectures, including POWER. */
1555
1556#define COMMON_UISA_REG_NAMES \
1557 /* 0 */ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1558 /* 8 */ "r8", "r9", "r10","r11","r12","r13","r14","r15", \
1559 /* 16 */ "r16","r17","r18","r19","r20","r21","r22","r23", \
1560 /* 24 */ "r24","r25","r26","r27","r28","r29","r30","r31", \
1561 /* 32 */ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1562 /* 40 */ "f8", "f9", "f10","f11","f12","f13","f14","f15", \
1563 /* 48 */ "f16","f17","f18","f19","f20","f21","f22","f23", \
1564 /* 56 */ "f24","f25","f26","f27","f28","f29","f30","f31", \
1565 /* 64 */ "pc", "ps"
1566
1567/* UISA-level SPR names for PowerPC. */
1568#define PPC_UISA_SPR_NAMES \
1569 /* 66 */ "cr", "lr", "ctr", "xer", ""
1570
1571/* Segment register names, for PowerPC. */
1572#define PPC_SEGMENT_REG_NAMES \
1573 /* 71 */ "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7", \
1574 /* 79 */ "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
1575
1576/* OEA SPR names for 32-bit PowerPC implementations.
1577 The blank space is for "asr", which is only present on 64-bit
1578 implementations. */
1579#define PPC_32_OEA_SPR_NAMES \
1580 /* 87 */ "pvr", \
1581 /* 88 */ "ibat0u", "ibat0l", "ibat1u", "ibat1l", \
1582 /* 92 */ "ibat2u", "ibat2l", "ibat3u", "ibat3l", \
1583 /* 96 */ "dbat0u", "dbat0l", "dbat1u", "dbat1l", \
1584 /* 100 */ "dbat2u", "dbat2l", "dbat3u", "dbat3l", \
1585 /* 104 */ "sdr1", "", "dar", "dsisr", "sprg0", "sprg1", "sprg2", "sprg3",\
1586 /* 112 */ "srr0", "srr1", "tbl", "tbu", "dec", "dabr", "ear"
1587
1588/* For the RS6000, we only cover user-level SPR's. */
1589char *register_names_rs6000[] =
1590{
1591 COMMON_UISA_REG_NAMES,
1592 /* 66 */ "cnd", "lr", "cnt", "xer", "mq"
1593};
1594
1595/* a UISA-only view of the PowerPC. */
1596char *register_names_uisa[] =
1597{
1598 COMMON_UISA_REG_NAMES,
1599 PPC_UISA_SPR_NAMES
1600};
1601
1602char *register_names_403[] =
c5aa993b 1603{
c906108c
SS
1604 COMMON_UISA_REG_NAMES,
1605 PPC_UISA_SPR_NAMES,
1606 PPC_SEGMENT_REG_NAMES,
1607 PPC_32_OEA_SPR_NAMES,
c5aa993b
JM
1608 /* 119 */ "icdbdr", "esr", "dear", "evpr", "cdbcr", "tsr", "tcr", "pit",
1609 /* 127 */ "tbhi", "tblo", "srr2", "srr3", "dbsr", "dbcr", "iac1", "iac2",
c906108c
SS
1610 /* 135 */ "dac1", "dac2", "dccr", "iccr", "pbl1", "pbu1", "pbl2", "pbu2"
1611};
1612
1613char *register_names_403GC[] =
c5aa993b 1614{
c906108c
SS
1615 COMMON_UISA_REG_NAMES,
1616 PPC_UISA_SPR_NAMES,
1617 PPC_SEGMENT_REG_NAMES,
1618 PPC_32_OEA_SPR_NAMES,
c5aa993b
JM
1619 /* 119 */ "icdbdr", "esr", "dear", "evpr", "cdbcr", "tsr", "tcr", "pit",
1620 /* 127 */ "tbhi", "tblo", "srr2", "srr3", "dbsr", "dbcr", "iac1", "iac2",
1621 /* 135 */ "dac1", "dac2", "dccr", "iccr", "pbl1", "pbu1", "pbl2", "pbu2",
c906108c
SS
1622 /* 143 */ "zpr", "pid", "sgr", "dcwr", "tbhu", "tblu"
1623};
1624
1625char *register_names_505[] =
c5aa993b 1626{
c906108c
SS
1627 COMMON_UISA_REG_NAMES,
1628 PPC_UISA_SPR_NAMES,
1629 PPC_SEGMENT_REG_NAMES,
1630 PPC_32_OEA_SPR_NAMES,
1631 /* 119 */ "eie", "eid", "nri"
1632};
1633
1634char *register_names_860[] =
c5aa993b 1635{
c906108c
SS
1636 COMMON_UISA_REG_NAMES,
1637 PPC_UISA_SPR_NAMES,
1638 PPC_SEGMENT_REG_NAMES,
1639 PPC_32_OEA_SPR_NAMES,
c5aa993b
JM
1640 /* 119 */ "eie", "eid", "nri", "cmpa", "cmpb", "cmpc", "cmpd", "icr",
1641 /* 127 */ "der", "counta", "countb", "cmpe", "cmpf", "cmpg", "cmph",
1642 /* 134 */ "lctrl1", "lctrl2", "ictrl", "bar", "ic_cst", "ic_adr", "ic_dat",
1643 /* 141 */ "dc_cst", "dc_adr", "dc_dat", "dpdr", "dpir", "immr", "mi_ctr",
1644 /* 148 */ "mi_ap", "mi_epn", "mi_twc", "mi_rpn", "md_ctr", "m_casid",
1645 /* 154 */ "md_ap", "md_epn", "md_twb", "md_twc", "md_rpn", "m_tw",
1646 /* 160 */ "mi_dbcam", "mi_dbram0", "mi_dbram1", "md_dbcam", "md_dbram0",
c906108c
SS
1647 /* 165 */ "md_dbram1"
1648};
1649
1650/* Note that the 601 has different register numbers for reading and
1651 writing RTCU and RTCL. However, how one reads and writes a
1652 register is the stub's problem. */
1653char *register_names_601[] =
c5aa993b 1654{
c906108c
SS
1655 COMMON_UISA_REG_NAMES,
1656 PPC_UISA_SPR_NAMES,
1657 PPC_SEGMENT_REG_NAMES,
1658 PPC_32_OEA_SPR_NAMES,
c5aa993b 1659 /* 119 */ "hid0", "hid1", "iabr", "dabr", "pir", "mq", "rtcu",
c906108c
SS
1660 /* 126 */ "rtcl"
1661};
1662
1663char *register_names_602[] =
c5aa993b 1664{
c906108c
SS
1665 COMMON_UISA_REG_NAMES,
1666 PPC_UISA_SPR_NAMES,
1667 PPC_SEGMENT_REG_NAMES,
1668 PPC_32_OEA_SPR_NAMES,
c5aa993b 1669 /* 119 */ "hid0", "hid1", "iabr", "", "", "tcr", "ibr", "esassr", "sebr",
c906108c
SS
1670 /* 128 */ "ser", "sp", "lt"
1671};
1672
1673char *register_names_603[] =
c5aa993b 1674{
c906108c
SS
1675 COMMON_UISA_REG_NAMES,
1676 PPC_UISA_SPR_NAMES,
1677 PPC_SEGMENT_REG_NAMES,
1678 PPC_32_OEA_SPR_NAMES,
c5aa993b 1679 /* 119 */ "hid0", "hid1", "iabr", "", "", "dmiss", "dcmp", "hash1",
c906108c
SS
1680 /* 127 */ "hash2", "imiss", "icmp", "rpa"
1681};
1682
1683char *register_names_604[] =
c5aa993b 1684{
c906108c
SS
1685 COMMON_UISA_REG_NAMES,
1686 PPC_UISA_SPR_NAMES,
1687 PPC_SEGMENT_REG_NAMES,
1688 PPC_32_OEA_SPR_NAMES,
c5aa993b 1689 /* 119 */ "hid0", "hid1", "iabr", "dabr", "pir", "mmcr0", "pmc1", "pmc2",
c906108c
SS
1690 /* 127 */ "sia", "sda"
1691};
1692
1693char *register_names_750[] =
c5aa993b 1694{
c906108c
SS
1695 COMMON_UISA_REG_NAMES,
1696 PPC_UISA_SPR_NAMES,
1697 PPC_SEGMENT_REG_NAMES,
1698 PPC_32_OEA_SPR_NAMES,
c5aa993b
JM
1699 /* 119 */ "hid0", "hid1", "iabr", "dabr", "", "ummcr0", "upmc1", "upmc2",
1700 /* 127 */ "usia", "ummcr1", "upmc3", "upmc4", "mmcr0", "pmc1", "pmc2",
1701 /* 134 */ "sia", "mmcr1", "pmc3", "pmc4", "l2cr", "ictc", "thrm1", "thrm2",
c906108c
SS
1702 /* 142 */ "thrm3"
1703};
1704
1705
1706/* Information about a particular processor variant. */
1707struct variant
c5aa993b
JM
1708 {
1709 /* Name of this variant. */
1710 char *name;
c906108c 1711
c5aa993b
JM
1712 /* English description of the variant. */
1713 char *description;
c906108c 1714
c5aa993b
JM
1715 /* Table of register names; registers[R] is the name of the register
1716 number R. */
1717 int num_registers;
1718 char **registers;
1719 };
c906108c
SS
1720
1721#define num_registers(list) (sizeof (list) / sizeof((list)[0]))
1722
1723
1724/* Information in this table comes from the following web sites:
1725 IBM: http://www.chips.ibm.com:80/products/embedded/
1726 Motorola: http://www.mot.com/SPS/PowerPC/
1727
1728 I'm sure I've got some of the variant descriptions not quite right.
1729 Please report any inaccuracies you find to GDB's maintainer.
1730
1731 If you add entries to this table, please be sure to allow the new
1732 value as an argument to the --with-cpu flag, in configure.in. */
1733
1734static struct variant
c5aa993b 1735 variants[] =
c906108c 1736{
c5aa993b
JM
1737 {"ppc-uisa", "PowerPC UISA - a PPC processor as viewed by user-level code",
1738 num_registers (register_names_uisa), register_names_uisa},
1739 {"rs6000", "IBM RS6000 (\"POWER\") architecture, user-level view",
1740 num_registers (register_names_rs6000), register_names_rs6000},
1741 {"403", "IBM PowerPC 403",
1742 num_registers (register_names_403), register_names_403},
1743 {"403GC", "IBM PowerPC 403GC",
1744 num_registers (register_names_403GC), register_names_403GC},
1745 {"505", "Motorola PowerPC 505",
1746 num_registers (register_names_505), register_names_505},
1747 {"860", "Motorola PowerPC 860 or 850",
1748 num_registers (register_names_860), register_names_860},
1749 {"601", "Motorola PowerPC 601",
1750 num_registers (register_names_601), register_names_601},
1751 {"602", "Motorola PowerPC 602",
1752 num_registers (register_names_602), register_names_602},
1753 {"603", "Motorola/IBM PowerPC 603 or 603e",
1754 num_registers (register_names_603), register_names_603},
1755 {"604", "Motorola PowerPC 604 or 604e",
1756 num_registers (register_names_604), register_names_604},
1757 {"750", "Motorola/IBM PowerPC 750 or 740",
1758 num_registers (register_names_750), register_names_750},
1759 {0, 0, 0, 0}
c906108c
SS
1760};
1761
1762
1763static struct variant *current_variant;
1764
1765char *
1766rs6000_register_name (int i)
1767{
1768 if (i < 0 || i >= NUM_REGS)
1769 error ("GDB bug: rs6000-tdep.c (rs6000_register_name): strange register number");
1770
1771 return ((i < current_variant->num_registers)
1772 ? current_variant->registers[i]
1773 : "");
1774}
1775
1776
1777static void
1778install_variant (struct variant *v)
1779{
1780 current_variant = v;
1781}
1782
1783
1784/* Look up the variant named NAME in the `variants' table. Return a
1785 pointer to the struct variant, or null if we couldn't find it. */
1786static struct variant *
1787find_variant_by_name (char *name)
1788{
1789 int i;
c5aa993b 1790
c906108c 1791 for (i = 0; variants[i].name; i++)
c5aa993b 1792 if (!strcmp (name, variants[i].name))
c906108c
SS
1793 return &variants[i];
1794
1795 return 0;
1796}
1797
1798
1799/* Install the PPC/RS6000 variant named NAME in the `variants' table.
1800 Return zero if we installed it successfully, or a non-zero value if
1801 we couldn't do it.
1802
1803 This might be useful to code outside this file, which doesn't want
1804 to depend on the exact indices of the entries in the `variants'
1805 table. Just make it non-static if you want that. */
1806static int
1807install_variant_by_name (char *name)
1808{
1809 struct variant *v = find_variant_by_name (name);
1810
1811 if (v)
1812 {
1813 install_variant (v);
1814 return 0;
1815 }
1816 else
1817 return 1;
1818}
1819
1820
1821static void
1822list_variants ()
1823{
1824 int i;
1825
1826 printf_filtered ("GDB knows about the following PowerPC and RS6000 variants:\n");
1827
1828 for (i = 0; variants[i].name; i++)
1829 printf_filtered (" %-8s %s\n",
1830 variants[i].name, variants[i].description);
1831}
1832
1833
1834static void
1835show_current_variant ()
1836{
1837 printf_filtered ("PowerPC / RS6000 processor variant is set to `%s'.\n",
1838 current_variant->name);
1839}
1840
1841
1842static void
1843set_processor (char *arg, int from_tty)
1844{
c5aa993b 1845 if (!arg || arg[0] == '\0')
c906108c
SS
1846 {
1847 list_variants ();
1848 return;
1849 }
1850
1851 if (install_variant_by_name (arg))
1852 {
1853 error_begin ();
1854 fprintf_filtered (gdb_stderr,
c5aa993b 1855 "`%s' is not a recognized PowerPC / RS6000 variant name.\n\n", arg);
c906108c
SS
1856 list_variants ();
1857 return_to_top_level (RETURN_ERROR);
1858 }
1859
1860 show_current_variant ();
1861}
1862
1863static void
1864show_processor (char *arg, int from_tty)
1865{
1866 show_current_variant ();
1867}
1868
1869
2acceee2
JM
1870\f
1871
c906108c
SS
1872/* Initialization code. */
1873
1874void
1875_initialize_rs6000_tdep ()
1876{
1877 /* FIXME, this should not be decided via ifdef. */
1878#ifdef GDB_TARGET_POWERPC
1879 tm_print_insn = gdb_print_insn_powerpc;
1880#else
1881 tm_print_insn = print_insn_rs6000;
1882#endif
1883
1884 /* I don't think we should use the set/show command arrangement
1885 here, because the way that's implemented makes it hard to do the
1886 error checking we want in a reasonable way. So we just add them
1887 as two separate commands. */
1888 add_cmd ("processor", class_support, set_processor,
1889 "`set processor NAME' sets the PowerPC/RS6000 variant to NAME.\n\
1890If you set this, GDB will know about the special-purpose registers that are\n\
1891available on the given variant.\n\
1892Type `set processor' alone for a list of recognized variant names.",
1893 &setlist);
1894 add_cmd ("processor", class_support, show_processor,
1895 "Show the variant of the PowerPC or RS6000 processor in use.\n\
1896Use `set processor' to change this.",
1897 &showlist);
1898
1899 /* Set the current PPC processor variant. */
1900 {
1901 int status = 1;
1902
1903#ifdef TARGET_CPU_DEFAULT
1904 status = install_variant_by_name (TARGET_CPU_DEFAULT);
1905#endif
1906
1907 if (status)
1908 {
1909#ifdef GDB_TARGET_POWERPC
1910 install_variant_by_name ("ppc-uisa");
1911#else
1912 install_variant_by_name ("rs6000");
1913#endif
1914 }
1915 }
1916}
This page took 0.129247 seconds and 4 git commands to generate.