projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
2012-02-02 Pedro Alves <palves@redhat.com>
[deliverable/binutils-gdb.git] / gdb / rs6000-tdep.c
CommitLineData
c906108c 1/* Target-dependent code for GDB, the GNU debugger.
7aea86e6 2
0b302171
JB		 3 Copyright (C) 1986-1987, 1989, 1991-2012 Free Software Foundation,
4 Inc.
c906108c 5
c5aa993b 6 This file is part of GDB.
c906108c 7
c5aa993b
JM		 8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
a9762ec7 10 the Free Software Foundation; either version 3 of the License, or
c5aa993b 11 (at your option) any later version.
c906108c 12
c5aa993b
JM		 13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
c906108c 17
c5aa993b 18 You should have received a copy of the GNU General Public License
a9762ec7 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c
SS		 20
21#include "defs.h"
22#include "frame.h"
23#include "inferior.h"
24#include "symtab.h"
25#include "target.h"
26#include "gdbcore.h"
27#include "gdbcmd.h"
c906108c 28#include "objfiles.h"
7a78ae4e 29#include "arch-utils.h"
4e052eda 30#include "regcache.h"
d195bc9f 31#include "regset.h"
d16aafd8 32#include "doublest.h"
fd0407d6 33#include "value.h"
1fcc0bb8 34#include "parser-defs.h"
4be87837 35#include "osabi.h"
7d9b040b 36#include "infcall.h"
9f643768
JB		 37#include "sim-regno.h"
38#include "gdb/sim-ppc.h"
6ced10dd 39#include "reggroups.h"
4fc771b8 40#include "dwarf2-frame.h"
7cc46491
DJ		 41#include "target-descriptions.h"
42#include "user-regs.h"
7a78ae4e 43
2fccf04a 44#include "libbfd.h" /* for bfd_default_set_arch_mach */
7a78ae4e 45#include "coff/internal.h" /* for libcoff.h */
2fccf04a 46#include "libcoff.h" /* for xcoff_data */
11ed25ac
KB		 47#include "coff/xcoff.h"
48#include "libxcoff.h"
7a78ae4e 49
9aa1e687 50#include "elf-bfd.h"
55eddb0f 51#include "elf/ppc.h"
7a78ae4e 52
6ded7999 53#include "solib-svr4.h"
9aa1e687 54#include "ppc-tdep.h"
7a78ae4e 55
338ef23d 56#include "gdb_assert.h"
a89aa300 57#include "dis-asm.h"
338ef23d 58
61a65099
KB		 59#include "trad-frame.h"
60#include "frame-unwind.h"
61#include "frame-base.h"
62
7cc46491 63#include "features/rs6000/powerpc-32.c"
7284e1be 64#include "features/rs6000/powerpc-altivec32.c"
604c2f83 65#include "features/rs6000/powerpc-vsx32.c"
7cc46491
DJ		 66#include "features/rs6000/powerpc-403.c"
67#include "features/rs6000/powerpc-403gc.c"
4d09ffea 68#include "features/rs6000/powerpc-405.c"
7cc46491
DJ		 69#include "features/rs6000/powerpc-505.c"
70#include "features/rs6000/powerpc-601.c"
71#include "features/rs6000/powerpc-602.c"
72#include "features/rs6000/powerpc-603.c"
73#include "features/rs6000/powerpc-604.c"
74#include "features/rs6000/powerpc-64.c"
7284e1be 75#include "features/rs6000/powerpc-altivec64.c"
604c2f83 76#include "features/rs6000/powerpc-vsx64.c"
7cc46491
DJ		 77#include "features/rs6000/powerpc-7400.c"
78#include "features/rs6000/powerpc-750.c"
79#include "features/rs6000/powerpc-860.c"
80#include "features/rs6000/powerpc-e500.c"
81#include "features/rs6000/rs6000.c"
82
5a9e69ba
TJB		 83/* Determine if regnum is an SPE pseudo-register. */
84#define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
85 && (regnum) >= (tdep)->ppc_ev0_regnum \
86 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
87
f949c649
TJB		 88/* Determine if regnum is a decimal float pseudo-register. */
89#define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
90 && (regnum) >= (tdep)->ppc_dl0_regnum \
91 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
92
604c2f83
LM		 93/* Determine if regnum is a POWER7 VSX register. */
94#define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
95 && (regnum) >= (tdep)->ppc_vsr0_regnum \
96 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
97
98/* Determine if regnum is a POWER7 Extended FP register. */
99#define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
100 && (regnum) >= (tdep)->ppc_efpr0_regnum \
d9492458 101 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
604c2f83 102
55eddb0f
DJ		 103/* The list of available "set powerpc ..." and "show powerpc ..."
104 commands. */
105static struct cmd_list_element *setpowerpccmdlist = NULL;
106static struct cmd_list_element *showpowerpccmdlist = NULL;
107
108static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO;
109
110/* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
40478521 111static const char *const powerpc_vector_strings[] =
55eddb0f
DJ		 112{
113 "auto",
114 "generic",
115 "altivec",
116 "spe",
117 NULL
118};
119
120/* A variable that can be configured by the user. */
121static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO;
122static const char *powerpc_vector_abi_string = "auto";
123
0df8b418 124/* To be used by skip_prologue. */
7a78ae4e
ND		 125
126struct rs6000_framedata
127 {
128 int offset; /* total size of frame --- the distance
129 by which we decrement sp to allocate
130 the frame */
131 int saved_gpr; /* smallest # of saved gpr */
46a9b8ed 132 unsigned int gpr_mask; /* Each bit is an individual saved GPR. */
7a78ae4e 133 int saved_fpr; /* smallest # of saved fpr */
6be8bc0c 134 int saved_vr; /* smallest # of saved vr */
96ff0de4 135 int saved_ev; /* smallest # of saved ev */
7a78ae4e 136 int alloca_reg; /* alloca register number (frame ptr) */
0df8b418
MS		 137 char frameless; /* true if frameless functions. */
138 char nosavedpc; /* true if pc not saved. */
46a9b8ed 139 char used_bl; /* true if link register clobbered */
7a78ae4e
ND		 140 int gpr_offset; /* offset of saved gprs from prev sp */
141 int fpr_offset; /* offset of saved fprs from prev sp */
6be8bc0c 142 int vr_offset; /* offset of saved vrs from prev sp */
96ff0de4 143 int ev_offset; /* offset of saved evs from prev sp */
7a78ae4e 144 int lr_offset; /* offset of saved lr */
46a9b8ed 145 int lr_register; /* register of saved lr, if trustworthy */
7a78ae4e 146 int cr_offset; /* offset of saved cr */
6be8bc0c 147 int vrsave_offset; /* offset of saved vrsave register */
7a78ae4e
ND		 148 };
149
c906108c 150
604c2f83
LM		 151/* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
152int
153vsx_register_p (struct gdbarch *gdbarch, int regno)
154{
155 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
156 if (tdep->ppc_vsr0_regnum < 0)
157 return 0;
158 else
159 return (regno >= tdep->ppc_vsr0_upper_regnum && regno
160 <= tdep->ppc_vsr0_upper_regnum + 31);
161}
162
64b84175
KB		 163/* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
164int
be8626e0 165altivec_register_p (struct gdbarch *gdbarch, int regno)
64b84175 166{
be8626e0 167 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
64b84175
KB		 168 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
169 return 0;
170 else
171 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
172}
173
383f0f5b 174
867e2dc5
JB		 175/* Return true if REGNO is an SPE register, false otherwise. */
176int
be8626e0 177spe_register_p (struct gdbarch *gdbarch, int regno)
867e2dc5 178{
be8626e0 179 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
867e2dc5
JB		 180
181 /* Is it a reference to EV0 -- EV31, and do we have those? */
5a9e69ba 182 if (IS_SPE_PSEUDOREG (tdep, regno))
867e2dc5
JB		 183 return 1;
184
6ced10dd
JB		 185 /* Is it a reference to one of the raw upper GPR halves? */
186 if (tdep->ppc_ev0_upper_regnum >= 0
187 && tdep->ppc_ev0_upper_regnum <= regno
188 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
189 return 1;
190
867e2dc5
JB		 191 /* Is it a reference to the 64-bit accumulator, and do we have that? */
192 if (tdep->ppc_acc_regnum >= 0
193 && tdep->ppc_acc_regnum == regno)
194 return 1;
195
196 /* Is it a reference to the SPE floating-point status and control register,
197 and do we have that? */
198 if (tdep->ppc_spefscr_regnum >= 0
199 && tdep->ppc_spefscr_regnum == regno)
200 return 1;
201
202 return 0;
203}
204
205
383f0f5b
JB		 206/* Return non-zero if the architecture described by GDBARCH has
207 floating-point registers (f0 --- f31 and fpscr). */
0a613259
AC		 208int
209ppc_floating_point_unit_p (struct gdbarch *gdbarch)
210{
383f0f5b
JB		 211 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
212
213 return (tdep->ppc_fp0_regnum >= 0
214 && tdep->ppc_fpscr_regnum >= 0);
0a613259 215}
9f643768 216
604c2f83
LM		 217/* Return non-zero if the architecture described by GDBARCH has
218 VSX registers (vsr0 --- vsr63). */
63807e1d 219static int
604c2f83
LM		 220ppc_vsx_support_p (struct gdbarch *gdbarch)
221{
222 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
223
224 return tdep->ppc_vsr0_regnum >= 0;
225}
226
06caf7d2
CES		 227/* Return non-zero if the architecture described by GDBARCH has
228 Altivec registers (vr0 --- vr31, vrsave and vscr). */
229int
230ppc_altivec_support_p (struct gdbarch *gdbarch)
231{
232 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
233
234 return (tdep->ppc_vr0_regnum >= 0
235 && tdep->ppc_vrsave_regnum >= 0);
236}
09991fa0
JB		 237
238/* Check that TABLE[GDB_REGNO] is not already initialized, and then
239 set it to SIM_REGNO.
240
241 This is a helper function for init_sim_regno_table, constructing
242 the table mapping GDB register numbers to sim register numbers; we
243 initialize every element in that table to -1 before we start
244 filling it in. */
9f643768
JB		 245static void
246set_sim_regno (int *table, int gdb_regno, int sim_regno)
247{
248 /* Make sure we don't try to assign any given GDB register a sim
249 register number more than once. */
250 gdb_assert (table[gdb_regno] == -1);
251 table[gdb_regno] = sim_regno;
252}
253
09991fa0
JB		 254
255/* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
256 numbers to simulator register numbers, based on the values placed
257 in the ARCH->tdep->ppc_foo_regnum members. */
9f643768
JB		 258static void
259init_sim_regno_table (struct gdbarch *arch)
260{
261 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
7cc46491 262 int total_regs = gdbarch_num_regs (arch);
9f643768
JB		 263 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
264 int i;
7cc46491
DJ		 265 static const char *const segment_regs[] = {
266 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
267 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
268 };
9f643768
JB		 269
270 /* Presume that all registers not explicitly mentioned below are
271 unavailable from the sim. */
272 for (i = 0; i < total_regs; i++)
273 sim_regno[i] = -1;
274
275 /* General-purpose registers. */
276 for (i = 0; i < ppc_num_gprs; i++)
277 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
278
279 /* Floating-point registers. */
280 if (tdep->ppc_fp0_regnum >= 0)
281 for (i = 0; i < ppc_num_fprs; i++)
282 set_sim_regno (sim_regno,
283 tdep->ppc_fp0_regnum + i,
284 sim_ppc_f0_regnum + i);
285 if (tdep->ppc_fpscr_regnum >= 0)
286 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
287
288 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
289 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
290 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
291
292 /* Segment registers. */
7cc46491
DJ		 293 for (i = 0; i < ppc_num_srs; i++)
294 {
295 int gdb_regno;
296
297 gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1);
298 if (gdb_regno >= 0)
299 set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i);
300 }
9f643768
JB		 301
302 /* Altivec registers. */
303 if (tdep->ppc_vr0_regnum >= 0)
304 {
305 for (i = 0; i < ppc_num_vrs; i++)
306 set_sim_regno (sim_regno,
307 tdep->ppc_vr0_regnum + i,
308 sim_ppc_vr0_regnum + i);
309
310 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
311 we can treat this more like the other cases. */
312 set_sim_regno (sim_regno,
313 tdep->ppc_vr0_regnum + ppc_num_vrs,
314 sim_ppc_vscr_regnum);
315 }
316 /* vsave is a special-purpose register, so the code below handles it. */
317
318 /* SPE APU (E500) registers. */
6ced10dd
JB		 319 if (tdep->ppc_ev0_upper_regnum >= 0)
320 for (i = 0; i < ppc_num_gprs; i++)
321 set_sim_regno (sim_regno,
322 tdep->ppc_ev0_upper_regnum + i,
323 sim_ppc_rh0_regnum + i);
9f643768
JB		 324 if (tdep->ppc_acc_regnum >= 0)
325 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
326 /* spefscr is a special-purpose register, so the code below handles it. */
327
7cc46491 328#ifdef WITH_SIM
9f643768
JB		 329 /* Now handle all special-purpose registers. Verify that they
330 haven't mistakenly been assigned numbers by any of the above
7cc46491
DJ		 331 code. */
332 for (i = 0; i < sim_ppc_num_sprs; i++)
333 {
334 const char *spr_name = sim_spr_register_name (i);
335 int gdb_regno = -1;
336
337 if (spr_name != NULL)
338 gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1);
339
340 if (gdb_regno != -1)
341 set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i);
342 }
343#endif
9f643768
JB		 344
345 /* Drop the initialized array into place. */
346 tdep->sim_regno = sim_regno;
347}
348
09991fa0
JB		 349
350/* Given a GDB register number REG, return the corresponding SIM
351 register number. */
9f643768 352static int
e7faf938 353rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg)
9f643768 354{
e7faf938 355 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9f643768
JB		 356 int sim_regno;
357
7cc46491 358 if (tdep->sim_regno == NULL)
e7faf938 359 init_sim_regno_table (gdbarch);
7cc46491 360
f57d151a 361 gdb_assert (0 <= reg
e7faf938
MD		 362 && reg <= gdbarch_num_regs (gdbarch)
363 + gdbarch_num_pseudo_regs (gdbarch));
9f643768
JB		 364 sim_regno = tdep->sim_regno[reg];
365
366 if (sim_regno >= 0)
367 return sim_regno;
368 else
369 return LEGACY_SIM_REGNO_IGNORE;
370}
371
d195bc9f
MK		 372\f
373
374/* Register set support functions. */
375
f2db237a
AM		 376/* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
377 Write the register to REGCACHE. */
378
7284e1be 379void
d195bc9f 380ppc_supply_reg (struct regcache *regcache, int regnum,
f2db237a 381 const gdb_byte *regs, size_t offset, int regsize)
d195bc9f
MK		 382{
383 if (regnum != -1 && offset != -1)
f2db237a
AM		 384 {
385 if (regsize > 4)
386 {
387 struct gdbarch *gdbarch = get_regcache_arch (regcache);
388 int gdb_regsize = register_size (gdbarch, regnum);
389 if (gdb_regsize < regsize
390 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
391 offset += regsize - gdb_regsize;
392 }
393 regcache_raw_supply (regcache, regnum, regs + offset);
394 }
d195bc9f
MK		 395}
396
f2db237a
AM		 397/* Read register REGNUM from REGCACHE and store to REGS + OFFSET
398 in a field REGSIZE wide. Zero pad as necessary. */
399
7284e1be 400void
d195bc9f 401ppc_collect_reg (const struct regcache *regcache, int regnum,
f2db237a 402 gdb_byte *regs, size_t offset, int regsize)
d195bc9f
MK		 403{
404 if (regnum != -1 && offset != -1)
f2db237a
AM		 405 {
406 if (regsize > 4)
407 {
408 struct gdbarch *gdbarch = get_regcache_arch (regcache);
409 int gdb_regsize = register_size (gdbarch, regnum);
410 if (gdb_regsize < regsize)
411 {
412 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
413 {
414 memset (regs + offset, 0, regsize - gdb_regsize);
415 offset += regsize - gdb_regsize;
416 }
417 else
418 memset (regs + offset + regsize - gdb_regsize, 0,
419 regsize - gdb_regsize);
420 }
421 }
422 regcache_raw_collect (regcache, regnum, regs + offset);
423 }
d195bc9f
MK		 424}
425
f2db237a
AM		 426static int
427ppc_greg_offset (struct gdbarch *gdbarch,
428 struct gdbarch_tdep *tdep,
429 const struct ppc_reg_offsets *offsets,
430 int regnum,
431 int *regsize)
432{
433 *regsize = offsets->gpr_size;
434 if (regnum >= tdep->ppc_gp0_regnum
435 && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs)
436 return (offsets->r0_offset
437 + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size);
438
439 if (regnum == gdbarch_pc_regnum (gdbarch))
440 return offsets->pc_offset;
441
442 if (regnum == tdep->ppc_ps_regnum)
443 return offsets->ps_offset;
444
445 if (regnum == tdep->ppc_lr_regnum)
446 return offsets->lr_offset;
447
448 if (regnum == tdep->ppc_ctr_regnum)
449 return offsets->ctr_offset;
450
451 *regsize = offsets->xr_size;
452 if (regnum == tdep->ppc_cr_regnum)
453 return offsets->cr_offset;
454
455 if (regnum == tdep->ppc_xer_regnum)
456 return offsets->xer_offset;
457
458 if (regnum == tdep->ppc_mq_regnum)
459 return offsets->mq_offset;
460
461 return -1;
462}
463
464static int
465ppc_fpreg_offset (struct gdbarch_tdep *tdep,
466 const struct ppc_reg_offsets *offsets,
467 int regnum)
468{
469 if (regnum >= tdep->ppc_fp0_regnum
470 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs)
471 return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8;
472
473 if (regnum == tdep->ppc_fpscr_regnum)
474 return offsets->fpscr_offset;
475
476 return -1;
477}
478
06caf7d2
CES		 479static int
480ppc_vrreg_offset (struct gdbarch_tdep *tdep,
481 const struct ppc_reg_offsets *offsets,
482 int regnum)
483{
484 if (regnum >= tdep->ppc_vr0_regnum
485 && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs)
486 return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16;
487
488 if (regnum == tdep->ppc_vrsave_regnum - 1)
489 return offsets->vscr_offset;
490
491 if (regnum == tdep->ppc_vrsave_regnum)
492 return offsets->vrsave_offset;
493
494 return -1;
495}
496
d195bc9f
MK		 497/* Supply register REGNUM in the general-purpose register set REGSET
498 from the buffer specified by GREGS and LEN to register cache
499 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
500
501void
502ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
503 int regnum, const void *gregs, size_t len)
504{
505 struct gdbarch *gdbarch = get_regcache_arch (regcache);
506 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
507 const struct ppc_reg_offsets *offsets = regset->descr;
508 size_t offset;
f2db237a 509 int regsize;
d195bc9f 510
f2db237a 511 if (regnum == -1)
d195bc9f 512 {
f2db237a
AM		 513 int i;
514 int gpr_size = offsets->gpr_size;
515
516 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
517 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
518 i++, offset += gpr_size)
519 ppc_supply_reg (regcache, i, gregs, offset, gpr_size);
520
521 ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch),
522 gregs, offsets->pc_offset, gpr_size);
523 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
524 gregs, offsets->ps_offset, gpr_size);
525 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
526 gregs, offsets->lr_offset, gpr_size);
527 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
528 gregs, offsets->ctr_offset, gpr_size);
529 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
530 gregs, offsets->cr_offset, offsets->xr_size);
531 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
532 gregs, offsets->xer_offset, offsets->xr_size);
533 ppc_supply_reg (regcache, tdep->ppc_mq_regnum,
534 gregs, offsets->mq_offset, offsets->xr_size);
535 return;
d195bc9f
MK		 536 }
537
f2db237a
AM		 538 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
539 ppc_supply_reg (regcache, regnum, gregs, offset, regsize);
d195bc9f
MK		 540}
541
542/* Supply register REGNUM in the floating-point register set REGSET
543 from the buffer specified by FPREGS and LEN to register cache
544 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
545
546void
547ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
548 int regnum, const void *fpregs, size_t len)
549{
550 struct gdbarch *gdbarch = get_regcache_arch (regcache);
f2db237a
AM		 551 struct gdbarch_tdep *tdep;
552 const struct ppc_reg_offsets *offsets;
d195bc9f 553 size_t offset;
d195bc9f 554
f2db237a
AM		 555 if (!ppc_floating_point_unit_p (gdbarch))
556 return;
383f0f5b 557
f2db237a
AM		 558 tdep = gdbarch_tdep (gdbarch);
559 offsets = regset->descr;
560 if (regnum == -1)
d195bc9f 561 {
f2db237a
AM		 562 int i;
563
564 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
565 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
566 i++, offset += 8)
567 ppc_supply_reg (regcache, i, fpregs, offset, 8);
568
569 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
570 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
571 return;
d195bc9f
MK		 572 }
573
f2db237a
AM		 574 offset = ppc_fpreg_offset (tdep, offsets, regnum);
575 ppc_supply_reg (regcache, regnum, fpregs, offset,
576 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
d195bc9f
MK		 577}
578
604c2f83
LM		 579/* Supply register REGNUM in the VSX register set REGSET
580 from the buffer specified by VSXREGS and LEN to register cache
581 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
582
583void
584ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache,
585 int regnum, const void *vsxregs, size_t len)
586{
587 struct gdbarch *gdbarch = get_regcache_arch (regcache);
588 struct gdbarch_tdep *tdep;
589
590 if (!ppc_vsx_support_p (gdbarch))
591 return;
592
593 tdep = gdbarch_tdep (gdbarch);
594
595 if (regnum == -1)
596 {
597 int i;
598
599 for (i = tdep->ppc_vsr0_upper_regnum;
600 i < tdep->ppc_vsr0_upper_regnum + 32;
601 i++)
602 ppc_supply_reg (regcache, i, vsxregs, 0, 8);
603
604 return;
605 }
606 else
607 ppc_supply_reg (regcache, regnum, vsxregs, 0, 8);
608}
609
06caf7d2
CES		 610/* Supply register REGNUM in the Altivec register set REGSET
611 from the buffer specified by VRREGS and LEN to register cache
612 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
613
614void
615ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache,
616 int regnum, const void *vrregs, size_t len)
617{
618 struct gdbarch *gdbarch = get_regcache_arch (regcache);
619 struct gdbarch_tdep *tdep;
620 const struct ppc_reg_offsets *offsets;
621 size_t offset;
622
623 if (!ppc_altivec_support_p (gdbarch))
624 return;
625
626 tdep = gdbarch_tdep (gdbarch);
627 offsets = regset->descr;
628 if (regnum == -1)
629 {
630 int i;
631
632 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
633 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
634 i++, offset += 16)
635 ppc_supply_reg (regcache, i, vrregs, offset, 16);
636
637 ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
638 vrregs, offsets->vscr_offset, 4);
639
640 ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum,
641 vrregs, offsets->vrsave_offset, 4);
642 return;
643 }
644
645 offset = ppc_vrreg_offset (tdep, offsets, regnum);
646 if (regnum != tdep->ppc_vrsave_regnum
647 && regnum != tdep->ppc_vrsave_regnum - 1)
648 ppc_supply_reg (regcache, regnum, vrregs, offset, 16);
649 else
650 ppc_supply_reg (regcache, regnum,
651 vrregs, offset, 4);
652}
653
d195bc9f 654/* Collect register REGNUM in the general-purpose register set
f2db237a 655 REGSET from register cache REGCACHE into the buffer specified by
d195bc9f
MK		 656 GREGS and LEN. If REGNUM is -1, do this for all registers in
657 REGSET. */
658
659void
660ppc_collect_gregset (const struct regset *regset,
661 const struct regcache *regcache,
662 int regnum, void *gregs, size_t len)
663{
664 struct gdbarch *gdbarch = get_regcache_arch (regcache);
665 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
666 const struct ppc_reg_offsets *offsets = regset->descr;
667 size_t offset;
f2db237a 668 int regsize;
d195bc9f 669
f2db237a 670 if (regnum == -1)
d195bc9f 671 {
f2db237a
AM		 672 int i;
673 int gpr_size = offsets->gpr_size;
674
675 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
676 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
677 i++, offset += gpr_size)
678 ppc_collect_reg (regcache, i, gregs, offset, gpr_size);
679
680 ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch),
681 gregs, offsets->pc_offset, gpr_size);
682 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
683 gregs, offsets->ps_offset, gpr_size);
684 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
685 gregs, offsets->lr_offset, gpr_size);
686 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
687 gregs, offsets->ctr_offset, gpr_size);
688 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
689 gregs, offsets->cr_offset, offsets->xr_size);
690 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
691 gregs, offsets->xer_offset, offsets->xr_size);
692 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
693 gregs, offsets->mq_offset, offsets->xr_size);
694 return;
d195bc9f
MK		 695 }
696
f2db237a
AM		 697 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
698 ppc_collect_reg (regcache, regnum, gregs, offset, regsize);
d195bc9f
MK		 699}
700
701/* Collect register REGNUM in the floating-point register set
f2db237a 702 REGSET from register cache REGCACHE into the buffer specified by
d195bc9f
MK		 703 FPREGS and LEN. If REGNUM is -1, do this for all registers in
704 REGSET. */
705
706void
707ppc_collect_fpregset (const struct regset *regset,
708 const struct regcache *regcache,
709 int regnum, void *fpregs, size_t len)
710{
711 struct gdbarch *gdbarch = get_regcache_arch (regcache);
f2db237a
AM		 712 struct gdbarch_tdep *tdep;
713 const struct ppc_reg_offsets *offsets;
d195bc9f 714 size_t offset;
d195bc9f 715
f2db237a
AM		 716 if (!ppc_floating_point_unit_p (gdbarch))
717 return;
383f0f5b 718
f2db237a
AM		 719 tdep = gdbarch_tdep (gdbarch);
720 offsets = regset->descr;
721 if (regnum == -1)
d195bc9f 722 {
f2db237a
AM		 723 int i;
724
725 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
726 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
727 i++, offset += 8)
728 ppc_collect_reg (regcache, i, fpregs, offset, 8);
729
730 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
731 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
732 return;
d195bc9f
MK		 733 }
734
f2db237a
AM		 735 offset = ppc_fpreg_offset (tdep, offsets, regnum);
736 ppc_collect_reg (regcache, regnum, fpregs, offset,
737 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
d195bc9f 738}
06caf7d2 739
604c2f83
LM		 740/* Collect register REGNUM in the VSX register set
741 REGSET from register cache REGCACHE into the buffer specified by
742 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
743 REGSET. */
744
745void
746ppc_collect_vsxregset (const struct regset *regset,
747 const struct regcache *regcache,
748 int regnum, void *vsxregs, size_t len)
749{
750 struct gdbarch *gdbarch = get_regcache_arch (regcache);
751 struct gdbarch_tdep *tdep;
752
753 if (!ppc_vsx_support_p (gdbarch))
754 return;
755
756 tdep = gdbarch_tdep (gdbarch);
757
758 if (regnum == -1)
759 {
760 int i;
761
762 for (i = tdep->ppc_vsr0_upper_regnum;
763 i < tdep->ppc_vsr0_upper_regnum + 32;
764 i++)
765 ppc_collect_reg (regcache, i, vsxregs, 0, 8);
766
767 return;
768 }
769 else
770 ppc_collect_reg (regcache, regnum, vsxregs, 0, 8);
771}
772
773
06caf7d2
CES		 774/* Collect register REGNUM in the Altivec register set
775 REGSET from register cache REGCACHE into the buffer specified by
776 VRREGS and LEN. If REGNUM is -1, do this for all registers in
777 REGSET. */
778
779void
780ppc_collect_vrregset (const struct regset *regset,
781 const struct regcache *regcache,
782 int regnum, void *vrregs, size_t len)
783{
784 struct gdbarch *gdbarch = get_regcache_arch (regcache);
785 struct gdbarch_tdep *tdep;
786 const struct ppc_reg_offsets *offsets;
787 size_t offset;
788
789 if (!ppc_altivec_support_p (gdbarch))
790 return;
791
792 tdep = gdbarch_tdep (gdbarch);
793 offsets = regset->descr;
794 if (regnum == -1)
795 {
796 int i;
797
798 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
799 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
800 i++, offset += 16)
801 ppc_collect_reg (regcache, i, vrregs, offset, 16);
802
803 ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
804 vrregs, offsets->vscr_offset, 4);
805
806 ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum,
807 vrregs, offsets->vrsave_offset, 4);
808 return;
809 }
810
811 offset = ppc_vrreg_offset (tdep, offsets, regnum);
812 if (regnum != tdep->ppc_vrsave_regnum
813 && regnum != tdep->ppc_vrsave_regnum - 1)
814 ppc_collect_reg (regcache, regnum, vrregs, offset, 16);
815 else
816 ppc_collect_reg (regcache, regnum,
817 vrregs, offset, 4);
818}
d195bc9f 819\f
0a613259 820
0d1243d9
PG		 821static int
822insn_changes_sp_or_jumps (unsigned long insn)
823{
824 int opcode = (insn >> 26) & 0x03f;
825 int sd = (insn >> 21) & 0x01f;
826 int a = (insn >> 16) & 0x01f;
827 int subcode = (insn >> 1) & 0x3ff;
828
829 /* Changes the stack pointer. */
830
831 /* NOTE: There are many ways to change the value of a given register.
832 The ways below are those used when the register is R1, the SP,
833 in a funtion's epilogue. */
834
835 if (opcode == 31 && subcode == 444 && a == 1)
836 return 1; /* mr R1,Rn */
837 if (opcode == 14 && sd == 1)
838 return 1; /* addi R1,Rn,simm */
839 if (opcode == 58 && sd == 1)
840 return 1; /* ld R1,ds(Rn) */
841
842 /* Transfers control. */
843
844 if (opcode == 18)
845 return 1; /* b */
846 if (opcode == 16)
847 return 1; /* bc */
848 if (opcode == 19 && subcode == 16)
849 return 1; /* bclr */
850 if (opcode == 19 && subcode == 528)
851 return 1; /* bcctr */
852
853 return 0;
854}
855
856/* Return true if we are in the function's epilogue, i.e. after the
857 instruction that destroyed the function's stack frame.
858
859 1) scan forward from the point of execution:
860 a) If you find an instruction that modifies the stack pointer
861 or transfers control (except a return), execution is not in
862 an epilogue, return.
863 b) Stop scanning if you find a return instruction or reach the
864 end of the function or reach the hard limit for the size of
865 an epilogue.
866 2) scan backward from the point of execution:
867 a) If you find an instruction that modifies the stack pointer,
868 execution *is* in an epilogue, return.
869 b) Stop scanning if you reach an instruction that transfers
870 control or the beginning of the function or reach the hard
871 limit for the size of an epilogue. */
872
873static int
874rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
875{
46a9b8ed 876 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 877 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
0d1243d9
PG		 878 bfd_byte insn_buf[PPC_INSN_SIZE];
879 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
880 unsigned long insn;
881 struct frame_info *curfrm;
882
883 /* Find the search limits based on function boundaries and hard limit. */
884
885 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
886 return 0;
887
888 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
889 if (epilogue_start < func_start) epilogue_start = func_start;
890
891 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
892 if (epilogue_end > func_end) epilogue_end = func_end;
893
894 curfrm = get_current_frame ();
895
896 /* Scan forward until next 'blr'. */
897
898 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
899 {
900 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
901 return 0;
e17a4113 902 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
0d1243d9
PG		 903 if (insn == 0x4e800020)
904 break;
46a9b8ed
DJ		 905 /* Assume a bctr is a tail call unless it points strictly within
906 this function. */
907 if (insn == 0x4e800420)
908 {
909 CORE_ADDR ctr = get_frame_register_unsigned (curfrm,
910 tdep->ppc_ctr_regnum);
911 if (ctr > func_start && ctr < func_end)
912 return 0;
913 else
914 break;
915 }
0d1243d9
PG		 916 if (insn_changes_sp_or_jumps (insn))
917 return 0;
918 }
919
920 /* Scan backward until adjustment to stack pointer (R1). */
921
922 for (scan_pc = pc - PPC_INSN_SIZE;
923 scan_pc >= epilogue_start;
924 scan_pc -= PPC_INSN_SIZE)
925 {
926 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
927 return 0;
e17a4113 928 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
0d1243d9
PG		 929 if (insn_changes_sp_or_jumps (insn))
930 return 1;
931 }
932
933 return 0;
934}
935
143985b7 936/* Get the ith function argument for the current function. */
b9362cc7 937static CORE_ADDR
143985b7
AF		 938rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
939 struct type *type)
940{
50fd1280 941 return get_frame_register_unsigned (frame, 3 + argi);
143985b7
AF		 942}
943
c906108c
SS		 944/* Sequence of bytes for breakpoint instruction. */
945
f4f9705a 946const static unsigned char *
67d57894
MD		 947rs6000_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
948 int *bp_size)
c906108c 949{
aaab4dba
AC		 950 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
951 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
c906108c 952 *bp_size = 4;
67d57894 953 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
c906108c
SS		 954 return big_breakpoint;
955 else
956 return little_breakpoint;
957}
958
f74c6cad
LM		 959/* Instruction masks for displaced stepping. */
960#define BRANCH_MASK 0xfc000000
961#define BP_MASK 0xFC0007FE
962#define B_INSN 0x48000000
963#define BC_INSN 0x40000000
964#define BXL_INSN 0x4c000000
965#define BP_INSN 0x7C000008
966
967/* Fix up the state of registers and memory after having single-stepped
968 a displaced instruction. */
63807e1d 969static void
f74c6cad 970ppc_displaced_step_fixup (struct gdbarch *gdbarch,
63807e1d
PA		 971 struct displaced_step_closure *closure,
972 CORE_ADDR from, CORE_ADDR to,
973 struct regcache *regs)
f74c6cad 974{
e17a4113 975 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
f74c6cad
LM		 976 /* Since we use simple_displaced_step_copy_insn, our closure is a
977 copy of the instruction. */
978 ULONGEST insn = extract_unsigned_integer ((gdb_byte *) closure,
e17a4113 979 PPC_INSN_SIZE, byte_order);
f74c6cad
LM		 980 ULONGEST opcode = 0;
981 /* Offset for non PC-relative instructions. */
982 LONGEST offset = PPC_INSN_SIZE;
983
984 opcode = insn & BRANCH_MASK;
985
986 if (debug_displaced)
987 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 988 "displaced: (ppc) fixup (%s, %s)\n",
989 paddress (gdbarch, from), paddress (gdbarch, to));
f74c6cad
LM		 990
991
992 /* Handle PC-relative branch instructions. */
993 if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN)
994 {
a4fafde3 995 ULONGEST current_pc;
f74c6cad
LM		 996
997 /* Read the current PC value after the instruction has been executed
998 in a displaced location. Calculate the offset to be applied to the
999 original PC value before the displaced stepping. */
1000 regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1001 &current_pc);
1002 offset = current_pc - to;
1003
1004 if (opcode != BXL_INSN)
1005 {
1006 /* Check for AA bit indicating whether this is an absolute
1007 addressing or PC-relative (1: absolute, 0: relative). */
1008 if (!(insn & 0x2))
1009 {
1010 /* PC-relative addressing is being used in the branch. */
1011 if (debug_displaced)
1012 fprintf_unfiltered
1013 (gdb_stdlog,
5af949e3
UW		 1014 "displaced: (ppc) branch instruction: %s\n"
1015 "displaced: (ppc) adjusted PC from %s to %s\n",
1016 paddress (gdbarch, insn), paddress (gdbarch, current_pc),
1017 paddress (gdbarch, from + offset));
f74c6cad 1018
0df8b418
MS		 1019 regcache_cooked_write_unsigned (regs,
1020 gdbarch_pc_regnum (gdbarch),
f74c6cad
LM		 1021 from + offset);
1022 }
1023 }
1024 else
1025 {
1026 /* If we're here, it means we have a branch to LR or CTR. If the
1027 branch was taken, the offset is probably greater than 4 (the next
1028 instruction), so it's safe to assume that an offset of 4 means we
1029 did not take the branch. */
1030 if (offset == PPC_INSN_SIZE)
1031 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1032 from + PPC_INSN_SIZE);
1033 }
1034
1035 /* Check for LK bit indicating whether we should set the link
1036 register to point to the next instruction
1037 (1: Set, 0: Don't set). */
1038 if (insn & 0x1)
1039 {
1040 /* Link register needs to be set to the next instruction's PC. */
1041 regcache_cooked_write_unsigned (regs,
1042 gdbarch_tdep (gdbarch)->ppc_lr_regnum,
1043 from + PPC_INSN_SIZE);
1044 if (debug_displaced)
1045 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 1046 "displaced: (ppc) adjusted LR to %s\n",
1047 paddress (gdbarch, from + PPC_INSN_SIZE));
f74c6cad
LM		 1048
1049 }
1050 }
1051 /* Check for breakpoints in the inferior. If we've found one, place the PC
1052 right at the breakpoint instruction. */
1053 else if ((insn & BP_MASK) == BP_INSN)
1054 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from);
1055 else
1056 /* Handle any other instructions that do not fit in the categories above. */
1057 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1058 from + offset);
1059}
c906108c 1060
99e40580
UW		 1061/* Always use hardware single-stepping to execute the
1062 displaced instruction. */
1063static int
1064ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
1065 struct displaced_step_closure *closure)
1066{
1067 return 1;
1068}
1069
ce5eab59
UW		 1070/* Instruction masks used during single-stepping of atomic sequences. */
1071#define LWARX_MASK 0xfc0007fe
1072#define LWARX_INSTRUCTION 0x7c000028
1073#define LDARX_INSTRUCTION 0x7c0000A8
1074#define STWCX_MASK 0xfc0007ff
1075#define STWCX_INSTRUCTION 0x7c00012d
1076#define STDCX_INSTRUCTION 0x7c0001ad
ce5eab59
UW		 1077
1078/* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1079 instruction and ending with a STWCX/STDCX instruction. If such a sequence
1080 is found, attempt to step through it. A breakpoint is placed at the end of
1081 the sequence. */
1082
4a7622d1
UW		 1083int
1084ppc_deal_with_atomic_sequence (struct frame_info *frame)
ce5eab59 1085{
a6d9a66e 1086 struct gdbarch *gdbarch = get_frame_arch (frame);
6c95b8df 1087 struct address_space *aspace = get_frame_address_space (frame);
e17a4113 1088 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
0b1b3e42 1089 CORE_ADDR pc = get_frame_pc (frame);
ce5eab59
UW		 1090 CORE_ADDR breaks[2] = {-1, -1};
1091 CORE_ADDR loc = pc;
24d45690 1092 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
e17a4113 1093 int insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
ce5eab59
UW		 1094 int insn_count;
1095 int index;
1096 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
1097 const int atomic_sequence_length = 16; /* Instruction sequence length. */
24d45690 1098 int opcode; /* Branch instruction's OPcode. */
ce5eab59
UW		 1099 int bc_insn_count = 0; /* Conditional branch instruction count. */
1100
1101 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1102 if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
1103 && (insn & LWARX_MASK) != LDARX_INSTRUCTION)
1104 return 0;
1105
1106 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1107 instructions. */
1108 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
1109 {
1110 loc += PPC_INSN_SIZE;
e17a4113 1111 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
ce5eab59
UW		 1112
1113 /* Assume that there is at most one conditional branch in the atomic
1114 sequence. If a conditional branch is found, put a breakpoint in
1115 its destination address. */
f74c6cad 1116 if ((insn & BRANCH_MASK) == BC_INSN)
ce5eab59 1117 {
a3769e0c
AM		 1118 int immediate = ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1119 int absolute = insn & 2;
4a7622d1 1120
ce5eab59
UW		 1121 if (bc_insn_count >= 1)
1122 return 0; /* More than one conditional branch found, fallback
1123 to the standard single-step code. */
4a7622d1
UW		 1124
1125 if (absolute)
1126 breaks[1] = immediate;
1127 else
a3769e0c 1128 breaks[1] = loc + immediate;
4a7622d1
UW		 1129
1130 bc_insn_count++;
1131 last_breakpoint++;
ce5eab59
UW		 1132 }
1133
1134 if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
1135 || (insn & STWCX_MASK) == STDCX_INSTRUCTION)
1136 break;
1137 }
1138
1139 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1140 if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
1141 && (insn & STWCX_MASK) != STDCX_INSTRUCTION)
1142 return 0;
1143
24d45690 1144 closing_insn = loc;
ce5eab59 1145 loc += PPC_INSN_SIZE;
e17a4113 1146 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
ce5eab59
UW		 1147
1148 /* Insert a breakpoint right after the end of the atomic sequence. */
1149 breaks[0] = loc;
1150
24d45690 1151 /* Check for duplicated breakpoints. Check also for a breakpoint
a3769e0c
AM		 1152 placed (branch instruction's destination) anywhere in sequence. */
1153 if (last_breakpoint
1154 && (breaks[1] == breaks[0]
1155 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
ce5eab59
UW		 1156 last_breakpoint = 0;
1157
1158 /* Effectively inserts the breakpoints. */
1159 for (index = 0; index <= last_breakpoint; index++)
6c95b8df 1160 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
ce5eab59
UW		 1161
1162 return 1;
1163}
1164
c906108c 1165
c906108c
SS		 1166#define SIGNED_SHORT(x) \
1167 ((sizeof (short) == 2) \
1168 ? ((int)(short)(x)) \
1169 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1170
1171#define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1172
55d05f3b
KB		 1173/* Limit the number of skipped non-prologue instructions, as the examining
1174 of the prologue is expensive. */
1175static int max_skip_non_prologue_insns = 10;
1176
773df3e5
JB		 1177/* Return nonzero if the given instruction OP can be part of the prologue
1178 of a function and saves a parameter on the stack. FRAMEP should be
1179 set if one of the previous instructions in the function has set the
1180 Frame Pointer. */
1181
1182static int
1183store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
1184{
1185 /* Move parameters from argument registers to temporary register. */
1186 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1187 {
1188 /* Rx must be scratch register r0. */
1189 const int rx_regno = (op >> 16) & 31;
1190 /* Ry: Only r3 - r10 are used for parameter passing. */
1191 const int ry_regno = GET_SRC_REG (op);
1192
1193 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
1194 {
1195 *r0_contains_arg = 1;
1196 return 1;
1197 }
1198 else
1199 return 0;
1200 }
1201
1202 /* Save a General Purpose Register on stack. */
1203
1204 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1205 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1206 {
1207 /* Rx: Only r3 - r10 are used for parameter passing. */
1208 const int rx_regno = GET_SRC_REG (op);
1209
1210 return (rx_regno >= 3 && rx_regno <= 10);
1211 }
1212
1213 /* Save a General Purpose Register on stack via the Frame Pointer. */
1214
1215 if (framep &&
1216 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1217 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1218 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1219 {
1220 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1221 However, the compiler sometimes uses r0 to hold an argument. */
1222 const int rx_regno = GET_SRC_REG (op);
1223
1224 return ((rx_regno >= 3 && rx_regno <= 10)
1225 || (rx_regno == 0 && *r0_contains_arg));
1226 }
1227
1228 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1229 {
1230 /* Only f2 - f8 are used for parameter passing. */
1231 const int src_regno = GET_SRC_REG (op);
1232
1233 return (src_regno >= 2 && src_regno <= 8);
1234 }
1235
1236 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1237 {
1238 /* Only f2 - f8 are used for parameter passing. */
1239 const int src_regno = GET_SRC_REG (op);
1240
1241 return (src_regno >= 2 && src_regno <= 8);
1242 }
1243
1244 /* Not an insn that saves a parameter on stack. */
1245 return 0;
1246}
55d05f3b 1247
3c77c82a
DJ		 1248/* Assuming that INSN is a "bl" instruction located at PC, return
1249 nonzero if the destination of the branch is a "blrl" instruction.
1250
1251 This sequence is sometimes found in certain function prologues.
1252 It allows the function to load the LR register with a value that
1253 they can use to access PIC data using PC-relative offsets. */
1254
1255static int
e17a4113 1256bl_to_blrl_insn_p (CORE_ADDR pc, int insn, enum bfd_endian byte_order)
3c77c82a 1257{
0b1b3e42
UW		 1258 CORE_ADDR dest;
1259 int immediate;
1260 int absolute;
3c77c82a
DJ		 1261 int dest_insn;
1262
0b1b3e42
UW		 1263 absolute = (int) ((insn >> 1) & 1);
1264 immediate = ((insn & ~3) << 6) >> 6;
1265 if (absolute)
1266 dest = immediate;
1267 else
1268 dest = pc + immediate;
1269
e17a4113 1270 dest_insn = read_memory_integer (dest, 4, byte_order);
3c77c82a
DJ		 1271 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
1272 return 1;
1273
1274 return 0;
1275}
1276
0df8b418 1277/* Masks for decoding a branch-and-link (bl) instruction.
8ab3d180
KB		 1278
1279 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1280 The former is anded with the opcode in question; if the result of
1281 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1282 question is a ``bl'' instruction.
1283
1284 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1285 the branch displacement. */
1286
1287#define BL_MASK 0xfc000001
1288#define BL_INSTRUCTION 0x48000001
1289#define BL_DISPLACEMENT_MASK 0x03fffffc
1290
de9f48f0 1291static unsigned long
e17a4113 1292rs6000_fetch_instruction (struct gdbarch *gdbarch, const CORE_ADDR pc)
de9f48f0 1293{
e17a4113 1294 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
de9f48f0
JG		 1295 gdb_byte buf[4];
1296 unsigned long op;
1297
1298 /* Fetch the instruction and convert it to an integer. */
1299 if (target_read_memory (pc, buf, 4))
1300 return 0;
e17a4113 1301 op = extract_unsigned_integer (buf, 4, byte_order);
de9f48f0
JG		 1302
1303 return op;
1304}
1305
1306/* GCC generates several well-known sequences of instructions at the begining
1307 of each function prologue when compiling with -fstack-check. If one of
1308 such sequences starts at START_PC, then return the address of the
1309 instruction immediately past this sequence. Otherwise, return START_PC. */
1310
1311static CORE_ADDR
e17a4113 1312rs6000_skip_stack_check (struct gdbarch *gdbarch, const CORE_ADDR start_pc)
de9f48f0
JG		 1313{
1314 CORE_ADDR pc = start_pc;
e17a4113 1315 unsigned long op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1316
1317 /* First possible sequence: A small number of probes.
1318 stw 0, -<some immediate>(1)
0df8b418 1319 [repeat this instruction any (small) number of times]. */
de9f48f0
JG		 1320
1321 if ((op & 0xffff0000) == 0x90010000)
1322 {
1323 while ((op & 0xffff0000) == 0x90010000)
1324 {
1325 pc = pc + 4;
e17a4113 1326 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1327 }
1328 return pc;
1329 }
1330
1331 /* Second sequence: A probing loop.
1332 addi 12,1,-<some immediate>
1333 lis 0,-<some immediate>
1334 [possibly ori 0,0,<some immediate>]
1335 add 0,12,0
1336 cmpw 0,12,0
1337 beq 0,<disp>
1338 addi 12,12,-<some immediate>
1339 stw 0,0(12)
1340 b <disp>
0df8b418 1341 [possibly one last probe: stw 0,<some immediate>(12)]. */
de9f48f0
JG		 1342
1343 while (1)
1344 {
1345 /* addi 12,1,-<some immediate> */
1346 if ((op & 0xffff0000) != 0x39810000)
1347 break;
1348
1349 /* lis 0,-<some immediate> */
1350 pc = pc + 4;
e17a4113 1351 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1352 if ((op & 0xffff0000) != 0x3c000000)
1353 break;
1354
1355 pc = pc + 4;
e17a4113 1356 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1357 /* [possibly ori 0,0,<some immediate>] */
1358 if ((op & 0xffff0000) == 0x60000000)
1359 {
1360 pc = pc + 4;
e17a4113 1361 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1362 }
1363 /* add 0,12,0 */
1364 if (op != 0x7c0c0214)
1365 break;
1366
1367 /* cmpw 0,12,0 */
1368 pc = pc + 4;
e17a4113 1369 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1370 if (op != 0x7c0c0000)
1371 break;
1372
1373 /* beq 0,<disp> */
1374 pc = pc + 4;
e17a4113 1375 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1376 if ((op & 0xff9f0001) != 0x41820000)
1377 break;
1378
1379 /* addi 12,12,-<some immediate> */
1380 pc = pc + 4;
e17a4113 1381 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1382 if ((op & 0xffff0000) != 0x398c0000)
1383 break;
1384
1385 /* stw 0,0(12) */
1386 pc = pc + 4;
e17a4113 1387 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1388 if (op != 0x900c0000)
1389 break;
1390
1391 /* b <disp> */
1392 pc = pc + 4;
e17a4113 1393 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1394 if ((op & 0xfc000001) != 0x48000000)
1395 break;
1396
0df8b418 1397 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
de9f48f0 1398 pc = pc + 4;
e17a4113 1399 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1400 if ((op & 0xffff0000) == 0x900c0000)
1401 {
1402 pc = pc + 4;
e17a4113 1403 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1404 }
1405
1406 /* We found a valid stack-check sequence, return the new PC. */
1407 return pc;
1408 }
1409
1410 /* Third sequence: No probe; instead, a comparizon between the stack size
1411 limit (saved in a run-time global variable) and the current stack
1412 pointer:
1413
1414 addi 0,1,-<some immediate>
1415 lis 12,__gnat_stack_limit@ha
1416 lwz 12,__gnat_stack_limit@l(12)
1417 twllt 0,12
1418
1419 or, with a small variant in the case of a bigger stack frame:
1420 addis 0,1,<some immediate>
1421 addic 0,0,-<some immediate>
1422 lis 12,__gnat_stack_limit@ha
1423 lwz 12,__gnat_stack_limit@l(12)
1424 twllt 0,12
1425 */
1426 while (1)
1427 {
1428 /* addi 0,1,-<some immediate> */
1429 if ((op & 0xffff0000) != 0x38010000)
1430 {
1431 /* small stack frame variant not recognized; try the
1432 big stack frame variant: */
1433
1434 /* addis 0,1,<some immediate> */
1435 if ((op & 0xffff0000) != 0x3c010000)
1436 break;
1437
1438 /* addic 0,0,-<some immediate> */
1439 pc = pc + 4;
e17a4113 1440 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1441 if ((op & 0xffff0000) != 0x30000000)
1442 break;
1443 }
1444
1445 /* lis 12,<some immediate> */
1446 pc = pc + 4;
e17a4113 1447 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1448 if ((op & 0xffff0000) != 0x3d800000)
1449 break;
1450
1451 /* lwz 12,<some immediate>(12) */
1452 pc = pc + 4;
e17a4113 1453 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1454 if ((op & 0xffff0000) != 0x818c0000)
1455 break;
1456
1457 /* twllt 0,12 */
1458 pc = pc + 4;
e17a4113 1459 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1460 if ((op & 0xfffffffe) != 0x7c406008)
1461 break;
1462
1463 /* We found a valid stack-check sequence, return the new PC. */
1464 return pc;
1465 }
1466
1467 /* No stack check code in our prologue, return the start_pc. */
1468 return start_pc;
1469}
1470
6a16c029
TJB		 1471/* return pc value after skipping a function prologue and also return
1472 information about a function frame.
1473
1474 in struct rs6000_framedata fdata:
1475 - frameless is TRUE, if function does not have a frame.
1476 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1477 - offset is the initial size of this stack frame --- the amount by
1478 which we decrement the sp to allocate the frame.
1479 - saved_gpr is the number of the first saved gpr.
1480 - saved_fpr is the number of the first saved fpr.
1481 - saved_vr is the number of the first saved vr.
1482 - saved_ev is the number of the first saved ev.
1483 - alloca_reg is the number of the register used for alloca() handling.
1484 Otherwise -1.
1485 - gpr_offset is the offset of the first saved gpr from the previous frame.
1486 - fpr_offset is the offset of the first saved fpr from the previous frame.
1487 - vr_offset is the offset of the first saved vr from the previous frame.
1488 - ev_offset is the offset of the first saved ev from the previous frame.
1489 - lr_offset is the offset of the saved lr
1490 - cr_offset is the offset of the saved cr
0df8b418 1491 - vrsave_offset is the offset of the saved vrsave register. */
6a16c029 1492
7a78ae4e 1493static CORE_ADDR
be8626e0
MD		 1494skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc,
1495 struct rs6000_framedata *fdata)
c906108c
SS		 1496{
1497 CORE_ADDR orig_pc = pc;
55d05f3b 1498 CORE_ADDR last_prologue_pc = pc;
6be8bc0c 1499 CORE_ADDR li_found_pc = 0;
50fd1280 1500 gdb_byte buf[4];
c906108c
SS		 1501 unsigned long op;
1502 long offset = 0;
6be8bc0c 1503 long vr_saved_offset = 0;
482ca3f5
KB		 1504 int lr_reg = -1;
1505 int cr_reg = -1;
6be8bc0c 1506 int vr_reg = -1;
96ff0de4
EZ		 1507 int ev_reg = -1;
1508 long ev_offset = 0;
6be8bc0c 1509 int vrsave_reg = -1;
c906108c
SS		 1510 int reg;
1511 int framep = 0;
1512 int minimal_toc_loaded = 0;
ddb20c56 1513 int prev_insn_was_prologue_insn = 1;
55d05f3b 1514 int num_skip_non_prologue_insns = 0;
773df3e5 1515 int r0_contains_arg = 0;
be8626e0
MD		 1516 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch);
1517 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 1518 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
c906108c 1519
ddb20c56 1520 memset (fdata, 0, sizeof (struct rs6000_framedata));
c906108c
SS		 1521 fdata->saved_gpr = -1;
1522 fdata->saved_fpr = -1;
6be8bc0c 1523 fdata->saved_vr = -1;
96ff0de4 1524 fdata->saved_ev = -1;
c906108c
SS		 1525 fdata->alloca_reg = -1;
1526 fdata->frameless = 1;
1527 fdata->nosavedpc = 1;
46a9b8ed 1528 fdata->lr_register = -1;
c906108c 1529
e17a4113 1530 pc = rs6000_skip_stack_check (gdbarch, pc);
de9f48f0
JG		 1531 if (pc >= lim_pc)
1532 pc = lim_pc;
1533
55d05f3b 1534 for (;; pc += 4)
c906108c 1535 {
ddb20c56
KB		 1536 /* Sometimes it isn't clear if an instruction is a prologue
1537 instruction or not. When we encounter one of these ambiguous
1538 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
0df8b418 1539 Otherwise, we'll assume that it really is a prologue instruction. */
ddb20c56
KB		 1540 if (prev_insn_was_prologue_insn)
1541 last_prologue_pc = pc;
55d05f3b
KB		 1542
1543 /* Stop scanning if we've hit the limit. */
4e463ff5 1544 if (pc >= lim_pc)
55d05f3b
KB		 1545 break;
1546
ddb20c56
KB		 1547 prev_insn_was_prologue_insn = 1;
1548
55d05f3b 1549 /* Fetch the instruction and convert it to an integer. */
ddb20c56
KB		 1550 if (target_read_memory (pc, buf, 4))
1551 break;
e17a4113 1552 op = extract_unsigned_integer (buf, 4, byte_order);
c906108c 1553
c5aa993b
JM		 1554 if ((op & 0xfc1fffff) == 0x7c0802a6)
1555 { /* mflr Rx */
43b1ab88
AC		 1556 /* Since shared library / PIC code, which needs to get its
1557 address at runtime, can appear to save more than one link
1558 register vis:
1559
1560 *INDENT-OFF*
1561 stwu r1,-304(r1)
1562 mflr r3
1563 bl 0xff570d0 (blrl)
1564 stw r30,296(r1)
1565 mflr r30
1566 stw r31,300(r1)
1567 stw r3,308(r1);
1568 ...
1569 *INDENT-ON*
1570
1571 remember just the first one, but skip over additional
1572 ones. */
721d14ba 1573 if (lr_reg == -1)
46a9b8ed 1574 lr_reg = (op & 0x03e00000) >> 21;
773df3e5
JB		 1575 if (lr_reg == 0)
1576 r0_contains_arg = 0;
c5aa993b 1577 continue;
c5aa993b
JM		 1578 }
1579 else if ((op & 0xfc1fffff) == 0x7c000026)
1580 { /* mfcr Rx */
98f08d3d 1581 cr_reg = (op & 0x03e00000);
773df3e5
JB		 1582 if (cr_reg == 0)
1583 r0_contains_arg = 0;
c5aa993b 1584 continue;
c906108c 1585
c906108c 1586 }
c5aa993b
JM		 1587 else if ((op & 0xfc1f0000) == 0xd8010000)
1588 { /* stfd Rx,NUM(r1) */
1589 reg = GET_SRC_REG (op);
1590 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1591 {
1592 fdata->saved_fpr = reg;
1593 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1594 }
1595 continue;
c906108c 1596
c5aa993b
JM		 1597 }
1598 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
7a78ae4e
ND		 1599 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1600 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1601 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
c5aa993b
JM		 1602 {
1603
1604 reg = GET_SRC_REG (op);
46a9b8ed
DJ		 1605 if ((op & 0xfc1f0000) == 0xbc010000)
1606 fdata->gpr_mask |= ~((1U << reg) - 1);
1607 else
1608 fdata->gpr_mask |= 1U << reg;
c5aa993b
JM		 1609 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1610 {
1611 fdata->saved_gpr = reg;
7a78ae4e 1612 if ((op & 0xfc1f0003) == 0xf8010000)
98f08d3d 1613 op &= ~3UL;
c5aa993b
JM		 1614 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1615 }
1616 continue;
c906108c 1617
ddb20c56
KB		 1618 }
1619 else if ((op & 0xffff0000) == 0x60000000)
1620 {
96ff0de4 1621 /* nop */
ddb20c56
KB		 1622 /* Allow nops in the prologue, but do not consider them to
1623 be part of the prologue unless followed by other prologue
0df8b418 1624 instructions. */
ddb20c56
KB		 1625 prev_insn_was_prologue_insn = 0;
1626 continue;
1627
c906108c 1628 }
c5aa993b
JM		 1629 else if ((op & 0xffff0000) == 0x3c000000)
1630 { /* addis 0,0,NUM, used
1631 for >= 32k frames */
1632 fdata->offset = (op & 0x0000ffff) << 16;
1633 fdata->frameless = 0;
773df3e5 1634 r0_contains_arg = 0;
c5aa993b
JM		 1635 continue;
1636
1637 }
1638 else if ((op & 0xffff0000) == 0x60000000)
1639 { /* ori 0,0,NUM, 2nd ha
1640 lf of >= 32k frames */
1641 fdata->offset |= (op & 0x0000ffff);
1642 fdata->frameless = 0;
773df3e5 1643 r0_contains_arg = 0;
c5aa993b
JM		 1644 continue;
1645
1646 }
be723e22 1647 else if (lr_reg >= 0 &&
98f08d3d
KB		 1648 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1649 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1650 /* stw Rx, NUM(r1) */
1651 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1652 /* stwu Rx, NUM(r1) */
1653 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1654 { /* where Rx == lr */
1655 fdata->lr_offset = offset;
c5aa993b 1656 fdata->nosavedpc = 0;
be723e22
MS		 1657 /* Invalidate lr_reg, but don't set it to -1.
1658 That would mean that it had never been set. */
1659 lr_reg = -2;
98f08d3d
KB		 1660 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1661 (op & 0xfc000000) == 0x90000000) /* stw */
1662 {
1663 /* Does not update r1, so add displacement to lr_offset. */
1664 fdata->lr_offset += SIGNED_SHORT (op);
1665 }
c5aa993b
JM		 1666 continue;
1667
1668 }
be723e22 1669 else if (cr_reg >= 0 &&
98f08d3d
KB		 1670 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1671 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1672 /* stw Rx, NUM(r1) */
1673 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1674 /* stwu Rx, NUM(r1) */
1675 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1676 { /* where Rx == cr */
1677 fdata->cr_offset = offset;
be723e22
MS		 1678 /* Invalidate cr_reg, but don't set it to -1.
1679 That would mean that it had never been set. */
1680 cr_reg = -2;
98f08d3d
KB		 1681 if ((op & 0xfc000003) == 0xf8000000 ||
1682 (op & 0xfc000000) == 0x90000000)
1683 {
1684 /* Does not update r1, so add displacement to cr_offset. */
1685 fdata->cr_offset += SIGNED_SHORT (op);
1686 }
c5aa993b
JM		 1687 continue;
1688
1689 }
721d14ba
DJ		 1690 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1691 {
1692 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1693 prediction bits. If the LR has already been saved, we can
1694 skip it. */
1695 continue;
1696 }
c5aa993b
JM		 1697 else if (op == 0x48000005)
1698 { /* bl .+4 used in
1699 -mrelocatable */
46a9b8ed 1700 fdata->used_bl = 1;
c5aa993b
JM		 1701 continue;
1702
1703 }
1704 else if (op == 0x48000004)
1705 { /* b .+4 (xlc) */
1706 break;
1707
c5aa993b 1708 }
6be8bc0c
EZ		 1709 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1710 in V.4 -mminimal-toc */
c5aa993b
JM		 1711 (op & 0xffff0000) == 0x3bde0000)
1712 { /* addi 30,30,foo@l */
1713 continue;
c906108c 1714
c5aa993b
JM		 1715 }
1716 else if ((op & 0xfc000001) == 0x48000001)
1717 { /* bl foo,
0df8b418 1718 to save fprs??? */
c906108c 1719
c5aa993b 1720 fdata->frameless = 0;
3c77c82a
DJ		 1721
1722 /* If the return address has already been saved, we can skip
1723 calls to blrl (for PIC). */
e17a4113 1724 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op, byte_order))
46a9b8ed
DJ		 1725 {
1726 fdata->used_bl = 1;
1727 continue;
1728 }
3c77c82a 1729
6be8bc0c 1730 /* Don't skip over the subroutine call if it is not within
ebd98106
FF		 1731 the first three instructions of the prologue and either
1732 we have no line table information or the line info tells
1733 us that the subroutine call is not part of the line
1734 associated with the prologue. */
c5aa993b 1735 if ((pc - orig_pc) > 8)
ebd98106
FF		 1736 {
1737 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1738 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1739
0df8b418
MS		 1740 if ((prologue_sal.line == 0)
1741 || (prologue_sal.line != this_sal.line))
ebd98106
FF		 1742 break;
1743 }
c5aa993b 1744
e17a4113 1745 op = read_memory_integer (pc + 4, 4, byte_order);
c5aa993b 1746
6be8bc0c
EZ		 1747 /* At this point, make sure this is not a trampoline
1748 function (a function that simply calls another functions,
1749 and nothing else). If the next is not a nop, this branch
0df8b418 1750 was part of the function prologue. */
c5aa993b
JM		 1751
1752 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
0df8b418
MS		 1753 break; /* Don't skip over
1754 this branch. */
c5aa993b 1755
46a9b8ed
DJ		 1756 fdata->used_bl = 1;
1757 continue;
c5aa993b 1758 }
98f08d3d
KB		 1759 /* update stack pointer */
1760 else if ((op & 0xfc1f0000) == 0x94010000)
1761 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
c5aa993b
JM		 1762 fdata->frameless = 0;
1763 fdata->offset = SIGNED_SHORT (op);
1764 offset = fdata->offset;
1765 continue;
c5aa993b 1766 }
98f08d3d
KB		 1767 else if ((op & 0xfc1f016a) == 0x7c01016e)
1768 { /* stwux rX,r1,rY */
0df8b418 1769 /* No way to figure out what r1 is going to be. */
98f08d3d
KB		 1770 fdata->frameless = 0;
1771 offset = fdata->offset;
1772 continue;
1773 }
1774 else if ((op & 0xfc1f0003) == 0xf8010001)
1775 { /* stdu rX,NUM(r1) */
1776 fdata->frameless = 0;
1777 fdata->offset = SIGNED_SHORT (op & ~3UL);
1778 offset = fdata->offset;
1779 continue;
1780 }
1781 else if ((op & 0xfc1f016a) == 0x7c01016a)
1782 { /* stdux rX,r1,rY */
0df8b418 1783 /* No way to figure out what r1 is going to be. */
c5aa993b
JM		 1784 fdata->frameless = 0;
1785 offset = fdata->offset;
1786 continue;
c5aa993b 1787 }
7313566f
FF		 1788 else if ((op & 0xffff0000) == 0x38210000)
1789 { /* addi r1,r1,SIMM */
1790 fdata->frameless = 0;
1791 fdata->offset += SIGNED_SHORT (op);
1792 offset = fdata->offset;
1793 continue;
1794 }
4e463ff5
DJ		 1795 /* Load up minimal toc pointer. Do not treat an epilogue restore
1796 of r31 as a minimal TOC load. */
0df8b418
MS		 1797 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1798 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
4e463ff5 1799 && !framep
c5aa993b 1800 && !minimal_toc_loaded)
98f08d3d 1801 {
c5aa993b
JM		 1802 minimal_toc_loaded = 1;
1803 continue;
1804
f6077098
KB		 1805 /* move parameters from argument registers to local variable
1806 registers */
1807 }
1808 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1809 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1810 (((op >> 21) & 31) <= 10) &&
0df8b418
MS		 1811 ((long) ((op >> 16) & 31)
1812 >= fdata->saved_gpr)) /* Rx: local var reg */
f6077098
KB		 1813 {
1814 continue;
1815
c5aa993b
JM		 1816 /* store parameters in stack */
1817 }
e802b915 1818 /* Move parameters from argument registers to temporary register. */
773df3e5 1819 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
e802b915 1820 {
c5aa993b
JM		 1821 continue;
1822
1823 /* Set up frame pointer */
1824 }
1825 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1826 || op == 0x7c3f0b78)
1827 { /* mr r31, r1 */
1828 fdata->frameless = 0;
1829 framep = 1;
6f99cb26 1830 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
c5aa993b
JM		 1831 continue;
1832
1833 /* Another way to set up the frame pointer. */
1834 }
1835 else if ((op & 0xfc1fffff) == 0x38010000)
1836 { /* addi rX, r1, 0x0 */
1837 fdata->frameless = 0;
1838 framep = 1;
6f99cb26
AC		 1839 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1840 + ((op & ~0x38010000) >> 21));
c5aa993b 1841 continue;
c5aa993b 1842 }
6be8bc0c
EZ		 1843 /* AltiVec related instructions. */
1844 /* Store the vrsave register (spr 256) in another register for
1845 later manipulation, or load a register into the vrsave
1846 register. 2 instructions are used: mfvrsave and
1847 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1848 and mtspr SPR256, Rn. */
1849 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1850 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1851 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1852 {
1853 vrsave_reg = GET_SRC_REG (op);
1854 continue;
1855 }
1856 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1857 {
1858 continue;
1859 }
1860 /* Store the register where vrsave was saved to onto the stack:
1861 rS is the register where vrsave was stored in a previous
1862 instruction. */
1863 /* 100100 sssss 00001 dddddddd dddddddd */
1864 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1865 {
1866 if (vrsave_reg == GET_SRC_REG (op))
1867 {
1868 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1869 vrsave_reg = -1;
1870 }
1871 continue;
1872 }
1873 /* Compute the new value of vrsave, by modifying the register
1874 where vrsave was saved to. */
1875 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1876 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1877 {
1878 continue;
1879 }
1880 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1881 in a pair of insns to save the vector registers on the
1882 stack. */
1883 /* 001110 00000 00000 iiii iiii iiii iiii */
96ff0de4
EZ		 1884 /* 001110 01110 00000 iiii iiii iiii iiii */
1885 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1886 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
6be8bc0c 1887 {
773df3e5
JB		 1888 if ((op & 0xffff0000) == 0x38000000)
1889 r0_contains_arg = 0;
6be8bc0c
EZ		 1890 li_found_pc = pc;
1891 vr_saved_offset = SIGNED_SHORT (op);
773df3e5
JB		 1892
1893 /* This insn by itself is not part of the prologue, unless
0df8b418 1894 if part of the pair of insns mentioned above. So do not
773df3e5
JB		 1895 record this insn as part of the prologue yet. */
1896 prev_insn_was_prologue_insn = 0;
6be8bc0c
EZ		 1897 }
1898 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1899 /* 011111 sssss 11111 00000 00111001110 */
1900 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1901 {
1902 if (pc == (li_found_pc + 4))
1903 {
1904 vr_reg = GET_SRC_REG (op);
1905 /* If this is the first vector reg to be saved, or if
1906 it has a lower number than others previously seen,
1907 reupdate the frame info. */
1908 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1909 {
1910 fdata->saved_vr = vr_reg;
1911 fdata->vr_offset = vr_saved_offset + offset;
1912 }
1913 vr_saved_offset = -1;
1914 vr_reg = -1;
1915 li_found_pc = 0;
1916 }
1917 }
1918 /* End AltiVec related instructions. */
96ff0de4
EZ		 1919
1920 /* Start BookE related instructions. */
1921 /* Store gen register S at (r31+uimm).
1922 Any register less than r13 is volatile, so we don't care. */
1923 /* 000100 sssss 11111 iiiii 01100100001 */
1924 else if (arch_info->mach == bfd_mach_ppc_e500
1925 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1926 {
1927 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1928 {
1929 unsigned int imm;
1930 ev_reg = GET_SRC_REG (op);
1931 imm = (op >> 11) & 0x1f;
1932 ev_offset = imm * 8;
1933 /* If this is the first vector reg to be saved, or if
1934 it has a lower number than others previously seen,
1935 reupdate the frame info. */
1936 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1937 {
1938 fdata->saved_ev = ev_reg;
1939 fdata->ev_offset = ev_offset + offset;
1940 }
1941 }
1942 continue;
1943 }
1944 /* Store gen register rS at (r1+rB). */
1945 /* 000100 sssss 00001 bbbbb 01100100000 */
1946 else if (arch_info->mach == bfd_mach_ppc_e500
1947 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1948 {
1949 if (pc == (li_found_pc + 4))
1950 {
1951 ev_reg = GET_SRC_REG (op);
1952 /* If this is the first vector reg to be saved, or if
1953 it has a lower number than others previously seen,
1954 reupdate the frame info. */
1955 /* We know the contents of rB from the previous instruction. */
1956 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1957 {
1958 fdata->saved_ev = ev_reg;
1959 fdata->ev_offset = vr_saved_offset + offset;
1960 }
1961 vr_saved_offset = -1;
1962 ev_reg = -1;
1963 li_found_pc = 0;
1964 }
1965 continue;
1966 }
1967 /* Store gen register r31 at (rA+uimm). */
1968 /* 000100 11111 aaaaa iiiii 01100100001 */
1969 else if (arch_info->mach == bfd_mach_ppc_e500
1970 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1971 {
1972 /* Wwe know that the source register is 31 already, but
1973 it can't hurt to compute it. */
1974 ev_reg = GET_SRC_REG (op);
1975 ev_offset = ((op >> 11) & 0x1f) * 8;
1976 /* If this is the first vector reg to be saved, or if
1977 it has a lower number than others previously seen,
1978 reupdate the frame info. */
1979 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1980 {
1981 fdata->saved_ev = ev_reg;
1982 fdata->ev_offset = ev_offset + offset;
1983 }
1984
1985 continue;
1986 }
1987 /* Store gen register S at (r31+r0).
1988 Store param on stack when offset from SP bigger than 4 bytes. */
1989 /* 000100 sssss 11111 00000 01100100000 */
1990 else if (arch_info->mach == bfd_mach_ppc_e500
1991 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1992 {
1993 if (pc == (li_found_pc + 4))
1994 {
1995 if ((op & 0x03e00000) >= 0x01a00000)
1996 {
1997 ev_reg = GET_SRC_REG (op);
1998 /* If this is the first vector reg to be saved, or if
1999 it has a lower number than others previously seen,
2000 reupdate the frame info. */
2001 /* We know the contents of r0 from the previous
2002 instruction. */
2003 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
2004 {
2005 fdata->saved_ev = ev_reg;
2006 fdata->ev_offset = vr_saved_offset + offset;
2007 }
2008 ev_reg = -1;
2009 }
2010 vr_saved_offset = -1;
2011 li_found_pc = 0;
2012 continue;
2013 }
2014 }
2015 /* End BookE related instructions. */
2016
c5aa993b
JM		 2017 else
2018 {
46a9b8ed
DJ		 2019 unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1);
2020
55d05f3b
KB		 2021 /* Not a recognized prologue instruction.
2022 Handle optimizer code motions into the prologue by continuing
2023 the search if we have no valid frame yet or if the return
46a9b8ed
DJ		 2024 address is not yet saved in the frame. Also skip instructions
2025 if some of the GPRs expected to be saved are not yet saved. */
2026 if (fdata->frameless == 0 && fdata->nosavedpc == 0
2027 && (fdata->gpr_mask & all_mask) == all_mask)
55d05f3b
KB		 2028 break;
2029
2030 if (op == 0x4e800020 /* blr */
2031 || op == 0x4e800420) /* bctr */
2032 /* Do not scan past epilogue in frameless functions or
2033 trampolines. */
2034 break;
2035 if ((op & 0xf4000000) == 0x40000000) /* bxx */
64366f1c 2036 /* Never skip branches. */
55d05f3b
KB		 2037 break;
2038
2039 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
2040 /* Do not scan too many insns, scanning insns is expensive with
2041 remote targets. */
2042 break;
2043
2044 /* Continue scanning. */
2045 prev_insn_was_prologue_insn = 0;
2046 continue;
c5aa993b 2047 }
c906108c
SS		 2048 }
2049
2050#if 0
2051/* I have problems with skipping over __main() that I need to address
0df8b418 2052 * sometime. Previously, I used to use misc_function_vector which
c906108c
SS		 2053 * didn't work as well as I wanted to be. -MGO */
2054
2055 /* If the first thing after skipping a prolog is a branch to a function,
2056 this might be a call to an initializer in main(), introduced by gcc2.
64366f1c 2057 We'd like to skip over it as well. Fortunately, xlc does some extra
c906108c 2058 work before calling a function right after a prologue, thus we can
64366f1c 2059 single out such gcc2 behaviour. */
c906108c 2060
c906108c 2061
c5aa993b 2062 if ((op & 0xfc000001) == 0x48000001)
0df8b418 2063 { /* bl foo, an initializer function? */
e17a4113 2064 op = read_memory_integer (pc + 4, 4, byte_order);
c5aa993b
JM		 2065
2066 if (op == 0x4def7b82)
2067 { /* cror 0xf, 0xf, 0xf (nop) */
c906108c 2068
64366f1c
EZ		 2069 /* Check and see if we are in main. If so, skip over this
2070 initializer function as well. */
c906108c 2071
c5aa993b 2072 tmp = find_pc_misc_function (pc);
6314a349
AC		 2073 if (tmp >= 0
2074 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
c5aa993b
JM		 2075 return pc + 8;
2076 }
c906108c 2077 }
c906108c 2078#endif /* 0 */
c5aa993b 2079
46a9b8ed
DJ		 2080 if (pc == lim_pc && lr_reg >= 0)
2081 fdata->lr_register = lr_reg;
2082
c5aa993b 2083 fdata->offset = -fdata->offset;
ddb20c56 2084 return last_prologue_pc;
c906108c
SS		 2085}
2086
7a78ae4e 2087static CORE_ADDR
4a7622d1 2088rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
c906108c 2089{
4a7622d1 2090 struct rs6000_framedata frame;
e3acb115 2091 CORE_ADDR limit_pc, func_addr, func_end_addr = 0;
c906108c 2092
4a7622d1
UW		 2093 /* See if we can determine the end of the prologue via the symbol table.
2094 If so, then return either PC, or the PC after the prologue, whichever
2095 is greater. */
e3acb115 2096 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr))
c5aa993b 2097 {
d80b854b
UW		 2098 CORE_ADDR post_prologue_pc
2099 = skip_prologue_using_sal (gdbarch, func_addr);
4a7622d1
UW		 2100 if (post_prologue_pc != 0)
2101 return max (pc, post_prologue_pc);
c906108c 2102 }
c906108c 2103
4a7622d1
UW		 2104 /* Can't determine prologue from the symbol table, need to examine
2105 instructions. */
c906108c 2106
4a7622d1
UW		 2107 /* Find an upper limit on the function prologue using the debug
2108 information. If the debug information could not be used to provide
2109 that bound, then use an arbitrary large number as the upper bound. */
d80b854b 2110 limit_pc = skip_prologue_using_sal (gdbarch, pc);
4a7622d1
UW		 2111 if (limit_pc == 0)
2112 limit_pc = pc + 100; /* Magic. */
794a477a 2113
e3acb115
JB		 2114 /* Do not allow limit_pc to be past the function end, if we know
2115 where that end is... */
2116 if (func_end_addr && limit_pc > func_end_addr)
2117 limit_pc = func_end_addr;
2118
4a7622d1
UW		 2119 pc = skip_prologue (gdbarch, pc, limit_pc, &frame);
2120 return pc;
c906108c 2121}
c906108c 2122
8ab3d180
KB		 2123/* When compiling for EABI, some versions of GCC emit a call to __eabi
2124 in the prologue of main().
2125
2126 The function below examines the code pointed at by PC and checks to
2127 see if it corresponds to a call to __eabi. If so, it returns the
2128 address of the instruction following that call. Otherwise, it simply
2129 returns PC. */
2130
63807e1d 2131static CORE_ADDR
8ab3d180
KB		 2132rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2133{
e17a4113 2134 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8ab3d180
KB		 2135 gdb_byte buf[4];
2136 unsigned long op;
2137
2138 if (target_read_memory (pc, buf, 4))
2139 return pc;
e17a4113 2140 op = extract_unsigned_integer (buf, 4, byte_order);
8ab3d180
KB		 2141
2142 if ((op & BL_MASK) == BL_INSTRUCTION)
2143 {
2144 CORE_ADDR displ = op & BL_DISPLACEMENT_MASK;
2145 CORE_ADDR call_dest = pc + 4 + displ;
2146 struct minimal_symbol *s = lookup_minimal_symbol_by_pc (call_dest);
2147
2148 /* We check for ___eabi (three leading underscores) in addition
2149 to __eabi in case the GCC option "-fleading-underscore" was
2150 used to compile the program. */
2151 if (s != NULL
2152 && SYMBOL_LINKAGE_NAME (s) != NULL
2153 && (strcmp (SYMBOL_LINKAGE_NAME (s), "__eabi") == 0
2154 || strcmp (SYMBOL_LINKAGE_NAME (s), "___eabi") == 0))
2155 pc += 4;
2156 }
2157 return pc;
2158}
383f0f5b 2159
4a7622d1
UW		 2160/* All the ABI's require 16 byte alignment. */
2161static CORE_ADDR
2162rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2163{
2164 return (addr & -16);
c906108c
SS		 2165}
2166
977adac5
ND		 2167/* Return whether handle_inferior_event() should proceed through code
2168 starting at PC in function NAME when stepping.
2169
2170 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2171 handle memory references that are too distant to fit in instructions
2172 generated by the compiler. For example, if 'foo' in the following
2173 instruction:
2174
2175 lwz r9,foo(r2)
2176
2177 is greater than 32767, the linker might replace the lwz with a branch to
2178 somewhere in @FIX1 that does the load in 2 instructions and then branches
2179 back to where execution should continue.
2180
2181 GDB should silently step over @FIX code, just like AIX dbx does.
2ec664f5
MS		 2182 Unfortunately, the linker uses the "b" instruction for the
2183 branches, meaning that the link register doesn't get set.
2184 Therefore, GDB's usual step_over_function () mechanism won't work.
977adac5 2185
e76f05fa
UW		 2186 Instead, use the gdbarch_skip_trampoline_code and
2187 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2ec664f5 2188 @FIX code. */
977adac5 2189
63807e1d 2190static int
e17a4113
UW		 2191rs6000_in_solib_return_trampoline (struct gdbarch *gdbarch,
2192 CORE_ADDR pc, char *name)
977adac5
ND		 2193{
2194 return name && !strncmp (name, "@FIX", 4);
2195}
2196
2197/* Skip code that the user doesn't want to see when stepping:
2198
2199 1. Indirect function calls use a piece of trampoline code to do context
2200 switching, i.e. to set the new TOC table. Skip such code if we are on
2201 its first instruction (as when we have single-stepped to here).
2202
2203 2. Skip shared library trampoline code (which is different from
c906108c 2204 indirect function call trampolines).
977adac5
ND		 2205
2206 3. Skip bigtoc fixup code.
2207
c906108c 2208 Result is desired PC to step until, or NULL if we are not in
977adac5 2209 code that should be skipped. */
c906108c 2210
63807e1d 2211static CORE_ADDR
52f729a7 2212rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
c906108c 2213{
e17a4113
UW		 2214 struct gdbarch *gdbarch = get_frame_arch (frame);
2215 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2216 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
52f0bd74 2217 unsigned int ii, op;
977adac5 2218 int rel;
c906108c 2219 CORE_ADDR solib_target_pc;
977adac5 2220 struct minimal_symbol *msymbol;
c906108c 2221
c5aa993b
JM		 2222 static unsigned trampoline_code[] =
2223 {
2224 0x800b0000, /* l r0,0x0(r11) */
2225 0x90410014, /* st r2,0x14(r1) */
2226 0x7c0903a6, /* mtctr r0 */
2227 0x804b0004, /* l r2,0x4(r11) */
2228 0x816b0008, /* l r11,0x8(r11) */
2229 0x4e800420, /* bctr */
2230 0x4e800020, /* br */
2231 0
c906108c
SS		 2232 };
2233
977adac5
ND		 2234 /* Check for bigtoc fixup code. */
2235 msymbol = lookup_minimal_symbol_by_pc (pc);
2ec664f5 2236 if (msymbol
e17a4113
UW		 2237 && rs6000_in_solib_return_trampoline (gdbarch, pc,
2238 SYMBOL_LINKAGE_NAME (msymbol)))
977adac5
ND		 2239 {
2240 /* Double-check that the third instruction from PC is relative "b". */
e17a4113 2241 op = read_memory_integer (pc + 8, 4, byte_order);
977adac5
ND		 2242 if ((op & 0xfc000003) == 0x48000000)
2243 {
2244 /* Extract bits 6-29 as a signed 24-bit relative word address and
2245 add it to the containing PC. */
2246 rel = ((int)(op << 6) >> 6);
2247 return pc + 8 + rel;
2248 }
2249 }
2250
c906108c 2251 /* If pc is in a shared library trampoline, return its target. */
52f729a7 2252 solib_target_pc = find_solib_trampoline_target (frame, pc);
c906108c
SS		 2253 if (solib_target_pc)
2254 return solib_target_pc;
2255
c5aa993b
JM		 2256 for (ii = 0; trampoline_code[ii]; ++ii)
2257 {
e17a4113 2258 op = read_memory_integer (pc + (ii * 4), 4, byte_order);
c5aa993b
JM		 2259 if (op != trampoline_code[ii])
2260 return 0;
2261 }
0df8b418
MS		 2262 ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination
2263 addr. */
e17a4113 2264 pc = read_memory_unsigned_integer (ii, tdep->wordsize, byte_order);
c906108c
SS		 2265 return pc;
2266}
2267
794ac428
UW		 2268/* ISA-specific vector types. */
2269
2270static struct type *
2271rs6000_builtin_type_vec64 (struct gdbarch *gdbarch)
2272{
2273 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2274
2275 if (!tdep->ppc_builtin_type_vec64)
2276 {
df4df182
UW		 2277 const struct builtin_type *bt = builtin_type (gdbarch);
2278
794ac428
UW		 2279 /* The type we're building is this: */
2280#if 0
2281 union __gdb_builtin_type_vec64
2282 {
2283 int64_t uint64;
2284 float v2_float[2];
2285 int32_t v2_int32[2];
2286 int16_t v4_int16[4];
2287 int8_t v8_int8[8];
2288 };
2289#endif
2290
2291 struct type *t;
2292
e9bb382b
UW		 2293 t = arch_composite_type (gdbarch,
2294 "__ppc_builtin_type_vec64", TYPE_CODE_UNION);
df4df182 2295 append_composite_type_field (t, "uint64", bt->builtin_int64);
794ac428 2296 append_composite_type_field (t, "v2_float",
df4df182 2297 init_vector_type (bt->builtin_float, 2));
794ac428 2298 append_composite_type_field (t, "v2_int32",
df4df182 2299 init_vector_type (bt->builtin_int32, 2));
794ac428 2300 append_composite_type_field (t, "v4_int16",
df4df182 2301 init_vector_type (bt->builtin_int16, 4));
794ac428 2302 append_composite_type_field (t, "v8_int8",
df4df182 2303 init_vector_type (bt->builtin_int8, 8));
794ac428 2304
876cecd0 2305 TYPE_VECTOR (t) = 1;
794ac428
UW		 2306 TYPE_NAME (t) = "ppc_builtin_type_vec64";
2307 tdep->ppc_builtin_type_vec64 = t;
2308 }
2309
2310 return tdep->ppc_builtin_type_vec64;
2311}
2312
604c2f83
LM		 2313/* Vector 128 type. */
2314
2315static struct type *
2316rs6000_builtin_type_vec128 (struct gdbarch *gdbarch)
2317{
2318 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2319
2320 if (!tdep->ppc_builtin_type_vec128)
2321 {
df4df182
UW		 2322 const struct builtin_type *bt = builtin_type (gdbarch);
2323
604c2f83
LM		 2324 /* The type we're building is this
2325
2326 type = union __ppc_builtin_type_vec128 {
2327 uint128_t uint128;
db9f5df8 2328 double v2_double[2];
604c2f83
LM		 2329 float v4_float[4];
2330 int32_t v4_int32[4];
2331 int16_t v8_int16[8];
2332 int8_t v16_int8[16];
2333 }
2334 */
2335
2336 struct type *t;
2337
e9bb382b
UW		 2338 t = arch_composite_type (gdbarch,
2339 "__ppc_builtin_type_vec128", TYPE_CODE_UNION);
df4df182 2340 append_composite_type_field (t, "uint128", bt->builtin_uint128);
db9f5df8
UW		 2341 append_composite_type_field (t, "v2_double",
2342 init_vector_type (bt->builtin_double, 2));
604c2f83 2343 append_composite_type_field (t, "v4_float",
df4df182 2344 init_vector_type (bt->builtin_float, 4));
604c2f83 2345 append_composite_type_field (t, "v4_int32",
df4df182 2346 init_vector_type (bt->builtin_int32, 4));
604c2f83 2347 append_composite_type_field (t, "v8_int16",
df4df182 2348 init_vector_type (bt->builtin_int16, 8));
604c2f83 2349 append_composite_type_field (t, "v16_int8",
df4df182 2350 init_vector_type (bt->builtin_int8, 16));
604c2f83 2351
803e1097 2352 TYPE_VECTOR (t) = 1;
604c2f83
LM		 2353 TYPE_NAME (t) = "ppc_builtin_type_vec128";
2354 tdep->ppc_builtin_type_vec128 = t;
2355 }
2356
2357 return tdep->ppc_builtin_type_vec128;
2358}
2359
7cc46491
DJ		 2360/* Return the name of register number REGNO, or the empty string if it
2361 is an anonymous register. */
7a78ae4e 2362
fa88f677 2363static const char *
d93859e2 2364rs6000_register_name (struct gdbarch *gdbarch, int regno)
7a78ae4e 2365{
d93859e2 2366 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7a78ae4e 2367
7cc46491
DJ		 2368 /* The upper half "registers" have names in the XML description,
2369 but we present only the low GPRs and the full 64-bit registers
2370 to the user. */
2371 if (tdep->ppc_ev0_upper_regnum >= 0
2372 && tdep->ppc_ev0_upper_regnum <= regno
2373 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
2374 return "";
2375
604c2f83
LM		 2376 /* Hide the upper halves of the vs0~vs31 registers. */
2377 if (tdep->ppc_vsr0_regnum >= 0
2378 && tdep->ppc_vsr0_upper_regnum <= regno
2379 && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs)
2380 return "";
2381
7cc46491 2382 /* Check if the SPE pseudo registers are available. */
5a9e69ba 2383 if (IS_SPE_PSEUDOREG (tdep, regno))
7cc46491
DJ		 2384 {
2385 static const char *const spe_regnames[] = {
2386 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2387 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2388 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2389 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2390 };
2391 return spe_regnames[regno - tdep->ppc_ev0_regnum];
2392 }
2393
f949c649
TJB		 2394 /* Check if the decimal128 pseudo-registers are available. */
2395 if (IS_DFP_PSEUDOREG (tdep, regno))
2396 {
2397 static const char *const dfp128_regnames[] = {
2398 "dl0", "dl1", "dl2", "dl3",
2399 "dl4", "dl5", "dl6", "dl7",
2400 "dl8", "dl9", "dl10", "dl11",
2401 "dl12", "dl13", "dl14", "dl15"
2402 };
2403 return dfp128_regnames[regno - tdep->ppc_dl0_regnum];
2404 }
2405
604c2f83
LM		 2406 /* Check if this is a VSX pseudo-register. */
2407 if (IS_VSX_PSEUDOREG (tdep, regno))
2408 {
2409 static const char *const vsx_regnames[] = {
2410 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2411 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2412 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2413 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2414 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2415 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2416 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2417 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2418 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2419 };
2420 return vsx_regnames[regno - tdep->ppc_vsr0_regnum];
2421 }
2422
2423 /* Check if the this is a Extended FP pseudo-register. */
2424 if (IS_EFP_PSEUDOREG (tdep, regno))
2425 {
2426 static const char *const efpr_regnames[] = {
2427 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2428 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2429 "f46", "f47", "f48", "f49", "f50", "f51",
2430 "f52", "f53", "f54", "f55", "f56", "f57",
2431 "f58", "f59", "f60", "f61", "f62", "f63"
2432 };
2433 return efpr_regnames[regno - tdep->ppc_efpr0_regnum];
2434 }
2435
d93859e2 2436 return tdesc_register_name (gdbarch, regno);
7a78ae4e
ND		 2437}
2438
7cc46491
DJ		 2439/* Return the GDB type object for the "standard" data type of data in
2440 register N. */
7a78ae4e
ND		 2441
2442static struct type *
7cc46491 2443rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
7a78ae4e 2444{
691d145a 2445 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7a78ae4e 2446
7cc46491 2447 /* These are the only pseudo-registers we support. */
f949c649 2448 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
604c2f83
LM		 2449 || IS_DFP_PSEUDOREG (tdep, regnum)
2450 || IS_VSX_PSEUDOREG (tdep, regnum)
2451 || IS_EFP_PSEUDOREG (tdep, regnum));
7cc46491 2452
f949c649
TJB		 2453 /* These are the e500 pseudo-registers. */
2454 if (IS_SPE_PSEUDOREG (tdep, regnum))
2455 return rs6000_builtin_type_vec64 (gdbarch);
604c2f83
LM		 2456 else if (IS_DFP_PSEUDOREG (tdep, regnum))
2457 /* PPC decimal128 pseudo-registers. */
f949c649 2458 return builtin_type (gdbarch)->builtin_declong;
604c2f83
LM		 2459 else if (IS_VSX_PSEUDOREG (tdep, regnum))
2460 /* POWER7 VSX pseudo-registers. */
2461 return rs6000_builtin_type_vec128 (gdbarch);
2462 else
2463 /* POWER7 Extended FP pseudo-registers. */
2464 return builtin_type (gdbarch)->builtin_double;
7a78ae4e
ND		 2465}
2466
c44ca51c
AC		 2467/* Is REGNUM a member of REGGROUP? */
2468static int
7cc46491
DJ		 2469rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2470 struct reggroup *group)
c44ca51c
AC		 2471{
2472 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
c44ca51c 2473
7cc46491 2474 /* These are the only pseudo-registers we support. */
f949c649 2475 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
604c2f83
LM		 2476 || IS_DFP_PSEUDOREG (tdep, regnum)
2477 || IS_VSX_PSEUDOREG (tdep, regnum)
2478 || IS_EFP_PSEUDOREG (tdep, regnum));
c44ca51c 2479
604c2f83
LM		 2480 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2481 if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum))
f949c649 2482 return group == all_reggroup || group == vector_reggroup;
7cc46491 2483 else
604c2f83 2484 /* PPC decimal128 or Extended FP pseudo-registers. */
f949c649 2485 return group == all_reggroup || group == float_reggroup;
c44ca51c
AC		 2486}
2487
691d145a 2488/* The register format for RS/6000 floating point registers is always
64366f1c 2489 double, we need a conversion if the memory format is float. */
7a78ae4e
ND		 2490
2491static int
0abe36f5
MD		 2492rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum,
2493 struct type *type)
7a78ae4e 2494{
0abe36f5 2495 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7cc46491
DJ		 2496
2497 return (tdep->ppc_fp0_regnum >= 0
2498 && regnum >= tdep->ppc_fp0_regnum
2499 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs
2500 && TYPE_CODE (type) == TYPE_CODE_FLT
0dfff4cb
UW		 2501 && TYPE_LENGTH (type)
2502 != TYPE_LENGTH (builtin_type (gdbarch)->builtin_double));
7a78ae4e
ND		 2503}
2504
8dccd430 2505static int
691d145a
JB		 2506rs6000_register_to_value (struct frame_info *frame,
2507 int regnum,
2508 struct type *type,
8dccd430
PA		 2509 gdb_byte *to,
2510 int *optimizedp, int *unavailablep)
7a78ae4e 2511{
0dfff4cb 2512 struct gdbarch *gdbarch = get_frame_arch (frame);
50fd1280 2513 gdb_byte from[MAX_REGISTER_SIZE];
691d145a 2514
691d145a 2515 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
7a78ae4e 2516
8dccd430
PA		 2517 if (!get_frame_register_bytes (frame, regnum, 0,
2518 register_size (gdbarch, regnum),
2519 from, optimizedp, unavailablep))
2520 return 0;
2521
0dfff4cb
UW		 2522 convert_typed_floating (from, builtin_type (gdbarch)->builtin_double,
2523 to, type);
8dccd430
PA		 2524 *optimizedp = *unavailablep = 0;
2525 return 1;
691d145a 2526}
7a292a7a 2527
7a78ae4e 2528static void
691d145a
JB		 2529rs6000_value_to_register (struct frame_info *frame,
2530 int regnum,
2531 struct type *type,
50fd1280 2532 const gdb_byte *from)
7a78ae4e 2533{
0dfff4cb 2534 struct gdbarch *gdbarch = get_frame_arch (frame);
50fd1280 2535 gdb_byte to[MAX_REGISTER_SIZE];
691d145a 2536
691d145a
JB		 2537 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2538
0dfff4cb
UW		 2539 convert_typed_floating (from, type,
2540 to, builtin_type (gdbarch)->builtin_double);
691d145a 2541 put_frame_register (frame, regnum, to);
7a78ae4e 2542}
c906108c 2543
05d1431c
PA		 2544 /* The type of a function that moves the value of REG between CACHE
2545 or BUF --- in either direction. */
2546typedef enum register_status (*move_ev_register_func) (struct regcache *,
2547 int, void *);
2548
6ced10dd
JB		 2549/* Move SPE vector register values between a 64-bit buffer and the two
2550 32-bit raw register halves in a regcache. This function handles
2551 both splitting a 64-bit value into two 32-bit halves, and joining
2552 two halves into a whole 64-bit value, depending on the function
2553 passed as the MOVE argument.
2554
2555 EV_REG must be the number of an SPE evN vector register --- a
2556 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2557 64-bit buffer.
2558
2559 Call MOVE once for each 32-bit half of that register, passing
2560 REGCACHE, the number of the raw register corresponding to that
2561 half, and the address of the appropriate half of BUFFER.
2562
2563 For example, passing 'regcache_raw_read' as the MOVE function will
2564 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2565 'regcache_raw_supply' will supply the contents of BUFFER to the
2566 appropriate pair of raw registers in REGCACHE.
2567
2568 You may need to cast away some 'const' qualifiers when passing
2569 MOVE, since this function can't tell at compile-time which of
2570 REGCACHE or BUFFER is acting as the source of the data. If C had
2571 co-variant type qualifiers, ... */
05d1431c
PA		 2572
2573static enum register_status
2574e500_move_ev_register (move_ev_register_func move,
2575 struct regcache *regcache, int ev_reg, void *buffer)
6ced10dd
JB		 2576{
2577 struct gdbarch *arch = get_regcache_arch (regcache);
2578 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2579 int reg_index;
50fd1280 2580 gdb_byte *byte_buffer = buffer;
05d1431c 2581 enum register_status status;
6ced10dd 2582
5a9e69ba 2583 gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg));
6ced10dd
JB		 2584
2585 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2586
8b164abb 2587 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
6ced10dd 2588 {
05d1431c
PA		 2589 status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index,
2590 byte_buffer);
2591 if (status == REG_VALID)
2592 status = move (regcache, tdep->ppc_gp0_regnum + reg_index,
2593 byte_buffer + 4);
6ced10dd
JB		 2594 }
2595 else
2596 {
05d1431c
PA		 2597 status = move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2598 if (status == REG_VALID)
2599 status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index,
2600 byte_buffer + 4);
6ced10dd 2601 }
05d1431c
PA		 2602
2603 return status;
6ced10dd
JB		 2604}
2605
05d1431c
PA		 2606static enum register_status
2607do_regcache_raw_read (struct regcache *regcache, int regnum, void *buffer)
2608{
2609 return regcache_raw_read (regcache, regnum, buffer);
2610}
2611
2612static enum register_status
2613do_regcache_raw_write (struct regcache *regcache, int regnum, void *buffer)
2614{
2615 regcache_raw_write (regcache, regnum, buffer);
2616
2617 return REG_VALID;
2618}
2619
2620static enum register_status
c8001721 2621e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
50fd1280 2622 int reg_nr, gdb_byte *buffer)
f949c649 2623{
05d1431c 2624 return e500_move_ev_register (do_regcache_raw_read, regcache, reg_nr, buffer);
f949c649
TJB		 2625}
2626
2627static void
2628e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2629 int reg_nr, const gdb_byte *buffer)
2630{
05d1431c
PA		 2631 e500_move_ev_register (do_regcache_raw_write, regcache,
2632 reg_nr, (void *) buffer);
f949c649
TJB		 2633}
2634
604c2f83 2635/* Read method for DFP pseudo-registers. */
05d1431c 2636static enum register_status
604c2f83 2637dfp_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
f949c649
TJB		 2638 int reg_nr, gdb_byte *buffer)
2639{
2640 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2641 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
05d1431c 2642 enum register_status status;
f949c649
TJB		 2643
2644 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2645 {
2646 /* Read two FP registers to form a whole dl register. */
05d1431c
PA		 2647 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2648 2 * reg_index, buffer);
2649 if (status == REG_VALID)
2650 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2651 2 * reg_index + 1, buffer + 8);
f949c649
TJB		 2652 }
2653 else
2654 {
05d1431c
PA		 2655 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2656 2 * reg_index + 1, buffer + 8);
2657 if (status == REG_VALID)
2658 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2659 2 * reg_index, buffer);
f949c649 2660 }
05d1431c
PA		 2661
2662 return status;
f949c649
TJB		 2663}
2664
604c2f83 2665/* Write method for DFP pseudo-registers. */
f949c649 2666static void
604c2f83 2667dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
f949c649
TJB		 2668 int reg_nr, const gdb_byte *buffer)
2669{
2670 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2671 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2672
2673 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2674 {
2675 /* Write each half of the dl register into a separate
2676 FP register. */
2677 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2678 2 * reg_index, buffer);
2679 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2680 2 * reg_index + 1, buffer + 8);
2681 }
2682 else
2683 {
2684 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2685 2 * reg_index + 1, buffer + 8);
2686 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2687 2 * reg_index, buffer);
2688 }
2689}
2690
604c2f83 2691/* Read method for POWER7 VSX pseudo-registers. */
05d1431c 2692static enum register_status
604c2f83
LM		 2693vsx_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2694 int reg_nr, gdb_byte *buffer)
2695{
2696 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2697 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
05d1431c 2698 enum register_status status;
604c2f83
LM		 2699
2700 /* Read the portion that overlaps the VMX registers. */
2701 if (reg_index > 31)
05d1431c
PA		 2702 status = regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2703 reg_index - 32, buffer);
604c2f83
LM		 2704 else
2705 /* Read the portion that overlaps the FPR registers. */
2706 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2707 {
05d1431c
PA		 2708 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2709 reg_index, buffer);
2710 if (status == REG_VALID)
2711 status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2712 reg_index, buffer + 8);
604c2f83
LM		 2713 }
2714 else
2715 {
05d1431c
PA		 2716 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2717 reg_index, buffer + 8);
2718 if (status == REG_VALID)
2719 status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2720 reg_index, buffer);
604c2f83 2721 }
05d1431c
PA		 2722
2723 return status;
604c2f83
LM		 2724}
2725
2726/* Write method for POWER7 VSX pseudo-registers. */
2727static void
2728vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2729 int reg_nr, const gdb_byte *buffer)
2730{
2731 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2732 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2733
2734 /* Write the portion that overlaps the VMX registers. */
2735 if (reg_index > 31)
2736 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2737 reg_index - 32, buffer);
2738 else
2739 /* Write the portion that overlaps the FPR registers. */
2740 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2741 {
2742 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2743 reg_index, buffer);
2744 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2745 reg_index, buffer + 8);
2746 }
2747 else
2748 {
2749 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2750 reg_index, buffer + 8);
2751 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2752 reg_index, buffer);
2753 }
2754}
2755
2756/* Read method for POWER7 Extended FP pseudo-registers. */
05d1431c 2757static enum register_status
604c2f83
LM		 2758efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2759 int reg_nr, gdb_byte *buffer)
2760{
2761 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2762 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2763
d9492458 2764 /* Read the portion that overlaps the VMX register. */
05d1431c
PA		 2765 return regcache_raw_read_part (regcache, tdep->ppc_vr0_regnum + reg_index, 0,
2766 register_size (gdbarch, reg_nr), buffer);
604c2f83
LM		 2767}
2768
2769/* Write method for POWER7 Extended FP pseudo-registers. */
2770static void
2771efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2772 int reg_nr, const gdb_byte *buffer)
2773{
2774 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2775 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2776
d9492458
TJB		 2777 /* Write the portion that overlaps the VMX register. */
2778 regcache_raw_write_part (regcache, tdep->ppc_vr0_regnum + reg_index, 0,
2779 register_size (gdbarch, reg_nr), buffer);
604c2f83
LM		 2780}
2781
05d1431c 2782static enum register_status
0df8b418
MS		 2783rs6000_pseudo_register_read (struct gdbarch *gdbarch,
2784 struct regcache *regcache,
f949c649 2785 int reg_nr, gdb_byte *buffer)
c8001721 2786{
6ced10dd 2787 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
c8001721
EZ		 2788 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2789
6ced10dd 2790 gdb_assert (regcache_arch == gdbarch);
f949c649 2791
5a9e69ba 2792 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
05d1431c 2793 return e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
f949c649 2794 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
05d1431c 2795 return dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
604c2f83 2796 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
05d1431c 2797 return vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
604c2f83 2798 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
05d1431c 2799 return efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
6ced10dd 2800 else
a44bddec 2801 internal_error (__FILE__, __LINE__,
f949c649
TJB		 2802 _("rs6000_pseudo_register_read: "
2803 "called on unexpected register '%s' (%d)"),
2804 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
c8001721
EZ		 2805}
2806
2807static void
f949c649
TJB		 2808rs6000_pseudo_register_write (struct gdbarch *gdbarch,
2809 struct regcache *regcache,
2810 int reg_nr, const gdb_byte *buffer)
c8001721 2811{
6ced10dd 2812 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
c8001721
EZ		 2813 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2814
6ced10dd 2815 gdb_assert (regcache_arch == gdbarch);
f949c649 2816
5a9e69ba 2817 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
f949c649
TJB		 2818 e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2819 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
604c2f83
LM		 2820 dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2821 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2822 vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2823 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2824 efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
6ced10dd 2825 else
a44bddec 2826 internal_error (__FILE__, __LINE__,
f949c649
TJB		 2827 _("rs6000_pseudo_register_write: "
2828 "called on unexpected register '%s' (%d)"),
2829 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
6ced10dd
JB		 2830}
2831
18ed0c4e 2832/* Convert a DBX STABS register number to a GDB register number. */
c8001721 2833static int
d3f73121 2834rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
c8001721 2835{
d3f73121 2836 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
c8001721 2837
9f744501
JB		 2838 if (0 <= num && num <= 31)
2839 return tdep->ppc_gp0_regnum + num;
2840 else if (32 <= num && num <= 63)
383f0f5b
JB		 2841 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2842 specifies registers the architecture doesn't have? Our
2843 callers don't check the value we return. */
366f009f 2844 return tdep->ppc_fp0_regnum + (num - 32);
18ed0c4e
JB		 2845 else if (77 <= num && num <= 108)
2846 return tdep->ppc_vr0_regnum + (num - 77);
9f744501
JB		 2847 else if (1200 <= num && num < 1200 + 32)
2848 return tdep->ppc_ev0_regnum + (num - 1200);
2849 else
2850 switch (num)
2851 {
2852 case 64:
2853 return tdep->ppc_mq_regnum;
2854 case 65:
2855 return tdep->ppc_lr_regnum;
2856 case 66:
2857 return tdep->ppc_ctr_regnum;
2858 case 76:
2859 return tdep->ppc_xer_regnum;
2860 case 109:
2861 return tdep->ppc_vrsave_regnum;
18ed0c4e
JB		 2862 case 110:
2863 return tdep->ppc_vrsave_regnum - 1; /* vscr */
867e2dc5 2864 case 111:
18ed0c4e 2865 return tdep->ppc_acc_regnum;
867e2dc5 2866 case 112:
18ed0c4e 2867 return tdep->ppc_spefscr_regnum;
9f744501
JB		 2868 default:
2869 return num;
2870 }
18ed0c4e 2871}
9f744501 2872
9f744501 2873
18ed0c4e
JB		 2874/* Convert a Dwarf 2 register number to a GDB register number. */
2875static int
d3f73121 2876rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
18ed0c4e 2877{
d3f73121 2878 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9f744501 2879
18ed0c4e
JB		 2880 if (0 <= num && num <= 31)
2881 return tdep->ppc_gp0_regnum + num;
2882 else if (32 <= num && num <= 63)
2883 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2884 specifies registers the architecture doesn't have? Our
2885 callers don't check the value we return. */
2886 return tdep->ppc_fp0_regnum + (num - 32);
2887 else if (1124 <= num && num < 1124 + 32)
2888 return tdep->ppc_vr0_regnum + (num - 1124);
2889 else if (1200 <= num && num < 1200 + 32)
2890 return tdep->ppc_ev0_regnum + (num - 1200);
2891 else
2892 switch (num)
2893 {
a489f789
AS		 2894 case 64:
2895 return tdep->ppc_cr_regnum;
18ed0c4e
JB		 2896 case 67:
2897 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2898 case 99:
2899 return tdep->ppc_acc_regnum;
2900 case 100:
2901 return tdep->ppc_mq_regnum;
2902 case 101:
2903 return tdep->ppc_xer_regnum;
2904 case 108:
2905 return tdep->ppc_lr_regnum;
2906 case 109:
2907 return tdep->ppc_ctr_regnum;
2908 case 356:
2909 return tdep->ppc_vrsave_regnum;
2910 case 612:
2911 return tdep->ppc_spefscr_regnum;
2912 default:
2913 return num;
2914 }
2188cbdd
EZ		 2915}
2916
4fc771b8
DJ		 2917/* Translate a .eh_frame register to DWARF register, or adjust a
2918 .debug_frame register. */
2919
2920static int
2921rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
2922{
2923 /* GCC releases before 3.4 use GCC internal register numbering in
2924 .debug_frame (and .debug_info, et cetera). The numbering is
2925 different from the standard SysV numbering for everything except
2926 for GPRs and FPRs. We can not detect this problem in most cases
2927 - to get accurate debug info for variables living in lr, ctr, v0,
2928 et cetera, use a newer version of GCC. But we must detect
2929 one important case - lr is in column 65 in .debug_frame output,
2930 instead of 108.
2931
2932 GCC 3.4, and the "hammer" branch, have a related problem. They
2933 record lr register saves in .debug_frame as 108, but still record
2934 the return column as 65. We fix that up too.
2935
2936 We can do this because 65 is assigned to fpsr, and GCC never
2937 generates debug info referring to it. To add support for
2938 handwritten debug info that restores fpsr, we would need to add a
2939 producer version check to this. */
2940 if (!eh_frame_p)
2941 {
2942 if (num == 65)
2943 return 108;
2944 else
2945 return num;
2946 }
2947
2948 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2949 internal register numbering; translate that to the standard DWARF2
2950 register numbering. */
2951 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */
2952 return num;
2953 else if (68 <= num && num <= 75) /* cr0-cr8 */
2954 return num - 68 + 86;
2955 else if (77 <= num && num <= 108) /* vr0-vr31 */
2956 return num - 77 + 1124;
2957 else
2958 switch (num)
2959 {
2960 case 64: /* mq */
2961 return 100;
2962 case 65: /* lr */
2963 return 108;
2964 case 66: /* ctr */
2965 return 109;
2966 case 76: /* xer */
2967 return 101;
2968 case 109: /* vrsave */
2969 return 356;
2970 case 110: /* vscr */
2971 return 67;
2972 case 111: /* spe_acc */
2973 return 99;
2974 case 112: /* spefscr */
2975 return 612;
2976 default:
2977 return num;
2978 }
2979}
c906108c 2980\f
c5aa993b 2981
7a78ae4e 2982/* Handling the various POWER/PowerPC variants. */
c906108c 2983
c906108c 2984/* Information about a particular processor variant. */
7a78ae4e 2985
c906108c 2986struct variant
c5aa993b
JM		 2987 {
2988 /* Name of this variant. */
2989 char *name;
c906108c 2990
c5aa993b
JM		 2991 /* English description of the variant. */
2992 char *description;
c906108c 2993
64366f1c 2994 /* bfd_arch_info.arch corresponding to variant. */
7a78ae4e
ND		 2995 enum bfd_architecture arch;
2996
64366f1c 2997 /* bfd_arch_info.mach corresponding to variant. */
7a78ae4e
ND		 2998 unsigned long mach;
2999
7cc46491
DJ		 3000 /* Target description for this variant. */
3001 struct target_desc **tdesc;
c5aa993b 3002 };
c906108c 3003
489461e2 3004static struct variant variants[] =
c906108c 3005{
7a78ae4e 3006 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
7284e1be 3007 bfd_mach_ppc, &tdesc_powerpc_altivec32},
7a78ae4e 3008 {"power", "POWER user-level", bfd_arch_rs6000,
7cc46491 3009 bfd_mach_rs6k, &tdesc_rs6000},
7a78ae4e 3010 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
7cc46491 3011 bfd_mach_ppc_403, &tdesc_powerpc_403},
4d09ffea
MS		 3012 {"405", "IBM PowerPC 405", bfd_arch_powerpc,
3013 bfd_mach_ppc_405, &tdesc_powerpc_405},
7a78ae4e 3014 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
7cc46491 3015 bfd_mach_ppc_601, &tdesc_powerpc_601},
7a78ae4e 3016 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
7cc46491 3017 bfd_mach_ppc_602, &tdesc_powerpc_602},
7a78ae4e 3018 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
7cc46491 3019 bfd_mach_ppc_603, &tdesc_powerpc_603},
7a78ae4e 3020 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
7cc46491 3021 604, &tdesc_powerpc_604},
7a78ae4e 3022 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
7cc46491 3023 bfd_mach_ppc_403gc, &tdesc_powerpc_403gc},
7a78ae4e 3024 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
7cc46491 3025 bfd_mach_ppc_505, &tdesc_powerpc_505},
7a78ae4e 3026 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
7cc46491 3027 bfd_mach_ppc_860, &tdesc_powerpc_860},
7a78ae4e 3028 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
7cc46491 3029 bfd_mach_ppc_750, &tdesc_powerpc_750},
1fcc0bb8 3030 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
7cc46491 3031 bfd_mach_ppc_7400, &tdesc_powerpc_7400},
c8001721 3032 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
7cc46491 3033 bfd_mach_ppc_e500, &tdesc_powerpc_e500},
7a78ae4e 3034
5d57ee30
KB		 3035 /* 64-bit */
3036 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
7284e1be 3037 bfd_mach_ppc64, &tdesc_powerpc_altivec64},
7a78ae4e 3038 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
7cc46491 3039 bfd_mach_ppc_620, &tdesc_powerpc_64},
5d57ee30 3040 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
7cc46491 3041 bfd_mach_ppc_630, &tdesc_powerpc_64},
7a78ae4e 3042 {"a35", "PowerPC A35", bfd_arch_powerpc,
7cc46491 3043 bfd_mach_ppc_a35, &tdesc_powerpc_64},
5d57ee30 3044 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
7cc46491 3045 bfd_mach_ppc_rs64ii, &tdesc_powerpc_64},
5d57ee30 3046 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
7cc46491 3047 bfd_mach_ppc_rs64iii, &tdesc_powerpc_64},
5d57ee30 3048
64366f1c 3049 /* FIXME: I haven't checked the register sets of the following. */
7a78ae4e 3050 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
7cc46491 3051 bfd_mach_rs6k_rs1, &tdesc_rs6000},
7a78ae4e 3052 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
7cc46491 3053 bfd_mach_rs6k_rsc, &tdesc_rs6000},
7a78ae4e 3054 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
7cc46491 3055 bfd_mach_rs6k_rs2, &tdesc_rs6000},
7a78ae4e 3056
7cc46491 3057 {0, 0, 0, 0, 0}
c906108c
SS		 3058};
3059
7a78ae4e 3060/* Return the variant corresponding to architecture ARCH and machine number
64366f1c 3061 MACH. If no such variant exists, return null. */
c906108c 3062
7a78ae4e
ND		 3063static const struct variant *
3064find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
c906108c 3065{
7a78ae4e 3066 const struct variant *v;
c5aa993b 3067
7a78ae4e
ND		 3068 for (v = variants; v->name; v++)
3069 if (arch == v->arch && mach == v->mach)
3070 return v;
c906108c 3071
7a78ae4e 3072 return NULL;
c906108c 3073}
9364a0ef
EZ		 3074
3075static int
3076gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
3077{
ee4f0f76 3078 if (!info->disassembler_options)
e52d5016
NF		 3079 {
3080 /* When debugging E500 binaries and disassembling code containing
3081 E500-specific (SPE) instructions, one sometimes sees AltiVec
3082 instructions instead. The opcode spaces for SPE instructions
3083 and AltiVec instructions overlap, and specifiying the "any" cpu
3084 looks for AltiVec instructions first. If we know we're
3085 debugging an E500 binary, however, we can specify the "e500x2"
3086 cpu and get much more sane disassembly output. */
3087 if (info->mach == bfd_mach_ppc_e500)
3088 info->disassembler_options = "e500x2";
3089 else
3090 info->disassembler_options = "any";
3091 }
ee4f0f76 3092
40887e1a 3093 if (info->endian == BFD_ENDIAN_BIG)
9364a0ef
EZ		 3094 return print_insn_big_powerpc (memaddr, info);
3095 else
3096 return print_insn_little_powerpc (memaddr, info);
3097}
7a78ae4e 3098\f
61a65099
KB		 3099static CORE_ADDR
3100rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
3101{
3e8c568d 3102 return frame_unwind_register_unsigned (next_frame,
8b164abb 3103 gdbarch_pc_regnum (gdbarch));
61a65099
KB		 3104}
3105
3106static struct frame_id
1af5d7ce 3107rs6000_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
61a65099 3108{
1af5d7ce
UW		 3109 return frame_id_build (get_frame_register_unsigned
3110 (this_frame, gdbarch_sp_regnum (gdbarch)),
3111 get_frame_pc (this_frame));
61a65099
KB		 3112}
3113
3114struct rs6000_frame_cache
3115{
3116 CORE_ADDR base;
3117 CORE_ADDR initial_sp;
3118 struct trad_frame_saved_reg *saved_regs;
3119};
3120
3121static struct rs6000_frame_cache *
1af5d7ce 3122rs6000_frame_cache (struct frame_info *this_frame, void **this_cache)
61a65099
KB		 3123{
3124 struct rs6000_frame_cache *cache;
1af5d7ce 3125 struct gdbarch *gdbarch = get_frame_arch (this_frame);
61a65099 3126 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 3127 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
61a65099
KB		 3128 struct rs6000_framedata fdata;
3129 int wordsize = tdep->wordsize;
e10b1c4c 3130 CORE_ADDR func, pc;
61a65099
KB		 3131
3132 if ((*this_cache) != NULL)
3133 return (*this_cache);
3134 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
3135 (*this_cache) = cache;
1af5d7ce 3136 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
61a65099 3137
1af5d7ce
UW		 3138 func = get_frame_func (this_frame);
3139 pc = get_frame_pc (this_frame);
be8626e0 3140 skip_prologue (gdbarch, func, pc, &fdata);
e10b1c4c
DJ		 3141
3142 /* Figure out the parent's stack pointer. */
3143
3144 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3145 address of the current frame. Things might be easier if the
3146 ->frame pointed to the outer-most address of the frame. In
3147 the mean time, the address of the prev frame is used as the
3148 base address of this frame. */
1af5d7ce
UW		 3149 cache->base = get_frame_register_unsigned
3150 (this_frame, gdbarch_sp_regnum (gdbarch));
e10b1c4c
DJ		 3151
3152 /* If the function appears to be frameless, check a couple of likely
3153 indicators that we have simply failed to find the frame setup.
3154 Two common cases of this are missing symbols (i.e.
ef02daa9 3155 get_frame_func returns the wrong address or 0), and assembly
e10b1c4c
DJ		 3156 stubs which have a fast exit path but set up a frame on the slow
3157 path.
3158
3159 If the LR appears to return to this function, then presume that
3160 we have an ABI compliant frame that we failed to find. */
3161 if (fdata.frameless && fdata.lr_offset == 0)
61a65099 3162 {
e10b1c4c
DJ		 3163 CORE_ADDR saved_lr;
3164 int make_frame = 0;
3165
1af5d7ce 3166 saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum);
e10b1c4c
DJ		 3167 if (func == 0 && saved_lr == pc)
3168 make_frame = 1;
3169 else if (func != 0)
3170 {
3171 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
3172 if (func == saved_func)
3173 make_frame = 1;
3174 }
3175
3176 if (make_frame)
3177 {
3178 fdata.frameless = 0;
de6a76fd 3179 fdata.lr_offset = tdep->lr_frame_offset;
e10b1c4c 3180 }
61a65099 3181 }
e10b1c4c
DJ		 3182
3183 if (!fdata.frameless)
3184 /* Frameless really means stackless. */
e17a4113
UW		 3185 cache->base
3186 = read_memory_unsigned_integer (cache->base, wordsize, byte_order);
e10b1c4c 3187
3e8c568d 3188 trad_frame_set_value (cache->saved_regs,
8b164abb 3189 gdbarch_sp_regnum (gdbarch), cache->base);
61a65099
KB		 3190
3191 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3192 All fpr's from saved_fpr to fp31 are saved. */
3193
3194 if (fdata.saved_fpr >= 0)
3195 {
3196 int i;
3197 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
383f0f5b
JB		 3198
3199 /* If skip_prologue says floating-point registers were saved,
3200 but the current architecture has no floating-point registers,
3201 then that's strange. But we have no indices to even record
3202 the addresses under, so we just ignore it. */
3203 if (ppc_floating_point_unit_p (gdbarch))
063715bf 3204 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
383f0f5b
JB		 3205 {
3206 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3207 fpr_addr += 8;
3208 }
61a65099
KB		 3209 }
3210
3211 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
46a9b8ed
DJ		 3212 All gpr's from saved_gpr to gpr31 are saved (except during the
3213 prologue). */
61a65099
KB		 3214
3215 if (fdata.saved_gpr >= 0)
3216 {
3217 int i;
3218 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
063715bf 3219 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
61a65099 3220 {
46a9b8ed
DJ		 3221 if (fdata.gpr_mask & (1U << i))
3222 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
61a65099
KB		 3223 gpr_addr += wordsize;
3224 }
3225 }
3226
3227 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3228 All vr's from saved_vr to vr31 are saved. */
3229 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3230 {
3231 if (fdata.saved_vr >= 0)
3232 {
3233 int i;
3234 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3235 for (i = fdata.saved_vr; i < 32; i++)
3236 {
3237 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3238 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3239 }
3240 }
3241 }
3242
3243 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
0df8b418 3244 All vr's from saved_ev to ev31 are saved. ????? */
5a9e69ba 3245 if (tdep->ppc_ev0_regnum != -1)
61a65099
KB		 3246 {
3247 if (fdata.saved_ev >= 0)
3248 {
3249 int i;
3250 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
063715bf 3251 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
61a65099
KB		 3252 {
3253 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3254 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
3255 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3256 }
3257 }
3258 }
3259
3260 /* If != 0, fdata.cr_offset is the offset from the frame that
3261 holds the CR. */
3262 if (fdata.cr_offset != 0)
0df8b418
MS		 3263 cache->saved_regs[tdep->ppc_cr_regnum].addr
3264 = cache->base + fdata.cr_offset;
61a65099
KB		 3265
3266 /* If != 0, fdata.lr_offset is the offset from the frame that
3267 holds the LR. */
3268 if (fdata.lr_offset != 0)
0df8b418
MS		 3269 cache->saved_regs[tdep->ppc_lr_regnum].addr
3270 = cache->base + fdata.lr_offset;
46a9b8ed
DJ		 3271 else if (fdata.lr_register != -1)
3272 cache->saved_regs[tdep->ppc_lr_regnum].realreg = fdata.lr_register;
61a65099 3273 /* The PC is found in the link register. */
8b164abb 3274 cache->saved_regs[gdbarch_pc_regnum (gdbarch)] =
3e8c568d 3275 cache->saved_regs[tdep->ppc_lr_regnum];
61a65099
KB		 3276
3277 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3278 holds the VRSAVE. */
3279 if (fdata.vrsave_offset != 0)
0df8b418
MS		 3280 cache->saved_regs[tdep->ppc_vrsave_regnum].addr
3281 = cache->base + fdata.vrsave_offset;
61a65099
KB		 3282
3283 if (fdata.alloca_reg < 0)
3284 /* If no alloca register used, then fi->frame is the value of the
3285 %sp for this frame, and it is good enough. */
1af5d7ce
UW		 3286 cache->initial_sp
3287 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
61a65099 3288 else
1af5d7ce
UW		 3289 cache->initial_sp
3290 = get_frame_register_unsigned (this_frame, fdata.alloca_reg);
61a65099
KB		 3291
3292 return cache;
3293}
3294
3295static void
1af5d7ce 3296rs6000_frame_this_id (struct frame_info *this_frame, void **this_cache,
61a65099
KB		 3297 struct frame_id *this_id)
3298{
1af5d7ce 3299 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099 3300 this_cache);
5b197912
UW		 3301 /* This marks the outermost frame. */
3302 if (info->base == 0)
3303 return;
3304
1af5d7ce 3305 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
61a65099
KB		 3306}
3307
1af5d7ce
UW		 3308static struct value *
3309rs6000_frame_prev_register (struct frame_info *this_frame,
3310 void **this_cache, int regnum)
61a65099 3311{
1af5d7ce 3312 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099 3313 this_cache);
1af5d7ce 3314 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
61a65099
KB		 3315}
3316
3317static const struct frame_unwind rs6000_frame_unwind =
3318{
3319 NORMAL_FRAME,
8fbca658 3320 default_frame_unwind_stop_reason,
61a65099 3321 rs6000_frame_this_id,
1af5d7ce
UW		 3322 rs6000_frame_prev_register,
3323 NULL,
3324 default_frame_sniffer
61a65099 3325};
61a65099
KB		 3326\f
3327
3328static CORE_ADDR
1af5d7ce 3329rs6000_frame_base_address (struct frame_info *this_frame, void **this_cache)
61a65099 3330{
1af5d7ce 3331 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099
KB		 3332 this_cache);
3333 return info->initial_sp;
3334}
3335
3336static const struct frame_base rs6000_frame_base = {
3337 &rs6000_frame_unwind,
3338 rs6000_frame_base_address,
3339 rs6000_frame_base_address,
3340 rs6000_frame_base_address
3341};
3342
3343static const struct frame_base *
1af5d7ce 3344rs6000_frame_base_sniffer (struct frame_info *this_frame)
61a65099
KB		 3345{
3346 return &rs6000_frame_base;
3347}
3348
9274a07c
LM		 3349/* DWARF-2 frame support. Used to handle the detection of
3350 clobbered registers during function calls. */
3351
3352static void
3353ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3354 struct dwarf2_frame_state_reg *reg,
4a4e5149 3355 struct frame_info *this_frame)
9274a07c
LM		 3356{
3357 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3358
3359 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3360 non-volatile registers. We will use the same code for both. */
3361
3362 /* Call-saved GP registers. */
3363 if ((regnum >= tdep->ppc_gp0_regnum + 14
3364 && regnum <= tdep->ppc_gp0_regnum + 31)
3365 || (regnum == tdep->ppc_gp0_regnum + 1))
3366 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3367
3368 /* Call-clobbered GP registers. */
3369 if ((regnum >= tdep->ppc_gp0_regnum + 3
3370 && regnum <= tdep->ppc_gp0_regnum + 12)
3371 || (regnum == tdep->ppc_gp0_regnum))
3372 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3373
3374 /* Deal with FP registers, if supported. */
3375 if (tdep->ppc_fp0_regnum >= 0)
3376 {
3377 /* Call-saved FP registers. */
3378 if ((regnum >= tdep->ppc_fp0_regnum + 14
3379 && regnum <= tdep->ppc_fp0_regnum + 31))
3380 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3381
3382 /* Call-clobbered FP registers. */
3383 if ((regnum >= tdep->ppc_fp0_regnum
3384 && regnum <= tdep->ppc_fp0_regnum + 13))
3385 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3386 }
3387
3388 /* Deal with ALTIVEC registers, if supported. */
3389 if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0)
3390 {
3391 /* Call-saved Altivec registers. */
3392 if ((regnum >= tdep->ppc_vr0_regnum + 20
3393 && regnum <= tdep->ppc_vr0_regnum + 31)
3394 || regnum == tdep->ppc_vrsave_regnum)
3395 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3396
3397 /* Call-clobbered Altivec registers. */
3398 if ((regnum >= tdep->ppc_vr0_regnum
3399 && regnum <= tdep->ppc_vr0_regnum + 19))
3400 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3401 }
3402
3403 /* Handle PC register and Stack Pointer correctly. */
40a6adc1 3404 if (regnum == gdbarch_pc_regnum (gdbarch))
9274a07c 3405 reg->how = DWARF2_FRAME_REG_RA;
40a6adc1 3406 else if (regnum == gdbarch_sp_regnum (gdbarch))
9274a07c
LM		 3407 reg->how = DWARF2_FRAME_REG_CFA;
3408}
3409
3410
74af9197
NF		 3411/* Return true if a .gnu_attributes section exists in BFD and it
3412 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3413 section exists in BFD and it indicates that SPE extensions are in
3414 use. Check the .gnu.attributes section first, as the binary might be
3415 compiled for SPE, but not actually using SPE instructions. */
3416
3417static int
3418bfd_uses_spe_extensions (bfd *abfd)
3419{
3420 asection *sect;
3421 gdb_byte *contents = NULL;
3422 bfd_size_type size;
3423 gdb_byte *ptr;
3424 int success = 0;
3425 int vector_abi;
3426
3427 if (!abfd)
3428 return 0;
3429
50a99728 3430#ifdef HAVE_ELF
74af9197
NF		 3431 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3432 could be using the SPE vector abi without actually using any spe
3433 bits whatsoever. But it's close enough for now. */
3434 vector_abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_GNU,
3435 Tag_GNU_Power_ABI_Vector);
3436 if (vector_abi == 3)
3437 return 1;
50a99728 3438#endif
74af9197
NF		 3439
3440 sect = bfd_get_section_by_name (abfd, ".PPC.EMB.apuinfo");
3441 if (!sect)
3442 return 0;
3443
3444 size = bfd_get_section_size (sect);
3445 contents = xmalloc (size);
3446 if (!bfd_get_section_contents (abfd, sect, contents, 0, size))
3447 {
3448 xfree (contents);
3449 return 0;
3450 }
3451
3452 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3453
3454 struct {
3455 uint32 name_len;
3456 uint32 data_len;
3457 uint32 type;
3458 char name[name_len rounded up to 4-byte alignment];
3459 char data[data_len];
3460 };
3461
3462 Technically, there's only supposed to be one such structure in a
3463 given apuinfo section, but the linker is not always vigilant about
3464 merging apuinfo sections from input files. Just go ahead and parse
3465 them all, exiting early when we discover the binary uses SPE
3466 insns.
3467
3468 It's not specified in what endianness the information in this
3469 section is stored. Assume that it's the endianness of the BFD. */
3470 ptr = contents;
3471 while (1)
3472 {
3473 unsigned int name_len;
3474 unsigned int data_len;
3475 unsigned int type;
3476
3477 /* If we can't read the first three fields, we're done. */
3478 if (size < 12)
3479 break;
3480
3481 name_len = bfd_get_32 (abfd, ptr);
3482 name_len = (name_len + 3) & ~3U; /* Round to 4 bytes. */
3483 data_len = bfd_get_32 (abfd, ptr + 4);
3484 type = bfd_get_32 (abfd, ptr + 8);
3485 ptr += 12;
3486
3487 /* The name must be "APUinfo\0". */
3488 if (name_len != 8
3489 && strcmp ((const char *) ptr, "APUinfo") != 0)
3490 break;
3491 ptr += name_len;
3492
3493 /* The type must be 2. */
3494 if (type != 2)
3495 break;
3496
3497 /* The data is stored as a series of uint32. The upper half of
3498 each uint32 indicates the particular APU used and the lower
3499 half indicates the revision of that APU. We just care about
3500 the upper half. */
3501
3502 /* Not 4-byte quantities. */
3503 if (data_len & 3U)
3504 break;
3505
3506 while (data_len)
3507 {
3508 unsigned int apuinfo = bfd_get_32 (abfd, ptr);
3509 unsigned int apu = apuinfo >> 16;
3510 ptr += 4;
3511 data_len -= 4;
3512
3513 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3514 either. */
3515 if (apu == 0x100 || apu == 0x101)
3516 {
3517 success = 1;
3518 data_len = 0;
3519 }
3520 }
3521
3522 if (success)
3523 break;
3524 }
3525
3526 xfree (contents);
3527 return success;
3528}
3529
7a78ae4e
ND		 3530/* Initialize the current architecture based on INFO. If possible, re-use an
3531 architecture from ARCHES, which is a list of architectures already created
3532 during this debugging session.
c906108c 3533
7a78ae4e 3534 Called e.g. at program startup, when reading a core file, and when reading
64366f1c 3535 a binary file. */
c906108c 3536
7a78ae4e
ND		 3537static struct gdbarch *
3538rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3539{
3540 struct gdbarch *gdbarch;
3541 struct gdbarch_tdep *tdep;
7cc46491 3542 int wordsize, from_xcoff_exec, from_elf_exec;
7a78ae4e
ND		 3543 enum bfd_architecture arch;
3544 unsigned long mach;
3545 bfd abfd;
5bf1c677 3546 asection *sect;
55eddb0f
DJ		 3547 enum auto_boolean soft_float_flag = powerpc_soft_float_global;
3548 int soft_float;
3549 enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
604c2f83
LM		 3550 int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0,
3551 have_vsx = 0;
7cc46491
DJ		 3552 int tdesc_wordsize = -1;
3553 const struct target_desc *tdesc = info.target_desc;
3554 struct tdesc_arch_data *tdesc_data = NULL;
f949c649 3555 int num_pseudoregs = 0;
604c2f83 3556 int cur_reg;
7a78ae4e 3557
f4d9bade
UW		 3558 /* INFO may refer to a binary that is not of the PowerPC architecture,
3559 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
3560 In this case, we must not attempt to infer properties of the (PowerPC
3561 side) of the target system from properties of that executable. Trust
3562 the target description instead. */
3563 if (info.abfd
3564 && bfd_get_arch (info.abfd) != bfd_arch_powerpc
3565 && bfd_get_arch (info.abfd) != bfd_arch_rs6000)
3566 info.abfd = NULL;
3567
9aa1e687 3568 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
7a78ae4e
ND		 3569 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3570
9aa1e687
KB		 3571 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3572 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3573
e712c1cf 3574 /* Check word size. If INFO is from a binary file, infer it from
64366f1c 3575 that, else choose a likely default. */
9aa1e687 3576 if (from_xcoff_exec)
c906108c 3577 {
11ed25ac 3578 if (bfd_xcoff_is_xcoff64 (info.abfd))
7a78ae4e
ND		 3579 wordsize = 8;
3580 else
3581 wordsize = 4;
c906108c 3582 }
9aa1e687
KB		 3583 else if (from_elf_exec)
3584 {
3585 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3586 wordsize = 8;
3587 else
3588 wordsize = 4;
3589 }
7cc46491
DJ		 3590 else if (tdesc_has_registers (tdesc))
3591 wordsize = -1;
c906108c 3592 else
7a78ae4e 3593 {
27b15785
KB		 3594 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3595 wordsize = info.bfd_arch_info->bits_per_word /
3596 info.bfd_arch_info->bits_per_byte;
3597 else
3598 wordsize = 4;
7a78ae4e 3599 }
c906108c 3600
475bbd17
JB		 3601 /* Get the architecture and machine from the BFD. */
3602 arch = info.bfd_arch_info->arch;
3603 mach = info.bfd_arch_info->mach;
5bf1c677
EZ		 3604
3605 /* For e500 executables, the apuinfo section is of help here. Such
3606 section contains the identifier and revision number of each
3607 Application-specific Processing Unit that is present on the
3608 chip. The content of the section is determined by the assembler
3609 which looks at each instruction and determines which unit (and
74af9197
NF		 3610 which version of it) can execute it. Grovel through the section
3611 looking for relevant e500 APUs. */
5bf1c677 3612
74af9197 3613 if (bfd_uses_spe_extensions (info.abfd))
5bf1c677 3614 {
74af9197
NF		 3615 arch = info.bfd_arch_info->arch;
3616 mach = bfd_mach_ppc_e500;
3617 bfd_default_set_arch_mach (&abfd, arch, mach);
3618 info.bfd_arch_info = bfd_get_arch_info (&abfd);
5bf1c677
EZ		 3619 }
3620
7cc46491
DJ		 3621 /* Find a default target description which describes our register
3622 layout, if we do not already have one. */
3623 if (! tdesc_has_registers (tdesc))
3624 {
3625 const struct variant *v;
3626
3627 /* Choose variant. */
3628 v = find_variant_by_arch (arch, mach);
3629 if (!v)
3630 return NULL;
3631
3632 tdesc = *v->tdesc;
3633 }
3634
3635 gdb_assert (tdesc_has_registers (tdesc));
3636
3637 /* Check any target description for validity. */
3638 if (tdesc_has_registers (tdesc))
3639 {
3640 static const char *const gprs[] = {
3641 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3642 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3643 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3644 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3645 };
3646 static const char *const segment_regs[] = {
3647 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
3648 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
3649 };
3650 const struct tdesc_feature *feature;
3651 int i, valid_p;
3652 static const char *const msr_names[] = { "msr", "ps" };
3653 static const char *const cr_names[] = { "cr", "cnd" };
3654 static const char *const ctr_names[] = { "ctr", "cnt" };
3655
3656 feature = tdesc_find_feature (tdesc,
3657 "org.gnu.gdb.power.core");
3658 if (feature == NULL)
3659 return NULL;
3660
3661 tdesc_data = tdesc_data_alloc ();
3662
3663 valid_p = 1;
3664 for (i = 0; i < ppc_num_gprs; i++)
3665 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]);
3666 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM,
3667 "pc");
3668 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM,
3669 "lr");
3670 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM,
3671 "xer");
3672
3673 /* Allow alternate names for these registers, to accomodate GDB's
3674 historic naming. */
3675 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3676 PPC_MSR_REGNUM, msr_names);
3677 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3678 PPC_CR_REGNUM, cr_names);
3679 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3680 PPC_CTR_REGNUM, ctr_names);
3681
3682 if (!valid_p)
3683 {
3684 tdesc_data_cleanup (tdesc_data);
3685 return NULL;
3686 }
3687
3688 have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM,
3689 "mq");
3690
3691 tdesc_wordsize = tdesc_register_size (feature, "pc") / 8;
3692 if (wordsize == -1)
3693 wordsize = tdesc_wordsize;
3694
3695 feature = tdesc_find_feature (tdesc,
3696 "org.gnu.gdb.power.fpu");
3697 if (feature != NULL)
3698 {
3699 static const char *const fprs[] = {
3700 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
3701 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
3702 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
3703 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
3704 };
3705 valid_p = 1;
3706 for (i = 0; i < ppc_num_fprs; i++)
3707 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3708 PPC_F0_REGNUM + i, fprs[i]);
3709 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3710 PPC_FPSCR_REGNUM, "fpscr");
3711
3712 if (!valid_p)
3713 {
3714 tdesc_data_cleanup (tdesc_data);
3715 return NULL;
3716 }
3717 have_fpu = 1;
3718 }
3719 else
3720 have_fpu = 0;
3721
f949c649
TJB		 3722 /* The DFP pseudo-registers will be available when there are floating
3723 point registers. */
3724 have_dfp = have_fpu;
3725
7cc46491
DJ		 3726 feature = tdesc_find_feature (tdesc,
3727 "org.gnu.gdb.power.altivec");
3728 if (feature != NULL)
3729 {
3730 static const char *const vector_regs[] = {
3731 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
3732 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
3733 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
3734 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
3735 };
3736
3737 valid_p = 1;
3738 for (i = 0; i < ppc_num_gprs; i++)
3739 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3740 PPC_VR0_REGNUM + i,
3741 vector_regs[i]);
3742 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3743 PPC_VSCR_REGNUM, "vscr");
3744 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3745 PPC_VRSAVE_REGNUM, "vrsave");
3746
3747 if (have_spe || !valid_p)
3748 {
3749 tdesc_data_cleanup (tdesc_data);
3750 return NULL;
3751 }
3752 have_altivec = 1;
3753 }
3754 else
3755 have_altivec = 0;
3756
604c2f83
LM		 3757 /* Check for POWER7 VSX registers support. */
3758 feature = tdesc_find_feature (tdesc,
3759 "org.gnu.gdb.power.vsx");
3760
3761 if (feature != NULL)
3762 {
3763 static const char *const vsx_regs[] = {
3764 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
3765 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
3766 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
3767 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
3768 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
3769 "vs30h", "vs31h"
3770 };
3771
3772 valid_p = 1;
3773
3774 for (i = 0; i < ppc_num_vshrs; i++)
3775 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3776 PPC_VSR0_UPPER_REGNUM + i,
3777 vsx_regs[i]);
3778 if (!valid_p)
3779 {
3780 tdesc_data_cleanup (tdesc_data);
3781 return NULL;
3782 }
3783
3784 have_vsx = 1;
3785 }
3786 else
3787 have_vsx = 0;
3788
7cc46491
DJ		 3789 /* On machines supporting the SPE APU, the general-purpose registers
3790 are 64 bits long. There are SIMD vector instructions to treat them
3791 as pairs of floats, but the rest of the instruction set treats them
3792 as 32-bit registers, and only operates on their lower halves.
3793
3794 In the GDB regcache, we treat their high and low halves as separate
3795 registers. The low halves we present as the general-purpose
3796 registers, and then we have pseudo-registers that stitch together
3797 the upper and lower halves and present them as pseudo-registers.
3798
3799 Thus, the target description is expected to supply the upper
3800 halves separately. */
3801
3802 feature = tdesc_find_feature (tdesc,
3803 "org.gnu.gdb.power.spe");
3804 if (feature != NULL)
3805 {
3806 static const char *const upper_spe[] = {
3807 "ev0h", "ev1h", "ev2h", "ev3h",
3808 "ev4h", "ev5h", "ev6h", "ev7h",
3809 "ev8h", "ev9h", "ev10h", "ev11h",
3810 "ev12h", "ev13h", "ev14h", "ev15h",
3811 "ev16h", "ev17h", "ev18h", "ev19h",
3812 "ev20h", "ev21h", "ev22h", "ev23h",
3813 "ev24h", "ev25h", "ev26h", "ev27h",
3814 "ev28h", "ev29h", "ev30h", "ev31h"
3815 };
3816
3817 valid_p = 1;
3818 for (i = 0; i < ppc_num_gprs; i++)
3819 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3820 PPC_SPE_UPPER_GP0_REGNUM + i,
3821 upper_spe[i]);
3822 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3823 PPC_SPE_ACC_REGNUM, "acc");
3824 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3825 PPC_SPE_FSCR_REGNUM, "spefscr");
3826
3827 if (have_mq || have_fpu || !valid_p)
3828 {
3829 tdesc_data_cleanup (tdesc_data);
3830 return NULL;
3831 }
3832 have_spe = 1;
3833 }
3834 else
3835 have_spe = 0;
3836 }
3837
3838 /* If we have a 64-bit binary on a 32-bit target, complain. Also
3839 complain for a 32-bit binary on a 64-bit target; we do not yet
3840 support that. For instance, the 32-bit ABI routines expect
3841 32-bit GPRs.
3842
3843 As long as there isn't an explicit target description, we'll
3844 choose one based on the BFD architecture and get a word size
3845 matching the binary (probably powerpc:common or
3846 powerpc:common64). So there is only trouble if a 64-bit target
3847 supplies a 64-bit description while debugging a 32-bit
3848 binary. */
3849 if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize)
3850 {
3851 tdesc_data_cleanup (tdesc_data);
3852 return NULL;
3853 }
3854
55eddb0f
DJ		 3855#ifdef HAVE_ELF
3856 if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec)
3857 {
3858 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3859 Tag_GNU_Power_ABI_FP))
3860 {
3861 case 1:
3862 soft_float_flag = AUTO_BOOLEAN_FALSE;
3863 break;
3864 case 2:
3865 soft_float_flag = AUTO_BOOLEAN_TRUE;
3866 break;
3867 default:
3868 break;
3869 }
3870 }
3871
3872 if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec)
3873 {
3874 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3875 Tag_GNU_Power_ABI_Vector))
3876 {
3877 case 1:
3878 vector_abi = POWERPC_VEC_GENERIC;
3879 break;
3880 case 2:
3881 vector_abi = POWERPC_VEC_ALTIVEC;
3882 break;
3883 case 3:
3884 vector_abi = POWERPC_VEC_SPE;
3885 break;
3886 default:
3887 break;
3888 }
3889 }
3890#endif
3891
3892 if (soft_float_flag == AUTO_BOOLEAN_TRUE)
3893 soft_float = 1;
3894 else if (soft_float_flag == AUTO_BOOLEAN_FALSE)
3895 soft_float = 0;
3896 else
3897 soft_float = !have_fpu;
3898
3899 /* If we have a hard float binary or setting but no floating point
3900 registers, downgrade to soft float anyway. We're still somewhat
3901 useful in this scenario. */
3902 if (!soft_float && !have_fpu)
3903 soft_float = 1;
3904
3905 /* Similarly for vector registers. */
3906 if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec)
3907 vector_abi = POWERPC_VEC_GENERIC;
3908
3909 if (vector_abi == POWERPC_VEC_SPE && !have_spe)
3910 vector_abi = POWERPC_VEC_GENERIC;
3911
3912 if (vector_abi == POWERPC_VEC_AUTO)
3913 {
3914 if (have_altivec)
3915 vector_abi = POWERPC_VEC_ALTIVEC;
3916 else if (have_spe)
3917 vector_abi = POWERPC_VEC_SPE;
3918 else
3919 vector_abi = POWERPC_VEC_GENERIC;
3920 }
3921
3922 /* Do not limit the vector ABI based on available hardware, since we
3923 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
3924
7cc46491
DJ		 3925 /* Find a candidate among extant architectures. */
3926 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3927 arches != NULL;
3928 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3929 {
3930 /* Word size in the various PowerPC bfd_arch_info structs isn't
3931 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3932 separate word size check. */
3933 tdep = gdbarch_tdep (arches->gdbarch);
55eddb0f
DJ		 3934 if (tdep && tdep->soft_float != soft_float)
3935 continue;
3936 if (tdep && tdep->vector_abi != vector_abi)
3937 continue;
7cc46491
DJ		 3938 if (tdep && tdep->wordsize == wordsize)
3939 {
3940 if (tdesc_data != NULL)
3941 tdesc_data_cleanup (tdesc_data);
3942 return arches->gdbarch;
3943 }
3944 }
3945
3946 /* None found, create a new architecture from INFO, whose bfd_arch_info
3947 validity depends on the source:
3948 - executable useless
3949 - rs6000_host_arch() good
3950 - core file good
3951 - "set arch" trust blindly
3952 - GDB startup useless but harmless */
3953
3954 tdep = XCALLOC (1, struct gdbarch_tdep);
3955 tdep->wordsize = wordsize;
55eddb0f
DJ		 3956 tdep->soft_float = soft_float;
3957 tdep->vector_abi = vector_abi;
7cc46491 3958
7a78ae4e 3959 gdbarch = gdbarch_alloc (&info, tdep);
7a78ae4e 3960
7cc46491
DJ		 3961 tdep->ppc_gp0_regnum = PPC_R0_REGNUM;
3962 tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2;
3963 tdep->ppc_ps_regnum = PPC_MSR_REGNUM;
3964 tdep->ppc_cr_regnum = PPC_CR_REGNUM;
3965 tdep->ppc_lr_regnum = PPC_LR_REGNUM;
3966 tdep->ppc_ctr_regnum = PPC_CTR_REGNUM;
3967 tdep->ppc_xer_regnum = PPC_XER_REGNUM;
3968 tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1;
3969
3970 tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1;
3971 tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1;
604c2f83 3972 tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1;
7cc46491
DJ		 3973 tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1;
3974 tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1;
3975 tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1;
3976 tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1;
3977 tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
3978
3979 set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
3980 set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3981 set_gdbarch_deprecated_fp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3982 set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum);
9f643768 3983 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
7cc46491
DJ		 3984
3985 /* The XML specification for PowerPC sensibly calls the MSR "msr".
3986 GDB traditionally called it "ps", though, so let GDB add an
3987 alias. */
3988 set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum);
3989
4a7622d1 3990 if (wordsize == 8)
05580c65 3991 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
afd48b75 3992 else
4a7622d1 3993 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
c8001721 3994
baffbae0
JB		 3995 /* Set lr_frame_offset. */
3996 if (wordsize == 8)
3997 tdep->lr_frame_offset = 16;
baffbae0 3998 else
4a7622d1 3999 tdep->lr_frame_offset = 4;
baffbae0 4000
604c2f83 4001 if (have_spe || have_dfp || have_vsx)
7cc46491 4002 {
f949c649 4003 set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read);
0df8b418
MS		 4004 set_gdbarch_pseudo_register_write (gdbarch,
4005 rs6000_pseudo_register_write);
7cc46491 4006 }
1fcc0bb8 4007
e0d24f8d
WZ		 4008 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
4009
56a6dfb9 4010 /* Select instruction printer. */
708ff411 4011 if (arch == bfd_arch_rs6000)
9364a0ef 4012 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
56a6dfb9 4013 else
9364a0ef 4014 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
7495d1dc 4015
5a9e69ba 4016 set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS);
f949c649
TJB		 4017
4018 if (have_spe)
4019 num_pseudoregs += 32;
4020 if (have_dfp)
4021 num_pseudoregs += 16;
604c2f83
LM		 4022 if (have_vsx)
4023 /* Include both VSX and Extended FP registers. */
4024 num_pseudoregs += 96;
f949c649
TJB		 4025
4026 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs);
7a78ae4e
ND		 4027
4028 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
4029 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
4030 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4031 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
4032 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4033 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4034 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4a7622d1 4035 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
4e409299 4036 set_gdbarch_char_signed (gdbarch, 0);
7a78ae4e 4037
11269d7e 4038 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
4a7622d1 4039 if (wordsize == 8)
8b148df9
AC		 4040 /* PPC64 SYSV. */
4041 set_gdbarch_frame_red_zone_size (gdbarch, 288);
7a78ae4e 4042
691d145a
JB		 4043 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
4044 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
4045 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
4046
18ed0c4e
JB		 4047 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
4048 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
d217aaed 4049
4a7622d1 4050 if (wordsize == 4)
77b2b6d4 4051 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
4a7622d1 4052 else if (wordsize == 8)
8be9034a 4053 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
7a78ae4e 4054
7a78ae4e 4055 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
0d1243d9 4056 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
8ab3d180 4057 set_gdbarch_skip_main_prologue (gdbarch, rs6000_skip_main_prologue);
0d1243d9 4058
7a78ae4e 4059 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
7a78ae4e
ND		 4060 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
4061
203c3895 4062 /* The value of symbols of type N_SO and N_FUN maybe null when
0df8b418 4063 it shouldn't be. */
203c3895
UW		 4064 set_gdbarch_sofun_address_maybe_missing (gdbarch, 1);
4065
ce5eab59 4066 /* Handles single stepping of atomic sequences. */
4a7622d1 4067 set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence);
ce5eab59 4068
0df8b418 4069 /* Not sure on this. FIXMEmgo */
7a78ae4e
ND		 4070 set_gdbarch_frame_args_skip (gdbarch, 8);
4071
143985b7
AF		 4072 /* Helpers for function argument information. */
4073 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
4074
6f7f3f0d
UW		 4075 /* Trampoline. */
4076 set_gdbarch_in_solib_return_trampoline
4077 (gdbarch, rs6000_in_solib_return_trampoline);
4078 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code);
4079
4fc771b8 4080 /* Hook in the DWARF CFI frame unwinder. */
1af5d7ce 4081 dwarf2_append_unwinders (gdbarch);
4fc771b8
DJ		 4082 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum);
4083
9274a07c
LM		 4084 /* Frame handling. */
4085 dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg);
4086
2454a024
UW		 4087 /* Setup displaced stepping. */
4088 set_gdbarch_displaced_step_copy_insn (gdbarch,
4089 simple_displaced_step_copy_insn);
99e40580
UW		 4090 set_gdbarch_displaced_step_hw_singlestep (gdbarch,
4091 ppc_displaced_step_hw_singlestep);
2454a024
UW		 4092 set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup);
4093 set_gdbarch_displaced_step_free_closure (gdbarch,
4094 simple_displaced_step_free_closure);
4095 set_gdbarch_displaced_step_location (gdbarch,
4096 displaced_step_at_entry_point);
4097
4098 set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE);
4099
7b112f9c 4100 /* Hook in ABI-specific overrides, if they have been registered. */
8a4c2d24
UW		 4101 info.target_desc = tdesc;
4102 info.tdep_info = (void *) tdesc_data;
4be87837 4103 gdbarch_init_osabi (info, gdbarch);
7b112f9c 4104
61a65099
KB		 4105 switch (info.osabi)
4106 {
f5aecab8 4107 case GDB_OSABI_LINUX:
61a65099
KB		 4108 case GDB_OSABI_NETBSD_AOUT:
4109 case GDB_OSABI_NETBSD_ELF:
4110 case GDB_OSABI_UNKNOWN:
61a65099 4111 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
1af5d7ce
UW		 4112 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
4113 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
61a65099
KB		 4114 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
4115 break;
4116 default:
61a65099 4117 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
81332287
KB		 4118
4119 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
1af5d7ce
UW		 4120 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
4121 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
81332287 4122 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
61a65099
KB		 4123 }
4124
7cc46491
DJ		 4125 set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type);
4126 set_tdesc_pseudo_register_reggroup_p (gdbarch,
4127 rs6000_pseudo_register_reggroup_p);
4128 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
4129
4130 /* Override the normal target description method to make the SPE upper
4131 halves anonymous. */
4132 set_gdbarch_register_name (gdbarch, rs6000_register_name);
4133
604c2f83
LM		 4134 /* Choose register numbers for all supported pseudo-registers. */
4135 tdep->ppc_ev0_regnum = -1;
4136 tdep->ppc_dl0_regnum = -1;
4137 tdep->ppc_vsr0_regnum = -1;
4138 tdep->ppc_efpr0_regnum = -1;
9f643768 4139
604c2f83
LM		 4140 cur_reg = gdbarch_num_regs (gdbarch);
4141
4142 if (have_spe)
4143 {
4144 tdep->ppc_ev0_regnum = cur_reg;
4145 cur_reg += 32;
4146 }
4147 if (have_dfp)
4148 {
4149 tdep->ppc_dl0_regnum = cur_reg;
4150 cur_reg += 16;
4151 }
4152 if (have_vsx)
4153 {
4154 tdep->ppc_vsr0_regnum = cur_reg;
4155 cur_reg += 64;
4156 tdep->ppc_efpr0_regnum = cur_reg;
4157 cur_reg += 32;
4158 }
f949c649 4159
604c2f83
LM		 4160 gdb_assert (gdbarch_num_regs (gdbarch)
4161 + gdbarch_num_pseudo_regs (gdbarch) == cur_reg);
f949c649 4162
7a78ae4e 4163 return gdbarch;
c906108c
SS		 4164}
4165
7b112f9c 4166static void
8b164abb 4167rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
7b112f9c 4168{
8b164abb 4169 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7b112f9c
JT		 4170
4171 if (tdep == NULL)
4172 return;
4173
4be87837 4174 /* FIXME: Dump gdbarch_tdep. */
7b112f9c
JT		 4175}
4176
55eddb0f
DJ		 4177/* PowerPC-specific commands. */
4178
4179static void
4180set_powerpc_command (char *args, int from_tty)
4181{
4182 printf_unfiltered (_("\
4183\"set powerpc\" must be followed by an appropriate subcommand.\n"));
4184 help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout);
4185}
4186
4187static void
4188show_powerpc_command (char *args, int from_tty)
4189{
4190 cmd_show_list (showpowerpccmdlist, from_tty, "");
4191}
4192
4193static void
4194powerpc_set_soft_float (char *args, int from_tty,
4195 struct cmd_list_element *c)
4196{
4197 struct gdbarch_info info;
4198
4199 /* Update the architecture. */
4200 gdbarch_info_init (&info);
4201 if (!gdbarch_update_p (info))
9b20d036 4202 internal_error (__FILE__, __LINE__, _("could not update architecture"));
55eddb0f
DJ		 4203}
4204
4205static void
4206powerpc_set_vector_abi (char *args, int from_tty,
4207 struct cmd_list_element *c)
4208{
4209 struct gdbarch_info info;
4210 enum powerpc_vector_abi vector_abi;
4211
4212 for (vector_abi = POWERPC_VEC_AUTO;
4213 vector_abi != POWERPC_VEC_LAST;
4214 vector_abi++)
4215 if (strcmp (powerpc_vector_abi_string,
4216 powerpc_vector_strings[vector_abi]) == 0)
4217 {
4218 powerpc_vector_abi_global = vector_abi;
4219 break;
4220 }
4221
4222 if (vector_abi == POWERPC_VEC_LAST)
4223 internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."),
4224 powerpc_vector_abi_string);
4225
4226 /* Update the architecture. */
4227 gdbarch_info_init (&info);
4228 if (!gdbarch_update_p (info))
9b20d036 4229 internal_error (__FILE__, __LINE__, _("could not update architecture"));
55eddb0f
DJ		 4230}
4231
e09342b5
TJB		 4232/* Show the current setting of the exact watchpoints flag. */
4233
4234static void
4235show_powerpc_exact_watchpoints (struct ui_file *file, int from_tty,
4236 struct cmd_list_element *c,
4237 const char *value)
4238{
4239 fprintf_filtered (file, _("Use of exact watchpoints is %s.\n"), value);
4240}
4241
c906108c
SS		 4242/* Initialization code. */
4243
0df8b418
MS		 4244/* -Wmissing-prototypes */
4245extern initialize_file_ftype _initialize_rs6000_tdep;
b9362cc7 4246
c906108c 4247void
fba45db2 4248_initialize_rs6000_tdep (void)
c906108c 4249{
7b112f9c
JT		 4250 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
4251 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
7cc46491
DJ		 4252
4253 /* Initialize the standard target descriptions. */
4254 initialize_tdesc_powerpc_32 ();
7284e1be 4255 initialize_tdesc_powerpc_altivec32 ();
604c2f83 4256 initialize_tdesc_powerpc_vsx32 ();
7cc46491
DJ		 4257 initialize_tdesc_powerpc_403 ();
4258 initialize_tdesc_powerpc_403gc ();
4d09ffea 4259 initialize_tdesc_powerpc_405 ();
7cc46491
DJ		 4260 initialize_tdesc_powerpc_505 ();
4261 initialize_tdesc_powerpc_601 ();
4262 initialize_tdesc_powerpc_602 ();
4263 initialize_tdesc_powerpc_603 ();
4264 initialize_tdesc_powerpc_604 ();
4265 initialize_tdesc_powerpc_64 ();
7284e1be 4266 initialize_tdesc_powerpc_altivec64 ();
604c2f83 4267 initialize_tdesc_powerpc_vsx64 ();
7cc46491
DJ		 4268 initialize_tdesc_powerpc_7400 ();
4269 initialize_tdesc_powerpc_750 ();
4270 initialize_tdesc_powerpc_860 ();
4271 initialize_tdesc_powerpc_e500 ();
4272 initialize_tdesc_rs6000 ();
55eddb0f
DJ		 4273
4274 /* Add root prefix command for all "set powerpc"/"show powerpc"
4275 commands. */
4276 add_prefix_cmd ("powerpc", no_class, set_powerpc_command,
4277 _("Various PowerPC-specific commands."),
4278 &setpowerpccmdlist, "set powerpc ", 0, &setlist);
4279
4280 add_prefix_cmd ("powerpc", no_class, show_powerpc_command,
4281 _("Various PowerPC-specific commands."),
4282 &showpowerpccmdlist, "show powerpc ", 0, &showlist);
4283
4284 /* Add a command to allow the user to force the ABI. */
4285 add_setshow_auto_boolean_cmd ("soft-float", class_support,
4286 &powerpc_soft_float_global,
4287 _("Set whether to use a soft-float ABI."),
4288 _("Show whether to use a soft-float ABI."),
4289 NULL,
4290 powerpc_set_soft_float, NULL,
4291 &setpowerpccmdlist, &showpowerpccmdlist);
4292
4293 add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings,
4294 &powerpc_vector_abi_string,
4295 _("Set the vector ABI."),
4296 _("Show the vector ABI."),
4297 NULL, powerpc_set_vector_abi, NULL,
4298 &setpowerpccmdlist, &showpowerpccmdlist);
e09342b5
TJB		 4299
4300 add_setshow_boolean_cmd ("exact-watchpoints", class_support,
4301 &target_exact_watchpoints,
4302 _("\
4303Set whether to use just one debug register for watchpoints on scalars."),
4304 _("\
4305Show whether to use just one debug register for watchpoints on scalars."),
4306 _("\
4307If true, GDB will use only one debug register when watching a variable of\n\
4308scalar type, thus assuming that the variable is accessed through the address\n\
4309of its first byte."),
4310 NULL, show_powerpc_exact_watchpoints,
4311 &setpowerpccmdlist, &showpowerpccmdlist);
c906108c 4312}
GDB Binutils - Deliverables
This page took 1.415947 seconds and 4 git commands to generate.