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* defs.h (strlen_paddr, paddr, paddr_nz): Remove.
[deliverable/binutils-gdb.git] / gdb / rs6000-tdep.c
CommitLineData
c906108c 1/* Target-dependent code for GDB, the GNU debugger.
7aea86e6 2
6aba47ca 3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
0fb0cc75 4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
721d14ba 5 Free Software Foundation, Inc.
c906108c 6
c5aa993b 7 This file is part of GDB.
c906108c 8
c5aa993b
JM		 9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
c5aa993b 12 (at your option) any later version.
c906108c 13
c5aa993b
JM		 14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
c906108c 18
c5aa993b 19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c
SS		 21
22#include "defs.h"
23#include "frame.h"
24#include "inferior.h"
25#include "symtab.h"
26#include "target.h"
27#include "gdbcore.h"
28#include "gdbcmd.h"
c906108c 29#include "objfiles.h"
7a78ae4e 30#include "arch-utils.h"
4e052eda 31#include "regcache.h"
d195bc9f 32#include "regset.h"
d16aafd8 33#include "doublest.h"
fd0407d6 34#include "value.h"
1fcc0bb8 35#include "parser-defs.h"
4be87837 36#include "osabi.h"
7d9b040b 37#include "infcall.h"
9f643768
JB		 38#include "sim-regno.h"
39#include "gdb/sim-ppc.h"
6ced10dd 40#include "reggroups.h"
4fc771b8 41#include "dwarf2-frame.h"
7cc46491
DJ		 42#include "target-descriptions.h"
43#include "user-regs.h"
7a78ae4e 44
2fccf04a 45#include "libbfd.h" /* for bfd_default_set_arch_mach */
7a78ae4e 46#include "coff/internal.h" /* for libcoff.h */
2fccf04a 47#include "libcoff.h" /* for xcoff_data */
11ed25ac
KB		 48#include "coff/xcoff.h"
49#include "libxcoff.h"
7a78ae4e 50
9aa1e687 51#include "elf-bfd.h"
55eddb0f 52#include "elf/ppc.h"
7a78ae4e 53
6ded7999 54#include "solib-svr4.h"
9aa1e687 55#include "ppc-tdep.h"
7a78ae4e 56
338ef23d 57#include "gdb_assert.h"
a89aa300 58#include "dis-asm.h"
338ef23d 59
61a65099
KB		 60#include "trad-frame.h"
61#include "frame-unwind.h"
62#include "frame-base.h"
63
7cc46491 64#include "features/rs6000/powerpc-32.c"
7284e1be 65#include "features/rs6000/powerpc-altivec32.c"
604c2f83 66#include "features/rs6000/powerpc-vsx32.c"
7cc46491
DJ		 67#include "features/rs6000/powerpc-403.c"
68#include "features/rs6000/powerpc-403gc.c"
69#include "features/rs6000/powerpc-505.c"
70#include "features/rs6000/powerpc-601.c"
71#include "features/rs6000/powerpc-602.c"
72#include "features/rs6000/powerpc-603.c"
73#include "features/rs6000/powerpc-604.c"
74#include "features/rs6000/powerpc-64.c"
7284e1be 75#include "features/rs6000/powerpc-altivec64.c"
604c2f83 76#include "features/rs6000/powerpc-vsx64.c"
7cc46491
DJ		 77#include "features/rs6000/powerpc-7400.c"
78#include "features/rs6000/powerpc-750.c"
79#include "features/rs6000/powerpc-860.c"
80#include "features/rs6000/powerpc-e500.c"
81#include "features/rs6000/rs6000.c"
82
5a9e69ba
TJB		 83/* Determine if regnum is an SPE pseudo-register. */
84#define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
85 && (regnum) >= (tdep)->ppc_ev0_regnum \
86 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
87
f949c649
TJB		 88/* Determine if regnum is a decimal float pseudo-register. */
89#define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
90 && (regnum) >= (tdep)->ppc_dl0_regnum \
91 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
92
604c2f83
LM		 93/* Determine if regnum is a POWER7 VSX register. */
94#define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
95 && (regnum) >= (tdep)->ppc_vsr0_regnum \
96 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
97
98/* Determine if regnum is a POWER7 Extended FP register. */
99#define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
100 && (regnum) >= (tdep)->ppc_efpr0_regnum \
101 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_fprs)
102
55eddb0f
DJ		 103/* The list of available "set powerpc ..." and "show powerpc ..."
104 commands. */
105static struct cmd_list_element *setpowerpccmdlist = NULL;
106static struct cmd_list_element *showpowerpccmdlist = NULL;
107
108static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO;
109
110/* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
111static const char *powerpc_vector_strings[] =
112{
113 "auto",
114 "generic",
115 "altivec",
116 "spe",
117 NULL
118};
119
120/* A variable that can be configured by the user. */
121static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO;
122static const char *powerpc_vector_abi_string = "auto";
123
7a78ae4e
ND		 124/* To be used by skip_prologue. */
125
126struct rs6000_framedata
127 {
128 int offset; /* total size of frame --- the distance
129 by which we decrement sp to allocate
130 the frame */
131 int saved_gpr; /* smallest # of saved gpr */
46a9b8ed 132 unsigned int gpr_mask; /* Each bit is an individual saved GPR. */
7a78ae4e 133 int saved_fpr; /* smallest # of saved fpr */
6be8bc0c 134 int saved_vr; /* smallest # of saved vr */
96ff0de4 135 int saved_ev; /* smallest # of saved ev */
7a78ae4e
ND		 136 int alloca_reg; /* alloca register number (frame ptr) */
137 char frameless; /* true if frameless functions. */
138 char nosavedpc; /* true if pc not saved. */
46a9b8ed 139 char used_bl; /* true if link register clobbered */
7a78ae4e
ND		 140 int gpr_offset; /* offset of saved gprs from prev sp */
141 int fpr_offset; /* offset of saved fprs from prev sp */
6be8bc0c 142 int vr_offset; /* offset of saved vrs from prev sp */
96ff0de4 143 int ev_offset; /* offset of saved evs from prev sp */
7a78ae4e 144 int lr_offset; /* offset of saved lr */
46a9b8ed 145 int lr_register; /* register of saved lr, if trustworthy */
7a78ae4e 146 int cr_offset; /* offset of saved cr */
6be8bc0c 147 int vrsave_offset; /* offset of saved vrsave register */
7a78ae4e
ND		 148 };
149
c906108c 150
604c2f83
LM		 151/* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
152int
153vsx_register_p (struct gdbarch *gdbarch, int regno)
154{
155 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
156 if (tdep->ppc_vsr0_regnum < 0)
157 return 0;
158 else
159 return (regno >= tdep->ppc_vsr0_upper_regnum && regno
160 <= tdep->ppc_vsr0_upper_regnum + 31);
161}
162
64b84175
KB		 163/* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
164int
be8626e0 165altivec_register_p (struct gdbarch *gdbarch, int regno)
64b84175 166{
be8626e0 167 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
64b84175
KB		 168 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
169 return 0;
170 else
171 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
172}
173
383f0f5b 174
867e2dc5
JB		 175/* Return true if REGNO is an SPE register, false otherwise. */
176int
be8626e0 177spe_register_p (struct gdbarch *gdbarch, int regno)
867e2dc5 178{
be8626e0 179 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
867e2dc5
JB		 180
181 /* Is it a reference to EV0 -- EV31, and do we have those? */
5a9e69ba 182 if (IS_SPE_PSEUDOREG (tdep, regno))
867e2dc5
JB		 183 return 1;
184
6ced10dd
JB		 185 /* Is it a reference to one of the raw upper GPR halves? */
186 if (tdep->ppc_ev0_upper_regnum >= 0
187 && tdep->ppc_ev0_upper_regnum <= regno
188 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
189 return 1;
190
867e2dc5
JB		 191 /* Is it a reference to the 64-bit accumulator, and do we have that? */
192 if (tdep->ppc_acc_regnum >= 0
193 && tdep->ppc_acc_regnum == regno)
194 return 1;
195
196 /* Is it a reference to the SPE floating-point status and control register,
197 and do we have that? */
198 if (tdep->ppc_spefscr_regnum >= 0
199 && tdep->ppc_spefscr_regnum == regno)
200 return 1;
201
202 return 0;
203}
204
205
383f0f5b
JB		 206/* Return non-zero if the architecture described by GDBARCH has
207 floating-point registers (f0 --- f31 and fpscr). */
0a613259
AC		 208int
209ppc_floating_point_unit_p (struct gdbarch *gdbarch)
210{
383f0f5b
JB		 211 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
212
213 return (tdep->ppc_fp0_regnum >= 0
214 && tdep->ppc_fpscr_regnum >= 0);
0a613259 215}
9f643768 216
604c2f83
LM		 217/* Return non-zero if the architecture described by GDBARCH has
218 VSX registers (vsr0 --- vsr63). */
63807e1d 219static int
604c2f83
LM		 220ppc_vsx_support_p (struct gdbarch *gdbarch)
221{
222 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
223
224 return tdep->ppc_vsr0_regnum >= 0;
225}
226
06caf7d2
CES		 227/* Return non-zero if the architecture described by GDBARCH has
228 Altivec registers (vr0 --- vr31, vrsave and vscr). */
229int
230ppc_altivec_support_p (struct gdbarch *gdbarch)
231{
232 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
233
234 return (tdep->ppc_vr0_regnum >= 0
235 && tdep->ppc_vrsave_regnum >= 0);
236}
09991fa0
JB		 237
238/* Check that TABLE[GDB_REGNO] is not already initialized, and then
239 set it to SIM_REGNO.
240
241 This is a helper function for init_sim_regno_table, constructing
242 the table mapping GDB register numbers to sim register numbers; we
243 initialize every element in that table to -1 before we start
244 filling it in. */
9f643768
JB		 245static void
246set_sim_regno (int *table, int gdb_regno, int sim_regno)
247{
248 /* Make sure we don't try to assign any given GDB register a sim
249 register number more than once. */
250 gdb_assert (table[gdb_regno] == -1);
251 table[gdb_regno] = sim_regno;
252}
253
09991fa0
JB		 254
255/* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
256 numbers to simulator register numbers, based on the values placed
257 in the ARCH->tdep->ppc_foo_regnum members. */
9f643768
JB		 258static void
259init_sim_regno_table (struct gdbarch *arch)
260{
261 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
7cc46491 262 int total_regs = gdbarch_num_regs (arch);
9f643768
JB		 263 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
264 int i;
7cc46491
DJ		 265 static const char *const segment_regs[] = {
266 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
267 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
268 };
9f643768
JB		 269
270 /* Presume that all registers not explicitly mentioned below are
271 unavailable from the sim. */
272 for (i = 0; i < total_regs; i++)
273 sim_regno[i] = -1;
274
275 /* General-purpose registers. */
276 for (i = 0; i < ppc_num_gprs; i++)
277 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
278
279 /* Floating-point registers. */
280 if (tdep->ppc_fp0_regnum >= 0)
281 for (i = 0; i < ppc_num_fprs; i++)
282 set_sim_regno (sim_regno,
283 tdep->ppc_fp0_regnum + i,
284 sim_ppc_f0_regnum + i);
285 if (tdep->ppc_fpscr_regnum >= 0)
286 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
287
288 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
289 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
290 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
291
292 /* Segment registers. */
7cc46491
DJ		 293 for (i = 0; i < ppc_num_srs; i++)
294 {
295 int gdb_regno;
296
297 gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1);
298 if (gdb_regno >= 0)
299 set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i);
300 }
9f643768
JB		 301
302 /* Altivec registers. */
303 if (tdep->ppc_vr0_regnum >= 0)
304 {
305 for (i = 0; i < ppc_num_vrs; i++)
306 set_sim_regno (sim_regno,
307 tdep->ppc_vr0_regnum + i,
308 sim_ppc_vr0_regnum + i);
309
310 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
311 we can treat this more like the other cases. */
312 set_sim_regno (sim_regno,
313 tdep->ppc_vr0_regnum + ppc_num_vrs,
314 sim_ppc_vscr_regnum);
315 }
316 /* vsave is a special-purpose register, so the code below handles it. */
317
318 /* SPE APU (E500) registers. */
6ced10dd
JB		 319 if (tdep->ppc_ev0_upper_regnum >= 0)
320 for (i = 0; i < ppc_num_gprs; i++)
321 set_sim_regno (sim_regno,
322 tdep->ppc_ev0_upper_regnum + i,
323 sim_ppc_rh0_regnum + i);
9f643768
JB		 324 if (tdep->ppc_acc_regnum >= 0)
325 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
326 /* spefscr is a special-purpose register, so the code below handles it. */
327
7cc46491 328#ifdef WITH_SIM
9f643768
JB		 329 /* Now handle all special-purpose registers. Verify that they
330 haven't mistakenly been assigned numbers by any of the above
7cc46491
DJ		 331 code. */
332 for (i = 0; i < sim_ppc_num_sprs; i++)
333 {
334 const char *spr_name = sim_spr_register_name (i);
335 int gdb_regno = -1;
336
337 if (spr_name != NULL)
338 gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1);
339
340 if (gdb_regno != -1)
341 set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i);
342 }
343#endif
9f643768
JB		 344
345 /* Drop the initialized array into place. */
346 tdep->sim_regno = sim_regno;
347}
348
09991fa0
JB		 349
350/* Given a GDB register number REG, return the corresponding SIM
351 register number. */
9f643768 352static int
e7faf938 353rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg)
9f643768 354{
e7faf938 355 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9f643768
JB		 356 int sim_regno;
357
7cc46491 358 if (tdep->sim_regno == NULL)
e7faf938 359 init_sim_regno_table (gdbarch);
7cc46491 360
f57d151a 361 gdb_assert (0 <= reg
e7faf938
MD		 362 && reg <= gdbarch_num_regs (gdbarch)
363 + gdbarch_num_pseudo_regs (gdbarch));
9f643768
JB		 364 sim_regno = tdep->sim_regno[reg];
365
366 if (sim_regno >= 0)
367 return sim_regno;
368 else
369 return LEGACY_SIM_REGNO_IGNORE;
370}
371
d195bc9f
MK		 372\f
373
374/* Register set support functions. */
375
f2db237a
AM		 376/* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
377 Write the register to REGCACHE. */
378
7284e1be 379void
d195bc9f 380ppc_supply_reg (struct regcache *regcache, int regnum,
f2db237a 381 const gdb_byte *regs, size_t offset, int regsize)
d195bc9f
MK		 382{
383 if (regnum != -1 && offset != -1)
f2db237a
AM		 384 {
385 if (regsize > 4)
386 {
387 struct gdbarch *gdbarch = get_regcache_arch (regcache);
388 int gdb_regsize = register_size (gdbarch, regnum);
389 if (gdb_regsize < regsize
390 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
391 offset += regsize - gdb_regsize;
392 }
393 regcache_raw_supply (regcache, regnum, regs + offset);
394 }
d195bc9f
MK		 395}
396
f2db237a
AM		 397/* Read register REGNUM from REGCACHE and store to REGS + OFFSET
398 in a field REGSIZE wide. Zero pad as necessary. */
399
7284e1be 400void
d195bc9f 401ppc_collect_reg (const struct regcache *regcache, int regnum,
f2db237a 402 gdb_byte *regs, size_t offset, int regsize)
d195bc9f
MK		 403{
404 if (regnum != -1 && offset != -1)
f2db237a
AM		 405 {
406 if (regsize > 4)
407 {
408 struct gdbarch *gdbarch = get_regcache_arch (regcache);
409 int gdb_regsize = register_size (gdbarch, regnum);
410 if (gdb_regsize < regsize)
411 {
412 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
413 {
414 memset (regs + offset, 0, regsize - gdb_regsize);
415 offset += regsize - gdb_regsize;
416 }
417 else
418 memset (regs + offset + regsize - gdb_regsize, 0,
419 regsize - gdb_regsize);
420 }
421 }
422 regcache_raw_collect (regcache, regnum, regs + offset);
423 }
d195bc9f
MK		 424}
425
f2db237a
AM		 426static int
427ppc_greg_offset (struct gdbarch *gdbarch,
428 struct gdbarch_tdep *tdep,
429 const struct ppc_reg_offsets *offsets,
430 int regnum,
431 int *regsize)
432{
433 *regsize = offsets->gpr_size;
434 if (regnum >= tdep->ppc_gp0_regnum
435 && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs)
436 return (offsets->r0_offset
437 + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size);
438
439 if (regnum == gdbarch_pc_regnum (gdbarch))
440 return offsets->pc_offset;
441
442 if (regnum == tdep->ppc_ps_regnum)
443 return offsets->ps_offset;
444
445 if (regnum == tdep->ppc_lr_regnum)
446 return offsets->lr_offset;
447
448 if (regnum == tdep->ppc_ctr_regnum)
449 return offsets->ctr_offset;
450
451 *regsize = offsets->xr_size;
452 if (regnum == tdep->ppc_cr_regnum)
453 return offsets->cr_offset;
454
455 if (regnum == tdep->ppc_xer_regnum)
456 return offsets->xer_offset;
457
458 if (regnum == tdep->ppc_mq_regnum)
459 return offsets->mq_offset;
460
461 return -1;
462}
463
464static int
465ppc_fpreg_offset (struct gdbarch_tdep *tdep,
466 const struct ppc_reg_offsets *offsets,
467 int regnum)
468{
469 if (regnum >= tdep->ppc_fp0_regnum
470 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs)
471 return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8;
472
473 if (regnum == tdep->ppc_fpscr_regnum)
474 return offsets->fpscr_offset;
475
476 return -1;
477}
478
06caf7d2
CES		 479static int
480ppc_vrreg_offset (struct gdbarch_tdep *tdep,
481 const struct ppc_reg_offsets *offsets,
482 int regnum)
483{
484 if (regnum >= tdep->ppc_vr0_regnum
485 && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs)
486 return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16;
487
488 if (regnum == tdep->ppc_vrsave_regnum - 1)
489 return offsets->vscr_offset;
490
491 if (regnum == tdep->ppc_vrsave_regnum)
492 return offsets->vrsave_offset;
493
494 return -1;
495}
496
d195bc9f
MK		 497/* Supply register REGNUM in the general-purpose register set REGSET
498 from the buffer specified by GREGS and LEN to register cache
499 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
500
501void
502ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
503 int regnum, const void *gregs, size_t len)
504{
505 struct gdbarch *gdbarch = get_regcache_arch (regcache);
506 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
507 const struct ppc_reg_offsets *offsets = regset->descr;
508 size_t offset;
f2db237a 509 int regsize;
d195bc9f 510
f2db237a 511 if (regnum == -1)
d195bc9f 512 {
f2db237a
AM		 513 int i;
514 int gpr_size = offsets->gpr_size;
515
516 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
517 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
518 i++, offset += gpr_size)
519 ppc_supply_reg (regcache, i, gregs, offset, gpr_size);
520
521 ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch),
522 gregs, offsets->pc_offset, gpr_size);
523 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
524 gregs, offsets->ps_offset, gpr_size);
525 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
526 gregs, offsets->lr_offset, gpr_size);
527 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
528 gregs, offsets->ctr_offset, gpr_size);
529 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
530 gregs, offsets->cr_offset, offsets->xr_size);
531 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
532 gregs, offsets->xer_offset, offsets->xr_size);
533 ppc_supply_reg (regcache, tdep->ppc_mq_regnum,
534 gregs, offsets->mq_offset, offsets->xr_size);
535 return;
d195bc9f
MK		 536 }
537
f2db237a
AM		 538 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
539 ppc_supply_reg (regcache, regnum, gregs, offset, regsize);
d195bc9f
MK		 540}
541
542/* Supply register REGNUM in the floating-point register set REGSET
543 from the buffer specified by FPREGS and LEN to register cache
544 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
545
546void
547ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
548 int regnum, const void *fpregs, size_t len)
549{
550 struct gdbarch *gdbarch = get_regcache_arch (regcache);
f2db237a
AM		 551 struct gdbarch_tdep *tdep;
552 const struct ppc_reg_offsets *offsets;
d195bc9f 553 size_t offset;
d195bc9f 554
f2db237a
AM		 555 if (!ppc_floating_point_unit_p (gdbarch))
556 return;
383f0f5b 557
f2db237a
AM		 558 tdep = gdbarch_tdep (gdbarch);
559 offsets = regset->descr;
560 if (regnum == -1)
d195bc9f 561 {
f2db237a
AM		 562 int i;
563
564 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
565 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
566 i++, offset += 8)
567 ppc_supply_reg (regcache, i, fpregs, offset, 8);
568
569 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
570 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
571 return;
d195bc9f
MK		 572 }
573
f2db237a
AM		 574 offset = ppc_fpreg_offset (tdep, offsets, regnum);
575 ppc_supply_reg (regcache, regnum, fpregs, offset,
576 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
d195bc9f
MK		 577}
578
604c2f83
LM		 579/* Supply register REGNUM in the VSX register set REGSET
580 from the buffer specified by VSXREGS and LEN to register cache
581 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
582
583void
584ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache,
585 int regnum, const void *vsxregs, size_t len)
586{
587 struct gdbarch *gdbarch = get_regcache_arch (regcache);
588 struct gdbarch_tdep *tdep;
589
590 if (!ppc_vsx_support_p (gdbarch))
591 return;
592
593 tdep = gdbarch_tdep (gdbarch);
594
595 if (regnum == -1)
596 {
597 int i;
598
599 for (i = tdep->ppc_vsr0_upper_regnum;
600 i < tdep->ppc_vsr0_upper_regnum + 32;
601 i++)
602 ppc_supply_reg (regcache, i, vsxregs, 0, 8);
603
604 return;
605 }
606 else
607 ppc_supply_reg (regcache, regnum, vsxregs, 0, 8);
608}
609
06caf7d2
CES		 610/* Supply register REGNUM in the Altivec register set REGSET
611 from the buffer specified by VRREGS and LEN to register cache
612 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
613
614void
615ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache,
616 int regnum, const void *vrregs, size_t len)
617{
618 struct gdbarch *gdbarch = get_regcache_arch (regcache);
619 struct gdbarch_tdep *tdep;
620 const struct ppc_reg_offsets *offsets;
621 size_t offset;
622
623 if (!ppc_altivec_support_p (gdbarch))
624 return;
625
626 tdep = gdbarch_tdep (gdbarch);
627 offsets = regset->descr;
628 if (regnum == -1)
629 {
630 int i;
631
632 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
633 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
634 i++, offset += 16)
635 ppc_supply_reg (regcache, i, vrregs, offset, 16);
636
637 ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
638 vrregs, offsets->vscr_offset, 4);
639
640 ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum,
641 vrregs, offsets->vrsave_offset, 4);
642 return;
643 }
644
645 offset = ppc_vrreg_offset (tdep, offsets, regnum);
646 if (regnum != tdep->ppc_vrsave_regnum
647 && regnum != tdep->ppc_vrsave_regnum - 1)
648 ppc_supply_reg (regcache, regnum, vrregs, offset, 16);
649 else
650 ppc_supply_reg (regcache, regnum,
651 vrregs, offset, 4);
652}
653
d195bc9f 654/* Collect register REGNUM in the general-purpose register set
f2db237a 655 REGSET from register cache REGCACHE into the buffer specified by
d195bc9f
MK		 656 GREGS and LEN. If REGNUM is -1, do this for all registers in
657 REGSET. */
658
659void
660ppc_collect_gregset (const struct regset *regset,
661 const struct regcache *regcache,
662 int regnum, void *gregs, size_t len)
663{
664 struct gdbarch *gdbarch = get_regcache_arch (regcache);
665 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
666 const struct ppc_reg_offsets *offsets = regset->descr;
667 size_t offset;
f2db237a 668 int regsize;
d195bc9f 669
f2db237a 670 if (regnum == -1)
d195bc9f 671 {
f2db237a
AM		 672 int i;
673 int gpr_size = offsets->gpr_size;
674
675 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
676 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
677 i++, offset += gpr_size)
678 ppc_collect_reg (regcache, i, gregs, offset, gpr_size);
679
680 ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch),
681 gregs, offsets->pc_offset, gpr_size);
682 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
683 gregs, offsets->ps_offset, gpr_size);
684 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
685 gregs, offsets->lr_offset, gpr_size);
686 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
687 gregs, offsets->ctr_offset, gpr_size);
688 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
689 gregs, offsets->cr_offset, offsets->xr_size);
690 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
691 gregs, offsets->xer_offset, offsets->xr_size);
692 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
693 gregs, offsets->mq_offset, offsets->xr_size);
694 return;
d195bc9f
MK		 695 }
696
f2db237a
AM		 697 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
698 ppc_collect_reg (regcache, regnum, gregs, offset, regsize);
d195bc9f
MK		 699}
700
701/* Collect register REGNUM in the floating-point register set
f2db237a 702 REGSET from register cache REGCACHE into the buffer specified by
d195bc9f
MK		 703 FPREGS and LEN. If REGNUM is -1, do this for all registers in
704 REGSET. */
705
706void
707ppc_collect_fpregset (const struct regset *regset,
708 const struct regcache *regcache,
709 int regnum, void *fpregs, size_t len)
710{
711 struct gdbarch *gdbarch = get_regcache_arch (regcache);
f2db237a
AM		 712 struct gdbarch_tdep *tdep;
713 const struct ppc_reg_offsets *offsets;
d195bc9f 714 size_t offset;
d195bc9f 715
f2db237a
AM		 716 if (!ppc_floating_point_unit_p (gdbarch))
717 return;
383f0f5b 718
f2db237a
AM		 719 tdep = gdbarch_tdep (gdbarch);
720 offsets = regset->descr;
721 if (regnum == -1)
d195bc9f 722 {
f2db237a
AM		 723 int i;
724
725 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
726 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
727 i++, offset += 8)
728 ppc_collect_reg (regcache, i, fpregs, offset, 8);
729
730 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
731 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
732 return;
d195bc9f
MK		 733 }
734
f2db237a
AM		 735 offset = ppc_fpreg_offset (tdep, offsets, regnum);
736 ppc_collect_reg (regcache, regnum, fpregs, offset,
737 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
d195bc9f 738}
06caf7d2 739
604c2f83
LM		 740/* Collect register REGNUM in the VSX register set
741 REGSET from register cache REGCACHE into the buffer specified by
742 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
743 REGSET. */
744
745void
746ppc_collect_vsxregset (const struct regset *regset,
747 const struct regcache *regcache,
748 int regnum, void *vsxregs, size_t len)
749{
750 struct gdbarch *gdbarch = get_regcache_arch (regcache);
751 struct gdbarch_tdep *tdep;
752
753 if (!ppc_vsx_support_p (gdbarch))
754 return;
755
756 tdep = gdbarch_tdep (gdbarch);
757
758 if (regnum == -1)
759 {
760 int i;
761
762 for (i = tdep->ppc_vsr0_upper_regnum;
763 i < tdep->ppc_vsr0_upper_regnum + 32;
764 i++)
765 ppc_collect_reg (regcache, i, vsxregs, 0, 8);
766
767 return;
768 }
769 else
770 ppc_collect_reg (regcache, regnum, vsxregs, 0, 8);
771}
772
773
06caf7d2
CES		 774/* Collect register REGNUM in the Altivec register set
775 REGSET from register cache REGCACHE into the buffer specified by
776 VRREGS and LEN. If REGNUM is -1, do this for all registers in
777 REGSET. */
778
779void
780ppc_collect_vrregset (const struct regset *regset,
781 const struct regcache *regcache,
782 int regnum, void *vrregs, size_t len)
783{
784 struct gdbarch *gdbarch = get_regcache_arch (regcache);
785 struct gdbarch_tdep *tdep;
786 const struct ppc_reg_offsets *offsets;
787 size_t offset;
788
789 if (!ppc_altivec_support_p (gdbarch))
790 return;
791
792 tdep = gdbarch_tdep (gdbarch);
793 offsets = regset->descr;
794 if (regnum == -1)
795 {
796 int i;
797
798 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
799 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
800 i++, offset += 16)
801 ppc_collect_reg (regcache, i, vrregs, offset, 16);
802
803 ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
804 vrregs, offsets->vscr_offset, 4);
805
806 ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum,
807 vrregs, offsets->vrsave_offset, 4);
808 return;
809 }
810
811 offset = ppc_vrreg_offset (tdep, offsets, regnum);
812 if (regnum != tdep->ppc_vrsave_regnum
813 && regnum != tdep->ppc_vrsave_regnum - 1)
814 ppc_collect_reg (regcache, regnum, vrregs, offset, 16);
815 else
816 ppc_collect_reg (regcache, regnum,
817 vrregs, offset, 4);
818}
d195bc9f 819\f
0a613259 820
0d1243d9
PG		 821static int
822insn_changes_sp_or_jumps (unsigned long insn)
823{
824 int opcode = (insn >> 26) & 0x03f;
825 int sd = (insn >> 21) & 0x01f;
826 int a = (insn >> 16) & 0x01f;
827 int subcode = (insn >> 1) & 0x3ff;
828
829 /* Changes the stack pointer. */
830
831 /* NOTE: There are many ways to change the value of a given register.
832 The ways below are those used when the register is R1, the SP,
833 in a funtion's epilogue. */
834
835 if (opcode == 31 && subcode == 444 && a == 1)
836 return 1; /* mr R1,Rn */
837 if (opcode == 14 && sd == 1)
838 return 1; /* addi R1,Rn,simm */
839 if (opcode == 58 && sd == 1)
840 return 1; /* ld R1,ds(Rn) */
841
842 /* Transfers control. */
843
844 if (opcode == 18)
845 return 1; /* b */
846 if (opcode == 16)
847 return 1; /* bc */
848 if (opcode == 19 && subcode == 16)
849 return 1; /* bclr */
850 if (opcode == 19 && subcode == 528)
851 return 1; /* bcctr */
852
853 return 0;
854}
855
856/* Return true if we are in the function's epilogue, i.e. after the
857 instruction that destroyed the function's stack frame.
858
859 1) scan forward from the point of execution:
860 a) If you find an instruction that modifies the stack pointer
861 or transfers control (except a return), execution is not in
862 an epilogue, return.
863 b) Stop scanning if you find a return instruction or reach the
864 end of the function or reach the hard limit for the size of
865 an epilogue.
866 2) scan backward from the point of execution:
867 a) If you find an instruction that modifies the stack pointer,
868 execution *is* in an epilogue, return.
869 b) Stop scanning if you reach an instruction that transfers
870 control or the beginning of the function or reach the hard
871 limit for the size of an epilogue. */
872
873static int
874rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
875{
46a9b8ed 876 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
0d1243d9
PG		 877 bfd_byte insn_buf[PPC_INSN_SIZE];
878 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
879 unsigned long insn;
880 struct frame_info *curfrm;
881
882 /* Find the search limits based on function boundaries and hard limit. */
883
884 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
885 return 0;
886
887 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
888 if (epilogue_start < func_start) epilogue_start = func_start;
889
890 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
891 if (epilogue_end > func_end) epilogue_end = func_end;
892
893 curfrm = get_current_frame ();
894
895 /* Scan forward until next 'blr'. */
896
897 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
898 {
899 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
900 return 0;
4e463ff5 901 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE);
0d1243d9
PG		 902 if (insn == 0x4e800020)
903 break;
46a9b8ed
DJ		 904 /* Assume a bctr is a tail call unless it points strictly within
905 this function. */
906 if (insn == 0x4e800420)
907 {
908 CORE_ADDR ctr = get_frame_register_unsigned (curfrm,
909 tdep->ppc_ctr_regnum);
910 if (ctr > func_start && ctr < func_end)
911 return 0;
912 else
913 break;
914 }
0d1243d9
PG		 915 if (insn_changes_sp_or_jumps (insn))
916 return 0;
917 }
918
919 /* Scan backward until adjustment to stack pointer (R1). */
920
921 for (scan_pc = pc - PPC_INSN_SIZE;
922 scan_pc >= epilogue_start;
923 scan_pc -= PPC_INSN_SIZE)
924 {
925 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
926 return 0;
4e463ff5 927 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE);
0d1243d9
PG		 928 if (insn_changes_sp_or_jumps (insn))
929 return 1;
930 }
931
932 return 0;
933}
934
143985b7 935/* Get the ith function argument for the current function. */
b9362cc7 936static CORE_ADDR
143985b7
AF		 937rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
938 struct type *type)
939{
50fd1280 940 return get_frame_register_unsigned (frame, 3 + argi);
143985b7
AF		 941}
942
c906108c
SS		 943/* Sequence of bytes for breakpoint instruction. */
944
f4f9705a 945const static unsigned char *
67d57894
MD		 946rs6000_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
947 int *bp_size)
c906108c 948{
aaab4dba
AC		 949 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
950 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
c906108c 951 *bp_size = 4;
67d57894 952 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
c906108c
SS		 953 return big_breakpoint;
954 else
955 return little_breakpoint;
956}
957
f74c6cad
LM		 958/* Instruction masks for displaced stepping. */
959#define BRANCH_MASK 0xfc000000
960#define BP_MASK 0xFC0007FE
961#define B_INSN 0x48000000
962#define BC_INSN 0x40000000
963#define BXL_INSN 0x4c000000
964#define BP_INSN 0x7C000008
965
966/* Fix up the state of registers and memory after having single-stepped
967 a displaced instruction. */
63807e1d 968static void
f74c6cad 969ppc_displaced_step_fixup (struct gdbarch *gdbarch,
63807e1d
PA		 970 struct displaced_step_closure *closure,
971 CORE_ADDR from, CORE_ADDR to,
972 struct regcache *regs)
f74c6cad
LM		 973{
974 /* Since we use simple_displaced_step_copy_insn, our closure is a
975 copy of the instruction. */
976 ULONGEST insn = extract_unsigned_integer ((gdb_byte *) closure,
977 PPC_INSN_SIZE);
978 ULONGEST opcode = 0;
979 /* Offset for non PC-relative instructions. */
980 LONGEST offset = PPC_INSN_SIZE;
981
982 opcode = insn & BRANCH_MASK;
983
984 if (debug_displaced)
985 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 986 "displaced: (ppc) fixup (%s, %s)\n",
987 paddress (gdbarch, from), paddress (gdbarch, to));
f74c6cad
LM		 988
989
990 /* Handle PC-relative branch instructions. */
991 if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN)
992 {
a4fafde3 993 ULONGEST current_pc;
f74c6cad
LM		 994
995 /* Read the current PC value after the instruction has been executed
996 in a displaced location. Calculate the offset to be applied to the
997 original PC value before the displaced stepping. */
998 regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch),
999 &current_pc);
1000 offset = current_pc - to;
1001
1002 if (opcode != BXL_INSN)
1003 {
1004 /* Check for AA bit indicating whether this is an absolute
1005 addressing or PC-relative (1: absolute, 0: relative). */
1006 if (!(insn & 0x2))
1007 {
1008 /* PC-relative addressing is being used in the branch. */
1009 if (debug_displaced)
1010 fprintf_unfiltered
1011 (gdb_stdlog,
5af949e3
UW		 1012 "displaced: (ppc) branch instruction: %s\n"
1013 "displaced: (ppc) adjusted PC from %s to %s\n",
1014 paddress (gdbarch, insn), paddress (gdbarch, current_pc),
1015 paddress (gdbarch, from + offset));
f74c6cad
LM		 1016
1017 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1018 from + offset);
1019 }
1020 }
1021 else
1022 {
1023 /* If we're here, it means we have a branch to LR or CTR. If the
1024 branch was taken, the offset is probably greater than 4 (the next
1025 instruction), so it's safe to assume that an offset of 4 means we
1026 did not take the branch. */
1027 if (offset == PPC_INSN_SIZE)
1028 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1029 from + PPC_INSN_SIZE);
1030 }
1031
1032 /* Check for LK bit indicating whether we should set the link
1033 register to point to the next instruction
1034 (1: Set, 0: Don't set). */
1035 if (insn & 0x1)
1036 {
1037 /* Link register needs to be set to the next instruction's PC. */
1038 regcache_cooked_write_unsigned (regs,
1039 gdbarch_tdep (gdbarch)->ppc_lr_regnum,
1040 from + PPC_INSN_SIZE);
1041 if (debug_displaced)
1042 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 1043 "displaced: (ppc) adjusted LR to %s\n",
1044 paddress (gdbarch, from + PPC_INSN_SIZE));
f74c6cad
LM		 1045
1046 }
1047 }
1048 /* Check for breakpoints in the inferior. If we've found one, place the PC
1049 right at the breakpoint instruction. */
1050 else if ((insn & BP_MASK) == BP_INSN)
1051 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from);
1052 else
1053 /* Handle any other instructions that do not fit in the categories above. */
1054 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1055 from + offset);
1056}
c906108c 1057
ce5eab59
UW		 1058/* Instruction masks used during single-stepping of atomic sequences. */
1059#define LWARX_MASK 0xfc0007fe
1060#define LWARX_INSTRUCTION 0x7c000028
1061#define LDARX_INSTRUCTION 0x7c0000A8
1062#define STWCX_MASK 0xfc0007ff
1063#define STWCX_INSTRUCTION 0x7c00012d
1064#define STDCX_INSTRUCTION 0x7c0001ad
ce5eab59
UW		 1065
1066/* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1067 instruction and ending with a STWCX/STDCX instruction. If such a sequence
1068 is found, attempt to step through it. A breakpoint is placed at the end of
1069 the sequence. */
1070
4a7622d1
UW		 1071int
1072ppc_deal_with_atomic_sequence (struct frame_info *frame)
ce5eab59 1073{
a6d9a66e 1074 struct gdbarch *gdbarch = get_frame_arch (frame);
0b1b3e42 1075 CORE_ADDR pc = get_frame_pc (frame);
ce5eab59
UW		 1076 CORE_ADDR breaks[2] = {-1, -1};
1077 CORE_ADDR loc = pc;
24d45690 1078 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
ce5eab59
UW		 1079 int insn = read_memory_integer (loc, PPC_INSN_SIZE);
1080 int insn_count;
1081 int index;
1082 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
1083 const int atomic_sequence_length = 16; /* Instruction sequence length. */
24d45690 1084 int opcode; /* Branch instruction's OPcode. */
ce5eab59
UW		 1085 int bc_insn_count = 0; /* Conditional branch instruction count. */
1086
1087 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1088 if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
1089 && (insn & LWARX_MASK) != LDARX_INSTRUCTION)
1090 return 0;
1091
1092 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1093 instructions. */
1094 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
1095 {
1096 loc += PPC_INSN_SIZE;
1097 insn = read_memory_integer (loc, PPC_INSN_SIZE);
1098
1099 /* Assume that there is at most one conditional branch in the atomic
1100 sequence. If a conditional branch is found, put a breakpoint in
1101 its destination address. */
f74c6cad 1102 if ((insn & BRANCH_MASK) == BC_INSN)
ce5eab59 1103 {
4a7622d1
UW		 1104 int immediate = ((insn & ~3) << 16) >> 16;
1105 int absolute = ((insn >> 1) & 1);
1106
ce5eab59
UW		 1107 if (bc_insn_count >= 1)
1108 return 0; /* More than one conditional branch found, fallback
1109 to the standard single-step code. */
4a7622d1
UW		 1110
1111 if (absolute)
1112 breaks[1] = immediate;
1113 else
1114 breaks[1] = pc + immediate;
1115
1116 bc_insn_count++;
1117 last_breakpoint++;
ce5eab59
UW		 1118 }
1119
1120 if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
1121 || (insn & STWCX_MASK) == STDCX_INSTRUCTION)
1122 break;
1123 }
1124
1125 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1126 if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
1127 && (insn & STWCX_MASK) != STDCX_INSTRUCTION)
1128 return 0;
1129
24d45690 1130 closing_insn = loc;
ce5eab59
UW		 1131 loc += PPC_INSN_SIZE;
1132 insn = read_memory_integer (loc, PPC_INSN_SIZE);
1133
1134 /* Insert a breakpoint right after the end of the atomic sequence. */
1135 breaks[0] = loc;
1136
24d45690
UW		 1137 /* Check for duplicated breakpoints. Check also for a breakpoint
1138 placed (branch instruction's destination) at the stwcx/stdcx
1139 instruction, this resets the reservation and take us back to the
1140 lwarx/ldarx instruction at the beginning of the atomic sequence. */
1141 if (last_breakpoint && ((breaks[1] == breaks[0])
1142 || (breaks[1] == closing_insn)))
ce5eab59
UW		 1143 last_breakpoint = 0;
1144
1145 /* Effectively inserts the breakpoints. */
1146 for (index = 0; index <= last_breakpoint; index++)
a6d9a66e 1147 insert_single_step_breakpoint (gdbarch, breaks[index]);
ce5eab59
UW		 1148
1149 return 1;
1150}
1151
c906108c 1152
c906108c
SS		 1153#define SIGNED_SHORT(x) \
1154 ((sizeof (short) == 2) \
1155 ? ((int)(short)(x)) \
1156 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1157
1158#define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1159
55d05f3b
KB		 1160/* Limit the number of skipped non-prologue instructions, as the examining
1161 of the prologue is expensive. */
1162static int max_skip_non_prologue_insns = 10;
1163
773df3e5
JB		 1164/* Return nonzero if the given instruction OP can be part of the prologue
1165 of a function and saves a parameter on the stack. FRAMEP should be
1166 set if one of the previous instructions in the function has set the
1167 Frame Pointer. */
1168
1169static int
1170store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
1171{
1172 /* Move parameters from argument registers to temporary register. */
1173 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1174 {
1175 /* Rx must be scratch register r0. */
1176 const int rx_regno = (op >> 16) & 31;
1177 /* Ry: Only r3 - r10 are used for parameter passing. */
1178 const int ry_regno = GET_SRC_REG (op);
1179
1180 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
1181 {
1182 *r0_contains_arg = 1;
1183 return 1;
1184 }
1185 else
1186 return 0;
1187 }
1188
1189 /* Save a General Purpose Register on stack. */
1190
1191 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1192 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1193 {
1194 /* Rx: Only r3 - r10 are used for parameter passing. */
1195 const int rx_regno = GET_SRC_REG (op);
1196
1197 return (rx_regno >= 3 && rx_regno <= 10);
1198 }
1199
1200 /* Save a General Purpose Register on stack via the Frame Pointer. */
1201
1202 if (framep &&
1203 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1204 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1205 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1206 {
1207 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1208 However, the compiler sometimes uses r0 to hold an argument. */
1209 const int rx_regno = GET_SRC_REG (op);
1210
1211 return ((rx_regno >= 3 && rx_regno <= 10)
1212 || (rx_regno == 0 && *r0_contains_arg));
1213 }
1214
1215 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1216 {
1217 /* Only f2 - f8 are used for parameter passing. */
1218 const int src_regno = GET_SRC_REG (op);
1219
1220 return (src_regno >= 2 && src_regno <= 8);
1221 }
1222
1223 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1224 {
1225 /* Only f2 - f8 are used for parameter passing. */
1226 const int src_regno = GET_SRC_REG (op);
1227
1228 return (src_regno >= 2 && src_regno <= 8);
1229 }
1230
1231 /* Not an insn that saves a parameter on stack. */
1232 return 0;
1233}
55d05f3b 1234
3c77c82a
DJ		 1235/* Assuming that INSN is a "bl" instruction located at PC, return
1236 nonzero if the destination of the branch is a "blrl" instruction.
1237
1238 This sequence is sometimes found in certain function prologues.
1239 It allows the function to load the LR register with a value that
1240 they can use to access PIC data using PC-relative offsets. */
1241
1242static int
1243bl_to_blrl_insn_p (CORE_ADDR pc, int insn)
1244{
0b1b3e42
UW		 1245 CORE_ADDR dest;
1246 int immediate;
1247 int absolute;
3c77c82a
DJ		 1248 int dest_insn;
1249
0b1b3e42
UW		 1250 absolute = (int) ((insn >> 1) & 1);
1251 immediate = ((insn & ~3) << 6) >> 6;
1252 if (absolute)
1253 dest = immediate;
1254 else
1255 dest = pc + immediate;
1256
3c77c82a
DJ		 1257 dest_insn = read_memory_integer (dest, 4);
1258 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
1259 return 1;
1260
1261 return 0;
1262}
1263
8ab3d180
KB		 1264/* Masks for decoding a branch-and-link (bl) instruction.
1265
1266 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1267 The former is anded with the opcode in question; if the result of
1268 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1269 question is a ``bl'' instruction.
1270
1271 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1272 the branch displacement. */
1273
1274#define BL_MASK 0xfc000001
1275#define BL_INSTRUCTION 0x48000001
1276#define BL_DISPLACEMENT_MASK 0x03fffffc
1277
de9f48f0
JG		 1278static unsigned long
1279rs6000_fetch_instruction (const CORE_ADDR pc)
1280{
1281 gdb_byte buf[4];
1282 unsigned long op;
1283
1284 /* Fetch the instruction and convert it to an integer. */
1285 if (target_read_memory (pc, buf, 4))
1286 return 0;
1287 op = extract_unsigned_integer (buf, 4);
1288
1289 return op;
1290}
1291
1292/* GCC generates several well-known sequences of instructions at the begining
1293 of each function prologue when compiling with -fstack-check. If one of
1294 such sequences starts at START_PC, then return the address of the
1295 instruction immediately past this sequence. Otherwise, return START_PC. */
1296
1297static CORE_ADDR
1298rs6000_skip_stack_check (const CORE_ADDR start_pc)
1299{
1300 CORE_ADDR pc = start_pc;
1301 unsigned long op = rs6000_fetch_instruction (pc);
1302
1303 /* First possible sequence: A small number of probes.
1304 stw 0, -<some immediate>(1)
1305 [repeat this instruction any (small) number of times]
1306 */
1307
1308 if ((op & 0xffff0000) == 0x90010000)
1309 {
1310 while ((op & 0xffff0000) == 0x90010000)
1311 {
1312 pc = pc + 4;
1313 op = rs6000_fetch_instruction (pc);
1314 }
1315 return pc;
1316 }
1317
1318 /* Second sequence: A probing loop.
1319 addi 12,1,-<some immediate>
1320 lis 0,-<some immediate>
1321 [possibly ori 0,0,<some immediate>]
1322 add 0,12,0
1323 cmpw 0,12,0
1324 beq 0,<disp>
1325 addi 12,12,-<some immediate>
1326 stw 0,0(12)
1327 b <disp>
1328 [possibly one last probe: stw 0,<some immediate>(12)]
1329 */
1330
1331 while (1)
1332 {
1333 /* addi 12,1,-<some immediate> */
1334 if ((op & 0xffff0000) != 0x39810000)
1335 break;
1336
1337 /* lis 0,-<some immediate> */
1338 pc = pc + 4;
1339 op = rs6000_fetch_instruction (pc);
1340 if ((op & 0xffff0000) != 0x3c000000)
1341 break;
1342
1343 pc = pc + 4;
1344 op = rs6000_fetch_instruction (pc);
1345 /* [possibly ori 0,0,<some immediate>] */
1346 if ((op & 0xffff0000) == 0x60000000)
1347 {
1348 pc = pc + 4;
1349 op = rs6000_fetch_instruction (pc);
1350 }
1351 /* add 0,12,0 */
1352 if (op != 0x7c0c0214)
1353 break;
1354
1355 /* cmpw 0,12,0 */
1356 pc = pc + 4;
1357 op = rs6000_fetch_instruction (pc);
1358 if (op != 0x7c0c0000)
1359 break;
1360
1361 /* beq 0,<disp> */
1362 pc = pc + 4;
1363 op = rs6000_fetch_instruction (pc);
1364 if ((op & 0xff9f0001) != 0x41820000)
1365 break;
1366
1367 /* addi 12,12,-<some immediate> */
1368 pc = pc + 4;
1369 op = rs6000_fetch_instruction (pc);
1370 if ((op & 0xffff0000) != 0x398c0000)
1371 break;
1372
1373 /* stw 0,0(12) */
1374 pc = pc + 4;
1375 op = rs6000_fetch_instruction (pc);
1376 if (op != 0x900c0000)
1377 break;
1378
1379 /* b <disp> */
1380 pc = pc + 4;
1381 op = rs6000_fetch_instruction (pc);
1382 if ((op & 0xfc000001) != 0x48000000)
1383 break;
1384
1385 /* [possibly one last probe: stw 0,<some immediate>(12)] */
1386 pc = pc + 4;
1387 op = rs6000_fetch_instruction (pc);
1388 if ((op & 0xffff0000) == 0x900c0000)
1389 {
1390 pc = pc + 4;
1391 op = rs6000_fetch_instruction (pc);
1392 }
1393
1394 /* We found a valid stack-check sequence, return the new PC. */
1395 return pc;
1396 }
1397
1398 /* Third sequence: No probe; instead, a comparizon between the stack size
1399 limit (saved in a run-time global variable) and the current stack
1400 pointer:
1401
1402 addi 0,1,-<some immediate>
1403 lis 12,__gnat_stack_limit@ha
1404 lwz 12,__gnat_stack_limit@l(12)
1405 twllt 0,12
1406
1407 or, with a small variant in the case of a bigger stack frame:
1408 addis 0,1,<some immediate>
1409 addic 0,0,-<some immediate>
1410 lis 12,__gnat_stack_limit@ha
1411 lwz 12,__gnat_stack_limit@l(12)
1412 twllt 0,12
1413 */
1414 while (1)
1415 {
1416 /* addi 0,1,-<some immediate> */
1417 if ((op & 0xffff0000) != 0x38010000)
1418 {
1419 /* small stack frame variant not recognized; try the
1420 big stack frame variant: */
1421
1422 /* addis 0,1,<some immediate> */
1423 if ((op & 0xffff0000) != 0x3c010000)
1424 break;
1425
1426 /* addic 0,0,-<some immediate> */
1427 pc = pc + 4;
1428 op = rs6000_fetch_instruction (pc);
1429 if ((op & 0xffff0000) != 0x30000000)
1430 break;
1431 }
1432
1433 /* lis 12,<some immediate> */
1434 pc = pc + 4;
1435 op = rs6000_fetch_instruction (pc);
1436 if ((op & 0xffff0000) != 0x3d800000)
1437 break;
1438
1439 /* lwz 12,<some immediate>(12) */
1440 pc = pc + 4;
1441 op = rs6000_fetch_instruction (pc);
1442 if ((op & 0xffff0000) != 0x818c0000)
1443 break;
1444
1445 /* twllt 0,12 */
1446 pc = pc + 4;
1447 op = rs6000_fetch_instruction (pc);
1448 if ((op & 0xfffffffe) != 0x7c406008)
1449 break;
1450
1451 /* We found a valid stack-check sequence, return the new PC. */
1452 return pc;
1453 }
1454
1455 /* No stack check code in our prologue, return the start_pc. */
1456 return start_pc;
1457}
1458
6a16c029
TJB		 1459/* return pc value after skipping a function prologue and also return
1460 information about a function frame.
1461
1462 in struct rs6000_framedata fdata:
1463 - frameless is TRUE, if function does not have a frame.
1464 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1465 - offset is the initial size of this stack frame --- the amount by
1466 which we decrement the sp to allocate the frame.
1467 - saved_gpr is the number of the first saved gpr.
1468 - saved_fpr is the number of the first saved fpr.
1469 - saved_vr is the number of the first saved vr.
1470 - saved_ev is the number of the first saved ev.
1471 - alloca_reg is the number of the register used for alloca() handling.
1472 Otherwise -1.
1473 - gpr_offset is the offset of the first saved gpr from the previous frame.
1474 - fpr_offset is the offset of the first saved fpr from the previous frame.
1475 - vr_offset is the offset of the first saved vr from the previous frame.
1476 - ev_offset is the offset of the first saved ev from the previous frame.
1477 - lr_offset is the offset of the saved lr
1478 - cr_offset is the offset of the saved cr
1479 - vrsave_offset is the offset of the saved vrsave register
1480 */
1481
7a78ae4e 1482static CORE_ADDR
be8626e0
MD		 1483skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc,
1484 struct rs6000_framedata *fdata)
c906108c
SS		 1485{
1486 CORE_ADDR orig_pc = pc;
55d05f3b 1487 CORE_ADDR last_prologue_pc = pc;
6be8bc0c 1488 CORE_ADDR li_found_pc = 0;
50fd1280 1489 gdb_byte buf[4];
c906108c
SS		 1490 unsigned long op;
1491 long offset = 0;
6be8bc0c 1492 long vr_saved_offset = 0;
482ca3f5
KB		 1493 int lr_reg = -1;
1494 int cr_reg = -1;
6be8bc0c 1495 int vr_reg = -1;
96ff0de4
EZ		 1496 int ev_reg = -1;
1497 long ev_offset = 0;
6be8bc0c 1498 int vrsave_reg = -1;
c906108c
SS		 1499 int reg;
1500 int framep = 0;
1501 int minimal_toc_loaded = 0;
ddb20c56 1502 int prev_insn_was_prologue_insn = 1;
55d05f3b 1503 int num_skip_non_prologue_insns = 0;
773df3e5 1504 int r0_contains_arg = 0;
be8626e0
MD		 1505 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch);
1506 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
c906108c 1507
ddb20c56 1508 memset (fdata, 0, sizeof (struct rs6000_framedata));
c906108c
SS		 1509 fdata->saved_gpr = -1;
1510 fdata->saved_fpr = -1;
6be8bc0c 1511 fdata->saved_vr = -1;
96ff0de4 1512 fdata->saved_ev = -1;
c906108c
SS		 1513 fdata->alloca_reg = -1;
1514 fdata->frameless = 1;
1515 fdata->nosavedpc = 1;
46a9b8ed 1516 fdata->lr_register = -1;
c906108c 1517
de9f48f0
JG		 1518 pc = rs6000_skip_stack_check (pc);
1519 if (pc >= lim_pc)
1520 pc = lim_pc;
1521
55d05f3b 1522 for (;; pc += 4)
c906108c 1523 {
ddb20c56
KB		 1524 /* Sometimes it isn't clear if an instruction is a prologue
1525 instruction or not. When we encounter one of these ambiguous
1526 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1527 Otherwise, we'll assume that it really is a prologue instruction. */
1528 if (prev_insn_was_prologue_insn)
1529 last_prologue_pc = pc;
55d05f3b
KB		 1530
1531 /* Stop scanning if we've hit the limit. */
4e463ff5 1532 if (pc >= lim_pc)
55d05f3b
KB		 1533 break;
1534
ddb20c56
KB		 1535 prev_insn_was_prologue_insn = 1;
1536
55d05f3b 1537 /* Fetch the instruction and convert it to an integer. */
ddb20c56
KB		 1538 if (target_read_memory (pc, buf, 4))
1539 break;
4e463ff5 1540 op = extract_unsigned_integer (buf, 4);
c906108c 1541
c5aa993b
JM		 1542 if ((op & 0xfc1fffff) == 0x7c0802a6)
1543 { /* mflr Rx */
43b1ab88
AC		 1544 /* Since shared library / PIC code, which needs to get its
1545 address at runtime, can appear to save more than one link
1546 register vis:
1547
1548 *INDENT-OFF*
1549 stwu r1,-304(r1)
1550 mflr r3
1551 bl 0xff570d0 (blrl)
1552 stw r30,296(r1)
1553 mflr r30
1554 stw r31,300(r1)
1555 stw r3,308(r1);
1556 ...
1557 *INDENT-ON*
1558
1559 remember just the first one, but skip over additional
1560 ones. */
721d14ba 1561 if (lr_reg == -1)
46a9b8ed 1562 lr_reg = (op & 0x03e00000) >> 21;
773df3e5
JB		 1563 if (lr_reg == 0)
1564 r0_contains_arg = 0;
c5aa993b 1565 continue;
c5aa993b
JM		 1566 }
1567 else if ((op & 0xfc1fffff) == 0x7c000026)
1568 { /* mfcr Rx */
98f08d3d 1569 cr_reg = (op & 0x03e00000);
773df3e5
JB		 1570 if (cr_reg == 0)
1571 r0_contains_arg = 0;
c5aa993b 1572 continue;
c906108c 1573
c906108c 1574 }
c5aa993b
JM		 1575 else if ((op & 0xfc1f0000) == 0xd8010000)
1576 { /* stfd Rx,NUM(r1) */
1577 reg = GET_SRC_REG (op);
1578 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1579 {
1580 fdata->saved_fpr = reg;
1581 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1582 }
1583 continue;
c906108c 1584
c5aa993b
JM		 1585 }
1586 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
7a78ae4e
ND		 1587 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1588 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1589 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
c5aa993b
JM		 1590 {
1591
1592 reg = GET_SRC_REG (op);
46a9b8ed
DJ		 1593 if ((op & 0xfc1f0000) == 0xbc010000)
1594 fdata->gpr_mask |= ~((1U << reg) - 1);
1595 else
1596 fdata->gpr_mask |= 1U << reg;
c5aa993b
JM		 1597 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1598 {
1599 fdata->saved_gpr = reg;
7a78ae4e 1600 if ((op & 0xfc1f0003) == 0xf8010000)
98f08d3d 1601 op &= ~3UL;
c5aa993b
JM		 1602 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1603 }
1604 continue;
c906108c 1605
ddb20c56
KB		 1606 }
1607 else if ((op & 0xffff0000) == 0x60000000)
1608 {
96ff0de4 1609 /* nop */
ddb20c56
KB		 1610 /* Allow nops in the prologue, but do not consider them to
1611 be part of the prologue unless followed by other prologue
1612 instructions. */
1613 prev_insn_was_prologue_insn = 0;
1614 continue;
1615
c906108c 1616 }
c5aa993b
JM		 1617 else if ((op & 0xffff0000) == 0x3c000000)
1618 { /* addis 0,0,NUM, used
1619 for >= 32k frames */
1620 fdata->offset = (op & 0x0000ffff) << 16;
1621 fdata->frameless = 0;
773df3e5 1622 r0_contains_arg = 0;
c5aa993b
JM		 1623 continue;
1624
1625 }
1626 else if ((op & 0xffff0000) == 0x60000000)
1627 { /* ori 0,0,NUM, 2nd ha
1628 lf of >= 32k frames */
1629 fdata->offset |= (op & 0x0000ffff);
1630 fdata->frameless = 0;
773df3e5 1631 r0_contains_arg = 0;
c5aa993b
JM		 1632 continue;
1633
1634 }
be723e22 1635 else if (lr_reg >= 0 &&
98f08d3d
KB		 1636 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1637 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1638 /* stw Rx, NUM(r1) */
1639 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1640 /* stwu Rx, NUM(r1) */
1641 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1642 { /* where Rx == lr */
1643 fdata->lr_offset = offset;
c5aa993b 1644 fdata->nosavedpc = 0;
be723e22
MS		 1645 /* Invalidate lr_reg, but don't set it to -1.
1646 That would mean that it had never been set. */
1647 lr_reg = -2;
98f08d3d
KB		 1648 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1649 (op & 0xfc000000) == 0x90000000) /* stw */
1650 {
1651 /* Does not update r1, so add displacement to lr_offset. */
1652 fdata->lr_offset += SIGNED_SHORT (op);
1653 }
c5aa993b
JM		 1654 continue;
1655
1656 }
be723e22 1657 else if (cr_reg >= 0 &&
98f08d3d
KB		 1658 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1659 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1660 /* stw Rx, NUM(r1) */
1661 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1662 /* stwu Rx, NUM(r1) */
1663 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1664 { /* where Rx == cr */
1665 fdata->cr_offset = offset;
be723e22
MS		 1666 /* Invalidate cr_reg, but don't set it to -1.
1667 That would mean that it had never been set. */
1668 cr_reg = -2;
98f08d3d
KB		 1669 if ((op & 0xfc000003) == 0xf8000000 ||
1670 (op & 0xfc000000) == 0x90000000)
1671 {
1672 /* Does not update r1, so add displacement to cr_offset. */
1673 fdata->cr_offset += SIGNED_SHORT (op);
1674 }
c5aa993b
JM		 1675 continue;
1676
1677 }
721d14ba
DJ		 1678 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1679 {
1680 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1681 prediction bits. If the LR has already been saved, we can
1682 skip it. */
1683 continue;
1684 }
c5aa993b
JM		 1685 else if (op == 0x48000005)
1686 { /* bl .+4 used in
1687 -mrelocatable */
46a9b8ed 1688 fdata->used_bl = 1;
c5aa993b
JM		 1689 continue;
1690
1691 }
1692 else if (op == 0x48000004)
1693 { /* b .+4 (xlc) */
1694 break;
1695
c5aa993b 1696 }
6be8bc0c
EZ		 1697 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1698 in V.4 -mminimal-toc */
c5aa993b
JM		 1699 (op & 0xffff0000) == 0x3bde0000)
1700 { /* addi 30,30,foo@l */
1701 continue;
c906108c 1702
c5aa993b
JM		 1703 }
1704 else if ((op & 0xfc000001) == 0x48000001)
1705 { /* bl foo,
1706 to save fprs??? */
c906108c 1707
c5aa993b 1708 fdata->frameless = 0;
3c77c82a
DJ		 1709
1710 /* If the return address has already been saved, we can skip
1711 calls to blrl (for PIC). */
1712 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op))
46a9b8ed
DJ		 1713 {
1714 fdata->used_bl = 1;
1715 continue;
1716 }
3c77c82a 1717
6be8bc0c 1718 /* Don't skip over the subroutine call if it is not within
ebd98106
FF		 1719 the first three instructions of the prologue and either
1720 we have no line table information or the line info tells
1721 us that the subroutine call is not part of the line
1722 associated with the prologue. */
c5aa993b 1723 if ((pc - orig_pc) > 8)
ebd98106
FF		 1724 {
1725 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1726 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1727
1728 if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line))
1729 break;
1730 }
c5aa993b
JM		 1731
1732 op = read_memory_integer (pc + 4, 4);
1733
6be8bc0c
EZ		 1734 /* At this point, make sure this is not a trampoline
1735 function (a function that simply calls another functions,
1736 and nothing else). If the next is not a nop, this branch
1737 was part of the function prologue. */
c5aa993b
JM		 1738
1739 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1740 break; /* don't skip over
1741 this branch */
c5aa993b 1742
46a9b8ed
DJ		 1743 fdata->used_bl = 1;
1744 continue;
c5aa993b 1745 }
98f08d3d
KB		 1746 /* update stack pointer */
1747 else if ((op & 0xfc1f0000) == 0x94010000)
1748 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
c5aa993b
JM		 1749 fdata->frameless = 0;
1750 fdata->offset = SIGNED_SHORT (op);
1751 offset = fdata->offset;
1752 continue;
c5aa993b 1753 }
98f08d3d
KB		 1754 else if ((op & 0xfc1f016a) == 0x7c01016e)
1755 { /* stwux rX,r1,rY */
1756 /* no way to figure out what r1 is going to be */
1757 fdata->frameless = 0;
1758 offset = fdata->offset;
1759 continue;
1760 }
1761 else if ((op & 0xfc1f0003) == 0xf8010001)
1762 { /* stdu rX,NUM(r1) */
1763 fdata->frameless = 0;
1764 fdata->offset = SIGNED_SHORT (op & ~3UL);
1765 offset = fdata->offset;
1766 continue;
1767 }
1768 else if ((op & 0xfc1f016a) == 0x7c01016a)
1769 { /* stdux rX,r1,rY */
1770 /* no way to figure out what r1 is going to be */
c5aa993b
JM		 1771 fdata->frameless = 0;
1772 offset = fdata->offset;
1773 continue;
c5aa993b 1774 }
7313566f
FF		 1775 else if ((op & 0xffff0000) == 0x38210000)
1776 { /* addi r1,r1,SIMM */
1777 fdata->frameless = 0;
1778 fdata->offset += SIGNED_SHORT (op);
1779 offset = fdata->offset;
1780 continue;
1781 }
4e463ff5
DJ		 1782 /* Load up minimal toc pointer. Do not treat an epilogue restore
1783 of r31 as a minimal TOC load. */
98f08d3d
KB		 1784 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1785 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
4e463ff5 1786 && !framep
c5aa993b 1787 && !minimal_toc_loaded)
98f08d3d 1788 {
c5aa993b
JM		 1789 minimal_toc_loaded = 1;
1790 continue;
1791
f6077098
KB		 1792 /* move parameters from argument registers to local variable
1793 registers */
1794 }
1795 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1796 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1797 (((op >> 21) & 31) <= 10) &&
96ff0de4 1798 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
f6077098
KB		 1799 {
1800 continue;
1801
c5aa993b
JM		 1802 /* store parameters in stack */
1803 }
e802b915 1804 /* Move parameters from argument registers to temporary register. */
773df3e5 1805 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
e802b915 1806 {
c5aa993b
JM		 1807 continue;
1808
1809 /* Set up frame pointer */
1810 }
1811 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1812 || op == 0x7c3f0b78)
1813 { /* mr r31, r1 */
1814 fdata->frameless = 0;
1815 framep = 1;
6f99cb26 1816 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
c5aa993b
JM		 1817 continue;
1818
1819 /* Another way to set up the frame pointer. */
1820 }
1821 else if ((op & 0xfc1fffff) == 0x38010000)
1822 { /* addi rX, r1, 0x0 */
1823 fdata->frameless = 0;
1824 framep = 1;
6f99cb26
AC		 1825 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1826 + ((op & ~0x38010000) >> 21));
c5aa993b 1827 continue;
c5aa993b 1828 }
6be8bc0c
EZ		 1829 /* AltiVec related instructions. */
1830 /* Store the vrsave register (spr 256) in another register for
1831 later manipulation, or load a register into the vrsave
1832 register. 2 instructions are used: mfvrsave and
1833 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1834 and mtspr SPR256, Rn. */
1835 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1836 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1837 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1838 {
1839 vrsave_reg = GET_SRC_REG (op);
1840 continue;
1841 }
1842 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1843 {
1844 continue;
1845 }
1846 /* Store the register where vrsave was saved to onto the stack:
1847 rS is the register where vrsave was stored in a previous
1848 instruction. */
1849 /* 100100 sssss 00001 dddddddd dddddddd */
1850 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1851 {
1852 if (vrsave_reg == GET_SRC_REG (op))
1853 {
1854 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1855 vrsave_reg = -1;
1856 }
1857 continue;
1858 }
1859 /* Compute the new value of vrsave, by modifying the register
1860 where vrsave was saved to. */
1861 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1862 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1863 {
1864 continue;
1865 }
1866 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1867 in a pair of insns to save the vector registers on the
1868 stack. */
1869 /* 001110 00000 00000 iiii iiii iiii iiii */
96ff0de4
EZ		 1870 /* 001110 01110 00000 iiii iiii iiii iiii */
1871 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1872 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
6be8bc0c 1873 {
773df3e5
JB		 1874 if ((op & 0xffff0000) == 0x38000000)
1875 r0_contains_arg = 0;
6be8bc0c
EZ		 1876 li_found_pc = pc;
1877 vr_saved_offset = SIGNED_SHORT (op);
773df3e5
JB		 1878
1879 /* This insn by itself is not part of the prologue, unless
1880 if part of the pair of insns mentioned above. So do not
1881 record this insn as part of the prologue yet. */
1882 prev_insn_was_prologue_insn = 0;
6be8bc0c
EZ		 1883 }
1884 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1885 /* 011111 sssss 11111 00000 00111001110 */
1886 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1887 {
1888 if (pc == (li_found_pc + 4))
1889 {
1890 vr_reg = GET_SRC_REG (op);
1891 /* If this is the first vector reg to be saved, or if
1892 it has a lower number than others previously seen,
1893 reupdate the frame info. */
1894 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1895 {
1896 fdata->saved_vr = vr_reg;
1897 fdata->vr_offset = vr_saved_offset + offset;
1898 }
1899 vr_saved_offset = -1;
1900 vr_reg = -1;
1901 li_found_pc = 0;
1902 }
1903 }
1904 /* End AltiVec related instructions. */
96ff0de4
EZ		 1905
1906 /* Start BookE related instructions. */
1907 /* Store gen register S at (r31+uimm).
1908 Any register less than r13 is volatile, so we don't care. */
1909 /* 000100 sssss 11111 iiiii 01100100001 */
1910 else if (arch_info->mach == bfd_mach_ppc_e500
1911 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1912 {
1913 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1914 {
1915 unsigned int imm;
1916 ev_reg = GET_SRC_REG (op);
1917 imm = (op >> 11) & 0x1f;
1918 ev_offset = imm * 8;
1919 /* If this is the first vector reg to be saved, or if
1920 it has a lower number than others previously seen,
1921 reupdate the frame info. */
1922 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1923 {
1924 fdata->saved_ev = ev_reg;
1925 fdata->ev_offset = ev_offset + offset;
1926 }
1927 }
1928 continue;
1929 }
1930 /* Store gen register rS at (r1+rB). */
1931 /* 000100 sssss 00001 bbbbb 01100100000 */
1932 else if (arch_info->mach == bfd_mach_ppc_e500
1933 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1934 {
1935 if (pc == (li_found_pc + 4))
1936 {
1937 ev_reg = GET_SRC_REG (op);
1938 /* If this is the first vector reg to be saved, or if
1939 it has a lower number than others previously seen,
1940 reupdate the frame info. */
1941 /* We know the contents of rB from the previous instruction. */
1942 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1943 {
1944 fdata->saved_ev = ev_reg;
1945 fdata->ev_offset = vr_saved_offset + offset;
1946 }
1947 vr_saved_offset = -1;
1948 ev_reg = -1;
1949 li_found_pc = 0;
1950 }
1951 continue;
1952 }
1953 /* Store gen register r31 at (rA+uimm). */
1954 /* 000100 11111 aaaaa iiiii 01100100001 */
1955 else if (arch_info->mach == bfd_mach_ppc_e500
1956 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1957 {
1958 /* Wwe know that the source register is 31 already, but
1959 it can't hurt to compute it. */
1960 ev_reg = GET_SRC_REG (op);
1961 ev_offset = ((op >> 11) & 0x1f) * 8;
1962 /* If this is the first vector reg to be saved, or if
1963 it has a lower number than others previously seen,
1964 reupdate the frame info. */
1965 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1966 {
1967 fdata->saved_ev = ev_reg;
1968 fdata->ev_offset = ev_offset + offset;
1969 }
1970
1971 continue;
1972 }
1973 /* Store gen register S at (r31+r0).
1974 Store param on stack when offset from SP bigger than 4 bytes. */
1975 /* 000100 sssss 11111 00000 01100100000 */
1976 else if (arch_info->mach == bfd_mach_ppc_e500
1977 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1978 {
1979 if (pc == (li_found_pc + 4))
1980 {
1981 if ((op & 0x03e00000) >= 0x01a00000)
1982 {
1983 ev_reg = GET_SRC_REG (op);
1984 /* If this is the first vector reg to be saved, or if
1985 it has a lower number than others previously seen,
1986 reupdate the frame info. */
1987 /* We know the contents of r0 from the previous
1988 instruction. */
1989 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1990 {
1991 fdata->saved_ev = ev_reg;
1992 fdata->ev_offset = vr_saved_offset + offset;
1993 }
1994 ev_reg = -1;
1995 }
1996 vr_saved_offset = -1;
1997 li_found_pc = 0;
1998 continue;
1999 }
2000 }
2001 /* End BookE related instructions. */
2002
c5aa993b
JM		 2003 else
2004 {
46a9b8ed
DJ		 2005 unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1);
2006
55d05f3b
KB		 2007 /* Not a recognized prologue instruction.
2008 Handle optimizer code motions into the prologue by continuing
2009 the search if we have no valid frame yet or if the return
46a9b8ed
DJ		 2010 address is not yet saved in the frame. Also skip instructions
2011 if some of the GPRs expected to be saved are not yet saved. */
2012 if (fdata->frameless == 0 && fdata->nosavedpc == 0
2013 && (fdata->gpr_mask & all_mask) == all_mask)
55d05f3b
KB		 2014 break;
2015
2016 if (op == 0x4e800020 /* blr */
2017 || op == 0x4e800420) /* bctr */
2018 /* Do not scan past epilogue in frameless functions or
2019 trampolines. */
2020 break;
2021 if ((op & 0xf4000000) == 0x40000000) /* bxx */
64366f1c 2022 /* Never skip branches. */
55d05f3b
KB		 2023 break;
2024
2025 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
2026 /* Do not scan too many insns, scanning insns is expensive with
2027 remote targets. */
2028 break;
2029
2030 /* Continue scanning. */
2031 prev_insn_was_prologue_insn = 0;
2032 continue;
c5aa993b 2033 }
c906108c
SS		 2034 }
2035
2036#if 0
2037/* I have problems with skipping over __main() that I need to address
2038 * sometime. Previously, I used to use misc_function_vector which
2039 * didn't work as well as I wanted to be. -MGO */
2040
2041 /* If the first thing after skipping a prolog is a branch to a function,
2042 this might be a call to an initializer in main(), introduced by gcc2.
64366f1c 2043 We'd like to skip over it as well. Fortunately, xlc does some extra
c906108c 2044 work before calling a function right after a prologue, thus we can
64366f1c 2045 single out such gcc2 behaviour. */
c906108c 2046
c906108c 2047
c5aa993b
JM		 2048 if ((op & 0xfc000001) == 0x48000001)
2049 { /* bl foo, an initializer function? */
2050 op = read_memory_integer (pc + 4, 4);
2051
2052 if (op == 0x4def7b82)
2053 { /* cror 0xf, 0xf, 0xf (nop) */
c906108c 2054
64366f1c
EZ		 2055 /* Check and see if we are in main. If so, skip over this
2056 initializer function as well. */
c906108c 2057
c5aa993b 2058 tmp = find_pc_misc_function (pc);
6314a349
AC		 2059 if (tmp >= 0
2060 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
c5aa993b
JM		 2061 return pc + 8;
2062 }
c906108c 2063 }
c906108c 2064#endif /* 0 */
c5aa993b 2065
46a9b8ed
DJ		 2066 if (pc == lim_pc && lr_reg >= 0)
2067 fdata->lr_register = lr_reg;
2068
c5aa993b 2069 fdata->offset = -fdata->offset;
ddb20c56 2070 return last_prologue_pc;
c906108c
SS		 2071}
2072
7a78ae4e 2073static CORE_ADDR
4a7622d1 2074rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
c906108c 2075{
4a7622d1
UW		 2076 struct rs6000_framedata frame;
2077 CORE_ADDR limit_pc, func_addr;
c906108c 2078
4a7622d1
UW		 2079 /* See if we can determine the end of the prologue via the symbol table.
2080 If so, then return either PC, or the PC after the prologue, whichever
2081 is greater. */
2082 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
c5aa993b 2083 {
d80b854b
UW		 2084 CORE_ADDR post_prologue_pc
2085 = skip_prologue_using_sal (gdbarch, func_addr);
4a7622d1
UW		 2086 if (post_prologue_pc != 0)
2087 return max (pc, post_prologue_pc);
c906108c 2088 }
c906108c 2089
4a7622d1
UW		 2090 /* Can't determine prologue from the symbol table, need to examine
2091 instructions. */
c906108c 2092
4a7622d1
UW		 2093 /* Find an upper limit on the function prologue using the debug
2094 information. If the debug information could not be used to provide
2095 that bound, then use an arbitrary large number as the upper bound. */
d80b854b 2096 limit_pc = skip_prologue_using_sal (gdbarch, pc);
4a7622d1
UW		 2097 if (limit_pc == 0)
2098 limit_pc = pc + 100; /* Magic. */
794a477a 2099
4a7622d1
UW		 2100 pc = skip_prologue (gdbarch, pc, limit_pc, &frame);
2101 return pc;
c906108c 2102}
c906108c 2103
8ab3d180
KB		 2104/* When compiling for EABI, some versions of GCC emit a call to __eabi
2105 in the prologue of main().
2106
2107 The function below examines the code pointed at by PC and checks to
2108 see if it corresponds to a call to __eabi. If so, it returns the
2109 address of the instruction following that call. Otherwise, it simply
2110 returns PC. */
2111
63807e1d 2112static CORE_ADDR
8ab3d180
KB		 2113rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2114{
2115 gdb_byte buf[4];
2116 unsigned long op;
2117
2118 if (target_read_memory (pc, buf, 4))
2119 return pc;
2120 op = extract_unsigned_integer (buf, 4);
2121
2122 if ((op & BL_MASK) == BL_INSTRUCTION)
2123 {
2124 CORE_ADDR displ = op & BL_DISPLACEMENT_MASK;
2125 CORE_ADDR call_dest = pc + 4 + displ;
2126 struct minimal_symbol *s = lookup_minimal_symbol_by_pc (call_dest);
2127
2128 /* We check for ___eabi (three leading underscores) in addition
2129 to __eabi in case the GCC option "-fleading-underscore" was
2130 used to compile the program. */
2131 if (s != NULL
2132 && SYMBOL_LINKAGE_NAME (s) != NULL
2133 && (strcmp (SYMBOL_LINKAGE_NAME (s), "__eabi") == 0
2134 || strcmp (SYMBOL_LINKAGE_NAME (s), "___eabi") == 0))
2135 pc += 4;
2136 }
2137 return pc;
2138}
383f0f5b 2139
4a7622d1
UW		 2140/* All the ABI's require 16 byte alignment. */
2141static CORE_ADDR
2142rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2143{
2144 return (addr & -16);
c906108c
SS		 2145}
2146
977adac5
ND		 2147/* Return whether handle_inferior_event() should proceed through code
2148 starting at PC in function NAME when stepping.
2149
2150 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2151 handle memory references that are too distant to fit in instructions
2152 generated by the compiler. For example, if 'foo' in the following
2153 instruction:
2154
2155 lwz r9,foo(r2)
2156
2157 is greater than 32767, the linker might replace the lwz with a branch to
2158 somewhere in @FIX1 that does the load in 2 instructions and then branches
2159 back to where execution should continue.
2160
2161 GDB should silently step over @FIX code, just like AIX dbx does.
2ec664f5
MS		 2162 Unfortunately, the linker uses the "b" instruction for the
2163 branches, meaning that the link register doesn't get set.
2164 Therefore, GDB's usual step_over_function () mechanism won't work.
977adac5 2165
e76f05fa
UW		 2166 Instead, use the gdbarch_skip_trampoline_code and
2167 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2ec664f5 2168 @FIX code. */
977adac5 2169
63807e1d 2170static int
977adac5
ND		 2171rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
2172{
2173 return name && !strncmp (name, "@FIX", 4);
2174}
2175
2176/* Skip code that the user doesn't want to see when stepping:
2177
2178 1. Indirect function calls use a piece of trampoline code to do context
2179 switching, i.e. to set the new TOC table. Skip such code if we are on
2180 its first instruction (as when we have single-stepped to here).
2181
2182 2. Skip shared library trampoline code (which is different from
c906108c 2183 indirect function call trampolines).
977adac5
ND		 2184
2185 3. Skip bigtoc fixup code.
2186
c906108c 2187 Result is desired PC to step until, or NULL if we are not in
977adac5 2188 code that should be skipped. */
c906108c 2189
63807e1d 2190static CORE_ADDR
52f729a7 2191rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
c906108c 2192{
4a7622d1 2193 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
52f0bd74 2194 unsigned int ii, op;
977adac5 2195 int rel;
c906108c 2196 CORE_ADDR solib_target_pc;
977adac5 2197 struct minimal_symbol *msymbol;
c906108c 2198
c5aa993b
JM		 2199 static unsigned trampoline_code[] =
2200 {
2201 0x800b0000, /* l r0,0x0(r11) */
2202 0x90410014, /* st r2,0x14(r1) */
2203 0x7c0903a6, /* mtctr r0 */
2204 0x804b0004, /* l r2,0x4(r11) */
2205 0x816b0008, /* l r11,0x8(r11) */
2206 0x4e800420, /* bctr */
2207 0x4e800020, /* br */
2208 0
c906108c
SS		 2209 };
2210
977adac5
ND		 2211 /* Check for bigtoc fixup code. */
2212 msymbol = lookup_minimal_symbol_by_pc (pc);
2ec664f5 2213 if (msymbol
4a7622d1 2214 && rs6000_in_solib_return_trampoline (pc, SYMBOL_LINKAGE_NAME (msymbol)))
977adac5
ND		 2215 {
2216 /* Double-check that the third instruction from PC is relative "b". */
2217 op = read_memory_integer (pc + 8, 4);
2218 if ((op & 0xfc000003) == 0x48000000)
2219 {
2220 /* Extract bits 6-29 as a signed 24-bit relative word address and
2221 add it to the containing PC. */
2222 rel = ((int)(op << 6) >> 6);
2223 return pc + 8 + rel;
2224 }
2225 }
2226
c906108c 2227 /* If pc is in a shared library trampoline, return its target. */
52f729a7 2228 solib_target_pc = find_solib_trampoline_target (frame, pc);
c906108c
SS		 2229 if (solib_target_pc)
2230 return solib_target_pc;
2231
c5aa993b
JM		 2232 for (ii = 0; trampoline_code[ii]; ++ii)
2233 {
2234 op = read_memory_integer (pc + (ii * 4), 4);
2235 if (op != trampoline_code[ii])
2236 return 0;
2237 }
52f729a7 2238 ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination addr */
4a7622d1 2239 pc = read_memory_unsigned_integer (ii, tdep->wordsize); /* (r11) value */
c906108c
SS		 2240 return pc;
2241}
2242
794ac428
UW		 2243/* ISA-specific vector types. */
2244
2245static struct type *
2246rs6000_builtin_type_vec64 (struct gdbarch *gdbarch)
2247{
2248 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2249
2250 if (!tdep->ppc_builtin_type_vec64)
2251 {
df4df182
UW		 2252 const struct builtin_type *bt = builtin_type (gdbarch);
2253
794ac428
UW		 2254 /* The type we're building is this: */
2255#if 0
2256 union __gdb_builtin_type_vec64
2257 {
2258 int64_t uint64;
2259 float v2_float[2];
2260 int32_t v2_int32[2];
2261 int16_t v4_int16[4];
2262 int8_t v8_int8[8];
2263 };
2264#endif
2265
2266 struct type *t;
2267
e9bb382b
UW		 2268 t = arch_composite_type (gdbarch,
2269 "__ppc_builtin_type_vec64", TYPE_CODE_UNION);
df4df182 2270 append_composite_type_field (t, "uint64", bt->builtin_int64);
794ac428 2271 append_composite_type_field (t, "v2_float",
df4df182 2272 init_vector_type (bt->builtin_float, 2));
794ac428 2273 append_composite_type_field (t, "v2_int32",
df4df182 2274 init_vector_type (bt->builtin_int32, 2));
794ac428 2275 append_composite_type_field (t, "v4_int16",
df4df182 2276 init_vector_type (bt->builtin_int16, 4));
794ac428 2277 append_composite_type_field (t, "v8_int8",
df4df182 2278 init_vector_type (bt->builtin_int8, 8));
794ac428 2279
876cecd0 2280 TYPE_VECTOR (t) = 1;
794ac428
UW		 2281 TYPE_NAME (t) = "ppc_builtin_type_vec64";
2282 tdep->ppc_builtin_type_vec64 = t;
2283 }
2284
2285 return tdep->ppc_builtin_type_vec64;
2286}
2287
604c2f83
LM		 2288/* Vector 128 type. */
2289
2290static struct type *
2291rs6000_builtin_type_vec128 (struct gdbarch *gdbarch)
2292{
2293 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2294
2295 if (!tdep->ppc_builtin_type_vec128)
2296 {
df4df182
UW		 2297 const struct builtin_type *bt = builtin_type (gdbarch);
2298
604c2f83
LM		 2299 /* The type we're building is this
2300
2301 type = union __ppc_builtin_type_vec128 {
2302 uint128_t uint128;
2303 float v4_float[4];
2304 int32_t v4_int32[4];
2305 int16_t v8_int16[8];
2306 int8_t v16_int8[16];
2307 }
2308 */
2309
2310 struct type *t;
2311
e9bb382b
UW		 2312 t = arch_composite_type (gdbarch,
2313 "__ppc_builtin_type_vec128", TYPE_CODE_UNION);
df4df182 2314 append_composite_type_field (t, "uint128", bt->builtin_uint128);
604c2f83 2315 append_composite_type_field (t, "v4_float",
df4df182 2316 init_vector_type (bt->builtin_float, 4));
604c2f83 2317 append_composite_type_field (t, "v4_int32",
df4df182 2318 init_vector_type (bt->builtin_int32, 4));
604c2f83 2319 append_composite_type_field (t, "v8_int16",
df4df182 2320 init_vector_type (bt->builtin_int16, 8));
604c2f83 2321 append_composite_type_field (t, "v16_int8",
df4df182 2322 init_vector_type (bt->builtin_int8, 16));
604c2f83 2323
803e1097 2324 TYPE_VECTOR (t) = 1;
604c2f83
LM		 2325 TYPE_NAME (t) = "ppc_builtin_type_vec128";
2326 tdep->ppc_builtin_type_vec128 = t;
2327 }
2328
2329 return tdep->ppc_builtin_type_vec128;
2330}
2331
7cc46491
DJ		 2332/* Return the name of register number REGNO, or the empty string if it
2333 is an anonymous register. */
7a78ae4e 2334
fa88f677 2335static const char *
d93859e2 2336rs6000_register_name (struct gdbarch *gdbarch, int regno)
7a78ae4e 2337{
d93859e2 2338 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7a78ae4e 2339
7cc46491
DJ		 2340 /* The upper half "registers" have names in the XML description,
2341 but we present only the low GPRs and the full 64-bit registers
2342 to the user. */
2343 if (tdep->ppc_ev0_upper_regnum >= 0
2344 && tdep->ppc_ev0_upper_regnum <= regno
2345 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
2346 return "";
2347
604c2f83
LM		 2348 /* Hide the upper halves of the vs0~vs31 registers. */
2349 if (tdep->ppc_vsr0_regnum >= 0
2350 && tdep->ppc_vsr0_upper_regnum <= regno
2351 && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs)
2352 return "";
2353
7cc46491 2354 /* Check if the SPE pseudo registers are available. */
5a9e69ba 2355 if (IS_SPE_PSEUDOREG (tdep, regno))
7cc46491
DJ		 2356 {
2357 static const char *const spe_regnames[] = {
2358 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2359 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2360 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2361 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2362 };
2363 return spe_regnames[regno - tdep->ppc_ev0_regnum];
2364 }
2365
f949c649
TJB		 2366 /* Check if the decimal128 pseudo-registers are available. */
2367 if (IS_DFP_PSEUDOREG (tdep, regno))
2368 {
2369 static const char *const dfp128_regnames[] = {
2370 "dl0", "dl1", "dl2", "dl3",
2371 "dl4", "dl5", "dl6", "dl7",
2372 "dl8", "dl9", "dl10", "dl11",
2373 "dl12", "dl13", "dl14", "dl15"
2374 };
2375 return dfp128_regnames[regno - tdep->ppc_dl0_regnum];
2376 }
2377
604c2f83
LM		 2378 /* Check if this is a VSX pseudo-register. */
2379 if (IS_VSX_PSEUDOREG (tdep, regno))
2380 {
2381 static const char *const vsx_regnames[] = {
2382 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2383 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2384 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2385 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2386 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2387 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2388 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2389 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2390 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2391 };
2392 return vsx_regnames[regno - tdep->ppc_vsr0_regnum];
2393 }
2394
2395 /* Check if the this is a Extended FP pseudo-register. */
2396 if (IS_EFP_PSEUDOREG (tdep, regno))
2397 {
2398 static const char *const efpr_regnames[] = {
2399 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2400 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2401 "f46", "f47", "f48", "f49", "f50", "f51",
2402 "f52", "f53", "f54", "f55", "f56", "f57",
2403 "f58", "f59", "f60", "f61", "f62", "f63"
2404 };
2405 return efpr_regnames[regno - tdep->ppc_efpr0_regnum];
2406 }
2407
d93859e2 2408 return tdesc_register_name (gdbarch, regno);
7a78ae4e
ND		 2409}
2410
7cc46491
DJ		 2411/* Return the GDB type object for the "standard" data type of data in
2412 register N. */
7a78ae4e
ND		 2413
2414static struct type *
7cc46491 2415rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
7a78ae4e 2416{
691d145a 2417 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7a78ae4e 2418
7cc46491 2419 /* These are the only pseudo-registers we support. */
f949c649 2420 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
604c2f83
LM		 2421 || IS_DFP_PSEUDOREG (tdep, regnum)
2422 || IS_VSX_PSEUDOREG (tdep, regnum)
2423 || IS_EFP_PSEUDOREG (tdep, regnum));
7cc46491 2424
f949c649
TJB		 2425 /* These are the e500 pseudo-registers. */
2426 if (IS_SPE_PSEUDOREG (tdep, regnum))
2427 return rs6000_builtin_type_vec64 (gdbarch);
604c2f83
LM		 2428 else if (IS_DFP_PSEUDOREG (tdep, regnum))
2429 /* PPC decimal128 pseudo-registers. */
f949c649 2430 return builtin_type (gdbarch)->builtin_declong;
604c2f83
LM		 2431 else if (IS_VSX_PSEUDOREG (tdep, regnum))
2432 /* POWER7 VSX pseudo-registers. */
2433 return rs6000_builtin_type_vec128 (gdbarch);
2434 else
2435 /* POWER7 Extended FP pseudo-registers. */
2436 return builtin_type (gdbarch)->builtin_double;
7a78ae4e
ND		 2437}
2438
c44ca51c
AC		 2439/* Is REGNUM a member of REGGROUP? */
2440static int
7cc46491
DJ		 2441rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2442 struct reggroup *group)
c44ca51c
AC		 2443{
2444 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
c44ca51c 2445
7cc46491 2446 /* These are the only pseudo-registers we support. */
f949c649 2447 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
604c2f83
LM		 2448 || IS_DFP_PSEUDOREG (tdep, regnum)
2449 || IS_VSX_PSEUDOREG (tdep, regnum)
2450 || IS_EFP_PSEUDOREG (tdep, regnum));
c44ca51c 2451
604c2f83
LM		 2452 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2453 if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum))
f949c649 2454 return group == all_reggroup || group == vector_reggroup;
7cc46491 2455 else
604c2f83 2456 /* PPC decimal128 or Extended FP pseudo-registers. */
f949c649 2457 return group == all_reggroup || group == float_reggroup;
c44ca51c
AC		 2458}
2459
691d145a 2460/* The register format for RS/6000 floating point registers is always
64366f1c 2461 double, we need a conversion if the memory format is float. */
7a78ae4e
ND		 2462
2463static int
0abe36f5
MD		 2464rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum,
2465 struct type *type)
7a78ae4e 2466{
0abe36f5 2467 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7cc46491
DJ		 2468
2469 return (tdep->ppc_fp0_regnum >= 0
2470 && regnum >= tdep->ppc_fp0_regnum
2471 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs
2472 && TYPE_CODE (type) == TYPE_CODE_FLT
0dfff4cb
UW		 2473 && TYPE_LENGTH (type)
2474 != TYPE_LENGTH (builtin_type (gdbarch)->builtin_double));
7a78ae4e
ND		 2475}
2476
7a78ae4e 2477static void
691d145a
JB		 2478rs6000_register_to_value (struct frame_info *frame,
2479 int regnum,
2480 struct type *type,
50fd1280 2481 gdb_byte *to)
7a78ae4e 2482{
0dfff4cb 2483 struct gdbarch *gdbarch = get_frame_arch (frame);
50fd1280 2484 gdb_byte from[MAX_REGISTER_SIZE];
691d145a 2485
691d145a 2486 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
7a78ae4e 2487
691d145a 2488 get_frame_register (frame, regnum, from);
0dfff4cb
UW		 2489 convert_typed_floating (from, builtin_type (gdbarch)->builtin_double,
2490 to, type);
691d145a 2491}
7a292a7a 2492
7a78ae4e 2493static void
691d145a
JB		 2494rs6000_value_to_register (struct frame_info *frame,
2495 int regnum,
2496 struct type *type,
50fd1280 2497 const gdb_byte *from)
7a78ae4e 2498{
0dfff4cb 2499 struct gdbarch *gdbarch = get_frame_arch (frame);
50fd1280 2500 gdb_byte to[MAX_REGISTER_SIZE];
691d145a 2501
691d145a
JB		 2502 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2503
0dfff4cb
UW		 2504 convert_typed_floating (from, type,
2505 to, builtin_type (gdbarch)->builtin_double);
691d145a 2506 put_frame_register (frame, regnum, to);
7a78ae4e 2507}
c906108c 2508
6ced10dd
JB		 2509/* Move SPE vector register values between a 64-bit buffer and the two
2510 32-bit raw register halves in a regcache. This function handles
2511 both splitting a 64-bit value into two 32-bit halves, and joining
2512 two halves into a whole 64-bit value, depending on the function
2513 passed as the MOVE argument.
2514
2515 EV_REG must be the number of an SPE evN vector register --- a
2516 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2517 64-bit buffer.
2518
2519 Call MOVE once for each 32-bit half of that register, passing
2520 REGCACHE, the number of the raw register corresponding to that
2521 half, and the address of the appropriate half of BUFFER.
2522
2523 For example, passing 'regcache_raw_read' as the MOVE function will
2524 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2525 'regcache_raw_supply' will supply the contents of BUFFER to the
2526 appropriate pair of raw registers in REGCACHE.
2527
2528 You may need to cast away some 'const' qualifiers when passing
2529 MOVE, since this function can't tell at compile-time which of
2530 REGCACHE or BUFFER is acting as the source of the data. If C had
2531 co-variant type qualifiers, ... */
2532static void
2533e500_move_ev_register (void (*move) (struct regcache *regcache,
50fd1280 2534 int regnum, gdb_byte *buf),
6ced10dd 2535 struct regcache *regcache, int ev_reg,
50fd1280 2536 gdb_byte *buffer)
6ced10dd
JB		 2537{
2538 struct gdbarch *arch = get_regcache_arch (regcache);
2539 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2540 int reg_index;
50fd1280 2541 gdb_byte *byte_buffer = buffer;
6ced10dd 2542
5a9e69ba 2543 gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg));
6ced10dd
JB		 2544
2545 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2546
8b164abb 2547 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
6ced10dd
JB		 2548 {
2549 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
2550 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
2551 }
2552 else
2553 {
2554 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2555 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
2556 }
2557}
2558
c8001721
EZ		 2559static void
2560e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
50fd1280 2561 int reg_nr, gdb_byte *buffer)
f949c649
TJB		 2562{
2563 e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
2564}
2565
2566static void
2567e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2568 int reg_nr, const gdb_byte *buffer)
2569{
2570 e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *))
2571 regcache_raw_write,
2572 regcache, reg_nr, (gdb_byte *) buffer);
2573}
2574
604c2f83 2575/* Read method for DFP pseudo-registers. */
f949c649 2576static void
604c2f83 2577dfp_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
f949c649
TJB		 2578 int reg_nr, gdb_byte *buffer)
2579{
2580 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2581 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2582
2583 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2584 {
2585 /* Read two FP registers to form a whole dl register. */
2586 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2587 2 * reg_index, buffer);
2588 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2589 2 * reg_index + 1, buffer + 8);
2590 }
2591 else
2592 {
2593 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2594 2 * reg_index + 1, buffer + 8);
2595 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2596 2 * reg_index, buffer);
2597 }
2598}
2599
604c2f83 2600/* Write method for DFP pseudo-registers. */
f949c649 2601static void
604c2f83 2602dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
f949c649
TJB		 2603 int reg_nr, const gdb_byte *buffer)
2604{
2605 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2606 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2607
2608 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2609 {
2610 /* Write each half of the dl register into a separate
2611 FP register. */
2612 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2613 2 * reg_index, buffer);
2614 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2615 2 * reg_index + 1, buffer + 8);
2616 }
2617 else
2618 {
2619 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2620 2 * reg_index + 1, buffer + 8);
2621 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2622 2 * reg_index, buffer);
2623 }
2624}
2625
604c2f83
LM		 2626/* Read method for POWER7 VSX pseudo-registers. */
2627static void
2628vsx_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2629 int reg_nr, gdb_byte *buffer)
2630{
2631 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2632 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2633
2634 /* Read the portion that overlaps the VMX registers. */
2635 if (reg_index > 31)
2636 regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2637 reg_index - 32, buffer);
2638 else
2639 /* Read the portion that overlaps the FPR registers. */
2640 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2641 {
2642 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2643 reg_index, buffer);
2644 regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2645 reg_index, buffer + 8);
2646 }
2647 else
2648 {
2649 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2650 reg_index, buffer + 8);
2651 regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2652 reg_index, buffer);
2653 }
2654}
2655
2656/* Write method for POWER7 VSX pseudo-registers. */
2657static void
2658vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2659 int reg_nr, const gdb_byte *buffer)
2660{
2661 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2662 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2663
2664 /* Write the portion that overlaps the VMX registers. */
2665 if (reg_index > 31)
2666 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2667 reg_index - 32, buffer);
2668 else
2669 /* Write the portion that overlaps the FPR registers. */
2670 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2671 {
2672 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2673 reg_index, buffer);
2674 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2675 reg_index, buffer + 8);
2676 }
2677 else
2678 {
2679 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2680 reg_index, buffer + 8);
2681 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2682 reg_index, buffer);
2683 }
2684}
2685
2686/* Read method for POWER7 Extended FP pseudo-registers. */
2687static void
2688efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2689 int reg_nr, gdb_byte *buffer)
2690{
2691 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2692 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2693
2694 /* Read the portion that overlaps the VMX registers. */
2695 regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2696 reg_index, buffer);
2697}
2698
2699/* Write method for POWER7 Extended FP pseudo-registers. */
2700static void
2701efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2702 int reg_nr, const gdb_byte *buffer)
2703{
2704 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2705 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2706
2707 /* Write the portion that overlaps the VMX registers. */
2708 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2709 reg_index, buffer);
2710}
2711
f949c649
TJB		 2712static void
2713rs6000_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2714 int reg_nr, gdb_byte *buffer)
c8001721 2715{
6ced10dd 2716 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
c8001721
EZ		 2717 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2718
6ced10dd 2719 gdb_assert (regcache_arch == gdbarch);
f949c649 2720
5a9e69ba 2721 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
f949c649
TJB		 2722 e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2723 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
604c2f83
LM		 2724 dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2725 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2726 vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2727 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2728 efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
6ced10dd 2729 else
a44bddec 2730 internal_error (__FILE__, __LINE__,
f949c649
TJB		 2731 _("rs6000_pseudo_register_read: "
2732 "called on unexpected register '%s' (%d)"),
2733 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
c8001721
EZ		 2734}
2735
2736static void
f949c649
TJB		 2737rs6000_pseudo_register_write (struct gdbarch *gdbarch,
2738 struct regcache *regcache,
2739 int reg_nr, const gdb_byte *buffer)
c8001721 2740{
6ced10dd 2741 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
c8001721
EZ		 2742 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2743
6ced10dd 2744 gdb_assert (regcache_arch == gdbarch);
f949c649 2745
5a9e69ba 2746 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
f949c649
TJB		 2747 e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2748 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
604c2f83
LM		 2749 dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2750 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2751 vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2752 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2753 efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
6ced10dd 2754 else
a44bddec 2755 internal_error (__FILE__, __LINE__,
f949c649
TJB		 2756 _("rs6000_pseudo_register_write: "
2757 "called on unexpected register '%s' (%d)"),
2758 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
6ced10dd
JB		 2759}
2760
18ed0c4e 2761/* Convert a DBX STABS register number to a GDB register number. */
c8001721 2762static int
d3f73121 2763rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
c8001721 2764{
d3f73121 2765 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
c8001721 2766
9f744501
JB		 2767 if (0 <= num && num <= 31)
2768 return tdep->ppc_gp0_regnum + num;
2769 else if (32 <= num && num <= 63)
383f0f5b
JB		 2770 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2771 specifies registers the architecture doesn't have? Our
2772 callers don't check the value we return. */
366f009f 2773 return tdep->ppc_fp0_regnum + (num - 32);
18ed0c4e
JB		 2774 else if (77 <= num && num <= 108)
2775 return tdep->ppc_vr0_regnum + (num - 77);
9f744501
JB		 2776 else if (1200 <= num && num < 1200 + 32)
2777 return tdep->ppc_ev0_regnum + (num - 1200);
2778 else
2779 switch (num)
2780 {
2781 case 64:
2782 return tdep->ppc_mq_regnum;
2783 case 65:
2784 return tdep->ppc_lr_regnum;
2785 case 66:
2786 return tdep->ppc_ctr_regnum;
2787 case 76:
2788 return tdep->ppc_xer_regnum;
2789 case 109:
2790 return tdep->ppc_vrsave_regnum;
18ed0c4e
JB		 2791 case 110:
2792 return tdep->ppc_vrsave_regnum - 1; /* vscr */
867e2dc5 2793 case 111:
18ed0c4e 2794 return tdep->ppc_acc_regnum;
867e2dc5 2795 case 112:
18ed0c4e 2796 return tdep->ppc_spefscr_regnum;
9f744501
JB		 2797 default:
2798 return num;
2799 }
18ed0c4e 2800}
9f744501 2801
9f744501 2802
18ed0c4e
JB		 2803/* Convert a Dwarf 2 register number to a GDB register number. */
2804static int
d3f73121 2805rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
18ed0c4e 2806{
d3f73121 2807 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9f744501 2808
18ed0c4e
JB		 2809 if (0 <= num && num <= 31)
2810 return tdep->ppc_gp0_regnum + num;
2811 else if (32 <= num && num <= 63)
2812 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2813 specifies registers the architecture doesn't have? Our
2814 callers don't check the value we return. */
2815 return tdep->ppc_fp0_regnum + (num - 32);
2816 else if (1124 <= num && num < 1124 + 32)
2817 return tdep->ppc_vr0_regnum + (num - 1124);
2818 else if (1200 <= num && num < 1200 + 32)
2819 return tdep->ppc_ev0_regnum + (num - 1200);
2820 else
2821 switch (num)
2822 {
a489f789
AS		 2823 case 64:
2824 return tdep->ppc_cr_regnum;
18ed0c4e
JB		 2825 case 67:
2826 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2827 case 99:
2828 return tdep->ppc_acc_regnum;
2829 case 100:
2830 return tdep->ppc_mq_regnum;
2831 case 101:
2832 return tdep->ppc_xer_regnum;
2833 case 108:
2834 return tdep->ppc_lr_regnum;
2835 case 109:
2836 return tdep->ppc_ctr_regnum;
2837 case 356:
2838 return tdep->ppc_vrsave_regnum;
2839 case 612:
2840 return tdep->ppc_spefscr_regnum;
2841 default:
2842 return num;
2843 }
2188cbdd
EZ		 2844}
2845
4fc771b8
DJ		 2846/* Translate a .eh_frame register to DWARF register, or adjust a
2847 .debug_frame register. */
2848
2849static int
2850rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
2851{
2852 /* GCC releases before 3.4 use GCC internal register numbering in
2853 .debug_frame (and .debug_info, et cetera). The numbering is
2854 different from the standard SysV numbering for everything except
2855 for GPRs and FPRs. We can not detect this problem in most cases
2856 - to get accurate debug info for variables living in lr, ctr, v0,
2857 et cetera, use a newer version of GCC. But we must detect
2858 one important case - lr is in column 65 in .debug_frame output,
2859 instead of 108.
2860
2861 GCC 3.4, and the "hammer" branch, have a related problem. They
2862 record lr register saves in .debug_frame as 108, but still record
2863 the return column as 65. We fix that up too.
2864
2865 We can do this because 65 is assigned to fpsr, and GCC never
2866 generates debug info referring to it. To add support for
2867 handwritten debug info that restores fpsr, we would need to add a
2868 producer version check to this. */
2869 if (!eh_frame_p)
2870 {
2871 if (num == 65)
2872 return 108;
2873 else
2874 return num;
2875 }
2876
2877 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2878 internal register numbering; translate that to the standard DWARF2
2879 register numbering. */
2880 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */
2881 return num;
2882 else if (68 <= num && num <= 75) /* cr0-cr8 */
2883 return num - 68 + 86;
2884 else if (77 <= num && num <= 108) /* vr0-vr31 */
2885 return num - 77 + 1124;
2886 else
2887 switch (num)
2888 {
2889 case 64: /* mq */
2890 return 100;
2891 case 65: /* lr */
2892 return 108;
2893 case 66: /* ctr */
2894 return 109;
2895 case 76: /* xer */
2896 return 101;
2897 case 109: /* vrsave */
2898 return 356;
2899 case 110: /* vscr */
2900 return 67;
2901 case 111: /* spe_acc */
2902 return 99;
2903 case 112: /* spefscr */
2904 return 612;
2905 default:
2906 return num;
2907 }
2908}
c906108c 2909\f
c5aa993b 2910
7a78ae4e 2911/* Handling the various POWER/PowerPC variants. */
c906108c 2912
c906108c 2913/* Information about a particular processor variant. */
7a78ae4e 2914
c906108c 2915struct variant
c5aa993b
JM		 2916 {
2917 /* Name of this variant. */
2918 char *name;
c906108c 2919
c5aa993b
JM		 2920 /* English description of the variant. */
2921 char *description;
c906108c 2922
64366f1c 2923 /* bfd_arch_info.arch corresponding to variant. */
7a78ae4e
ND		 2924 enum bfd_architecture arch;
2925
64366f1c 2926 /* bfd_arch_info.mach corresponding to variant. */
7a78ae4e
ND		 2927 unsigned long mach;
2928
7cc46491
DJ		 2929 /* Target description for this variant. */
2930 struct target_desc **tdesc;
c5aa993b 2931 };
c906108c 2932
489461e2 2933static struct variant variants[] =
c906108c 2934{
7a78ae4e 2935 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
7284e1be 2936 bfd_mach_ppc, &tdesc_powerpc_altivec32},
7a78ae4e 2937 {"power", "POWER user-level", bfd_arch_rs6000,
7cc46491 2938 bfd_mach_rs6k, &tdesc_rs6000},
7a78ae4e 2939 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
7cc46491 2940 bfd_mach_ppc_403, &tdesc_powerpc_403},
7a78ae4e 2941 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
7cc46491 2942 bfd_mach_ppc_601, &tdesc_powerpc_601},
7a78ae4e 2943 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
7cc46491 2944 bfd_mach_ppc_602, &tdesc_powerpc_602},
7a78ae4e 2945 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
7cc46491 2946 bfd_mach_ppc_603, &tdesc_powerpc_603},
7a78ae4e 2947 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
7cc46491 2948 604, &tdesc_powerpc_604},
7a78ae4e 2949 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
7cc46491 2950 bfd_mach_ppc_403gc, &tdesc_powerpc_403gc},
7a78ae4e 2951 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
7cc46491 2952 bfd_mach_ppc_505, &tdesc_powerpc_505},
7a78ae4e 2953 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
7cc46491 2954 bfd_mach_ppc_860, &tdesc_powerpc_860},
7a78ae4e 2955 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
7cc46491 2956 bfd_mach_ppc_750, &tdesc_powerpc_750},
1fcc0bb8 2957 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
7cc46491 2958 bfd_mach_ppc_7400, &tdesc_powerpc_7400},
c8001721 2959 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
7cc46491 2960 bfd_mach_ppc_e500, &tdesc_powerpc_e500},
7a78ae4e 2961
5d57ee30
KB		 2962 /* 64-bit */
2963 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
7284e1be 2964 bfd_mach_ppc64, &tdesc_powerpc_altivec64},
7a78ae4e 2965 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
7cc46491 2966 bfd_mach_ppc_620, &tdesc_powerpc_64},
5d57ee30 2967 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
7cc46491 2968 bfd_mach_ppc_630, &tdesc_powerpc_64},
7a78ae4e 2969 {"a35", "PowerPC A35", bfd_arch_powerpc,
7cc46491 2970 bfd_mach_ppc_a35, &tdesc_powerpc_64},
5d57ee30 2971 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
7cc46491 2972 bfd_mach_ppc_rs64ii, &tdesc_powerpc_64},
5d57ee30 2973 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
7cc46491 2974 bfd_mach_ppc_rs64iii, &tdesc_powerpc_64},
5d57ee30 2975
64366f1c 2976 /* FIXME: I haven't checked the register sets of the following. */
7a78ae4e 2977 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
7cc46491 2978 bfd_mach_rs6k_rs1, &tdesc_rs6000},
7a78ae4e 2979 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
7cc46491 2980 bfd_mach_rs6k_rsc, &tdesc_rs6000},
7a78ae4e 2981 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
7cc46491 2982 bfd_mach_rs6k_rs2, &tdesc_rs6000},
7a78ae4e 2983
7cc46491 2984 {0, 0, 0, 0, 0}
c906108c
SS		 2985};
2986
7a78ae4e 2987/* Return the variant corresponding to architecture ARCH and machine number
64366f1c 2988 MACH. If no such variant exists, return null. */
c906108c 2989
7a78ae4e
ND		 2990static const struct variant *
2991find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
c906108c 2992{
7a78ae4e 2993 const struct variant *v;
c5aa993b 2994
7a78ae4e
ND		 2995 for (v = variants; v->name; v++)
2996 if (arch == v->arch && mach == v->mach)
2997 return v;
c906108c 2998
7a78ae4e 2999 return NULL;
c906108c 3000}
9364a0ef
EZ		 3001
3002static int
3003gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
3004{
ee4f0f76
DJ		 3005 if (!info->disassembler_options)
3006 info->disassembler_options = "any";
3007
40887e1a 3008 if (info->endian == BFD_ENDIAN_BIG)
9364a0ef
EZ		 3009 return print_insn_big_powerpc (memaddr, info);
3010 else
3011 return print_insn_little_powerpc (memaddr, info);
3012}
7a78ae4e 3013\f
61a65099
KB		 3014static CORE_ADDR
3015rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
3016{
3e8c568d 3017 return frame_unwind_register_unsigned (next_frame,
8b164abb 3018 gdbarch_pc_regnum (gdbarch));
61a65099
KB		 3019}
3020
3021static struct frame_id
1af5d7ce 3022rs6000_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
61a65099 3023{
1af5d7ce
UW		 3024 return frame_id_build (get_frame_register_unsigned
3025 (this_frame, gdbarch_sp_regnum (gdbarch)),
3026 get_frame_pc (this_frame));
61a65099
KB		 3027}
3028
3029struct rs6000_frame_cache
3030{
3031 CORE_ADDR base;
3032 CORE_ADDR initial_sp;
3033 struct trad_frame_saved_reg *saved_regs;
3034};
3035
3036static struct rs6000_frame_cache *
1af5d7ce 3037rs6000_frame_cache (struct frame_info *this_frame, void **this_cache)
61a65099
KB		 3038{
3039 struct rs6000_frame_cache *cache;
1af5d7ce 3040 struct gdbarch *gdbarch = get_frame_arch (this_frame);
61a65099
KB		 3041 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3042 struct rs6000_framedata fdata;
3043 int wordsize = tdep->wordsize;
e10b1c4c 3044 CORE_ADDR func, pc;
61a65099
KB		 3045
3046 if ((*this_cache) != NULL)
3047 return (*this_cache);
3048 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
3049 (*this_cache) = cache;
1af5d7ce 3050 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
61a65099 3051
1af5d7ce
UW		 3052 func = get_frame_func (this_frame);
3053 pc = get_frame_pc (this_frame);
be8626e0 3054 skip_prologue (gdbarch, func, pc, &fdata);
e10b1c4c
DJ		 3055
3056 /* Figure out the parent's stack pointer. */
3057
3058 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3059 address of the current frame. Things might be easier if the
3060 ->frame pointed to the outer-most address of the frame. In
3061 the mean time, the address of the prev frame is used as the
3062 base address of this frame. */
1af5d7ce
UW		 3063 cache->base = get_frame_register_unsigned
3064 (this_frame, gdbarch_sp_regnum (gdbarch));
e10b1c4c
DJ		 3065
3066 /* If the function appears to be frameless, check a couple of likely
3067 indicators that we have simply failed to find the frame setup.
3068 Two common cases of this are missing symbols (i.e.
ef02daa9 3069 get_frame_func returns the wrong address or 0), and assembly
e10b1c4c
DJ		 3070 stubs which have a fast exit path but set up a frame on the slow
3071 path.
3072
3073 If the LR appears to return to this function, then presume that
3074 we have an ABI compliant frame that we failed to find. */
3075 if (fdata.frameless && fdata.lr_offset == 0)
61a65099 3076 {
e10b1c4c
DJ		 3077 CORE_ADDR saved_lr;
3078 int make_frame = 0;
3079
1af5d7ce 3080 saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum);
e10b1c4c
DJ		 3081 if (func == 0 && saved_lr == pc)
3082 make_frame = 1;
3083 else if (func != 0)
3084 {
3085 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
3086 if (func == saved_func)
3087 make_frame = 1;
3088 }
3089
3090 if (make_frame)
3091 {
3092 fdata.frameless = 0;
de6a76fd 3093 fdata.lr_offset = tdep->lr_frame_offset;
e10b1c4c 3094 }
61a65099 3095 }
e10b1c4c
DJ		 3096
3097 if (!fdata.frameless)
3098 /* Frameless really means stackless. */
4a7622d1 3099 cache->base = read_memory_unsigned_integer (cache->base, wordsize);
e10b1c4c 3100
3e8c568d 3101 trad_frame_set_value (cache->saved_regs,
8b164abb 3102 gdbarch_sp_regnum (gdbarch), cache->base);
61a65099
KB		 3103
3104 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3105 All fpr's from saved_fpr to fp31 are saved. */
3106
3107 if (fdata.saved_fpr >= 0)
3108 {
3109 int i;
3110 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
383f0f5b
JB		 3111
3112 /* If skip_prologue says floating-point registers were saved,
3113 but the current architecture has no floating-point registers,
3114 then that's strange. But we have no indices to even record
3115 the addresses under, so we just ignore it. */
3116 if (ppc_floating_point_unit_p (gdbarch))
063715bf 3117 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
383f0f5b
JB		 3118 {
3119 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3120 fpr_addr += 8;
3121 }
61a65099
KB		 3122 }
3123
3124 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
46a9b8ed
DJ		 3125 All gpr's from saved_gpr to gpr31 are saved (except during the
3126 prologue). */
61a65099
KB		 3127
3128 if (fdata.saved_gpr >= 0)
3129 {
3130 int i;
3131 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
063715bf 3132 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
61a65099 3133 {
46a9b8ed
DJ		 3134 if (fdata.gpr_mask & (1U << i))
3135 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
61a65099
KB		 3136 gpr_addr += wordsize;
3137 }
3138 }
3139
3140 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3141 All vr's from saved_vr to vr31 are saved. */
3142 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3143 {
3144 if (fdata.saved_vr >= 0)
3145 {
3146 int i;
3147 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3148 for (i = fdata.saved_vr; i < 32; i++)
3149 {
3150 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3151 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3152 }
3153 }
3154 }
3155
3156 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3157 All vr's from saved_ev to ev31 are saved. ????? */
5a9e69ba 3158 if (tdep->ppc_ev0_regnum != -1)
61a65099
KB		 3159 {
3160 if (fdata.saved_ev >= 0)
3161 {
3162 int i;
3163 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
063715bf 3164 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
61a65099
KB		 3165 {
3166 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3167 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
3168 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3169 }
3170 }
3171 }
3172
3173 /* If != 0, fdata.cr_offset is the offset from the frame that
3174 holds the CR. */
3175 if (fdata.cr_offset != 0)
3176 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
3177
3178 /* If != 0, fdata.lr_offset is the offset from the frame that
3179 holds the LR. */
3180 if (fdata.lr_offset != 0)
3181 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
46a9b8ed
DJ		 3182 else if (fdata.lr_register != -1)
3183 cache->saved_regs[tdep->ppc_lr_regnum].realreg = fdata.lr_register;
61a65099 3184 /* The PC is found in the link register. */
8b164abb 3185 cache->saved_regs[gdbarch_pc_regnum (gdbarch)] =
3e8c568d 3186 cache->saved_regs[tdep->ppc_lr_regnum];
61a65099
KB		 3187
3188 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3189 holds the VRSAVE. */
3190 if (fdata.vrsave_offset != 0)
3191 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
3192
3193 if (fdata.alloca_reg < 0)
3194 /* If no alloca register used, then fi->frame is the value of the
3195 %sp for this frame, and it is good enough. */
1af5d7ce
UW		 3196 cache->initial_sp
3197 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
61a65099 3198 else
1af5d7ce
UW		 3199 cache->initial_sp
3200 = get_frame_register_unsigned (this_frame, fdata.alloca_reg);
61a65099
KB		 3201
3202 return cache;
3203}
3204
3205static void
1af5d7ce 3206rs6000_frame_this_id (struct frame_info *this_frame, void **this_cache,
61a65099
KB		 3207 struct frame_id *this_id)
3208{
1af5d7ce 3209 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099 3210 this_cache);
5b197912
UW		 3211 /* This marks the outermost frame. */
3212 if (info->base == 0)
3213 return;
3214
1af5d7ce 3215 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
61a65099
KB		 3216}
3217
1af5d7ce
UW		 3218static struct value *
3219rs6000_frame_prev_register (struct frame_info *this_frame,
3220 void **this_cache, int regnum)
61a65099 3221{
1af5d7ce 3222 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099 3223 this_cache);
1af5d7ce 3224 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
61a65099
KB		 3225}
3226
3227static const struct frame_unwind rs6000_frame_unwind =
3228{
3229 NORMAL_FRAME,
3230 rs6000_frame_this_id,
1af5d7ce
UW		 3231 rs6000_frame_prev_register,
3232 NULL,
3233 default_frame_sniffer
61a65099 3234};
61a65099
KB		 3235\f
3236
3237static CORE_ADDR
1af5d7ce 3238rs6000_frame_base_address (struct frame_info *this_frame, void **this_cache)
61a65099 3239{
1af5d7ce 3240 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099
KB		 3241 this_cache);
3242 return info->initial_sp;
3243}
3244
3245static const struct frame_base rs6000_frame_base = {
3246 &rs6000_frame_unwind,
3247 rs6000_frame_base_address,
3248 rs6000_frame_base_address,
3249 rs6000_frame_base_address
3250};
3251
3252static const struct frame_base *
1af5d7ce 3253rs6000_frame_base_sniffer (struct frame_info *this_frame)
61a65099
KB		 3254{
3255 return &rs6000_frame_base;
3256}
3257
9274a07c
LM		 3258/* DWARF-2 frame support. Used to handle the detection of
3259 clobbered registers during function calls. */
3260
3261static void
3262ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3263 struct dwarf2_frame_state_reg *reg,
4a4e5149 3264 struct frame_info *this_frame)
9274a07c
LM		 3265{
3266 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3267
3268 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3269 non-volatile registers. We will use the same code for both. */
3270
3271 /* Call-saved GP registers. */
3272 if ((regnum >= tdep->ppc_gp0_regnum + 14
3273 && regnum <= tdep->ppc_gp0_regnum + 31)
3274 || (regnum == tdep->ppc_gp0_regnum + 1))
3275 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3276
3277 /* Call-clobbered GP registers. */
3278 if ((regnum >= tdep->ppc_gp0_regnum + 3
3279 && regnum <= tdep->ppc_gp0_regnum + 12)
3280 || (regnum == tdep->ppc_gp0_regnum))
3281 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3282
3283 /* Deal with FP registers, if supported. */
3284 if (tdep->ppc_fp0_regnum >= 0)
3285 {
3286 /* Call-saved FP registers. */
3287 if ((regnum >= tdep->ppc_fp0_regnum + 14
3288 && regnum <= tdep->ppc_fp0_regnum + 31))
3289 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3290
3291 /* Call-clobbered FP registers. */
3292 if ((regnum >= tdep->ppc_fp0_regnum
3293 && regnum <= tdep->ppc_fp0_regnum + 13))
3294 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3295 }
3296
3297 /* Deal with ALTIVEC registers, if supported. */
3298 if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0)
3299 {
3300 /* Call-saved Altivec registers. */
3301 if ((regnum >= tdep->ppc_vr0_regnum + 20
3302 && regnum <= tdep->ppc_vr0_regnum + 31)
3303 || regnum == tdep->ppc_vrsave_regnum)
3304 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3305
3306 /* Call-clobbered Altivec registers. */
3307 if ((regnum >= tdep->ppc_vr0_regnum
3308 && regnum <= tdep->ppc_vr0_regnum + 19))
3309 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3310 }
3311
3312 /* Handle PC register and Stack Pointer correctly. */
40a6adc1 3313 if (regnum == gdbarch_pc_regnum (gdbarch))
9274a07c 3314 reg->how = DWARF2_FRAME_REG_RA;
40a6adc1 3315 else if (regnum == gdbarch_sp_regnum (gdbarch))
9274a07c
LM		 3316 reg->how = DWARF2_FRAME_REG_CFA;
3317}
3318
3319
7a78ae4e
ND		 3320/* Initialize the current architecture based on INFO. If possible, re-use an
3321 architecture from ARCHES, which is a list of architectures already created
3322 during this debugging session.
c906108c 3323
7a78ae4e 3324 Called e.g. at program startup, when reading a core file, and when reading
64366f1c 3325 a binary file. */
c906108c 3326
7a78ae4e
ND		 3327static struct gdbarch *
3328rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3329{
3330 struct gdbarch *gdbarch;
3331 struct gdbarch_tdep *tdep;
7cc46491 3332 int wordsize, from_xcoff_exec, from_elf_exec;
7a78ae4e
ND		 3333 enum bfd_architecture arch;
3334 unsigned long mach;
3335 bfd abfd;
5bf1c677 3336 asection *sect;
55eddb0f
DJ		 3337 enum auto_boolean soft_float_flag = powerpc_soft_float_global;
3338 int soft_float;
3339 enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
604c2f83
LM		 3340 int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0,
3341 have_vsx = 0;
7cc46491
DJ		 3342 int tdesc_wordsize = -1;
3343 const struct target_desc *tdesc = info.target_desc;
3344 struct tdesc_arch_data *tdesc_data = NULL;
f949c649 3345 int num_pseudoregs = 0;
604c2f83 3346 int cur_reg;
7a78ae4e 3347
9aa1e687 3348 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
7a78ae4e
ND		 3349 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3350
9aa1e687
KB		 3351 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3352 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3353
e712c1cf 3354 /* Check word size. If INFO is from a binary file, infer it from
64366f1c 3355 that, else choose a likely default. */
9aa1e687 3356 if (from_xcoff_exec)
c906108c 3357 {
11ed25ac 3358 if (bfd_xcoff_is_xcoff64 (info.abfd))
7a78ae4e
ND		 3359 wordsize = 8;
3360 else
3361 wordsize = 4;
c906108c 3362 }
9aa1e687
KB		 3363 else if (from_elf_exec)
3364 {
3365 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3366 wordsize = 8;
3367 else
3368 wordsize = 4;
3369 }
7cc46491
DJ		 3370 else if (tdesc_has_registers (tdesc))
3371 wordsize = -1;
c906108c 3372 else
7a78ae4e 3373 {
27b15785
KB		 3374 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3375 wordsize = info.bfd_arch_info->bits_per_word /
3376 info.bfd_arch_info->bits_per_byte;
3377 else
3378 wordsize = 4;
7a78ae4e 3379 }
c906108c 3380
475bbd17
JB		 3381 /* Get the architecture and machine from the BFD. */
3382 arch = info.bfd_arch_info->arch;
3383 mach = info.bfd_arch_info->mach;
5bf1c677
EZ		 3384
3385 /* For e500 executables, the apuinfo section is of help here. Such
3386 section contains the identifier and revision number of each
3387 Application-specific Processing Unit that is present on the
3388 chip. The content of the section is determined by the assembler
3389 which looks at each instruction and determines which unit (and
3390 which version of it) can execute it. In our case we just look for
3391 the existance of the section. */
3392
3393 if (info.abfd)
3394 {
3395 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
3396 if (sect)
3397 {
3398 arch = info.bfd_arch_info->arch;
3399 mach = bfd_mach_ppc_e500;
3400 bfd_default_set_arch_mach (&abfd, arch, mach);
3401 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3402 }
3403 }
3404
7cc46491
DJ		 3405 /* Find a default target description which describes our register
3406 layout, if we do not already have one. */
3407 if (! tdesc_has_registers (tdesc))
3408 {
3409 const struct variant *v;
3410
3411 /* Choose variant. */
3412 v = find_variant_by_arch (arch, mach);
3413 if (!v)
3414 return NULL;
3415
3416 tdesc = *v->tdesc;
3417 }
3418
3419 gdb_assert (tdesc_has_registers (tdesc));
3420
3421 /* Check any target description for validity. */
3422 if (tdesc_has_registers (tdesc))
3423 {
3424 static const char *const gprs[] = {
3425 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3426 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3427 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3428 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3429 };
3430 static const char *const segment_regs[] = {
3431 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
3432 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
3433 };
3434 const struct tdesc_feature *feature;
3435 int i, valid_p;
3436 static const char *const msr_names[] = { "msr", "ps" };
3437 static const char *const cr_names[] = { "cr", "cnd" };
3438 static const char *const ctr_names[] = { "ctr", "cnt" };
3439
3440 feature = tdesc_find_feature (tdesc,
3441 "org.gnu.gdb.power.core");
3442 if (feature == NULL)
3443 return NULL;
3444
3445 tdesc_data = tdesc_data_alloc ();
3446
3447 valid_p = 1;
3448 for (i = 0; i < ppc_num_gprs; i++)
3449 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]);
3450 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM,
3451 "pc");
3452 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM,
3453 "lr");
3454 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM,
3455 "xer");
3456
3457 /* Allow alternate names for these registers, to accomodate GDB's
3458 historic naming. */
3459 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3460 PPC_MSR_REGNUM, msr_names);
3461 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3462 PPC_CR_REGNUM, cr_names);
3463 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3464 PPC_CTR_REGNUM, ctr_names);
3465
3466 if (!valid_p)
3467 {
3468 tdesc_data_cleanup (tdesc_data);
3469 return NULL;
3470 }
3471
3472 have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM,
3473 "mq");
3474
3475 tdesc_wordsize = tdesc_register_size (feature, "pc") / 8;
3476 if (wordsize == -1)
3477 wordsize = tdesc_wordsize;
3478
3479 feature = tdesc_find_feature (tdesc,
3480 "org.gnu.gdb.power.fpu");
3481 if (feature != NULL)
3482 {
3483 static const char *const fprs[] = {
3484 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
3485 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
3486 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
3487 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
3488 };
3489 valid_p = 1;
3490 for (i = 0; i < ppc_num_fprs; i++)
3491 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3492 PPC_F0_REGNUM + i, fprs[i]);
3493 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3494 PPC_FPSCR_REGNUM, "fpscr");
3495
3496 if (!valid_p)
3497 {
3498 tdesc_data_cleanup (tdesc_data);
3499 return NULL;
3500 }
3501 have_fpu = 1;
3502 }
3503 else
3504 have_fpu = 0;
3505
f949c649
TJB		 3506 /* The DFP pseudo-registers will be available when there are floating
3507 point registers. */
3508 have_dfp = have_fpu;
3509
7cc46491
DJ		 3510 feature = tdesc_find_feature (tdesc,
3511 "org.gnu.gdb.power.altivec");
3512 if (feature != NULL)
3513 {
3514 static const char *const vector_regs[] = {
3515 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
3516 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
3517 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
3518 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
3519 };
3520
3521 valid_p = 1;
3522 for (i = 0; i < ppc_num_gprs; i++)
3523 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3524 PPC_VR0_REGNUM + i,
3525 vector_regs[i]);
3526 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3527 PPC_VSCR_REGNUM, "vscr");
3528 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3529 PPC_VRSAVE_REGNUM, "vrsave");
3530
3531 if (have_spe || !valid_p)
3532 {
3533 tdesc_data_cleanup (tdesc_data);
3534 return NULL;
3535 }
3536 have_altivec = 1;
3537 }
3538 else
3539 have_altivec = 0;
3540
604c2f83
LM		 3541 /* Check for POWER7 VSX registers support. */
3542 feature = tdesc_find_feature (tdesc,
3543 "org.gnu.gdb.power.vsx");
3544
3545 if (feature != NULL)
3546 {
3547 static const char *const vsx_regs[] = {
3548 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
3549 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
3550 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
3551 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
3552 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
3553 "vs30h", "vs31h"
3554 };
3555
3556 valid_p = 1;
3557
3558 for (i = 0; i < ppc_num_vshrs; i++)
3559 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3560 PPC_VSR0_UPPER_REGNUM + i,
3561 vsx_regs[i]);
3562 if (!valid_p)
3563 {
3564 tdesc_data_cleanup (tdesc_data);
3565 return NULL;
3566 }
3567
3568 have_vsx = 1;
3569 }
3570 else
3571 have_vsx = 0;
3572
7cc46491
DJ		 3573 /* On machines supporting the SPE APU, the general-purpose registers
3574 are 64 bits long. There are SIMD vector instructions to treat them
3575 as pairs of floats, but the rest of the instruction set treats them
3576 as 32-bit registers, and only operates on their lower halves.
3577
3578 In the GDB regcache, we treat their high and low halves as separate
3579 registers. The low halves we present as the general-purpose
3580 registers, and then we have pseudo-registers that stitch together
3581 the upper and lower halves and present them as pseudo-registers.
3582
3583 Thus, the target description is expected to supply the upper
3584 halves separately. */
3585
3586 feature = tdesc_find_feature (tdesc,
3587 "org.gnu.gdb.power.spe");
3588 if (feature != NULL)
3589 {
3590 static const char *const upper_spe[] = {
3591 "ev0h", "ev1h", "ev2h", "ev3h",
3592 "ev4h", "ev5h", "ev6h", "ev7h",
3593 "ev8h", "ev9h", "ev10h", "ev11h",
3594 "ev12h", "ev13h", "ev14h", "ev15h",
3595 "ev16h", "ev17h", "ev18h", "ev19h",
3596 "ev20h", "ev21h", "ev22h", "ev23h",
3597 "ev24h", "ev25h", "ev26h", "ev27h",
3598 "ev28h", "ev29h", "ev30h", "ev31h"
3599 };
3600
3601 valid_p = 1;
3602 for (i = 0; i < ppc_num_gprs; i++)
3603 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3604 PPC_SPE_UPPER_GP0_REGNUM + i,
3605 upper_spe[i]);
3606 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3607 PPC_SPE_ACC_REGNUM, "acc");
3608 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3609 PPC_SPE_FSCR_REGNUM, "spefscr");
3610
3611 if (have_mq || have_fpu || !valid_p)
3612 {
3613 tdesc_data_cleanup (tdesc_data);
3614 return NULL;
3615 }
3616 have_spe = 1;
3617 }
3618 else
3619 have_spe = 0;
3620 }
3621
3622 /* If we have a 64-bit binary on a 32-bit target, complain. Also
3623 complain for a 32-bit binary on a 64-bit target; we do not yet
3624 support that. For instance, the 32-bit ABI routines expect
3625 32-bit GPRs.
3626
3627 As long as there isn't an explicit target description, we'll
3628 choose one based on the BFD architecture and get a word size
3629 matching the binary (probably powerpc:common or
3630 powerpc:common64). So there is only trouble if a 64-bit target
3631 supplies a 64-bit description while debugging a 32-bit
3632 binary. */
3633 if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize)
3634 {
3635 tdesc_data_cleanup (tdesc_data);
3636 return NULL;
3637 }
3638
55eddb0f
DJ		 3639#ifdef HAVE_ELF
3640 if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec)
3641 {
3642 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3643 Tag_GNU_Power_ABI_FP))
3644 {
3645 case 1:
3646 soft_float_flag = AUTO_BOOLEAN_FALSE;
3647 break;
3648 case 2:
3649 soft_float_flag = AUTO_BOOLEAN_TRUE;
3650 break;
3651 default:
3652 break;
3653 }
3654 }
3655
3656 if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec)
3657 {
3658 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3659 Tag_GNU_Power_ABI_Vector))
3660 {
3661 case 1:
3662 vector_abi = POWERPC_VEC_GENERIC;
3663 break;
3664 case 2:
3665 vector_abi = POWERPC_VEC_ALTIVEC;
3666 break;
3667 case 3:
3668 vector_abi = POWERPC_VEC_SPE;
3669 break;
3670 default:
3671 break;
3672 }
3673 }
3674#endif
3675
3676 if (soft_float_flag == AUTO_BOOLEAN_TRUE)
3677 soft_float = 1;
3678 else if (soft_float_flag == AUTO_BOOLEAN_FALSE)
3679 soft_float = 0;
3680 else
3681 soft_float = !have_fpu;
3682
3683 /* If we have a hard float binary or setting but no floating point
3684 registers, downgrade to soft float anyway. We're still somewhat
3685 useful in this scenario. */
3686 if (!soft_float && !have_fpu)
3687 soft_float = 1;
3688
3689 /* Similarly for vector registers. */
3690 if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec)
3691 vector_abi = POWERPC_VEC_GENERIC;
3692
3693 if (vector_abi == POWERPC_VEC_SPE && !have_spe)
3694 vector_abi = POWERPC_VEC_GENERIC;
3695
3696 if (vector_abi == POWERPC_VEC_AUTO)
3697 {
3698 if (have_altivec)
3699 vector_abi = POWERPC_VEC_ALTIVEC;
3700 else if (have_spe)
3701 vector_abi = POWERPC_VEC_SPE;
3702 else
3703 vector_abi = POWERPC_VEC_GENERIC;
3704 }
3705
3706 /* Do not limit the vector ABI based on available hardware, since we
3707 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
3708
7cc46491
DJ		 3709 /* Find a candidate among extant architectures. */
3710 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3711 arches != NULL;
3712 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3713 {
3714 /* Word size in the various PowerPC bfd_arch_info structs isn't
3715 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3716 separate word size check. */
3717 tdep = gdbarch_tdep (arches->gdbarch);
55eddb0f
DJ		 3718 if (tdep && tdep->soft_float != soft_float)
3719 continue;
3720 if (tdep && tdep->vector_abi != vector_abi)
3721 continue;
7cc46491
DJ		 3722 if (tdep && tdep->wordsize == wordsize)
3723 {
3724 if (tdesc_data != NULL)
3725 tdesc_data_cleanup (tdesc_data);
3726 return arches->gdbarch;
3727 }
3728 }
3729
3730 /* None found, create a new architecture from INFO, whose bfd_arch_info
3731 validity depends on the source:
3732 - executable useless
3733 - rs6000_host_arch() good
3734 - core file good
3735 - "set arch" trust blindly
3736 - GDB startup useless but harmless */
3737
3738 tdep = XCALLOC (1, struct gdbarch_tdep);
3739 tdep->wordsize = wordsize;
55eddb0f
DJ		 3740 tdep->soft_float = soft_float;
3741 tdep->vector_abi = vector_abi;
7cc46491 3742
7a78ae4e 3743 gdbarch = gdbarch_alloc (&info, tdep);
7a78ae4e 3744
7cc46491
DJ		 3745 tdep->ppc_gp0_regnum = PPC_R0_REGNUM;
3746 tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2;
3747 tdep->ppc_ps_regnum = PPC_MSR_REGNUM;
3748 tdep->ppc_cr_regnum = PPC_CR_REGNUM;
3749 tdep->ppc_lr_regnum = PPC_LR_REGNUM;
3750 tdep->ppc_ctr_regnum = PPC_CTR_REGNUM;
3751 tdep->ppc_xer_regnum = PPC_XER_REGNUM;
3752 tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1;
3753
3754 tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1;
3755 tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1;
604c2f83 3756 tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1;
7cc46491
DJ		 3757 tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1;
3758 tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1;
3759 tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1;
3760 tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1;
3761 tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
3762
3763 set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
3764 set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3765 set_gdbarch_deprecated_fp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3766 set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum);
9f643768 3767 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
7cc46491
DJ		 3768
3769 /* The XML specification for PowerPC sensibly calls the MSR "msr".
3770 GDB traditionally called it "ps", though, so let GDB add an
3771 alias. */
3772 set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum);
3773
4a7622d1 3774 if (wordsize == 8)
05580c65 3775 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
afd48b75 3776 else
4a7622d1 3777 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
c8001721 3778
baffbae0
JB		 3779 /* Set lr_frame_offset. */
3780 if (wordsize == 8)
3781 tdep->lr_frame_offset = 16;
baffbae0 3782 else
4a7622d1 3783 tdep->lr_frame_offset = 4;
baffbae0 3784
604c2f83 3785 if (have_spe || have_dfp || have_vsx)
7cc46491 3786 {
f949c649
TJB		 3787 set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read);
3788 set_gdbarch_pseudo_register_write (gdbarch, rs6000_pseudo_register_write);
7cc46491 3789 }
1fcc0bb8 3790
e0d24f8d
WZ		 3791 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3792
56a6dfb9 3793 /* Select instruction printer. */
708ff411 3794 if (arch == bfd_arch_rs6000)
9364a0ef 3795 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
56a6dfb9 3796 else
9364a0ef 3797 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
7495d1dc 3798
5a9e69ba 3799 set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS);
f949c649
TJB		 3800
3801 if (have_spe)
3802 num_pseudoregs += 32;
3803 if (have_dfp)
3804 num_pseudoregs += 16;
604c2f83
LM		 3805 if (have_vsx)
3806 /* Include both VSX and Extended FP registers. */
3807 num_pseudoregs += 96;
f949c649
TJB		 3808
3809 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs);
7a78ae4e
ND		 3810
3811 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3812 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3813 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3814 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3815 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3816 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3817 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4a7622d1 3818 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
4e409299 3819 set_gdbarch_char_signed (gdbarch, 0);
7a78ae4e 3820
11269d7e 3821 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
4a7622d1 3822 if (wordsize == 8)
8b148df9
AC		 3823 /* PPC64 SYSV. */
3824 set_gdbarch_frame_red_zone_size (gdbarch, 288);
7a78ae4e 3825
691d145a
JB		 3826 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
3827 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
3828 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
3829
18ed0c4e
JB		 3830 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
3831 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
d217aaed 3832
4a7622d1 3833 if (wordsize == 4)
77b2b6d4 3834 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
4a7622d1 3835 else if (wordsize == 8)
8be9034a 3836 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
7a78ae4e 3837
7a78ae4e 3838 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
0d1243d9 3839 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
8ab3d180 3840 set_gdbarch_skip_main_prologue (gdbarch, rs6000_skip_main_prologue);
0d1243d9 3841
7a78ae4e 3842 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
7a78ae4e
ND		 3843 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
3844
203c3895
UW		 3845 /* The value of symbols of type N_SO and N_FUN maybe null when
3846 it shouldn't be. */
3847 set_gdbarch_sofun_address_maybe_missing (gdbarch, 1);
3848
ce5eab59 3849 /* Handles single stepping of atomic sequences. */
4a7622d1 3850 set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence);
ce5eab59 3851
7a78ae4e
ND		 3852 /* Not sure on this. FIXMEmgo */
3853 set_gdbarch_frame_args_skip (gdbarch, 8);
3854
143985b7
AF		 3855 /* Helpers for function argument information. */
3856 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
3857
6f7f3f0d
UW		 3858 /* Trampoline. */
3859 set_gdbarch_in_solib_return_trampoline
3860 (gdbarch, rs6000_in_solib_return_trampoline);
3861 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code);
3862
4fc771b8 3863 /* Hook in the DWARF CFI frame unwinder. */
1af5d7ce 3864 dwarf2_append_unwinders (gdbarch);
4fc771b8
DJ		 3865 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum);
3866
9274a07c
LM		 3867 /* Frame handling. */
3868 dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg);
3869
2454a024
UW		 3870 /* Setup displaced stepping. */
3871 set_gdbarch_displaced_step_copy_insn (gdbarch,
3872 simple_displaced_step_copy_insn);
3873 set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup);
3874 set_gdbarch_displaced_step_free_closure (gdbarch,
3875 simple_displaced_step_free_closure);
3876 set_gdbarch_displaced_step_location (gdbarch,
3877 displaced_step_at_entry_point);
3878
3879 set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE);
3880
7b112f9c 3881 /* Hook in ABI-specific overrides, if they have been registered. */
8a4c2d24
UW		 3882 info.target_desc = tdesc;
3883 info.tdep_info = (void *) tdesc_data;
4be87837 3884 gdbarch_init_osabi (info, gdbarch);
7b112f9c 3885
61a65099
KB		 3886 switch (info.osabi)
3887 {
f5aecab8 3888 case GDB_OSABI_LINUX:
61a65099
KB		 3889 case GDB_OSABI_NETBSD_AOUT:
3890 case GDB_OSABI_NETBSD_ELF:
3891 case GDB_OSABI_UNKNOWN:
61a65099 3892 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
1af5d7ce
UW		 3893 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
3894 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
61a65099
KB		 3895 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3896 break;
3897 default:
61a65099 3898 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
81332287
KB		 3899
3900 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
1af5d7ce
UW		 3901 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
3902 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
81332287 3903 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
61a65099
KB		 3904 }
3905
7cc46491
DJ		 3906 set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type);
3907 set_tdesc_pseudo_register_reggroup_p (gdbarch,
3908 rs6000_pseudo_register_reggroup_p);
3909 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3910
3911 /* Override the normal target description method to make the SPE upper
3912 halves anonymous. */
3913 set_gdbarch_register_name (gdbarch, rs6000_register_name);
3914
604c2f83
LM		 3915 /* Choose register numbers for all supported pseudo-registers. */
3916 tdep->ppc_ev0_regnum = -1;
3917 tdep->ppc_dl0_regnum = -1;
3918 tdep->ppc_vsr0_regnum = -1;
3919 tdep->ppc_efpr0_regnum = -1;
9f643768 3920
604c2f83
LM		 3921 cur_reg = gdbarch_num_regs (gdbarch);
3922
3923 if (have_spe)
3924 {
3925 tdep->ppc_ev0_regnum = cur_reg;
3926 cur_reg += 32;
3927 }
3928 if (have_dfp)
3929 {
3930 tdep->ppc_dl0_regnum = cur_reg;
3931 cur_reg += 16;
3932 }
3933 if (have_vsx)
3934 {
3935 tdep->ppc_vsr0_regnum = cur_reg;
3936 cur_reg += 64;
3937 tdep->ppc_efpr0_regnum = cur_reg;
3938 cur_reg += 32;
3939 }
f949c649 3940
604c2f83
LM		 3941 gdb_assert (gdbarch_num_regs (gdbarch)
3942 + gdbarch_num_pseudo_regs (gdbarch) == cur_reg);
f949c649 3943
7a78ae4e 3944 return gdbarch;
c906108c
SS		 3945}
3946
7b112f9c 3947static void
8b164abb 3948rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
7b112f9c 3949{
8b164abb 3950 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7b112f9c
JT		 3951
3952 if (tdep == NULL)
3953 return;
3954
4be87837 3955 /* FIXME: Dump gdbarch_tdep. */
7b112f9c
JT		 3956}
3957
55eddb0f
DJ		 3958/* PowerPC-specific commands. */
3959
3960static void
3961set_powerpc_command (char *args, int from_tty)
3962{
3963 printf_unfiltered (_("\
3964\"set powerpc\" must be followed by an appropriate subcommand.\n"));
3965 help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout);
3966}
3967
3968static void
3969show_powerpc_command (char *args, int from_tty)
3970{
3971 cmd_show_list (showpowerpccmdlist, from_tty, "");
3972}
3973
3974static void
3975powerpc_set_soft_float (char *args, int from_tty,
3976 struct cmd_list_element *c)
3977{
3978 struct gdbarch_info info;
3979
3980 /* Update the architecture. */
3981 gdbarch_info_init (&info);
3982 if (!gdbarch_update_p (info))
3983 internal_error (__FILE__, __LINE__, "could not update architecture");
3984}
3985
3986static void
3987powerpc_set_vector_abi (char *args, int from_tty,
3988 struct cmd_list_element *c)
3989{
3990 struct gdbarch_info info;
3991 enum powerpc_vector_abi vector_abi;
3992
3993 for (vector_abi = POWERPC_VEC_AUTO;
3994 vector_abi != POWERPC_VEC_LAST;
3995 vector_abi++)
3996 if (strcmp (powerpc_vector_abi_string,
3997 powerpc_vector_strings[vector_abi]) == 0)
3998 {
3999 powerpc_vector_abi_global = vector_abi;
4000 break;
4001 }
4002
4003 if (vector_abi == POWERPC_VEC_LAST)
4004 internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."),
4005 powerpc_vector_abi_string);
4006
4007 /* Update the architecture. */
4008 gdbarch_info_init (&info);
4009 if (!gdbarch_update_p (info))
4010 internal_error (__FILE__, __LINE__, "could not update architecture");
4011}
4012
c906108c
SS		 4013/* Initialization code. */
4014
a78f21af 4015extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
b9362cc7 4016
c906108c 4017void
fba45db2 4018_initialize_rs6000_tdep (void)
c906108c 4019{
7b112f9c
JT		 4020 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
4021 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
7cc46491
DJ		 4022
4023 /* Initialize the standard target descriptions. */
4024 initialize_tdesc_powerpc_32 ();
7284e1be 4025 initialize_tdesc_powerpc_altivec32 ();
604c2f83 4026 initialize_tdesc_powerpc_vsx32 ();
7cc46491
DJ		 4027 initialize_tdesc_powerpc_403 ();
4028 initialize_tdesc_powerpc_403gc ();
4029 initialize_tdesc_powerpc_505 ();
4030 initialize_tdesc_powerpc_601 ();
4031 initialize_tdesc_powerpc_602 ();
4032 initialize_tdesc_powerpc_603 ();
4033 initialize_tdesc_powerpc_604 ();
4034 initialize_tdesc_powerpc_64 ();
7284e1be 4035 initialize_tdesc_powerpc_altivec64 ();
604c2f83 4036 initialize_tdesc_powerpc_vsx64 ();
7cc46491
DJ		 4037 initialize_tdesc_powerpc_7400 ();
4038 initialize_tdesc_powerpc_750 ();
4039 initialize_tdesc_powerpc_860 ();
4040 initialize_tdesc_powerpc_e500 ();
4041 initialize_tdesc_rs6000 ();
55eddb0f
DJ		 4042
4043 /* Add root prefix command for all "set powerpc"/"show powerpc"
4044 commands. */
4045 add_prefix_cmd ("powerpc", no_class, set_powerpc_command,
4046 _("Various PowerPC-specific commands."),
4047 &setpowerpccmdlist, "set powerpc ", 0, &setlist);
4048
4049 add_prefix_cmd ("powerpc", no_class, show_powerpc_command,
4050 _("Various PowerPC-specific commands."),
4051 &showpowerpccmdlist, "show powerpc ", 0, &showlist);
4052
4053 /* Add a command to allow the user to force the ABI. */
4054 add_setshow_auto_boolean_cmd ("soft-float", class_support,
4055 &powerpc_soft_float_global,
4056 _("Set whether to use a soft-float ABI."),
4057 _("Show whether to use a soft-float ABI."),
4058 NULL,
4059 powerpc_set_soft_float, NULL,
4060 &setpowerpccmdlist, &showpowerpccmdlist);
4061
4062 add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings,
4063 &powerpc_vector_abi_string,
4064 _("Set the vector ABI."),
4065 _("Show the vector ABI."),
4066 NULL, powerpc_set_vector_abi, NULL,
4067 &setpowerpccmdlist, &showpowerpccmdlist);
c906108c 4068}
GDB Binutils - Deliverables
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