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2011-02-15 Tristan Gingold <gingold@adacore.com>
[deliverable/binutils-gdb.git] / gdb / rs6000-tdep.c
CommitLineData
c906108c 1/* Target-dependent code for GDB, the GNU debugger.
7aea86e6 2
6aba47ca 3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4c38e0a4 4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
7b6bb8da 5 2010, 2011 Free Software Foundation, Inc.
c906108c 6
c5aa993b 7 This file is part of GDB.
c906108c 8
c5aa993b
JM		 9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
c5aa993b 12 (at your option) any later version.
c906108c 13
c5aa993b
JM		 14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
c906108c 18
c5aa993b 19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c
SS		 21
22#include "defs.h"
23#include "frame.h"
24#include "inferior.h"
25#include "symtab.h"
26#include "target.h"
27#include "gdbcore.h"
28#include "gdbcmd.h"
c906108c 29#include "objfiles.h"
7a78ae4e 30#include "arch-utils.h"
4e052eda 31#include "regcache.h"
d195bc9f 32#include "regset.h"
d16aafd8 33#include "doublest.h"
fd0407d6 34#include "value.h"
1fcc0bb8 35#include "parser-defs.h"
4be87837 36#include "osabi.h"
7d9b040b 37#include "infcall.h"
9f643768
JB		 38#include "sim-regno.h"
39#include "gdb/sim-ppc.h"
6ced10dd 40#include "reggroups.h"
4fc771b8 41#include "dwarf2-frame.h"
7cc46491
DJ		 42#include "target-descriptions.h"
43#include "user-regs.h"
7a78ae4e 44
2fccf04a 45#include "libbfd.h" /* for bfd_default_set_arch_mach */
7a78ae4e 46#include "coff/internal.h" /* for libcoff.h */
2fccf04a 47#include "libcoff.h" /* for xcoff_data */
11ed25ac
KB		 48#include "coff/xcoff.h"
49#include "libxcoff.h"
7a78ae4e 50
9aa1e687 51#include "elf-bfd.h"
55eddb0f 52#include "elf/ppc.h"
7a78ae4e 53
6ded7999 54#include "solib-svr4.h"
9aa1e687 55#include "ppc-tdep.h"
7a78ae4e 56
338ef23d 57#include "gdb_assert.h"
a89aa300 58#include "dis-asm.h"
338ef23d 59
61a65099
KB		 60#include "trad-frame.h"
61#include "frame-unwind.h"
62#include "frame-base.h"
63
7cc46491 64#include "features/rs6000/powerpc-32.c"
7284e1be 65#include "features/rs6000/powerpc-altivec32.c"
604c2f83 66#include "features/rs6000/powerpc-vsx32.c"
7cc46491
DJ		 67#include "features/rs6000/powerpc-403.c"
68#include "features/rs6000/powerpc-403gc.c"
4d09ffea 69#include "features/rs6000/powerpc-405.c"
7cc46491
DJ		 70#include "features/rs6000/powerpc-505.c"
71#include "features/rs6000/powerpc-601.c"
72#include "features/rs6000/powerpc-602.c"
73#include "features/rs6000/powerpc-603.c"
74#include "features/rs6000/powerpc-604.c"
75#include "features/rs6000/powerpc-64.c"
7284e1be 76#include "features/rs6000/powerpc-altivec64.c"
604c2f83 77#include "features/rs6000/powerpc-vsx64.c"
7cc46491
DJ		 78#include "features/rs6000/powerpc-7400.c"
79#include "features/rs6000/powerpc-750.c"
80#include "features/rs6000/powerpc-860.c"
81#include "features/rs6000/powerpc-e500.c"
82#include "features/rs6000/rs6000.c"
83
5a9e69ba
TJB		 84/* Determine if regnum is an SPE pseudo-register. */
85#define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
86 && (regnum) >= (tdep)->ppc_ev0_regnum \
87 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
88
f949c649
TJB		 89/* Determine if regnum is a decimal float pseudo-register. */
90#define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_dl0_regnum \
92 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
93
604c2f83
LM		 94/* Determine if regnum is a POWER7 VSX register. */
95#define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_vsr0_regnum \
97 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
98
99/* Determine if regnum is a POWER7 Extended FP register. */
100#define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
101 && (regnum) >= (tdep)->ppc_efpr0_regnum \
102 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_fprs)
103
55eddb0f
DJ		 104/* The list of available "set powerpc ..." and "show powerpc ..."
105 commands. */
106static struct cmd_list_element *setpowerpccmdlist = NULL;
107static struct cmd_list_element *showpowerpccmdlist = NULL;
108
109static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO;
110
111/* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
112static const char *powerpc_vector_strings[] =
113{
114 "auto",
115 "generic",
116 "altivec",
117 "spe",
118 NULL
119};
120
121/* A variable that can be configured by the user. */
122static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO;
123static const char *powerpc_vector_abi_string = "auto";
124
0df8b418 125/* To be used by skip_prologue. */
7a78ae4e
ND		 126
127struct rs6000_framedata
128 {
129 int offset; /* total size of frame --- the distance
130 by which we decrement sp to allocate
131 the frame */
132 int saved_gpr; /* smallest # of saved gpr */
46a9b8ed 133 unsigned int gpr_mask; /* Each bit is an individual saved GPR. */
7a78ae4e 134 int saved_fpr; /* smallest # of saved fpr */
6be8bc0c 135 int saved_vr; /* smallest # of saved vr */
96ff0de4 136 int saved_ev; /* smallest # of saved ev */
7a78ae4e 137 int alloca_reg; /* alloca register number (frame ptr) */
0df8b418
MS		 138 char frameless; /* true if frameless functions. */
139 char nosavedpc; /* true if pc not saved. */
46a9b8ed 140 char used_bl; /* true if link register clobbered */
7a78ae4e
ND		 141 int gpr_offset; /* offset of saved gprs from prev sp */
142 int fpr_offset; /* offset of saved fprs from prev sp */
6be8bc0c 143 int vr_offset; /* offset of saved vrs from prev sp */
96ff0de4 144 int ev_offset; /* offset of saved evs from prev sp */
7a78ae4e 145 int lr_offset; /* offset of saved lr */
46a9b8ed 146 int lr_register; /* register of saved lr, if trustworthy */
7a78ae4e 147 int cr_offset; /* offset of saved cr */
6be8bc0c 148 int vrsave_offset; /* offset of saved vrsave register */
7a78ae4e
ND		 149 };
150
c906108c 151
604c2f83
LM		 152/* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
153int
154vsx_register_p (struct gdbarch *gdbarch, int regno)
155{
156 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
157 if (tdep->ppc_vsr0_regnum < 0)
158 return 0;
159 else
160 return (regno >= tdep->ppc_vsr0_upper_regnum && regno
161 <= tdep->ppc_vsr0_upper_regnum + 31);
162}
163
64b84175
KB		 164/* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
165int
be8626e0 166altivec_register_p (struct gdbarch *gdbarch, int regno)
64b84175 167{
be8626e0 168 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
64b84175
KB		 169 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
170 return 0;
171 else
172 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
173}
174
383f0f5b 175
867e2dc5
JB		 176/* Return true if REGNO is an SPE register, false otherwise. */
177int
be8626e0 178spe_register_p (struct gdbarch *gdbarch, int regno)
867e2dc5 179{
be8626e0 180 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
867e2dc5
JB		 181
182 /* Is it a reference to EV0 -- EV31, and do we have those? */
5a9e69ba 183 if (IS_SPE_PSEUDOREG (tdep, regno))
867e2dc5
JB		 184 return 1;
185
6ced10dd
JB		 186 /* Is it a reference to one of the raw upper GPR halves? */
187 if (tdep->ppc_ev0_upper_regnum >= 0
188 && tdep->ppc_ev0_upper_regnum <= regno
189 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
190 return 1;
191
867e2dc5
JB		 192 /* Is it a reference to the 64-bit accumulator, and do we have that? */
193 if (tdep->ppc_acc_regnum >= 0
194 && tdep->ppc_acc_regnum == regno)
195 return 1;
196
197 /* Is it a reference to the SPE floating-point status and control register,
198 and do we have that? */
199 if (tdep->ppc_spefscr_regnum >= 0
200 && tdep->ppc_spefscr_regnum == regno)
201 return 1;
202
203 return 0;
204}
205
206
383f0f5b
JB		 207/* Return non-zero if the architecture described by GDBARCH has
208 floating-point registers (f0 --- f31 and fpscr). */
0a613259
AC		 209int
210ppc_floating_point_unit_p (struct gdbarch *gdbarch)
211{
383f0f5b
JB		 212 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
213
214 return (tdep->ppc_fp0_regnum >= 0
215 && tdep->ppc_fpscr_regnum >= 0);
0a613259 216}
9f643768 217
604c2f83
LM		 218/* Return non-zero if the architecture described by GDBARCH has
219 VSX registers (vsr0 --- vsr63). */
63807e1d 220static int
604c2f83
LM		 221ppc_vsx_support_p (struct gdbarch *gdbarch)
222{
223 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
224
225 return tdep->ppc_vsr0_regnum >= 0;
226}
227
06caf7d2
CES		 228/* Return non-zero if the architecture described by GDBARCH has
229 Altivec registers (vr0 --- vr31, vrsave and vscr). */
230int
231ppc_altivec_support_p (struct gdbarch *gdbarch)
232{
233 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
234
235 return (tdep->ppc_vr0_regnum >= 0
236 && tdep->ppc_vrsave_regnum >= 0);
237}
09991fa0
JB		 238
239/* Check that TABLE[GDB_REGNO] is not already initialized, and then
240 set it to SIM_REGNO.
241
242 This is a helper function for init_sim_regno_table, constructing
243 the table mapping GDB register numbers to sim register numbers; we
244 initialize every element in that table to -1 before we start
245 filling it in. */
9f643768
JB		 246static void
247set_sim_regno (int *table, int gdb_regno, int sim_regno)
248{
249 /* Make sure we don't try to assign any given GDB register a sim
250 register number more than once. */
251 gdb_assert (table[gdb_regno] == -1);
252 table[gdb_regno] = sim_regno;
253}
254
09991fa0
JB		 255
256/* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
257 numbers to simulator register numbers, based on the values placed
258 in the ARCH->tdep->ppc_foo_regnum members. */
9f643768
JB		 259static void
260init_sim_regno_table (struct gdbarch *arch)
261{
262 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
7cc46491 263 int total_regs = gdbarch_num_regs (arch);
9f643768
JB		 264 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
265 int i;
7cc46491
DJ		 266 static const char *const segment_regs[] = {
267 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
268 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
269 };
9f643768
JB		 270
271 /* Presume that all registers not explicitly mentioned below are
272 unavailable from the sim. */
273 for (i = 0; i < total_regs; i++)
274 sim_regno[i] = -1;
275
276 /* General-purpose registers. */
277 for (i = 0; i < ppc_num_gprs; i++)
278 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
279
280 /* Floating-point registers. */
281 if (tdep->ppc_fp0_regnum >= 0)
282 for (i = 0; i < ppc_num_fprs; i++)
283 set_sim_regno (sim_regno,
284 tdep->ppc_fp0_regnum + i,
285 sim_ppc_f0_regnum + i);
286 if (tdep->ppc_fpscr_regnum >= 0)
287 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
288
289 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
290 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
291 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
292
293 /* Segment registers. */
7cc46491
DJ		 294 for (i = 0; i < ppc_num_srs; i++)
295 {
296 int gdb_regno;
297
298 gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1);
299 if (gdb_regno >= 0)
300 set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i);
301 }
9f643768
JB		 302
303 /* Altivec registers. */
304 if (tdep->ppc_vr0_regnum >= 0)
305 {
306 for (i = 0; i < ppc_num_vrs; i++)
307 set_sim_regno (sim_regno,
308 tdep->ppc_vr0_regnum + i,
309 sim_ppc_vr0_regnum + i);
310
311 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
312 we can treat this more like the other cases. */
313 set_sim_regno (sim_regno,
314 tdep->ppc_vr0_regnum + ppc_num_vrs,
315 sim_ppc_vscr_regnum);
316 }
317 /* vsave is a special-purpose register, so the code below handles it. */
318
319 /* SPE APU (E500) registers. */
6ced10dd
JB		 320 if (tdep->ppc_ev0_upper_regnum >= 0)
321 for (i = 0; i < ppc_num_gprs; i++)
322 set_sim_regno (sim_regno,
323 tdep->ppc_ev0_upper_regnum + i,
324 sim_ppc_rh0_regnum + i);
9f643768
JB		 325 if (tdep->ppc_acc_regnum >= 0)
326 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
327 /* spefscr is a special-purpose register, so the code below handles it. */
328
7cc46491 329#ifdef WITH_SIM
9f643768
JB		 330 /* Now handle all special-purpose registers. Verify that they
331 haven't mistakenly been assigned numbers by any of the above
7cc46491
DJ		 332 code. */
333 for (i = 0; i < sim_ppc_num_sprs; i++)
334 {
335 const char *spr_name = sim_spr_register_name (i);
336 int gdb_regno = -1;
337
338 if (spr_name != NULL)
339 gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1);
340
341 if (gdb_regno != -1)
342 set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i);
343 }
344#endif
9f643768
JB		 345
346 /* Drop the initialized array into place. */
347 tdep->sim_regno = sim_regno;
348}
349
09991fa0
JB		 350
351/* Given a GDB register number REG, return the corresponding SIM
352 register number. */
9f643768 353static int
e7faf938 354rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg)
9f643768 355{
e7faf938 356 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9f643768
JB		 357 int sim_regno;
358
7cc46491 359 if (tdep->sim_regno == NULL)
e7faf938 360 init_sim_regno_table (gdbarch);
7cc46491 361
f57d151a 362 gdb_assert (0 <= reg
e7faf938
MD		 363 && reg <= gdbarch_num_regs (gdbarch)
364 + gdbarch_num_pseudo_regs (gdbarch));
9f643768
JB		 365 sim_regno = tdep->sim_regno[reg];
366
367 if (sim_regno >= 0)
368 return sim_regno;
369 else
370 return LEGACY_SIM_REGNO_IGNORE;
371}
372
d195bc9f
MK		 373\f
374
375/* Register set support functions. */
376
f2db237a
AM		 377/* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
378 Write the register to REGCACHE. */
379
7284e1be 380void
d195bc9f 381ppc_supply_reg (struct regcache *regcache, int regnum,
f2db237a 382 const gdb_byte *regs, size_t offset, int regsize)
d195bc9f
MK		 383{
384 if (regnum != -1 && offset != -1)
f2db237a
AM		 385 {
386 if (regsize > 4)
387 {
388 struct gdbarch *gdbarch = get_regcache_arch (regcache);
389 int gdb_regsize = register_size (gdbarch, regnum);
390 if (gdb_regsize < regsize
391 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
392 offset += regsize - gdb_regsize;
393 }
394 regcache_raw_supply (regcache, regnum, regs + offset);
395 }
d195bc9f
MK		 396}
397
f2db237a
AM		 398/* Read register REGNUM from REGCACHE and store to REGS + OFFSET
399 in a field REGSIZE wide. Zero pad as necessary. */
400
7284e1be 401void
d195bc9f 402ppc_collect_reg (const struct regcache *regcache, int regnum,
f2db237a 403 gdb_byte *regs, size_t offset, int regsize)
d195bc9f
MK		 404{
405 if (regnum != -1 && offset != -1)
f2db237a
AM		 406 {
407 if (regsize > 4)
408 {
409 struct gdbarch *gdbarch = get_regcache_arch (regcache);
410 int gdb_regsize = register_size (gdbarch, regnum);
411 if (gdb_regsize < regsize)
412 {
413 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
414 {
415 memset (regs + offset, 0, regsize - gdb_regsize);
416 offset += regsize - gdb_regsize;
417 }
418 else
419 memset (regs + offset + regsize - gdb_regsize, 0,
420 regsize - gdb_regsize);
421 }
422 }
423 regcache_raw_collect (regcache, regnum, regs + offset);
424 }
d195bc9f
MK		 425}
426
f2db237a
AM		 427static int
428ppc_greg_offset (struct gdbarch *gdbarch,
429 struct gdbarch_tdep *tdep,
430 const struct ppc_reg_offsets *offsets,
431 int regnum,
432 int *regsize)
433{
434 *regsize = offsets->gpr_size;
435 if (regnum >= tdep->ppc_gp0_regnum
436 && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs)
437 return (offsets->r0_offset
438 + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size);
439
440 if (regnum == gdbarch_pc_regnum (gdbarch))
441 return offsets->pc_offset;
442
443 if (regnum == tdep->ppc_ps_regnum)
444 return offsets->ps_offset;
445
446 if (regnum == tdep->ppc_lr_regnum)
447 return offsets->lr_offset;
448
449 if (regnum == tdep->ppc_ctr_regnum)
450 return offsets->ctr_offset;
451
452 *regsize = offsets->xr_size;
453 if (regnum == tdep->ppc_cr_regnum)
454 return offsets->cr_offset;
455
456 if (regnum == tdep->ppc_xer_regnum)
457 return offsets->xer_offset;
458
459 if (regnum == tdep->ppc_mq_regnum)
460 return offsets->mq_offset;
461
462 return -1;
463}
464
465static int
466ppc_fpreg_offset (struct gdbarch_tdep *tdep,
467 const struct ppc_reg_offsets *offsets,
468 int regnum)
469{
470 if (regnum >= tdep->ppc_fp0_regnum
471 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs)
472 return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8;
473
474 if (regnum == tdep->ppc_fpscr_regnum)
475 return offsets->fpscr_offset;
476
477 return -1;
478}
479
06caf7d2
CES		 480static int
481ppc_vrreg_offset (struct gdbarch_tdep *tdep,
482 const struct ppc_reg_offsets *offsets,
483 int regnum)
484{
485 if (regnum >= tdep->ppc_vr0_regnum
486 && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs)
487 return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16;
488
489 if (regnum == tdep->ppc_vrsave_regnum - 1)
490 return offsets->vscr_offset;
491
492 if (regnum == tdep->ppc_vrsave_regnum)
493 return offsets->vrsave_offset;
494
495 return -1;
496}
497
d195bc9f
MK		 498/* Supply register REGNUM in the general-purpose register set REGSET
499 from the buffer specified by GREGS and LEN to register cache
500 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
501
502void
503ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
504 int regnum, const void *gregs, size_t len)
505{
506 struct gdbarch *gdbarch = get_regcache_arch (regcache);
507 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
508 const struct ppc_reg_offsets *offsets = regset->descr;
509 size_t offset;
f2db237a 510 int regsize;
d195bc9f 511
f2db237a 512 if (regnum == -1)
d195bc9f 513 {
f2db237a
AM		 514 int i;
515 int gpr_size = offsets->gpr_size;
516
517 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
518 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
519 i++, offset += gpr_size)
520 ppc_supply_reg (regcache, i, gregs, offset, gpr_size);
521
522 ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch),
523 gregs, offsets->pc_offset, gpr_size);
524 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
525 gregs, offsets->ps_offset, gpr_size);
526 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
527 gregs, offsets->lr_offset, gpr_size);
528 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
529 gregs, offsets->ctr_offset, gpr_size);
530 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
531 gregs, offsets->cr_offset, offsets->xr_size);
532 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
533 gregs, offsets->xer_offset, offsets->xr_size);
534 ppc_supply_reg (regcache, tdep->ppc_mq_regnum,
535 gregs, offsets->mq_offset, offsets->xr_size);
536 return;
d195bc9f
MK		 537 }
538
f2db237a
AM		 539 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
540 ppc_supply_reg (regcache, regnum, gregs, offset, regsize);
d195bc9f
MK		 541}
542
543/* Supply register REGNUM in the floating-point register set REGSET
544 from the buffer specified by FPREGS and LEN to register cache
545 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
546
547void
548ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
549 int regnum, const void *fpregs, size_t len)
550{
551 struct gdbarch *gdbarch = get_regcache_arch (regcache);
f2db237a
AM		 552 struct gdbarch_tdep *tdep;
553 const struct ppc_reg_offsets *offsets;
d195bc9f 554 size_t offset;
d195bc9f 555
f2db237a
AM		 556 if (!ppc_floating_point_unit_p (gdbarch))
557 return;
383f0f5b 558
f2db237a
AM		 559 tdep = gdbarch_tdep (gdbarch);
560 offsets = regset->descr;
561 if (regnum == -1)
d195bc9f 562 {
f2db237a
AM		 563 int i;
564
565 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
566 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
567 i++, offset += 8)
568 ppc_supply_reg (regcache, i, fpregs, offset, 8);
569
570 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
571 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
572 return;
d195bc9f
MK		 573 }
574
f2db237a
AM		 575 offset = ppc_fpreg_offset (tdep, offsets, regnum);
576 ppc_supply_reg (regcache, regnum, fpregs, offset,
577 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
d195bc9f
MK		 578}
579
604c2f83
LM		 580/* Supply register REGNUM in the VSX register set REGSET
581 from the buffer specified by VSXREGS and LEN to register cache
582 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
583
584void
585ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache,
586 int regnum, const void *vsxregs, size_t len)
587{
588 struct gdbarch *gdbarch = get_regcache_arch (regcache);
589 struct gdbarch_tdep *tdep;
590
591 if (!ppc_vsx_support_p (gdbarch))
592 return;
593
594 tdep = gdbarch_tdep (gdbarch);
595
596 if (regnum == -1)
597 {
598 int i;
599
600 for (i = tdep->ppc_vsr0_upper_regnum;
601 i < tdep->ppc_vsr0_upper_regnum + 32;
602 i++)
603 ppc_supply_reg (regcache, i, vsxregs, 0, 8);
604
605 return;
606 }
607 else
608 ppc_supply_reg (regcache, regnum, vsxregs, 0, 8);
609}
610
06caf7d2
CES		 611/* Supply register REGNUM in the Altivec register set REGSET
612 from the buffer specified by VRREGS and LEN to register cache
613 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
614
615void
616ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache,
617 int regnum, const void *vrregs, size_t len)
618{
619 struct gdbarch *gdbarch = get_regcache_arch (regcache);
620 struct gdbarch_tdep *tdep;
621 const struct ppc_reg_offsets *offsets;
622 size_t offset;
623
624 if (!ppc_altivec_support_p (gdbarch))
625 return;
626
627 tdep = gdbarch_tdep (gdbarch);
628 offsets = regset->descr;
629 if (regnum == -1)
630 {
631 int i;
632
633 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
634 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
635 i++, offset += 16)
636 ppc_supply_reg (regcache, i, vrregs, offset, 16);
637
638 ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
639 vrregs, offsets->vscr_offset, 4);
640
641 ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum,
642 vrregs, offsets->vrsave_offset, 4);
643 return;
644 }
645
646 offset = ppc_vrreg_offset (tdep, offsets, regnum);
647 if (regnum != tdep->ppc_vrsave_regnum
648 && regnum != tdep->ppc_vrsave_regnum - 1)
649 ppc_supply_reg (regcache, regnum, vrregs, offset, 16);
650 else
651 ppc_supply_reg (regcache, regnum,
652 vrregs, offset, 4);
653}
654
d195bc9f 655/* Collect register REGNUM in the general-purpose register set
f2db237a 656 REGSET from register cache REGCACHE into the buffer specified by
d195bc9f
MK		 657 GREGS and LEN. If REGNUM is -1, do this for all registers in
658 REGSET. */
659
660void
661ppc_collect_gregset (const struct regset *regset,
662 const struct regcache *regcache,
663 int regnum, void *gregs, size_t len)
664{
665 struct gdbarch *gdbarch = get_regcache_arch (regcache);
666 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
667 const struct ppc_reg_offsets *offsets = regset->descr;
668 size_t offset;
f2db237a 669 int regsize;
d195bc9f 670
f2db237a 671 if (regnum == -1)
d195bc9f 672 {
f2db237a
AM		 673 int i;
674 int gpr_size = offsets->gpr_size;
675
676 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
677 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
678 i++, offset += gpr_size)
679 ppc_collect_reg (regcache, i, gregs, offset, gpr_size);
680
681 ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch),
682 gregs, offsets->pc_offset, gpr_size);
683 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
684 gregs, offsets->ps_offset, gpr_size);
685 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
686 gregs, offsets->lr_offset, gpr_size);
687 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
688 gregs, offsets->ctr_offset, gpr_size);
689 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
690 gregs, offsets->cr_offset, offsets->xr_size);
691 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
692 gregs, offsets->xer_offset, offsets->xr_size);
693 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
694 gregs, offsets->mq_offset, offsets->xr_size);
695 return;
d195bc9f
MK		 696 }
697
f2db237a
AM		 698 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
699 ppc_collect_reg (regcache, regnum, gregs, offset, regsize);
d195bc9f
MK		 700}
701
702/* Collect register REGNUM in the floating-point register set
f2db237a 703 REGSET from register cache REGCACHE into the buffer specified by
d195bc9f
MK		 704 FPREGS and LEN. If REGNUM is -1, do this for all registers in
705 REGSET. */
706
707void
708ppc_collect_fpregset (const struct regset *regset,
709 const struct regcache *regcache,
710 int regnum, void *fpregs, size_t len)
711{
712 struct gdbarch *gdbarch = get_regcache_arch (regcache);
f2db237a
AM		 713 struct gdbarch_tdep *tdep;
714 const struct ppc_reg_offsets *offsets;
d195bc9f 715 size_t offset;
d195bc9f 716
f2db237a
AM		 717 if (!ppc_floating_point_unit_p (gdbarch))
718 return;
383f0f5b 719
f2db237a
AM		 720 tdep = gdbarch_tdep (gdbarch);
721 offsets = regset->descr;
722 if (regnum == -1)
d195bc9f 723 {
f2db237a
AM		 724 int i;
725
726 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
727 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
728 i++, offset += 8)
729 ppc_collect_reg (regcache, i, fpregs, offset, 8);
730
731 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
732 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
733 return;
d195bc9f
MK		 734 }
735
f2db237a
AM		 736 offset = ppc_fpreg_offset (tdep, offsets, regnum);
737 ppc_collect_reg (regcache, regnum, fpregs, offset,
738 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
d195bc9f 739}
06caf7d2 740
604c2f83
LM		 741/* Collect register REGNUM in the VSX register set
742 REGSET from register cache REGCACHE into the buffer specified by
743 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
744 REGSET. */
745
746void
747ppc_collect_vsxregset (const struct regset *regset,
748 const struct regcache *regcache,
749 int regnum, void *vsxregs, size_t len)
750{
751 struct gdbarch *gdbarch = get_regcache_arch (regcache);
752 struct gdbarch_tdep *tdep;
753
754 if (!ppc_vsx_support_p (gdbarch))
755 return;
756
757 tdep = gdbarch_tdep (gdbarch);
758
759 if (regnum == -1)
760 {
761 int i;
762
763 for (i = tdep->ppc_vsr0_upper_regnum;
764 i < tdep->ppc_vsr0_upper_regnum + 32;
765 i++)
766 ppc_collect_reg (regcache, i, vsxregs, 0, 8);
767
768 return;
769 }
770 else
771 ppc_collect_reg (regcache, regnum, vsxregs, 0, 8);
772}
773
774
06caf7d2
CES		 775/* Collect register REGNUM in the Altivec register set
776 REGSET from register cache REGCACHE into the buffer specified by
777 VRREGS and LEN. If REGNUM is -1, do this for all registers in
778 REGSET. */
779
780void
781ppc_collect_vrregset (const struct regset *regset,
782 const struct regcache *regcache,
783 int regnum, void *vrregs, size_t len)
784{
785 struct gdbarch *gdbarch = get_regcache_arch (regcache);
786 struct gdbarch_tdep *tdep;
787 const struct ppc_reg_offsets *offsets;
788 size_t offset;
789
790 if (!ppc_altivec_support_p (gdbarch))
791 return;
792
793 tdep = gdbarch_tdep (gdbarch);
794 offsets = regset->descr;
795 if (regnum == -1)
796 {
797 int i;
798
799 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
800 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
801 i++, offset += 16)
802 ppc_collect_reg (regcache, i, vrregs, offset, 16);
803
804 ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
805 vrregs, offsets->vscr_offset, 4);
806
807 ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum,
808 vrregs, offsets->vrsave_offset, 4);
809 return;
810 }
811
812 offset = ppc_vrreg_offset (tdep, offsets, regnum);
813 if (regnum != tdep->ppc_vrsave_regnum
814 && regnum != tdep->ppc_vrsave_regnum - 1)
815 ppc_collect_reg (regcache, regnum, vrregs, offset, 16);
816 else
817 ppc_collect_reg (regcache, regnum,
818 vrregs, offset, 4);
819}
d195bc9f 820\f
0a613259 821
0d1243d9
PG		 822static int
823insn_changes_sp_or_jumps (unsigned long insn)
824{
825 int opcode = (insn >> 26) & 0x03f;
826 int sd = (insn >> 21) & 0x01f;
827 int a = (insn >> 16) & 0x01f;
828 int subcode = (insn >> 1) & 0x3ff;
829
830 /* Changes the stack pointer. */
831
832 /* NOTE: There are many ways to change the value of a given register.
833 The ways below are those used when the register is R1, the SP,
834 in a funtion's epilogue. */
835
836 if (opcode == 31 && subcode == 444 && a == 1)
837 return 1; /* mr R1,Rn */
838 if (opcode == 14 && sd == 1)
839 return 1; /* addi R1,Rn,simm */
840 if (opcode == 58 && sd == 1)
841 return 1; /* ld R1,ds(Rn) */
842
843 /* Transfers control. */
844
845 if (opcode == 18)
846 return 1; /* b */
847 if (opcode == 16)
848 return 1; /* bc */
849 if (opcode == 19 && subcode == 16)
850 return 1; /* bclr */
851 if (opcode == 19 && subcode == 528)
852 return 1; /* bcctr */
853
854 return 0;
855}
856
857/* Return true if we are in the function's epilogue, i.e. after the
858 instruction that destroyed the function's stack frame.
859
860 1) scan forward from the point of execution:
861 a) If you find an instruction that modifies the stack pointer
862 or transfers control (except a return), execution is not in
863 an epilogue, return.
864 b) Stop scanning if you find a return instruction or reach the
865 end of the function or reach the hard limit for the size of
866 an epilogue.
867 2) scan backward from the point of execution:
868 a) If you find an instruction that modifies the stack pointer,
869 execution *is* in an epilogue, return.
870 b) Stop scanning if you reach an instruction that transfers
871 control or the beginning of the function or reach the hard
872 limit for the size of an epilogue. */
873
874static int
875rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
876{
46a9b8ed 877 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 878 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
0d1243d9
PG		 879 bfd_byte insn_buf[PPC_INSN_SIZE];
880 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
881 unsigned long insn;
882 struct frame_info *curfrm;
883
884 /* Find the search limits based on function boundaries and hard limit. */
885
886 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
887 return 0;
888
889 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
890 if (epilogue_start < func_start) epilogue_start = func_start;
891
892 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
893 if (epilogue_end > func_end) epilogue_end = func_end;
894
895 curfrm = get_current_frame ();
896
897 /* Scan forward until next 'blr'. */
898
899 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
900 {
901 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
902 return 0;
e17a4113 903 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
0d1243d9
PG		 904 if (insn == 0x4e800020)
905 break;
46a9b8ed
DJ		 906 /* Assume a bctr is a tail call unless it points strictly within
907 this function. */
908 if (insn == 0x4e800420)
909 {
910 CORE_ADDR ctr = get_frame_register_unsigned (curfrm,
911 tdep->ppc_ctr_regnum);
912 if (ctr > func_start && ctr < func_end)
913 return 0;
914 else
915 break;
916 }
0d1243d9
PG		 917 if (insn_changes_sp_or_jumps (insn))
918 return 0;
919 }
920
921 /* Scan backward until adjustment to stack pointer (R1). */
922
923 for (scan_pc = pc - PPC_INSN_SIZE;
924 scan_pc >= epilogue_start;
925 scan_pc -= PPC_INSN_SIZE)
926 {
927 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
928 return 0;
e17a4113 929 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
0d1243d9
PG		 930 if (insn_changes_sp_or_jumps (insn))
931 return 1;
932 }
933
934 return 0;
935}
936
143985b7 937/* Get the ith function argument for the current function. */
b9362cc7 938static CORE_ADDR
143985b7
AF		 939rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
940 struct type *type)
941{
50fd1280 942 return get_frame_register_unsigned (frame, 3 + argi);
143985b7
AF		 943}
944
c906108c
SS		 945/* Sequence of bytes for breakpoint instruction. */
946
f4f9705a 947const static unsigned char *
67d57894
MD		 948rs6000_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
949 int *bp_size)
c906108c 950{
aaab4dba
AC		 951 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
952 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
c906108c 953 *bp_size = 4;
67d57894 954 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
c906108c
SS		 955 return big_breakpoint;
956 else
957 return little_breakpoint;
958}
959
f74c6cad
LM		 960/* Instruction masks for displaced stepping. */
961#define BRANCH_MASK 0xfc000000
962#define BP_MASK 0xFC0007FE
963#define B_INSN 0x48000000
964#define BC_INSN 0x40000000
965#define BXL_INSN 0x4c000000
966#define BP_INSN 0x7C000008
967
968/* Fix up the state of registers and memory after having single-stepped
969 a displaced instruction. */
63807e1d 970static void
f74c6cad 971ppc_displaced_step_fixup (struct gdbarch *gdbarch,
63807e1d
PA		 972 struct displaced_step_closure *closure,
973 CORE_ADDR from, CORE_ADDR to,
974 struct regcache *regs)
f74c6cad 975{
e17a4113 976 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
f74c6cad
LM		 977 /* Since we use simple_displaced_step_copy_insn, our closure is a
978 copy of the instruction. */
979 ULONGEST insn = extract_unsigned_integer ((gdb_byte *) closure,
e17a4113 980 PPC_INSN_SIZE, byte_order);
f74c6cad
LM		 981 ULONGEST opcode = 0;
982 /* Offset for non PC-relative instructions. */
983 LONGEST offset = PPC_INSN_SIZE;
984
985 opcode = insn & BRANCH_MASK;
986
987 if (debug_displaced)
988 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 989 "displaced: (ppc) fixup (%s, %s)\n",
990 paddress (gdbarch, from), paddress (gdbarch, to));
f74c6cad
LM		 991
992
993 /* Handle PC-relative branch instructions. */
994 if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN)
995 {
a4fafde3 996 ULONGEST current_pc;
f74c6cad
LM		 997
998 /* Read the current PC value after the instruction has been executed
999 in a displaced location. Calculate the offset to be applied to the
1000 original PC value before the displaced stepping. */
1001 regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1002 &current_pc);
1003 offset = current_pc - to;
1004
1005 if (opcode != BXL_INSN)
1006 {
1007 /* Check for AA bit indicating whether this is an absolute
1008 addressing or PC-relative (1: absolute, 0: relative). */
1009 if (!(insn & 0x2))
1010 {
1011 /* PC-relative addressing is being used in the branch. */
1012 if (debug_displaced)
1013 fprintf_unfiltered
1014 (gdb_stdlog,
5af949e3
UW		 1015 "displaced: (ppc) branch instruction: %s\n"
1016 "displaced: (ppc) adjusted PC from %s to %s\n",
1017 paddress (gdbarch, insn), paddress (gdbarch, current_pc),
1018 paddress (gdbarch, from + offset));
f74c6cad 1019
0df8b418
MS		 1020 regcache_cooked_write_unsigned (regs,
1021 gdbarch_pc_regnum (gdbarch),
f74c6cad
LM		 1022 from + offset);
1023 }
1024 }
1025 else
1026 {
1027 /* If we're here, it means we have a branch to LR or CTR. If the
1028 branch was taken, the offset is probably greater than 4 (the next
1029 instruction), so it's safe to assume that an offset of 4 means we
1030 did not take the branch. */
1031 if (offset == PPC_INSN_SIZE)
1032 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1033 from + PPC_INSN_SIZE);
1034 }
1035
1036 /* Check for LK bit indicating whether we should set the link
1037 register to point to the next instruction
1038 (1: Set, 0: Don't set). */
1039 if (insn & 0x1)
1040 {
1041 /* Link register needs to be set to the next instruction's PC. */
1042 regcache_cooked_write_unsigned (regs,
1043 gdbarch_tdep (gdbarch)->ppc_lr_regnum,
1044 from + PPC_INSN_SIZE);
1045 if (debug_displaced)
1046 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 1047 "displaced: (ppc) adjusted LR to %s\n",
1048 paddress (gdbarch, from + PPC_INSN_SIZE));
f74c6cad
LM		 1049
1050 }
1051 }
1052 /* Check for breakpoints in the inferior. If we've found one, place the PC
1053 right at the breakpoint instruction. */
1054 else if ((insn & BP_MASK) == BP_INSN)
1055 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from);
1056 else
1057 /* Handle any other instructions that do not fit in the categories above. */
1058 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1059 from + offset);
1060}
c906108c 1061
99e40580
UW		 1062/* Always use hardware single-stepping to execute the
1063 displaced instruction. */
1064static int
1065ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
1066 struct displaced_step_closure *closure)
1067{
1068 return 1;
1069}
1070
ce5eab59
UW		 1071/* Instruction masks used during single-stepping of atomic sequences. */
1072#define LWARX_MASK 0xfc0007fe
1073#define LWARX_INSTRUCTION 0x7c000028
1074#define LDARX_INSTRUCTION 0x7c0000A8
1075#define STWCX_MASK 0xfc0007ff
1076#define STWCX_INSTRUCTION 0x7c00012d
1077#define STDCX_INSTRUCTION 0x7c0001ad
ce5eab59
UW		 1078
1079/* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1080 instruction and ending with a STWCX/STDCX instruction. If such a sequence
1081 is found, attempt to step through it. A breakpoint is placed at the end of
1082 the sequence. */
1083
4a7622d1
UW		 1084int
1085ppc_deal_with_atomic_sequence (struct frame_info *frame)
ce5eab59 1086{
a6d9a66e 1087 struct gdbarch *gdbarch = get_frame_arch (frame);
6c95b8df 1088 struct address_space *aspace = get_frame_address_space (frame);
e17a4113 1089 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
0b1b3e42 1090 CORE_ADDR pc = get_frame_pc (frame);
ce5eab59
UW		 1091 CORE_ADDR breaks[2] = {-1, -1};
1092 CORE_ADDR loc = pc;
24d45690 1093 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
e17a4113 1094 int insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
ce5eab59
UW		 1095 int insn_count;
1096 int index;
1097 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
1098 const int atomic_sequence_length = 16; /* Instruction sequence length. */
24d45690 1099 int opcode; /* Branch instruction's OPcode. */
ce5eab59
UW		 1100 int bc_insn_count = 0; /* Conditional branch instruction count. */
1101
1102 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1103 if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
1104 && (insn & LWARX_MASK) != LDARX_INSTRUCTION)
1105 return 0;
1106
1107 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1108 instructions. */
1109 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
1110 {
1111 loc += PPC_INSN_SIZE;
e17a4113 1112 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
ce5eab59
UW		 1113
1114 /* Assume that there is at most one conditional branch in the atomic
1115 sequence. If a conditional branch is found, put a breakpoint in
1116 its destination address. */
f74c6cad 1117 if ((insn & BRANCH_MASK) == BC_INSN)
ce5eab59 1118 {
4a7622d1
UW		 1119 int immediate = ((insn & ~3) << 16) >> 16;
1120 int absolute = ((insn >> 1) & 1);
1121
ce5eab59
UW		 1122 if (bc_insn_count >= 1)
1123 return 0; /* More than one conditional branch found, fallback
1124 to the standard single-step code. */
4a7622d1
UW		 1125
1126 if (absolute)
1127 breaks[1] = immediate;
1128 else
1129 breaks[1] = pc + immediate;
1130
1131 bc_insn_count++;
1132 last_breakpoint++;
ce5eab59
UW		 1133 }
1134
1135 if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
1136 || (insn & STWCX_MASK) == STDCX_INSTRUCTION)
1137 break;
1138 }
1139
1140 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1141 if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
1142 && (insn & STWCX_MASK) != STDCX_INSTRUCTION)
1143 return 0;
1144
24d45690 1145 closing_insn = loc;
ce5eab59 1146 loc += PPC_INSN_SIZE;
e17a4113 1147 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
ce5eab59
UW		 1148
1149 /* Insert a breakpoint right after the end of the atomic sequence. */
1150 breaks[0] = loc;
1151
24d45690
UW		 1152 /* Check for duplicated breakpoints. Check also for a breakpoint
1153 placed (branch instruction's destination) at the stwcx/stdcx
1154 instruction, this resets the reservation and take us back to the
1155 lwarx/ldarx instruction at the beginning of the atomic sequence. */
1156 if (last_breakpoint && ((breaks[1] == breaks[0])
1157 || (breaks[1] == closing_insn)))
ce5eab59
UW		 1158 last_breakpoint = 0;
1159
1160 /* Effectively inserts the breakpoints. */
1161 for (index = 0; index <= last_breakpoint; index++)
6c95b8df 1162 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
ce5eab59
UW		 1163
1164 return 1;
1165}
1166
c906108c 1167
c906108c
SS		 1168#define SIGNED_SHORT(x) \
1169 ((sizeof (short) == 2) \
1170 ? ((int)(short)(x)) \
1171 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1172
1173#define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1174
55d05f3b
KB		 1175/* Limit the number of skipped non-prologue instructions, as the examining
1176 of the prologue is expensive. */
1177static int max_skip_non_prologue_insns = 10;
1178
773df3e5
JB		 1179/* Return nonzero if the given instruction OP can be part of the prologue
1180 of a function and saves a parameter on the stack. FRAMEP should be
1181 set if one of the previous instructions in the function has set the
1182 Frame Pointer. */
1183
1184static int
1185store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
1186{
1187 /* Move parameters from argument registers to temporary register. */
1188 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1189 {
1190 /* Rx must be scratch register r0. */
1191 const int rx_regno = (op >> 16) & 31;
1192 /* Ry: Only r3 - r10 are used for parameter passing. */
1193 const int ry_regno = GET_SRC_REG (op);
1194
1195 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
1196 {
1197 *r0_contains_arg = 1;
1198 return 1;
1199 }
1200 else
1201 return 0;
1202 }
1203
1204 /* Save a General Purpose Register on stack. */
1205
1206 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1207 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1208 {
1209 /* Rx: Only r3 - r10 are used for parameter passing. */
1210 const int rx_regno = GET_SRC_REG (op);
1211
1212 return (rx_regno >= 3 && rx_regno <= 10);
1213 }
1214
1215 /* Save a General Purpose Register on stack via the Frame Pointer. */
1216
1217 if (framep &&
1218 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1219 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1220 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1221 {
1222 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1223 However, the compiler sometimes uses r0 to hold an argument. */
1224 const int rx_regno = GET_SRC_REG (op);
1225
1226 return ((rx_regno >= 3 && rx_regno <= 10)
1227 || (rx_regno == 0 && *r0_contains_arg));
1228 }
1229
1230 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1231 {
1232 /* Only f2 - f8 are used for parameter passing. */
1233 const int src_regno = GET_SRC_REG (op);
1234
1235 return (src_regno >= 2 && src_regno <= 8);
1236 }
1237
1238 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1239 {
1240 /* Only f2 - f8 are used for parameter passing. */
1241 const int src_regno = GET_SRC_REG (op);
1242
1243 return (src_regno >= 2 && src_regno <= 8);
1244 }
1245
1246 /* Not an insn that saves a parameter on stack. */
1247 return 0;
1248}
55d05f3b 1249
3c77c82a
DJ		 1250/* Assuming that INSN is a "bl" instruction located at PC, return
1251 nonzero if the destination of the branch is a "blrl" instruction.
1252
1253 This sequence is sometimes found in certain function prologues.
1254 It allows the function to load the LR register with a value that
1255 they can use to access PIC data using PC-relative offsets. */
1256
1257static int
e17a4113 1258bl_to_blrl_insn_p (CORE_ADDR pc, int insn, enum bfd_endian byte_order)
3c77c82a 1259{
0b1b3e42
UW		 1260 CORE_ADDR dest;
1261 int immediate;
1262 int absolute;
3c77c82a
DJ		 1263 int dest_insn;
1264
0b1b3e42
UW		 1265 absolute = (int) ((insn >> 1) & 1);
1266 immediate = ((insn & ~3) << 6) >> 6;
1267 if (absolute)
1268 dest = immediate;
1269 else
1270 dest = pc + immediate;
1271
e17a4113 1272 dest_insn = read_memory_integer (dest, 4, byte_order);
3c77c82a
DJ		 1273 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
1274 return 1;
1275
1276 return 0;
1277}
1278
0df8b418 1279/* Masks for decoding a branch-and-link (bl) instruction.
8ab3d180
KB		 1280
1281 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1282 The former is anded with the opcode in question; if the result of
1283 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1284 question is a ``bl'' instruction.
1285
1286 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1287 the branch displacement. */
1288
1289#define BL_MASK 0xfc000001
1290#define BL_INSTRUCTION 0x48000001
1291#define BL_DISPLACEMENT_MASK 0x03fffffc
1292
de9f48f0 1293static unsigned long
e17a4113 1294rs6000_fetch_instruction (struct gdbarch *gdbarch, const CORE_ADDR pc)
de9f48f0 1295{
e17a4113 1296 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
de9f48f0
JG		 1297 gdb_byte buf[4];
1298 unsigned long op;
1299
1300 /* Fetch the instruction and convert it to an integer. */
1301 if (target_read_memory (pc, buf, 4))
1302 return 0;
e17a4113 1303 op = extract_unsigned_integer (buf, 4, byte_order);
de9f48f0
JG		 1304
1305 return op;
1306}
1307
1308/* GCC generates several well-known sequences of instructions at the begining
1309 of each function prologue when compiling with -fstack-check. If one of
1310 such sequences starts at START_PC, then return the address of the
1311 instruction immediately past this sequence. Otherwise, return START_PC. */
1312
1313static CORE_ADDR
e17a4113 1314rs6000_skip_stack_check (struct gdbarch *gdbarch, const CORE_ADDR start_pc)
de9f48f0
JG		 1315{
1316 CORE_ADDR pc = start_pc;
e17a4113 1317 unsigned long op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1318
1319 /* First possible sequence: A small number of probes.
1320 stw 0, -<some immediate>(1)
0df8b418 1321 [repeat this instruction any (small) number of times]. */
de9f48f0
JG		 1322
1323 if ((op & 0xffff0000) == 0x90010000)
1324 {
1325 while ((op & 0xffff0000) == 0x90010000)
1326 {
1327 pc = pc + 4;
e17a4113 1328 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1329 }
1330 return pc;
1331 }
1332
1333 /* Second sequence: A probing loop.
1334 addi 12,1,-<some immediate>
1335 lis 0,-<some immediate>
1336 [possibly ori 0,0,<some immediate>]
1337 add 0,12,0
1338 cmpw 0,12,0
1339 beq 0,<disp>
1340 addi 12,12,-<some immediate>
1341 stw 0,0(12)
1342 b <disp>
0df8b418 1343 [possibly one last probe: stw 0,<some immediate>(12)]. */
de9f48f0
JG		 1344
1345 while (1)
1346 {
1347 /* addi 12,1,-<some immediate> */
1348 if ((op & 0xffff0000) != 0x39810000)
1349 break;
1350
1351 /* lis 0,-<some immediate> */
1352 pc = pc + 4;
e17a4113 1353 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1354 if ((op & 0xffff0000) != 0x3c000000)
1355 break;
1356
1357 pc = pc + 4;
e17a4113 1358 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1359 /* [possibly ori 0,0,<some immediate>] */
1360 if ((op & 0xffff0000) == 0x60000000)
1361 {
1362 pc = pc + 4;
e17a4113 1363 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1364 }
1365 /* add 0,12,0 */
1366 if (op != 0x7c0c0214)
1367 break;
1368
1369 /* cmpw 0,12,0 */
1370 pc = pc + 4;
e17a4113 1371 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1372 if (op != 0x7c0c0000)
1373 break;
1374
1375 /* beq 0,<disp> */
1376 pc = pc + 4;
e17a4113 1377 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1378 if ((op & 0xff9f0001) != 0x41820000)
1379 break;
1380
1381 /* addi 12,12,-<some immediate> */
1382 pc = pc + 4;
e17a4113 1383 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1384 if ((op & 0xffff0000) != 0x398c0000)
1385 break;
1386
1387 /* stw 0,0(12) */
1388 pc = pc + 4;
e17a4113 1389 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1390 if (op != 0x900c0000)
1391 break;
1392
1393 /* b <disp> */
1394 pc = pc + 4;
e17a4113 1395 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1396 if ((op & 0xfc000001) != 0x48000000)
1397 break;
1398
0df8b418 1399 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
de9f48f0 1400 pc = pc + 4;
e17a4113 1401 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1402 if ((op & 0xffff0000) == 0x900c0000)
1403 {
1404 pc = pc + 4;
e17a4113 1405 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1406 }
1407
1408 /* We found a valid stack-check sequence, return the new PC. */
1409 return pc;
1410 }
1411
1412 /* Third sequence: No probe; instead, a comparizon between the stack size
1413 limit (saved in a run-time global variable) and the current stack
1414 pointer:
1415
1416 addi 0,1,-<some immediate>
1417 lis 12,__gnat_stack_limit@ha
1418 lwz 12,__gnat_stack_limit@l(12)
1419 twllt 0,12
1420
1421 or, with a small variant in the case of a bigger stack frame:
1422 addis 0,1,<some immediate>
1423 addic 0,0,-<some immediate>
1424 lis 12,__gnat_stack_limit@ha
1425 lwz 12,__gnat_stack_limit@l(12)
1426 twllt 0,12
1427 */
1428 while (1)
1429 {
1430 /* addi 0,1,-<some immediate> */
1431 if ((op & 0xffff0000) != 0x38010000)
1432 {
1433 /* small stack frame variant not recognized; try the
1434 big stack frame variant: */
1435
1436 /* addis 0,1,<some immediate> */
1437 if ((op & 0xffff0000) != 0x3c010000)
1438 break;
1439
1440 /* addic 0,0,-<some immediate> */
1441 pc = pc + 4;
e17a4113 1442 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1443 if ((op & 0xffff0000) != 0x30000000)
1444 break;
1445 }
1446
1447 /* lis 12,<some immediate> */
1448 pc = pc + 4;
e17a4113 1449 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1450 if ((op & 0xffff0000) != 0x3d800000)
1451 break;
1452
1453 /* lwz 12,<some immediate>(12) */
1454 pc = pc + 4;
e17a4113 1455 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1456 if ((op & 0xffff0000) != 0x818c0000)
1457 break;
1458
1459 /* twllt 0,12 */
1460 pc = pc + 4;
e17a4113 1461 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1462 if ((op & 0xfffffffe) != 0x7c406008)
1463 break;
1464
1465 /* We found a valid stack-check sequence, return the new PC. */
1466 return pc;
1467 }
1468
1469 /* No stack check code in our prologue, return the start_pc. */
1470 return start_pc;
1471}
1472
6a16c029
TJB		 1473/* return pc value after skipping a function prologue and also return
1474 information about a function frame.
1475
1476 in struct rs6000_framedata fdata:
1477 - frameless is TRUE, if function does not have a frame.
1478 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1479 - offset is the initial size of this stack frame --- the amount by
1480 which we decrement the sp to allocate the frame.
1481 - saved_gpr is the number of the first saved gpr.
1482 - saved_fpr is the number of the first saved fpr.
1483 - saved_vr is the number of the first saved vr.
1484 - saved_ev is the number of the first saved ev.
1485 - alloca_reg is the number of the register used for alloca() handling.
1486 Otherwise -1.
1487 - gpr_offset is the offset of the first saved gpr from the previous frame.
1488 - fpr_offset is the offset of the first saved fpr from the previous frame.
1489 - vr_offset is the offset of the first saved vr from the previous frame.
1490 - ev_offset is the offset of the first saved ev from the previous frame.
1491 - lr_offset is the offset of the saved lr
1492 - cr_offset is the offset of the saved cr
0df8b418 1493 - vrsave_offset is the offset of the saved vrsave register. */
6a16c029 1494
7a78ae4e 1495static CORE_ADDR
be8626e0
MD		 1496skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc,
1497 struct rs6000_framedata *fdata)
c906108c
SS		 1498{
1499 CORE_ADDR orig_pc = pc;
55d05f3b 1500 CORE_ADDR last_prologue_pc = pc;
6be8bc0c 1501 CORE_ADDR li_found_pc = 0;
50fd1280 1502 gdb_byte buf[4];
c906108c
SS		 1503 unsigned long op;
1504 long offset = 0;
6be8bc0c 1505 long vr_saved_offset = 0;
482ca3f5
KB		 1506 int lr_reg = -1;
1507 int cr_reg = -1;
6be8bc0c 1508 int vr_reg = -1;
96ff0de4
EZ		 1509 int ev_reg = -1;
1510 long ev_offset = 0;
6be8bc0c 1511 int vrsave_reg = -1;
c906108c
SS		 1512 int reg;
1513 int framep = 0;
1514 int minimal_toc_loaded = 0;
ddb20c56 1515 int prev_insn_was_prologue_insn = 1;
55d05f3b 1516 int num_skip_non_prologue_insns = 0;
773df3e5 1517 int r0_contains_arg = 0;
be8626e0
MD		 1518 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch);
1519 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 1520 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
c906108c 1521
ddb20c56 1522 memset (fdata, 0, sizeof (struct rs6000_framedata));
c906108c
SS		 1523 fdata->saved_gpr = -1;
1524 fdata->saved_fpr = -1;
6be8bc0c 1525 fdata->saved_vr = -1;
96ff0de4 1526 fdata->saved_ev = -1;
c906108c
SS		 1527 fdata->alloca_reg = -1;
1528 fdata->frameless = 1;
1529 fdata->nosavedpc = 1;
46a9b8ed 1530 fdata->lr_register = -1;
c906108c 1531
e17a4113 1532 pc = rs6000_skip_stack_check (gdbarch, pc);
de9f48f0
JG		 1533 if (pc >= lim_pc)
1534 pc = lim_pc;
1535
55d05f3b 1536 for (;; pc += 4)
c906108c 1537 {
ddb20c56
KB		 1538 /* Sometimes it isn't clear if an instruction is a prologue
1539 instruction or not. When we encounter one of these ambiguous
1540 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
0df8b418 1541 Otherwise, we'll assume that it really is a prologue instruction. */
ddb20c56
KB		 1542 if (prev_insn_was_prologue_insn)
1543 last_prologue_pc = pc;
55d05f3b
KB		 1544
1545 /* Stop scanning if we've hit the limit. */
4e463ff5 1546 if (pc >= lim_pc)
55d05f3b
KB		 1547 break;
1548
ddb20c56
KB		 1549 prev_insn_was_prologue_insn = 1;
1550
55d05f3b 1551 /* Fetch the instruction and convert it to an integer. */
ddb20c56
KB		 1552 if (target_read_memory (pc, buf, 4))
1553 break;
e17a4113 1554 op = extract_unsigned_integer (buf, 4, byte_order);
c906108c 1555
c5aa993b
JM		 1556 if ((op & 0xfc1fffff) == 0x7c0802a6)
1557 { /* mflr Rx */
43b1ab88
AC		 1558 /* Since shared library / PIC code, which needs to get its
1559 address at runtime, can appear to save more than one link
1560 register vis:
1561
1562 *INDENT-OFF*
1563 stwu r1,-304(r1)
1564 mflr r3
1565 bl 0xff570d0 (blrl)
1566 stw r30,296(r1)
1567 mflr r30
1568 stw r31,300(r1)
1569 stw r3,308(r1);
1570 ...
1571 *INDENT-ON*
1572
1573 remember just the first one, but skip over additional
1574 ones. */
721d14ba 1575 if (lr_reg == -1)
46a9b8ed 1576 lr_reg = (op & 0x03e00000) >> 21;
773df3e5
JB		 1577 if (lr_reg == 0)
1578 r0_contains_arg = 0;
c5aa993b 1579 continue;
c5aa993b
JM		 1580 }
1581 else if ((op & 0xfc1fffff) == 0x7c000026)
1582 { /* mfcr Rx */
98f08d3d 1583 cr_reg = (op & 0x03e00000);
773df3e5
JB		 1584 if (cr_reg == 0)
1585 r0_contains_arg = 0;
c5aa993b 1586 continue;
c906108c 1587
c906108c 1588 }
c5aa993b
JM		 1589 else if ((op & 0xfc1f0000) == 0xd8010000)
1590 { /* stfd Rx,NUM(r1) */
1591 reg = GET_SRC_REG (op);
1592 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1593 {
1594 fdata->saved_fpr = reg;
1595 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1596 }
1597 continue;
c906108c 1598
c5aa993b
JM		 1599 }
1600 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
7a78ae4e
ND		 1601 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1602 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1603 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
c5aa993b
JM		 1604 {
1605
1606 reg = GET_SRC_REG (op);
46a9b8ed
DJ		 1607 if ((op & 0xfc1f0000) == 0xbc010000)
1608 fdata->gpr_mask |= ~((1U << reg) - 1);
1609 else
1610 fdata->gpr_mask |= 1U << reg;
c5aa993b
JM		 1611 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1612 {
1613 fdata->saved_gpr = reg;
7a78ae4e 1614 if ((op & 0xfc1f0003) == 0xf8010000)
98f08d3d 1615 op &= ~3UL;
c5aa993b
JM		 1616 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1617 }
1618 continue;
c906108c 1619
ddb20c56
KB		 1620 }
1621 else if ((op & 0xffff0000) == 0x60000000)
1622 {
96ff0de4 1623 /* nop */
ddb20c56
KB		 1624 /* Allow nops in the prologue, but do not consider them to
1625 be part of the prologue unless followed by other prologue
0df8b418 1626 instructions. */
ddb20c56
KB		 1627 prev_insn_was_prologue_insn = 0;
1628 continue;
1629
c906108c 1630 }
c5aa993b
JM		 1631 else if ((op & 0xffff0000) == 0x3c000000)
1632 { /* addis 0,0,NUM, used
1633 for >= 32k frames */
1634 fdata->offset = (op & 0x0000ffff) << 16;
1635 fdata->frameless = 0;
773df3e5 1636 r0_contains_arg = 0;
c5aa993b
JM		 1637 continue;
1638
1639 }
1640 else if ((op & 0xffff0000) == 0x60000000)
1641 { /* ori 0,0,NUM, 2nd ha
1642 lf of >= 32k frames */
1643 fdata->offset |= (op & 0x0000ffff);
1644 fdata->frameless = 0;
773df3e5 1645 r0_contains_arg = 0;
c5aa993b
JM		 1646 continue;
1647
1648 }
be723e22 1649 else if (lr_reg >= 0 &&
98f08d3d
KB		 1650 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1651 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1652 /* stw Rx, NUM(r1) */
1653 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1654 /* stwu Rx, NUM(r1) */
1655 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1656 { /* where Rx == lr */
1657 fdata->lr_offset = offset;
c5aa993b 1658 fdata->nosavedpc = 0;
be723e22
MS		 1659 /* Invalidate lr_reg, but don't set it to -1.
1660 That would mean that it had never been set. */
1661 lr_reg = -2;
98f08d3d
KB		 1662 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1663 (op & 0xfc000000) == 0x90000000) /* stw */
1664 {
1665 /* Does not update r1, so add displacement to lr_offset. */
1666 fdata->lr_offset += SIGNED_SHORT (op);
1667 }
c5aa993b
JM		 1668 continue;
1669
1670 }
be723e22 1671 else if (cr_reg >= 0 &&
98f08d3d
KB		 1672 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1673 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1674 /* stw Rx, NUM(r1) */
1675 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1676 /* stwu Rx, NUM(r1) */
1677 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1678 { /* where Rx == cr */
1679 fdata->cr_offset = offset;
be723e22
MS		 1680 /* Invalidate cr_reg, but don't set it to -1.
1681 That would mean that it had never been set. */
1682 cr_reg = -2;
98f08d3d
KB		 1683 if ((op & 0xfc000003) == 0xf8000000 ||
1684 (op & 0xfc000000) == 0x90000000)
1685 {
1686 /* Does not update r1, so add displacement to cr_offset. */
1687 fdata->cr_offset += SIGNED_SHORT (op);
1688 }
c5aa993b
JM		 1689 continue;
1690
1691 }
721d14ba
DJ		 1692 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1693 {
1694 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1695 prediction bits. If the LR has already been saved, we can
1696 skip it. */
1697 continue;
1698 }
c5aa993b
JM		 1699 else if (op == 0x48000005)
1700 { /* bl .+4 used in
1701 -mrelocatable */
46a9b8ed 1702 fdata->used_bl = 1;
c5aa993b
JM		 1703 continue;
1704
1705 }
1706 else if (op == 0x48000004)
1707 { /* b .+4 (xlc) */
1708 break;
1709
c5aa993b 1710 }
6be8bc0c
EZ		 1711 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1712 in V.4 -mminimal-toc */
c5aa993b
JM		 1713 (op & 0xffff0000) == 0x3bde0000)
1714 { /* addi 30,30,foo@l */
1715 continue;
c906108c 1716
c5aa993b
JM		 1717 }
1718 else if ((op & 0xfc000001) == 0x48000001)
1719 { /* bl foo,
0df8b418 1720 to save fprs??? */
c906108c 1721
c5aa993b 1722 fdata->frameless = 0;
3c77c82a
DJ		 1723
1724 /* If the return address has already been saved, we can skip
1725 calls to blrl (for PIC). */
e17a4113 1726 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op, byte_order))
46a9b8ed
DJ		 1727 {
1728 fdata->used_bl = 1;
1729 continue;
1730 }
3c77c82a 1731
6be8bc0c 1732 /* Don't skip over the subroutine call if it is not within
ebd98106
FF		 1733 the first three instructions of the prologue and either
1734 we have no line table information or the line info tells
1735 us that the subroutine call is not part of the line
1736 associated with the prologue. */
c5aa993b 1737 if ((pc - orig_pc) > 8)
ebd98106
FF		 1738 {
1739 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1740 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1741
0df8b418
MS		 1742 if ((prologue_sal.line == 0)
1743 || (prologue_sal.line != this_sal.line))
ebd98106
FF		 1744 break;
1745 }
c5aa993b 1746
e17a4113 1747 op = read_memory_integer (pc + 4, 4, byte_order);
c5aa993b 1748
6be8bc0c
EZ		 1749 /* At this point, make sure this is not a trampoline
1750 function (a function that simply calls another functions,
1751 and nothing else). If the next is not a nop, this branch
0df8b418 1752 was part of the function prologue. */
c5aa993b
JM		 1753
1754 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
0df8b418
MS		 1755 break; /* Don't skip over
1756 this branch. */
c5aa993b 1757
46a9b8ed
DJ		 1758 fdata->used_bl = 1;
1759 continue;
c5aa993b 1760 }
98f08d3d
KB		 1761 /* update stack pointer */
1762 else if ((op & 0xfc1f0000) == 0x94010000)
1763 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
c5aa993b
JM		 1764 fdata->frameless = 0;
1765 fdata->offset = SIGNED_SHORT (op);
1766 offset = fdata->offset;
1767 continue;
c5aa993b 1768 }
98f08d3d
KB		 1769 else if ((op & 0xfc1f016a) == 0x7c01016e)
1770 { /* stwux rX,r1,rY */
0df8b418 1771 /* No way to figure out what r1 is going to be. */
98f08d3d
KB		 1772 fdata->frameless = 0;
1773 offset = fdata->offset;
1774 continue;
1775 }
1776 else if ((op & 0xfc1f0003) == 0xf8010001)
1777 { /* stdu rX,NUM(r1) */
1778 fdata->frameless = 0;
1779 fdata->offset = SIGNED_SHORT (op & ~3UL);
1780 offset = fdata->offset;
1781 continue;
1782 }
1783 else if ((op & 0xfc1f016a) == 0x7c01016a)
1784 { /* stdux rX,r1,rY */
0df8b418 1785 /* No way to figure out what r1 is going to be. */
c5aa993b
JM		 1786 fdata->frameless = 0;
1787 offset = fdata->offset;
1788 continue;
c5aa993b 1789 }
7313566f
FF		 1790 else if ((op & 0xffff0000) == 0x38210000)
1791 { /* addi r1,r1,SIMM */
1792 fdata->frameless = 0;
1793 fdata->offset += SIGNED_SHORT (op);
1794 offset = fdata->offset;
1795 continue;
1796 }
4e463ff5
DJ		 1797 /* Load up minimal toc pointer. Do not treat an epilogue restore
1798 of r31 as a minimal TOC load. */
0df8b418
MS		 1799 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1800 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
4e463ff5 1801 && !framep
c5aa993b 1802 && !minimal_toc_loaded)
98f08d3d 1803 {
c5aa993b
JM		 1804 minimal_toc_loaded = 1;
1805 continue;
1806
f6077098
KB		 1807 /* move parameters from argument registers to local variable
1808 registers */
1809 }
1810 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1811 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1812 (((op >> 21) & 31) <= 10) &&
0df8b418
MS		 1813 ((long) ((op >> 16) & 31)
1814 >= fdata->saved_gpr)) /* Rx: local var reg */
f6077098
KB		 1815 {
1816 continue;
1817
c5aa993b
JM		 1818 /* store parameters in stack */
1819 }
e802b915 1820 /* Move parameters from argument registers to temporary register. */
773df3e5 1821 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
e802b915 1822 {
c5aa993b
JM		 1823 continue;
1824
1825 /* Set up frame pointer */
1826 }
1827 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1828 || op == 0x7c3f0b78)
1829 { /* mr r31, r1 */
1830 fdata->frameless = 0;
1831 framep = 1;
6f99cb26 1832 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
c5aa993b
JM		 1833 continue;
1834
1835 /* Another way to set up the frame pointer. */
1836 }
1837 else if ((op & 0xfc1fffff) == 0x38010000)
1838 { /* addi rX, r1, 0x0 */
1839 fdata->frameless = 0;
1840 framep = 1;
6f99cb26
AC		 1841 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1842 + ((op & ~0x38010000) >> 21));
c5aa993b 1843 continue;
c5aa993b 1844 }
6be8bc0c
EZ		 1845 /* AltiVec related instructions. */
1846 /* Store the vrsave register (spr 256) in another register for
1847 later manipulation, or load a register into the vrsave
1848 register. 2 instructions are used: mfvrsave and
1849 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1850 and mtspr SPR256, Rn. */
1851 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1852 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1853 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1854 {
1855 vrsave_reg = GET_SRC_REG (op);
1856 continue;
1857 }
1858 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1859 {
1860 continue;
1861 }
1862 /* Store the register where vrsave was saved to onto the stack:
1863 rS is the register where vrsave was stored in a previous
1864 instruction. */
1865 /* 100100 sssss 00001 dddddddd dddddddd */
1866 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1867 {
1868 if (vrsave_reg == GET_SRC_REG (op))
1869 {
1870 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1871 vrsave_reg = -1;
1872 }
1873 continue;
1874 }
1875 /* Compute the new value of vrsave, by modifying the register
1876 where vrsave was saved to. */
1877 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1878 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1879 {
1880 continue;
1881 }
1882 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1883 in a pair of insns to save the vector registers on the
1884 stack. */
1885 /* 001110 00000 00000 iiii iiii iiii iiii */
96ff0de4
EZ		 1886 /* 001110 01110 00000 iiii iiii iiii iiii */
1887 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1888 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
6be8bc0c 1889 {
773df3e5
JB		 1890 if ((op & 0xffff0000) == 0x38000000)
1891 r0_contains_arg = 0;
6be8bc0c
EZ		 1892 li_found_pc = pc;
1893 vr_saved_offset = SIGNED_SHORT (op);
773df3e5
JB		 1894
1895 /* This insn by itself is not part of the prologue, unless
0df8b418 1896 if part of the pair of insns mentioned above. So do not
773df3e5
JB		 1897 record this insn as part of the prologue yet. */
1898 prev_insn_was_prologue_insn = 0;
6be8bc0c
EZ		 1899 }
1900 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1901 /* 011111 sssss 11111 00000 00111001110 */
1902 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1903 {
1904 if (pc == (li_found_pc + 4))
1905 {
1906 vr_reg = GET_SRC_REG (op);
1907 /* If this is the first vector reg to be saved, or if
1908 it has a lower number than others previously seen,
1909 reupdate the frame info. */
1910 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1911 {
1912 fdata->saved_vr = vr_reg;
1913 fdata->vr_offset = vr_saved_offset + offset;
1914 }
1915 vr_saved_offset = -1;
1916 vr_reg = -1;
1917 li_found_pc = 0;
1918 }
1919 }
1920 /* End AltiVec related instructions. */
96ff0de4
EZ		 1921
1922 /* Start BookE related instructions. */
1923 /* Store gen register S at (r31+uimm).
1924 Any register less than r13 is volatile, so we don't care. */
1925 /* 000100 sssss 11111 iiiii 01100100001 */
1926 else if (arch_info->mach == bfd_mach_ppc_e500
1927 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1928 {
1929 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1930 {
1931 unsigned int imm;
1932 ev_reg = GET_SRC_REG (op);
1933 imm = (op >> 11) & 0x1f;
1934 ev_offset = imm * 8;
1935 /* If this is the first vector reg to be saved, or if
1936 it has a lower number than others previously seen,
1937 reupdate the frame info. */
1938 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1939 {
1940 fdata->saved_ev = ev_reg;
1941 fdata->ev_offset = ev_offset + offset;
1942 }
1943 }
1944 continue;
1945 }
1946 /* Store gen register rS at (r1+rB). */
1947 /* 000100 sssss 00001 bbbbb 01100100000 */
1948 else if (arch_info->mach == bfd_mach_ppc_e500
1949 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1950 {
1951 if (pc == (li_found_pc + 4))
1952 {
1953 ev_reg = GET_SRC_REG (op);
1954 /* If this is the first vector reg to be saved, or if
1955 it has a lower number than others previously seen,
1956 reupdate the frame info. */
1957 /* We know the contents of rB from the previous instruction. */
1958 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1959 {
1960 fdata->saved_ev = ev_reg;
1961 fdata->ev_offset = vr_saved_offset + offset;
1962 }
1963 vr_saved_offset = -1;
1964 ev_reg = -1;
1965 li_found_pc = 0;
1966 }
1967 continue;
1968 }
1969 /* Store gen register r31 at (rA+uimm). */
1970 /* 000100 11111 aaaaa iiiii 01100100001 */
1971 else if (arch_info->mach == bfd_mach_ppc_e500
1972 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1973 {
1974 /* Wwe know that the source register is 31 already, but
1975 it can't hurt to compute it. */
1976 ev_reg = GET_SRC_REG (op);
1977 ev_offset = ((op >> 11) & 0x1f) * 8;
1978 /* If this is the first vector reg to be saved, or if
1979 it has a lower number than others previously seen,
1980 reupdate the frame info. */
1981 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1982 {
1983 fdata->saved_ev = ev_reg;
1984 fdata->ev_offset = ev_offset + offset;
1985 }
1986
1987 continue;
1988 }
1989 /* Store gen register S at (r31+r0).
1990 Store param on stack when offset from SP bigger than 4 bytes. */
1991 /* 000100 sssss 11111 00000 01100100000 */
1992 else if (arch_info->mach == bfd_mach_ppc_e500
1993 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1994 {
1995 if (pc == (li_found_pc + 4))
1996 {
1997 if ((op & 0x03e00000) >= 0x01a00000)
1998 {
1999 ev_reg = GET_SRC_REG (op);
2000 /* If this is the first vector reg to be saved, or if
2001 it has a lower number than others previously seen,
2002 reupdate the frame info. */
2003 /* We know the contents of r0 from the previous
2004 instruction. */
2005 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
2006 {
2007 fdata->saved_ev = ev_reg;
2008 fdata->ev_offset = vr_saved_offset + offset;
2009 }
2010 ev_reg = -1;
2011 }
2012 vr_saved_offset = -1;
2013 li_found_pc = 0;
2014 continue;
2015 }
2016 }
2017 /* End BookE related instructions. */
2018
c5aa993b
JM		 2019 else
2020 {
46a9b8ed
DJ		 2021 unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1);
2022
55d05f3b
KB		 2023 /* Not a recognized prologue instruction.
2024 Handle optimizer code motions into the prologue by continuing
2025 the search if we have no valid frame yet or if the return
46a9b8ed
DJ		 2026 address is not yet saved in the frame. Also skip instructions
2027 if some of the GPRs expected to be saved are not yet saved. */
2028 if (fdata->frameless == 0 && fdata->nosavedpc == 0
2029 && (fdata->gpr_mask & all_mask) == all_mask)
55d05f3b
KB		 2030 break;
2031
2032 if (op == 0x4e800020 /* blr */
2033 || op == 0x4e800420) /* bctr */
2034 /* Do not scan past epilogue in frameless functions or
2035 trampolines. */
2036 break;
2037 if ((op & 0xf4000000) == 0x40000000) /* bxx */
64366f1c 2038 /* Never skip branches. */
55d05f3b
KB		 2039 break;
2040
2041 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
2042 /* Do not scan too many insns, scanning insns is expensive with
2043 remote targets. */
2044 break;
2045
2046 /* Continue scanning. */
2047 prev_insn_was_prologue_insn = 0;
2048 continue;
c5aa993b 2049 }
c906108c
SS		 2050 }
2051
2052#if 0
2053/* I have problems with skipping over __main() that I need to address
0df8b418 2054 * sometime. Previously, I used to use misc_function_vector which
c906108c
SS		 2055 * didn't work as well as I wanted to be. -MGO */
2056
2057 /* If the first thing after skipping a prolog is a branch to a function,
2058 this might be a call to an initializer in main(), introduced by gcc2.
64366f1c 2059 We'd like to skip over it as well. Fortunately, xlc does some extra
c906108c 2060 work before calling a function right after a prologue, thus we can
64366f1c 2061 single out such gcc2 behaviour. */
c906108c 2062
c906108c 2063
c5aa993b 2064 if ((op & 0xfc000001) == 0x48000001)
0df8b418 2065 { /* bl foo, an initializer function? */
e17a4113 2066 op = read_memory_integer (pc + 4, 4, byte_order);
c5aa993b
JM		 2067
2068 if (op == 0x4def7b82)
2069 { /* cror 0xf, 0xf, 0xf (nop) */
c906108c 2070
64366f1c
EZ		 2071 /* Check and see if we are in main. If so, skip over this
2072 initializer function as well. */
c906108c 2073
c5aa993b 2074 tmp = find_pc_misc_function (pc);
6314a349
AC		 2075 if (tmp >= 0
2076 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
c5aa993b
JM		 2077 return pc + 8;
2078 }
c906108c 2079 }
c906108c 2080#endif /* 0 */
c5aa993b 2081
46a9b8ed
DJ		 2082 if (pc == lim_pc && lr_reg >= 0)
2083 fdata->lr_register = lr_reg;
2084
c5aa993b 2085 fdata->offset = -fdata->offset;
ddb20c56 2086 return last_prologue_pc;
c906108c
SS		 2087}
2088
7a78ae4e 2089static CORE_ADDR
4a7622d1 2090rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
c906108c 2091{
4a7622d1 2092 struct rs6000_framedata frame;
e3acb115 2093 CORE_ADDR limit_pc, func_addr, func_end_addr = 0;
c906108c 2094
4a7622d1
UW		 2095 /* See if we can determine the end of the prologue via the symbol table.
2096 If so, then return either PC, or the PC after the prologue, whichever
2097 is greater. */
e3acb115 2098 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr))
c5aa993b 2099 {
d80b854b
UW		 2100 CORE_ADDR post_prologue_pc
2101 = skip_prologue_using_sal (gdbarch, func_addr);
4a7622d1
UW		 2102 if (post_prologue_pc != 0)
2103 return max (pc, post_prologue_pc);
c906108c 2104 }
c906108c 2105
4a7622d1
UW		 2106 /* Can't determine prologue from the symbol table, need to examine
2107 instructions. */
c906108c 2108
4a7622d1
UW		 2109 /* Find an upper limit on the function prologue using the debug
2110 information. If the debug information could not be used to provide
2111 that bound, then use an arbitrary large number as the upper bound. */
d80b854b 2112 limit_pc = skip_prologue_using_sal (gdbarch, pc);
4a7622d1
UW		 2113 if (limit_pc == 0)
2114 limit_pc = pc + 100; /* Magic. */
794a477a 2115
e3acb115
JB		 2116 /* Do not allow limit_pc to be past the function end, if we know
2117 where that end is... */
2118 if (func_end_addr && limit_pc > func_end_addr)
2119 limit_pc = func_end_addr;
2120
4a7622d1
UW		 2121 pc = skip_prologue (gdbarch, pc, limit_pc, &frame);
2122 return pc;
c906108c 2123}
c906108c 2124
8ab3d180
KB		 2125/* When compiling for EABI, some versions of GCC emit a call to __eabi
2126 in the prologue of main().
2127
2128 The function below examines the code pointed at by PC and checks to
2129 see if it corresponds to a call to __eabi. If so, it returns the
2130 address of the instruction following that call. Otherwise, it simply
2131 returns PC. */
2132
63807e1d 2133static CORE_ADDR
8ab3d180
KB		 2134rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2135{
e17a4113 2136 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8ab3d180
KB		 2137 gdb_byte buf[4];
2138 unsigned long op;
2139
2140 if (target_read_memory (pc, buf, 4))
2141 return pc;
e17a4113 2142 op = extract_unsigned_integer (buf, 4, byte_order);
8ab3d180
KB		 2143
2144 if ((op & BL_MASK) == BL_INSTRUCTION)
2145 {
2146 CORE_ADDR displ = op & BL_DISPLACEMENT_MASK;
2147 CORE_ADDR call_dest = pc + 4 + displ;
2148 struct minimal_symbol *s = lookup_minimal_symbol_by_pc (call_dest);
2149
2150 /* We check for ___eabi (three leading underscores) in addition
2151 to __eabi in case the GCC option "-fleading-underscore" was
2152 used to compile the program. */
2153 if (s != NULL
2154 && SYMBOL_LINKAGE_NAME (s) != NULL
2155 && (strcmp (SYMBOL_LINKAGE_NAME (s), "__eabi") == 0
2156 || strcmp (SYMBOL_LINKAGE_NAME (s), "___eabi") == 0))
2157 pc += 4;
2158 }
2159 return pc;
2160}
383f0f5b 2161
4a7622d1
UW		 2162/* All the ABI's require 16 byte alignment. */
2163static CORE_ADDR
2164rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2165{
2166 return (addr & -16);
c906108c
SS		 2167}
2168
977adac5
ND		 2169/* Return whether handle_inferior_event() should proceed through code
2170 starting at PC in function NAME when stepping.
2171
2172 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2173 handle memory references that are too distant to fit in instructions
2174 generated by the compiler. For example, if 'foo' in the following
2175 instruction:
2176
2177 lwz r9,foo(r2)
2178
2179 is greater than 32767, the linker might replace the lwz with a branch to
2180 somewhere in @FIX1 that does the load in 2 instructions and then branches
2181 back to where execution should continue.
2182
2183 GDB should silently step over @FIX code, just like AIX dbx does.
2ec664f5
MS		 2184 Unfortunately, the linker uses the "b" instruction for the
2185 branches, meaning that the link register doesn't get set.
2186 Therefore, GDB's usual step_over_function () mechanism won't work.
977adac5 2187
e76f05fa
UW		 2188 Instead, use the gdbarch_skip_trampoline_code and
2189 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2ec664f5 2190 @FIX code. */
977adac5 2191
63807e1d 2192static int
e17a4113
UW		 2193rs6000_in_solib_return_trampoline (struct gdbarch *gdbarch,
2194 CORE_ADDR pc, char *name)
977adac5
ND		 2195{
2196 return name && !strncmp (name, "@FIX", 4);
2197}
2198
2199/* Skip code that the user doesn't want to see when stepping:
2200
2201 1. Indirect function calls use a piece of trampoline code to do context
2202 switching, i.e. to set the new TOC table. Skip such code if we are on
2203 its first instruction (as when we have single-stepped to here).
2204
2205 2. Skip shared library trampoline code (which is different from
c906108c 2206 indirect function call trampolines).
977adac5
ND		 2207
2208 3. Skip bigtoc fixup code.
2209
c906108c 2210 Result is desired PC to step until, or NULL if we are not in
977adac5 2211 code that should be skipped. */
c906108c 2212
63807e1d 2213static CORE_ADDR
52f729a7 2214rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
c906108c 2215{
e17a4113
UW		 2216 struct gdbarch *gdbarch = get_frame_arch (frame);
2217 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2218 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
52f0bd74 2219 unsigned int ii, op;
977adac5 2220 int rel;
c906108c 2221 CORE_ADDR solib_target_pc;
977adac5 2222 struct minimal_symbol *msymbol;
c906108c 2223
c5aa993b
JM		 2224 static unsigned trampoline_code[] =
2225 {
2226 0x800b0000, /* l r0,0x0(r11) */
2227 0x90410014, /* st r2,0x14(r1) */
2228 0x7c0903a6, /* mtctr r0 */
2229 0x804b0004, /* l r2,0x4(r11) */
2230 0x816b0008, /* l r11,0x8(r11) */
2231 0x4e800420, /* bctr */
2232 0x4e800020, /* br */
2233 0
c906108c
SS		 2234 };
2235
977adac5
ND		 2236 /* Check for bigtoc fixup code. */
2237 msymbol = lookup_minimal_symbol_by_pc (pc);
2ec664f5 2238 if (msymbol
e17a4113
UW		 2239 && rs6000_in_solib_return_trampoline (gdbarch, pc,
2240 SYMBOL_LINKAGE_NAME (msymbol)))
977adac5
ND		 2241 {
2242 /* Double-check that the third instruction from PC is relative "b". */
e17a4113 2243 op = read_memory_integer (pc + 8, 4, byte_order);
977adac5
ND		 2244 if ((op & 0xfc000003) == 0x48000000)
2245 {
2246 /* Extract bits 6-29 as a signed 24-bit relative word address and
2247 add it to the containing PC. */
2248 rel = ((int)(op << 6) >> 6);
2249 return pc + 8 + rel;
2250 }
2251 }
2252
c906108c 2253 /* If pc is in a shared library trampoline, return its target. */
52f729a7 2254 solib_target_pc = find_solib_trampoline_target (frame, pc);
c906108c
SS		 2255 if (solib_target_pc)
2256 return solib_target_pc;
2257
c5aa993b
JM		 2258 for (ii = 0; trampoline_code[ii]; ++ii)
2259 {
e17a4113 2260 op = read_memory_integer (pc + (ii * 4), 4, byte_order);
c5aa993b
JM		 2261 if (op != trampoline_code[ii])
2262 return 0;
2263 }
0df8b418
MS		 2264 ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination
2265 addr. */
e17a4113 2266 pc = read_memory_unsigned_integer (ii, tdep->wordsize, byte_order);
c906108c
SS		 2267 return pc;
2268}
2269
794ac428
UW		 2270/* ISA-specific vector types. */
2271
2272static struct type *
2273rs6000_builtin_type_vec64 (struct gdbarch *gdbarch)
2274{
2275 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2276
2277 if (!tdep->ppc_builtin_type_vec64)
2278 {
df4df182
UW		 2279 const struct builtin_type *bt = builtin_type (gdbarch);
2280
794ac428
UW		 2281 /* The type we're building is this: */
2282#if 0
2283 union __gdb_builtin_type_vec64
2284 {
2285 int64_t uint64;
2286 float v2_float[2];
2287 int32_t v2_int32[2];
2288 int16_t v4_int16[4];
2289 int8_t v8_int8[8];
2290 };
2291#endif
2292
2293 struct type *t;
2294
e9bb382b
UW		 2295 t = arch_composite_type (gdbarch,
2296 "__ppc_builtin_type_vec64", TYPE_CODE_UNION);
df4df182 2297 append_composite_type_field (t, "uint64", bt->builtin_int64);
794ac428 2298 append_composite_type_field (t, "v2_float",
df4df182 2299 init_vector_type (bt->builtin_float, 2));
794ac428 2300 append_composite_type_field (t, "v2_int32",
df4df182 2301 init_vector_type (bt->builtin_int32, 2));
794ac428 2302 append_composite_type_field (t, "v4_int16",
df4df182 2303 init_vector_type (bt->builtin_int16, 4));
794ac428 2304 append_composite_type_field (t, "v8_int8",
df4df182 2305 init_vector_type (bt->builtin_int8, 8));
794ac428 2306
876cecd0 2307 TYPE_VECTOR (t) = 1;
794ac428
UW		 2308 TYPE_NAME (t) = "ppc_builtin_type_vec64";
2309 tdep->ppc_builtin_type_vec64 = t;
2310 }
2311
2312 return tdep->ppc_builtin_type_vec64;
2313}
2314
604c2f83
LM		 2315/* Vector 128 type. */
2316
2317static struct type *
2318rs6000_builtin_type_vec128 (struct gdbarch *gdbarch)
2319{
2320 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2321
2322 if (!tdep->ppc_builtin_type_vec128)
2323 {
df4df182
UW		 2324 const struct builtin_type *bt = builtin_type (gdbarch);
2325
604c2f83
LM		 2326 /* The type we're building is this
2327
2328 type = union __ppc_builtin_type_vec128 {
2329 uint128_t uint128;
db9f5df8 2330 double v2_double[2];
604c2f83
LM		 2331 float v4_float[4];
2332 int32_t v4_int32[4];
2333 int16_t v8_int16[8];
2334 int8_t v16_int8[16];
2335 }
2336 */
2337
2338 struct type *t;
2339
e9bb382b
UW		 2340 t = arch_composite_type (gdbarch,
2341 "__ppc_builtin_type_vec128", TYPE_CODE_UNION);
df4df182 2342 append_composite_type_field (t, "uint128", bt->builtin_uint128);
db9f5df8
UW		 2343 append_composite_type_field (t, "v2_double",
2344 init_vector_type (bt->builtin_double, 2));
604c2f83 2345 append_composite_type_field (t, "v4_float",
df4df182 2346 init_vector_type (bt->builtin_float, 4));
604c2f83 2347 append_composite_type_field (t, "v4_int32",
df4df182 2348 init_vector_type (bt->builtin_int32, 4));
604c2f83 2349 append_composite_type_field (t, "v8_int16",
df4df182 2350 init_vector_type (bt->builtin_int16, 8));
604c2f83 2351 append_composite_type_field (t, "v16_int8",
df4df182 2352 init_vector_type (bt->builtin_int8, 16));
604c2f83 2353
803e1097 2354 TYPE_VECTOR (t) = 1;
604c2f83
LM		 2355 TYPE_NAME (t) = "ppc_builtin_type_vec128";
2356 tdep->ppc_builtin_type_vec128 = t;
2357 }
2358
2359 return tdep->ppc_builtin_type_vec128;
2360}
2361
7cc46491
DJ		 2362/* Return the name of register number REGNO, or the empty string if it
2363 is an anonymous register. */
7a78ae4e 2364
fa88f677 2365static const char *
d93859e2 2366rs6000_register_name (struct gdbarch *gdbarch, int regno)
7a78ae4e 2367{
d93859e2 2368 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7a78ae4e 2369
7cc46491
DJ		 2370 /* The upper half "registers" have names in the XML description,
2371 but we present only the low GPRs and the full 64-bit registers
2372 to the user. */
2373 if (tdep->ppc_ev0_upper_regnum >= 0
2374 && tdep->ppc_ev0_upper_regnum <= regno
2375 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
2376 return "";
2377
604c2f83
LM		 2378 /* Hide the upper halves of the vs0~vs31 registers. */
2379 if (tdep->ppc_vsr0_regnum >= 0
2380 && tdep->ppc_vsr0_upper_regnum <= regno
2381 && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs)
2382 return "";
2383
7cc46491 2384 /* Check if the SPE pseudo registers are available. */
5a9e69ba 2385 if (IS_SPE_PSEUDOREG (tdep, regno))
7cc46491
DJ		 2386 {
2387 static const char *const spe_regnames[] = {
2388 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2389 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2390 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2391 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2392 };
2393 return spe_regnames[regno - tdep->ppc_ev0_regnum];
2394 }
2395
f949c649
TJB		 2396 /* Check if the decimal128 pseudo-registers are available. */
2397 if (IS_DFP_PSEUDOREG (tdep, regno))
2398 {
2399 static const char *const dfp128_regnames[] = {
2400 "dl0", "dl1", "dl2", "dl3",
2401 "dl4", "dl5", "dl6", "dl7",
2402 "dl8", "dl9", "dl10", "dl11",
2403 "dl12", "dl13", "dl14", "dl15"
2404 };
2405 return dfp128_regnames[regno - tdep->ppc_dl0_regnum];
2406 }
2407
604c2f83
LM		 2408 /* Check if this is a VSX pseudo-register. */
2409 if (IS_VSX_PSEUDOREG (tdep, regno))
2410 {
2411 static const char *const vsx_regnames[] = {
2412 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2413 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2414 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2415 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2416 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2417 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2418 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2419 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2420 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2421 };
2422 return vsx_regnames[regno - tdep->ppc_vsr0_regnum];
2423 }
2424
2425 /* Check if the this is a Extended FP pseudo-register. */
2426 if (IS_EFP_PSEUDOREG (tdep, regno))
2427 {
2428 static const char *const efpr_regnames[] = {
2429 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2430 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2431 "f46", "f47", "f48", "f49", "f50", "f51",
2432 "f52", "f53", "f54", "f55", "f56", "f57",
2433 "f58", "f59", "f60", "f61", "f62", "f63"
2434 };
2435 return efpr_regnames[regno - tdep->ppc_efpr0_regnum];
2436 }
2437
d93859e2 2438 return tdesc_register_name (gdbarch, regno);
7a78ae4e
ND		 2439}
2440
7cc46491
DJ		 2441/* Return the GDB type object for the "standard" data type of data in
2442 register N. */
7a78ae4e
ND		 2443
2444static struct type *
7cc46491 2445rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
7a78ae4e 2446{
691d145a 2447 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7a78ae4e 2448
7cc46491 2449 /* These are the only pseudo-registers we support. */
f949c649 2450 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
604c2f83
LM		 2451 || IS_DFP_PSEUDOREG (tdep, regnum)
2452 || IS_VSX_PSEUDOREG (tdep, regnum)
2453 || IS_EFP_PSEUDOREG (tdep, regnum));
7cc46491 2454
f949c649
TJB		 2455 /* These are the e500 pseudo-registers. */
2456 if (IS_SPE_PSEUDOREG (tdep, regnum))
2457 return rs6000_builtin_type_vec64 (gdbarch);
604c2f83
LM		 2458 else if (IS_DFP_PSEUDOREG (tdep, regnum))
2459 /* PPC decimal128 pseudo-registers. */
f949c649 2460 return builtin_type (gdbarch)->builtin_declong;
604c2f83
LM		 2461 else if (IS_VSX_PSEUDOREG (tdep, regnum))
2462 /* POWER7 VSX pseudo-registers. */
2463 return rs6000_builtin_type_vec128 (gdbarch);
2464 else
2465 /* POWER7 Extended FP pseudo-registers. */
2466 return builtin_type (gdbarch)->builtin_double;
7a78ae4e
ND		 2467}
2468
c44ca51c
AC		 2469/* Is REGNUM a member of REGGROUP? */
2470static int
7cc46491
DJ		 2471rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2472 struct reggroup *group)
c44ca51c
AC		 2473{
2474 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
c44ca51c 2475
7cc46491 2476 /* These are the only pseudo-registers we support. */
f949c649 2477 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
604c2f83
LM		 2478 || IS_DFP_PSEUDOREG (tdep, regnum)
2479 || IS_VSX_PSEUDOREG (tdep, regnum)
2480 || IS_EFP_PSEUDOREG (tdep, regnum));
c44ca51c 2481
604c2f83
LM		 2482 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2483 if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum))
f949c649 2484 return group == all_reggroup || group == vector_reggroup;
7cc46491 2485 else
604c2f83 2486 /* PPC decimal128 or Extended FP pseudo-registers. */
f949c649 2487 return group == all_reggroup || group == float_reggroup;
c44ca51c
AC		 2488}
2489
691d145a 2490/* The register format for RS/6000 floating point registers is always
64366f1c 2491 double, we need a conversion if the memory format is float. */
7a78ae4e
ND		 2492
2493static int
0abe36f5
MD		 2494rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum,
2495 struct type *type)
7a78ae4e 2496{
0abe36f5 2497 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7cc46491
DJ		 2498
2499 return (tdep->ppc_fp0_regnum >= 0
2500 && regnum >= tdep->ppc_fp0_regnum
2501 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs
2502 && TYPE_CODE (type) == TYPE_CODE_FLT
0dfff4cb
UW		 2503 && TYPE_LENGTH (type)
2504 != TYPE_LENGTH (builtin_type (gdbarch)->builtin_double));
7a78ae4e
ND		 2505}
2506
7a78ae4e 2507static void
691d145a
JB		 2508rs6000_register_to_value (struct frame_info *frame,
2509 int regnum,
2510 struct type *type,
50fd1280 2511 gdb_byte *to)
7a78ae4e 2512{
0dfff4cb 2513 struct gdbarch *gdbarch = get_frame_arch (frame);
50fd1280 2514 gdb_byte from[MAX_REGISTER_SIZE];
691d145a 2515
691d145a 2516 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
7a78ae4e 2517
691d145a 2518 get_frame_register (frame, regnum, from);
0dfff4cb
UW		 2519 convert_typed_floating (from, builtin_type (gdbarch)->builtin_double,
2520 to, type);
691d145a 2521}
7a292a7a 2522
7a78ae4e 2523static void
691d145a
JB		 2524rs6000_value_to_register (struct frame_info *frame,
2525 int regnum,
2526 struct type *type,
50fd1280 2527 const gdb_byte *from)
7a78ae4e 2528{
0dfff4cb 2529 struct gdbarch *gdbarch = get_frame_arch (frame);
50fd1280 2530 gdb_byte to[MAX_REGISTER_SIZE];
691d145a 2531
691d145a
JB		 2532 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2533
0dfff4cb
UW		 2534 convert_typed_floating (from, type,
2535 to, builtin_type (gdbarch)->builtin_double);
691d145a 2536 put_frame_register (frame, regnum, to);
7a78ae4e 2537}
c906108c 2538
6ced10dd
JB		 2539/* Move SPE vector register values between a 64-bit buffer and the two
2540 32-bit raw register halves in a regcache. This function handles
2541 both splitting a 64-bit value into two 32-bit halves, and joining
2542 two halves into a whole 64-bit value, depending on the function
2543 passed as the MOVE argument.
2544
2545 EV_REG must be the number of an SPE evN vector register --- a
2546 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2547 64-bit buffer.
2548
2549 Call MOVE once for each 32-bit half of that register, passing
2550 REGCACHE, the number of the raw register corresponding to that
2551 half, and the address of the appropriate half of BUFFER.
2552
2553 For example, passing 'regcache_raw_read' as the MOVE function will
2554 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2555 'regcache_raw_supply' will supply the contents of BUFFER to the
2556 appropriate pair of raw registers in REGCACHE.
2557
2558 You may need to cast away some 'const' qualifiers when passing
2559 MOVE, since this function can't tell at compile-time which of
2560 REGCACHE or BUFFER is acting as the source of the data. If C had
2561 co-variant type qualifiers, ... */
2562static void
2563e500_move_ev_register (void (*move) (struct regcache *regcache,
50fd1280 2564 int regnum, gdb_byte *buf),
6ced10dd 2565 struct regcache *regcache, int ev_reg,
50fd1280 2566 gdb_byte *buffer)
6ced10dd
JB		 2567{
2568 struct gdbarch *arch = get_regcache_arch (regcache);
2569 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2570 int reg_index;
50fd1280 2571 gdb_byte *byte_buffer = buffer;
6ced10dd 2572
5a9e69ba 2573 gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg));
6ced10dd
JB		 2574
2575 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2576
8b164abb 2577 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
6ced10dd
JB		 2578 {
2579 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
2580 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
2581 }
2582 else
2583 {
2584 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2585 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
2586 }
2587}
2588
c8001721
EZ		 2589static void
2590e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
50fd1280 2591 int reg_nr, gdb_byte *buffer)
f949c649
TJB		 2592{
2593 e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
2594}
2595
2596static void
2597e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2598 int reg_nr, const gdb_byte *buffer)
2599{
2600 e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *))
2601 regcache_raw_write,
2602 regcache, reg_nr, (gdb_byte *) buffer);
2603}
2604
604c2f83 2605/* Read method for DFP pseudo-registers. */
f949c649 2606static void
604c2f83 2607dfp_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
f949c649
TJB		 2608 int reg_nr, gdb_byte *buffer)
2609{
2610 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2611 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2612
2613 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2614 {
2615 /* Read two FP registers to form a whole dl register. */
2616 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2617 2 * reg_index, buffer);
2618 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2619 2 * reg_index + 1, buffer + 8);
2620 }
2621 else
2622 {
2623 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2624 2 * reg_index + 1, buffer + 8);
2625 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2626 2 * reg_index, buffer);
2627 }
2628}
2629
604c2f83 2630/* Write method for DFP pseudo-registers. */
f949c649 2631static void
604c2f83 2632dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
f949c649
TJB		 2633 int reg_nr, const gdb_byte *buffer)
2634{
2635 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2636 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2637
2638 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2639 {
2640 /* Write each half of the dl register into a separate
2641 FP register. */
2642 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2643 2 * reg_index, buffer);
2644 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2645 2 * reg_index + 1, buffer + 8);
2646 }
2647 else
2648 {
2649 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2650 2 * reg_index + 1, buffer + 8);
2651 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2652 2 * reg_index, buffer);
2653 }
2654}
2655
604c2f83
LM		 2656/* Read method for POWER7 VSX pseudo-registers. */
2657static void
2658vsx_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2659 int reg_nr, gdb_byte *buffer)
2660{
2661 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2662 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2663
2664 /* Read the portion that overlaps the VMX registers. */
2665 if (reg_index > 31)
2666 regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2667 reg_index - 32, buffer);
2668 else
2669 /* Read the portion that overlaps the FPR registers. */
2670 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2671 {
2672 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2673 reg_index, buffer);
2674 regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2675 reg_index, buffer + 8);
2676 }
2677 else
2678 {
2679 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2680 reg_index, buffer + 8);
2681 regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2682 reg_index, buffer);
2683 }
2684}
2685
2686/* Write method for POWER7 VSX pseudo-registers. */
2687static void
2688vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2689 int reg_nr, const gdb_byte *buffer)
2690{
2691 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2692 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2693
2694 /* Write the portion that overlaps the VMX registers. */
2695 if (reg_index > 31)
2696 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2697 reg_index - 32, buffer);
2698 else
2699 /* Write the portion that overlaps the FPR registers. */
2700 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2701 {
2702 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2703 reg_index, buffer);
2704 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2705 reg_index, buffer + 8);
2706 }
2707 else
2708 {
2709 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2710 reg_index, buffer + 8);
2711 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2712 reg_index, buffer);
2713 }
2714}
2715
2716/* Read method for POWER7 Extended FP pseudo-registers. */
2717static void
2718efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2719 int reg_nr, gdb_byte *buffer)
2720{
2721 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2722 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2723
2724 /* Read the portion that overlaps the VMX registers. */
2725 regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2726 reg_index, buffer);
2727}
2728
2729/* Write method for POWER7 Extended FP pseudo-registers. */
2730static void
2731efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2732 int reg_nr, const gdb_byte *buffer)
2733{
2734 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2735 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2736
2737 /* Write the portion that overlaps the VMX registers. */
2738 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2739 reg_index, buffer);
2740}
2741
f949c649 2742static void
0df8b418
MS		 2743rs6000_pseudo_register_read (struct gdbarch *gdbarch,
2744 struct regcache *regcache,
f949c649 2745 int reg_nr, gdb_byte *buffer)
c8001721 2746{
6ced10dd 2747 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
c8001721
EZ		 2748 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2749
6ced10dd 2750 gdb_assert (regcache_arch == gdbarch);
f949c649 2751
5a9e69ba 2752 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
f949c649
TJB		 2753 e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2754 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
604c2f83
LM		 2755 dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2756 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2757 vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2758 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2759 efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
6ced10dd 2760 else
a44bddec 2761 internal_error (__FILE__, __LINE__,
f949c649
TJB		 2762 _("rs6000_pseudo_register_read: "
2763 "called on unexpected register '%s' (%d)"),
2764 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
c8001721
EZ		 2765}
2766
2767static void
f949c649
TJB		 2768rs6000_pseudo_register_write (struct gdbarch *gdbarch,
2769 struct regcache *regcache,
2770 int reg_nr, const gdb_byte *buffer)
c8001721 2771{
6ced10dd 2772 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
c8001721
EZ		 2773 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2774
6ced10dd 2775 gdb_assert (regcache_arch == gdbarch);
f949c649 2776
5a9e69ba 2777 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
f949c649
TJB		 2778 e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2779 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
604c2f83
LM		 2780 dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2781 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2782 vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2783 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2784 efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
6ced10dd 2785 else
a44bddec 2786 internal_error (__FILE__, __LINE__,
f949c649
TJB		 2787 _("rs6000_pseudo_register_write: "
2788 "called on unexpected register '%s' (%d)"),
2789 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
6ced10dd
JB		 2790}
2791
18ed0c4e 2792/* Convert a DBX STABS register number to a GDB register number. */
c8001721 2793static int
d3f73121 2794rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
c8001721 2795{
d3f73121 2796 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
c8001721 2797
9f744501
JB		 2798 if (0 <= num && num <= 31)
2799 return tdep->ppc_gp0_regnum + num;
2800 else if (32 <= num && num <= 63)
383f0f5b
JB		 2801 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2802 specifies registers the architecture doesn't have? Our
2803 callers don't check the value we return. */
366f009f 2804 return tdep->ppc_fp0_regnum + (num - 32);
18ed0c4e
JB		 2805 else if (77 <= num && num <= 108)
2806 return tdep->ppc_vr0_regnum + (num - 77);
9f744501
JB		 2807 else if (1200 <= num && num < 1200 + 32)
2808 return tdep->ppc_ev0_regnum + (num - 1200);
2809 else
2810 switch (num)
2811 {
2812 case 64:
2813 return tdep->ppc_mq_regnum;
2814 case 65:
2815 return tdep->ppc_lr_regnum;
2816 case 66:
2817 return tdep->ppc_ctr_regnum;
2818 case 76:
2819 return tdep->ppc_xer_regnum;
2820 case 109:
2821 return tdep->ppc_vrsave_regnum;
18ed0c4e
JB		 2822 case 110:
2823 return tdep->ppc_vrsave_regnum - 1; /* vscr */
867e2dc5 2824 case 111:
18ed0c4e 2825 return tdep->ppc_acc_regnum;
867e2dc5 2826 case 112:
18ed0c4e 2827 return tdep->ppc_spefscr_regnum;
9f744501
JB		 2828 default:
2829 return num;
2830 }
18ed0c4e 2831}
9f744501 2832
9f744501 2833
18ed0c4e
JB		 2834/* Convert a Dwarf 2 register number to a GDB register number. */
2835static int
d3f73121 2836rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
18ed0c4e 2837{
d3f73121 2838 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9f744501 2839
18ed0c4e
JB		 2840 if (0 <= num && num <= 31)
2841 return tdep->ppc_gp0_regnum + num;
2842 else if (32 <= num && num <= 63)
2843 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2844 specifies registers the architecture doesn't have? Our
2845 callers don't check the value we return. */
2846 return tdep->ppc_fp0_regnum + (num - 32);
2847 else if (1124 <= num && num < 1124 + 32)
2848 return tdep->ppc_vr0_regnum + (num - 1124);
2849 else if (1200 <= num && num < 1200 + 32)
2850 return tdep->ppc_ev0_regnum + (num - 1200);
2851 else
2852 switch (num)
2853 {
a489f789
AS		 2854 case 64:
2855 return tdep->ppc_cr_regnum;
18ed0c4e
JB		 2856 case 67:
2857 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2858 case 99:
2859 return tdep->ppc_acc_regnum;
2860 case 100:
2861 return tdep->ppc_mq_regnum;
2862 case 101:
2863 return tdep->ppc_xer_regnum;
2864 case 108:
2865 return tdep->ppc_lr_regnum;
2866 case 109:
2867 return tdep->ppc_ctr_regnum;
2868 case 356:
2869 return tdep->ppc_vrsave_regnum;
2870 case 612:
2871 return tdep->ppc_spefscr_regnum;
2872 default:
2873 return num;
2874 }
2188cbdd
EZ		 2875}
2876
4fc771b8
DJ		 2877/* Translate a .eh_frame register to DWARF register, or adjust a
2878 .debug_frame register. */
2879
2880static int
2881rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
2882{
2883 /* GCC releases before 3.4 use GCC internal register numbering in
2884 .debug_frame (and .debug_info, et cetera). The numbering is
2885 different from the standard SysV numbering for everything except
2886 for GPRs and FPRs. We can not detect this problem in most cases
2887 - to get accurate debug info for variables living in lr, ctr, v0,
2888 et cetera, use a newer version of GCC. But we must detect
2889 one important case - lr is in column 65 in .debug_frame output,
2890 instead of 108.
2891
2892 GCC 3.4, and the "hammer" branch, have a related problem. They
2893 record lr register saves in .debug_frame as 108, but still record
2894 the return column as 65. We fix that up too.
2895
2896 We can do this because 65 is assigned to fpsr, and GCC never
2897 generates debug info referring to it. To add support for
2898 handwritten debug info that restores fpsr, we would need to add a
2899 producer version check to this. */
2900 if (!eh_frame_p)
2901 {
2902 if (num == 65)
2903 return 108;
2904 else
2905 return num;
2906 }
2907
2908 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2909 internal register numbering; translate that to the standard DWARF2
2910 register numbering. */
2911 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */
2912 return num;
2913 else if (68 <= num && num <= 75) /* cr0-cr8 */
2914 return num - 68 + 86;
2915 else if (77 <= num && num <= 108) /* vr0-vr31 */
2916 return num - 77 + 1124;
2917 else
2918 switch (num)
2919 {
2920 case 64: /* mq */
2921 return 100;
2922 case 65: /* lr */
2923 return 108;
2924 case 66: /* ctr */
2925 return 109;
2926 case 76: /* xer */
2927 return 101;
2928 case 109: /* vrsave */
2929 return 356;
2930 case 110: /* vscr */
2931 return 67;
2932 case 111: /* spe_acc */
2933 return 99;
2934 case 112: /* spefscr */
2935 return 612;
2936 default:
2937 return num;
2938 }
2939}
c906108c 2940\f
c5aa993b 2941
7a78ae4e 2942/* Handling the various POWER/PowerPC variants. */
c906108c 2943
c906108c 2944/* Information about a particular processor variant. */
7a78ae4e 2945
c906108c 2946struct variant
c5aa993b
JM		 2947 {
2948 /* Name of this variant. */
2949 char *name;
c906108c 2950
c5aa993b
JM		 2951 /* English description of the variant. */
2952 char *description;
c906108c 2953
64366f1c 2954 /* bfd_arch_info.arch corresponding to variant. */
7a78ae4e
ND		 2955 enum bfd_architecture arch;
2956
64366f1c 2957 /* bfd_arch_info.mach corresponding to variant. */
7a78ae4e
ND		 2958 unsigned long mach;
2959
7cc46491
DJ		 2960 /* Target description for this variant. */
2961 struct target_desc **tdesc;
c5aa993b 2962 };
c906108c 2963
489461e2 2964static struct variant variants[] =
c906108c 2965{
7a78ae4e 2966 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
7284e1be 2967 bfd_mach_ppc, &tdesc_powerpc_altivec32},
7a78ae4e 2968 {"power", "POWER user-level", bfd_arch_rs6000,
7cc46491 2969 bfd_mach_rs6k, &tdesc_rs6000},
7a78ae4e 2970 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
7cc46491 2971 bfd_mach_ppc_403, &tdesc_powerpc_403},
4d09ffea
MS		 2972 {"405", "IBM PowerPC 405", bfd_arch_powerpc,
2973 bfd_mach_ppc_405, &tdesc_powerpc_405},
7a78ae4e 2974 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
7cc46491 2975 bfd_mach_ppc_601, &tdesc_powerpc_601},
7a78ae4e 2976 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
7cc46491 2977 bfd_mach_ppc_602, &tdesc_powerpc_602},
7a78ae4e 2978 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
7cc46491 2979 bfd_mach_ppc_603, &tdesc_powerpc_603},
7a78ae4e 2980 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
7cc46491 2981 604, &tdesc_powerpc_604},
7a78ae4e 2982 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
7cc46491 2983 bfd_mach_ppc_403gc, &tdesc_powerpc_403gc},
7a78ae4e 2984 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
7cc46491 2985 bfd_mach_ppc_505, &tdesc_powerpc_505},
7a78ae4e 2986 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
7cc46491 2987 bfd_mach_ppc_860, &tdesc_powerpc_860},
7a78ae4e 2988 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
7cc46491 2989 bfd_mach_ppc_750, &tdesc_powerpc_750},
1fcc0bb8 2990 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
7cc46491 2991 bfd_mach_ppc_7400, &tdesc_powerpc_7400},
c8001721 2992 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
7cc46491 2993 bfd_mach_ppc_e500, &tdesc_powerpc_e500},
7a78ae4e 2994
5d57ee30
KB		 2995 /* 64-bit */
2996 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
7284e1be 2997 bfd_mach_ppc64, &tdesc_powerpc_altivec64},
7a78ae4e 2998 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
7cc46491 2999 bfd_mach_ppc_620, &tdesc_powerpc_64},
5d57ee30 3000 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
7cc46491 3001 bfd_mach_ppc_630, &tdesc_powerpc_64},
7a78ae4e 3002 {"a35", "PowerPC A35", bfd_arch_powerpc,
7cc46491 3003 bfd_mach_ppc_a35, &tdesc_powerpc_64},
5d57ee30 3004 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
7cc46491 3005 bfd_mach_ppc_rs64ii, &tdesc_powerpc_64},
5d57ee30 3006 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
7cc46491 3007 bfd_mach_ppc_rs64iii, &tdesc_powerpc_64},
5d57ee30 3008
64366f1c 3009 /* FIXME: I haven't checked the register sets of the following. */
7a78ae4e 3010 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
7cc46491 3011 bfd_mach_rs6k_rs1, &tdesc_rs6000},
7a78ae4e 3012 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
7cc46491 3013 bfd_mach_rs6k_rsc, &tdesc_rs6000},
7a78ae4e 3014 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
7cc46491 3015 bfd_mach_rs6k_rs2, &tdesc_rs6000},
7a78ae4e 3016
7cc46491 3017 {0, 0, 0, 0, 0}
c906108c
SS		 3018};
3019
7a78ae4e 3020/* Return the variant corresponding to architecture ARCH and machine number
64366f1c 3021 MACH. If no such variant exists, return null. */
c906108c 3022
7a78ae4e
ND		 3023static const struct variant *
3024find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
c906108c 3025{
7a78ae4e 3026 const struct variant *v;
c5aa993b 3027
7a78ae4e
ND		 3028 for (v = variants; v->name; v++)
3029 if (arch == v->arch && mach == v->mach)
3030 return v;
c906108c 3031
7a78ae4e 3032 return NULL;
c906108c 3033}
9364a0ef
EZ		 3034
3035static int
3036gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
3037{
ee4f0f76 3038 if (!info->disassembler_options)
e52d5016
NF		 3039 {
3040 /* When debugging E500 binaries and disassembling code containing
3041 E500-specific (SPE) instructions, one sometimes sees AltiVec
3042 instructions instead. The opcode spaces for SPE instructions
3043 and AltiVec instructions overlap, and specifiying the "any" cpu
3044 looks for AltiVec instructions first. If we know we're
3045 debugging an E500 binary, however, we can specify the "e500x2"
3046 cpu and get much more sane disassembly output. */
3047 if (info->mach == bfd_mach_ppc_e500)
3048 info->disassembler_options = "e500x2";
3049 else
3050 info->disassembler_options = "any";
3051 }
ee4f0f76 3052
40887e1a 3053 if (info->endian == BFD_ENDIAN_BIG)
9364a0ef
EZ		 3054 return print_insn_big_powerpc (memaddr, info);
3055 else
3056 return print_insn_little_powerpc (memaddr, info);
3057}
7a78ae4e 3058\f
61a65099
KB		 3059static CORE_ADDR
3060rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
3061{
3e8c568d 3062 return frame_unwind_register_unsigned (next_frame,
8b164abb 3063 gdbarch_pc_regnum (gdbarch));
61a65099
KB		 3064}
3065
3066static struct frame_id
1af5d7ce 3067rs6000_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
61a65099 3068{
1af5d7ce
UW		 3069 return frame_id_build (get_frame_register_unsigned
3070 (this_frame, gdbarch_sp_regnum (gdbarch)),
3071 get_frame_pc (this_frame));
61a65099
KB		 3072}
3073
3074struct rs6000_frame_cache
3075{
3076 CORE_ADDR base;
3077 CORE_ADDR initial_sp;
3078 struct trad_frame_saved_reg *saved_regs;
3079};
3080
3081static struct rs6000_frame_cache *
1af5d7ce 3082rs6000_frame_cache (struct frame_info *this_frame, void **this_cache)
61a65099
KB		 3083{
3084 struct rs6000_frame_cache *cache;
1af5d7ce 3085 struct gdbarch *gdbarch = get_frame_arch (this_frame);
61a65099 3086 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 3087 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
61a65099
KB		 3088 struct rs6000_framedata fdata;
3089 int wordsize = tdep->wordsize;
e10b1c4c 3090 CORE_ADDR func, pc;
61a65099
KB		 3091
3092 if ((*this_cache) != NULL)
3093 return (*this_cache);
3094 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
3095 (*this_cache) = cache;
1af5d7ce 3096 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
61a65099 3097
1af5d7ce
UW		 3098 func = get_frame_func (this_frame);
3099 pc = get_frame_pc (this_frame);
be8626e0 3100 skip_prologue (gdbarch, func, pc, &fdata);
e10b1c4c
DJ		 3101
3102 /* Figure out the parent's stack pointer. */
3103
3104 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3105 address of the current frame. Things might be easier if the
3106 ->frame pointed to the outer-most address of the frame. In
3107 the mean time, the address of the prev frame is used as the
3108 base address of this frame. */
1af5d7ce
UW		 3109 cache->base = get_frame_register_unsigned
3110 (this_frame, gdbarch_sp_regnum (gdbarch));
e10b1c4c
DJ		 3111
3112 /* If the function appears to be frameless, check a couple of likely
3113 indicators that we have simply failed to find the frame setup.
3114 Two common cases of this are missing symbols (i.e.
ef02daa9 3115 get_frame_func returns the wrong address or 0), and assembly
e10b1c4c
DJ		 3116 stubs which have a fast exit path but set up a frame on the slow
3117 path.
3118
3119 If the LR appears to return to this function, then presume that
3120 we have an ABI compliant frame that we failed to find. */
3121 if (fdata.frameless && fdata.lr_offset == 0)
61a65099 3122 {
e10b1c4c
DJ		 3123 CORE_ADDR saved_lr;
3124 int make_frame = 0;
3125
1af5d7ce 3126 saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum);
e10b1c4c
DJ		 3127 if (func == 0 && saved_lr == pc)
3128 make_frame = 1;
3129 else if (func != 0)
3130 {
3131 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
3132 if (func == saved_func)
3133 make_frame = 1;
3134 }
3135
3136 if (make_frame)
3137 {
3138 fdata.frameless = 0;
de6a76fd 3139 fdata.lr_offset = tdep->lr_frame_offset;
e10b1c4c 3140 }
61a65099 3141 }
e10b1c4c
DJ		 3142
3143 if (!fdata.frameless)
3144 /* Frameless really means stackless. */
e17a4113
UW		 3145 cache->base
3146 = read_memory_unsigned_integer (cache->base, wordsize, byte_order);
e10b1c4c 3147
3e8c568d 3148 trad_frame_set_value (cache->saved_regs,
8b164abb 3149 gdbarch_sp_regnum (gdbarch), cache->base);
61a65099
KB		 3150
3151 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3152 All fpr's from saved_fpr to fp31 are saved. */
3153
3154 if (fdata.saved_fpr >= 0)
3155 {
3156 int i;
3157 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
383f0f5b
JB		 3158
3159 /* If skip_prologue says floating-point registers were saved,
3160 but the current architecture has no floating-point registers,
3161 then that's strange. But we have no indices to even record
3162 the addresses under, so we just ignore it. */
3163 if (ppc_floating_point_unit_p (gdbarch))
063715bf 3164 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
383f0f5b
JB		 3165 {
3166 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3167 fpr_addr += 8;
3168 }
61a65099
KB		 3169 }
3170
3171 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
46a9b8ed
DJ		 3172 All gpr's from saved_gpr to gpr31 are saved (except during the
3173 prologue). */
61a65099
KB		 3174
3175 if (fdata.saved_gpr >= 0)
3176 {
3177 int i;
3178 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
063715bf 3179 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
61a65099 3180 {
46a9b8ed
DJ		 3181 if (fdata.gpr_mask & (1U << i))
3182 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
61a65099
KB		 3183 gpr_addr += wordsize;
3184 }
3185 }
3186
3187 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3188 All vr's from saved_vr to vr31 are saved. */
3189 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3190 {
3191 if (fdata.saved_vr >= 0)
3192 {
3193 int i;
3194 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3195 for (i = fdata.saved_vr; i < 32; i++)
3196 {
3197 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3198 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3199 }
3200 }
3201 }
3202
3203 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
0df8b418 3204 All vr's from saved_ev to ev31 are saved. ????? */
5a9e69ba 3205 if (tdep->ppc_ev0_regnum != -1)
61a65099
KB		 3206 {
3207 if (fdata.saved_ev >= 0)
3208 {
3209 int i;
3210 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
063715bf 3211 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
61a65099
KB		 3212 {
3213 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3214 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
3215 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3216 }
3217 }
3218 }
3219
3220 /* If != 0, fdata.cr_offset is the offset from the frame that
3221 holds the CR. */
3222 if (fdata.cr_offset != 0)
0df8b418
MS		 3223 cache->saved_regs[tdep->ppc_cr_regnum].addr
3224 = cache->base + fdata.cr_offset;
61a65099
KB		 3225
3226 /* If != 0, fdata.lr_offset is the offset from the frame that
3227 holds the LR. */
3228 if (fdata.lr_offset != 0)
0df8b418
MS		 3229 cache->saved_regs[tdep->ppc_lr_regnum].addr
3230 = cache->base + fdata.lr_offset;
46a9b8ed
DJ		 3231 else if (fdata.lr_register != -1)
3232 cache->saved_regs[tdep->ppc_lr_regnum].realreg = fdata.lr_register;
61a65099 3233 /* The PC is found in the link register. */
8b164abb 3234 cache->saved_regs[gdbarch_pc_regnum (gdbarch)] =
3e8c568d 3235 cache->saved_regs[tdep->ppc_lr_regnum];
61a65099
KB		 3236
3237 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3238 holds the VRSAVE. */
3239 if (fdata.vrsave_offset != 0)
0df8b418
MS		 3240 cache->saved_regs[tdep->ppc_vrsave_regnum].addr
3241 = cache->base + fdata.vrsave_offset;
61a65099
KB		 3242
3243 if (fdata.alloca_reg < 0)
3244 /* If no alloca register used, then fi->frame is the value of the
3245 %sp for this frame, and it is good enough. */
1af5d7ce
UW		 3246 cache->initial_sp
3247 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
61a65099 3248 else
1af5d7ce
UW		 3249 cache->initial_sp
3250 = get_frame_register_unsigned (this_frame, fdata.alloca_reg);
61a65099
KB		 3251
3252 return cache;
3253}
3254
3255static void
1af5d7ce 3256rs6000_frame_this_id (struct frame_info *this_frame, void **this_cache,
61a65099
KB		 3257 struct frame_id *this_id)
3258{
1af5d7ce 3259 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099 3260 this_cache);
5b197912
UW		 3261 /* This marks the outermost frame. */
3262 if (info->base == 0)
3263 return;
3264
1af5d7ce 3265 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
61a65099
KB		 3266}
3267
1af5d7ce
UW		 3268static struct value *
3269rs6000_frame_prev_register (struct frame_info *this_frame,
3270 void **this_cache, int regnum)
61a65099 3271{
1af5d7ce 3272 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099 3273 this_cache);
1af5d7ce 3274 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
61a65099
KB		 3275}
3276
3277static const struct frame_unwind rs6000_frame_unwind =
3278{
3279 NORMAL_FRAME,
3280 rs6000_frame_this_id,
1af5d7ce
UW		 3281 rs6000_frame_prev_register,
3282 NULL,
3283 default_frame_sniffer
61a65099 3284};
61a65099
KB		 3285\f
3286
3287static CORE_ADDR
1af5d7ce 3288rs6000_frame_base_address (struct frame_info *this_frame, void **this_cache)
61a65099 3289{
1af5d7ce 3290 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099
KB		 3291 this_cache);
3292 return info->initial_sp;
3293}
3294
3295static const struct frame_base rs6000_frame_base = {
3296 &rs6000_frame_unwind,
3297 rs6000_frame_base_address,
3298 rs6000_frame_base_address,
3299 rs6000_frame_base_address
3300};
3301
3302static const struct frame_base *
1af5d7ce 3303rs6000_frame_base_sniffer (struct frame_info *this_frame)
61a65099
KB		 3304{
3305 return &rs6000_frame_base;
3306}
3307
9274a07c
LM		 3308/* DWARF-2 frame support. Used to handle the detection of
3309 clobbered registers during function calls. */
3310
3311static void
3312ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3313 struct dwarf2_frame_state_reg *reg,
4a4e5149 3314 struct frame_info *this_frame)
9274a07c
LM		 3315{
3316 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3317
3318 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3319 non-volatile registers. We will use the same code for both. */
3320
3321 /* Call-saved GP registers. */
3322 if ((regnum >= tdep->ppc_gp0_regnum + 14
3323 && regnum <= tdep->ppc_gp0_regnum + 31)
3324 || (regnum == tdep->ppc_gp0_regnum + 1))
3325 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3326
3327 /* Call-clobbered GP registers. */
3328 if ((regnum >= tdep->ppc_gp0_regnum + 3
3329 && regnum <= tdep->ppc_gp0_regnum + 12)
3330 || (regnum == tdep->ppc_gp0_regnum))
3331 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3332
3333 /* Deal with FP registers, if supported. */
3334 if (tdep->ppc_fp0_regnum >= 0)
3335 {
3336 /* Call-saved FP registers. */
3337 if ((regnum >= tdep->ppc_fp0_regnum + 14
3338 && regnum <= tdep->ppc_fp0_regnum + 31))
3339 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3340
3341 /* Call-clobbered FP registers. */
3342 if ((regnum >= tdep->ppc_fp0_regnum
3343 && regnum <= tdep->ppc_fp0_regnum + 13))
3344 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3345 }
3346
3347 /* Deal with ALTIVEC registers, if supported. */
3348 if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0)
3349 {
3350 /* Call-saved Altivec registers. */
3351 if ((regnum >= tdep->ppc_vr0_regnum + 20
3352 && regnum <= tdep->ppc_vr0_regnum + 31)
3353 || regnum == tdep->ppc_vrsave_regnum)
3354 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3355
3356 /* Call-clobbered Altivec registers. */
3357 if ((regnum >= tdep->ppc_vr0_regnum
3358 && regnum <= tdep->ppc_vr0_regnum + 19))
3359 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3360 }
3361
3362 /* Handle PC register and Stack Pointer correctly. */
40a6adc1 3363 if (regnum == gdbarch_pc_regnum (gdbarch))
9274a07c 3364 reg->how = DWARF2_FRAME_REG_RA;
40a6adc1 3365 else if (regnum == gdbarch_sp_regnum (gdbarch))
9274a07c
LM		 3366 reg->how = DWARF2_FRAME_REG_CFA;
3367}
3368
3369
74af9197
NF		 3370/* Return true if a .gnu_attributes section exists in BFD and it
3371 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3372 section exists in BFD and it indicates that SPE extensions are in
3373 use. Check the .gnu.attributes section first, as the binary might be
3374 compiled for SPE, but not actually using SPE instructions. */
3375
3376static int
3377bfd_uses_spe_extensions (bfd *abfd)
3378{
3379 asection *sect;
3380 gdb_byte *contents = NULL;
3381 bfd_size_type size;
3382 gdb_byte *ptr;
3383 int success = 0;
3384 int vector_abi;
3385
3386 if (!abfd)
3387 return 0;
3388
50a99728 3389#ifdef HAVE_ELF
74af9197
NF		 3390 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3391 could be using the SPE vector abi without actually using any spe
3392 bits whatsoever. But it's close enough for now. */
3393 vector_abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_GNU,
3394 Tag_GNU_Power_ABI_Vector);
3395 if (vector_abi == 3)
3396 return 1;
50a99728 3397#endif
74af9197
NF		 3398
3399 sect = bfd_get_section_by_name (abfd, ".PPC.EMB.apuinfo");
3400 if (!sect)
3401 return 0;
3402
3403 size = bfd_get_section_size (sect);
3404 contents = xmalloc (size);
3405 if (!bfd_get_section_contents (abfd, sect, contents, 0, size))
3406 {
3407 xfree (contents);
3408 return 0;
3409 }
3410
3411 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3412
3413 struct {
3414 uint32 name_len;
3415 uint32 data_len;
3416 uint32 type;
3417 char name[name_len rounded up to 4-byte alignment];
3418 char data[data_len];
3419 };
3420
3421 Technically, there's only supposed to be one such structure in a
3422 given apuinfo section, but the linker is not always vigilant about
3423 merging apuinfo sections from input files. Just go ahead and parse
3424 them all, exiting early when we discover the binary uses SPE
3425 insns.
3426
3427 It's not specified in what endianness the information in this
3428 section is stored. Assume that it's the endianness of the BFD. */
3429 ptr = contents;
3430 while (1)
3431 {
3432 unsigned int name_len;
3433 unsigned int data_len;
3434 unsigned int type;
3435
3436 /* If we can't read the first three fields, we're done. */
3437 if (size < 12)
3438 break;
3439
3440 name_len = bfd_get_32 (abfd, ptr);
3441 name_len = (name_len + 3) & ~3U; /* Round to 4 bytes. */
3442 data_len = bfd_get_32 (abfd, ptr + 4);
3443 type = bfd_get_32 (abfd, ptr + 8);
3444 ptr += 12;
3445
3446 /* The name must be "APUinfo\0". */
3447 if (name_len != 8
3448 && strcmp ((const char *) ptr, "APUinfo") != 0)
3449 break;
3450 ptr += name_len;
3451
3452 /* The type must be 2. */
3453 if (type != 2)
3454 break;
3455
3456 /* The data is stored as a series of uint32. The upper half of
3457 each uint32 indicates the particular APU used and the lower
3458 half indicates the revision of that APU. We just care about
3459 the upper half. */
3460
3461 /* Not 4-byte quantities. */
3462 if (data_len & 3U)
3463 break;
3464
3465 while (data_len)
3466 {
3467 unsigned int apuinfo = bfd_get_32 (abfd, ptr);
3468 unsigned int apu = apuinfo >> 16;
3469 ptr += 4;
3470 data_len -= 4;
3471
3472 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3473 either. */
3474 if (apu == 0x100 || apu == 0x101)
3475 {
3476 success = 1;
3477 data_len = 0;
3478 }
3479 }
3480
3481 if (success)
3482 break;
3483 }
3484
3485 xfree (contents);
3486 return success;
3487}
3488
7a78ae4e
ND		 3489/* Initialize the current architecture based on INFO. If possible, re-use an
3490 architecture from ARCHES, which is a list of architectures already created
3491 during this debugging session.
c906108c 3492
7a78ae4e 3493 Called e.g. at program startup, when reading a core file, and when reading
64366f1c 3494 a binary file. */
c906108c 3495
7a78ae4e
ND		 3496static struct gdbarch *
3497rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3498{
3499 struct gdbarch *gdbarch;
3500 struct gdbarch_tdep *tdep;
7cc46491 3501 int wordsize, from_xcoff_exec, from_elf_exec;
7a78ae4e
ND		 3502 enum bfd_architecture arch;
3503 unsigned long mach;
3504 bfd abfd;
5bf1c677 3505 asection *sect;
55eddb0f
DJ		 3506 enum auto_boolean soft_float_flag = powerpc_soft_float_global;
3507 int soft_float;
3508 enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
604c2f83
LM		 3509 int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0,
3510 have_vsx = 0;
7cc46491
DJ		 3511 int tdesc_wordsize = -1;
3512 const struct target_desc *tdesc = info.target_desc;
3513 struct tdesc_arch_data *tdesc_data = NULL;
f949c649 3514 int num_pseudoregs = 0;
604c2f83 3515 int cur_reg;
7a78ae4e 3516
f4d9bade
UW		 3517 /* INFO may refer to a binary that is not of the PowerPC architecture,
3518 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
3519 In this case, we must not attempt to infer properties of the (PowerPC
3520 side) of the target system from properties of that executable. Trust
3521 the target description instead. */
3522 if (info.abfd
3523 && bfd_get_arch (info.abfd) != bfd_arch_powerpc
3524 && bfd_get_arch (info.abfd) != bfd_arch_rs6000)
3525 info.abfd = NULL;
3526
9aa1e687 3527 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
7a78ae4e
ND		 3528 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3529
9aa1e687
KB		 3530 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3531 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3532
e712c1cf 3533 /* Check word size. If INFO is from a binary file, infer it from
64366f1c 3534 that, else choose a likely default. */
9aa1e687 3535 if (from_xcoff_exec)
c906108c 3536 {
11ed25ac 3537 if (bfd_xcoff_is_xcoff64 (info.abfd))
7a78ae4e
ND		 3538 wordsize = 8;
3539 else
3540 wordsize = 4;
c906108c 3541 }
9aa1e687
KB		 3542 else if (from_elf_exec)
3543 {
3544 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3545 wordsize = 8;
3546 else
3547 wordsize = 4;
3548 }
7cc46491
DJ		 3549 else if (tdesc_has_registers (tdesc))
3550 wordsize = -1;
c906108c 3551 else
7a78ae4e 3552 {
27b15785
KB		 3553 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3554 wordsize = info.bfd_arch_info->bits_per_word /
3555 info.bfd_arch_info->bits_per_byte;
3556 else
3557 wordsize = 4;
7a78ae4e 3558 }
c906108c 3559
475bbd17
JB		 3560 /* Get the architecture and machine from the BFD. */
3561 arch = info.bfd_arch_info->arch;
3562 mach = info.bfd_arch_info->mach;
5bf1c677
EZ		 3563
3564 /* For e500 executables, the apuinfo section is of help here. Such
3565 section contains the identifier and revision number of each
3566 Application-specific Processing Unit that is present on the
3567 chip. The content of the section is determined by the assembler
3568 which looks at each instruction and determines which unit (and
74af9197
NF		 3569 which version of it) can execute it. Grovel through the section
3570 looking for relevant e500 APUs. */
5bf1c677 3571
74af9197 3572 if (bfd_uses_spe_extensions (info.abfd))
5bf1c677 3573 {
74af9197
NF		 3574 arch = info.bfd_arch_info->arch;
3575 mach = bfd_mach_ppc_e500;
3576 bfd_default_set_arch_mach (&abfd, arch, mach);
3577 info.bfd_arch_info = bfd_get_arch_info (&abfd);
5bf1c677
EZ		 3578 }
3579
7cc46491
DJ		 3580 /* Find a default target description which describes our register
3581 layout, if we do not already have one. */
3582 if (! tdesc_has_registers (tdesc))
3583 {
3584 const struct variant *v;
3585
3586 /* Choose variant. */
3587 v = find_variant_by_arch (arch, mach);
3588 if (!v)
3589 return NULL;
3590
3591 tdesc = *v->tdesc;
3592 }
3593
3594 gdb_assert (tdesc_has_registers (tdesc));
3595
3596 /* Check any target description for validity. */
3597 if (tdesc_has_registers (tdesc))
3598 {
3599 static const char *const gprs[] = {
3600 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3601 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3602 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3603 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3604 };
3605 static const char *const segment_regs[] = {
3606 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
3607 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
3608 };
3609 const struct tdesc_feature *feature;
3610 int i, valid_p;
3611 static const char *const msr_names[] = { "msr", "ps" };
3612 static const char *const cr_names[] = { "cr", "cnd" };
3613 static const char *const ctr_names[] = { "ctr", "cnt" };
3614
3615 feature = tdesc_find_feature (tdesc,
3616 "org.gnu.gdb.power.core");
3617 if (feature == NULL)
3618 return NULL;
3619
3620 tdesc_data = tdesc_data_alloc ();
3621
3622 valid_p = 1;
3623 for (i = 0; i < ppc_num_gprs; i++)
3624 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]);
3625 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM,
3626 "pc");
3627 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM,
3628 "lr");
3629 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM,
3630 "xer");
3631
3632 /* Allow alternate names for these registers, to accomodate GDB's
3633 historic naming. */
3634 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3635 PPC_MSR_REGNUM, msr_names);
3636 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3637 PPC_CR_REGNUM, cr_names);
3638 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3639 PPC_CTR_REGNUM, ctr_names);
3640
3641 if (!valid_p)
3642 {
3643 tdesc_data_cleanup (tdesc_data);
3644 return NULL;
3645 }
3646
3647 have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM,
3648 "mq");
3649
3650 tdesc_wordsize = tdesc_register_size (feature, "pc") / 8;
3651 if (wordsize == -1)
3652 wordsize = tdesc_wordsize;
3653
3654 feature = tdesc_find_feature (tdesc,
3655 "org.gnu.gdb.power.fpu");
3656 if (feature != NULL)
3657 {
3658 static const char *const fprs[] = {
3659 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
3660 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
3661 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
3662 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
3663 };
3664 valid_p = 1;
3665 for (i = 0; i < ppc_num_fprs; i++)
3666 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3667 PPC_F0_REGNUM + i, fprs[i]);
3668 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3669 PPC_FPSCR_REGNUM, "fpscr");
3670
3671 if (!valid_p)
3672 {
3673 tdesc_data_cleanup (tdesc_data);
3674 return NULL;
3675 }
3676 have_fpu = 1;
3677 }
3678 else
3679 have_fpu = 0;
3680
f949c649
TJB		 3681 /* The DFP pseudo-registers will be available when there are floating
3682 point registers. */
3683 have_dfp = have_fpu;
3684
7cc46491
DJ		 3685 feature = tdesc_find_feature (tdesc,
3686 "org.gnu.gdb.power.altivec");
3687 if (feature != NULL)
3688 {
3689 static const char *const vector_regs[] = {
3690 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
3691 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
3692 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
3693 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
3694 };
3695
3696 valid_p = 1;
3697 for (i = 0; i < ppc_num_gprs; i++)
3698 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3699 PPC_VR0_REGNUM + i,
3700 vector_regs[i]);
3701 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3702 PPC_VSCR_REGNUM, "vscr");
3703 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3704 PPC_VRSAVE_REGNUM, "vrsave");
3705
3706 if (have_spe || !valid_p)
3707 {
3708 tdesc_data_cleanup (tdesc_data);
3709 return NULL;
3710 }
3711 have_altivec = 1;
3712 }
3713 else
3714 have_altivec = 0;
3715
604c2f83
LM		 3716 /* Check for POWER7 VSX registers support. */
3717 feature = tdesc_find_feature (tdesc,
3718 "org.gnu.gdb.power.vsx");
3719
3720 if (feature != NULL)
3721 {
3722 static const char *const vsx_regs[] = {
3723 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
3724 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
3725 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
3726 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
3727 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
3728 "vs30h", "vs31h"
3729 };
3730
3731 valid_p = 1;
3732
3733 for (i = 0; i < ppc_num_vshrs; i++)
3734 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3735 PPC_VSR0_UPPER_REGNUM + i,
3736 vsx_regs[i]);
3737 if (!valid_p)
3738 {
3739 tdesc_data_cleanup (tdesc_data);
3740 return NULL;
3741 }
3742
3743 have_vsx = 1;
3744 }
3745 else
3746 have_vsx = 0;
3747
7cc46491
DJ		 3748 /* On machines supporting the SPE APU, the general-purpose registers
3749 are 64 bits long. There are SIMD vector instructions to treat them
3750 as pairs of floats, but the rest of the instruction set treats them
3751 as 32-bit registers, and only operates on their lower halves.
3752
3753 In the GDB regcache, we treat their high and low halves as separate
3754 registers. The low halves we present as the general-purpose
3755 registers, and then we have pseudo-registers that stitch together
3756 the upper and lower halves and present them as pseudo-registers.
3757
3758 Thus, the target description is expected to supply the upper
3759 halves separately. */
3760
3761 feature = tdesc_find_feature (tdesc,
3762 "org.gnu.gdb.power.spe");
3763 if (feature != NULL)
3764 {
3765 static const char *const upper_spe[] = {
3766 "ev0h", "ev1h", "ev2h", "ev3h",
3767 "ev4h", "ev5h", "ev6h", "ev7h",
3768 "ev8h", "ev9h", "ev10h", "ev11h",
3769 "ev12h", "ev13h", "ev14h", "ev15h",
3770 "ev16h", "ev17h", "ev18h", "ev19h",
3771 "ev20h", "ev21h", "ev22h", "ev23h",
3772 "ev24h", "ev25h", "ev26h", "ev27h",
3773 "ev28h", "ev29h", "ev30h", "ev31h"
3774 };
3775
3776 valid_p = 1;
3777 for (i = 0; i < ppc_num_gprs; i++)
3778 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3779 PPC_SPE_UPPER_GP0_REGNUM + i,
3780 upper_spe[i]);
3781 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3782 PPC_SPE_ACC_REGNUM, "acc");
3783 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3784 PPC_SPE_FSCR_REGNUM, "spefscr");
3785
3786 if (have_mq || have_fpu || !valid_p)
3787 {
3788 tdesc_data_cleanup (tdesc_data);
3789 return NULL;
3790 }
3791 have_spe = 1;
3792 }
3793 else
3794 have_spe = 0;
3795 }
3796
3797 /* If we have a 64-bit binary on a 32-bit target, complain. Also
3798 complain for a 32-bit binary on a 64-bit target; we do not yet
3799 support that. For instance, the 32-bit ABI routines expect
3800 32-bit GPRs.
3801
3802 As long as there isn't an explicit target description, we'll
3803 choose one based on the BFD architecture and get a word size
3804 matching the binary (probably powerpc:common or
3805 powerpc:common64). So there is only trouble if a 64-bit target
3806 supplies a 64-bit description while debugging a 32-bit
3807 binary. */
3808 if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize)
3809 {
3810 tdesc_data_cleanup (tdesc_data);
3811 return NULL;
3812 }
3813
55eddb0f
DJ		 3814#ifdef HAVE_ELF
3815 if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec)
3816 {
3817 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3818 Tag_GNU_Power_ABI_FP))
3819 {
3820 case 1:
3821 soft_float_flag = AUTO_BOOLEAN_FALSE;
3822 break;
3823 case 2:
3824 soft_float_flag = AUTO_BOOLEAN_TRUE;
3825 break;
3826 default:
3827 break;
3828 }
3829 }
3830
3831 if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec)
3832 {
3833 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3834 Tag_GNU_Power_ABI_Vector))
3835 {
3836 case 1:
3837 vector_abi = POWERPC_VEC_GENERIC;
3838 break;
3839 case 2:
3840 vector_abi = POWERPC_VEC_ALTIVEC;
3841 break;
3842 case 3:
3843 vector_abi = POWERPC_VEC_SPE;
3844 break;
3845 default:
3846 break;
3847 }
3848 }
3849#endif
3850
3851 if (soft_float_flag == AUTO_BOOLEAN_TRUE)
3852 soft_float = 1;
3853 else if (soft_float_flag == AUTO_BOOLEAN_FALSE)
3854 soft_float = 0;
3855 else
3856 soft_float = !have_fpu;
3857
3858 /* If we have a hard float binary or setting but no floating point
3859 registers, downgrade to soft float anyway. We're still somewhat
3860 useful in this scenario. */
3861 if (!soft_float && !have_fpu)
3862 soft_float = 1;
3863
3864 /* Similarly for vector registers. */
3865 if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec)
3866 vector_abi = POWERPC_VEC_GENERIC;
3867
3868 if (vector_abi == POWERPC_VEC_SPE && !have_spe)
3869 vector_abi = POWERPC_VEC_GENERIC;
3870
3871 if (vector_abi == POWERPC_VEC_AUTO)
3872 {
3873 if (have_altivec)
3874 vector_abi = POWERPC_VEC_ALTIVEC;
3875 else if (have_spe)
3876 vector_abi = POWERPC_VEC_SPE;
3877 else
3878 vector_abi = POWERPC_VEC_GENERIC;
3879 }
3880
3881 /* Do not limit the vector ABI based on available hardware, since we
3882 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
3883
7cc46491
DJ		 3884 /* Find a candidate among extant architectures. */
3885 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3886 arches != NULL;
3887 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3888 {
3889 /* Word size in the various PowerPC bfd_arch_info structs isn't
3890 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3891 separate word size check. */
3892 tdep = gdbarch_tdep (arches->gdbarch);
55eddb0f
DJ		 3893 if (tdep && tdep->soft_float != soft_float)
3894 continue;
3895 if (tdep && tdep->vector_abi != vector_abi)
3896 continue;
7cc46491
DJ		 3897 if (tdep && tdep->wordsize == wordsize)
3898 {
3899 if (tdesc_data != NULL)
3900 tdesc_data_cleanup (tdesc_data);
3901 return arches->gdbarch;
3902 }
3903 }
3904
3905 /* None found, create a new architecture from INFO, whose bfd_arch_info
3906 validity depends on the source:
3907 - executable useless
3908 - rs6000_host_arch() good
3909 - core file good
3910 - "set arch" trust blindly
3911 - GDB startup useless but harmless */
3912
3913 tdep = XCALLOC (1, struct gdbarch_tdep);
3914 tdep->wordsize = wordsize;
55eddb0f
DJ		 3915 tdep->soft_float = soft_float;
3916 tdep->vector_abi = vector_abi;
7cc46491 3917
7a78ae4e 3918 gdbarch = gdbarch_alloc (&info, tdep);
7a78ae4e 3919
7cc46491
DJ		 3920 tdep->ppc_gp0_regnum = PPC_R0_REGNUM;
3921 tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2;
3922 tdep->ppc_ps_regnum = PPC_MSR_REGNUM;
3923 tdep->ppc_cr_regnum = PPC_CR_REGNUM;
3924 tdep->ppc_lr_regnum = PPC_LR_REGNUM;
3925 tdep->ppc_ctr_regnum = PPC_CTR_REGNUM;
3926 tdep->ppc_xer_regnum = PPC_XER_REGNUM;
3927 tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1;
3928
3929 tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1;
3930 tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1;
604c2f83 3931 tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1;
7cc46491
DJ		 3932 tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1;
3933 tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1;
3934 tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1;
3935 tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1;
3936 tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
3937
3938 set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
3939 set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3940 set_gdbarch_deprecated_fp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3941 set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum);
9f643768 3942 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
7cc46491
DJ		 3943
3944 /* The XML specification for PowerPC sensibly calls the MSR "msr".
3945 GDB traditionally called it "ps", though, so let GDB add an
3946 alias. */
3947 set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum);
3948
4a7622d1 3949 if (wordsize == 8)
05580c65 3950 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
afd48b75 3951 else
4a7622d1 3952 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
c8001721 3953
baffbae0
JB		 3954 /* Set lr_frame_offset. */
3955 if (wordsize == 8)
3956 tdep->lr_frame_offset = 16;
baffbae0 3957 else
4a7622d1 3958 tdep->lr_frame_offset = 4;
baffbae0 3959
604c2f83 3960 if (have_spe || have_dfp || have_vsx)
7cc46491 3961 {
f949c649 3962 set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read);
0df8b418
MS		 3963 set_gdbarch_pseudo_register_write (gdbarch,
3964 rs6000_pseudo_register_write);
7cc46491 3965 }
1fcc0bb8 3966
e0d24f8d
WZ		 3967 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3968
56a6dfb9 3969 /* Select instruction printer. */
708ff411 3970 if (arch == bfd_arch_rs6000)
9364a0ef 3971 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
56a6dfb9 3972 else
9364a0ef 3973 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
7495d1dc 3974
5a9e69ba 3975 set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS);
f949c649
TJB		 3976
3977 if (have_spe)
3978 num_pseudoregs += 32;
3979 if (have_dfp)
3980 num_pseudoregs += 16;
604c2f83
LM		 3981 if (have_vsx)
3982 /* Include both VSX and Extended FP registers. */
3983 num_pseudoregs += 96;
f949c649
TJB		 3984
3985 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs);
7a78ae4e
ND		 3986
3987 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3988 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3989 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3990 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3991 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3992 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3993 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4a7622d1 3994 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
4e409299 3995 set_gdbarch_char_signed (gdbarch, 0);
7a78ae4e 3996
11269d7e 3997 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
4a7622d1 3998 if (wordsize == 8)
8b148df9
AC		 3999 /* PPC64 SYSV. */
4000 set_gdbarch_frame_red_zone_size (gdbarch, 288);
7a78ae4e 4001
691d145a
JB		 4002 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
4003 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
4004 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
4005
18ed0c4e
JB		 4006 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
4007 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
d217aaed 4008
4a7622d1 4009 if (wordsize == 4)
77b2b6d4 4010 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
4a7622d1 4011 else if (wordsize == 8)
8be9034a 4012 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
7a78ae4e 4013
7a78ae4e 4014 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
0d1243d9 4015 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
8ab3d180 4016 set_gdbarch_skip_main_prologue (gdbarch, rs6000_skip_main_prologue);
0d1243d9 4017
7a78ae4e 4018 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
7a78ae4e
ND		 4019 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
4020
203c3895 4021 /* The value of symbols of type N_SO and N_FUN maybe null when
0df8b418 4022 it shouldn't be. */
203c3895
UW		 4023 set_gdbarch_sofun_address_maybe_missing (gdbarch, 1);
4024
ce5eab59 4025 /* Handles single stepping of atomic sequences. */
4a7622d1 4026 set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence);
ce5eab59 4027
0df8b418 4028 /* Not sure on this. FIXMEmgo */
7a78ae4e
ND		 4029 set_gdbarch_frame_args_skip (gdbarch, 8);
4030
143985b7
AF		 4031 /* Helpers for function argument information. */
4032 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
4033
6f7f3f0d
UW		 4034 /* Trampoline. */
4035 set_gdbarch_in_solib_return_trampoline
4036 (gdbarch, rs6000_in_solib_return_trampoline);
4037 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code);
4038
4fc771b8 4039 /* Hook in the DWARF CFI frame unwinder. */
1af5d7ce 4040 dwarf2_append_unwinders (gdbarch);
4fc771b8
DJ		 4041 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum);
4042
9274a07c
LM		 4043 /* Frame handling. */
4044 dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg);
4045
2454a024
UW		 4046 /* Setup displaced stepping. */
4047 set_gdbarch_displaced_step_copy_insn (gdbarch,
4048 simple_displaced_step_copy_insn);
99e40580
UW		 4049 set_gdbarch_displaced_step_hw_singlestep (gdbarch,
4050 ppc_displaced_step_hw_singlestep);
2454a024
UW		 4051 set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup);
4052 set_gdbarch_displaced_step_free_closure (gdbarch,
4053 simple_displaced_step_free_closure);
4054 set_gdbarch_displaced_step_location (gdbarch,
4055 displaced_step_at_entry_point);
4056
4057 set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE);
4058
7b112f9c 4059 /* Hook in ABI-specific overrides, if they have been registered. */
8a4c2d24
UW		 4060 info.target_desc = tdesc;
4061 info.tdep_info = (void *) tdesc_data;
4be87837 4062 gdbarch_init_osabi (info, gdbarch);
7b112f9c 4063
61a65099
KB		 4064 switch (info.osabi)
4065 {
f5aecab8 4066 case GDB_OSABI_LINUX:
61a65099
KB		 4067 case GDB_OSABI_NETBSD_AOUT:
4068 case GDB_OSABI_NETBSD_ELF:
4069 case GDB_OSABI_UNKNOWN:
61a65099 4070 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
1af5d7ce
UW		 4071 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
4072 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
61a65099
KB		 4073 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
4074 break;
4075 default:
61a65099 4076 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
81332287
KB		 4077
4078 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
1af5d7ce
UW		 4079 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
4080 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
81332287 4081 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
61a65099
KB		 4082 }
4083
7cc46491
DJ		 4084 set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type);
4085 set_tdesc_pseudo_register_reggroup_p (gdbarch,
4086 rs6000_pseudo_register_reggroup_p);
4087 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
4088
4089 /* Override the normal target description method to make the SPE upper
4090 halves anonymous. */
4091 set_gdbarch_register_name (gdbarch, rs6000_register_name);
4092
604c2f83
LM		 4093 /* Choose register numbers for all supported pseudo-registers. */
4094 tdep->ppc_ev0_regnum = -1;
4095 tdep->ppc_dl0_regnum = -1;
4096 tdep->ppc_vsr0_regnum = -1;
4097 tdep->ppc_efpr0_regnum = -1;
9f643768 4098
604c2f83
LM		 4099 cur_reg = gdbarch_num_regs (gdbarch);
4100
4101 if (have_spe)
4102 {
4103 tdep->ppc_ev0_regnum = cur_reg;
4104 cur_reg += 32;
4105 }
4106 if (have_dfp)
4107 {
4108 tdep->ppc_dl0_regnum = cur_reg;
4109 cur_reg += 16;
4110 }
4111 if (have_vsx)
4112 {
4113 tdep->ppc_vsr0_regnum = cur_reg;
4114 cur_reg += 64;
4115 tdep->ppc_efpr0_regnum = cur_reg;
4116 cur_reg += 32;
4117 }
f949c649 4118
604c2f83
LM		 4119 gdb_assert (gdbarch_num_regs (gdbarch)
4120 + gdbarch_num_pseudo_regs (gdbarch) == cur_reg);
f949c649 4121
7a78ae4e 4122 return gdbarch;
c906108c
SS		 4123}
4124
7b112f9c 4125static void
8b164abb 4126rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
7b112f9c 4127{
8b164abb 4128 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7b112f9c
JT		 4129
4130 if (tdep == NULL)
4131 return;
4132
4be87837 4133 /* FIXME: Dump gdbarch_tdep. */
7b112f9c
JT		 4134}
4135
55eddb0f
DJ		 4136/* PowerPC-specific commands. */
4137
4138static void
4139set_powerpc_command (char *args, int from_tty)
4140{
4141 printf_unfiltered (_("\
4142\"set powerpc\" must be followed by an appropriate subcommand.\n"));
4143 help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout);
4144}
4145
4146static void
4147show_powerpc_command (char *args, int from_tty)
4148{
4149 cmd_show_list (showpowerpccmdlist, from_tty, "");
4150}
4151
4152static void
4153powerpc_set_soft_float (char *args, int from_tty,
4154 struct cmd_list_element *c)
4155{
4156 struct gdbarch_info info;
4157
4158 /* Update the architecture. */
4159 gdbarch_info_init (&info);
4160 if (!gdbarch_update_p (info))
9b20d036 4161 internal_error (__FILE__, __LINE__, _("could not update architecture"));
55eddb0f
DJ		 4162}
4163
4164static void
4165powerpc_set_vector_abi (char *args, int from_tty,
4166 struct cmd_list_element *c)
4167{
4168 struct gdbarch_info info;
4169 enum powerpc_vector_abi vector_abi;
4170
4171 for (vector_abi = POWERPC_VEC_AUTO;
4172 vector_abi != POWERPC_VEC_LAST;
4173 vector_abi++)
4174 if (strcmp (powerpc_vector_abi_string,
4175 powerpc_vector_strings[vector_abi]) == 0)
4176 {
4177 powerpc_vector_abi_global = vector_abi;
4178 break;
4179 }
4180
4181 if (vector_abi == POWERPC_VEC_LAST)
4182 internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."),
4183 powerpc_vector_abi_string);
4184
4185 /* Update the architecture. */
4186 gdbarch_info_init (&info);
4187 if (!gdbarch_update_p (info))
9b20d036 4188 internal_error (__FILE__, __LINE__, _("could not update architecture"));
55eddb0f
DJ		 4189}
4190
e09342b5
TJB		 4191/* Show the current setting of the exact watchpoints flag. */
4192
4193static void
4194show_powerpc_exact_watchpoints (struct ui_file *file, int from_tty,
4195 struct cmd_list_element *c,
4196 const char *value)
4197{
4198 fprintf_filtered (file, _("Use of exact watchpoints is %s.\n"), value);
4199}
4200
c906108c
SS		 4201/* Initialization code. */
4202
0df8b418
MS		 4203/* -Wmissing-prototypes */
4204extern initialize_file_ftype _initialize_rs6000_tdep;
b9362cc7 4205
c906108c 4206void
fba45db2 4207_initialize_rs6000_tdep (void)
c906108c 4208{
7b112f9c
JT		 4209 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
4210 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
7cc46491
DJ		 4211
4212 /* Initialize the standard target descriptions. */
4213 initialize_tdesc_powerpc_32 ();
7284e1be 4214 initialize_tdesc_powerpc_altivec32 ();
604c2f83 4215 initialize_tdesc_powerpc_vsx32 ();
7cc46491
DJ		 4216 initialize_tdesc_powerpc_403 ();
4217 initialize_tdesc_powerpc_403gc ();
4d09ffea 4218 initialize_tdesc_powerpc_405 ();
7cc46491
DJ		 4219 initialize_tdesc_powerpc_505 ();
4220 initialize_tdesc_powerpc_601 ();
4221 initialize_tdesc_powerpc_602 ();
4222 initialize_tdesc_powerpc_603 ();
4223 initialize_tdesc_powerpc_604 ();
4224 initialize_tdesc_powerpc_64 ();
7284e1be 4225 initialize_tdesc_powerpc_altivec64 ();
604c2f83 4226 initialize_tdesc_powerpc_vsx64 ();
7cc46491
DJ		 4227 initialize_tdesc_powerpc_7400 ();
4228 initialize_tdesc_powerpc_750 ();
4229 initialize_tdesc_powerpc_860 ();
4230 initialize_tdesc_powerpc_e500 ();
4231 initialize_tdesc_rs6000 ();
55eddb0f
DJ		 4232
4233 /* Add root prefix command for all "set powerpc"/"show powerpc"
4234 commands. */
4235 add_prefix_cmd ("powerpc", no_class, set_powerpc_command,
4236 _("Various PowerPC-specific commands."),
4237 &setpowerpccmdlist, "set powerpc ", 0, &setlist);
4238
4239 add_prefix_cmd ("powerpc", no_class, show_powerpc_command,
4240 _("Various PowerPC-specific commands."),
4241 &showpowerpccmdlist, "show powerpc ", 0, &showlist);
4242
4243 /* Add a command to allow the user to force the ABI. */
4244 add_setshow_auto_boolean_cmd ("soft-float", class_support,
4245 &powerpc_soft_float_global,
4246 _("Set whether to use a soft-float ABI."),
4247 _("Show whether to use a soft-float ABI."),
4248 NULL,
4249 powerpc_set_soft_float, NULL,
4250 &setpowerpccmdlist, &showpowerpccmdlist);
4251
4252 add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings,
4253 &powerpc_vector_abi_string,
4254 _("Set the vector ABI."),
4255 _("Show the vector ABI."),
4256 NULL, powerpc_set_vector_abi, NULL,
4257 &setpowerpccmdlist, &showpowerpccmdlist);
e09342b5
TJB		 4258
4259 add_setshow_boolean_cmd ("exact-watchpoints", class_support,
4260 &target_exact_watchpoints,
4261 _("\
4262Set whether to use just one debug register for watchpoints on scalars."),
4263 _("\
4264Show whether to use just one debug register for watchpoints on scalars."),
4265 _("\
4266If true, GDB will use only one debug register when watching a variable of\n\
4267scalar type, thus assuming that the variable is accessed through the address\n\
4268of its first byte."),
4269 NULL, show_powerpc_exact_watchpoints,
4270 &setpowerpccmdlist, &showpowerpccmdlist);
c906108c 4271}
GDB Binutils - Deliverables
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