Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for GDB, the GNU debugger. |
7aea86e6 | 2 | |
6aba47ca DJ |
3 | Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 | |
721d14ba | 5 | Free Software Foundation, Inc. |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b JM |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
21 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
22 | Boston, MA 02110-1301, USA. */ | |
c906108c SS |
23 | |
24 | #include "defs.h" | |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "symtab.h" | |
28 | #include "target.h" | |
29 | #include "gdbcore.h" | |
30 | #include "gdbcmd.h" | |
c906108c | 31 | #include "objfiles.h" |
7a78ae4e | 32 | #include "arch-utils.h" |
4e052eda | 33 | #include "regcache.h" |
d195bc9f | 34 | #include "regset.h" |
d16aafd8 | 35 | #include "doublest.h" |
fd0407d6 | 36 | #include "value.h" |
1fcc0bb8 | 37 | #include "parser-defs.h" |
4be87837 | 38 | #include "osabi.h" |
7d9b040b | 39 | #include "infcall.h" |
9f643768 JB |
40 | #include "sim-regno.h" |
41 | #include "gdb/sim-ppc.h" | |
6ced10dd | 42 | #include "reggroups.h" |
4fc771b8 | 43 | #include "dwarf2-frame.h" |
7a78ae4e | 44 | |
2fccf04a | 45 | #include "libbfd.h" /* for bfd_default_set_arch_mach */ |
7a78ae4e | 46 | #include "coff/internal.h" /* for libcoff.h */ |
2fccf04a | 47 | #include "libcoff.h" /* for xcoff_data */ |
11ed25ac KB |
48 | #include "coff/xcoff.h" |
49 | #include "libxcoff.h" | |
7a78ae4e | 50 | |
9aa1e687 | 51 | #include "elf-bfd.h" |
7a78ae4e | 52 | |
6ded7999 | 53 | #include "solib-svr4.h" |
9aa1e687 | 54 | #include "ppc-tdep.h" |
7a78ae4e | 55 | |
338ef23d | 56 | #include "gdb_assert.h" |
a89aa300 | 57 | #include "dis-asm.h" |
338ef23d | 58 | |
61a65099 KB |
59 | #include "trad-frame.h" |
60 | #include "frame-unwind.h" | |
61 | #include "frame-base.h" | |
62 | ||
1f82754b | 63 | #include "rs6000-tdep.h" |
c44ca51c | 64 | |
7a78ae4e ND |
65 | /* If the kernel has to deliver a signal, it pushes a sigcontext |
66 | structure on the stack and then calls the signal handler, passing | |
67 | the address of the sigcontext in an argument register. Usually | |
68 | the signal handler doesn't save this register, so we have to | |
69 | access the sigcontext structure via an offset from the signal handler | |
70 | frame. | |
71 | The following constants were determined by experimentation on AIX 3.2. */ | |
72 | #define SIG_FRAME_PC_OFFSET 96 | |
73 | #define SIG_FRAME_LR_OFFSET 108 | |
74 | #define SIG_FRAME_FP_OFFSET 284 | |
75 | ||
7a78ae4e ND |
76 | /* To be used by skip_prologue. */ |
77 | ||
78 | struct rs6000_framedata | |
79 | { | |
80 | int offset; /* total size of frame --- the distance | |
81 | by which we decrement sp to allocate | |
82 | the frame */ | |
83 | int saved_gpr; /* smallest # of saved gpr */ | |
84 | int saved_fpr; /* smallest # of saved fpr */ | |
6be8bc0c | 85 | int saved_vr; /* smallest # of saved vr */ |
96ff0de4 | 86 | int saved_ev; /* smallest # of saved ev */ |
7a78ae4e ND |
87 | int alloca_reg; /* alloca register number (frame ptr) */ |
88 | char frameless; /* true if frameless functions. */ | |
89 | char nosavedpc; /* true if pc not saved. */ | |
90 | int gpr_offset; /* offset of saved gprs from prev sp */ | |
91 | int fpr_offset; /* offset of saved fprs from prev sp */ | |
6be8bc0c | 92 | int vr_offset; /* offset of saved vrs from prev sp */ |
96ff0de4 | 93 | int ev_offset; /* offset of saved evs from prev sp */ |
7a78ae4e ND |
94 | int lr_offset; /* offset of saved lr */ |
95 | int cr_offset; /* offset of saved cr */ | |
6be8bc0c | 96 | int vrsave_offset; /* offset of saved vrsave register */ |
7a78ae4e ND |
97 | }; |
98 | ||
99 | /* Description of a single register. */ | |
100 | ||
101 | struct reg | |
102 | { | |
103 | char *name; /* name of register */ | |
0bcc32ae JB |
104 | unsigned char sz32; /* size on 32-bit arch, 0 if nonexistent */ |
105 | unsigned char sz64; /* size on 64-bit arch, 0 if nonexistent */ | |
7a78ae4e | 106 | unsigned char fpr; /* whether register is floating-point */ |
489461e2 | 107 | unsigned char pseudo; /* whether register is pseudo */ |
13ac140c JB |
108 | int spr_num; /* PowerPC SPR number, or -1 if not an SPR. |
109 | This is an ISA SPR number, not a GDB | |
110 | register number. */ | |
7a78ae4e ND |
111 | }; |
112 | ||
c906108c SS |
113 | /* Hook for determining the TOC address when calling functions in the |
114 | inferior under AIX. The initialization code in rs6000-nat.c sets | |
115 | this hook to point to find_toc_address. */ | |
116 | ||
7a78ae4e ND |
117 | CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL; |
118 | ||
c906108c SS |
119 | /* Static function prototypes */ |
120 | ||
a14ed312 KB |
121 | static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc, |
122 | CORE_ADDR safety); | |
077276e8 KB |
123 | static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR, |
124 | struct rs6000_framedata *); | |
c906108c | 125 | |
64b84175 KB |
126 | /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ |
127 | int | |
128 | altivec_register_p (int regno) | |
129 | { | |
130 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
131 | if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) | |
132 | return 0; | |
133 | else | |
134 | return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); | |
135 | } | |
136 | ||
383f0f5b | 137 | |
867e2dc5 JB |
138 | /* Return true if REGNO is an SPE register, false otherwise. */ |
139 | int | |
140 | spe_register_p (int regno) | |
141 | { | |
142 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
143 | ||
144 | /* Is it a reference to EV0 -- EV31, and do we have those? */ | |
145 | if (tdep->ppc_ev0_regnum >= 0 | |
146 | && tdep->ppc_ev31_regnum >= 0 | |
147 | && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum) | |
148 | return 1; | |
149 | ||
6ced10dd JB |
150 | /* Is it a reference to one of the raw upper GPR halves? */ |
151 | if (tdep->ppc_ev0_upper_regnum >= 0 | |
152 | && tdep->ppc_ev0_upper_regnum <= regno | |
153 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
154 | return 1; | |
155 | ||
867e2dc5 JB |
156 | /* Is it a reference to the 64-bit accumulator, and do we have that? */ |
157 | if (tdep->ppc_acc_regnum >= 0 | |
158 | && tdep->ppc_acc_regnum == regno) | |
159 | return 1; | |
160 | ||
161 | /* Is it a reference to the SPE floating-point status and control register, | |
162 | and do we have that? */ | |
163 | if (tdep->ppc_spefscr_regnum >= 0 | |
164 | && tdep->ppc_spefscr_regnum == regno) | |
165 | return 1; | |
166 | ||
167 | return 0; | |
168 | } | |
169 | ||
170 | ||
383f0f5b JB |
171 | /* Return non-zero if the architecture described by GDBARCH has |
172 | floating-point registers (f0 --- f31 and fpscr). */ | |
0a613259 AC |
173 | int |
174 | ppc_floating_point_unit_p (struct gdbarch *gdbarch) | |
175 | { | |
383f0f5b JB |
176 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
177 | ||
178 | return (tdep->ppc_fp0_regnum >= 0 | |
179 | && tdep->ppc_fpscr_regnum >= 0); | |
0a613259 | 180 | } |
9f643768 | 181 | |
09991fa0 JB |
182 | |
183 | /* Check that TABLE[GDB_REGNO] is not already initialized, and then | |
184 | set it to SIM_REGNO. | |
185 | ||
186 | This is a helper function for init_sim_regno_table, constructing | |
187 | the table mapping GDB register numbers to sim register numbers; we | |
188 | initialize every element in that table to -1 before we start | |
189 | filling it in. */ | |
9f643768 JB |
190 | static void |
191 | set_sim_regno (int *table, int gdb_regno, int sim_regno) | |
192 | { | |
193 | /* Make sure we don't try to assign any given GDB register a sim | |
194 | register number more than once. */ | |
195 | gdb_assert (table[gdb_regno] == -1); | |
196 | table[gdb_regno] = sim_regno; | |
197 | } | |
198 | ||
09991fa0 JB |
199 | |
200 | /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register | |
201 | numbers to simulator register numbers, based on the values placed | |
202 | in the ARCH->tdep->ppc_foo_regnum members. */ | |
9f643768 JB |
203 | static void |
204 | init_sim_regno_table (struct gdbarch *arch) | |
205 | { | |
206 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
207 | int total_regs = gdbarch_num_regs (arch) + gdbarch_num_pseudo_regs (arch); | |
208 | const struct reg *regs = tdep->regs; | |
209 | int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int); | |
210 | int i; | |
211 | ||
212 | /* Presume that all registers not explicitly mentioned below are | |
213 | unavailable from the sim. */ | |
214 | for (i = 0; i < total_regs; i++) | |
215 | sim_regno[i] = -1; | |
216 | ||
217 | /* General-purpose registers. */ | |
218 | for (i = 0; i < ppc_num_gprs; i++) | |
219 | set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i); | |
220 | ||
221 | /* Floating-point registers. */ | |
222 | if (tdep->ppc_fp0_regnum >= 0) | |
223 | for (i = 0; i < ppc_num_fprs; i++) | |
224 | set_sim_regno (sim_regno, | |
225 | tdep->ppc_fp0_regnum + i, | |
226 | sim_ppc_f0_regnum + i); | |
227 | if (tdep->ppc_fpscr_regnum >= 0) | |
228 | set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum); | |
229 | ||
230 | set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum); | |
231 | set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum); | |
232 | set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum); | |
233 | ||
234 | /* Segment registers. */ | |
235 | if (tdep->ppc_sr0_regnum >= 0) | |
236 | for (i = 0; i < ppc_num_srs; i++) | |
237 | set_sim_regno (sim_regno, | |
238 | tdep->ppc_sr0_regnum + i, | |
239 | sim_ppc_sr0_regnum + i); | |
240 | ||
241 | /* Altivec registers. */ | |
242 | if (tdep->ppc_vr0_regnum >= 0) | |
243 | { | |
244 | for (i = 0; i < ppc_num_vrs; i++) | |
245 | set_sim_regno (sim_regno, | |
246 | tdep->ppc_vr0_regnum + i, | |
247 | sim_ppc_vr0_regnum + i); | |
248 | ||
249 | /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum, | |
250 | we can treat this more like the other cases. */ | |
251 | set_sim_regno (sim_regno, | |
252 | tdep->ppc_vr0_regnum + ppc_num_vrs, | |
253 | sim_ppc_vscr_regnum); | |
254 | } | |
255 | /* vsave is a special-purpose register, so the code below handles it. */ | |
256 | ||
257 | /* SPE APU (E500) registers. */ | |
258 | if (tdep->ppc_ev0_regnum >= 0) | |
259 | for (i = 0; i < ppc_num_gprs; i++) | |
260 | set_sim_regno (sim_regno, | |
261 | tdep->ppc_ev0_regnum + i, | |
262 | sim_ppc_ev0_regnum + i); | |
6ced10dd JB |
263 | if (tdep->ppc_ev0_upper_regnum >= 0) |
264 | for (i = 0; i < ppc_num_gprs; i++) | |
265 | set_sim_regno (sim_regno, | |
266 | tdep->ppc_ev0_upper_regnum + i, | |
267 | sim_ppc_rh0_regnum + i); | |
9f643768 JB |
268 | if (tdep->ppc_acc_regnum >= 0) |
269 | set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum); | |
270 | /* spefscr is a special-purpose register, so the code below handles it. */ | |
271 | ||
272 | /* Now handle all special-purpose registers. Verify that they | |
273 | haven't mistakenly been assigned numbers by any of the above | |
274 | code). */ | |
275 | for (i = 0; i < total_regs; i++) | |
276 | if (regs[i].spr_num >= 0) | |
277 | set_sim_regno (sim_regno, i, regs[i].spr_num + sim_ppc_spr0_regnum); | |
278 | ||
279 | /* Drop the initialized array into place. */ | |
280 | tdep->sim_regno = sim_regno; | |
281 | } | |
282 | ||
09991fa0 JB |
283 | |
284 | /* Given a GDB register number REG, return the corresponding SIM | |
285 | register number. */ | |
9f643768 JB |
286 | static int |
287 | rs6000_register_sim_regno (int reg) | |
288 | { | |
289 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
290 | int sim_regno; | |
291 | ||
292 | gdb_assert (0 <= reg && reg <= NUM_REGS + NUM_PSEUDO_REGS); | |
293 | sim_regno = tdep->sim_regno[reg]; | |
294 | ||
295 | if (sim_regno >= 0) | |
296 | return sim_regno; | |
297 | else | |
298 | return LEGACY_SIM_REGNO_IGNORE; | |
299 | } | |
300 | ||
d195bc9f MK |
301 | \f |
302 | ||
303 | /* Register set support functions. */ | |
304 | ||
305 | static void | |
306 | ppc_supply_reg (struct regcache *regcache, int regnum, | |
50fd1280 | 307 | const gdb_byte *regs, size_t offset) |
d195bc9f MK |
308 | { |
309 | if (regnum != -1 && offset != -1) | |
310 | regcache_raw_supply (regcache, regnum, regs + offset); | |
311 | } | |
312 | ||
313 | static void | |
314 | ppc_collect_reg (const struct regcache *regcache, int regnum, | |
50fd1280 | 315 | gdb_byte *regs, size_t offset) |
d195bc9f MK |
316 | { |
317 | if (regnum != -1 && offset != -1) | |
318 | regcache_raw_collect (regcache, regnum, regs + offset); | |
319 | } | |
320 | ||
321 | /* Supply register REGNUM in the general-purpose register set REGSET | |
322 | from the buffer specified by GREGS and LEN to register cache | |
323 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
324 | ||
325 | void | |
326 | ppc_supply_gregset (const struct regset *regset, struct regcache *regcache, | |
327 | int regnum, const void *gregs, size_t len) | |
328 | { | |
329 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
330 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
331 | const struct ppc_reg_offsets *offsets = regset->descr; | |
332 | size_t offset; | |
333 | int i; | |
334 | ||
cdf2c5f5 | 335 | for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; |
063715bf | 336 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; |
cdf2c5f5 | 337 | i++, offset += 4) |
d195bc9f MK |
338 | { |
339 | if (regnum == -1 || regnum == i) | |
340 | ppc_supply_reg (regcache, i, gregs, offset); | |
341 | } | |
342 | ||
343 | if (regnum == -1 || regnum == PC_REGNUM) | |
344 | ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset); | |
345 | if (regnum == -1 || regnum == tdep->ppc_ps_regnum) | |
346 | ppc_supply_reg (regcache, tdep->ppc_ps_regnum, | |
347 | gregs, offsets->ps_offset); | |
348 | if (regnum == -1 || regnum == tdep->ppc_cr_regnum) | |
349 | ppc_supply_reg (regcache, tdep->ppc_cr_regnum, | |
350 | gregs, offsets->cr_offset); | |
351 | if (regnum == -1 || regnum == tdep->ppc_lr_regnum) | |
352 | ppc_supply_reg (regcache, tdep->ppc_lr_regnum, | |
353 | gregs, offsets->lr_offset); | |
354 | if (regnum == -1 || regnum == tdep->ppc_ctr_regnum) | |
355 | ppc_supply_reg (regcache, tdep->ppc_ctr_regnum, | |
356 | gregs, offsets->ctr_offset); | |
357 | if (regnum == -1 || regnum == tdep->ppc_xer_regnum) | |
358 | ppc_supply_reg (regcache, tdep->ppc_xer_regnum, | |
359 | gregs, offsets->cr_offset); | |
360 | if (regnum == -1 || regnum == tdep->ppc_mq_regnum) | |
361 | ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset); | |
362 | } | |
363 | ||
364 | /* Supply register REGNUM in the floating-point register set REGSET | |
365 | from the buffer specified by FPREGS and LEN to register cache | |
366 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
367 | ||
368 | void | |
369 | ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
370 | int regnum, const void *fpregs, size_t len) | |
371 | { | |
372 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
373 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
374 | const struct ppc_reg_offsets *offsets = regset->descr; | |
375 | size_t offset; | |
376 | int i; | |
377 | ||
383f0f5b JB |
378 | gdb_assert (ppc_floating_point_unit_p (gdbarch)); |
379 | ||
d195bc9f | 380 | offset = offsets->f0_offset; |
366f009f JB |
381 | for (i = tdep->ppc_fp0_regnum; |
382 | i < tdep->ppc_fp0_regnum + ppc_num_fprs; | |
bdbcb8b4 | 383 | i++, offset += 8) |
d195bc9f MK |
384 | { |
385 | if (regnum == -1 || regnum == i) | |
386 | ppc_supply_reg (regcache, i, fpregs, offset); | |
387 | } | |
388 | ||
389 | if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum) | |
390 | ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum, | |
391 | fpregs, offsets->fpscr_offset); | |
392 | } | |
393 | ||
394 | /* Collect register REGNUM in the general-purpose register set | |
395 | REGSET. from register cache REGCACHE into the buffer specified by | |
396 | GREGS and LEN. If REGNUM is -1, do this for all registers in | |
397 | REGSET. */ | |
398 | ||
399 | void | |
400 | ppc_collect_gregset (const struct regset *regset, | |
401 | const struct regcache *regcache, | |
402 | int regnum, void *gregs, size_t len) | |
403 | { | |
404 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
405 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
406 | const struct ppc_reg_offsets *offsets = regset->descr; | |
407 | size_t offset; | |
408 | int i; | |
409 | ||
410 | offset = offsets->r0_offset; | |
cdf2c5f5 | 411 | for (i = tdep->ppc_gp0_regnum; |
063715bf | 412 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; |
cdf2c5f5 | 413 | i++, offset += 4) |
d195bc9f MK |
414 | { |
415 | if (regnum == -1 || regnum == i) | |
2e56e9c1 | 416 | ppc_collect_reg (regcache, i, gregs, offset); |
d195bc9f MK |
417 | } |
418 | ||
419 | if (regnum == -1 || regnum == PC_REGNUM) | |
420 | ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset); | |
421 | if (regnum == -1 || regnum == tdep->ppc_ps_regnum) | |
422 | ppc_collect_reg (regcache, tdep->ppc_ps_regnum, | |
423 | gregs, offsets->ps_offset); | |
424 | if (regnum == -1 || regnum == tdep->ppc_cr_regnum) | |
425 | ppc_collect_reg (regcache, tdep->ppc_cr_regnum, | |
426 | gregs, offsets->cr_offset); | |
427 | if (regnum == -1 || regnum == tdep->ppc_lr_regnum) | |
428 | ppc_collect_reg (regcache, tdep->ppc_lr_regnum, | |
429 | gregs, offsets->lr_offset); | |
430 | if (regnum == -1 || regnum == tdep->ppc_ctr_regnum) | |
431 | ppc_collect_reg (regcache, tdep->ppc_ctr_regnum, | |
432 | gregs, offsets->ctr_offset); | |
433 | if (regnum == -1 || regnum == tdep->ppc_xer_regnum) | |
434 | ppc_collect_reg (regcache, tdep->ppc_xer_regnum, | |
435 | gregs, offsets->xer_offset); | |
436 | if (regnum == -1 || regnum == tdep->ppc_mq_regnum) | |
437 | ppc_collect_reg (regcache, tdep->ppc_mq_regnum, | |
438 | gregs, offsets->mq_offset); | |
439 | } | |
440 | ||
441 | /* Collect register REGNUM in the floating-point register set | |
442 | REGSET. from register cache REGCACHE into the buffer specified by | |
443 | FPREGS and LEN. If REGNUM is -1, do this for all registers in | |
444 | REGSET. */ | |
445 | ||
446 | void | |
447 | ppc_collect_fpregset (const struct regset *regset, | |
448 | const struct regcache *regcache, | |
449 | int regnum, void *fpregs, size_t len) | |
450 | { | |
451 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
452 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
453 | const struct ppc_reg_offsets *offsets = regset->descr; | |
454 | size_t offset; | |
455 | int i; | |
456 | ||
383f0f5b JB |
457 | gdb_assert (ppc_floating_point_unit_p (gdbarch)); |
458 | ||
d195bc9f | 459 | offset = offsets->f0_offset; |
366f009f JB |
460 | for (i = tdep->ppc_fp0_regnum; |
461 | i <= tdep->ppc_fp0_regnum + ppc_num_fprs; | |
bdbcb8b4 | 462 | i++, offset += 8) |
d195bc9f MK |
463 | { |
464 | if (regnum == -1 || regnum == i) | |
bdbcb8b4 | 465 | ppc_collect_reg (regcache, i, fpregs, offset); |
d195bc9f MK |
466 | } |
467 | ||
468 | if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum) | |
469 | ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum, | |
470 | fpregs, offsets->fpscr_offset); | |
471 | } | |
472 | \f | |
0a613259 | 473 | |
7a78ae4e | 474 | /* Read a LEN-byte address from debugged memory address MEMADDR. */ |
c906108c | 475 | |
7a78ae4e ND |
476 | static CORE_ADDR |
477 | read_memory_addr (CORE_ADDR memaddr, int len) | |
478 | { | |
479 | return read_memory_unsigned_integer (memaddr, len); | |
480 | } | |
c906108c | 481 | |
7a78ae4e ND |
482 | static CORE_ADDR |
483 | rs6000_skip_prologue (CORE_ADDR pc) | |
b83266a0 SS |
484 | { |
485 | struct rs6000_framedata frame; | |
4e463ff5 DJ |
486 | CORE_ADDR limit_pc, func_addr; |
487 | ||
488 | /* See if we can determine the end of the prologue via the symbol table. | |
489 | If so, then return either PC, or the PC after the prologue, whichever | |
490 | is greater. */ | |
491 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
492 | { | |
493 | CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr); | |
494 | if (post_prologue_pc != 0) | |
495 | return max (pc, post_prologue_pc); | |
496 | } | |
497 | ||
498 | /* Can't determine prologue from the symbol table, need to examine | |
499 | instructions. */ | |
500 | ||
501 | /* Find an upper limit on the function prologue using the debug | |
502 | information. If the debug information could not be used to provide | |
503 | that bound, then use an arbitrary large number as the upper bound. */ | |
504 | limit_pc = skip_prologue_using_sal (pc); | |
505 | if (limit_pc == 0) | |
506 | limit_pc = pc + 100; /* Magic. */ | |
507 | ||
508 | pc = skip_prologue (pc, limit_pc, &frame); | |
b83266a0 SS |
509 | return pc; |
510 | } | |
511 | ||
0d1243d9 PG |
512 | static int |
513 | insn_changes_sp_or_jumps (unsigned long insn) | |
514 | { | |
515 | int opcode = (insn >> 26) & 0x03f; | |
516 | int sd = (insn >> 21) & 0x01f; | |
517 | int a = (insn >> 16) & 0x01f; | |
518 | int subcode = (insn >> 1) & 0x3ff; | |
519 | ||
520 | /* Changes the stack pointer. */ | |
521 | ||
522 | /* NOTE: There are many ways to change the value of a given register. | |
523 | The ways below are those used when the register is R1, the SP, | |
524 | in a funtion's epilogue. */ | |
525 | ||
526 | if (opcode == 31 && subcode == 444 && a == 1) | |
527 | return 1; /* mr R1,Rn */ | |
528 | if (opcode == 14 && sd == 1) | |
529 | return 1; /* addi R1,Rn,simm */ | |
530 | if (opcode == 58 && sd == 1) | |
531 | return 1; /* ld R1,ds(Rn) */ | |
532 | ||
533 | /* Transfers control. */ | |
534 | ||
535 | if (opcode == 18) | |
536 | return 1; /* b */ | |
537 | if (opcode == 16) | |
538 | return 1; /* bc */ | |
539 | if (opcode == 19 && subcode == 16) | |
540 | return 1; /* bclr */ | |
541 | if (opcode == 19 && subcode == 528) | |
542 | return 1; /* bcctr */ | |
543 | ||
544 | return 0; | |
545 | } | |
546 | ||
547 | /* Return true if we are in the function's epilogue, i.e. after the | |
548 | instruction that destroyed the function's stack frame. | |
549 | ||
550 | 1) scan forward from the point of execution: | |
551 | a) If you find an instruction that modifies the stack pointer | |
552 | or transfers control (except a return), execution is not in | |
553 | an epilogue, return. | |
554 | b) Stop scanning if you find a return instruction or reach the | |
555 | end of the function or reach the hard limit for the size of | |
556 | an epilogue. | |
557 | 2) scan backward from the point of execution: | |
558 | a) If you find an instruction that modifies the stack pointer, | |
559 | execution *is* in an epilogue, return. | |
560 | b) Stop scanning if you reach an instruction that transfers | |
561 | control or the beginning of the function or reach the hard | |
562 | limit for the size of an epilogue. */ | |
563 | ||
564 | static int | |
565 | rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
566 | { | |
567 | bfd_byte insn_buf[PPC_INSN_SIZE]; | |
568 | CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end; | |
569 | unsigned long insn; | |
570 | struct frame_info *curfrm; | |
571 | ||
572 | /* Find the search limits based on function boundaries and hard limit. */ | |
573 | ||
574 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) | |
575 | return 0; | |
576 | ||
577 | epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; | |
578 | if (epilogue_start < func_start) epilogue_start = func_start; | |
579 | ||
580 | epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; | |
581 | if (epilogue_end > func_end) epilogue_end = func_end; | |
582 | ||
583 | curfrm = get_current_frame (); | |
584 | ||
585 | /* Scan forward until next 'blr'. */ | |
586 | ||
587 | for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE) | |
588 | { | |
589 | if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) | |
590 | return 0; | |
4e463ff5 | 591 | insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE); |
0d1243d9 PG |
592 | if (insn == 0x4e800020) |
593 | break; | |
594 | if (insn_changes_sp_or_jumps (insn)) | |
595 | return 0; | |
596 | } | |
597 | ||
598 | /* Scan backward until adjustment to stack pointer (R1). */ | |
599 | ||
600 | for (scan_pc = pc - PPC_INSN_SIZE; | |
601 | scan_pc >= epilogue_start; | |
602 | scan_pc -= PPC_INSN_SIZE) | |
603 | { | |
604 | if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) | |
605 | return 0; | |
4e463ff5 | 606 | insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE); |
0d1243d9 PG |
607 | if (insn_changes_sp_or_jumps (insn)) |
608 | return 1; | |
609 | } | |
610 | ||
611 | return 0; | |
612 | } | |
613 | ||
b83266a0 | 614 | |
c906108c SS |
615 | /* Fill in fi->saved_regs */ |
616 | ||
617 | struct frame_extra_info | |
618 | { | |
619 | /* Functions calling alloca() change the value of the stack | |
620 | pointer. We need to use initial stack pointer (which is saved in | |
621 | r31 by gcc) in such cases. If a compiler emits traceback table, | |
622 | then we should use the alloca register specified in traceback | |
623 | table. FIXME. */ | |
c5aa993b | 624 | CORE_ADDR initial_sp; /* initial stack pointer. */ |
c906108c SS |
625 | }; |
626 | ||
143985b7 | 627 | /* Get the ith function argument for the current function. */ |
b9362cc7 | 628 | static CORE_ADDR |
143985b7 AF |
629 | rs6000_fetch_pointer_argument (struct frame_info *frame, int argi, |
630 | struct type *type) | |
631 | { | |
50fd1280 | 632 | return get_frame_register_unsigned (frame, 3 + argi); |
143985b7 AF |
633 | } |
634 | ||
c906108c SS |
635 | /* Calculate the destination of a branch/jump. Return -1 if not a branch. */ |
636 | ||
637 | static CORE_ADDR | |
7a78ae4e | 638 | branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety) |
c906108c SS |
639 | { |
640 | CORE_ADDR dest; | |
641 | int immediate; | |
642 | int absolute; | |
643 | int ext_op; | |
644 | ||
645 | absolute = (int) ((instr >> 1) & 1); | |
646 | ||
c5aa993b JM |
647 | switch (opcode) |
648 | { | |
649 | case 18: | |
650 | immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */ | |
651 | if (absolute) | |
652 | dest = immediate; | |
653 | else | |
654 | dest = pc + immediate; | |
655 | break; | |
656 | ||
657 | case 16: | |
658 | immediate = ((instr & ~3) << 16) >> 16; /* br conditional */ | |
659 | if (absolute) | |
660 | dest = immediate; | |
661 | else | |
662 | dest = pc + immediate; | |
663 | break; | |
664 | ||
665 | case 19: | |
666 | ext_op = (instr >> 1) & 0x3ff; | |
667 | ||
668 | if (ext_op == 16) /* br conditional register */ | |
669 | { | |
2188cbdd | 670 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; |
c5aa993b JM |
671 | |
672 | /* If we are about to return from a signal handler, dest is | |
673 | something like 0x3c90. The current frame is a signal handler | |
674 | caller frame, upon completion of the sigreturn system call | |
675 | execution will return to the saved PC in the frame. */ | |
6f7f3f0d | 676 | if (dest < gdbarch_tdep (current_gdbarch)->text_segment_base) |
c5aa993b JM |
677 | { |
678 | struct frame_info *fi; | |
679 | ||
680 | fi = get_current_frame (); | |
681 | if (fi != NULL) | |
8b36eed8 | 682 | dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET, |
21283beb | 683 | gdbarch_tdep (current_gdbarch)->wordsize); |
c5aa993b JM |
684 | } |
685 | } | |
686 | ||
687 | else if (ext_op == 528) /* br cond to count reg */ | |
688 | { | |
2188cbdd | 689 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3; |
c5aa993b JM |
690 | |
691 | /* If we are about to execute a system call, dest is something | |
692 | like 0x22fc or 0x3b00. Upon completion the system call | |
693 | will return to the address in the link register. */ | |
6f7f3f0d | 694 | if (dest < gdbarch_tdep (current_gdbarch)->text_segment_base) |
2188cbdd | 695 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; |
c5aa993b JM |
696 | } |
697 | else | |
698 | return -1; | |
699 | break; | |
c906108c | 700 | |
c5aa993b JM |
701 | default: |
702 | return -1; | |
703 | } | |
6f7f3f0d | 704 | return (dest < gdbarch_tdep (current_gdbarch)->text_segment_base) ? safety : dest; |
c906108c SS |
705 | } |
706 | ||
707 | ||
708 | /* Sequence of bytes for breakpoint instruction. */ | |
709 | ||
f4f9705a | 710 | const static unsigned char * |
7a78ae4e | 711 | rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size) |
c906108c | 712 | { |
aaab4dba AC |
713 | static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 }; |
714 | static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d }; | |
c906108c | 715 | *bp_size = 4; |
d7449b42 | 716 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
717 | return big_breakpoint; |
718 | else | |
719 | return little_breakpoint; | |
720 | } | |
721 | ||
722 | ||
723 | /* AIX does not support PT_STEP. Simulate it. */ | |
724 | ||
725 | void | |
379d08a1 AC |
726 | rs6000_software_single_step (enum target_signal signal, |
727 | int insert_breakpoints_p) | |
c906108c | 728 | { |
7c40d541 KB |
729 | CORE_ADDR dummy; |
730 | int breakp_sz; | |
50fd1280 | 731 | const gdb_byte *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz); |
c906108c SS |
732 | int ii, insn; |
733 | CORE_ADDR loc; | |
734 | CORE_ADDR breaks[2]; | |
735 | int opcode; | |
736 | ||
c5aa993b JM |
737 | if (insert_breakpoints_p) |
738 | { | |
c5aa993b | 739 | loc = read_pc (); |
c906108c | 740 | |
c5aa993b | 741 | insn = read_memory_integer (loc, 4); |
c906108c | 742 | |
7c40d541 | 743 | breaks[0] = loc + breakp_sz; |
c5aa993b JM |
744 | opcode = insn >> 26; |
745 | breaks[1] = branch_dest (opcode, insn, loc, breaks[0]); | |
c906108c | 746 | |
c5aa993b JM |
747 | /* Don't put two breakpoints on the same address. */ |
748 | if (breaks[1] == breaks[0]) | |
749 | breaks[1] = -1; | |
c906108c | 750 | |
c5aa993b JM |
751 | for (ii = 0; ii < 2; ++ii) |
752 | { | |
c5aa993b JM |
753 | /* ignore invalid breakpoint. */ |
754 | if (breaks[ii] == -1) | |
755 | continue; | |
8181d85f | 756 | insert_single_step_breakpoint (breaks[ii]); |
c5aa993b | 757 | } |
c5aa993b JM |
758 | } |
759 | else | |
8181d85f | 760 | remove_single_step_breakpoints (); |
c906108c | 761 | |
c906108c | 762 | errno = 0; /* FIXME, don't ignore errors! */ |
c5aa993b | 763 | /* What errors? {read,write}_memory call error(). */ |
c906108c SS |
764 | } |
765 | ||
766 | ||
767 | /* return pc value after skipping a function prologue and also return | |
768 | information about a function frame. | |
769 | ||
770 | in struct rs6000_framedata fdata: | |
c5aa993b JM |
771 | - frameless is TRUE, if function does not have a frame. |
772 | - nosavedpc is TRUE, if function does not save %pc value in its frame. | |
773 | - offset is the initial size of this stack frame --- the amount by | |
774 | which we decrement the sp to allocate the frame. | |
775 | - saved_gpr is the number of the first saved gpr. | |
776 | - saved_fpr is the number of the first saved fpr. | |
6be8bc0c | 777 | - saved_vr is the number of the first saved vr. |
96ff0de4 | 778 | - saved_ev is the number of the first saved ev. |
c5aa993b JM |
779 | - alloca_reg is the number of the register used for alloca() handling. |
780 | Otherwise -1. | |
781 | - gpr_offset is the offset of the first saved gpr from the previous frame. | |
782 | - fpr_offset is the offset of the first saved fpr from the previous frame. | |
6be8bc0c | 783 | - vr_offset is the offset of the first saved vr from the previous frame. |
96ff0de4 | 784 | - ev_offset is the offset of the first saved ev from the previous frame. |
c5aa993b JM |
785 | - lr_offset is the offset of the saved lr |
786 | - cr_offset is the offset of the saved cr | |
6be8bc0c | 787 | - vrsave_offset is the offset of the saved vrsave register |
c5aa993b | 788 | */ |
c906108c SS |
789 | |
790 | #define SIGNED_SHORT(x) \ | |
791 | ((sizeof (short) == 2) \ | |
792 | ? ((int)(short)(x)) \ | |
793 | : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) | |
794 | ||
795 | #define GET_SRC_REG(x) (((x) >> 21) & 0x1f) | |
796 | ||
55d05f3b KB |
797 | /* Limit the number of skipped non-prologue instructions, as the examining |
798 | of the prologue is expensive. */ | |
799 | static int max_skip_non_prologue_insns = 10; | |
800 | ||
773df3e5 JB |
801 | /* Return nonzero if the given instruction OP can be part of the prologue |
802 | of a function and saves a parameter on the stack. FRAMEP should be | |
803 | set if one of the previous instructions in the function has set the | |
804 | Frame Pointer. */ | |
805 | ||
806 | static int | |
807 | store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg) | |
808 | { | |
809 | /* Move parameters from argument registers to temporary register. */ | |
810 | if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */ | |
811 | { | |
812 | /* Rx must be scratch register r0. */ | |
813 | const int rx_regno = (op >> 16) & 31; | |
814 | /* Ry: Only r3 - r10 are used for parameter passing. */ | |
815 | const int ry_regno = GET_SRC_REG (op); | |
816 | ||
817 | if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10) | |
818 | { | |
819 | *r0_contains_arg = 1; | |
820 | return 1; | |
821 | } | |
822 | else | |
823 | return 0; | |
824 | } | |
825 | ||
826 | /* Save a General Purpose Register on stack. */ | |
827 | ||
828 | if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */ | |
829 | (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */ | |
830 | { | |
831 | /* Rx: Only r3 - r10 are used for parameter passing. */ | |
832 | const int rx_regno = GET_SRC_REG (op); | |
833 | ||
834 | return (rx_regno >= 3 && rx_regno <= 10); | |
835 | } | |
836 | ||
837 | /* Save a General Purpose Register on stack via the Frame Pointer. */ | |
838 | ||
839 | if (framep && | |
840 | ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */ | |
841 | (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */ | |
842 | (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */ | |
843 | { | |
844 | /* Rx: Usually, only r3 - r10 are used for parameter passing. | |
845 | However, the compiler sometimes uses r0 to hold an argument. */ | |
846 | const int rx_regno = GET_SRC_REG (op); | |
847 | ||
848 | return ((rx_regno >= 3 && rx_regno <= 10) | |
849 | || (rx_regno == 0 && *r0_contains_arg)); | |
850 | } | |
851 | ||
852 | if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ | |
853 | { | |
854 | /* Only f2 - f8 are used for parameter passing. */ | |
855 | const int src_regno = GET_SRC_REG (op); | |
856 | ||
857 | return (src_regno >= 2 && src_regno <= 8); | |
858 | } | |
859 | ||
860 | if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */ | |
861 | { | |
862 | /* Only f2 - f8 are used for parameter passing. */ | |
863 | const int src_regno = GET_SRC_REG (op); | |
864 | ||
865 | return (src_regno >= 2 && src_regno <= 8); | |
866 | } | |
867 | ||
868 | /* Not an insn that saves a parameter on stack. */ | |
869 | return 0; | |
870 | } | |
55d05f3b | 871 | |
3c77c82a DJ |
872 | /* Assuming that INSN is a "bl" instruction located at PC, return |
873 | nonzero if the destination of the branch is a "blrl" instruction. | |
874 | ||
875 | This sequence is sometimes found in certain function prologues. | |
876 | It allows the function to load the LR register with a value that | |
877 | they can use to access PIC data using PC-relative offsets. */ | |
878 | ||
879 | static int | |
880 | bl_to_blrl_insn_p (CORE_ADDR pc, int insn) | |
881 | { | |
882 | const int opcode = 18; | |
883 | const CORE_ADDR dest = branch_dest (opcode, insn, pc, -1); | |
884 | int dest_insn; | |
885 | ||
886 | if (dest == -1) | |
887 | return 0; /* Should never happen, but just return zero to be safe. */ | |
888 | ||
889 | dest_insn = read_memory_integer (dest, 4); | |
890 | if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */ | |
891 | return 1; | |
892 | ||
893 | return 0; | |
894 | } | |
895 | ||
7a78ae4e | 896 | static CORE_ADDR |
077276e8 | 897 | skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) |
c906108c SS |
898 | { |
899 | CORE_ADDR orig_pc = pc; | |
55d05f3b | 900 | CORE_ADDR last_prologue_pc = pc; |
6be8bc0c | 901 | CORE_ADDR li_found_pc = 0; |
50fd1280 | 902 | gdb_byte buf[4]; |
c906108c SS |
903 | unsigned long op; |
904 | long offset = 0; | |
6be8bc0c | 905 | long vr_saved_offset = 0; |
482ca3f5 KB |
906 | int lr_reg = -1; |
907 | int cr_reg = -1; | |
6be8bc0c | 908 | int vr_reg = -1; |
96ff0de4 EZ |
909 | int ev_reg = -1; |
910 | long ev_offset = 0; | |
6be8bc0c | 911 | int vrsave_reg = -1; |
c906108c SS |
912 | int reg; |
913 | int framep = 0; | |
914 | int minimal_toc_loaded = 0; | |
ddb20c56 | 915 | int prev_insn_was_prologue_insn = 1; |
55d05f3b | 916 | int num_skip_non_prologue_insns = 0; |
773df3e5 | 917 | int r0_contains_arg = 0; |
96ff0de4 | 918 | const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch); |
6f99cb26 | 919 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 920 | |
ddb20c56 | 921 | memset (fdata, 0, sizeof (struct rs6000_framedata)); |
c906108c SS |
922 | fdata->saved_gpr = -1; |
923 | fdata->saved_fpr = -1; | |
6be8bc0c | 924 | fdata->saved_vr = -1; |
96ff0de4 | 925 | fdata->saved_ev = -1; |
c906108c SS |
926 | fdata->alloca_reg = -1; |
927 | fdata->frameless = 1; | |
928 | fdata->nosavedpc = 1; | |
929 | ||
55d05f3b | 930 | for (;; pc += 4) |
c906108c | 931 | { |
ddb20c56 KB |
932 | /* Sometimes it isn't clear if an instruction is a prologue |
933 | instruction or not. When we encounter one of these ambiguous | |
934 | cases, we'll set prev_insn_was_prologue_insn to 0 (false). | |
935 | Otherwise, we'll assume that it really is a prologue instruction. */ | |
936 | if (prev_insn_was_prologue_insn) | |
937 | last_prologue_pc = pc; | |
55d05f3b KB |
938 | |
939 | /* Stop scanning if we've hit the limit. */ | |
4e463ff5 | 940 | if (pc >= lim_pc) |
55d05f3b KB |
941 | break; |
942 | ||
ddb20c56 KB |
943 | prev_insn_was_prologue_insn = 1; |
944 | ||
55d05f3b | 945 | /* Fetch the instruction and convert it to an integer. */ |
ddb20c56 KB |
946 | if (target_read_memory (pc, buf, 4)) |
947 | break; | |
4e463ff5 | 948 | op = extract_unsigned_integer (buf, 4); |
c906108c | 949 | |
c5aa993b JM |
950 | if ((op & 0xfc1fffff) == 0x7c0802a6) |
951 | { /* mflr Rx */ | |
43b1ab88 AC |
952 | /* Since shared library / PIC code, which needs to get its |
953 | address at runtime, can appear to save more than one link | |
954 | register vis: | |
955 | ||
956 | *INDENT-OFF* | |
957 | stwu r1,-304(r1) | |
958 | mflr r3 | |
959 | bl 0xff570d0 (blrl) | |
960 | stw r30,296(r1) | |
961 | mflr r30 | |
962 | stw r31,300(r1) | |
963 | stw r3,308(r1); | |
964 | ... | |
965 | *INDENT-ON* | |
966 | ||
967 | remember just the first one, but skip over additional | |
968 | ones. */ | |
721d14ba | 969 | if (lr_reg == -1) |
43b1ab88 | 970 | lr_reg = (op & 0x03e00000); |
773df3e5 JB |
971 | if (lr_reg == 0) |
972 | r0_contains_arg = 0; | |
c5aa993b | 973 | continue; |
c5aa993b JM |
974 | } |
975 | else if ((op & 0xfc1fffff) == 0x7c000026) | |
976 | { /* mfcr Rx */ | |
98f08d3d | 977 | cr_reg = (op & 0x03e00000); |
773df3e5 JB |
978 | if (cr_reg == 0) |
979 | r0_contains_arg = 0; | |
c5aa993b | 980 | continue; |
c906108c | 981 | |
c906108c | 982 | } |
c5aa993b JM |
983 | else if ((op & 0xfc1f0000) == 0xd8010000) |
984 | { /* stfd Rx,NUM(r1) */ | |
985 | reg = GET_SRC_REG (op); | |
986 | if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) | |
987 | { | |
988 | fdata->saved_fpr = reg; | |
989 | fdata->fpr_offset = SIGNED_SHORT (op) + offset; | |
990 | } | |
991 | continue; | |
c906108c | 992 | |
c5aa993b JM |
993 | } |
994 | else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ | |
7a78ae4e ND |
995 | (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ |
996 | (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ | |
997 | (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ | |
c5aa993b JM |
998 | { |
999 | ||
1000 | reg = GET_SRC_REG (op); | |
1001 | if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) | |
1002 | { | |
1003 | fdata->saved_gpr = reg; | |
7a78ae4e | 1004 | if ((op & 0xfc1f0003) == 0xf8010000) |
98f08d3d | 1005 | op &= ~3UL; |
c5aa993b JM |
1006 | fdata->gpr_offset = SIGNED_SHORT (op) + offset; |
1007 | } | |
1008 | continue; | |
c906108c | 1009 | |
ddb20c56 KB |
1010 | } |
1011 | else if ((op & 0xffff0000) == 0x60000000) | |
1012 | { | |
96ff0de4 | 1013 | /* nop */ |
ddb20c56 KB |
1014 | /* Allow nops in the prologue, but do not consider them to |
1015 | be part of the prologue unless followed by other prologue | |
1016 | instructions. */ | |
1017 | prev_insn_was_prologue_insn = 0; | |
1018 | continue; | |
1019 | ||
c906108c | 1020 | } |
c5aa993b JM |
1021 | else if ((op & 0xffff0000) == 0x3c000000) |
1022 | { /* addis 0,0,NUM, used | |
1023 | for >= 32k frames */ | |
1024 | fdata->offset = (op & 0x0000ffff) << 16; | |
1025 | fdata->frameless = 0; | |
773df3e5 | 1026 | r0_contains_arg = 0; |
c5aa993b JM |
1027 | continue; |
1028 | ||
1029 | } | |
1030 | else if ((op & 0xffff0000) == 0x60000000) | |
1031 | { /* ori 0,0,NUM, 2nd ha | |
1032 | lf of >= 32k frames */ | |
1033 | fdata->offset |= (op & 0x0000ffff); | |
1034 | fdata->frameless = 0; | |
773df3e5 | 1035 | r0_contains_arg = 0; |
c5aa993b JM |
1036 | continue; |
1037 | ||
1038 | } | |
be723e22 | 1039 | else if (lr_reg >= 0 && |
98f08d3d KB |
1040 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ |
1041 | (((op & 0xffff0000) == (lr_reg | 0xf8010000)) || | |
1042 | /* stw Rx, NUM(r1) */ | |
1043 | ((op & 0xffff0000) == (lr_reg | 0x90010000)) || | |
1044 | /* stwu Rx, NUM(r1) */ | |
1045 | ((op & 0xffff0000) == (lr_reg | 0x94010000)))) | |
1046 | { /* where Rx == lr */ | |
1047 | fdata->lr_offset = offset; | |
c5aa993b | 1048 | fdata->nosavedpc = 0; |
be723e22 MS |
1049 | /* Invalidate lr_reg, but don't set it to -1. |
1050 | That would mean that it had never been set. */ | |
1051 | lr_reg = -2; | |
98f08d3d KB |
1052 | if ((op & 0xfc000003) == 0xf8000000 || /* std */ |
1053 | (op & 0xfc000000) == 0x90000000) /* stw */ | |
1054 | { | |
1055 | /* Does not update r1, so add displacement to lr_offset. */ | |
1056 | fdata->lr_offset += SIGNED_SHORT (op); | |
1057 | } | |
c5aa993b JM |
1058 | continue; |
1059 | ||
1060 | } | |
be723e22 | 1061 | else if (cr_reg >= 0 && |
98f08d3d KB |
1062 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ |
1063 | (((op & 0xffff0000) == (cr_reg | 0xf8010000)) || | |
1064 | /* stw Rx, NUM(r1) */ | |
1065 | ((op & 0xffff0000) == (cr_reg | 0x90010000)) || | |
1066 | /* stwu Rx, NUM(r1) */ | |
1067 | ((op & 0xffff0000) == (cr_reg | 0x94010000)))) | |
1068 | { /* where Rx == cr */ | |
1069 | fdata->cr_offset = offset; | |
be723e22 MS |
1070 | /* Invalidate cr_reg, but don't set it to -1. |
1071 | That would mean that it had never been set. */ | |
1072 | cr_reg = -2; | |
98f08d3d KB |
1073 | if ((op & 0xfc000003) == 0xf8000000 || |
1074 | (op & 0xfc000000) == 0x90000000) | |
1075 | { | |
1076 | /* Does not update r1, so add displacement to cr_offset. */ | |
1077 | fdata->cr_offset += SIGNED_SHORT (op); | |
1078 | } | |
c5aa993b JM |
1079 | continue; |
1080 | ||
1081 | } | |
721d14ba DJ |
1082 | else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1) |
1083 | { | |
1084 | /* bcl 20,xx,.+4 is used to get the current PC, with or without | |
1085 | prediction bits. If the LR has already been saved, we can | |
1086 | skip it. */ | |
1087 | continue; | |
1088 | } | |
c5aa993b JM |
1089 | else if (op == 0x48000005) |
1090 | { /* bl .+4 used in | |
1091 | -mrelocatable */ | |
1092 | continue; | |
1093 | ||
1094 | } | |
1095 | else if (op == 0x48000004) | |
1096 | { /* b .+4 (xlc) */ | |
1097 | break; | |
1098 | ||
c5aa993b | 1099 | } |
6be8bc0c EZ |
1100 | else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used |
1101 | in V.4 -mminimal-toc */ | |
c5aa993b JM |
1102 | (op & 0xffff0000) == 0x3bde0000) |
1103 | { /* addi 30,30,foo@l */ | |
1104 | continue; | |
c906108c | 1105 | |
c5aa993b JM |
1106 | } |
1107 | else if ((op & 0xfc000001) == 0x48000001) | |
1108 | { /* bl foo, | |
1109 | to save fprs??? */ | |
c906108c | 1110 | |
c5aa993b | 1111 | fdata->frameless = 0; |
3c77c82a DJ |
1112 | |
1113 | /* If the return address has already been saved, we can skip | |
1114 | calls to blrl (for PIC). */ | |
1115 | if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op)) | |
1116 | continue; | |
1117 | ||
6be8bc0c | 1118 | /* Don't skip over the subroutine call if it is not within |
ebd98106 FF |
1119 | the first three instructions of the prologue and either |
1120 | we have no line table information or the line info tells | |
1121 | us that the subroutine call is not part of the line | |
1122 | associated with the prologue. */ | |
c5aa993b | 1123 | if ((pc - orig_pc) > 8) |
ebd98106 FF |
1124 | { |
1125 | struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0); | |
1126 | struct symtab_and_line this_sal = find_pc_line (pc, 0); | |
1127 | ||
1128 | if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line)) | |
1129 | break; | |
1130 | } | |
c5aa993b JM |
1131 | |
1132 | op = read_memory_integer (pc + 4, 4); | |
1133 | ||
6be8bc0c EZ |
1134 | /* At this point, make sure this is not a trampoline |
1135 | function (a function that simply calls another functions, | |
1136 | and nothing else). If the next is not a nop, this branch | |
1137 | was part of the function prologue. */ | |
c5aa993b JM |
1138 | |
1139 | if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ | |
1140 | break; /* don't skip over | |
1141 | this branch */ | |
1142 | continue; | |
1143 | ||
c5aa993b | 1144 | } |
98f08d3d KB |
1145 | /* update stack pointer */ |
1146 | else if ((op & 0xfc1f0000) == 0x94010000) | |
1147 | { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */ | |
c5aa993b JM |
1148 | fdata->frameless = 0; |
1149 | fdata->offset = SIGNED_SHORT (op); | |
1150 | offset = fdata->offset; | |
1151 | continue; | |
c5aa993b | 1152 | } |
98f08d3d KB |
1153 | else if ((op & 0xfc1f016a) == 0x7c01016e) |
1154 | { /* stwux rX,r1,rY */ | |
1155 | /* no way to figure out what r1 is going to be */ | |
1156 | fdata->frameless = 0; | |
1157 | offset = fdata->offset; | |
1158 | continue; | |
1159 | } | |
1160 | else if ((op & 0xfc1f0003) == 0xf8010001) | |
1161 | { /* stdu rX,NUM(r1) */ | |
1162 | fdata->frameless = 0; | |
1163 | fdata->offset = SIGNED_SHORT (op & ~3UL); | |
1164 | offset = fdata->offset; | |
1165 | continue; | |
1166 | } | |
1167 | else if ((op & 0xfc1f016a) == 0x7c01016a) | |
1168 | { /* stdux rX,r1,rY */ | |
1169 | /* no way to figure out what r1 is going to be */ | |
c5aa993b JM |
1170 | fdata->frameless = 0; |
1171 | offset = fdata->offset; | |
1172 | continue; | |
c5aa993b | 1173 | } |
7313566f FF |
1174 | else if ((op & 0xffff0000) == 0x38210000) |
1175 | { /* addi r1,r1,SIMM */ | |
1176 | fdata->frameless = 0; | |
1177 | fdata->offset += SIGNED_SHORT (op); | |
1178 | offset = fdata->offset; | |
1179 | continue; | |
1180 | } | |
4e463ff5 DJ |
1181 | /* Load up minimal toc pointer. Do not treat an epilogue restore |
1182 | of r31 as a minimal TOC load. */ | |
98f08d3d KB |
1183 | else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */ |
1184 | (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */ | |
4e463ff5 | 1185 | && !framep |
c5aa993b | 1186 | && !minimal_toc_loaded) |
98f08d3d | 1187 | { |
c5aa993b JM |
1188 | minimal_toc_loaded = 1; |
1189 | continue; | |
1190 | ||
f6077098 KB |
1191 | /* move parameters from argument registers to local variable |
1192 | registers */ | |
1193 | } | |
1194 | else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ | |
1195 | (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ | |
1196 | (((op >> 21) & 31) <= 10) && | |
96ff0de4 | 1197 | ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */ |
f6077098 KB |
1198 | { |
1199 | continue; | |
1200 | ||
c5aa993b JM |
1201 | /* store parameters in stack */ |
1202 | } | |
e802b915 | 1203 | /* Move parameters from argument registers to temporary register. */ |
773df3e5 | 1204 | else if (store_param_on_stack_p (op, framep, &r0_contains_arg)) |
e802b915 | 1205 | { |
c5aa993b JM |
1206 | continue; |
1207 | ||
1208 | /* Set up frame pointer */ | |
1209 | } | |
1210 | else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ | |
1211 | || op == 0x7c3f0b78) | |
1212 | { /* mr r31, r1 */ | |
1213 | fdata->frameless = 0; | |
1214 | framep = 1; | |
6f99cb26 | 1215 | fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); |
c5aa993b JM |
1216 | continue; |
1217 | ||
1218 | /* Another way to set up the frame pointer. */ | |
1219 | } | |
1220 | else if ((op & 0xfc1fffff) == 0x38010000) | |
1221 | { /* addi rX, r1, 0x0 */ | |
1222 | fdata->frameless = 0; | |
1223 | framep = 1; | |
6f99cb26 AC |
1224 | fdata->alloca_reg = (tdep->ppc_gp0_regnum |
1225 | + ((op & ~0x38010000) >> 21)); | |
c5aa993b | 1226 | continue; |
c5aa993b | 1227 | } |
6be8bc0c EZ |
1228 | /* AltiVec related instructions. */ |
1229 | /* Store the vrsave register (spr 256) in another register for | |
1230 | later manipulation, or load a register into the vrsave | |
1231 | register. 2 instructions are used: mfvrsave and | |
1232 | mtvrsave. They are shorthand notation for mfspr Rn, SPR256 | |
1233 | and mtspr SPR256, Rn. */ | |
1234 | /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 | |
1235 | mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ | |
1236 | else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ | |
1237 | { | |
1238 | vrsave_reg = GET_SRC_REG (op); | |
1239 | continue; | |
1240 | } | |
1241 | else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ | |
1242 | { | |
1243 | continue; | |
1244 | } | |
1245 | /* Store the register where vrsave was saved to onto the stack: | |
1246 | rS is the register where vrsave was stored in a previous | |
1247 | instruction. */ | |
1248 | /* 100100 sssss 00001 dddddddd dddddddd */ | |
1249 | else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ | |
1250 | { | |
1251 | if (vrsave_reg == GET_SRC_REG (op)) | |
1252 | { | |
1253 | fdata->vrsave_offset = SIGNED_SHORT (op) + offset; | |
1254 | vrsave_reg = -1; | |
1255 | } | |
1256 | continue; | |
1257 | } | |
1258 | /* Compute the new value of vrsave, by modifying the register | |
1259 | where vrsave was saved to. */ | |
1260 | else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ | |
1261 | || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ | |
1262 | { | |
1263 | continue; | |
1264 | } | |
1265 | /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first | |
1266 | in a pair of insns to save the vector registers on the | |
1267 | stack. */ | |
1268 | /* 001110 00000 00000 iiii iiii iiii iiii */ | |
96ff0de4 EZ |
1269 | /* 001110 01110 00000 iiii iiii iiii iiii */ |
1270 | else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ | |
1271 | || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ | |
6be8bc0c | 1272 | { |
773df3e5 JB |
1273 | if ((op & 0xffff0000) == 0x38000000) |
1274 | r0_contains_arg = 0; | |
6be8bc0c EZ |
1275 | li_found_pc = pc; |
1276 | vr_saved_offset = SIGNED_SHORT (op); | |
773df3e5 JB |
1277 | |
1278 | /* This insn by itself is not part of the prologue, unless | |
1279 | if part of the pair of insns mentioned above. So do not | |
1280 | record this insn as part of the prologue yet. */ | |
1281 | prev_insn_was_prologue_insn = 0; | |
6be8bc0c EZ |
1282 | } |
1283 | /* Store vector register S at (r31+r0) aligned to 16 bytes. */ | |
1284 | /* 011111 sssss 11111 00000 00111001110 */ | |
1285 | else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ | |
1286 | { | |
1287 | if (pc == (li_found_pc + 4)) | |
1288 | { | |
1289 | vr_reg = GET_SRC_REG (op); | |
1290 | /* If this is the first vector reg to be saved, or if | |
1291 | it has a lower number than others previously seen, | |
1292 | reupdate the frame info. */ | |
1293 | if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) | |
1294 | { | |
1295 | fdata->saved_vr = vr_reg; | |
1296 | fdata->vr_offset = vr_saved_offset + offset; | |
1297 | } | |
1298 | vr_saved_offset = -1; | |
1299 | vr_reg = -1; | |
1300 | li_found_pc = 0; | |
1301 | } | |
1302 | } | |
1303 | /* End AltiVec related instructions. */ | |
96ff0de4 EZ |
1304 | |
1305 | /* Start BookE related instructions. */ | |
1306 | /* Store gen register S at (r31+uimm). | |
1307 | Any register less than r13 is volatile, so we don't care. */ | |
1308 | /* 000100 sssss 11111 iiiii 01100100001 */ | |
1309 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1310 | && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ | |
1311 | { | |
1312 | if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ | |
1313 | { | |
1314 | unsigned int imm; | |
1315 | ev_reg = GET_SRC_REG (op); | |
1316 | imm = (op >> 11) & 0x1f; | |
1317 | ev_offset = imm * 8; | |
1318 | /* If this is the first vector reg to be saved, or if | |
1319 | it has a lower number than others previously seen, | |
1320 | reupdate the frame info. */ | |
1321 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1322 | { | |
1323 | fdata->saved_ev = ev_reg; | |
1324 | fdata->ev_offset = ev_offset + offset; | |
1325 | } | |
1326 | } | |
1327 | continue; | |
1328 | } | |
1329 | /* Store gen register rS at (r1+rB). */ | |
1330 | /* 000100 sssss 00001 bbbbb 01100100000 */ | |
1331 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1332 | && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ | |
1333 | { | |
1334 | if (pc == (li_found_pc + 4)) | |
1335 | { | |
1336 | ev_reg = GET_SRC_REG (op); | |
1337 | /* If this is the first vector reg to be saved, or if | |
1338 | it has a lower number than others previously seen, | |
1339 | reupdate the frame info. */ | |
1340 | /* We know the contents of rB from the previous instruction. */ | |
1341 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1342 | { | |
1343 | fdata->saved_ev = ev_reg; | |
1344 | fdata->ev_offset = vr_saved_offset + offset; | |
1345 | } | |
1346 | vr_saved_offset = -1; | |
1347 | ev_reg = -1; | |
1348 | li_found_pc = 0; | |
1349 | } | |
1350 | continue; | |
1351 | } | |
1352 | /* Store gen register r31 at (rA+uimm). */ | |
1353 | /* 000100 11111 aaaaa iiiii 01100100001 */ | |
1354 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1355 | && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ | |
1356 | { | |
1357 | /* Wwe know that the source register is 31 already, but | |
1358 | it can't hurt to compute it. */ | |
1359 | ev_reg = GET_SRC_REG (op); | |
1360 | ev_offset = ((op >> 11) & 0x1f) * 8; | |
1361 | /* If this is the first vector reg to be saved, or if | |
1362 | it has a lower number than others previously seen, | |
1363 | reupdate the frame info. */ | |
1364 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1365 | { | |
1366 | fdata->saved_ev = ev_reg; | |
1367 | fdata->ev_offset = ev_offset + offset; | |
1368 | } | |
1369 | ||
1370 | continue; | |
1371 | } | |
1372 | /* Store gen register S at (r31+r0). | |
1373 | Store param on stack when offset from SP bigger than 4 bytes. */ | |
1374 | /* 000100 sssss 11111 00000 01100100000 */ | |
1375 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1376 | && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ | |
1377 | { | |
1378 | if (pc == (li_found_pc + 4)) | |
1379 | { | |
1380 | if ((op & 0x03e00000) >= 0x01a00000) | |
1381 | { | |
1382 | ev_reg = GET_SRC_REG (op); | |
1383 | /* If this is the first vector reg to be saved, or if | |
1384 | it has a lower number than others previously seen, | |
1385 | reupdate the frame info. */ | |
1386 | /* We know the contents of r0 from the previous | |
1387 | instruction. */ | |
1388 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1389 | { | |
1390 | fdata->saved_ev = ev_reg; | |
1391 | fdata->ev_offset = vr_saved_offset + offset; | |
1392 | } | |
1393 | ev_reg = -1; | |
1394 | } | |
1395 | vr_saved_offset = -1; | |
1396 | li_found_pc = 0; | |
1397 | continue; | |
1398 | } | |
1399 | } | |
1400 | /* End BookE related instructions. */ | |
1401 | ||
c5aa993b JM |
1402 | else |
1403 | { | |
55d05f3b KB |
1404 | /* Not a recognized prologue instruction. |
1405 | Handle optimizer code motions into the prologue by continuing | |
1406 | the search if we have no valid frame yet or if the return | |
1407 | address is not yet saved in the frame. */ | |
4e463ff5 | 1408 | if (fdata->frameless == 0 && fdata->nosavedpc == 0) |
55d05f3b KB |
1409 | break; |
1410 | ||
1411 | if (op == 0x4e800020 /* blr */ | |
1412 | || op == 0x4e800420) /* bctr */ | |
1413 | /* Do not scan past epilogue in frameless functions or | |
1414 | trampolines. */ | |
1415 | break; | |
1416 | if ((op & 0xf4000000) == 0x40000000) /* bxx */ | |
64366f1c | 1417 | /* Never skip branches. */ |
55d05f3b KB |
1418 | break; |
1419 | ||
1420 | if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) | |
1421 | /* Do not scan too many insns, scanning insns is expensive with | |
1422 | remote targets. */ | |
1423 | break; | |
1424 | ||
1425 | /* Continue scanning. */ | |
1426 | prev_insn_was_prologue_insn = 0; | |
1427 | continue; | |
c5aa993b | 1428 | } |
c906108c SS |
1429 | } |
1430 | ||
1431 | #if 0 | |
1432 | /* I have problems with skipping over __main() that I need to address | |
1433 | * sometime. Previously, I used to use misc_function_vector which | |
1434 | * didn't work as well as I wanted to be. -MGO */ | |
1435 | ||
1436 | /* If the first thing after skipping a prolog is a branch to a function, | |
1437 | this might be a call to an initializer in main(), introduced by gcc2. | |
64366f1c | 1438 | We'd like to skip over it as well. Fortunately, xlc does some extra |
c906108c | 1439 | work before calling a function right after a prologue, thus we can |
64366f1c | 1440 | single out such gcc2 behaviour. */ |
c906108c | 1441 | |
c906108c | 1442 | |
c5aa993b JM |
1443 | if ((op & 0xfc000001) == 0x48000001) |
1444 | { /* bl foo, an initializer function? */ | |
1445 | op = read_memory_integer (pc + 4, 4); | |
1446 | ||
1447 | if (op == 0x4def7b82) | |
1448 | { /* cror 0xf, 0xf, 0xf (nop) */ | |
c906108c | 1449 | |
64366f1c EZ |
1450 | /* Check and see if we are in main. If so, skip over this |
1451 | initializer function as well. */ | |
c906108c | 1452 | |
c5aa993b | 1453 | tmp = find_pc_misc_function (pc); |
6314a349 AC |
1454 | if (tmp >= 0 |
1455 | && strcmp (misc_function_vector[tmp].name, main_name ()) == 0) | |
c5aa993b JM |
1456 | return pc + 8; |
1457 | } | |
c906108c | 1458 | } |
c906108c | 1459 | #endif /* 0 */ |
c5aa993b JM |
1460 | |
1461 | fdata->offset = -fdata->offset; | |
ddb20c56 | 1462 | return last_prologue_pc; |
c906108c SS |
1463 | } |
1464 | ||
1465 | ||
1466 | /************************************************************************* | |
f6077098 | 1467 | Support for creating pushing a dummy frame into the stack, and popping |
c906108c SS |
1468 | frames, etc. |
1469 | *************************************************************************/ | |
1470 | ||
c906108c | 1471 | |
11269d7e AC |
1472 | /* All the ABI's require 16 byte alignment. */ |
1473 | static CORE_ADDR | |
1474 | rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
1475 | { | |
1476 | return (addr & -16); | |
1477 | } | |
1478 | ||
7a78ae4e | 1479 | /* Pass the arguments in either registers, or in the stack. In RS/6000, |
c906108c SS |
1480 | the first eight words of the argument list (that might be less than |
1481 | eight parameters if some parameters occupy more than one word) are | |
7a78ae4e | 1482 | passed in r3..r10 registers. float and double parameters are |
64366f1c EZ |
1483 | passed in fpr's, in addition to that. Rest of the parameters if any |
1484 | are passed in user stack. There might be cases in which half of the | |
c906108c SS |
1485 | parameter is copied into registers, the other half is pushed into |
1486 | stack. | |
1487 | ||
7a78ae4e ND |
1488 | Stack must be aligned on 64-bit boundaries when synthesizing |
1489 | function calls. | |
1490 | ||
c906108c SS |
1491 | If the function is returning a structure, then the return address is passed |
1492 | in r3, then the first 7 words of the parameters can be passed in registers, | |
64366f1c | 1493 | starting from r4. */ |
c906108c | 1494 | |
7a78ae4e | 1495 | static CORE_ADDR |
7d9b040b | 1496 | rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
77b2b6d4 AC |
1497 | struct regcache *regcache, CORE_ADDR bp_addr, |
1498 | int nargs, struct value **args, CORE_ADDR sp, | |
1499 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 1500 | { |
7a41266b | 1501 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
1502 | int ii; |
1503 | int len = 0; | |
c5aa993b JM |
1504 | int argno; /* current argument number */ |
1505 | int argbytes; /* current argument byte */ | |
50fd1280 | 1506 | gdb_byte tmp_buffer[50]; |
c5aa993b | 1507 | int f_argno = 0; /* current floating point argno */ |
21283beb | 1508 | int wordsize = gdbarch_tdep (current_gdbarch)->wordsize; |
7d9b040b | 1509 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
c906108c | 1510 | |
ea7c478f | 1511 | struct value *arg = 0; |
c906108c SS |
1512 | struct type *type; |
1513 | ||
1514 | CORE_ADDR saved_sp; | |
1515 | ||
383f0f5b JB |
1516 | /* The calling convention this function implements assumes the |
1517 | processor has floating-point registers. We shouldn't be using it | |
1518 | on PPC variants that lack them. */ | |
1519 | gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); | |
1520 | ||
64366f1c | 1521 | /* The first eight words of ther arguments are passed in registers. |
7a41266b AC |
1522 | Copy them appropriately. */ |
1523 | ii = 0; | |
1524 | ||
1525 | /* If the function is returning a `struct', then the first word | |
1526 | (which will be passed in r3) is used for struct return address. | |
1527 | In that case we should advance one word and start from r4 | |
1528 | register to copy parameters. */ | |
1529 | if (struct_return) | |
1530 | { | |
1531 | regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3, | |
1532 | struct_addr); | |
1533 | ii++; | |
1534 | } | |
c906108c SS |
1535 | |
1536 | /* | |
c5aa993b JM |
1537 | effectively indirect call... gcc does... |
1538 | ||
1539 | return_val example( float, int); | |
1540 | ||
1541 | eabi: | |
1542 | float in fp0, int in r3 | |
1543 | offset of stack on overflow 8/16 | |
1544 | for varargs, must go by type. | |
1545 | power open: | |
1546 | float in r3&r4, int in r5 | |
1547 | offset of stack on overflow different | |
1548 | both: | |
1549 | return in r3 or f0. If no float, must study how gcc emulates floats; | |
1550 | pay attention to arg promotion. | |
1551 | User may have to cast\args to handle promotion correctly | |
1552 | since gdb won't know if prototype supplied or not. | |
1553 | */ | |
c906108c | 1554 | |
c5aa993b JM |
1555 | for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii) |
1556 | { | |
3acba339 | 1557 | int reg_size = register_size (current_gdbarch, ii + 3); |
c5aa993b JM |
1558 | |
1559 | arg = args[argno]; | |
df407dfe | 1560 | type = check_typedef (value_type (arg)); |
c5aa993b JM |
1561 | len = TYPE_LENGTH (type); |
1562 | ||
1563 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1564 | { | |
1565 | ||
64366f1c | 1566 | /* Floating point arguments are passed in fpr's, as well as gpr's. |
c5aa993b | 1567 | There are 13 fpr's reserved for passing parameters. At this point |
64366f1c | 1568 | there is no way we would run out of them. */ |
c5aa993b | 1569 | |
9f335945 KB |
1570 | gdb_assert (len <= 8); |
1571 | ||
1572 | regcache_cooked_write (regcache, | |
1573 | tdep->ppc_fp0_regnum + 1 + f_argno, | |
0fd88904 | 1574 | value_contents (arg)); |
c5aa993b JM |
1575 | ++f_argno; |
1576 | } | |
1577 | ||
f6077098 | 1578 | if (len > reg_size) |
c5aa993b JM |
1579 | { |
1580 | ||
64366f1c | 1581 | /* Argument takes more than one register. */ |
c5aa993b JM |
1582 | while (argbytes < len) |
1583 | { | |
50fd1280 | 1584 | gdb_byte word[MAX_REGISTER_SIZE]; |
9f335945 KB |
1585 | memset (word, 0, reg_size); |
1586 | memcpy (word, | |
0fd88904 | 1587 | ((char *) value_contents (arg)) + argbytes, |
f6077098 KB |
1588 | (len - argbytes) > reg_size |
1589 | ? reg_size : len - argbytes); | |
9f335945 KB |
1590 | regcache_cooked_write (regcache, |
1591 | tdep->ppc_gp0_regnum + 3 + ii, | |
1592 | word); | |
f6077098 | 1593 | ++ii, argbytes += reg_size; |
c5aa993b JM |
1594 | |
1595 | if (ii >= 8) | |
1596 | goto ran_out_of_registers_for_arguments; | |
1597 | } | |
1598 | argbytes = 0; | |
1599 | --ii; | |
1600 | } | |
1601 | else | |
64366f1c EZ |
1602 | { |
1603 | /* Argument can fit in one register. No problem. */ | |
d7449b42 | 1604 | int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0; |
50fd1280 | 1605 | gdb_byte word[MAX_REGISTER_SIZE]; |
9f335945 KB |
1606 | |
1607 | memset (word, 0, reg_size); | |
0fd88904 | 1608 | memcpy (word, value_contents (arg), len); |
9f335945 | 1609 | regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word); |
c5aa993b JM |
1610 | } |
1611 | ++argno; | |
c906108c | 1612 | } |
c906108c SS |
1613 | |
1614 | ran_out_of_registers_for_arguments: | |
1615 | ||
7a78ae4e | 1616 | saved_sp = read_sp (); |
cc9836a8 | 1617 | |
64366f1c | 1618 | /* Location for 8 parameters are always reserved. */ |
7a78ae4e | 1619 | sp -= wordsize * 8; |
f6077098 | 1620 | |
64366f1c | 1621 | /* Another six words for back chain, TOC register, link register, etc. */ |
7a78ae4e | 1622 | sp -= wordsize * 6; |
f6077098 | 1623 | |
64366f1c | 1624 | /* Stack pointer must be quadword aligned. */ |
7a78ae4e | 1625 | sp &= -16; |
c906108c | 1626 | |
64366f1c EZ |
1627 | /* If there are more arguments, allocate space for them in |
1628 | the stack, then push them starting from the ninth one. */ | |
c906108c | 1629 | |
c5aa993b JM |
1630 | if ((argno < nargs) || argbytes) |
1631 | { | |
1632 | int space = 0, jj; | |
c906108c | 1633 | |
c5aa993b JM |
1634 | if (argbytes) |
1635 | { | |
1636 | space += ((len - argbytes + 3) & -4); | |
1637 | jj = argno + 1; | |
1638 | } | |
1639 | else | |
1640 | jj = argno; | |
c906108c | 1641 | |
c5aa993b JM |
1642 | for (; jj < nargs; ++jj) |
1643 | { | |
ea7c478f | 1644 | struct value *val = args[jj]; |
df407dfe | 1645 | space += ((TYPE_LENGTH (value_type (val))) + 3) & -4; |
c5aa993b | 1646 | } |
c906108c | 1647 | |
64366f1c | 1648 | /* Add location required for the rest of the parameters. */ |
f6077098 | 1649 | space = (space + 15) & -16; |
c5aa993b | 1650 | sp -= space; |
c906108c | 1651 | |
7aea86e6 AC |
1652 | /* This is another instance we need to be concerned about |
1653 | securing our stack space. If we write anything underneath %sp | |
1654 | (r1), we might conflict with the kernel who thinks he is free | |
1655 | to use this area. So, update %sp first before doing anything | |
1656 | else. */ | |
1657 | ||
1658 | regcache_raw_write_signed (regcache, SP_REGNUM, sp); | |
1659 | ||
64366f1c EZ |
1660 | /* If the last argument copied into the registers didn't fit there |
1661 | completely, push the rest of it into stack. */ | |
c906108c | 1662 | |
c5aa993b JM |
1663 | if (argbytes) |
1664 | { | |
1665 | write_memory (sp + 24 + (ii * 4), | |
50fd1280 | 1666 | value_contents (arg) + argbytes, |
c5aa993b JM |
1667 | len - argbytes); |
1668 | ++argno; | |
1669 | ii += ((len - argbytes + 3) & -4) / 4; | |
1670 | } | |
c906108c | 1671 | |
64366f1c | 1672 | /* Push the rest of the arguments into stack. */ |
c5aa993b JM |
1673 | for (; argno < nargs; ++argno) |
1674 | { | |
c906108c | 1675 | |
c5aa993b | 1676 | arg = args[argno]; |
df407dfe | 1677 | type = check_typedef (value_type (arg)); |
c5aa993b | 1678 | len = TYPE_LENGTH (type); |
c906108c SS |
1679 | |
1680 | ||
64366f1c EZ |
1681 | /* Float types should be passed in fpr's, as well as in the |
1682 | stack. */ | |
c5aa993b JM |
1683 | if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13) |
1684 | { | |
c906108c | 1685 | |
9f335945 | 1686 | gdb_assert (len <= 8); |
c906108c | 1687 | |
9f335945 KB |
1688 | regcache_cooked_write (regcache, |
1689 | tdep->ppc_fp0_regnum + 1 + f_argno, | |
0fd88904 | 1690 | value_contents (arg)); |
c5aa993b JM |
1691 | ++f_argno; |
1692 | } | |
c906108c | 1693 | |
50fd1280 | 1694 | write_memory (sp + 24 + (ii * 4), value_contents (arg), len); |
c5aa993b JM |
1695 | ii += ((len + 3) & -4) / 4; |
1696 | } | |
c906108c | 1697 | } |
c906108c | 1698 | |
69517000 | 1699 | /* Set the stack pointer. According to the ABI, the SP is meant to |
7aea86e6 AC |
1700 | be set _before_ the corresponding stack space is used. On AIX, |
1701 | this even applies when the target has been completely stopped! | |
1702 | Not doing this can lead to conflicts with the kernel which thinks | |
1703 | that it still has control over this not-yet-allocated stack | |
1704 | region. */ | |
33a7c2fc AC |
1705 | regcache_raw_write_signed (regcache, SP_REGNUM, sp); |
1706 | ||
7aea86e6 | 1707 | /* Set back chain properly. */ |
8ba0209f AM |
1708 | store_unsigned_integer (tmp_buffer, wordsize, saved_sp); |
1709 | write_memory (sp, tmp_buffer, wordsize); | |
7aea86e6 | 1710 | |
e56a0ecc AC |
1711 | /* Point the inferior function call's return address at the dummy's |
1712 | breakpoint. */ | |
1713 | regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr); | |
1714 | ||
794a477a AC |
1715 | /* Set the TOC register, get the value from the objfile reader |
1716 | which, in turn, gets it from the VMAP table. */ | |
1717 | if (rs6000_find_toc_address_hook != NULL) | |
1718 | { | |
1719 | CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr); | |
1720 | regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue); | |
1721 | } | |
1722 | ||
c906108c SS |
1723 | target_store_registers (-1); |
1724 | return sp; | |
1725 | } | |
c906108c | 1726 | |
d217aaed MK |
1727 | static enum return_value_convention |
1728 | rs6000_return_value (struct gdbarch *gdbarch, struct type *valtype, | |
1729 | struct regcache *regcache, gdb_byte *readbuf, | |
1730 | const gdb_byte *writebuf) | |
c906108c | 1731 | { |
ace1378a | 1732 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
d217aaed | 1733 | gdb_byte buf[8]; |
c906108c | 1734 | |
383f0f5b JB |
1735 | /* The calling convention this function implements assumes the |
1736 | processor has floating-point registers. We shouldn't be using it | |
d217aaed | 1737 | on PowerPC variants that lack them. */ |
383f0f5b JB |
1738 | gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); |
1739 | ||
d217aaed MK |
1740 | /* AltiVec extension: Functions that declare a vector data type as a |
1741 | return value place that return value in VR2. */ | |
1742 | if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY && TYPE_VECTOR (valtype) | |
1743 | && TYPE_LENGTH (valtype) == 16) | |
c5aa993b | 1744 | { |
d217aaed MK |
1745 | if (readbuf) |
1746 | regcache_cooked_read (regcache, tdep->ppc_vr0_regnum + 2, readbuf); | |
1747 | if (writebuf) | |
1748 | regcache_cooked_write (regcache, tdep->ppc_vr0_regnum + 2, writebuf); | |
c906108c | 1749 | |
d217aaed | 1750 | return RETURN_VALUE_REGISTER_CONVENTION; |
c5aa993b | 1751 | } |
d217aaed MK |
1752 | |
1753 | /* If the called subprogram returns an aggregate, there exists an | |
1754 | implicit first argument, whose value is the address of a caller- | |
1755 | allocated buffer into which the callee is assumed to store its | |
1756 | return value. All explicit parameters are appropriately | |
1757 | relabeled. */ | |
1758 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
1759 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
1760 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
1761 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1762 | ||
1763 | /* Scalar floating-point values are returned in FPR1 for float or | |
1764 | double, and in FPR1:FPR2 for quadword precision. Fortran | |
1765 | complex*8 and complex*16 are returned in FPR1:FPR2, and | |
1766 | complex*32 is returned in FPR1:FPR4. */ | |
1767 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
1768 | && (TYPE_LENGTH (valtype) == 4 || TYPE_LENGTH (valtype) == 8)) | |
1769 | { | |
1770 | struct type *regtype = register_type (gdbarch, tdep->ppc_fp0_regnum); | |
1771 | gdb_byte regval[8]; | |
1772 | ||
1773 | /* FIXME: kettenis/2007-01-01: Add support for quadword | |
1774 | precision and complex. */ | |
1775 | ||
1776 | if (readbuf) | |
1777 | { | |
1778 | regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1, regval); | |
1779 | convert_typed_floating (regval, regtype, readbuf, valtype); | |
1780 | } | |
1781 | if (writebuf) | |
1782 | { | |
1783 | convert_typed_floating (writebuf, valtype, regval, regtype); | |
1784 | regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1, regval); | |
1785 | } | |
1786 | ||
1787 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1788 | } | |
1789 | ||
1790 | /* Values of the types int, long, short, pointer, and char (length | |
1791 | is less than or equal to four bytes), as well as bit values of | |
1792 | lengths less than or equal to 32 bits, must be returned right | |
1793 | justified in GPR3 with signed values sign extended and unsigned | |
1794 | values zero extended, as necessary. */ | |
1795 | if (TYPE_LENGTH (valtype) <= tdep->wordsize) | |
ace1378a | 1796 | { |
d217aaed MK |
1797 | if (readbuf) |
1798 | { | |
1799 | ULONGEST regval; | |
1800 | ||
1801 | /* For reading we don't have to worry about sign extension. */ | |
1802 | regcache_cooked_read_unsigned (regcache, tdep->ppc_gp0_regnum + 3, | |
1803 | ®val); | |
1804 | store_unsigned_integer (readbuf, TYPE_LENGTH (valtype), regval); | |
1805 | } | |
1806 | if (writebuf) | |
1807 | { | |
1808 | /* For writing, use unpack_long since that should handle any | |
1809 | required sign extension. */ | |
1810 | regcache_cooked_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3, | |
1811 | unpack_long (valtype, writebuf)); | |
1812 | } | |
1813 | ||
1814 | return RETURN_VALUE_REGISTER_CONVENTION; | |
ace1378a | 1815 | } |
d217aaed MK |
1816 | |
1817 | /* Eight-byte non-floating-point scalar values must be returned in | |
1818 | GPR3:GPR4. */ | |
1819 | ||
1820 | if (TYPE_LENGTH (valtype) == 8) | |
c5aa993b | 1821 | { |
d217aaed MK |
1822 | gdb_assert (TYPE_CODE (valtype) != TYPE_CODE_FLT); |
1823 | gdb_assert (tdep->wordsize == 4); | |
1824 | ||
1825 | if (readbuf) | |
1826 | { | |
1827 | gdb_byte regval[8]; | |
1828 | ||
1829 | regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 3, regval); | |
1830 | regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 4, | |
1831 | regval + 4); | |
1832 | memcpy (readbuf, regval, 8); | |
1833 | } | |
1834 | if (writebuf) | |
1835 | { | |
1836 | regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3, writebuf); | |
1837 | regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 4, | |
1838 | writebuf + 4); | |
1839 | } | |
1840 | ||
1841 | return RETURN_VALUE_REGISTER_CONVENTION; | |
c906108c | 1842 | } |
d217aaed MK |
1843 | |
1844 | return RETURN_VALUE_STRUCT_CONVENTION; | |
c906108c SS |
1845 | } |
1846 | ||
977adac5 ND |
1847 | /* Return whether handle_inferior_event() should proceed through code |
1848 | starting at PC in function NAME when stepping. | |
1849 | ||
1850 | The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to | |
1851 | handle memory references that are too distant to fit in instructions | |
1852 | generated by the compiler. For example, if 'foo' in the following | |
1853 | instruction: | |
1854 | ||
1855 | lwz r9,foo(r2) | |
1856 | ||
1857 | is greater than 32767, the linker might replace the lwz with a branch to | |
1858 | somewhere in @FIX1 that does the load in 2 instructions and then branches | |
1859 | back to where execution should continue. | |
1860 | ||
1861 | GDB should silently step over @FIX code, just like AIX dbx does. | |
2ec664f5 MS |
1862 | Unfortunately, the linker uses the "b" instruction for the |
1863 | branches, meaning that the link register doesn't get set. | |
1864 | Therefore, GDB's usual step_over_function () mechanism won't work. | |
977adac5 | 1865 | |
2ec664f5 MS |
1866 | Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and |
1867 | SKIP_TRAMPOLINE_CODE hooks in handle_inferior_event() to skip past | |
1868 | @FIX code. */ | |
977adac5 ND |
1869 | |
1870 | int | |
1871 | rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name) | |
1872 | { | |
1873 | return name && !strncmp (name, "@FIX", 4); | |
1874 | } | |
1875 | ||
1876 | /* Skip code that the user doesn't want to see when stepping: | |
1877 | ||
1878 | 1. Indirect function calls use a piece of trampoline code to do context | |
1879 | switching, i.e. to set the new TOC table. Skip such code if we are on | |
1880 | its first instruction (as when we have single-stepped to here). | |
1881 | ||
1882 | 2. Skip shared library trampoline code (which is different from | |
c906108c | 1883 | indirect function call trampolines). |
977adac5 ND |
1884 | |
1885 | 3. Skip bigtoc fixup code. | |
1886 | ||
c906108c | 1887 | Result is desired PC to step until, or NULL if we are not in |
977adac5 | 1888 | code that should be skipped. */ |
c906108c SS |
1889 | |
1890 | CORE_ADDR | |
7a78ae4e | 1891 | rs6000_skip_trampoline_code (CORE_ADDR pc) |
c906108c | 1892 | { |
52f0bd74 | 1893 | unsigned int ii, op; |
977adac5 | 1894 | int rel; |
c906108c | 1895 | CORE_ADDR solib_target_pc; |
977adac5 | 1896 | struct minimal_symbol *msymbol; |
c906108c | 1897 | |
c5aa993b JM |
1898 | static unsigned trampoline_code[] = |
1899 | { | |
1900 | 0x800b0000, /* l r0,0x0(r11) */ | |
1901 | 0x90410014, /* st r2,0x14(r1) */ | |
1902 | 0x7c0903a6, /* mtctr r0 */ | |
1903 | 0x804b0004, /* l r2,0x4(r11) */ | |
1904 | 0x816b0008, /* l r11,0x8(r11) */ | |
1905 | 0x4e800420, /* bctr */ | |
1906 | 0x4e800020, /* br */ | |
1907 | 0 | |
c906108c SS |
1908 | }; |
1909 | ||
977adac5 ND |
1910 | /* Check for bigtoc fixup code. */ |
1911 | msymbol = lookup_minimal_symbol_by_pc (pc); | |
2ec664f5 MS |
1912 | if (msymbol |
1913 | && rs6000_in_solib_return_trampoline (pc, | |
1914 | DEPRECATED_SYMBOL_NAME (msymbol))) | |
977adac5 ND |
1915 | { |
1916 | /* Double-check that the third instruction from PC is relative "b". */ | |
1917 | op = read_memory_integer (pc + 8, 4); | |
1918 | if ((op & 0xfc000003) == 0x48000000) | |
1919 | { | |
1920 | /* Extract bits 6-29 as a signed 24-bit relative word address and | |
1921 | add it to the containing PC. */ | |
1922 | rel = ((int)(op << 6) >> 6); | |
1923 | return pc + 8 + rel; | |
1924 | } | |
1925 | } | |
1926 | ||
c906108c SS |
1927 | /* If pc is in a shared library trampoline, return its target. */ |
1928 | solib_target_pc = find_solib_trampoline_target (pc); | |
1929 | if (solib_target_pc) | |
1930 | return solib_target_pc; | |
1931 | ||
c5aa993b JM |
1932 | for (ii = 0; trampoline_code[ii]; ++ii) |
1933 | { | |
1934 | op = read_memory_integer (pc + (ii * 4), 4); | |
1935 | if (op != trampoline_code[ii]) | |
1936 | return 0; | |
1937 | } | |
1938 | ii = read_register (11); /* r11 holds destination addr */ | |
21283beb | 1939 | pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */ |
c906108c SS |
1940 | return pc; |
1941 | } | |
1942 | ||
7a78ae4e | 1943 | /* Return the size of register REG when words are WORDSIZE bytes long. If REG |
64366f1c | 1944 | isn't available with that word size, return 0. */ |
7a78ae4e ND |
1945 | |
1946 | static int | |
1947 | regsize (const struct reg *reg, int wordsize) | |
1948 | { | |
1949 | return wordsize == 8 ? reg->sz64 : reg->sz32; | |
1950 | } | |
1951 | ||
1952 | /* Return the name of register number N, or null if no such register exists | |
64366f1c | 1953 | in the current architecture. */ |
7a78ae4e | 1954 | |
fa88f677 | 1955 | static const char * |
7a78ae4e ND |
1956 | rs6000_register_name (int n) |
1957 | { | |
21283beb | 1958 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
1959 | const struct reg *reg = tdep->regs + n; |
1960 | ||
1961 | if (!regsize (reg, tdep->wordsize)) | |
1962 | return NULL; | |
1963 | return reg->name; | |
1964 | } | |
1965 | ||
7a78ae4e ND |
1966 | /* Return the GDB type object for the "standard" data type |
1967 | of data in register N. */ | |
1968 | ||
1969 | static struct type * | |
691d145a | 1970 | rs6000_register_type (struct gdbarch *gdbarch, int n) |
7a78ae4e | 1971 | { |
691d145a | 1972 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a78ae4e ND |
1973 | const struct reg *reg = tdep->regs + n; |
1974 | ||
1fcc0bb8 EZ |
1975 | if (reg->fpr) |
1976 | return builtin_type_double; | |
1977 | else | |
1978 | { | |
1979 | int size = regsize (reg, tdep->wordsize); | |
1980 | switch (size) | |
1981 | { | |
449a5da4 AC |
1982 | case 0: |
1983 | return builtin_type_int0; | |
1984 | case 4: | |
ed6edd9b | 1985 | return builtin_type_uint32; |
1fcc0bb8 | 1986 | case 8: |
c8001721 EZ |
1987 | if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum) |
1988 | return builtin_type_vec64; | |
1989 | else | |
ed6edd9b | 1990 | return builtin_type_uint64; |
1fcc0bb8 EZ |
1991 | break; |
1992 | case 16: | |
08cf96df | 1993 | return builtin_type_vec128; |
1fcc0bb8 EZ |
1994 | break; |
1995 | default: | |
e2e0b3e5 | 1996 | internal_error (__FILE__, __LINE__, _("Register %d size %d unknown"), |
449a5da4 | 1997 | n, size); |
1fcc0bb8 EZ |
1998 | } |
1999 | } | |
7a78ae4e ND |
2000 | } |
2001 | ||
c44ca51c AC |
2002 | /* Is REGNUM a member of REGGROUP? */ |
2003 | static int | |
2004 | rs6000_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
2005 | struct reggroup *group) | |
2006 | { | |
2007 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2008 | int float_p; | |
2009 | int vector_p; | |
2010 | int general_p; | |
2011 | ||
2012 | if (REGISTER_NAME (regnum) == NULL | |
2013 | || *REGISTER_NAME (regnum) == '\0') | |
2014 | return 0; | |
2015 | if (group == all_reggroup) | |
2016 | return 1; | |
2017 | ||
2018 | float_p = (regnum == tdep->ppc_fpscr_regnum | |
2019 | || (regnum >= tdep->ppc_fp0_regnum | |
2020 | && regnum < tdep->ppc_fp0_regnum + 32)); | |
2021 | if (group == float_reggroup) | |
2022 | return float_p; | |
2023 | ||
826d5376 PG |
2024 | vector_p = ((tdep->ppc_vr0_regnum >= 0 |
2025 | && regnum >= tdep->ppc_vr0_regnum | |
c44ca51c | 2026 | && regnum < tdep->ppc_vr0_regnum + 32) |
826d5376 PG |
2027 | || (tdep->ppc_ev0_regnum >= 0 |
2028 | && regnum >= tdep->ppc_ev0_regnum | |
c44ca51c | 2029 | && regnum < tdep->ppc_ev0_regnum + 32) |
3bf49e1b | 2030 | || regnum == tdep->ppc_vrsave_regnum - 1 /* vscr */ |
c44ca51c AC |
2031 | || regnum == tdep->ppc_vrsave_regnum |
2032 | || regnum == tdep->ppc_acc_regnum | |
2033 | || regnum == tdep->ppc_spefscr_regnum); | |
2034 | if (group == vector_reggroup) | |
2035 | return vector_p; | |
2036 | ||
2037 | /* Note that PS aka MSR isn't included - it's a system register (and | |
2038 | besides, due to GCC's CFI foobar you do not want to restore | |
2039 | it). */ | |
2040 | general_p = ((regnum >= tdep->ppc_gp0_regnum | |
2041 | && regnum < tdep->ppc_gp0_regnum + 32) | |
2042 | || regnum == tdep->ppc_toc_regnum | |
2043 | || regnum == tdep->ppc_cr_regnum | |
2044 | || regnum == tdep->ppc_lr_regnum | |
2045 | || regnum == tdep->ppc_ctr_regnum | |
2046 | || regnum == tdep->ppc_xer_regnum | |
2047 | || regnum == PC_REGNUM); | |
2048 | if (group == general_reggroup) | |
2049 | return general_p; | |
2050 | ||
2051 | if (group == save_reggroup || group == restore_reggroup) | |
2052 | return general_p || vector_p || float_p; | |
2053 | ||
2054 | return 0; | |
2055 | } | |
2056 | ||
691d145a | 2057 | /* The register format for RS/6000 floating point registers is always |
64366f1c | 2058 | double, we need a conversion if the memory format is float. */ |
7a78ae4e ND |
2059 | |
2060 | static int | |
691d145a | 2061 | rs6000_convert_register_p (int regnum, struct type *type) |
7a78ae4e | 2062 | { |
691d145a JB |
2063 | const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; |
2064 | ||
2065 | return (reg->fpr | |
2066 | && TYPE_CODE (type) == TYPE_CODE_FLT | |
2067 | && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double)); | |
7a78ae4e ND |
2068 | } |
2069 | ||
7a78ae4e | 2070 | static void |
691d145a JB |
2071 | rs6000_register_to_value (struct frame_info *frame, |
2072 | int regnum, | |
2073 | struct type *type, | |
50fd1280 | 2074 | gdb_byte *to) |
7a78ae4e | 2075 | { |
691d145a | 2076 | const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; |
50fd1280 | 2077 | gdb_byte from[MAX_REGISTER_SIZE]; |
691d145a JB |
2078 | |
2079 | gdb_assert (reg->fpr); | |
2080 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); | |
7a78ae4e | 2081 | |
691d145a JB |
2082 | get_frame_register (frame, regnum, from); |
2083 | convert_typed_floating (from, builtin_type_double, to, type); | |
2084 | } | |
7a292a7a | 2085 | |
7a78ae4e | 2086 | static void |
691d145a JB |
2087 | rs6000_value_to_register (struct frame_info *frame, |
2088 | int regnum, | |
2089 | struct type *type, | |
50fd1280 | 2090 | const gdb_byte *from) |
7a78ae4e | 2091 | { |
691d145a | 2092 | const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; |
50fd1280 | 2093 | gdb_byte to[MAX_REGISTER_SIZE]; |
691d145a JB |
2094 | |
2095 | gdb_assert (reg->fpr); | |
2096 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); | |
2097 | ||
2098 | convert_typed_floating (from, type, to, builtin_type_double); | |
2099 | put_frame_register (frame, regnum, to); | |
7a78ae4e | 2100 | } |
c906108c | 2101 | |
6ced10dd JB |
2102 | /* Move SPE vector register values between a 64-bit buffer and the two |
2103 | 32-bit raw register halves in a regcache. This function handles | |
2104 | both splitting a 64-bit value into two 32-bit halves, and joining | |
2105 | two halves into a whole 64-bit value, depending on the function | |
2106 | passed as the MOVE argument. | |
2107 | ||
2108 | EV_REG must be the number of an SPE evN vector register --- a | |
2109 | pseudoregister. REGCACHE must be a regcache, and BUFFER must be a | |
2110 | 64-bit buffer. | |
2111 | ||
2112 | Call MOVE once for each 32-bit half of that register, passing | |
2113 | REGCACHE, the number of the raw register corresponding to that | |
2114 | half, and the address of the appropriate half of BUFFER. | |
2115 | ||
2116 | For example, passing 'regcache_raw_read' as the MOVE function will | |
2117 | fill BUFFER with the full 64-bit contents of EV_REG. Or, passing | |
2118 | 'regcache_raw_supply' will supply the contents of BUFFER to the | |
2119 | appropriate pair of raw registers in REGCACHE. | |
2120 | ||
2121 | You may need to cast away some 'const' qualifiers when passing | |
2122 | MOVE, since this function can't tell at compile-time which of | |
2123 | REGCACHE or BUFFER is acting as the source of the data. If C had | |
2124 | co-variant type qualifiers, ... */ | |
2125 | static void | |
2126 | e500_move_ev_register (void (*move) (struct regcache *regcache, | |
50fd1280 | 2127 | int regnum, gdb_byte *buf), |
6ced10dd | 2128 | struct regcache *regcache, int ev_reg, |
50fd1280 | 2129 | gdb_byte *buffer) |
6ced10dd JB |
2130 | { |
2131 | struct gdbarch *arch = get_regcache_arch (regcache); | |
2132 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
2133 | int reg_index; | |
50fd1280 | 2134 | gdb_byte *byte_buffer = buffer; |
6ced10dd JB |
2135 | |
2136 | gdb_assert (tdep->ppc_ev0_regnum <= ev_reg | |
2137 | && ev_reg < tdep->ppc_ev0_regnum + ppc_num_gprs); | |
2138 | ||
2139 | reg_index = ev_reg - tdep->ppc_ev0_regnum; | |
2140 | ||
2141 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2142 | { | |
2143 | move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer); | |
2144 | move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4); | |
2145 | } | |
2146 | else | |
2147 | { | |
2148 | move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer); | |
2149 | move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4); | |
2150 | } | |
2151 | } | |
2152 | ||
c8001721 EZ |
2153 | static void |
2154 | e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
50fd1280 | 2155 | int reg_nr, gdb_byte *buffer) |
c8001721 | 2156 | { |
6ced10dd | 2157 | struct gdbarch *regcache_arch = get_regcache_arch (regcache); |
c8001721 EZ |
2158 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2159 | ||
6ced10dd JB |
2160 | gdb_assert (regcache_arch == gdbarch); |
2161 | ||
2162 | if (tdep->ppc_ev0_regnum <= reg_nr | |
2163 | && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs) | |
2164 | e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer); | |
2165 | else | |
a44bddec | 2166 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
2167 | _("e500_pseudo_register_read: " |
2168 | "called on unexpected register '%s' (%d)"), | |
a44bddec | 2169 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); |
c8001721 EZ |
2170 | } |
2171 | ||
2172 | static void | |
2173 | e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
50fd1280 | 2174 | int reg_nr, const gdb_byte *buffer) |
c8001721 | 2175 | { |
6ced10dd | 2176 | struct gdbarch *regcache_arch = get_regcache_arch (regcache); |
c8001721 EZ |
2177 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2178 | ||
6ced10dd JB |
2179 | gdb_assert (regcache_arch == gdbarch); |
2180 | ||
2181 | if (tdep->ppc_ev0_regnum <= reg_nr | |
2182 | && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs) | |
50fd1280 | 2183 | e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *)) |
6ced10dd | 2184 | regcache_raw_write, |
50fd1280 | 2185 | regcache, reg_nr, (gdb_byte *) buffer); |
6ced10dd | 2186 | else |
a44bddec | 2187 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
2188 | _("e500_pseudo_register_read: " |
2189 | "called on unexpected register '%s' (%d)"), | |
a44bddec | 2190 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); |
6ced10dd JB |
2191 | } |
2192 | ||
2193 | /* The E500 needs a custom reggroup function: it has anonymous raw | |
2194 | registers, and default_register_reggroup_p assumes that anonymous | |
2195 | registers are not members of any reggroup. */ | |
2196 | static int | |
2197 | e500_register_reggroup_p (struct gdbarch *gdbarch, | |
2198 | int regnum, | |
2199 | struct reggroup *group) | |
2200 | { | |
2201 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2202 | ||
2203 | /* The save and restore register groups need to include the | |
2204 | upper-half registers, even though they're anonymous. */ | |
2205 | if ((group == save_reggroup | |
2206 | || group == restore_reggroup) | |
2207 | && (tdep->ppc_ev0_upper_regnum <= regnum | |
2208 | && regnum < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)) | |
2209 | return 1; | |
2210 | ||
2211 | /* In all other regards, the default reggroup definition is fine. */ | |
2212 | return default_register_reggroup_p (gdbarch, regnum, group); | |
c8001721 EZ |
2213 | } |
2214 | ||
18ed0c4e | 2215 | /* Convert a DBX STABS register number to a GDB register number. */ |
c8001721 | 2216 | static int |
18ed0c4e | 2217 | rs6000_stab_reg_to_regnum (int num) |
c8001721 | 2218 | { |
9f744501 | 2219 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c8001721 | 2220 | |
9f744501 JB |
2221 | if (0 <= num && num <= 31) |
2222 | return tdep->ppc_gp0_regnum + num; | |
2223 | else if (32 <= num && num <= 63) | |
383f0f5b JB |
2224 | /* FIXME: jimb/2004-05-05: What should we do when the debug info |
2225 | specifies registers the architecture doesn't have? Our | |
2226 | callers don't check the value we return. */ | |
366f009f | 2227 | return tdep->ppc_fp0_regnum + (num - 32); |
18ed0c4e JB |
2228 | else if (77 <= num && num <= 108) |
2229 | return tdep->ppc_vr0_regnum + (num - 77); | |
9f744501 JB |
2230 | else if (1200 <= num && num < 1200 + 32) |
2231 | return tdep->ppc_ev0_regnum + (num - 1200); | |
2232 | else | |
2233 | switch (num) | |
2234 | { | |
2235 | case 64: | |
2236 | return tdep->ppc_mq_regnum; | |
2237 | case 65: | |
2238 | return tdep->ppc_lr_regnum; | |
2239 | case 66: | |
2240 | return tdep->ppc_ctr_regnum; | |
2241 | case 76: | |
2242 | return tdep->ppc_xer_regnum; | |
2243 | case 109: | |
2244 | return tdep->ppc_vrsave_regnum; | |
18ed0c4e JB |
2245 | case 110: |
2246 | return tdep->ppc_vrsave_regnum - 1; /* vscr */ | |
867e2dc5 | 2247 | case 111: |
18ed0c4e | 2248 | return tdep->ppc_acc_regnum; |
867e2dc5 | 2249 | case 112: |
18ed0c4e | 2250 | return tdep->ppc_spefscr_regnum; |
9f744501 JB |
2251 | default: |
2252 | return num; | |
2253 | } | |
18ed0c4e | 2254 | } |
9f744501 | 2255 | |
9f744501 | 2256 | |
18ed0c4e JB |
2257 | /* Convert a Dwarf 2 register number to a GDB register number. */ |
2258 | static int | |
2259 | rs6000_dwarf2_reg_to_regnum (int num) | |
2260 | { | |
2261 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
9f744501 | 2262 | |
18ed0c4e JB |
2263 | if (0 <= num && num <= 31) |
2264 | return tdep->ppc_gp0_regnum + num; | |
2265 | else if (32 <= num && num <= 63) | |
2266 | /* FIXME: jimb/2004-05-05: What should we do when the debug info | |
2267 | specifies registers the architecture doesn't have? Our | |
2268 | callers don't check the value we return. */ | |
2269 | return tdep->ppc_fp0_regnum + (num - 32); | |
2270 | else if (1124 <= num && num < 1124 + 32) | |
2271 | return tdep->ppc_vr0_regnum + (num - 1124); | |
2272 | else if (1200 <= num && num < 1200 + 32) | |
2273 | return tdep->ppc_ev0_regnum + (num - 1200); | |
2274 | else | |
2275 | switch (num) | |
2276 | { | |
a489f789 AS |
2277 | case 64: |
2278 | return tdep->ppc_cr_regnum; | |
18ed0c4e JB |
2279 | case 67: |
2280 | return tdep->ppc_vrsave_regnum - 1; /* vscr */ | |
2281 | case 99: | |
2282 | return tdep->ppc_acc_regnum; | |
2283 | case 100: | |
2284 | return tdep->ppc_mq_regnum; | |
2285 | case 101: | |
2286 | return tdep->ppc_xer_regnum; | |
2287 | case 108: | |
2288 | return tdep->ppc_lr_regnum; | |
2289 | case 109: | |
2290 | return tdep->ppc_ctr_regnum; | |
2291 | case 356: | |
2292 | return tdep->ppc_vrsave_regnum; | |
2293 | case 612: | |
2294 | return tdep->ppc_spefscr_regnum; | |
2295 | default: | |
2296 | return num; | |
2297 | } | |
2188cbdd EZ |
2298 | } |
2299 | ||
4fc771b8 DJ |
2300 | /* Translate a .eh_frame register to DWARF register, or adjust a |
2301 | .debug_frame register. */ | |
2302 | ||
2303 | static int | |
2304 | rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p) | |
2305 | { | |
2306 | /* GCC releases before 3.4 use GCC internal register numbering in | |
2307 | .debug_frame (and .debug_info, et cetera). The numbering is | |
2308 | different from the standard SysV numbering for everything except | |
2309 | for GPRs and FPRs. We can not detect this problem in most cases | |
2310 | - to get accurate debug info for variables living in lr, ctr, v0, | |
2311 | et cetera, use a newer version of GCC. But we must detect | |
2312 | one important case - lr is in column 65 in .debug_frame output, | |
2313 | instead of 108. | |
2314 | ||
2315 | GCC 3.4, and the "hammer" branch, have a related problem. They | |
2316 | record lr register saves in .debug_frame as 108, but still record | |
2317 | the return column as 65. We fix that up too. | |
2318 | ||
2319 | We can do this because 65 is assigned to fpsr, and GCC never | |
2320 | generates debug info referring to it. To add support for | |
2321 | handwritten debug info that restores fpsr, we would need to add a | |
2322 | producer version check to this. */ | |
2323 | if (!eh_frame_p) | |
2324 | { | |
2325 | if (num == 65) | |
2326 | return 108; | |
2327 | else | |
2328 | return num; | |
2329 | } | |
2330 | ||
2331 | /* .eh_frame is GCC specific. For binary compatibility, it uses GCC | |
2332 | internal register numbering; translate that to the standard DWARF2 | |
2333 | register numbering. */ | |
2334 | if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */ | |
2335 | return num; | |
2336 | else if (68 <= num && num <= 75) /* cr0-cr8 */ | |
2337 | return num - 68 + 86; | |
2338 | else if (77 <= num && num <= 108) /* vr0-vr31 */ | |
2339 | return num - 77 + 1124; | |
2340 | else | |
2341 | switch (num) | |
2342 | { | |
2343 | case 64: /* mq */ | |
2344 | return 100; | |
2345 | case 65: /* lr */ | |
2346 | return 108; | |
2347 | case 66: /* ctr */ | |
2348 | return 109; | |
2349 | case 76: /* xer */ | |
2350 | return 101; | |
2351 | case 109: /* vrsave */ | |
2352 | return 356; | |
2353 | case 110: /* vscr */ | |
2354 | return 67; | |
2355 | case 111: /* spe_acc */ | |
2356 | return 99; | |
2357 | case 112: /* spefscr */ | |
2358 | return 612; | |
2359 | default: | |
2360 | return num; | |
2361 | } | |
2362 | } | |
c906108c | 2363 | \f |
e2d0e7eb | 2364 | /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG). |
7a78ae4e ND |
2365 | |
2366 | Usually a function pointer's representation is simply the address | |
2367 | of the function. On the RS/6000 however, a function pointer is | |
8ba0209f | 2368 | represented by a pointer to an OPD entry. This OPD entry contains |
7a78ae4e ND |
2369 | three words, the first word is the address of the function, the |
2370 | second word is the TOC pointer (r2), and the third word is the | |
2371 | static chain value. Throughout GDB it is currently assumed that a | |
2372 | function pointer contains the address of the function, which is not | |
2373 | easy to fix. In addition, the conversion of a function address to | |
8ba0209f | 2374 | a function pointer would require allocation of an OPD entry in the |
7a78ae4e ND |
2375 | inferior's memory space, with all its drawbacks. To be able to |
2376 | call C++ virtual methods in the inferior (which are called via | |
f517ea4e | 2377 | function pointers), find_function_addr uses this function to get the |
7a78ae4e ND |
2378 | function address from a function pointer. */ |
2379 | ||
f517ea4e PS |
2380 | /* Return real function address if ADDR (a function pointer) is in the data |
2381 | space and is therefore a special function pointer. */ | |
c906108c | 2382 | |
b9362cc7 | 2383 | static CORE_ADDR |
e2d0e7eb AC |
2384 | rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch, |
2385 | CORE_ADDR addr, | |
2386 | struct target_ops *targ) | |
c906108c SS |
2387 | { |
2388 | struct obj_section *s; | |
2389 | ||
2390 | s = find_pc_section (addr); | |
2391 | if (s && s->the_bfd_section->flags & SEC_CODE) | |
7a78ae4e | 2392 | return addr; |
c906108c | 2393 | |
7a78ae4e | 2394 | /* ADDR is in the data space, so it's a special function pointer. */ |
7f68ac27 | 2395 | return read_memory_addr (addr, gdbarch_tdep (gdbarch)->wordsize); |
c906108c | 2396 | } |
c906108c | 2397 | \f |
c5aa993b | 2398 | |
7a78ae4e | 2399 | /* Handling the various POWER/PowerPC variants. */ |
c906108c SS |
2400 | |
2401 | ||
7a78ae4e ND |
2402 | /* The arrays here called registers_MUMBLE hold information about available |
2403 | registers. | |
c906108c SS |
2404 | |
2405 | For each family of PPC variants, I've tried to isolate out the | |
2406 | common registers and put them up front, so that as long as you get | |
2407 | the general family right, GDB will correctly identify the registers | |
2408 | common to that family. The common register sets are: | |
2409 | ||
2410 | For the 60x family: hid0 hid1 iabr dabr pir | |
2411 | ||
2412 | For the 505 and 860 family: eie eid nri | |
2413 | ||
2414 | For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi | |
c5aa993b JM |
2415 | tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1 |
2416 | pbu1 pbl2 pbu2 | |
c906108c SS |
2417 | |
2418 | Most of these register groups aren't anything formal. I arrived at | |
2419 | them by looking at the registers that occurred in more than one | |
6f5987a6 KB |
2420 | processor. |
2421 | ||
2422 | Note: kevinb/2002-04-30: Support for the fpscr register was added | |
2423 | during April, 2002. Slot 70 is being used for PowerPC and slot 71 | |
2424 | for Power. For PowerPC, slot 70 was unused and was already in the | |
2425 | PPC_UISA_SPRS which is ideally where fpscr should go. For Power, | |
2426 | slot 70 was being used for "mq", so the next available slot (71) | |
2427 | was chosen. It would have been nice to be able to make the | |
2428 | register numbers the same across processor cores, but this wasn't | |
2429 | possible without either 1) renumbering some registers for some | |
2430 | processors or 2) assigning fpscr to a really high slot that's | |
2431 | larger than any current register number. Doing (1) is bad because | |
2432 | existing stubs would break. Doing (2) is undesirable because it | |
2433 | would introduce a really large gap between fpscr and the rest of | |
2434 | the registers for most processors. */ | |
7a78ae4e | 2435 | |
64366f1c | 2436 | /* Convenience macros for populating register arrays. */ |
7a78ae4e | 2437 | |
64366f1c | 2438 | /* Within another macro, convert S to a string. */ |
7a78ae4e ND |
2439 | |
2440 | #define STR(s) #s | |
2441 | ||
2442 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems | |
64366f1c | 2443 | and 64 bits on 64-bit systems. */ |
13ac140c | 2444 | #define R(name) { STR(name), 4, 8, 0, 0, -1 } |
7a78ae4e ND |
2445 | |
2446 | /* Return a struct reg defining register NAME that's 32 bits on all | |
64366f1c | 2447 | systems. */ |
13ac140c | 2448 | #define R4(name) { STR(name), 4, 4, 0, 0, -1 } |
7a78ae4e ND |
2449 | |
2450 | /* Return a struct reg defining register NAME that's 64 bits on all | |
64366f1c | 2451 | systems. */ |
13ac140c | 2452 | #define R8(name) { STR(name), 8, 8, 0, 0, -1 } |
7a78ae4e | 2453 | |
1fcc0bb8 | 2454 | /* Return a struct reg defining register NAME that's 128 bits on all |
64366f1c | 2455 | systems. */ |
13ac140c | 2456 | #define R16(name) { STR(name), 16, 16, 0, 0, -1 } |
1fcc0bb8 | 2457 | |
64366f1c | 2458 | /* Return a struct reg defining floating-point register NAME. */ |
13ac140c | 2459 | #define F(name) { STR(name), 8, 8, 1, 0, -1 } |
489461e2 | 2460 | |
6ced10dd JB |
2461 | /* Return a struct reg defining a pseudo register NAME that is 64 bits |
2462 | long on all systems. */ | |
2463 | #define P8(name) { STR(name), 8, 8, 0, 1, -1 } | |
7a78ae4e ND |
2464 | |
2465 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit | |
64366f1c | 2466 | systems and that doesn't exist on 64-bit systems. */ |
13ac140c | 2467 | #define R32(name) { STR(name), 4, 0, 0, 0, -1 } |
7a78ae4e ND |
2468 | |
2469 | /* Return a struct reg defining register NAME that's 64 bits on 64-bit | |
64366f1c | 2470 | systems and that doesn't exist on 32-bit systems. */ |
13ac140c | 2471 | #define R64(name) { STR(name), 0, 8, 0, 0, -1 } |
7a78ae4e | 2472 | |
64366f1c | 2473 | /* Return a struct reg placeholder for a register that doesn't exist. */ |
13ac140c | 2474 | #define R0 { 0, 0, 0, 0, 0, -1 } |
7a78ae4e | 2475 | |
6ced10dd JB |
2476 | /* Return a struct reg defining an anonymous raw register that's 32 |
2477 | bits on all systems. */ | |
2478 | #define A4 { 0, 4, 4, 0, 0, -1 } | |
2479 | ||
13ac140c JB |
2480 | /* Return a struct reg defining an SPR named NAME that is 32 bits on |
2481 | 32-bit systems and 64 bits on 64-bit systems. */ | |
2482 | #define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name } | |
2483 | ||
2484 | /* Return a struct reg defining an SPR named NAME that is 32 bits on | |
2485 | all systems. */ | |
2486 | #define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name } | |
2487 | ||
2488 | /* Return a struct reg defining an SPR named NAME that is 32 bits on | |
2489 | all systems, and whose SPR number is NUMBER. */ | |
2490 | #define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) } | |
2491 | ||
2492 | /* Return a struct reg defining an SPR named NAME that's 64 bits on | |
2493 | 64-bit systems and that doesn't exist on 32-bit systems. */ | |
2494 | #define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name } | |
2495 | ||
7a78ae4e ND |
2496 | /* UISA registers common across all architectures, including POWER. */ |
2497 | ||
2498 | #define COMMON_UISA_REGS \ | |
2499 | /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ | |
2500 | /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ | |
2501 | /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ | |
2502 | /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ | |
2503 | /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \ | |
2504 | /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \ | |
2505 | /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \ | |
2506 | /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \ | |
2507 | /* 64 */ R(pc), R(ps) | |
2508 | ||
2509 | /* UISA-level SPRs for PowerPC. */ | |
2510 | #define PPC_UISA_SPRS \ | |
13ac140c | 2511 | /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr) |
7a78ae4e | 2512 | |
c8001721 EZ |
2513 | /* UISA-level SPRs for PowerPC without floating point support. */ |
2514 | #define PPC_UISA_NOFP_SPRS \ | |
13ac140c | 2515 | /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0 |
c8001721 | 2516 | |
7a78ae4e ND |
2517 | /* Segment registers, for PowerPC. */ |
2518 | #define PPC_SEGMENT_REGS \ | |
2519 | /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \ | |
2520 | /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \ | |
2521 | /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \ | |
2522 | /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15) | |
2523 | ||
2524 | /* OEA SPRs for PowerPC. */ | |
2525 | #define PPC_OEA_SPRS \ | |
13ac140c JB |
2526 | /* 87 */ S4(pvr), \ |
2527 | /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \ | |
2528 | /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \ | |
2529 | /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \ | |
2530 | /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \ | |
2531 | /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \ | |
2532 | /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \ | |
2533 | /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \ | |
2534 | /* 116 */ S4(dec), S(dabr), S4(ear) | |
7a78ae4e | 2535 | |
64366f1c | 2536 | /* AltiVec registers. */ |
1fcc0bb8 EZ |
2537 | #define PPC_ALTIVEC_REGS \ |
2538 | /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \ | |
2539 | /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \ | |
2540 | /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \ | |
2541 | /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \ | |
2542 | /*151*/R4(vscr), R4(vrsave) | |
2543 | ||
c8001721 | 2544 | |
6ced10dd JB |
2545 | /* On machines supporting the SPE APU, the general-purpose registers |
2546 | are 64 bits long. There are SIMD vector instructions to treat them | |
2547 | as pairs of floats, but the rest of the instruction set treats them | |
2548 | as 32-bit registers, and only operates on their lower halves. | |
2549 | ||
2550 | In the GDB regcache, we treat their high and low halves as separate | |
2551 | registers. The low halves we present as the general-purpose | |
2552 | registers, and then we have pseudo-registers that stitch together | |
2553 | the upper and lower halves and present them as pseudo-registers. */ | |
2554 | ||
2555 | /* SPE GPR lower halves --- raw registers. */ | |
2556 | #define PPC_SPE_GP_REGS \ | |
2557 | /* 0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7), \ | |
2558 | /* 8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \ | |
2559 | /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \ | |
2560 | /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31) | |
2561 | ||
2562 | /* SPE GPR upper halves --- anonymous raw registers. */ | |
2563 | #define PPC_SPE_UPPER_GP_REGS \ | |
2564 | /* 0 */ A4, A4, A4, A4, A4, A4, A4, A4, \ | |
2565 | /* 8 */ A4, A4, A4, A4, A4, A4, A4, A4, \ | |
2566 | /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4, \ | |
2567 | /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4 | |
2568 | ||
2569 | /* SPE GPR vector registers --- pseudo registers based on underlying | |
2570 | gprs and the anonymous upper half raw registers. */ | |
2571 | #define PPC_EV_PSEUDO_REGS \ | |
2572 | /* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \ | |
2573 | /* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\ | |
2574 | /*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\ | |
2575 | /*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31) | |
c8001721 | 2576 | |
7a78ae4e | 2577 | /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover |
64366f1c | 2578 | user-level SPR's. */ |
7a78ae4e | 2579 | static const struct reg registers_power[] = |
c906108c | 2580 | { |
7a78ae4e | 2581 | COMMON_UISA_REGS, |
13ac140c | 2582 | /* 66 */ R4(cnd), S(lr), S(cnt), S4(xer), S4(mq), |
e3f36dbd | 2583 | /* 71 */ R4(fpscr) |
c906108c SS |
2584 | }; |
2585 | ||
7a78ae4e | 2586 | /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only |
64366f1c | 2587 | view of the PowerPC. */ |
7a78ae4e | 2588 | static const struct reg registers_powerpc[] = |
c906108c | 2589 | { |
7a78ae4e | 2590 | COMMON_UISA_REGS, |
1fcc0bb8 EZ |
2591 | PPC_UISA_SPRS, |
2592 | PPC_ALTIVEC_REGS | |
c906108c SS |
2593 | }; |
2594 | ||
13ac140c JB |
2595 | /* IBM PowerPC 403. |
2596 | ||
2597 | Some notes about the "tcr" special-purpose register: | |
2598 | - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the | |
2599 | 403's programmable interval timer, fixed interval timer, and | |
2600 | watchdog timer. | |
2601 | - On the 602, SPR 984 is named "tcr", and it controls the 602's | |
2602 | watchdog timer, and nothing else. | |
2603 | ||
2604 | Some of the fields are similar between the two, but they're not | |
2605 | compatible with each other. Since the two variants have different | |
2606 | registers, with different numbers, but the same name, we can't | |
2607 | splice the register name to get the SPR number. */ | |
7a78ae4e | 2608 | static const struct reg registers_403[] = |
c5aa993b | 2609 | { |
7a78ae4e ND |
2610 | COMMON_UISA_REGS, |
2611 | PPC_UISA_SPRS, | |
2612 | PPC_SEGMENT_REGS, | |
2613 | PPC_OEA_SPRS, | |
13ac140c JB |
2614 | /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr), |
2615 | /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit), | |
2616 | /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3), | |
2617 | /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2), | |
2618 | /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr), | |
2619 | /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2) | |
c906108c SS |
2620 | }; |
2621 | ||
13ac140c JB |
2622 | /* IBM PowerPC 403GC. |
2623 | See the comments about 'tcr' for the 403, above. */ | |
7a78ae4e | 2624 | static const struct reg registers_403GC[] = |
c5aa993b | 2625 | { |
7a78ae4e ND |
2626 | COMMON_UISA_REGS, |
2627 | PPC_UISA_SPRS, | |
2628 | PPC_SEGMENT_REGS, | |
2629 | PPC_OEA_SPRS, | |
13ac140c JB |
2630 | /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr), |
2631 | /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit), | |
2632 | /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3), | |
2633 | /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2), | |
2634 | /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr), | |
2635 | /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2), | |
2636 | /* 143 */ S(zpr), S(pid), S(sgr), S(dcwr), | |
2637 | /* 147 */ S(tbhu), S(tblu) | |
c906108c SS |
2638 | }; |
2639 | ||
64366f1c | 2640 | /* Motorola PowerPC 505. */ |
7a78ae4e | 2641 | static const struct reg registers_505[] = |
c5aa993b | 2642 | { |
7a78ae4e ND |
2643 | COMMON_UISA_REGS, |
2644 | PPC_UISA_SPRS, | |
2645 | PPC_SEGMENT_REGS, | |
2646 | PPC_OEA_SPRS, | |
13ac140c | 2647 | /* 119 */ S(eie), S(eid), S(nri) |
c906108c SS |
2648 | }; |
2649 | ||
64366f1c | 2650 | /* Motorola PowerPC 860 or 850. */ |
7a78ae4e | 2651 | static const struct reg registers_860[] = |
c5aa993b | 2652 | { |
7a78ae4e ND |
2653 | COMMON_UISA_REGS, |
2654 | PPC_UISA_SPRS, | |
2655 | PPC_SEGMENT_REGS, | |
2656 | PPC_OEA_SPRS, | |
13ac140c JB |
2657 | /* 119 */ S(eie), S(eid), S(nri), S(cmpa), |
2658 | /* 123 */ S(cmpb), S(cmpc), S(cmpd), S(icr), | |
2659 | /* 127 */ S(der), S(counta), S(countb), S(cmpe), | |
2660 | /* 131 */ S(cmpf), S(cmpg), S(cmph), S(lctrl1), | |
2661 | /* 135 */ S(lctrl2), S(ictrl), S(bar), S(ic_cst), | |
2662 | /* 139 */ S(ic_adr), S(ic_dat), S(dc_cst), S(dc_adr), | |
2663 | /* 143 */ S(dc_dat), S(dpdr), S(dpir), S(immr), | |
2664 | /* 147 */ S(mi_ctr), S(mi_ap), S(mi_epn), S(mi_twc), | |
2665 | /* 151 */ S(mi_rpn), S(md_ctr), S(m_casid), S(md_ap), | |
2666 | /* 155 */ S(md_epn), S(m_twb), S(md_twc), S(md_rpn), | |
2667 | /* 159 */ S(m_tw), S(mi_dbcam), S(mi_dbram0), S(mi_dbram1), | |
2668 | /* 163 */ S(md_dbcam), S(md_dbram0), S(md_dbram1) | |
c906108c SS |
2669 | }; |
2670 | ||
7a78ae4e ND |
2671 | /* Motorola PowerPC 601. Note that the 601 has different register numbers |
2672 | for reading and writing RTCU and RTCL. However, how one reads and writes a | |
c906108c | 2673 | register is the stub's problem. */ |
7a78ae4e | 2674 | static const struct reg registers_601[] = |
c5aa993b | 2675 | { |
7a78ae4e ND |
2676 | COMMON_UISA_REGS, |
2677 | PPC_UISA_SPRS, | |
2678 | PPC_SEGMENT_REGS, | |
2679 | PPC_OEA_SPRS, | |
13ac140c JB |
2680 | /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), |
2681 | /* 123 */ S(pir), S(mq), S(rtcu), S(rtcl) | |
c906108c SS |
2682 | }; |
2683 | ||
13ac140c JB |
2684 | /* Motorola PowerPC 602. |
2685 | See the notes under the 403 about 'tcr'. */ | |
7a78ae4e | 2686 | static const struct reg registers_602[] = |
c5aa993b | 2687 | { |
7a78ae4e ND |
2688 | COMMON_UISA_REGS, |
2689 | PPC_UISA_SPRS, | |
2690 | PPC_SEGMENT_REGS, | |
2691 | PPC_OEA_SPRS, | |
13ac140c JB |
2692 | /* 119 */ S(hid0), S(hid1), S(iabr), R0, |
2693 | /* 123 */ R0, SN4(tcr, ppc_spr_602_tcr), S(ibr), S(esasrr), | |
2694 | /* 127 */ S(sebr), S(ser), S(sp), S(lt) | |
c906108c SS |
2695 | }; |
2696 | ||
64366f1c | 2697 | /* Motorola/IBM PowerPC 603 or 603e. */ |
7a78ae4e | 2698 | static const struct reg registers_603[] = |
c5aa993b | 2699 | { |
7a78ae4e ND |
2700 | COMMON_UISA_REGS, |
2701 | PPC_UISA_SPRS, | |
2702 | PPC_SEGMENT_REGS, | |
2703 | PPC_OEA_SPRS, | |
13ac140c JB |
2704 | /* 119 */ S(hid0), S(hid1), S(iabr), R0, |
2705 | /* 123 */ R0, S(dmiss), S(dcmp), S(hash1), | |
2706 | /* 127 */ S(hash2), S(imiss), S(icmp), S(rpa) | |
c906108c SS |
2707 | }; |
2708 | ||
64366f1c | 2709 | /* Motorola PowerPC 604 or 604e. */ |
7a78ae4e | 2710 | static const struct reg registers_604[] = |
c5aa993b | 2711 | { |
7a78ae4e ND |
2712 | COMMON_UISA_REGS, |
2713 | PPC_UISA_SPRS, | |
2714 | PPC_SEGMENT_REGS, | |
2715 | PPC_OEA_SPRS, | |
13ac140c JB |
2716 | /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), |
2717 | /* 123 */ S(pir), S(mmcr0), S(pmc1), S(pmc2), | |
2718 | /* 127 */ S(sia), S(sda) | |
c906108c SS |
2719 | }; |
2720 | ||
64366f1c | 2721 | /* Motorola/IBM PowerPC 750 or 740. */ |
7a78ae4e | 2722 | static const struct reg registers_750[] = |
c5aa993b | 2723 | { |
7a78ae4e ND |
2724 | COMMON_UISA_REGS, |
2725 | PPC_UISA_SPRS, | |
2726 | PPC_SEGMENT_REGS, | |
2727 | PPC_OEA_SPRS, | |
13ac140c JB |
2728 | /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), |
2729 | /* 123 */ R0, S(ummcr0), S(upmc1), S(upmc2), | |
2730 | /* 127 */ S(usia), S(ummcr1), S(upmc3), S(upmc4), | |
2731 | /* 131 */ S(mmcr0), S(pmc1), S(pmc2), S(sia), | |
2732 | /* 135 */ S(mmcr1), S(pmc3), S(pmc4), S(l2cr), | |
2733 | /* 139 */ S(ictc), S(thrm1), S(thrm2), S(thrm3) | |
c906108c SS |
2734 | }; |
2735 | ||
2736 | ||
64366f1c | 2737 | /* Motorola PowerPC 7400. */ |
1fcc0bb8 EZ |
2738 | static const struct reg registers_7400[] = |
2739 | { | |
2740 | /* gpr0-gpr31, fpr0-fpr31 */ | |
2741 | COMMON_UISA_REGS, | |
13c7b1ca | 2742 | /* cr, lr, ctr, xer, fpscr */ |
1fcc0bb8 EZ |
2743 | PPC_UISA_SPRS, |
2744 | /* sr0-sr15 */ | |
2745 | PPC_SEGMENT_REGS, | |
2746 | PPC_OEA_SPRS, | |
2747 | /* vr0-vr31, vrsave, vscr */ | |
2748 | PPC_ALTIVEC_REGS | |
2749 | /* FIXME? Add more registers? */ | |
2750 | }; | |
2751 | ||
c8001721 EZ |
2752 | /* Motorola e500. */ |
2753 | static const struct reg registers_e500[] = | |
2754 | { | |
6ced10dd JB |
2755 | /* 0 .. 31 */ PPC_SPE_GP_REGS, |
2756 | /* 32 .. 63 */ PPC_SPE_UPPER_GP_REGS, | |
2757 | /* 64 .. 65 */ R(pc), R(ps), | |
2758 | /* 66 .. 70 */ PPC_UISA_NOFP_SPRS, | |
2759 | /* 71 .. 72 */ R8(acc), S4(spefscr), | |
338ef23d AC |
2760 | /* NOTE: Add new registers here the end of the raw register |
2761 | list and just before the first pseudo register. */ | |
6ced10dd | 2762 | /* 73 .. 104 */ PPC_EV_PSEUDO_REGS |
c8001721 EZ |
2763 | }; |
2764 | ||
c906108c | 2765 | /* Information about a particular processor variant. */ |
7a78ae4e | 2766 | |
c906108c | 2767 | struct variant |
c5aa993b JM |
2768 | { |
2769 | /* Name of this variant. */ | |
2770 | char *name; | |
c906108c | 2771 | |
c5aa993b JM |
2772 | /* English description of the variant. */ |
2773 | char *description; | |
c906108c | 2774 | |
64366f1c | 2775 | /* bfd_arch_info.arch corresponding to variant. */ |
7a78ae4e ND |
2776 | enum bfd_architecture arch; |
2777 | ||
64366f1c | 2778 | /* bfd_arch_info.mach corresponding to variant. */ |
7a78ae4e ND |
2779 | unsigned long mach; |
2780 | ||
489461e2 EZ |
2781 | /* Number of real registers. */ |
2782 | int nregs; | |
2783 | ||
2784 | /* Number of pseudo registers. */ | |
2785 | int npregs; | |
2786 | ||
2787 | /* Number of total registers (the sum of nregs and npregs). */ | |
2788 | int num_tot_regs; | |
2789 | ||
c5aa993b JM |
2790 | /* Table of register names; registers[R] is the name of the register |
2791 | number R. */ | |
7a78ae4e | 2792 | const struct reg *regs; |
c5aa993b | 2793 | }; |
c906108c | 2794 | |
489461e2 EZ |
2795 | #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0])) |
2796 | ||
2797 | static int | |
2798 | num_registers (const struct reg *reg_list, int num_tot_regs) | |
2799 | { | |
2800 | int i; | |
2801 | int nregs = 0; | |
2802 | ||
2803 | for (i = 0; i < num_tot_regs; i++) | |
2804 | if (!reg_list[i].pseudo) | |
2805 | nregs++; | |
2806 | ||
2807 | return nregs; | |
2808 | } | |
2809 | ||
2810 | static int | |
2811 | num_pseudo_registers (const struct reg *reg_list, int num_tot_regs) | |
2812 | { | |
2813 | int i; | |
2814 | int npregs = 0; | |
2815 | ||
2816 | for (i = 0; i < num_tot_regs; i++) | |
2817 | if (reg_list[i].pseudo) | |
2818 | npregs ++; | |
2819 | ||
2820 | return npregs; | |
2821 | } | |
c906108c | 2822 | |
c906108c SS |
2823 | /* Information in this table comes from the following web sites: |
2824 | IBM: http://www.chips.ibm.com:80/products/embedded/ | |
2825 | Motorola: http://www.mot.com/SPS/PowerPC/ | |
2826 | ||
2827 | I'm sure I've got some of the variant descriptions not quite right. | |
2828 | Please report any inaccuracies you find to GDB's maintainer. | |
2829 | ||
2830 | If you add entries to this table, please be sure to allow the new | |
2831 | value as an argument to the --with-cpu flag, in configure.in. */ | |
2832 | ||
489461e2 | 2833 | static struct variant variants[] = |
c906108c | 2834 | { |
489461e2 | 2835 | |
7a78ae4e | 2836 | {"powerpc", "PowerPC user-level", bfd_arch_powerpc, |
489461e2 EZ |
2837 | bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc), |
2838 | registers_powerpc}, | |
7a78ae4e | 2839 | {"power", "POWER user-level", bfd_arch_rs6000, |
489461e2 EZ |
2840 | bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power), |
2841 | registers_power}, | |
7a78ae4e | 2842 | {"403", "IBM PowerPC 403", bfd_arch_powerpc, |
489461e2 EZ |
2843 | bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403), |
2844 | registers_403}, | |
7a78ae4e | 2845 | {"601", "Motorola PowerPC 601", bfd_arch_powerpc, |
489461e2 EZ |
2846 | bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601), |
2847 | registers_601}, | |
7a78ae4e | 2848 | {"602", "Motorola PowerPC 602", bfd_arch_powerpc, |
489461e2 EZ |
2849 | bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602), |
2850 | registers_602}, | |
7a78ae4e | 2851 | {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, |
489461e2 EZ |
2852 | bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603), |
2853 | registers_603}, | |
7a78ae4e | 2854 | {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, |
489461e2 EZ |
2855 | 604, -1, -1, tot_num_registers (registers_604), |
2856 | registers_604}, | |
7a78ae4e | 2857 | {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, |
489461e2 EZ |
2858 | bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC), |
2859 | registers_403GC}, | |
7a78ae4e | 2860 | {"505", "Motorola PowerPC 505", bfd_arch_powerpc, |
489461e2 EZ |
2861 | bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505), |
2862 | registers_505}, | |
7a78ae4e | 2863 | {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, |
489461e2 EZ |
2864 | bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860), |
2865 | registers_860}, | |
7a78ae4e | 2866 | {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, |
489461e2 EZ |
2867 | bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750), |
2868 | registers_750}, | |
1fcc0bb8 | 2869 | {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, |
489461e2 EZ |
2870 | bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400), |
2871 | registers_7400}, | |
c8001721 EZ |
2872 | {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, |
2873 | bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500), | |
2874 | registers_e500}, | |
7a78ae4e | 2875 | |
5d57ee30 KB |
2876 | /* 64-bit */ |
2877 | {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, | |
489461e2 EZ |
2878 | bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc), |
2879 | registers_powerpc}, | |
7a78ae4e | 2880 | {"620", "Motorola PowerPC 620", bfd_arch_powerpc, |
489461e2 EZ |
2881 | bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc), |
2882 | registers_powerpc}, | |
5d57ee30 | 2883 | {"630", "Motorola PowerPC 630", bfd_arch_powerpc, |
489461e2 EZ |
2884 | bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc), |
2885 | registers_powerpc}, | |
7a78ae4e | 2886 | {"a35", "PowerPC A35", bfd_arch_powerpc, |
489461e2 EZ |
2887 | bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc), |
2888 | registers_powerpc}, | |
5d57ee30 | 2889 | {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, |
489461e2 EZ |
2890 | bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc), |
2891 | registers_powerpc}, | |
5d57ee30 | 2892 | {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, |
489461e2 EZ |
2893 | bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc), |
2894 | registers_powerpc}, | |
5d57ee30 | 2895 | |
64366f1c | 2896 | /* FIXME: I haven't checked the register sets of the following. */ |
7a78ae4e | 2897 | {"rs1", "IBM POWER RS1", bfd_arch_rs6000, |
489461e2 EZ |
2898 | bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power), |
2899 | registers_power}, | |
7a78ae4e | 2900 | {"rsc", "IBM POWER RSC", bfd_arch_rs6000, |
489461e2 EZ |
2901 | bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power), |
2902 | registers_power}, | |
7a78ae4e | 2903 | {"rs2", "IBM POWER RS2", bfd_arch_rs6000, |
489461e2 EZ |
2904 | bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power), |
2905 | registers_power}, | |
7a78ae4e | 2906 | |
489461e2 | 2907 | {0, 0, 0, 0, 0, 0, 0, 0} |
c906108c SS |
2908 | }; |
2909 | ||
64366f1c | 2910 | /* Initialize the number of registers and pseudo registers in each variant. */ |
489461e2 EZ |
2911 | |
2912 | static void | |
2913 | init_variants (void) | |
2914 | { | |
2915 | struct variant *v; | |
2916 | ||
2917 | for (v = variants; v->name; v++) | |
2918 | { | |
2919 | if (v->nregs == -1) | |
2920 | v->nregs = num_registers (v->regs, v->num_tot_regs); | |
2921 | if (v->npregs == -1) | |
2922 | v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs); | |
2923 | } | |
2924 | } | |
c906108c | 2925 | |
7a78ae4e | 2926 | /* Return the variant corresponding to architecture ARCH and machine number |
64366f1c | 2927 | MACH. If no such variant exists, return null. */ |
c906108c | 2928 | |
7a78ae4e ND |
2929 | static const struct variant * |
2930 | find_variant_by_arch (enum bfd_architecture arch, unsigned long mach) | |
c906108c | 2931 | { |
7a78ae4e | 2932 | const struct variant *v; |
c5aa993b | 2933 | |
7a78ae4e ND |
2934 | for (v = variants; v->name; v++) |
2935 | if (arch == v->arch && mach == v->mach) | |
2936 | return v; | |
c906108c | 2937 | |
7a78ae4e | 2938 | return NULL; |
c906108c | 2939 | } |
9364a0ef EZ |
2940 | |
2941 | static int | |
2942 | gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info) | |
2943 | { | |
ee4f0f76 DJ |
2944 | if (!info->disassembler_options) |
2945 | info->disassembler_options = "any"; | |
2946 | ||
9364a0ef EZ |
2947 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
2948 | return print_insn_big_powerpc (memaddr, info); | |
2949 | else | |
2950 | return print_insn_little_powerpc (memaddr, info); | |
2951 | } | |
7a78ae4e | 2952 | \f |
61a65099 KB |
2953 | static CORE_ADDR |
2954 | rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2955 | { | |
2956 | return frame_unwind_register_unsigned (next_frame, PC_REGNUM); | |
2957 | } | |
2958 | ||
2959 | static struct frame_id | |
2960 | rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2961 | { | |
2962 | return frame_id_build (frame_unwind_register_unsigned (next_frame, | |
2963 | SP_REGNUM), | |
2964 | frame_pc_unwind (next_frame)); | |
2965 | } | |
2966 | ||
2967 | struct rs6000_frame_cache | |
2968 | { | |
2969 | CORE_ADDR base; | |
2970 | CORE_ADDR initial_sp; | |
2971 | struct trad_frame_saved_reg *saved_regs; | |
2972 | }; | |
2973 | ||
2974 | static struct rs6000_frame_cache * | |
2975 | rs6000_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2976 | { | |
2977 | struct rs6000_frame_cache *cache; | |
2978 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
2979 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2980 | struct rs6000_framedata fdata; | |
2981 | int wordsize = tdep->wordsize; | |
e10b1c4c | 2982 | CORE_ADDR func, pc; |
61a65099 KB |
2983 | |
2984 | if ((*this_cache) != NULL) | |
2985 | return (*this_cache); | |
2986 | cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); | |
2987 | (*this_cache) = cache; | |
2988 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
2989 | ||
93d42b30 | 2990 | func = frame_func_unwind (next_frame, NORMAL_FRAME); |
e10b1c4c DJ |
2991 | pc = frame_pc_unwind (next_frame); |
2992 | skip_prologue (func, pc, &fdata); | |
2993 | ||
2994 | /* Figure out the parent's stack pointer. */ | |
2995 | ||
2996 | /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most | |
2997 | address of the current frame. Things might be easier if the | |
2998 | ->frame pointed to the outer-most address of the frame. In | |
2999 | the mean time, the address of the prev frame is used as the | |
3000 | base address of this frame. */ | |
3001 | cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
3002 | ||
3003 | /* If the function appears to be frameless, check a couple of likely | |
3004 | indicators that we have simply failed to find the frame setup. | |
3005 | Two common cases of this are missing symbols (i.e. | |
3006 | frame_func_unwind returns the wrong address or 0), and assembly | |
3007 | stubs which have a fast exit path but set up a frame on the slow | |
3008 | path. | |
3009 | ||
3010 | If the LR appears to return to this function, then presume that | |
3011 | we have an ABI compliant frame that we failed to find. */ | |
3012 | if (fdata.frameless && fdata.lr_offset == 0) | |
61a65099 | 3013 | { |
e10b1c4c DJ |
3014 | CORE_ADDR saved_lr; |
3015 | int make_frame = 0; | |
3016 | ||
3017 | saved_lr = frame_unwind_register_unsigned (next_frame, | |
3018 | tdep->ppc_lr_regnum); | |
3019 | if (func == 0 && saved_lr == pc) | |
3020 | make_frame = 1; | |
3021 | else if (func != 0) | |
3022 | { | |
3023 | CORE_ADDR saved_func = get_pc_function_start (saved_lr); | |
3024 | if (func == saved_func) | |
3025 | make_frame = 1; | |
3026 | } | |
3027 | ||
3028 | if (make_frame) | |
3029 | { | |
3030 | fdata.frameless = 0; | |
de6a76fd | 3031 | fdata.lr_offset = tdep->lr_frame_offset; |
e10b1c4c | 3032 | } |
61a65099 | 3033 | } |
e10b1c4c DJ |
3034 | |
3035 | if (!fdata.frameless) | |
3036 | /* Frameless really means stackless. */ | |
3037 | cache->base = read_memory_addr (cache->base, wordsize); | |
3038 | ||
61a65099 KB |
3039 | trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base); |
3040 | ||
3041 | /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr. | |
3042 | All fpr's from saved_fpr to fp31 are saved. */ | |
3043 | ||
3044 | if (fdata.saved_fpr >= 0) | |
3045 | { | |
3046 | int i; | |
3047 | CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset; | |
383f0f5b JB |
3048 | |
3049 | /* If skip_prologue says floating-point registers were saved, | |
3050 | but the current architecture has no floating-point registers, | |
3051 | then that's strange. But we have no indices to even record | |
3052 | the addresses under, so we just ignore it. */ | |
3053 | if (ppc_floating_point_unit_p (gdbarch)) | |
063715bf | 3054 | for (i = fdata.saved_fpr; i < ppc_num_fprs; i++) |
383f0f5b JB |
3055 | { |
3056 | cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr; | |
3057 | fpr_addr += 8; | |
3058 | } | |
61a65099 KB |
3059 | } |
3060 | ||
3061 | /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr. | |
3062 | All gpr's from saved_gpr to gpr31 are saved. */ | |
3063 | ||
3064 | if (fdata.saved_gpr >= 0) | |
3065 | { | |
3066 | int i; | |
3067 | CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset; | |
063715bf | 3068 | for (i = fdata.saved_gpr; i < ppc_num_gprs; i++) |
61a65099 KB |
3069 | { |
3070 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr; | |
3071 | gpr_addr += wordsize; | |
3072 | } | |
3073 | } | |
3074 | ||
3075 | /* if != -1, fdata.saved_vr is the smallest number of saved_vr. | |
3076 | All vr's from saved_vr to vr31 are saved. */ | |
3077 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
3078 | { | |
3079 | if (fdata.saved_vr >= 0) | |
3080 | { | |
3081 | int i; | |
3082 | CORE_ADDR vr_addr = cache->base + fdata.vr_offset; | |
3083 | for (i = fdata.saved_vr; i < 32; i++) | |
3084 | { | |
3085 | cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr; | |
3086 | vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum); | |
3087 | } | |
3088 | } | |
3089 | } | |
3090 | ||
3091 | /* if != -1, fdata.saved_ev is the smallest number of saved_ev. | |
3092 | All vr's from saved_ev to ev31 are saved. ????? */ | |
3093 | if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1) | |
3094 | { | |
3095 | if (fdata.saved_ev >= 0) | |
3096 | { | |
3097 | int i; | |
3098 | CORE_ADDR ev_addr = cache->base + fdata.ev_offset; | |
063715bf | 3099 | for (i = fdata.saved_ev; i < ppc_num_gprs; i++) |
61a65099 KB |
3100 | { |
3101 | cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr; | |
3102 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4; | |
3103 | ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum); | |
3104 | } | |
3105 | } | |
3106 | } | |
3107 | ||
3108 | /* If != 0, fdata.cr_offset is the offset from the frame that | |
3109 | holds the CR. */ | |
3110 | if (fdata.cr_offset != 0) | |
3111 | cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset; | |
3112 | ||
3113 | /* If != 0, fdata.lr_offset is the offset from the frame that | |
3114 | holds the LR. */ | |
3115 | if (fdata.lr_offset != 0) | |
3116 | cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset; | |
3117 | /* The PC is found in the link register. */ | |
3118 | cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum]; | |
3119 | ||
3120 | /* If != 0, fdata.vrsave_offset is the offset from the frame that | |
3121 | holds the VRSAVE. */ | |
3122 | if (fdata.vrsave_offset != 0) | |
3123 | cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset; | |
3124 | ||
3125 | if (fdata.alloca_reg < 0) | |
3126 | /* If no alloca register used, then fi->frame is the value of the | |
3127 | %sp for this frame, and it is good enough. */ | |
3128 | cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
3129 | else | |
3130 | cache->initial_sp = frame_unwind_register_unsigned (next_frame, | |
3131 | fdata.alloca_reg); | |
3132 | ||
3133 | return cache; | |
3134 | } | |
3135 | ||
3136 | static void | |
3137 | rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
3138 | struct frame_id *this_id) | |
3139 | { | |
3140 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
3141 | this_cache); | |
93d42b30 DJ |
3142 | (*this_id) = frame_id_build (info->base, |
3143 | frame_func_unwind (next_frame, NORMAL_FRAME)); | |
61a65099 KB |
3144 | } |
3145 | ||
3146 | static void | |
3147 | rs6000_frame_prev_register (struct frame_info *next_frame, | |
3148 | void **this_cache, | |
3149 | int regnum, int *optimizedp, | |
3150 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
50fd1280 | 3151 | int *realnump, gdb_byte *valuep) |
61a65099 KB |
3152 | { |
3153 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
3154 | this_cache); | |
1f67027d AC |
3155 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
3156 | optimizedp, lvalp, addrp, realnump, valuep); | |
61a65099 KB |
3157 | } |
3158 | ||
3159 | static const struct frame_unwind rs6000_frame_unwind = | |
3160 | { | |
3161 | NORMAL_FRAME, | |
3162 | rs6000_frame_this_id, | |
3163 | rs6000_frame_prev_register | |
3164 | }; | |
3165 | ||
3166 | static const struct frame_unwind * | |
3167 | rs6000_frame_sniffer (struct frame_info *next_frame) | |
3168 | { | |
3169 | return &rs6000_frame_unwind; | |
3170 | } | |
3171 | ||
3172 | \f | |
3173 | ||
3174 | static CORE_ADDR | |
3175 | rs6000_frame_base_address (struct frame_info *next_frame, | |
3176 | void **this_cache) | |
3177 | { | |
3178 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
3179 | this_cache); | |
3180 | return info->initial_sp; | |
3181 | } | |
3182 | ||
3183 | static const struct frame_base rs6000_frame_base = { | |
3184 | &rs6000_frame_unwind, | |
3185 | rs6000_frame_base_address, | |
3186 | rs6000_frame_base_address, | |
3187 | rs6000_frame_base_address | |
3188 | }; | |
3189 | ||
3190 | static const struct frame_base * | |
3191 | rs6000_frame_base_sniffer (struct frame_info *next_frame) | |
3192 | { | |
3193 | return &rs6000_frame_base; | |
3194 | } | |
3195 | ||
7a78ae4e ND |
3196 | /* Initialize the current architecture based on INFO. If possible, re-use an |
3197 | architecture from ARCHES, which is a list of architectures already created | |
3198 | during this debugging session. | |
c906108c | 3199 | |
7a78ae4e | 3200 | Called e.g. at program startup, when reading a core file, and when reading |
64366f1c | 3201 | a binary file. */ |
c906108c | 3202 | |
7a78ae4e ND |
3203 | static struct gdbarch * |
3204 | rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
3205 | { | |
3206 | struct gdbarch *gdbarch; | |
3207 | struct gdbarch_tdep *tdep; | |
708ff411 | 3208 | int wordsize, from_xcoff_exec, from_elf_exec, i, off; |
7a78ae4e ND |
3209 | struct reg *regs; |
3210 | const struct variant *v; | |
3211 | enum bfd_architecture arch; | |
3212 | unsigned long mach; | |
3213 | bfd abfd; | |
7b112f9c | 3214 | int sysv_abi; |
5bf1c677 | 3215 | asection *sect; |
7a78ae4e | 3216 | |
9aa1e687 | 3217 | from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && |
7a78ae4e ND |
3218 | bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; |
3219 | ||
9aa1e687 KB |
3220 | from_elf_exec = info.abfd && info.abfd->format == bfd_object && |
3221 | bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
3222 | ||
3223 | sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
3224 | ||
e712c1cf | 3225 | /* Check word size. If INFO is from a binary file, infer it from |
64366f1c | 3226 | that, else choose a likely default. */ |
9aa1e687 | 3227 | if (from_xcoff_exec) |
c906108c | 3228 | { |
11ed25ac | 3229 | if (bfd_xcoff_is_xcoff64 (info.abfd)) |
7a78ae4e ND |
3230 | wordsize = 8; |
3231 | else | |
3232 | wordsize = 4; | |
c906108c | 3233 | } |
9aa1e687 KB |
3234 | else if (from_elf_exec) |
3235 | { | |
3236 | if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
3237 | wordsize = 8; | |
3238 | else | |
3239 | wordsize = 4; | |
3240 | } | |
c906108c | 3241 | else |
7a78ae4e | 3242 | { |
27b15785 KB |
3243 | if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) |
3244 | wordsize = info.bfd_arch_info->bits_per_word / | |
3245 | info.bfd_arch_info->bits_per_byte; | |
3246 | else | |
3247 | wordsize = 4; | |
7a78ae4e | 3248 | } |
c906108c | 3249 | |
13c0b536 | 3250 | /* Find a candidate among extant architectures. */ |
7a78ae4e ND |
3251 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
3252 | arches != NULL; | |
3253 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
3254 | { | |
3255 | /* Word size in the various PowerPC bfd_arch_info structs isn't | |
3256 | meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform | |
64366f1c | 3257 | separate word size check. */ |
7a78ae4e | 3258 | tdep = gdbarch_tdep (arches->gdbarch); |
4be87837 | 3259 | if (tdep && tdep->wordsize == wordsize) |
7a78ae4e ND |
3260 | return arches->gdbarch; |
3261 | } | |
c906108c | 3262 | |
7a78ae4e ND |
3263 | /* None found, create a new architecture from INFO, whose bfd_arch_info |
3264 | validity depends on the source: | |
3265 | - executable useless | |
3266 | - rs6000_host_arch() good | |
3267 | - core file good | |
3268 | - "set arch" trust blindly | |
3269 | - GDB startup useless but harmless */ | |
c906108c | 3270 | |
9aa1e687 | 3271 | if (!from_xcoff_exec) |
c906108c | 3272 | { |
b732d07d | 3273 | arch = info.bfd_arch_info->arch; |
7a78ae4e | 3274 | mach = info.bfd_arch_info->mach; |
c906108c | 3275 | } |
7a78ae4e | 3276 | else |
c906108c | 3277 | { |
7a78ae4e | 3278 | arch = bfd_arch_powerpc; |
35cec841 | 3279 | bfd_default_set_arch_mach (&abfd, arch, 0); |
7a78ae4e | 3280 | info.bfd_arch_info = bfd_get_arch_info (&abfd); |
35cec841 | 3281 | mach = info.bfd_arch_info->mach; |
7a78ae4e ND |
3282 | } |
3283 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
3284 | tdep->wordsize = wordsize; | |
5bf1c677 EZ |
3285 | |
3286 | /* For e500 executables, the apuinfo section is of help here. Such | |
3287 | section contains the identifier and revision number of each | |
3288 | Application-specific Processing Unit that is present on the | |
3289 | chip. The content of the section is determined by the assembler | |
3290 | which looks at each instruction and determines which unit (and | |
3291 | which version of it) can execute it. In our case we just look for | |
3292 | the existance of the section. */ | |
3293 | ||
3294 | if (info.abfd) | |
3295 | { | |
3296 | sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo"); | |
3297 | if (sect) | |
3298 | { | |
3299 | arch = info.bfd_arch_info->arch; | |
3300 | mach = bfd_mach_ppc_e500; | |
3301 | bfd_default_set_arch_mach (&abfd, arch, mach); | |
3302 | info.bfd_arch_info = bfd_get_arch_info (&abfd); | |
3303 | } | |
3304 | } | |
3305 | ||
7a78ae4e | 3306 | gdbarch = gdbarch_alloc (&info, tdep); |
7a78ae4e | 3307 | |
489461e2 EZ |
3308 | /* Initialize the number of real and pseudo registers in each variant. */ |
3309 | init_variants (); | |
3310 | ||
64366f1c | 3311 | /* Choose variant. */ |
7a78ae4e ND |
3312 | v = find_variant_by_arch (arch, mach); |
3313 | if (!v) | |
dd47e6fd EZ |
3314 | return NULL; |
3315 | ||
7a78ae4e ND |
3316 | tdep->regs = v->regs; |
3317 | ||
2188cbdd | 3318 | tdep->ppc_gp0_regnum = 0; |
2188cbdd EZ |
3319 | tdep->ppc_toc_regnum = 2; |
3320 | tdep->ppc_ps_regnum = 65; | |
3321 | tdep->ppc_cr_regnum = 66; | |
3322 | tdep->ppc_lr_regnum = 67; | |
3323 | tdep->ppc_ctr_regnum = 68; | |
3324 | tdep->ppc_xer_regnum = 69; | |
3325 | if (v->mach == bfd_mach_ppc_601) | |
3326 | tdep->ppc_mq_regnum = 124; | |
708ff411 | 3327 | else if (arch == bfd_arch_rs6000) |
2188cbdd | 3328 | tdep->ppc_mq_regnum = 70; |
e3f36dbd KB |
3329 | else |
3330 | tdep->ppc_mq_regnum = -1; | |
366f009f | 3331 | tdep->ppc_fp0_regnum = 32; |
708ff411 | 3332 | tdep->ppc_fpscr_regnum = (arch == bfd_arch_rs6000) ? 71 : 70; |
f86a7158 | 3333 | tdep->ppc_sr0_regnum = 71; |
baffbae0 JB |
3334 | tdep->ppc_vr0_regnum = -1; |
3335 | tdep->ppc_vrsave_regnum = -1; | |
6ced10dd | 3336 | tdep->ppc_ev0_upper_regnum = -1; |
baffbae0 JB |
3337 | tdep->ppc_ev0_regnum = -1; |
3338 | tdep->ppc_ev31_regnum = -1; | |
867e2dc5 JB |
3339 | tdep->ppc_acc_regnum = -1; |
3340 | tdep->ppc_spefscr_regnum = -1; | |
2188cbdd | 3341 | |
c8001721 EZ |
3342 | set_gdbarch_pc_regnum (gdbarch, 64); |
3343 | set_gdbarch_sp_regnum (gdbarch, 1); | |
0ba6dca9 | 3344 | set_gdbarch_deprecated_fp_regnum (gdbarch, 1); |
6f7f3f0d | 3345 | set_gdbarch_fp0_regnum (gdbarch, 32); |
9f643768 | 3346 | set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno); |
afd48b75 | 3347 | if (sysv_abi && wordsize == 8) |
05580c65 | 3348 | set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value); |
e754ae69 | 3349 | else if (sysv_abi && wordsize == 4) |
05580c65 | 3350 | set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value); |
afd48b75 | 3351 | else |
d217aaed | 3352 | set_gdbarch_return_value (gdbarch, rs6000_return_value); |
c8001721 | 3353 | |
baffbae0 JB |
3354 | /* Set lr_frame_offset. */ |
3355 | if (wordsize == 8) | |
3356 | tdep->lr_frame_offset = 16; | |
3357 | else if (sysv_abi) | |
3358 | tdep->lr_frame_offset = 4; | |
3359 | else | |
3360 | tdep->lr_frame_offset = 8; | |
3361 | ||
f86a7158 JB |
3362 | if (v->arch == bfd_arch_rs6000) |
3363 | tdep->ppc_sr0_regnum = -1; | |
3364 | else if (v->arch == bfd_arch_powerpc) | |
1fcc0bb8 EZ |
3365 | switch (v->mach) |
3366 | { | |
3367 | case bfd_mach_ppc: | |
412b3060 | 3368 | tdep->ppc_sr0_regnum = -1; |
1fcc0bb8 EZ |
3369 | tdep->ppc_vr0_regnum = 71; |
3370 | tdep->ppc_vrsave_regnum = 104; | |
3371 | break; | |
3372 | case bfd_mach_ppc_7400: | |
3373 | tdep->ppc_vr0_regnum = 119; | |
54c2a1e6 | 3374 | tdep->ppc_vrsave_regnum = 152; |
c8001721 EZ |
3375 | break; |
3376 | case bfd_mach_ppc_e500: | |
c8001721 | 3377 | tdep->ppc_toc_regnum = -1; |
6ced10dd JB |
3378 | tdep->ppc_ev0_upper_regnum = 32; |
3379 | tdep->ppc_ev0_regnum = 73; | |
3380 | tdep->ppc_ev31_regnum = 104; | |
3381 | tdep->ppc_acc_regnum = 71; | |
3382 | tdep->ppc_spefscr_regnum = 72; | |
383f0f5b JB |
3383 | tdep->ppc_fp0_regnum = -1; |
3384 | tdep->ppc_fpscr_regnum = -1; | |
f86a7158 | 3385 | tdep->ppc_sr0_regnum = -1; |
c8001721 EZ |
3386 | set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read); |
3387 | set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write); | |
6ced10dd | 3388 | set_gdbarch_register_reggroup_p (gdbarch, e500_register_reggroup_p); |
1fcc0bb8 | 3389 | break; |
f86a7158 JB |
3390 | |
3391 | case bfd_mach_ppc64: | |
3392 | case bfd_mach_ppc_620: | |
3393 | case bfd_mach_ppc_630: | |
3394 | case bfd_mach_ppc_a35: | |
3395 | case bfd_mach_ppc_rs64ii: | |
3396 | case bfd_mach_ppc_rs64iii: | |
3397 | /* These processor's register sets don't have segment registers. */ | |
3398 | tdep->ppc_sr0_regnum = -1; | |
3399 | break; | |
1fcc0bb8 | 3400 | } |
f86a7158 JB |
3401 | else |
3402 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 AC |
3403 | _("rs6000_gdbarch_init: " |
3404 | "received unexpected BFD 'arch' value")); | |
1fcc0bb8 | 3405 | |
e0d24f8d WZ |
3406 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
3407 | ||
338ef23d AC |
3408 | /* Sanity check on registers. */ |
3409 | gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0); | |
3410 | ||
56a6dfb9 | 3411 | /* Select instruction printer. */ |
708ff411 | 3412 | if (arch == bfd_arch_rs6000) |
9364a0ef | 3413 | set_gdbarch_print_insn (gdbarch, print_insn_rs6000); |
56a6dfb9 | 3414 | else |
9364a0ef | 3415 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc); |
7495d1dc | 3416 | |
7a78ae4e | 3417 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
7a78ae4e ND |
3418 | |
3419 | set_gdbarch_num_regs (gdbarch, v->nregs); | |
c8001721 | 3420 | set_gdbarch_num_pseudo_regs (gdbarch, v->npregs); |
7a78ae4e | 3421 | set_gdbarch_register_name (gdbarch, rs6000_register_name); |
691d145a | 3422 | set_gdbarch_register_type (gdbarch, rs6000_register_type); |
c44ca51c | 3423 | set_gdbarch_register_reggroup_p (gdbarch, rs6000_register_reggroup_p); |
7a78ae4e ND |
3424 | |
3425 | set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
3426 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
3427 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
3428 | set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
3429 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
3430 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
3431 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
ab9fe00e KB |
3432 | if (sysv_abi) |
3433 | set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); | |
3434 | else | |
3435 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4e409299 | 3436 | set_gdbarch_char_signed (gdbarch, 0); |
7a78ae4e | 3437 | |
11269d7e | 3438 | set_gdbarch_frame_align (gdbarch, rs6000_frame_align); |
8b148df9 AC |
3439 | if (sysv_abi && wordsize == 8) |
3440 | /* PPC64 SYSV. */ | |
3441 | set_gdbarch_frame_red_zone_size (gdbarch, 288); | |
3442 | else if (!sysv_abi && wordsize == 4) | |
5bffac25 AC |
3443 | /* PowerOpen / AIX 32 bit. The saved area or red zone consists of |
3444 | 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes. | |
3445 | Problem is, 220 isn't frame (16 byte) aligned. Round it up to | |
3446 | 224. */ | |
3447 | set_gdbarch_frame_red_zone_size (gdbarch, 224); | |
7a78ae4e | 3448 | |
691d145a JB |
3449 | set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p); |
3450 | set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value); | |
3451 | set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register); | |
3452 | ||
18ed0c4e JB |
3453 | set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); |
3454 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum); | |
d217aaed | 3455 | |
2ea5f656 | 3456 | if (sysv_abi && wordsize == 4) |
77b2b6d4 | 3457 | set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call); |
8be9034a AC |
3458 | else if (sysv_abi && wordsize == 8) |
3459 | set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call); | |
9aa1e687 | 3460 | else |
77b2b6d4 | 3461 | set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call); |
7a78ae4e | 3462 | |
7a78ae4e | 3463 | set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); |
0d1243d9 PG |
3464 | set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p); |
3465 | ||
7a78ae4e | 3466 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
7a78ae4e ND |
3467 | set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc); |
3468 | ||
6066c3de AC |
3469 | /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN" |
3470 | for the descriptor and ".FN" for the entry-point -- a user | |
3471 | specifying "break FN" will unexpectedly end up with a breakpoint | |
3472 | on the descriptor and not the function. This architecture method | |
3473 | transforms any breakpoints on descriptors into breakpoints on the | |
3474 | corresponding entry point. */ | |
3475 | if (sysv_abi && wordsize == 8) | |
3476 | set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address); | |
3477 | ||
7a78ae4e ND |
3478 | /* Not sure on this. FIXMEmgo */ |
3479 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
3480 | ||
15813d3f AC |
3481 | if (!sysv_abi) |
3482 | { | |
3483 | /* Handle RS/6000 function pointers (which are really function | |
3484 | descriptors). */ | |
f517ea4e PS |
3485 | set_gdbarch_convert_from_func_ptr_addr (gdbarch, |
3486 | rs6000_convert_from_func_ptr_addr); | |
9aa1e687 | 3487 | } |
7a78ae4e | 3488 | |
143985b7 AF |
3489 | /* Helpers for function argument information. */ |
3490 | set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument); | |
3491 | ||
6f7f3f0d UW |
3492 | /* Trampoline. */ |
3493 | set_gdbarch_in_solib_return_trampoline | |
3494 | (gdbarch, rs6000_in_solib_return_trampoline); | |
3495 | set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code); | |
3496 | ||
4fc771b8 DJ |
3497 | /* Hook in the DWARF CFI frame unwinder. */ |
3498 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); | |
3499 | dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum); | |
3500 | ||
7b112f9c | 3501 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4be87837 | 3502 | gdbarch_init_osabi (info, gdbarch); |
7b112f9c | 3503 | |
61a65099 KB |
3504 | switch (info.osabi) |
3505 | { | |
f5aecab8 PG |
3506 | case GDB_OSABI_LINUX: |
3507 | /* FIXME: pgilliam/2005-10-21: Assume all PowerPC 64-bit linux systems | |
3508 | have altivec registers. If not, ptrace will fail the first time it's | |
3509 | called to access one and will not be called again. This wart will | |
3510 | be removed when Daniel Jacobowitz's proposal for autodetecting target | |
3511 | registers is implemented. */ | |
3512 | if ((v->arch == bfd_arch_powerpc) && ((v->mach)== bfd_mach_ppc64)) | |
3513 | { | |
3514 | tdep->ppc_vr0_regnum = 71; | |
3515 | tdep->ppc_vrsave_regnum = 104; | |
3516 | } | |
3517 | /* Fall Thru */ | |
61a65099 KB |
3518 | case GDB_OSABI_NETBSD_AOUT: |
3519 | case GDB_OSABI_NETBSD_ELF: | |
3520 | case GDB_OSABI_UNKNOWN: | |
61a65099 KB |
3521 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); |
3522 | frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); | |
3523 | set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); | |
3524 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); | |
3525 | break; | |
3526 | default: | |
61a65099 | 3527 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
81332287 KB |
3528 | |
3529 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); | |
3530 | frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); | |
3531 | set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); | |
3532 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); | |
61a65099 KB |
3533 | } |
3534 | ||
9f643768 JB |
3535 | init_sim_regno_table (gdbarch); |
3536 | ||
7a78ae4e | 3537 | return gdbarch; |
c906108c SS |
3538 | } |
3539 | ||
7b112f9c JT |
3540 | static void |
3541 | rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
3542 | { | |
3543 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3544 | ||
3545 | if (tdep == NULL) | |
3546 | return; | |
3547 | ||
4be87837 | 3548 | /* FIXME: Dump gdbarch_tdep. */ |
7b112f9c JT |
3549 | } |
3550 | ||
c906108c SS |
3551 | /* Initialization code. */ |
3552 | ||
a78f21af | 3553 | extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */ |
b9362cc7 | 3554 | |
c906108c | 3555 | void |
fba45db2 | 3556 | _initialize_rs6000_tdep (void) |
c906108c | 3557 | { |
7b112f9c JT |
3558 | gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); |
3559 | gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); | |
c906108c | 3560 | } |