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2005-01-26 Orjan Friberg <orjanf@axis.com>
[deliverable/binutils-gdb.git] / gdb / rs6000-tdep.c
CommitLineData
c906108c 1/* Target-dependent code for GDB, the GNU debugger.
7aea86e6
AC		 2
3 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
5 Foundation, Inc.
c906108c 6
c5aa993b 7 This file is part of GDB.
c906108c 8
c5aa993b
JM		 9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
c906108c 13
c5aa993b
JM		 14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
c906108c 18
c5aa993b
JM		 19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
c906108c
SS		 23
24#include "defs.h"
25#include "frame.h"
26#include "inferior.h"
27#include "symtab.h"
28#include "target.h"
29#include "gdbcore.h"
30#include "gdbcmd.h"
c906108c 31#include "objfiles.h"
7a78ae4e 32#include "arch-utils.h"
4e052eda 33#include "regcache.h"
d195bc9f 34#include "regset.h"
d16aafd8 35#include "doublest.h"
fd0407d6 36#include "value.h"
1fcc0bb8 37#include "parser-defs.h"
4be87837 38#include "osabi.h"
7d9b040b 39#include "infcall.h"
9f643768
JB		 40#include "sim-regno.h"
41#include "gdb/sim-ppc.h"
6ced10dd 42#include "reggroups.h"
7a78ae4e 43
2fccf04a 44#include "libbfd.h" /* for bfd_default_set_arch_mach */
7a78ae4e 45#include "coff/internal.h" /* for libcoff.h */
2fccf04a 46#include "libcoff.h" /* for xcoff_data */
11ed25ac
KB		 47#include "coff/xcoff.h"
48#include "libxcoff.h"
7a78ae4e 49
9aa1e687 50#include "elf-bfd.h"
7a78ae4e 51
6ded7999 52#include "solib-svr4.h"
9aa1e687 53#include "ppc-tdep.h"
7a78ae4e 54
338ef23d 55#include "gdb_assert.h"
a89aa300 56#include "dis-asm.h"
338ef23d 57
61a65099
KB		 58#include "trad-frame.h"
59#include "frame-unwind.h"
60#include "frame-base.h"
61
7a78ae4e
ND		 62/* If the kernel has to deliver a signal, it pushes a sigcontext
63 structure on the stack and then calls the signal handler, passing
64 the address of the sigcontext in an argument register. Usually
65 the signal handler doesn't save this register, so we have to
66 access the sigcontext structure via an offset from the signal handler
67 frame.
68 The following constants were determined by experimentation on AIX 3.2. */
69#define SIG_FRAME_PC_OFFSET 96
70#define SIG_FRAME_LR_OFFSET 108
71#define SIG_FRAME_FP_OFFSET 284
72
7a78ae4e
ND		 73/* To be used by skip_prologue. */
74
75struct rs6000_framedata
76 {
77 int offset; /* total size of frame --- the distance
78 by which we decrement sp to allocate
79 the frame */
80 int saved_gpr; /* smallest # of saved gpr */
81 int saved_fpr; /* smallest # of saved fpr */
6be8bc0c 82 int saved_vr; /* smallest # of saved vr */
96ff0de4 83 int saved_ev; /* smallest # of saved ev */
7a78ae4e
ND		 84 int alloca_reg; /* alloca register number (frame ptr) */
85 char frameless; /* true if frameless functions. */
86 char nosavedpc; /* true if pc not saved. */
87 int gpr_offset; /* offset of saved gprs from prev sp */
88 int fpr_offset; /* offset of saved fprs from prev sp */
6be8bc0c 89 int vr_offset; /* offset of saved vrs from prev sp */
96ff0de4 90 int ev_offset; /* offset of saved evs from prev sp */
7a78ae4e
ND		 91 int lr_offset; /* offset of saved lr */
92 int cr_offset; /* offset of saved cr */
6be8bc0c 93 int vrsave_offset; /* offset of saved vrsave register */
7a78ae4e
ND		 94 };
95
96/* Description of a single register. */
97
98struct reg
99 {
100 char *name; /* name of register */
101 unsigned char sz32; /* size on 32-bit arch, 0 if nonextant */
102 unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */
103 unsigned char fpr; /* whether register is floating-point */
489461e2 104 unsigned char pseudo; /* whether register is pseudo */
13ac140c
JB		 105 int spr_num; /* PowerPC SPR number, or -1 if not an SPR.
106 This is an ISA SPR number, not a GDB
107 register number. */
7a78ae4e
ND		 108 };
109
c906108c
SS		 110/* Breakpoint shadows for the single step instructions will be kept here. */
111
c5aa993b
JM		 112static struct sstep_breaks
113 {
114 /* Address, or 0 if this is not in use. */
115 CORE_ADDR address;
116 /* Shadow contents. */
117 char data[4];
118 }
119stepBreaks[2];
c906108c
SS		 120
121/* Hook for determining the TOC address when calling functions in the
122 inferior under AIX. The initialization code in rs6000-nat.c sets
123 this hook to point to find_toc_address. */
124
7a78ae4e
ND		 125CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL;
126
127/* Hook to set the current architecture when starting a child process.
128 rs6000-nat.c sets this. */
129
130void (*rs6000_set_host_arch_hook) (int) = NULL;
c906108c
SS		 131
132/* Static function prototypes */
133
a14ed312
KB		 134static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc,
135 CORE_ADDR safety);
077276e8
KB		 136static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR,
137 struct rs6000_framedata *);
c906108c 138
64b84175
KB		 139/* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
140int
141altivec_register_p (int regno)
142{
143 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
144 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
145 return 0;
146 else
147 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
148}
149
383f0f5b 150
867e2dc5
JB		 151/* Return true if REGNO is an SPE register, false otherwise. */
152int
153spe_register_p (int regno)
154{
155 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
156
157 /* Is it a reference to EV0 -- EV31, and do we have those? */
158 if (tdep->ppc_ev0_regnum >= 0
159 && tdep->ppc_ev31_regnum >= 0
160 && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum)
161 return 1;
162
6ced10dd
JB		 163 /* Is it a reference to one of the raw upper GPR halves? */
164 if (tdep->ppc_ev0_upper_regnum >= 0
165 && tdep->ppc_ev0_upper_regnum <= regno
166 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
167 return 1;
168
867e2dc5
JB		 169 /* Is it a reference to the 64-bit accumulator, and do we have that? */
170 if (tdep->ppc_acc_regnum >= 0
171 && tdep->ppc_acc_regnum == regno)
172 return 1;
173
174 /* Is it a reference to the SPE floating-point status and control register,
175 and do we have that? */
176 if (tdep->ppc_spefscr_regnum >= 0
177 && tdep->ppc_spefscr_regnum == regno)
178 return 1;
179
180 return 0;
181}
182
183
383f0f5b
JB		 184/* Return non-zero if the architecture described by GDBARCH has
185 floating-point registers (f0 --- f31 and fpscr). */
0a613259
AC		 186int
187ppc_floating_point_unit_p (struct gdbarch *gdbarch)
188{
383f0f5b
JB		 189 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
190
191 return (tdep->ppc_fp0_regnum >= 0
192 && tdep->ppc_fpscr_regnum >= 0);
0a613259 193}
9f643768 194
09991fa0
JB		 195
196/* Check that TABLE[GDB_REGNO] is not already initialized, and then
197 set it to SIM_REGNO.
198
199 This is a helper function for init_sim_regno_table, constructing
200 the table mapping GDB register numbers to sim register numbers; we
201 initialize every element in that table to -1 before we start
202 filling it in. */
9f643768
JB		 203static void
204set_sim_regno (int *table, int gdb_regno, int sim_regno)
205{
206 /* Make sure we don't try to assign any given GDB register a sim
207 register number more than once. */
208 gdb_assert (table[gdb_regno] == -1);
209 table[gdb_regno] = sim_regno;
210}
211
09991fa0
JB		 212
213/* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
214 numbers to simulator register numbers, based on the values placed
215 in the ARCH->tdep->ppc_foo_regnum members. */
9f643768
JB		 216static void
217init_sim_regno_table (struct gdbarch *arch)
218{
219 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
220 int total_regs = gdbarch_num_regs (arch) + gdbarch_num_pseudo_regs (arch);
221 const struct reg *regs = tdep->regs;
222 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
223 int i;
224
225 /* Presume that all registers not explicitly mentioned below are
226 unavailable from the sim. */
227 for (i = 0; i < total_regs; i++)
228 sim_regno[i] = -1;
229
230 /* General-purpose registers. */
231 for (i = 0; i < ppc_num_gprs; i++)
232 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
233
234 /* Floating-point registers. */
235 if (tdep->ppc_fp0_regnum >= 0)
236 for (i = 0; i < ppc_num_fprs; i++)
237 set_sim_regno (sim_regno,
238 tdep->ppc_fp0_regnum + i,
239 sim_ppc_f0_regnum + i);
240 if (tdep->ppc_fpscr_regnum >= 0)
241 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
242
243 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
244 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
245 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
246
247 /* Segment registers. */
248 if (tdep->ppc_sr0_regnum >= 0)
249 for (i = 0; i < ppc_num_srs; i++)
250 set_sim_regno (sim_regno,
251 tdep->ppc_sr0_regnum + i,
252 sim_ppc_sr0_regnum + i);
253
254 /* Altivec registers. */
255 if (tdep->ppc_vr0_regnum >= 0)
256 {
257 for (i = 0; i < ppc_num_vrs; i++)
258 set_sim_regno (sim_regno,
259 tdep->ppc_vr0_regnum + i,
260 sim_ppc_vr0_regnum + i);
261
262 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
263 we can treat this more like the other cases. */
264 set_sim_regno (sim_regno,
265 tdep->ppc_vr0_regnum + ppc_num_vrs,
266 sim_ppc_vscr_regnum);
267 }
268 /* vsave is a special-purpose register, so the code below handles it. */
269
270 /* SPE APU (E500) registers. */
271 if (tdep->ppc_ev0_regnum >= 0)
272 for (i = 0; i < ppc_num_gprs; i++)
273 set_sim_regno (sim_regno,
274 tdep->ppc_ev0_regnum + i,
275 sim_ppc_ev0_regnum + i);
6ced10dd
JB		 276 if (tdep->ppc_ev0_upper_regnum >= 0)
277 for (i = 0; i < ppc_num_gprs; i++)
278 set_sim_regno (sim_regno,
279 tdep->ppc_ev0_upper_regnum + i,
280 sim_ppc_rh0_regnum + i);
9f643768
JB		 281 if (tdep->ppc_acc_regnum >= 0)
282 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
283 /* spefscr is a special-purpose register, so the code below handles it. */
284
285 /* Now handle all special-purpose registers. Verify that they
286 haven't mistakenly been assigned numbers by any of the above
287 code). */
288 for (i = 0; i < total_regs; i++)
289 if (regs[i].spr_num >= 0)
290 set_sim_regno (sim_regno, i, regs[i].spr_num + sim_ppc_spr0_regnum);
291
292 /* Drop the initialized array into place. */
293 tdep->sim_regno = sim_regno;
294}
295
09991fa0
JB		 296
297/* Given a GDB register number REG, return the corresponding SIM
298 register number. */
9f643768
JB		 299static int
300rs6000_register_sim_regno (int reg)
301{
302 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
303 int sim_regno;
304
305 gdb_assert (0 <= reg && reg <= NUM_REGS + NUM_PSEUDO_REGS);
306 sim_regno = tdep->sim_regno[reg];
307
308 if (sim_regno >= 0)
309 return sim_regno;
310 else
311 return LEGACY_SIM_REGNO_IGNORE;
312}
313
d195bc9f
MK		 314\f
315
316/* Register set support functions. */
317
318static void
319ppc_supply_reg (struct regcache *regcache, int regnum,
320 const char *regs, size_t offset)
321{
322 if (regnum != -1 && offset != -1)
323 regcache_raw_supply (regcache, regnum, regs + offset);
324}
325
326static void
327ppc_collect_reg (const struct regcache *regcache, int regnum,
328 char *regs, size_t offset)
329{
330 if (regnum != -1 && offset != -1)
331 regcache_raw_collect (regcache, regnum, regs + offset);
332}
333
334/* Supply register REGNUM in the general-purpose register set REGSET
335 from the buffer specified by GREGS and LEN to register cache
336 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
337
338void
339ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
340 int regnum, const void *gregs, size_t len)
341{
342 struct gdbarch *gdbarch = get_regcache_arch (regcache);
343 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
344 const struct ppc_reg_offsets *offsets = regset->descr;
345 size_t offset;
346 int i;
347
cdf2c5f5 348 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
063715bf 349 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
cdf2c5f5 350 i++, offset += 4)
d195bc9f
MK		 351 {
352 if (regnum == -1 || regnum == i)
353 ppc_supply_reg (regcache, i, gregs, offset);
354 }
355
356 if (regnum == -1 || regnum == PC_REGNUM)
357 ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
358 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
359 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
360 gregs, offsets->ps_offset);
361 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
362 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
363 gregs, offsets->cr_offset);
364 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
365 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
366 gregs, offsets->lr_offset);
367 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
368 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
369 gregs, offsets->ctr_offset);
370 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
371 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
372 gregs, offsets->cr_offset);
373 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
374 ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset);
375}
376
377/* Supply register REGNUM in the floating-point register set REGSET
378 from the buffer specified by FPREGS and LEN to register cache
379 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
380
381void
382ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
383 int regnum, const void *fpregs, size_t len)
384{
385 struct gdbarch *gdbarch = get_regcache_arch (regcache);
386 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
387 const struct ppc_reg_offsets *offsets = regset->descr;
388 size_t offset;
389 int i;
390
383f0f5b
JB		 391 gdb_assert (ppc_floating_point_unit_p (gdbarch));
392
d195bc9f 393 offset = offsets->f0_offset;
366f009f
JB		 394 for (i = tdep->ppc_fp0_regnum;
395 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
396 i++, offset += 4)
d195bc9f
MK		 397 {
398 if (regnum == -1 || regnum == i)
399 ppc_supply_reg (regcache, i, fpregs, offset);
400 }
401
402 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
403 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
404 fpregs, offsets->fpscr_offset);
405}
406
407/* Collect register REGNUM in the general-purpose register set
408 REGSET. from register cache REGCACHE into the buffer specified by
409 GREGS and LEN. If REGNUM is -1, do this for all registers in
410 REGSET. */
411
412void
413ppc_collect_gregset (const struct regset *regset,
414 const struct regcache *regcache,
415 int regnum, void *gregs, size_t len)
416{
417 struct gdbarch *gdbarch = get_regcache_arch (regcache);
418 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
419 const struct ppc_reg_offsets *offsets = regset->descr;
420 size_t offset;
421 int i;
422
423 offset = offsets->r0_offset;
cdf2c5f5 424 for (i = tdep->ppc_gp0_regnum;
063715bf 425 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
cdf2c5f5 426 i++, offset += 4)
d195bc9f
MK		 427 {
428 if (regnum == -1 || regnum == i)
2e56e9c1 429 ppc_collect_reg (regcache, i, gregs, offset);
d195bc9f
MK		 430 }
431
432 if (regnum == -1 || regnum == PC_REGNUM)
433 ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
434 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
435 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
436 gregs, offsets->ps_offset);
437 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
438 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
439 gregs, offsets->cr_offset);
440 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
441 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
442 gregs, offsets->lr_offset);
443 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
444 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
445 gregs, offsets->ctr_offset);
446 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
447 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
448 gregs, offsets->xer_offset);
449 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
450 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
451 gregs, offsets->mq_offset);
452}
453
454/* Collect register REGNUM in the floating-point register set
455 REGSET. from register cache REGCACHE into the buffer specified by
456 FPREGS and LEN. If REGNUM is -1, do this for all registers in
457 REGSET. */
458
459void
460ppc_collect_fpregset (const struct regset *regset,
461 const struct regcache *regcache,
462 int regnum, void *fpregs, size_t len)
463{
464 struct gdbarch *gdbarch = get_regcache_arch (regcache);
465 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
466 const struct ppc_reg_offsets *offsets = regset->descr;
467 size_t offset;
468 int i;
469
383f0f5b
JB		 470 gdb_assert (ppc_floating_point_unit_p (gdbarch));
471
d195bc9f 472 offset = offsets->f0_offset;
366f009f
JB		 473 for (i = tdep->ppc_fp0_regnum;
474 i <= tdep->ppc_fp0_regnum + ppc_num_fprs;
475 i++, offset += 4)
d195bc9f
MK		 476 {
477 if (regnum == -1 || regnum == i)
478 ppc_collect_reg (regcache, regnum, fpregs, offset);
479 }
480
481 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
482 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
483 fpregs, offsets->fpscr_offset);
484}
485\f
0a613259 486
7a78ae4e 487/* Read a LEN-byte address from debugged memory address MEMADDR. */
c906108c 488
7a78ae4e
ND		 489static CORE_ADDR
490read_memory_addr (CORE_ADDR memaddr, int len)
491{
492 return read_memory_unsigned_integer (memaddr, len);
493}
c906108c 494
7a78ae4e
ND		 495static CORE_ADDR
496rs6000_skip_prologue (CORE_ADDR pc)
b83266a0
SS		 497{
498 struct rs6000_framedata frame;
077276e8 499 pc = skip_prologue (pc, 0, &frame);
b83266a0
SS		 500 return pc;
501}
502
503
c906108c
SS		 504/* Fill in fi->saved_regs */
505
506struct frame_extra_info
507{
508 /* Functions calling alloca() change the value of the stack
509 pointer. We need to use initial stack pointer (which is saved in
510 r31 by gcc) in such cases. If a compiler emits traceback table,
511 then we should use the alloca register specified in traceback
512 table. FIXME. */
c5aa993b 513 CORE_ADDR initial_sp; /* initial stack pointer. */
c906108c
SS		 514};
515
143985b7 516/* Get the ith function argument for the current function. */
b9362cc7 517static CORE_ADDR
143985b7
AF		 518rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
519 struct type *type)
520{
521 CORE_ADDR addr;
7f5f525d 522 get_frame_register (frame, 3 + argi, &addr);
143985b7
AF		 523 return addr;
524}
525
c906108c
SS		 526/* Calculate the destination of a branch/jump. Return -1 if not a branch. */
527
528static CORE_ADDR
7a78ae4e 529branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety)
c906108c
SS		 530{
531 CORE_ADDR dest;
532 int immediate;
533 int absolute;
534 int ext_op;
535
536 absolute = (int) ((instr >> 1) & 1);
537
c5aa993b
JM		 538 switch (opcode)
539 {
540 case 18:
541 immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */
542 if (absolute)
543 dest = immediate;
544 else
545 dest = pc + immediate;
546 break;
547
548 case 16:
549 immediate = ((instr & ~3) << 16) >> 16; /* br conditional */
550 if (absolute)
551 dest = immediate;
552 else
553 dest = pc + immediate;
554 break;
555
556 case 19:
557 ext_op = (instr >> 1) & 0x3ff;
558
559 if (ext_op == 16) /* br conditional register */
560 {
2188cbdd 561 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
c5aa993b
JM		 562
563 /* If we are about to return from a signal handler, dest is
564 something like 0x3c90. The current frame is a signal handler
565 caller frame, upon completion of the sigreturn system call
566 execution will return to the saved PC in the frame. */
567 if (dest < TEXT_SEGMENT_BASE)
568 {
569 struct frame_info *fi;
570
571 fi = get_current_frame ();
572 if (fi != NULL)
8b36eed8 573 dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET,
21283beb 574 gdbarch_tdep (current_gdbarch)->wordsize);
c5aa993b
JM		 575 }
576 }
577
578 else if (ext_op == 528) /* br cond to count reg */
579 {
2188cbdd 580 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3;
c5aa993b
JM		 581
582 /* If we are about to execute a system call, dest is something
583 like 0x22fc or 0x3b00. Upon completion the system call
584 will return to the address in the link register. */
585 if (dest < TEXT_SEGMENT_BASE)
2188cbdd 586 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
c5aa993b
JM		 587 }
588 else
589 return -1;
590 break;
c906108c 591
c5aa993b
JM		 592 default:
593 return -1;
594 }
c906108c
SS		 595 return (dest < TEXT_SEGMENT_BASE) ? safety : dest;
596}
597
598
599/* Sequence of bytes for breakpoint instruction. */
600
f4f9705a 601const static unsigned char *
7a78ae4e 602rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
c906108c 603{
aaab4dba
AC		 604 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
605 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
c906108c 606 *bp_size = 4;
d7449b42 607 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
c906108c
SS		 608 return big_breakpoint;
609 else
610 return little_breakpoint;
611}
612
613
614/* AIX does not support PT_STEP. Simulate it. */
615
616void
379d08a1
AC		 617rs6000_software_single_step (enum target_signal signal,
618 int insert_breakpoints_p)
c906108c 619{
7c40d541
KB		 620 CORE_ADDR dummy;
621 int breakp_sz;
f4f9705a 622 const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz);
c906108c
SS		 623 int ii, insn;
624 CORE_ADDR loc;
625 CORE_ADDR breaks[2];
626 int opcode;
627
c5aa993b
JM		 628 if (insert_breakpoints_p)
629 {
c906108c 630
c5aa993b 631 loc = read_pc ();
c906108c 632
c5aa993b 633 insn = read_memory_integer (loc, 4);
c906108c 634
7c40d541 635 breaks[0] = loc + breakp_sz;
c5aa993b
JM		 636 opcode = insn >> 26;
637 breaks[1] = branch_dest (opcode, insn, loc, breaks[0]);
c906108c 638
c5aa993b
JM		 639 /* Don't put two breakpoints on the same address. */
640 if (breaks[1] == breaks[0])
641 breaks[1] = -1;
c906108c 642
c5aa993b 643 stepBreaks[1].address = 0;
c906108c 644
c5aa993b
JM		 645 for (ii = 0; ii < 2; ++ii)
646 {
c906108c 647
c5aa993b
JM		 648 /* ignore invalid breakpoint. */
649 if (breaks[ii] == -1)
650 continue;
7c40d541 651 target_insert_breakpoint (breaks[ii], stepBreaks[ii].data);
c5aa993b
JM		 652 stepBreaks[ii].address = breaks[ii];
653 }
c906108c 654
c5aa993b
JM		 655 }
656 else
657 {
c906108c 658
c5aa993b
JM		 659 /* remove step breakpoints. */
660 for (ii = 0; ii < 2; ++ii)
661 if (stepBreaks[ii].address != 0)
7c40d541
KB		 662 target_remove_breakpoint (stepBreaks[ii].address,
663 stepBreaks[ii].data);
c5aa993b 664 }
c906108c 665 errno = 0; /* FIXME, don't ignore errors! */
c5aa993b 666 /* What errors? {read,write}_memory call error(). */
c906108c
SS		 667}
668
669
670/* return pc value after skipping a function prologue and also return
671 information about a function frame.
672
673 in struct rs6000_framedata fdata:
c5aa993b
JM		 674 - frameless is TRUE, if function does not have a frame.
675 - nosavedpc is TRUE, if function does not save %pc value in its frame.
676 - offset is the initial size of this stack frame --- the amount by
677 which we decrement the sp to allocate the frame.
678 - saved_gpr is the number of the first saved gpr.
679 - saved_fpr is the number of the first saved fpr.
6be8bc0c 680 - saved_vr is the number of the first saved vr.
96ff0de4 681 - saved_ev is the number of the first saved ev.
c5aa993b
JM		 682 - alloca_reg is the number of the register used for alloca() handling.
683 Otherwise -1.
684 - gpr_offset is the offset of the first saved gpr from the previous frame.
685 - fpr_offset is the offset of the first saved fpr from the previous frame.
6be8bc0c 686 - vr_offset is the offset of the first saved vr from the previous frame.
96ff0de4 687 - ev_offset is the offset of the first saved ev from the previous frame.
c5aa993b
JM		 688 - lr_offset is the offset of the saved lr
689 - cr_offset is the offset of the saved cr
6be8bc0c 690 - vrsave_offset is the offset of the saved vrsave register
c5aa993b 691 */
c906108c
SS		 692
693#define SIGNED_SHORT(x) \
694 ((sizeof (short) == 2) \
695 ? ((int)(short)(x)) \
696 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
697
698#define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
699
55d05f3b
KB		 700/* Limit the number of skipped non-prologue instructions, as the examining
701 of the prologue is expensive. */
702static int max_skip_non_prologue_insns = 10;
703
704/* Given PC representing the starting address of a function, and
705 LIM_PC which is the (sloppy) limit to which to scan when looking
706 for a prologue, attempt to further refine this limit by using
707 the line data in the symbol table. If successful, a better guess
708 on where the prologue ends is returned, otherwise the previous
709 value of lim_pc is returned. */
634aa483
AC		 710
711/* FIXME: cagney/2004-02-14: This function and logic have largely been
712 superseded by skip_prologue_using_sal. */
713
55d05f3b
KB		 714static CORE_ADDR
715refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc)
716{
717 struct symtab_and_line prologue_sal;
718
719 prologue_sal = find_pc_line (pc, 0);
720 if (prologue_sal.line != 0)
721 {
722 int i;
723 CORE_ADDR addr = prologue_sal.end;
724
725 /* Handle the case in which compiler's optimizer/scheduler
726 has moved instructions into the prologue. We scan ahead
727 in the function looking for address ranges whose corresponding
728 line number is less than or equal to the first one that we
729 found for the function. (It can be less than when the
730 scheduler puts a body instruction before the first prologue
731 instruction.) */
732 for (i = 2 * max_skip_non_prologue_insns;
733 i > 0 && (lim_pc == 0 || addr < lim_pc);
734 i--)
735 {
736 struct symtab_and_line sal;
737
738 sal = find_pc_line (addr, 0);
739 if (sal.line == 0)
740 break;
741 if (sal.line <= prologue_sal.line
742 && sal.symtab == prologue_sal.symtab)
743 {
744 prologue_sal = sal;
745 }
746 addr = sal.end;
747 }
748
749 if (lim_pc == 0 || prologue_sal.end < lim_pc)
750 lim_pc = prologue_sal.end;
751 }
752 return lim_pc;
753}
754
773df3e5
JB		 755/* Return nonzero if the given instruction OP can be part of the prologue
756 of a function and saves a parameter on the stack. FRAMEP should be
757 set if one of the previous instructions in the function has set the
758 Frame Pointer. */
759
760static int
761store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
762{
763 /* Move parameters from argument registers to temporary register. */
764 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
765 {
766 /* Rx must be scratch register r0. */
767 const int rx_regno = (op >> 16) & 31;
768 /* Ry: Only r3 - r10 are used for parameter passing. */
769 const int ry_regno = GET_SRC_REG (op);
770
771 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
772 {
773 *r0_contains_arg = 1;
774 return 1;
775 }
776 else
777 return 0;
778 }
779
780 /* Save a General Purpose Register on stack. */
781
782 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
783 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
784 {
785 /* Rx: Only r3 - r10 are used for parameter passing. */
786 const int rx_regno = GET_SRC_REG (op);
787
788 return (rx_regno >= 3 && rx_regno <= 10);
789 }
790
791 /* Save a General Purpose Register on stack via the Frame Pointer. */
792
793 if (framep &&
794 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
795 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
796 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
797 {
798 /* Rx: Usually, only r3 - r10 are used for parameter passing.
799 However, the compiler sometimes uses r0 to hold an argument. */
800 const int rx_regno = GET_SRC_REG (op);
801
802 return ((rx_regno >= 3 && rx_regno <= 10)
803 || (rx_regno == 0 && *r0_contains_arg));
804 }
805
806 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
807 {
808 /* Only f2 - f8 are used for parameter passing. */
809 const int src_regno = GET_SRC_REG (op);
810
811 return (src_regno >= 2 && src_regno <= 8);
812 }
813
814 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
815 {
816 /* Only f2 - f8 are used for parameter passing. */
817 const int src_regno = GET_SRC_REG (op);
818
819 return (src_regno >= 2 && src_regno <= 8);
820 }
821
822 /* Not an insn that saves a parameter on stack. */
823 return 0;
824}
55d05f3b 825
7a78ae4e 826static CORE_ADDR
077276e8 827skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata)
c906108c
SS		 828{
829 CORE_ADDR orig_pc = pc;
55d05f3b 830 CORE_ADDR last_prologue_pc = pc;
6be8bc0c 831 CORE_ADDR li_found_pc = 0;
c906108c
SS		 832 char buf[4];
833 unsigned long op;
834 long offset = 0;
6be8bc0c 835 long vr_saved_offset = 0;
482ca3f5
KB		 836 int lr_reg = -1;
837 int cr_reg = -1;
6be8bc0c 838 int vr_reg = -1;
96ff0de4
EZ		 839 int ev_reg = -1;
840 long ev_offset = 0;
6be8bc0c 841 int vrsave_reg = -1;
c906108c
SS		 842 int reg;
843 int framep = 0;
844 int minimal_toc_loaded = 0;
ddb20c56 845 int prev_insn_was_prologue_insn = 1;
55d05f3b 846 int num_skip_non_prologue_insns = 0;
773df3e5 847 int r0_contains_arg = 0;
96ff0de4 848 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch);
6f99cb26 849 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
96ff0de4 850
55d05f3b
KB		 851 /* Attempt to find the end of the prologue when no limit is specified.
852 Note that refine_prologue_limit() has been written so that it may
853 be used to "refine" the limits of non-zero PC values too, but this
854 is only safe if we 1) trust the line information provided by the
855 compiler and 2) iterate enough to actually find the end of the
856 prologue.
857
858 It may become a good idea at some point (for both performance and
859 accuracy) to unconditionally call refine_prologue_limit(). But,
860 until we can make a clear determination that this is beneficial,
861 we'll play it safe and only use it to obtain a limit when none
862 has been specified. */
863 if (lim_pc == 0)
864 lim_pc = refine_prologue_limit (pc, lim_pc);
c906108c 865
ddb20c56 866 memset (fdata, 0, sizeof (struct rs6000_framedata));
c906108c
SS		 867 fdata->saved_gpr = -1;
868 fdata->saved_fpr = -1;
6be8bc0c 869 fdata->saved_vr = -1;
96ff0de4 870 fdata->saved_ev = -1;
c906108c
SS		 871 fdata->alloca_reg = -1;
872 fdata->frameless = 1;
873 fdata->nosavedpc = 1;
874
55d05f3b 875 for (;; pc += 4)
c906108c 876 {
ddb20c56
KB		 877 /* Sometimes it isn't clear if an instruction is a prologue
878 instruction or not. When we encounter one of these ambiguous
879 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
880 Otherwise, we'll assume that it really is a prologue instruction. */
881 if (prev_insn_was_prologue_insn)
882 last_prologue_pc = pc;
55d05f3b
KB		 883
884 /* Stop scanning if we've hit the limit. */
885 if (lim_pc != 0 && pc >= lim_pc)
886 break;
887
ddb20c56
KB		 888 prev_insn_was_prologue_insn = 1;
889
55d05f3b 890 /* Fetch the instruction and convert it to an integer. */
ddb20c56
KB		 891 if (target_read_memory (pc, buf, 4))
892 break;
893 op = extract_signed_integer (buf, 4);
c906108c 894
c5aa993b
JM		 895 if ((op & 0xfc1fffff) == 0x7c0802a6)
896 { /* mflr Rx */
43b1ab88
AC		 897 /* Since shared library / PIC code, which needs to get its
898 address at runtime, can appear to save more than one link
899 register vis:
900
901 *INDENT-OFF*
902 stwu r1,-304(r1)
903 mflr r3
904 bl 0xff570d0 (blrl)
905 stw r30,296(r1)
906 mflr r30
907 stw r31,300(r1)
908 stw r3,308(r1);
909 ...
910 *INDENT-ON*
911
912 remember just the first one, but skip over additional
913 ones. */
914 if (lr_reg < 0)
915 lr_reg = (op & 0x03e00000);
773df3e5
JB		 916 if (lr_reg == 0)
917 r0_contains_arg = 0;
c5aa993b 918 continue;
c5aa993b
JM		 919 }
920 else if ((op & 0xfc1fffff) == 0x7c000026)
921 { /* mfcr Rx */
98f08d3d 922 cr_reg = (op & 0x03e00000);
773df3e5
JB		 923 if (cr_reg == 0)
924 r0_contains_arg = 0;
c5aa993b 925 continue;
c906108c 926
c906108c 927 }
c5aa993b
JM		 928 else if ((op & 0xfc1f0000) == 0xd8010000)
929 { /* stfd Rx,NUM(r1) */
930 reg = GET_SRC_REG (op);
931 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
932 {
933 fdata->saved_fpr = reg;
934 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
935 }
936 continue;
c906108c 937
c5aa993b
JM		 938 }
939 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
7a78ae4e
ND		 940 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
941 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
942 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
c5aa993b
JM		 943 {
944
945 reg = GET_SRC_REG (op);
946 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
947 {
948 fdata->saved_gpr = reg;
7a78ae4e 949 if ((op & 0xfc1f0003) == 0xf8010000)
98f08d3d 950 op &= ~3UL;
c5aa993b
JM		 951 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
952 }
953 continue;
c906108c 954
ddb20c56
KB		 955 }
956 else if ((op & 0xffff0000) == 0x60000000)
957 {
96ff0de4 958 /* nop */
ddb20c56
KB		 959 /* Allow nops in the prologue, but do not consider them to
960 be part of the prologue unless followed by other prologue
961 instructions. */
962 prev_insn_was_prologue_insn = 0;
963 continue;
964
c906108c 965 }
c5aa993b
JM		 966 else if ((op & 0xffff0000) == 0x3c000000)
967 { /* addis 0,0,NUM, used
968 for >= 32k frames */
969 fdata->offset = (op & 0x0000ffff) << 16;
970 fdata->frameless = 0;
773df3e5 971 r0_contains_arg = 0;
c5aa993b
JM		 972 continue;
973
974 }
975 else if ((op & 0xffff0000) == 0x60000000)
976 { /* ori 0,0,NUM, 2nd ha
977 lf of >= 32k frames */
978 fdata->offset |= (op & 0x0000ffff);
979 fdata->frameless = 0;
773df3e5 980 r0_contains_arg = 0;
c5aa993b
JM		 981 continue;
982
983 }
be723e22 984 else if (lr_reg >= 0 &&
98f08d3d
KB		 985 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
986 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
987 /* stw Rx, NUM(r1) */
988 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
989 /* stwu Rx, NUM(r1) */
990 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
991 { /* where Rx == lr */
992 fdata->lr_offset = offset;
c5aa993b 993 fdata->nosavedpc = 0;
be723e22
MS		 994 /* Invalidate lr_reg, but don't set it to -1.
995 That would mean that it had never been set. */
996 lr_reg = -2;
98f08d3d
KB		 997 if ((op & 0xfc000003) == 0xf8000000 || /* std */
998 (op & 0xfc000000) == 0x90000000) /* stw */
999 {
1000 /* Does not update r1, so add displacement to lr_offset. */
1001 fdata->lr_offset += SIGNED_SHORT (op);
1002 }
c5aa993b
JM		 1003 continue;
1004
1005 }
be723e22 1006 else if (cr_reg >= 0 &&
98f08d3d
KB		 1007 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1008 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1009 /* stw Rx, NUM(r1) */
1010 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1011 /* stwu Rx, NUM(r1) */
1012 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1013 { /* where Rx == cr */
1014 fdata->cr_offset = offset;
be723e22
MS		 1015 /* Invalidate cr_reg, but don't set it to -1.
1016 That would mean that it had never been set. */
1017 cr_reg = -2;
98f08d3d
KB		 1018 if ((op & 0xfc000003) == 0xf8000000 ||
1019 (op & 0xfc000000) == 0x90000000)
1020 {
1021 /* Does not update r1, so add displacement to cr_offset. */
1022 fdata->cr_offset += SIGNED_SHORT (op);
1023 }
c5aa993b
JM		 1024 continue;
1025
1026 }
1027 else if (op == 0x48000005)
1028 { /* bl .+4 used in
1029 -mrelocatable */
1030 continue;
1031
1032 }
1033 else if (op == 0x48000004)
1034 { /* b .+4 (xlc) */
1035 break;
1036
c5aa993b 1037 }
6be8bc0c
EZ		 1038 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1039 in V.4 -mminimal-toc */
c5aa993b
JM		 1040 (op & 0xffff0000) == 0x3bde0000)
1041 { /* addi 30,30,foo@l */
1042 continue;
c906108c 1043
c5aa993b
JM		 1044 }
1045 else if ((op & 0xfc000001) == 0x48000001)
1046 { /* bl foo,
1047 to save fprs??? */
c906108c 1048
c5aa993b 1049 fdata->frameless = 0;
6be8bc0c 1050 /* Don't skip over the subroutine call if it is not within
ebd98106
FF		 1051 the first three instructions of the prologue and either
1052 we have no line table information or the line info tells
1053 us that the subroutine call is not part of the line
1054 associated with the prologue. */
c5aa993b 1055 if ((pc - orig_pc) > 8)
ebd98106
FF		 1056 {
1057 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1058 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1059
1060 if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line))
1061 break;
1062 }
c5aa993b
JM		 1063
1064 op = read_memory_integer (pc + 4, 4);
1065
6be8bc0c
EZ		 1066 /* At this point, make sure this is not a trampoline
1067 function (a function that simply calls another functions,
1068 and nothing else). If the next is not a nop, this branch
1069 was part of the function prologue. */
c5aa993b
JM		 1070
1071 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1072 break; /* don't skip over
1073 this branch */
1074 continue;
1075
c5aa993b 1076 }
98f08d3d
KB		 1077 /* update stack pointer */
1078 else if ((op & 0xfc1f0000) == 0x94010000)
1079 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
c5aa993b
JM		 1080 fdata->frameless = 0;
1081 fdata->offset = SIGNED_SHORT (op);
1082 offset = fdata->offset;
1083 continue;
c5aa993b 1084 }
98f08d3d
KB		 1085 else if ((op & 0xfc1f016a) == 0x7c01016e)
1086 { /* stwux rX,r1,rY */
1087 /* no way to figure out what r1 is going to be */
1088 fdata->frameless = 0;
1089 offset = fdata->offset;
1090 continue;
1091 }
1092 else if ((op & 0xfc1f0003) == 0xf8010001)
1093 { /* stdu rX,NUM(r1) */
1094 fdata->frameless = 0;
1095 fdata->offset = SIGNED_SHORT (op & ~3UL);
1096 offset = fdata->offset;
1097 continue;
1098 }
1099 else if ((op & 0xfc1f016a) == 0x7c01016a)
1100 { /* stdux rX,r1,rY */
1101 /* no way to figure out what r1 is going to be */
c5aa993b
JM		 1102 fdata->frameless = 0;
1103 offset = fdata->offset;
1104 continue;
c5aa993b 1105 }
98f08d3d
KB		 1106 /* Load up minimal toc pointer */
1107 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1108 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
c5aa993b 1109 && !minimal_toc_loaded)
98f08d3d 1110 {
c5aa993b
JM		 1111 minimal_toc_loaded = 1;
1112 continue;
1113
f6077098
KB		 1114 /* move parameters from argument registers to local variable
1115 registers */
1116 }
1117 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1118 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1119 (((op >> 21) & 31) <= 10) &&
96ff0de4 1120 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
f6077098
KB		 1121 {
1122 continue;
1123
c5aa993b
JM		 1124 /* store parameters in stack */
1125 }
e802b915 1126 /* Move parameters from argument registers to temporary register. */
773df3e5 1127 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
e802b915 1128 {
c5aa993b
JM		 1129 continue;
1130
1131 /* Set up frame pointer */
1132 }
1133 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1134 || op == 0x7c3f0b78)
1135 { /* mr r31, r1 */
1136 fdata->frameless = 0;
1137 framep = 1;
6f99cb26 1138 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
c5aa993b
JM		 1139 continue;
1140
1141 /* Another way to set up the frame pointer. */
1142 }
1143 else if ((op & 0xfc1fffff) == 0x38010000)
1144 { /* addi rX, r1, 0x0 */
1145 fdata->frameless = 0;
1146 framep = 1;
6f99cb26
AC		 1147 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1148 + ((op & ~0x38010000) >> 21));
c5aa993b 1149 continue;
c5aa993b 1150 }
6be8bc0c
EZ		 1151 /* AltiVec related instructions. */
1152 /* Store the vrsave register (spr 256) in another register for
1153 later manipulation, or load a register into the vrsave
1154 register. 2 instructions are used: mfvrsave and
1155 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1156 and mtspr SPR256, Rn. */
1157 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1158 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1159 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1160 {
1161 vrsave_reg = GET_SRC_REG (op);
1162 continue;
1163 }
1164 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1165 {
1166 continue;
1167 }
1168 /* Store the register where vrsave was saved to onto the stack:
1169 rS is the register where vrsave was stored in a previous
1170 instruction. */
1171 /* 100100 sssss 00001 dddddddd dddddddd */
1172 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1173 {
1174 if (vrsave_reg == GET_SRC_REG (op))
1175 {
1176 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1177 vrsave_reg = -1;
1178 }
1179 continue;
1180 }
1181 /* Compute the new value of vrsave, by modifying the register
1182 where vrsave was saved to. */
1183 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1184 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1185 {
1186 continue;
1187 }
1188 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1189 in a pair of insns to save the vector registers on the
1190 stack. */
1191 /* 001110 00000 00000 iiii iiii iiii iiii */
96ff0de4
EZ		 1192 /* 001110 01110 00000 iiii iiii iiii iiii */
1193 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1194 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
6be8bc0c 1195 {
773df3e5
JB		 1196 if ((op & 0xffff0000) == 0x38000000)
1197 r0_contains_arg = 0;
6be8bc0c
EZ		 1198 li_found_pc = pc;
1199 vr_saved_offset = SIGNED_SHORT (op);
773df3e5
JB		 1200
1201 /* This insn by itself is not part of the prologue, unless
1202 if part of the pair of insns mentioned above. So do not
1203 record this insn as part of the prologue yet. */
1204 prev_insn_was_prologue_insn = 0;
6be8bc0c
EZ		 1205 }
1206 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1207 /* 011111 sssss 11111 00000 00111001110 */
1208 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1209 {
1210 if (pc == (li_found_pc + 4))
1211 {
1212 vr_reg = GET_SRC_REG (op);
1213 /* If this is the first vector reg to be saved, or if
1214 it has a lower number than others previously seen,
1215 reupdate the frame info. */
1216 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1217 {
1218 fdata->saved_vr = vr_reg;
1219 fdata->vr_offset = vr_saved_offset + offset;
1220 }
1221 vr_saved_offset = -1;
1222 vr_reg = -1;
1223 li_found_pc = 0;
1224 }
1225 }
1226 /* End AltiVec related instructions. */
96ff0de4
EZ		 1227
1228 /* Start BookE related instructions. */
1229 /* Store gen register S at (r31+uimm).
1230 Any register less than r13 is volatile, so we don't care. */
1231 /* 000100 sssss 11111 iiiii 01100100001 */
1232 else if (arch_info->mach == bfd_mach_ppc_e500
1233 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1234 {
1235 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1236 {
1237 unsigned int imm;
1238 ev_reg = GET_SRC_REG (op);
1239 imm = (op >> 11) & 0x1f;
1240 ev_offset = imm * 8;
1241 /* If this is the first vector reg to be saved, or if
1242 it has a lower number than others previously seen,
1243 reupdate the frame info. */
1244 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1245 {
1246 fdata->saved_ev = ev_reg;
1247 fdata->ev_offset = ev_offset + offset;
1248 }
1249 }
1250 continue;
1251 }
1252 /* Store gen register rS at (r1+rB). */
1253 /* 000100 sssss 00001 bbbbb 01100100000 */
1254 else if (arch_info->mach == bfd_mach_ppc_e500
1255 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1256 {
1257 if (pc == (li_found_pc + 4))
1258 {
1259 ev_reg = GET_SRC_REG (op);
1260 /* If this is the first vector reg to be saved, or if
1261 it has a lower number than others previously seen,
1262 reupdate the frame info. */
1263 /* We know the contents of rB from the previous instruction. */
1264 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1265 {
1266 fdata->saved_ev = ev_reg;
1267 fdata->ev_offset = vr_saved_offset + offset;
1268 }
1269 vr_saved_offset = -1;
1270 ev_reg = -1;
1271 li_found_pc = 0;
1272 }
1273 continue;
1274 }
1275 /* Store gen register r31 at (rA+uimm). */
1276 /* 000100 11111 aaaaa iiiii 01100100001 */
1277 else if (arch_info->mach == bfd_mach_ppc_e500
1278 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1279 {
1280 /* Wwe know that the source register is 31 already, but
1281 it can't hurt to compute it. */
1282 ev_reg = GET_SRC_REG (op);
1283 ev_offset = ((op >> 11) & 0x1f) * 8;
1284 /* If this is the first vector reg to be saved, or if
1285 it has a lower number than others previously seen,
1286 reupdate the frame info. */
1287 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1288 {
1289 fdata->saved_ev = ev_reg;
1290 fdata->ev_offset = ev_offset + offset;
1291 }
1292
1293 continue;
1294 }
1295 /* Store gen register S at (r31+r0).
1296 Store param on stack when offset from SP bigger than 4 bytes. */
1297 /* 000100 sssss 11111 00000 01100100000 */
1298 else if (arch_info->mach == bfd_mach_ppc_e500
1299 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1300 {
1301 if (pc == (li_found_pc + 4))
1302 {
1303 if ((op & 0x03e00000) >= 0x01a00000)
1304 {
1305 ev_reg = GET_SRC_REG (op);
1306 /* If this is the first vector reg to be saved, or if
1307 it has a lower number than others previously seen,
1308 reupdate the frame info. */
1309 /* We know the contents of r0 from the previous
1310 instruction. */
1311 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1312 {
1313 fdata->saved_ev = ev_reg;
1314 fdata->ev_offset = vr_saved_offset + offset;
1315 }
1316 ev_reg = -1;
1317 }
1318 vr_saved_offset = -1;
1319 li_found_pc = 0;
1320 continue;
1321 }
1322 }
1323 /* End BookE related instructions. */
1324
c5aa993b
JM		 1325 else
1326 {
55d05f3b
KB		 1327 /* Not a recognized prologue instruction.
1328 Handle optimizer code motions into the prologue by continuing
1329 the search if we have no valid frame yet or if the return
1330 address is not yet saved in the frame. */
1331 if (fdata->frameless == 0
1332 && (lr_reg == -1 || fdata->nosavedpc == 0))
1333 break;
1334
1335 if (op == 0x4e800020 /* blr */
1336 || op == 0x4e800420) /* bctr */
1337 /* Do not scan past epilogue in frameless functions or
1338 trampolines. */
1339 break;
1340 if ((op & 0xf4000000) == 0x40000000) /* bxx */
64366f1c 1341 /* Never skip branches. */
55d05f3b
KB		 1342 break;
1343
1344 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
1345 /* Do not scan too many insns, scanning insns is expensive with
1346 remote targets. */
1347 break;
1348
1349 /* Continue scanning. */
1350 prev_insn_was_prologue_insn = 0;
1351 continue;
c5aa993b 1352 }
c906108c
SS		 1353 }
1354
1355#if 0
1356/* I have problems with skipping over __main() that I need to address
1357 * sometime. Previously, I used to use misc_function_vector which
1358 * didn't work as well as I wanted to be. -MGO */
1359
1360 /* If the first thing after skipping a prolog is a branch to a function,
1361 this might be a call to an initializer in main(), introduced by gcc2.
64366f1c 1362 We'd like to skip over it as well. Fortunately, xlc does some extra
c906108c 1363 work before calling a function right after a prologue, thus we can
64366f1c 1364 single out such gcc2 behaviour. */
c906108c 1365
c906108c 1366
c5aa993b
JM		 1367 if ((op & 0xfc000001) == 0x48000001)
1368 { /* bl foo, an initializer function? */
1369 op = read_memory_integer (pc + 4, 4);
1370
1371 if (op == 0x4def7b82)
1372 { /* cror 0xf, 0xf, 0xf (nop) */
c906108c 1373
64366f1c
EZ		 1374 /* Check and see if we are in main. If so, skip over this
1375 initializer function as well. */
c906108c 1376
c5aa993b 1377 tmp = find_pc_misc_function (pc);
6314a349
AC		 1378 if (tmp >= 0
1379 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
c5aa993b
JM		 1380 return pc + 8;
1381 }
c906108c 1382 }
c906108c 1383#endif /* 0 */
c5aa993b
JM		 1384
1385 fdata->offset = -fdata->offset;
ddb20c56 1386 return last_prologue_pc;
c906108c
SS		 1387}
1388
1389
1390/*************************************************************************
f6077098 1391 Support for creating pushing a dummy frame into the stack, and popping
c906108c
SS		 1392 frames, etc.
1393*************************************************************************/
1394
c906108c 1395
11269d7e
AC		 1396/* All the ABI's require 16 byte alignment. */
1397static CORE_ADDR
1398rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
1399{
1400 return (addr & -16);
1401}
1402
7a78ae4e 1403/* Pass the arguments in either registers, or in the stack. In RS/6000,
c906108c
SS		 1404 the first eight words of the argument list (that might be less than
1405 eight parameters if some parameters occupy more than one word) are
7a78ae4e 1406 passed in r3..r10 registers. float and double parameters are
64366f1c
EZ		 1407 passed in fpr's, in addition to that. Rest of the parameters if any
1408 are passed in user stack. There might be cases in which half of the
c906108c
SS		 1409 parameter is copied into registers, the other half is pushed into
1410 stack.
1411
7a78ae4e
ND		 1412 Stack must be aligned on 64-bit boundaries when synthesizing
1413 function calls.
1414
c906108c
SS		 1415 If the function is returning a structure, then the return address is passed
1416 in r3, then the first 7 words of the parameters can be passed in registers,
64366f1c 1417 starting from r4. */
c906108c 1418
7a78ae4e 1419static CORE_ADDR
7d9b040b 1420rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
77b2b6d4
AC		 1421 struct regcache *regcache, CORE_ADDR bp_addr,
1422 int nargs, struct value **args, CORE_ADDR sp,
1423 int struct_return, CORE_ADDR struct_addr)
c906108c 1424{
7a41266b 1425 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
c906108c
SS		 1426 int ii;
1427 int len = 0;
c5aa993b
JM		 1428 int argno; /* current argument number */
1429 int argbytes; /* current argument byte */
1430 char tmp_buffer[50];
1431 int f_argno = 0; /* current floating point argno */
21283beb 1432 int wordsize = gdbarch_tdep (current_gdbarch)->wordsize;
7d9b040b 1433 CORE_ADDR func_addr = find_function_addr (function, NULL);
c906108c 1434
ea7c478f 1435 struct value *arg = 0;
c906108c
SS		 1436 struct type *type;
1437
1438 CORE_ADDR saved_sp;
1439
383f0f5b
JB		 1440 /* The calling convention this function implements assumes the
1441 processor has floating-point registers. We shouldn't be using it
1442 on PPC variants that lack them. */
1443 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1444
64366f1c 1445 /* The first eight words of ther arguments are passed in registers.
7a41266b
AC		 1446 Copy them appropriately. */
1447 ii = 0;
1448
1449 /* If the function is returning a `struct', then the first word
1450 (which will be passed in r3) is used for struct return address.
1451 In that case we should advance one word and start from r4
1452 register to copy parameters. */
1453 if (struct_return)
1454 {
1455 regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1456 struct_addr);
1457 ii++;
1458 }
c906108c
SS		 1459
1460/*
c5aa993b
JM		 1461 effectively indirect call... gcc does...
1462
1463 return_val example( float, int);
1464
1465 eabi:
1466 float in fp0, int in r3
1467 offset of stack on overflow 8/16
1468 for varargs, must go by type.
1469 power open:
1470 float in r3&r4, int in r5
1471 offset of stack on overflow different
1472 both:
1473 return in r3 or f0. If no float, must study how gcc emulates floats;
1474 pay attention to arg promotion.
1475 User may have to cast\args to handle promotion correctly
1476 since gdb won't know if prototype supplied or not.
1477 */
c906108c 1478
c5aa993b
JM		 1479 for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
1480 {
3acba339 1481 int reg_size = register_size (current_gdbarch, ii + 3);
c5aa993b
JM		 1482
1483 arg = args[argno];
df407dfe 1484 type = check_typedef (value_type (arg));
c5aa993b
JM		 1485 len = TYPE_LENGTH (type);
1486
1487 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1488 {
1489
64366f1c 1490 /* Floating point arguments are passed in fpr's, as well as gpr's.
c5aa993b 1491 There are 13 fpr's reserved for passing parameters. At this point
64366f1c 1492 there is no way we would run out of them. */
c5aa993b 1493
9f335945
KB		 1494 gdb_assert (len <= 8);
1495
1496 regcache_cooked_write (regcache,
1497 tdep->ppc_fp0_regnum + 1 + f_argno,
1498 VALUE_CONTENTS (arg));
c5aa993b
JM		 1499 ++f_argno;
1500 }
1501
f6077098 1502 if (len > reg_size)
c5aa993b
JM		 1503 {
1504
64366f1c 1505 /* Argument takes more than one register. */
c5aa993b
JM		 1506 while (argbytes < len)
1507 {
9f335945
KB		 1508 char word[MAX_REGISTER_SIZE];
1509 memset (word, 0, reg_size);
1510 memcpy (word,
c5aa993b 1511 ((char *) VALUE_CONTENTS (arg)) + argbytes,
f6077098
KB		 1512 (len - argbytes) > reg_size
1513 ? reg_size : len - argbytes);
9f335945
KB		 1514 regcache_cooked_write (regcache,
1515 tdep->ppc_gp0_regnum + 3 + ii,
1516 word);
f6077098 1517 ++ii, argbytes += reg_size;
c5aa993b
JM		 1518
1519 if (ii >= 8)
1520 goto ran_out_of_registers_for_arguments;
1521 }
1522 argbytes = 0;
1523 --ii;
1524 }
1525 else
64366f1c
EZ		 1526 {
1527 /* Argument can fit in one register. No problem. */
d7449b42 1528 int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0;
9f335945
KB		 1529 char word[MAX_REGISTER_SIZE];
1530
1531 memset (word, 0, reg_size);
1532 memcpy (word, VALUE_CONTENTS (arg), len);
1533 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word);
c5aa993b
JM		 1534 }
1535 ++argno;
c906108c 1536 }
c906108c
SS		 1537
1538ran_out_of_registers_for_arguments:
1539
7a78ae4e 1540 saved_sp = read_sp ();
cc9836a8 1541
64366f1c 1542 /* Location for 8 parameters are always reserved. */
7a78ae4e 1543 sp -= wordsize * 8;
f6077098 1544
64366f1c 1545 /* Another six words for back chain, TOC register, link register, etc. */
7a78ae4e 1546 sp -= wordsize * 6;
f6077098 1547
64366f1c 1548 /* Stack pointer must be quadword aligned. */
7a78ae4e 1549 sp &= -16;
c906108c 1550
64366f1c
EZ		 1551 /* If there are more arguments, allocate space for them in
1552 the stack, then push them starting from the ninth one. */
c906108c 1553
c5aa993b
JM		 1554 if ((argno < nargs) || argbytes)
1555 {
1556 int space = 0, jj;
c906108c 1557
c5aa993b
JM		 1558 if (argbytes)
1559 {
1560 space += ((len - argbytes + 3) & -4);
1561 jj = argno + 1;
1562 }
1563 else
1564 jj = argno;
c906108c 1565
c5aa993b
JM		 1566 for (; jj < nargs; ++jj)
1567 {
ea7c478f 1568 struct value *val = args[jj];
df407dfe 1569 space += ((TYPE_LENGTH (value_type (val))) + 3) & -4;
c5aa993b 1570 }
c906108c 1571
64366f1c 1572 /* Add location required for the rest of the parameters. */
f6077098 1573 space = (space + 15) & -16;
c5aa993b 1574 sp -= space;
c906108c 1575
7aea86e6
AC		 1576 /* This is another instance we need to be concerned about
1577 securing our stack space. If we write anything underneath %sp
1578 (r1), we might conflict with the kernel who thinks he is free
1579 to use this area. So, update %sp first before doing anything
1580 else. */
1581
1582 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1583
64366f1c
EZ		 1584 /* If the last argument copied into the registers didn't fit there
1585 completely, push the rest of it into stack. */
c906108c 1586
c5aa993b
JM		 1587 if (argbytes)
1588 {
1589 write_memory (sp + 24 + (ii * 4),
1590 ((char *) VALUE_CONTENTS (arg)) + argbytes,
1591 len - argbytes);
1592 ++argno;
1593 ii += ((len - argbytes + 3) & -4) / 4;
1594 }
c906108c 1595
64366f1c 1596 /* Push the rest of the arguments into stack. */
c5aa993b
JM		 1597 for (; argno < nargs; ++argno)
1598 {
c906108c 1599
c5aa993b 1600 arg = args[argno];
df407dfe 1601 type = check_typedef (value_type (arg));
c5aa993b 1602 len = TYPE_LENGTH (type);
c906108c
SS		 1603
1604
64366f1c
EZ		 1605 /* Float types should be passed in fpr's, as well as in the
1606 stack. */
c5aa993b
JM		 1607 if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
1608 {
c906108c 1609
9f335945 1610 gdb_assert (len <= 8);
c906108c 1611
9f335945
KB		 1612 regcache_cooked_write (regcache,
1613 tdep->ppc_fp0_regnum + 1 + f_argno,
1614 VALUE_CONTENTS (arg));
c5aa993b
JM		 1615 ++f_argno;
1616 }
c906108c 1617
c2b6b4aa
JB		 1618 write_memory (sp + 24 + (ii * 4),
1619 (char *) VALUE_CONTENTS (arg),
1620 len);
c5aa993b
JM		 1621 ii += ((len + 3) & -4) / 4;
1622 }
c906108c 1623 }
c906108c 1624
69517000 1625 /* Set the stack pointer. According to the ABI, the SP is meant to
7aea86e6
AC		 1626 be set _before_ the corresponding stack space is used. On AIX,
1627 this even applies when the target has been completely stopped!
1628 Not doing this can lead to conflicts with the kernel which thinks
1629 that it still has control over this not-yet-allocated stack
1630 region. */
33a7c2fc
AC		 1631 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1632
7aea86e6
AC		 1633 /* Set back chain properly. */
1634 store_unsigned_integer (tmp_buffer, 4, saved_sp);
1635 write_memory (sp, tmp_buffer, 4);
1636
e56a0ecc
AC		 1637 /* Point the inferior function call's return address at the dummy's
1638 breakpoint. */
1639 regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
1640
794a477a
AC		 1641 /* Set the TOC register, get the value from the objfile reader
1642 which, in turn, gets it from the VMAP table. */
1643 if (rs6000_find_toc_address_hook != NULL)
1644 {
1645 CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr);
1646 regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue);
1647 }
1648
c906108c
SS		 1649 target_store_registers (-1);
1650 return sp;
1651}
c906108c 1652
b9ff3018
AC		 1653/* PowerOpen always puts structures in memory. Vectors, which were
1654 added later, do get returned in a register though. */
1655
1656static int
1657rs6000_use_struct_convention (int gcc_p, struct type *value_type)
1658{
1659 if ((TYPE_LENGTH (value_type) == 16 || TYPE_LENGTH (value_type) == 8)
1660 && TYPE_VECTOR (value_type))
1661 return 0;
1662 return 1;
1663}
1664
7a78ae4e
ND		 1665static void
1666rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf)
c906108c
SS		 1667{
1668 int offset = 0;
ace1378a 1669 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
c906108c 1670
383f0f5b
JB		 1671 /* The calling convention this function implements assumes the
1672 processor has floating-point registers. We shouldn't be using it
1673 on PPC variants that lack them. */
1674 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1675
c5aa993b
JM		 1676 if (TYPE_CODE (valtype) == TYPE_CODE_FLT)
1677 {
c906108c 1678
c5aa993b
JM		 1679 /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes.
1680 We need to truncate the return value into float size (4 byte) if
64366f1c 1681 necessary. */
c906108c 1682
65951cd9 1683 convert_typed_floating (&regbuf[DEPRECATED_REGISTER_BYTE
366f009f 1684 (tdep->ppc_fp0_regnum + 1)],
65951cd9
JG		 1685 builtin_type_double,
1686 valbuf,
1687 valtype);
c5aa993b 1688 }
ace1378a
EZ		 1689 else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY
1690 && TYPE_LENGTH (valtype) == 16
1691 && TYPE_VECTOR (valtype))
1692 {
62700349 1693 memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2),
ace1378a
EZ		 1694 TYPE_LENGTH (valtype));
1695 }
c5aa993b
JM		 1696 else
1697 {
1698 /* return value is copied starting from r3. */
d7449b42 1699 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3acba339
AC		 1700 && TYPE_LENGTH (valtype) < register_size (current_gdbarch, 3))
1701 offset = register_size (current_gdbarch, 3) - TYPE_LENGTH (valtype);
c5aa993b
JM		 1702
1703 memcpy (valbuf,
62700349 1704 regbuf + DEPRECATED_REGISTER_BYTE (3) + offset,
c906108c 1705 TYPE_LENGTH (valtype));
c906108c 1706 }
c906108c
SS		 1707}
1708
977adac5
ND		 1709/* Return whether handle_inferior_event() should proceed through code
1710 starting at PC in function NAME when stepping.
1711
1712 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1713 handle memory references that are too distant to fit in instructions
1714 generated by the compiler. For example, if 'foo' in the following
1715 instruction:
1716
1717 lwz r9,foo(r2)
1718
1719 is greater than 32767, the linker might replace the lwz with a branch to
1720 somewhere in @FIX1 that does the load in 2 instructions and then branches
1721 back to where execution should continue.
1722
1723 GDB should silently step over @FIX code, just like AIX dbx does.
2ec664f5
MS		 1724 Unfortunately, the linker uses the "b" instruction for the
1725 branches, meaning that the link register doesn't get set.
1726 Therefore, GDB's usual step_over_function () mechanism won't work.
977adac5 1727
2ec664f5
MS		 1728 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and
1729 SKIP_TRAMPOLINE_CODE hooks in handle_inferior_event() to skip past
1730 @FIX code. */
977adac5
ND		 1731
1732int
1733rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
1734{
1735 return name && !strncmp (name, "@FIX", 4);
1736}
1737
1738/* Skip code that the user doesn't want to see when stepping:
1739
1740 1. Indirect function calls use a piece of trampoline code to do context
1741 switching, i.e. to set the new TOC table. Skip such code if we are on
1742 its first instruction (as when we have single-stepped to here).
1743
1744 2. Skip shared library trampoline code (which is different from
c906108c 1745 indirect function call trampolines).
977adac5
ND		 1746
1747 3. Skip bigtoc fixup code.
1748
c906108c 1749 Result is desired PC to step until, or NULL if we are not in
977adac5 1750 code that should be skipped. */
c906108c
SS		 1751
1752CORE_ADDR
7a78ae4e 1753rs6000_skip_trampoline_code (CORE_ADDR pc)
c906108c 1754{
52f0bd74 1755 unsigned int ii, op;
977adac5 1756 int rel;
c906108c 1757 CORE_ADDR solib_target_pc;
977adac5 1758 struct minimal_symbol *msymbol;
c906108c 1759
c5aa993b
JM		 1760 static unsigned trampoline_code[] =
1761 {
1762 0x800b0000, /* l r0,0x0(r11) */
1763 0x90410014, /* st r2,0x14(r1) */
1764 0x7c0903a6, /* mtctr r0 */
1765 0x804b0004, /* l r2,0x4(r11) */
1766 0x816b0008, /* l r11,0x8(r11) */
1767 0x4e800420, /* bctr */
1768 0x4e800020, /* br */
1769 0
c906108c
SS		 1770 };
1771
977adac5
ND		 1772 /* Check for bigtoc fixup code. */
1773 msymbol = lookup_minimal_symbol_by_pc (pc);
2ec664f5
MS		 1774 if (msymbol
1775 && rs6000_in_solib_return_trampoline (pc,
1776 DEPRECATED_SYMBOL_NAME (msymbol)))
977adac5
ND		 1777 {
1778 /* Double-check that the third instruction from PC is relative "b". */
1779 op = read_memory_integer (pc + 8, 4);
1780 if ((op & 0xfc000003) == 0x48000000)
1781 {
1782 /* Extract bits 6-29 as a signed 24-bit relative word address and
1783 add it to the containing PC. */
1784 rel = ((int)(op << 6) >> 6);
1785 return pc + 8 + rel;
1786 }
1787 }
1788
c906108c
SS		 1789 /* If pc is in a shared library trampoline, return its target. */
1790 solib_target_pc = find_solib_trampoline_target (pc);
1791 if (solib_target_pc)
1792 return solib_target_pc;
1793
c5aa993b
JM		 1794 for (ii = 0; trampoline_code[ii]; ++ii)
1795 {
1796 op = read_memory_integer (pc + (ii * 4), 4);
1797 if (op != trampoline_code[ii])
1798 return 0;
1799 }
1800 ii = read_register (11); /* r11 holds destination addr */
21283beb 1801 pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */
c906108c
SS		 1802 return pc;
1803}
1804
7a78ae4e 1805/* Return the size of register REG when words are WORDSIZE bytes long. If REG
64366f1c 1806 isn't available with that word size, return 0. */
7a78ae4e
ND		 1807
1808static int
1809regsize (const struct reg *reg, int wordsize)
1810{
1811 return wordsize == 8 ? reg->sz64 : reg->sz32;
1812}
1813
1814/* Return the name of register number N, or null if no such register exists
64366f1c 1815 in the current architecture. */
7a78ae4e 1816
fa88f677 1817static const char *
7a78ae4e
ND		 1818rs6000_register_name (int n)
1819{
21283beb 1820 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
7a78ae4e
ND		 1821 const struct reg *reg = tdep->regs + n;
1822
1823 if (!regsize (reg, tdep->wordsize))
1824 return NULL;
1825 return reg->name;
1826}
1827
7a78ae4e
ND		 1828/* Return the GDB type object for the "standard" data type
1829 of data in register N. */
1830
1831static struct type *
691d145a 1832rs6000_register_type (struct gdbarch *gdbarch, int n)
7a78ae4e 1833{
691d145a 1834 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7a78ae4e
ND		 1835 const struct reg *reg = tdep->regs + n;
1836
1fcc0bb8
EZ		 1837 if (reg->fpr)
1838 return builtin_type_double;
1839 else
1840 {
1841 int size = regsize (reg, tdep->wordsize);
1842 switch (size)
1843 {
449a5da4
AC		 1844 case 0:
1845 return builtin_type_int0;
1846 case 4:
ed6edd9b 1847 return builtin_type_uint32;
1fcc0bb8 1848 case 8:
c8001721
EZ		 1849 if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum)
1850 return builtin_type_vec64;
1851 else
ed6edd9b 1852 return builtin_type_uint64;
1fcc0bb8
EZ		 1853 break;
1854 case 16:
08cf96df 1855 return builtin_type_vec128;
1fcc0bb8
EZ		 1856 break;
1857 default:
449a5da4
AC		 1858 internal_error (__FILE__, __LINE__, "Register %d size %d unknown",
1859 n, size);
1fcc0bb8
EZ		 1860 }
1861 }
7a78ae4e
ND		 1862}
1863
691d145a 1864/* The register format for RS/6000 floating point registers is always
64366f1c 1865 double, we need a conversion if the memory format is float. */
7a78ae4e
ND		 1866
1867static int
691d145a 1868rs6000_convert_register_p (int regnum, struct type *type)
7a78ae4e 1869{
691d145a
JB		 1870 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
1871
1872 return (reg->fpr
1873 && TYPE_CODE (type) == TYPE_CODE_FLT
1874 && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double));
7a78ae4e
ND		 1875}
1876
7a78ae4e 1877static void
691d145a
JB		 1878rs6000_register_to_value (struct frame_info *frame,
1879 int regnum,
1880 struct type *type,
1881 void *to)
7a78ae4e 1882{
691d145a
JB		 1883 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
1884 char from[MAX_REGISTER_SIZE];
1885
1886 gdb_assert (reg->fpr);
1887 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
7a78ae4e 1888
691d145a
JB		 1889 get_frame_register (frame, regnum, from);
1890 convert_typed_floating (from, builtin_type_double, to, type);
1891}
7a292a7a 1892
7a78ae4e 1893static void
691d145a
JB		 1894rs6000_value_to_register (struct frame_info *frame,
1895 int regnum,
1896 struct type *type,
1897 const void *from)
7a78ae4e 1898{
691d145a
JB		 1899 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
1900 char to[MAX_REGISTER_SIZE];
1901
1902 gdb_assert (reg->fpr);
1903 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
1904
1905 convert_typed_floating (from, type, to, builtin_type_double);
1906 put_frame_register (frame, regnum, to);
7a78ae4e 1907}
c906108c 1908
6ced10dd
JB		 1909/* Move SPE vector register values between a 64-bit buffer and the two
1910 32-bit raw register halves in a regcache. This function handles
1911 both splitting a 64-bit value into two 32-bit halves, and joining
1912 two halves into a whole 64-bit value, depending on the function
1913 passed as the MOVE argument.
1914
1915 EV_REG must be the number of an SPE evN vector register --- a
1916 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
1917 64-bit buffer.
1918
1919 Call MOVE once for each 32-bit half of that register, passing
1920 REGCACHE, the number of the raw register corresponding to that
1921 half, and the address of the appropriate half of BUFFER.
1922
1923 For example, passing 'regcache_raw_read' as the MOVE function will
1924 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
1925 'regcache_raw_supply' will supply the contents of BUFFER to the
1926 appropriate pair of raw registers in REGCACHE.
1927
1928 You may need to cast away some 'const' qualifiers when passing
1929 MOVE, since this function can't tell at compile-time which of
1930 REGCACHE or BUFFER is acting as the source of the data. If C had
1931 co-variant type qualifiers, ... */
1932static void
1933e500_move_ev_register (void (*move) (struct regcache *regcache,
1934 int regnum, void *buf),
1935 struct regcache *regcache, int ev_reg,
1936 void *buffer)
1937{
1938 struct gdbarch *arch = get_regcache_arch (regcache);
1939 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1940 int reg_index;
1941 char *byte_buffer = buffer;
1942
1943 gdb_assert (tdep->ppc_ev0_regnum <= ev_reg
1944 && ev_reg < tdep->ppc_ev0_regnum + ppc_num_gprs);
1945
1946 reg_index = ev_reg - tdep->ppc_ev0_regnum;
1947
1948 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1949 {
1950 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
1951 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
1952 }
1953 else
1954 {
1955 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
1956 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
1957 }
1958}
1959
c8001721
EZ		 1960static void
1961e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1962 int reg_nr, void *buffer)
1963{
6ced10dd 1964 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
c8001721
EZ		 1965 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1966
6ced10dd
JB		 1967 gdb_assert (regcache_arch == gdbarch);
1968
1969 if (tdep->ppc_ev0_regnum <= reg_nr
1970 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
1971 e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
1972 else
a44bddec
JB		 1973 internal_error (__FILE__, __LINE__,
1974 "e500_pseudo_register_read: "
1975 "called on unexpected register '%s' (%d)",
1976 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
c8001721
EZ		 1977}
1978
1979static void
1980e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1981 int reg_nr, const void *buffer)
1982{
6ced10dd 1983 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
c8001721
EZ		 1984 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1985
6ced10dd
JB		 1986 gdb_assert (regcache_arch == gdbarch);
1987
1988 if (tdep->ppc_ev0_regnum <= reg_nr
1989 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
1990 e500_move_ev_register ((void (*) (struct regcache *, int, void *))
1991 regcache_raw_write,
1992 regcache, reg_nr, (void *) buffer);
1993 else
a44bddec
JB		 1994 internal_error (__FILE__, __LINE__,
1995 "e500_pseudo_register_read: "
1996 "called on unexpected register '%s' (%d)",
1997 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
6ced10dd
JB		 1998}
1999
2000/* The E500 needs a custom reggroup function: it has anonymous raw
2001 registers, and default_register_reggroup_p assumes that anonymous
2002 registers are not members of any reggroup. */
2003static int
2004e500_register_reggroup_p (struct gdbarch *gdbarch,
2005 int regnum,
2006 struct reggroup *group)
2007{
2008 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2009
2010 /* The save and restore register groups need to include the
2011 upper-half registers, even though they're anonymous. */
2012 if ((group == save_reggroup
2013 || group == restore_reggroup)
2014 && (tdep->ppc_ev0_upper_regnum <= regnum
2015 && regnum < tdep->ppc_ev0_upper_regnum + ppc_num_gprs))
2016 return 1;
2017
2018 /* In all other regards, the default reggroup definition is fine. */
2019 return default_register_reggroup_p (gdbarch, regnum, group);
c8001721
EZ		 2020}
2021
18ed0c4e 2022/* Convert a DBX STABS register number to a GDB register number. */
c8001721 2023static int
18ed0c4e 2024rs6000_stab_reg_to_regnum (int num)
c8001721 2025{
9f744501 2026 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
c8001721 2027
9f744501
JB		 2028 if (0 <= num && num <= 31)
2029 return tdep->ppc_gp0_regnum + num;
2030 else if (32 <= num && num <= 63)
383f0f5b
JB		 2031 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2032 specifies registers the architecture doesn't have? Our
2033 callers don't check the value we return. */
366f009f 2034 return tdep->ppc_fp0_regnum + (num - 32);
18ed0c4e
JB		 2035 else if (77 <= num && num <= 108)
2036 return tdep->ppc_vr0_regnum + (num - 77);
9f744501
JB		 2037 else if (1200 <= num && num < 1200 + 32)
2038 return tdep->ppc_ev0_regnum + (num - 1200);
2039 else
2040 switch (num)
2041 {
2042 case 64:
2043 return tdep->ppc_mq_regnum;
2044 case 65:
2045 return tdep->ppc_lr_regnum;
2046 case 66:
2047 return tdep->ppc_ctr_regnum;
2048 case 76:
2049 return tdep->ppc_xer_regnum;
2050 case 109:
2051 return tdep->ppc_vrsave_regnum;
18ed0c4e
JB		 2052 case 110:
2053 return tdep->ppc_vrsave_regnum - 1; /* vscr */
867e2dc5 2054 case 111:
18ed0c4e 2055 return tdep->ppc_acc_regnum;
867e2dc5 2056 case 112:
18ed0c4e 2057 return tdep->ppc_spefscr_regnum;
9f744501
JB		 2058 default:
2059 return num;
2060 }
18ed0c4e 2061}
9f744501 2062
9f744501 2063
18ed0c4e
JB		 2064/* Convert a Dwarf 2 register number to a GDB register number. */
2065static int
2066rs6000_dwarf2_reg_to_regnum (int num)
2067{
2068 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
9f744501 2069
18ed0c4e
JB		 2070 if (0 <= num && num <= 31)
2071 return tdep->ppc_gp0_regnum + num;
2072 else if (32 <= num && num <= 63)
2073 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2074 specifies registers the architecture doesn't have? Our
2075 callers don't check the value we return. */
2076 return tdep->ppc_fp0_regnum + (num - 32);
2077 else if (1124 <= num && num < 1124 + 32)
2078 return tdep->ppc_vr0_regnum + (num - 1124);
2079 else if (1200 <= num && num < 1200 + 32)
2080 return tdep->ppc_ev0_regnum + (num - 1200);
2081 else
2082 switch (num)
2083 {
2084 case 67:
2085 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2086 case 99:
2087 return tdep->ppc_acc_regnum;
2088 case 100:
2089 return tdep->ppc_mq_regnum;
2090 case 101:
2091 return tdep->ppc_xer_regnum;
2092 case 108:
2093 return tdep->ppc_lr_regnum;
2094 case 109:
2095 return tdep->ppc_ctr_regnum;
2096 case 356:
2097 return tdep->ppc_vrsave_regnum;
2098 case 612:
2099 return tdep->ppc_spefscr_regnum;
2100 default:
2101 return num;
2102 }
2188cbdd
EZ		 2103}
2104
18ed0c4e 2105
7a78ae4e 2106static void
a3c001ce
JB		 2107rs6000_store_return_value (struct type *type,
2108 struct regcache *regcache,
2109 const void *valbuf)
7a78ae4e 2110{
a3c001ce
JB		 2111 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2112 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2113 int regnum = -1;
ace1378a 2114
383f0f5b
JB		 2115 /* The calling convention this function implements assumes the
2116 processor has floating-point registers. We shouldn't be using it
2117 on PPC variants that lack them. */
a3c001ce 2118 gdb_assert (ppc_floating_point_unit_p (gdbarch));
383f0f5b 2119
7a78ae4e 2120 if (TYPE_CODE (type) == TYPE_CODE_FLT)
7a78ae4e
ND		 2121 /* Floating point values are returned starting from FPR1 and up.
2122 Say a double_double_double type could be returned in
64366f1c 2123 FPR1/FPR2/FPR3 triple. */
a3c001ce 2124 regnum = tdep->ppc_fp0_regnum + 1;
ace1378a
EZ		 2125 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2126 {
2127 if (TYPE_LENGTH (type) == 16
2128 && TYPE_VECTOR (type))
a3c001ce
JB		 2129 regnum = tdep->ppc_vr0_regnum + 2;
2130 else
a44bddec
JB		 2131 internal_error (__FILE__, __LINE__,
2132 "rs6000_store_return_value: "
2133 "unexpected array return type");
ace1378a 2134 }
7a78ae4e 2135 else
64366f1c 2136 /* Everything else is returned in GPR3 and up. */
a3c001ce
JB		 2137 regnum = tdep->ppc_gp0_regnum + 3;
2138
2139 {
2140 size_t bytes_written = 0;
2141
2142 while (bytes_written < TYPE_LENGTH (type))
2143 {
2144 /* How much of this value can we write to this register? */
2145 size_t bytes_to_write = min (TYPE_LENGTH (type) - bytes_written,
2146 register_size (gdbarch, regnum));
2147 regcache_cooked_write_part (regcache, regnum,
2148 0, bytes_to_write,
2149 (char *) valbuf + bytes_written);
2150 regnum++;
2151 bytes_written += bytes_to_write;
2152 }
2153 }
7a78ae4e
ND		 2154}
2155
a3c001ce 2156
7a78ae4e
ND		 2157/* Extract from an array REGBUF containing the (raw) register state
2158 the address in which a function should return its structure value,
2159 as a CORE_ADDR (or an expression that can be used as one). */
2160
2161static CORE_ADDR
11269d7e
AC		 2162rs6000_extract_struct_value_address (struct regcache *regcache)
2163{
2164 /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior
2165 function call GDB knows the address of the struct return value
2166 and hence, should not need to call this function. Unfortunately,
e8a8712a
AC		 2167 the current call_function_by_hand() code only saves the most
2168 recent struct address leading to occasional calls. The code
2169 should instead maintain a stack of such addresses (in the dummy
2170 frame object). */
11269d7e
AC		 2171 /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've
2172 really got no idea where the return value is being stored. While
2173 r3, on function entry, contained the address it will have since
2174 been reused (scratch) and hence wouldn't be valid */
2175 return 0;
7a78ae4e
ND		 2176}
2177
64366f1c 2178/* Hook called when a new child process is started. */
7a78ae4e
ND		 2179
2180void
2181rs6000_create_inferior (int pid)
2182{
2183 if (rs6000_set_host_arch_hook)
2184 rs6000_set_host_arch_hook (pid);
c906108c
SS		 2185}
2186\f
e2d0e7eb 2187/* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
7a78ae4e
ND		 2188
2189 Usually a function pointer's representation is simply the address
2190 of the function. On the RS/6000 however, a function pointer is
2191 represented by a pointer to a TOC entry. This TOC entry contains
2192 three words, the first word is the address of the function, the
2193 second word is the TOC pointer (r2), and the third word is the
2194 static chain value. Throughout GDB it is currently assumed that a
2195 function pointer contains the address of the function, which is not
2196 easy to fix. In addition, the conversion of a function address to
2197 a function pointer would require allocation of a TOC entry in the
2198 inferior's memory space, with all its drawbacks. To be able to
2199 call C++ virtual methods in the inferior (which are called via
f517ea4e 2200 function pointers), find_function_addr uses this function to get the
7a78ae4e
ND		 2201 function address from a function pointer. */
2202
f517ea4e
PS		 2203/* Return real function address if ADDR (a function pointer) is in the data
2204 space and is therefore a special function pointer. */
c906108c 2205
b9362cc7 2206static CORE_ADDR
e2d0e7eb
AC		 2207rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch,
2208 CORE_ADDR addr,
2209 struct target_ops *targ)
c906108c
SS		 2210{
2211 struct obj_section *s;
2212
2213 s = find_pc_section (addr);
2214 if (s && s->the_bfd_section->flags & SEC_CODE)
7a78ae4e 2215 return addr;
c906108c 2216
7a78ae4e 2217 /* ADDR is in the data space, so it's a special function pointer. */
21283beb 2218 return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize);
c906108c 2219}
c906108c 2220\f
c5aa993b 2221
7a78ae4e 2222/* Handling the various POWER/PowerPC variants. */
c906108c
SS		 2223
2224
7a78ae4e
ND		 2225/* The arrays here called registers_MUMBLE hold information about available
2226 registers.
c906108c
SS		 2227
2228 For each family of PPC variants, I've tried to isolate out the
2229 common registers and put them up front, so that as long as you get
2230 the general family right, GDB will correctly identify the registers
2231 common to that family. The common register sets are:
2232
2233 For the 60x family: hid0 hid1 iabr dabr pir
2234
2235 For the 505 and 860 family: eie eid nri
2236
2237 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
c5aa993b
JM		 2238 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
2239 pbu1 pbl2 pbu2
c906108c
SS		 2240
2241 Most of these register groups aren't anything formal. I arrived at
2242 them by looking at the registers that occurred in more than one
6f5987a6
KB		 2243 processor.
2244
2245 Note: kevinb/2002-04-30: Support for the fpscr register was added
2246 during April, 2002. Slot 70 is being used for PowerPC and slot 71
2247 for Power. For PowerPC, slot 70 was unused and was already in the
2248 PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
2249 slot 70 was being used for "mq", so the next available slot (71)
2250 was chosen. It would have been nice to be able to make the
2251 register numbers the same across processor cores, but this wasn't
2252 possible without either 1) renumbering some registers for some
2253 processors or 2) assigning fpscr to a really high slot that's
2254 larger than any current register number. Doing (1) is bad because
2255 existing stubs would break. Doing (2) is undesirable because it
2256 would introduce a really large gap between fpscr and the rest of
2257 the registers for most processors. */
7a78ae4e 2258
64366f1c 2259/* Convenience macros for populating register arrays. */
7a78ae4e 2260
64366f1c 2261/* Within another macro, convert S to a string. */
7a78ae4e
ND		 2262
2263#define STR(s) #s
2264
2265/* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
64366f1c 2266 and 64 bits on 64-bit systems. */
13ac140c 2267#define R(name) { STR(name), 4, 8, 0, 0, -1 }
7a78ae4e
ND		 2268
2269/* Return a struct reg defining register NAME that's 32 bits on all
64366f1c 2270 systems. */
13ac140c 2271#define R4(name) { STR(name), 4, 4, 0, 0, -1 }
7a78ae4e
ND		 2272
2273/* Return a struct reg defining register NAME that's 64 bits on all
64366f1c 2274 systems. */
13ac140c 2275#define R8(name) { STR(name), 8, 8, 0, 0, -1 }
7a78ae4e 2276
1fcc0bb8 2277/* Return a struct reg defining register NAME that's 128 bits on all
64366f1c 2278 systems. */
13ac140c 2279#define R16(name) { STR(name), 16, 16, 0, 0, -1 }
1fcc0bb8 2280
64366f1c 2281/* Return a struct reg defining floating-point register NAME. */
13ac140c 2282#define F(name) { STR(name), 8, 8, 1, 0, -1 }
489461e2 2283
6ced10dd
JB		 2284/* Return a struct reg defining a pseudo register NAME that is 64 bits
2285 long on all systems. */
2286#define P8(name) { STR(name), 8, 8, 0, 1, -1 }
7a78ae4e
ND		 2287
2288/* Return a struct reg defining register NAME that's 32 bits on 32-bit
64366f1c 2289 systems and that doesn't exist on 64-bit systems. */
13ac140c 2290#define R32(name) { STR(name), 4, 0, 0, 0, -1 }
7a78ae4e
ND		 2291
2292/* Return a struct reg defining register NAME that's 64 bits on 64-bit
64366f1c 2293 systems and that doesn't exist on 32-bit systems. */
13ac140c 2294#define R64(name) { STR(name), 0, 8, 0, 0, -1 }
7a78ae4e 2295
64366f1c 2296/* Return a struct reg placeholder for a register that doesn't exist. */
13ac140c 2297#define R0 { 0, 0, 0, 0, 0, -1 }
7a78ae4e 2298
6ced10dd
JB		 2299/* Return a struct reg defining an anonymous raw register that's 32
2300 bits on all systems. */
2301#define A4 { 0, 4, 4, 0, 0, -1 }
2302
13ac140c
JB		 2303/* Return a struct reg defining an SPR named NAME that is 32 bits on
2304 32-bit systems and 64 bits on 64-bit systems. */
2305#define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name }
2306
2307/* Return a struct reg defining an SPR named NAME that is 32 bits on
2308 all systems. */
2309#define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name }
2310
2311/* Return a struct reg defining an SPR named NAME that is 32 bits on
2312 all systems, and whose SPR number is NUMBER. */
2313#define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) }
2314
2315/* Return a struct reg defining an SPR named NAME that's 64 bits on
2316 64-bit systems and that doesn't exist on 32-bit systems. */
2317#define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name }
2318
7a78ae4e
ND		 2319/* UISA registers common across all architectures, including POWER. */
2320
2321#define COMMON_UISA_REGS \
2322 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
2323 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
2324 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
2325 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
2326 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
2327 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
2328 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
2329 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
2330 /* 64 */ R(pc), R(ps)
2331
2332/* UISA-level SPRs for PowerPC. */
2333#define PPC_UISA_SPRS \
13ac140c 2334 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr)
7a78ae4e 2335
c8001721
EZ		 2336/* UISA-level SPRs for PowerPC without floating point support. */
2337#define PPC_UISA_NOFP_SPRS \
13ac140c 2338 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0
c8001721 2339
7a78ae4e
ND		 2340/* Segment registers, for PowerPC. */
2341#define PPC_SEGMENT_REGS \
2342 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
2343 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
2344 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
2345 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
2346
2347/* OEA SPRs for PowerPC. */
2348#define PPC_OEA_SPRS \
13ac140c
JB		 2349 /* 87 */ S4(pvr), \
2350 /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \
2351 /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \
2352 /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \
2353 /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \
2354 /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \
2355 /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \
2356 /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \
2357 /* 116 */ S4(dec), S(dabr), S4(ear)
7a78ae4e 2358
64366f1c 2359/* AltiVec registers. */
1fcc0bb8
EZ		 2360#define PPC_ALTIVEC_REGS \
2361 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
2362 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
2363 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
2364 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
2365 /*151*/R4(vscr), R4(vrsave)
2366
c8001721 2367
6ced10dd
JB		 2368/* On machines supporting the SPE APU, the general-purpose registers
2369 are 64 bits long. There are SIMD vector instructions to treat them
2370 as pairs of floats, but the rest of the instruction set treats them
2371 as 32-bit registers, and only operates on their lower halves.
2372
2373 In the GDB regcache, we treat their high and low halves as separate
2374 registers. The low halves we present as the general-purpose
2375 registers, and then we have pseudo-registers that stitch together
2376 the upper and lower halves and present them as pseudo-registers. */
2377
2378/* SPE GPR lower halves --- raw registers. */
2379#define PPC_SPE_GP_REGS \
2380 /* 0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7), \
2381 /* 8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \
2382 /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \
2383 /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31)
2384
2385/* SPE GPR upper halves --- anonymous raw registers. */
2386#define PPC_SPE_UPPER_GP_REGS \
2387 /* 0 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2388 /* 8 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2389 /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2390 /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4
2391
2392/* SPE GPR vector registers --- pseudo registers based on underlying
2393 gprs and the anonymous upper half raw registers. */
2394#define PPC_EV_PSEUDO_REGS \
2395/* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \
2396/* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\
2397/*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\
2398/*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31)
c8001721 2399
7a78ae4e 2400/* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
64366f1c 2401 user-level SPR's. */
7a78ae4e 2402static const struct reg registers_power[] =
c906108c 2403{
7a78ae4e 2404 COMMON_UISA_REGS,
13ac140c 2405 /* 66 */ R4(cnd), S(lr), S(cnt), S4(xer), S4(mq),
e3f36dbd 2406 /* 71 */ R4(fpscr)
c906108c
SS		 2407};
2408
7a78ae4e 2409/* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
64366f1c 2410 view of the PowerPC. */
7a78ae4e 2411static const struct reg registers_powerpc[] =
c906108c 2412{
7a78ae4e 2413 COMMON_UISA_REGS,
1fcc0bb8
EZ		 2414 PPC_UISA_SPRS,
2415 PPC_ALTIVEC_REGS
c906108c
SS		 2416};
2417
13ac140c
JB		 2418/* IBM PowerPC 403.
2419
2420 Some notes about the "tcr" special-purpose register:
2421 - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the
2422 403's programmable interval timer, fixed interval timer, and
2423 watchdog timer.
2424 - On the 602, SPR 984 is named "tcr", and it controls the 602's
2425 watchdog timer, and nothing else.
2426
2427 Some of the fields are similar between the two, but they're not
2428 compatible with each other. Since the two variants have different
2429 registers, with different numbers, but the same name, we can't
2430 splice the register name to get the SPR number. */
7a78ae4e 2431static const struct reg registers_403[] =
c5aa993b 2432{
7a78ae4e
ND		 2433 COMMON_UISA_REGS,
2434 PPC_UISA_SPRS,
2435 PPC_SEGMENT_REGS,
2436 PPC_OEA_SPRS,
13ac140c
JB		 2437 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr),
2438 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit),
2439 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3),
2440 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2),
2441 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr),
2442 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2)
c906108c
SS		 2443};
2444
13ac140c
JB		 2445/* IBM PowerPC 403GC.
2446 See the comments about 'tcr' for the 403, above. */
7a78ae4e 2447static const struct reg registers_403GC[] =
c5aa993b 2448{
7a78ae4e
ND		 2449 COMMON_UISA_REGS,
2450 PPC_UISA_SPRS,
2451 PPC_SEGMENT_REGS,
2452 PPC_OEA_SPRS,
13ac140c
JB		 2453 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr),
2454 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit),
2455 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3),
2456 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2),
2457 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr),
2458 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2),
2459 /* 143 */ S(zpr), S(pid), S(sgr), S(dcwr),
2460 /* 147 */ S(tbhu), S(tblu)
c906108c
SS		 2461};
2462
64366f1c 2463/* Motorola PowerPC 505. */
7a78ae4e 2464static const struct reg registers_505[] =
c5aa993b 2465{
7a78ae4e
ND		 2466 COMMON_UISA_REGS,
2467 PPC_UISA_SPRS,
2468 PPC_SEGMENT_REGS,
2469 PPC_OEA_SPRS,
13ac140c 2470 /* 119 */ S(eie), S(eid), S(nri)
c906108c
SS		 2471};
2472
64366f1c 2473/* Motorola PowerPC 860 or 850. */
7a78ae4e 2474static const struct reg registers_860[] =
c5aa993b 2475{
7a78ae4e
ND		 2476 COMMON_UISA_REGS,
2477 PPC_UISA_SPRS,
2478 PPC_SEGMENT_REGS,
2479 PPC_OEA_SPRS,
13ac140c
JB		 2480 /* 119 */ S(eie), S(eid), S(nri), S(cmpa),
2481 /* 123 */ S(cmpb), S(cmpc), S(cmpd), S(icr),
2482 /* 127 */ S(der), S(counta), S(countb), S(cmpe),
2483 /* 131 */ S(cmpf), S(cmpg), S(cmph), S(lctrl1),
2484 /* 135 */ S(lctrl2), S(ictrl), S(bar), S(ic_cst),
2485 /* 139 */ S(ic_adr), S(ic_dat), S(dc_cst), S(dc_adr),
2486 /* 143 */ S(dc_dat), S(dpdr), S(dpir), S(immr),
2487 /* 147 */ S(mi_ctr), S(mi_ap), S(mi_epn), S(mi_twc),
2488 /* 151 */ S(mi_rpn), S(md_ctr), S(m_casid), S(md_ap),
2489 /* 155 */ S(md_epn), S(m_twb), S(md_twc), S(md_rpn),
2490 /* 159 */ S(m_tw), S(mi_dbcam), S(mi_dbram0), S(mi_dbram1),
2491 /* 163 */ S(md_dbcam), S(md_dbram0), S(md_dbram1)
c906108c
SS		 2492};
2493
7a78ae4e
ND		 2494/* Motorola PowerPC 601. Note that the 601 has different register numbers
2495 for reading and writing RTCU and RTCL. However, how one reads and writes a
c906108c 2496 register is the stub's problem. */
7a78ae4e 2497static const struct reg registers_601[] =
c5aa993b 2498{
7a78ae4e
ND		 2499 COMMON_UISA_REGS,
2500 PPC_UISA_SPRS,
2501 PPC_SEGMENT_REGS,
2502 PPC_OEA_SPRS,
13ac140c
JB		 2503 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2504 /* 123 */ S(pir), S(mq), S(rtcu), S(rtcl)
c906108c
SS		 2505};
2506
13ac140c
JB		 2507/* Motorola PowerPC 602.
2508 See the notes under the 403 about 'tcr'. */
7a78ae4e 2509static const struct reg registers_602[] =
c5aa993b 2510{
7a78ae4e
ND		 2511 COMMON_UISA_REGS,
2512 PPC_UISA_SPRS,
2513 PPC_SEGMENT_REGS,
2514 PPC_OEA_SPRS,
13ac140c
JB		 2515 /* 119 */ S(hid0), S(hid1), S(iabr), R0,
2516 /* 123 */ R0, SN4(tcr, ppc_spr_602_tcr), S(ibr), S(esasrr),
2517 /* 127 */ S(sebr), S(ser), S(sp), S(lt)
c906108c
SS		 2518};
2519
64366f1c 2520/* Motorola/IBM PowerPC 603 or 603e. */
7a78ae4e 2521static const struct reg registers_603[] =
c5aa993b 2522{
7a78ae4e
ND		 2523 COMMON_UISA_REGS,
2524 PPC_UISA_SPRS,
2525 PPC_SEGMENT_REGS,
2526 PPC_OEA_SPRS,
13ac140c
JB		 2527 /* 119 */ S(hid0), S(hid1), S(iabr), R0,
2528 /* 123 */ R0, S(dmiss), S(dcmp), S(hash1),
2529 /* 127 */ S(hash2), S(imiss), S(icmp), S(rpa)
c906108c
SS		 2530};
2531
64366f1c 2532/* Motorola PowerPC 604 or 604e. */
7a78ae4e 2533static const struct reg registers_604[] =
c5aa993b 2534{
7a78ae4e
ND		 2535 COMMON_UISA_REGS,
2536 PPC_UISA_SPRS,
2537 PPC_SEGMENT_REGS,
2538 PPC_OEA_SPRS,
13ac140c
JB		 2539 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2540 /* 123 */ S(pir), S(mmcr0), S(pmc1), S(pmc2),
2541 /* 127 */ S(sia), S(sda)
c906108c
SS		 2542};
2543
64366f1c 2544/* Motorola/IBM PowerPC 750 or 740. */
7a78ae4e 2545static const struct reg registers_750[] =
c5aa993b 2546{
7a78ae4e
ND		 2547 COMMON_UISA_REGS,
2548 PPC_UISA_SPRS,
2549 PPC_SEGMENT_REGS,
2550 PPC_OEA_SPRS,
13ac140c
JB		 2551 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2552 /* 123 */ R0, S(ummcr0), S(upmc1), S(upmc2),
2553 /* 127 */ S(usia), S(ummcr1), S(upmc3), S(upmc4),
2554 /* 131 */ S(mmcr0), S(pmc1), S(pmc2), S(sia),
2555 /* 135 */ S(mmcr1), S(pmc3), S(pmc4), S(l2cr),
2556 /* 139 */ S(ictc), S(thrm1), S(thrm2), S(thrm3)
c906108c
SS		 2557};
2558
2559
64366f1c 2560/* Motorola PowerPC 7400. */
1fcc0bb8
EZ		 2561static const struct reg registers_7400[] =
2562{
2563 /* gpr0-gpr31, fpr0-fpr31 */
2564 COMMON_UISA_REGS,
13c7b1ca 2565 /* cr, lr, ctr, xer, fpscr */
1fcc0bb8
EZ		 2566 PPC_UISA_SPRS,
2567 /* sr0-sr15 */
2568 PPC_SEGMENT_REGS,
2569 PPC_OEA_SPRS,
2570 /* vr0-vr31, vrsave, vscr */
2571 PPC_ALTIVEC_REGS
2572 /* FIXME? Add more registers? */
2573};
2574
c8001721
EZ		 2575/* Motorola e500. */
2576static const struct reg registers_e500[] =
2577{
6ced10dd
JB		 2578 /* 0 .. 31 */ PPC_SPE_GP_REGS,
2579 /* 32 .. 63 */ PPC_SPE_UPPER_GP_REGS,
2580 /* 64 .. 65 */ R(pc), R(ps),
2581 /* 66 .. 70 */ PPC_UISA_NOFP_SPRS,
2582 /* 71 .. 72 */ R8(acc), S4(spefscr),
338ef23d
AC		 2583 /* NOTE: Add new registers here the end of the raw register
2584 list and just before the first pseudo register. */
6ced10dd 2585 /* 73 .. 104 */ PPC_EV_PSEUDO_REGS
c8001721
EZ		 2586};
2587
c906108c 2588/* Information about a particular processor variant. */
7a78ae4e 2589
c906108c 2590struct variant
c5aa993b
JM		 2591 {
2592 /* Name of this variant. */
2593 char *name;
c906108c 2594
c5aa993b
JM		 2595 /* English description of the variant. */
2596 char *description;
c906108c 2597
64366f1c 2598 /* bfd_arch_info.arch corresponding to variant. */
7a78ae4e
ND		 2599 enum bfd_architecture arch;
2600
64366f1c 2601 /* bfd_arch_info.mach corresponding to variant. */
7a78ae4e
ND		 2602 unsigned long mach;
2603
489461e2
EZ		 2604 /* Number of real registers. */
2605 int nregs;
2606
2607 /* Number of pseudo registers. */
2608 int npregs;
2609
2610 /* Number of total registers (the sum of nregs and npregs). */
2611 int num_tot_regs;
2612
c5aa993b
JM		 2613 /* Table of register names; registers[R] is the name of the register
2614 number R. */
7a78ae4e 2615 const struct reg *regs;
c5aa993b 2616 };
c906108c 2617
489461e2
EZ		 2618#define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
2619
2620static int
2621num_registers (const struct reg *reg_list, int num_tot_regs)
2622{
2623 int i;
2624 int nregs = 0;
2625
2626 for (i = 0; i < num_tot_regs; i++)
2627 if (!reg_list[i].pseudo)
2628 nregs++;
2629
2630 return nregs;
2631}
2632
2633static int
2634num_pseudo_registers (const struct reg *reg_list, int num_tot_regs)
2635{
2636 int i;
2637 int npregs = 0;
2638
2639 for (i = 0; i < num_tot_regs; i++)
2640 if (reg_list[i].pseudo)
2641 npregs ++;
2642
2643 return npregs;
2644}
c906108c 2645
c906108c
SS		 2646/* Information in this table comes from the following web sites:
2647 IBM: http://www.chips.ibm.com:80/products/embedded/
2648 Motorola: http://www.mot.com/SPS/PowerPC/
2649
2650 I'm sure I've got some of the variant descriptions not quite right.
2651 Please report any inaccuracies you find to GDB's maintainer.
2652
2653 If you add entries to this table, please be sure to allow the new
2654 value as an argument to the --with-cpu flag, in configure.in. */
2655
489461e2 2656static struct variant variants[] =
c906108c 2657{
489461e2 2658
7a78ae4e 2659 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
489461e2
EZ		 2660 bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc),
2661 registers_powerpc},
7a78ae4e 2662 {"power", "POWER user-level", bfd_arch_rs6000,
489461e2
EZ		 2663 bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power),
2664 registers_power},
7a78ae4e 2665 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
489461e2
EZ		 2666 bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403),
2667 registers_403},
7a78ae4e 2668 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
489461e2
EZ		 2669 bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601),
2670 registers_601},
7a78ae4e 2671 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
489461e2
EZ		 2672 bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602),
2673 registers_602},
7a78ae4e 2674 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
489461e2
EZ		 2675 bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603),
2676 registers_603},
7a78ae4e 2677 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
489461e2
EZ		 2678 604, -1, -1, tot_num_registers (registers_604),
2679 registers_604},
7a78ae4e 2680 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
489461e2
EZ		 2681 bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC),
2682 registers_403GC},
7a78ae4e 2683 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
489461e2
EZ		 2684 bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505),
2685 registers_505},
7a78ae4e 2686 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
489461e2
EZ		 2687 bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860),
2688 registers_860},
7a78ae4e 2689 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
489461e2
EZ		 2690 bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750),
2691 registers_750},
1fcc0bb8 2692 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
489461e2
EZ		 2693 bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400),
2694 registers_7400},
c8001721
EZ		 2695 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
2696 bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500),
2697 registers_e500},
7a78ae4e 2698
5d57ee30
KB		 2699 /* 64-bit */
2700 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
489461e2
EZ		 2701 bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc),
2702 registers_powerpc},
7a78ae4e 2703 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
489461e2
EZ		 2704 bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc),
2705 registers_powerpc},
5d57ee30 2706 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
489461e2
EZ		 2707 bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc),
2708 registers_powerpc},
7a78ae4e 2709 {"a35", "PowerPC A35", bfd_arch_powerpc,
489461e2
EZ		 2710 bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc),
2711 registers_powerpc},
5d57ee30 2712 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
489461e2
EZ		 2713 bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc),
2714 registers_powerpc},
5d57ee30 2715 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
489461e2
EZ		 2716 bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc),
2717 registers_powerpc},
5d57ee30 2718
64366f1c 2719 /* FIXME: I haven't checked the register sets of the following. */
7a78ae4e 2720 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
489461e2
EZ		 2721 bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power),
2722 registers_power},
7a78ae4e 2723 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
489461e2
EZ		 2724 bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power),
2725 registers_power},
7a78ae4e 2726 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
489461e2
EZ		 2727 bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power),
2728 registers_power},
7a78ae4e 2729
489461e2 2730 {0, 0, 0, 0, 0, 0, 0, 0}
c906108c
SS		 2731};
2732
64366f1c 2733/* Initialize the number of registers and pseudo registers in each variant. */
489461e2
EZ		 2734
2735static void
2736init_variants (void)
2737{
2738 struct variant *v;
2739
2740 for (v = variants; v->name; v++)
2741 {
2742 if (v->nregs == -1)
2743 v->nregs = num_registers (v->regs, v->num_tot_regs);
2744 if (v->npregs == -1)
2745 v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs);
2746 }
2747}
c906108c 2748
7a78ae4e 2749/* Return the variant corresponding to architecture ARCH and machine number
64366f1c 2750 MACH. If no such variant exists, return null. */
c906108c 2751
7a78ae4e
ND		 2752static const struct variant *
2753find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
c906108c 2754{
7a78ae4e 2755 const struct variant *v;
c5aa993b 2756
7a78ae4e
ND		 2757 for (v = variants; v->name; v++)
2758 if (arch == v->arch && mach == v->mach)
2759 return v;
c906108c 2760
7a78ae4e 2761 return NULL;
c906108c 2762}
9364a0ef
EZ		 2763
2764static int
2765gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
2766{
2767 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2768 return print_insn_big_powerpc (memaddr, info);
2769 else
2770 return print_insn_little_powerpc (memaddr, info);
2771}
7a78ae4e 2772\f
61a65099
KB		 2773static CORE_ADDR
2774rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2775{
2776 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2777}
2778
2779static struct frame_id
2780rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2781{
2782 return frame_id_build (frame_unwind_register_unsigned (next_frame,
2783 SP_REGNUM),
2784 frame_pc_unwind (next_frame));
2785}
2786
2787struct rs6000_frame_cache
2788{
2789 CORE_ADDR base;
2790 CORE_ADDR initial_sp;
2791 struct trad_frame_saved_reg *saved_regs;
2792};
2793
2794static struct rs6000_frame_cache *
2795rs6000_frame_cache (struct frame_info *next_frame, void **this_cache)
2796{
2797 struct rs6000_frame_cache *cache;
2798 struct gdbarch *gdbarch = get_frame_arch (next_frame);
2799 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2800 struct rs6000_framedata fdata;
2801 int wordsize = tdep->wordsize;
2802
2803 if ((*this_cache) != NULL)
2804 return (*this_cache);
2805 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
2806 (*this_cache) = cache;
2807 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
2808
2809 skip_prologue (frame_func_unwind (next_frame), frame_pc_unwind (next_frame),
2810 &fdata);
2811
2812 /* If there were any saved registers, figure out parent's stack
2813 pointer. */
2814 /* The following is true only if the frame doesn't have a call to
2815 alloca(), FIXME. */
2816
2817 if (fdata.saved_fpr == 0
2818 && fdata.saved_gpr == 0
2819 && fdata.saved_vr == 0
2820 && fdata.saved_ev == 0
2821 && fdata.lr_offset == 0
2822 && fdata.cr_offset == 0
2823 && fdata.vr_offset == 0
2824 && fdata.ev_offset == 0)
2825 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2826 else
2827 {
2828 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2829 address of the current frame. Things might be easier if the
2830 ->frame pointed to the outer-most address of the frame. In
2831 the mean time, the address of the prev frame is used as the
2832 base address of this frame. */
2833 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2834 if (!fdata.frameless)
2835 /* Frameless really means stackless. */
2836 cache->base = read_memory_addr (cache->base, wordsize);
2837 }
2838 trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base);
2839
2840 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
2841 All fpr's from saved_fpr to fp31 are saved. */
2842
2843 if (fdata.saved_fpr >= 0)
2844 {
2845 int i;
2846 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
383f0f5b
JB		 2847
2848 /* If skip_prologue says floating-point registers were saved,
2849 but the current architecture has no floating-point registers,
2850 then that's strange. But we have no indices to even record
2851 the addresses under, so we just ignore it. */
2852 if (ppc_floating_point_unit_p (gdbarch))
063715bf 2853 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
383f0f5b
JB		 2854 {
2855 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
2856 fpr_addr += 8;
2857 }
61a65099
KB		 2858 }
2859
2860 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
2861 All gpr's from saved_gpr to gpr31 are saved. */
2862
2863 if (fdata.saved_gpr >= 0)
2864 {
2865 int i;
2866 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
063715bf 2867 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
61a65099
KB		 2868 {
2869 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
2870 gpr_addr += wordsize;
2871 }
2872 }
2873
2874 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
2875 All vr's from saved_vr to vr31 are saved. */
2876 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
2877 {
2878 if (fdata.saved_vr >= 0)
2879 {
2880 int i;
2881 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
2882 for (i = fdata.saved_vr; i < 32; i++)
2883 {
2884 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
2885 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
2886 }
2887 }
2888 }
2889
2890 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
2891 All vr's from saved_ev to ev31 are saved. ????? */
2892 if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1)
2893 {
2894 if (fdata.saved_ev >= 0)
2895 {
2896 int i;
2897 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
063715bf 2898 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
61a65099
KB		 2899 {
2900 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
2901 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
2902 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
2903 }
2904 }
2905 }
2906
2907 /* If != 0, fdata.cr_offset is the offset from the frame that
2908 holds the CR. */
2909 if (fdata.cr_offset != 0)
2910 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
2911
2912 /* If != 0, fdata.lr_offset is the offset from the frame that
2913 holds the LR. */
2914 if (fdata.lr_offset != 0)
2915 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
2916 /* The PC is found in the link register. */
2917 cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum];
2918
2919 /* If != 0, fdata.vrsave_offset is the offset from the frame that
2920 holds the VRSAVE. */
2921 if (fdata.vrsave_offset != 0)
2922 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
2923
2924 if (fdata.alloca_reg < 0)
2925 /* If no alloca register used, then fi->frame is the value of the
2926 %sp for this frame, and it is good enough. */
2927 cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2928 else
2929 cache->initial_sp = frame_unwind_register_unsigned (next_frame,
2930 fdata.alloca_reg);
2931
2932 return cache;
2933}
2934
2935static void
2936rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache,
2937 struct frame_id *this_id)
2938{
2939 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
2940 this_cache);
2941 (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame));
2942}
2943
2944static void
2945rs6000_frame_prev_register (struct frame_info *next_frame,
2946 void **this_cache,
2947 int regnum, int *optimizedp,
2948 enum lval_type *lvalp, CORE_ADDR *addrp,
2949 int *realnump, void *valuep)
2950{
2951 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
2952 this_cache);
1f67027d
AC		 2953 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
2954 optimizedp, lvalp, addrp, realnump, valuep);
61a65099
KB		 2955}
2956
2957static const struct frame_unwind rs6000_frame_unwind =
2958{
2959 NORMAL_FRAME,
2960 rs6000_frame_this_id,
2961 rs6000_frame_prev_register
2962};
2963
2964static const struct frame_unwind *
2965rs6000_frame_sniffer (struct frame_info *next_frame)
2966{
2967 return &rs6000_frame_unwind;
2968}
2969
2970\f
2971
2972static CORE_ADDR
2973rs6000_frame_base_address (struct frame_info *next_frame,
2974 void **this_cache)
2975{
2976 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
2977 this_cache);
2978 return info->initial_sp;
2979}
2980
2981static const struct frame_base rs6000_frame_base = {
2982 &rs6000_frame_unwind,
2983 rs6000_frame_base_address,
2984 rs6000_frame_base_address,
2985 rs6000_frame_base_address
2986};
2987
2988static const struct frame_base *
2989rs6000_frame_base_sniffer (struct frame_info *next_frame)
2990{
2991 return &rs6000_frame_base;
2992}
2993
7a78ae4e
ND		 2994/* Initialize the current architecture based on INFO. If possible, re-use an
2995 architecture from ARCHES, which is a list of architectures already created
2996 during this debugging session.
c906108c 2997
7a78ae4e 2998 Called e.g. at program startup, when reading a core file, and when reading
64366f1c 2999 a binary file. */
c906108c 3000
7a78ae4e
ND		 3001static struct gdbarch *
3002rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3003{
3004 struct gdbarch *gdbarch;
3005 struct gdbarch_tdep *tdep;
708ff411 3006 int wordsize, from_xcoff_exec, from_elf_exec, i, off;
7a78ae4e
ND		 3007 struct reg *regs;
3008 const struct variant *v;
3009 enum bfd_architecture arch;
3010 unsigned long mach;
3011 bfd abfd;
7b112f9c 3012 int sysv_abi;
5bf1c677 3013 asection *sect;
7a78ae4e 3014
9aa1e687 3015 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
7a78ae4e
ND		 3016 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3017
9aa1e687
KB		 3018 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3019 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3020
3021 sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3022
e712c1cf 3023 /* Check word size. If INFO is from a binary file, infer it from
64366f1c 3024 that, else choose a likely default. */
9aa1e687 3025 if (from_xcoff_exec)
c906108c 3026 {
11ed25ac 3027 if (bfd_xcoff_is_xcoff64 (info.abfd))
7a78ae4e
ND		 3028 wordsize = 8;
3029 else
3030 wordsize = 4;
c906108c 3031 }
9aa1e687
KB		 3032 else if (from_elf_exec)
3033 {
3034 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3035 wordsize = 8;
3036 else
3037 wordsize = 4;
3038 }
c906108c 3039 else
7a78ae4e 3040 {
27b15785
KB		 3041 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3042 wordsize = info.bfd_arch_info->bits_per_word /
3043 info.bfd_arch_info->bits_per_byte;
3044 else
3045 wordsize = 4;
7a78ae4e 3046 }
c906108c 3047
64366f1c 3048 /* Find a candidate among extant architectures. */
7a78ae4e
ND		 3049 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3050 arches != NULL;
3051 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3052 {
3053 /* Word size in the various PowerPC bfd_arch_info structs isn't
3054 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
64366f1c 3055 separate word size check. */
7a78ae4e 3056 tdep = gdbarch_tdep (arches->gdbarch);
4be87837 3057 if (tdep && tdep->wordsize == wordsize)
7a78ae4e
ND		 3058 return arches->gdbarch;
3059 }
c906108c 3060
7a78ae4e
ND		 3061 /* None found, create a new architecture from INFO, whose bfd_arch_info
3062 validity depends on the source:
3063 - executable useless
3064 - rs6000_host_arch() good
3065 - core file good
3066 - "set arch" trust blindly
3067 - GDB startup useless but harmless */
c906108c 3068
9aa1e687 3069 if (!from_xcoff_exec)
c906108c 3070 {
b732d07d 3071 arch = info.bfd_arch_info->arch;
7a78ae4e 3072 mach = info.bfd_arch_info->mach;
c906108c 3073 }
7a78ae4e 3074 else
c906108c 3075 {
7a78ae4e 3076 arch = bfd_arch_powerpc;
35cec841 3077 bfd_default_set_arch_mach (&abfd, arch, 0);
7a78ae4e 3078 info.bfd_arch_info = bfd_get_arch_info (&abfd);
35cec841 3079 mach = info.bfd_arch_info->mach;
7a78ae4e
ND		 3080 }
3081 tdep = xmalloc (sizeof (struct gdbarch_tdep));
3082 tdep->wordsize = wordsize;
5bf1c677
EZ		 3083
3084 /* For e500 executables, the apuinfo section is of help here. Such
3085 section contains the identifier and revision number of each
3086 Application-specific Processing Unit that is present on the
3087 chip. The content of the section is determined by the assembler
3088 which looks at each instruction and determines which unit (and
3089 which version of it) can execute it. In our case we just look for
3090 the existance of the section. */
3091
3092 if (info.abfd)
3093 {
3094 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
3095 if (sect)
3096 {
3097 arch = info.bfd_arch_info->arch;
3098 mach = bfd_mach_ppc_e500;
3099 bfd_default_set_arch_mach (&abfd, arch, mach);
3100 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3101 }
3102 }
3103
7a78ae4e 3104 gdbarch = gdbarch_alloc (&info, tdep);
7a78ae4e 3105
489461e2
EZ		 3106 /* Initialize the number of real and pseudo registers in each variant. */
3107 init_variants ();
3108
64366f1c 3109 /* Choose variant. */
7a78ae4e
ND		 3110 v = find_variant_by_arch (arch, mach);
3111 if (!v)
dd47e6fd
EZ		 3112 return NULL;
3113
7a78ae4e
ND		 3114 tdep->regs = v->regs;
3115
2188cbdd 3116 tdep->ppc_gp0_regnum = 0;
2188cbdd
EZ		 3117 tdep->ppc_toc_regnum = 2;
3118 tdep->ppc_ps_regnum = 65;
3119 tdep->ppc_cr_regnum = 66;
3120 tdep->ppc_lr_regnum = 67;
3121 tdep->ppc_ctr_regnum = 68;
3122 tdep->ppc_xer_regnum = 69;
3123 if (v->mach == bfd_mach_ppc_601)
3124 tdep->ppc_mq_regnum = 124;
708ff411 3125 else if (arch == bfd_arch_rs6000)
2188cbdd 3126 tdep->ppc_mq_regnum = 70;
e3f36dbd
KB		 3127 else
3128 tdep->ppc_mq_regnum = -1;
366f009f 3129 tdep->ppc_fp0_regnum = 32;
708ff411 3130 tdep->ppc_fpscr_regnum = (arch == bfd_arch_rs6000) ? 71 : 70;
f86a7158 3131 tdep->ppc_sr0_regnum = 71;
baffbae0
JB		 3132 tdep->ppc_vr0_regnum = -1;
3133 tdep->ppc_vrsave_regnum = -1;
6ced10dd 3134 tdep->ppc_ev0_upper_regnum = -1;
baffbae0
JB		 3135 tdep->ppc_ev0_regnum = -1;
3136 tdep->ppc_ev31_regnum = -1;
867e2dc5
JB		 3137 tdep->ppc_acc_regnum = -1;
3138 tdep->ppc_spefscr_regnum = -1;
2188cbdd 3139
c8001721
EZ		 3140 set_gdbarch_pc_regnum (gdbarch, 64);
3141 set_gdbarch_sp_regnum (gdbarch, 1);
0ba6dca9 3142 set_gdbarch_deprecated_fp_regnum (gdbarch, 1);
9f643768 3143 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
afd48b75 3144 if (sysv_abi && wordsize == 8)
05580c65 3145 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
e754ae69 3146 else if (sysv_abi && wordsize == 4)
05580c65 3147 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
afd48b75
AC		 3148 else
3149 {
3150 set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value);
a3c001ce 3151 set_gdbarch_store_return_value (gdbarch, rs6000_store_return_value);
afd48b75 3152 }
c8001721 3153
baffbae0
JB		 3154 /* Set lr_frame_offset. */
3155 if (wordsize == 8)
3156 tdep->lr_frame_offset = 16;
3157 else if (sysv_abi)
3158 tdep->lr_frame_offset = 4;
3159 else
3160 tdep->lr_frame_offset = 8;
3161
f86a7158
JB		 3162 if (v->arch == bfd_arch_rs6000)
3163 tdep->ppc_sr0_regnum = -1;
3164 else if (v->arch == bfd_arch_powerpc)
1fcc0bb8
EZ		 3165 switch (v->mach)
3166 {
3167 case bfd_mach_ppc:
412b3060 3168 tdep->ppc_sr0_regnum = -1;
1fcc0bb8
EZ		 3169 tdep->ppc_vr0_regnum = 71;
3170 tdep->ppc_vrsave_regnum = 104;
3171 break;
3172 case bfd_mach_ppc_7400:
3173 tdep->ppc_vr0_regnum = 119;
54c2a1e6 3174 tdep->ppc_vrsave_regnum = 152;
c8001721
EZ		 3175 break;
3176 case bfd_mach_ppc_e500:
c8001721 3177 tdep->ppc_toc_regnum = -1;
6ced10dd
JB		 3178 tdep->ppc_ev0_upper_regnum = 32;
3179 tdep->ppc_ev0_regnum = 73;
3180 tdep->ppc_ev31_regnum = 104;
3181 tdep->ppc_acc_regnum = 71;
3182 tdep->ppc_spefscr_regnum = 72;
383f0f5b
JB		 3183 tdep->ppc_fp0_regnum = -1;
3184 tdep->ppc_fpscr_regnum = -1;
f86a7158 3185 tdep->ppc_sr0_regnum = -1;
c8001721
EZ		 3186 set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read);
3187 set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write);
6ced10dd 3188 set_gdbarch_register_reggroup_p (gdbarch, e500_register_reggroup_p);
1fcc0bb8 3189 break;
f86a7158
JB		 3190
3191 case bfd_mach_ppc64:
3192 case bfd_mach_ppc_620:
3193 case bfd_mach_ppc_630:
3194 case bfd_mach_ppc_a35:
3195 case bfd_mach_ppc_rs64ii:
3196 case bfd_mach_ppc_rs64iii:
3197 /* These processor's register sets don't have segment registers. */
3198 tdep->ppc_sr0_regnum = -1;
3199 break;
1fcc0bb8 3200 }
f86a7158
JB		 3201 else
3202 internal_error (__FILE__, __LINE__,
3203 "rs6000_gdbarch_init: "
3204 "received unexpected BFD 'arch' value");
1fcc0bb8 3205
338ef23d
AC		 3206 /* Sanity check on registers. */
3207 gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0);
3208
56a6dfb9 3209 /* Select instruction printer. */
708ff411 3210 if (arch == bfd_arch_rs6000)
9364a0ef 3211 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
56a6dfb9 3212 else
9364a0ef 3213 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
7495d1dc 3214
7a78ae4e 3215 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
7a78ae4e
ND		 3216
3217 set_gdbarch_num_regs (gdbarch, v->nregs);
c8001721 3218 set_gdbarch_num_pseudo_regs (gdbarch, v->npregs);
7a78ae4e 3219 set_gdbarch_register_name (gdbarch, rs6000_register_name);
691d145a 3220 set_gdbarch_register_type (gdbarch, rs6000_register_type);
7a78ae4e
ND		 3221
3222 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3223 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3224 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3225 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3226 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3227 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3228 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
ab9fe00e
KB		 3229 if (sysv_abi)
3230 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
3231 else
3232 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4e409299 3233 set_gdbarch_char_signed (gdbarch, 0);
7a78ae4e 3234
11269d7e 3235 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
8b148df9
AC		 3236 if (sysv_abi && wordsize == 8)
3237 /* PPC64 SYSV. */
3238 set_gdbarch_frame_red_zone_size (gdbarch, 288);
3239 else if (!sysv_abi && wordsize == 4)
5bffac25
AC		 3240 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
3241 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
3242 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
3243 224. */
3244 set_gdbarch_frame_red_zone_size (gdbarch, 224);
7a78ae4e 3245
691d145a
JB		 3246 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
3247 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
3248 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
3249
18ed0c4e
JB		 3250 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
3251 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
2ea5f656
KB		 3252 /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments()
3253 is correct for the SysV ABI when the wordsize is 8, but I'm also
3254 fairly certain that ppc_sysv_abi_push_arguments() will give even
3255 worse results since it only works for 32-bit code. So, for the moment,
3256 we're better off calling rs6000_push_arguments() since it works for
3257 64-bit code. At some point in the future, this matter needs to be
3258 revisited. */
3259 if (sysv_abi && wordsize == 4)
77b2b6d4 3260 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
8be9034a
AC		 3261 else if (sysv_abi && wordsize == 8)
3262 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
9aa1e687 3263 else
77b2b6d4 3264 set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call);
7a78ae4e 3265
74055713 3266 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address);
7a78ae4e
ND		 3267
3268 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
3269 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
7a78ae4e
ND		 3270 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
3271
6066c3de
AC		 3272 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
3273 for the descriptor and ".FN" for the entry-point -- a user
3274 specifying "break FN" will unexpectedly end up with a breakpoint
3275 on the descriptor and not the function. This architecture method
3276 transforms any breakpoints on descriptors into breakpoints on the
3277 corresponding entry point. */
3278 if (sysv_abi && wordsize == 8)
3279 set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address);
3280
7a78ae4e
ND		 3281 /* Not sure on this. FIXMEmgo */
3282 set_gdbarch_frame_args_skip (gdbarch, 8);
3283
05580c65 3284 if (!sysv_abi)
b5622e8d 3285 set_gdbarch_deprecated_use_struct_convention (gdbarch, rs6000_use_struct_convention);
8e0662df 3286
15813d3f
AC		 3287 if (!sysv_abi)
3288 {
3289 /* Handle RS/6000 function pointers (which are really function
3290 descriptors). */
f517ea4e
PS		 3291 set_gdbarch_convert_from_func_ptr_addr (gdbarch,
3292 rs6000_convert_from_func_ptr_addr);
9aa1e687 3293 }
7a78ae4e 3294
143985b7
AF		 3295 /* Helpers for function argument information. */
3296 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
3297
7b112f9c 3298 /* Hook in ABI-specific overrides, if they have been registered. */
4be87837 3299 gdbarch_init_osabi (info, gdbarch);
7b112f9c 3300
61a65099
KB		 3301 switch (info.osabi)
3302 {
3303 case GDB_OSABI_NETBSD_AOUT:
3304 case GDB_OSABI_NETBSD_ELF:
3305 case GDB_OSABI_UNKNOWN:
3306 case GDB_OSABI_LINUX:
3307 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3308 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3309 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3310 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3311 break;
3312 default:
61a65099 3313 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
81332287
KB		 3314
3315 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3316 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3317 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3318 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
61a65099
KB		 3319 }
3320
ef5200c1
AC		 3321 if (from_xcoff_exec)
3322 {
3323 /* NOTE: jimix/2003-06-09: This test should really check for
3324 GDB_OSABI_AIX when that is defined and becomes
3325 available. (Actually, once things are properly split apart,
3326 the test goes away.) */
3327 /* RS6000/AIX does not support PT_STEP. Has to be simulated. */
3328 set_gdbarch_software_single_step (gdbarch, rs6000_software_single_step);
3329 }
3330
9f643768
JB		 3331 init_sim_regno_table (gdbarch);
3332
7a78ae4e 3333 return gdbarch;
c906108c
SS		 3334}
3335
7b112f9c
JT		 3336static void
3337rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
3338{
3339 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3340
3341 if (tdep == NULL)
3342 return;
3343
4be87837 3344 /* FIXME: Dump gdbarch_tdep. */
7b112f9c
JT		 3345}
3346
1fcc0bb8
EZ		 3347static struct cmd_list_element *info_powerpc_cmdlist = NULL;
3348
3349static void
3350rs6000_info_powerpc_command (char *args, int from_tty)
3351{
3352 help_list (info_powerpc_cmdlist, "info powerpc ", class_info, gdb_stdout);
3353}
3354
c906108c
SS		 3355/* Initialization code. */
3356
a78f21af 3357extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
b9362cc7 3358
c906108c 3359void
fba45db2 3360_initialize_rs6000_tdep (void)
c906108c 3361{
7b112f9c
JT		 3362 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
3363 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
1fcc0bb8
EZ		 3364
3365 /* Add root prefix command for "info powerpc" commands */
3366 add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command,
3367 "Various POWERPC info specific commands.",
3368 &info_powerpc_cmdlist, "info powerpc ", 0, &infolist);
c906108c 3369}
GDB Binutils - Deliverables
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