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27fd2f50 Q |
1 | /* Target-dependent code for the S+core architecture, for GDB, |
2 | the GNU Debugger. | |
3 | ||
0fb0cc75 | 4 | Copyright (C) 2006, 2007, 2008, 2009 Free Software Foundation, Inc. |
27fd2f50 Q |
5 | |
6 | Contributed by Qinwei (qinwei@sunnorth.com.cn) | |
7 | Contributed by Ching-Peng Lin (cplin@sunplus.com) | |
8 | ||
9 | This file is part of GDB. | |
10 | ||
11 | This program is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 13 | the Free Software Foundation; either version 3 of the License, or |
27fd2f50 Q |
14 | (at your option) any later version. |
15 | ||
16 | This program is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 22 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
27fd2f50 Q |
23 | |
24 | #ifndef SCORE_TDEP_H | |
25 | #define SCORE_TDEP_H | |
26 | #include "math.h" | |
27 | ||
28 | enum gdb_regnum | |
29 | { | |
30 | SCORE_SP_REGNUM = 0, | |
31 | SCORE_FP_REGNUM = 2, | |
32 | SCORE_RA_REGNUM = 3, | |
33 | SCORE_A0_REGNUM = 4, | |
34 | SCORE_AL_REGNUM = 7, | |
35 | SCORE_PC_REGNUM = 49, | |
36 | }; | |
37 | ||
38 | #define SCORE_A0_REGNUM 4 | |
39 | #define SCORE_A1_REGNUM 5 | |
40 | #define SCORE_REGSIZE 4 | |
5f814c3b DL |
41 | #define SCORE7_NUM_REGS 56 |
42 | #define SCORE3_NUM_REGS 50 | |
27fd2f50 Q |
43 | #define SCORE_BEGIN_ARG_REGNUM 4 |
44 | #define SCORE_LAST_ARG_REGNUM 7 | |
45 | ||
46 | #define SCORE_INSTLEN 4 | |
47 | #define SCORE16_INSTLEN 2 | |
48 | ||
5f814c3b DL |
49 | /* Forward declarations. */ |
50 | struct regset; | |
51 | ||
52 | /* Target-dependent structure in gdbarch */ | |
53 | struct gdbarch_tdep | |
54 | { | |
55 | /* Cached core file helpers. */ | |
56 | struct regset *gregset; | |
57 | }; | |
58 | ||
59 | /* Linux Core file support (dirty hack) | |
60 | ||
61 | S+core Linux register set definition, copy from S+core Linux */ | |
62 | struct pt_regs { | |
63 | /* Pad bytes for argument save space on the stack. */ | |
64 | unsigned long pad0[6]; /* may be 4,MIPS accept 6var,SCore accepts 4 Var--yuchen */ | |
65 | ||
66 | /* Saved main processor registers. */ | |
67 | unsigned long orig_r4; | |
68 | unsigned long regs[32]; | |
69 | ||
70 | /* Other saved registers. */ | |
71 | unsigned long cel; | |
72 | unsigned long ceh; | |
73 | ||
74 | unsigned long sr0; /*cnt*/ | |
75 | unsigned long sr1; /*lcr*/ | |
76 | unsigned long sr2; /*scr*/ | |
77 | ||
78 | /* saved cp0 registers */ | |
79 | unsigned long cp0_epc; | |
80 | unsigned long cp0_ema; | |
81 | unsigned long cp0_psr; | |
82 | unsigned long cp0_ecr; | |
83 | unsigned long cp0_condition; | |
84 | }; | |
85 | ||
86 | typedef struct pt_regs elf_gregset_t; | |
87 | ||
88 | #ifdef WITH_SIM | |
89 | ||
90 | #include <breakpoint.h> | |
91 | ||
92 | int soc_gh_can_use_watch(int type, int cnt); | |
93 | int soc_gh_add_watch(unsigned int addr, int len, int type); | |
94 | int soc_gh_del_watch(unsigned int addr, int len, int type); | |
95 | int soc_gh_stopped_by_watch(void); | |
96 | int soc_gh_add_hardbp(unsigned int addr); | |
97 | int soc_gh_del_hardbp(unsigned int addr); | |
98 | ||
99 | int score_target_can_use_watch(int type, int cnt, int ot); | |
100 | int score_stopped_by_watch(void); | |
101 | int score_target_insert_watchpoint (CORE_ADDR addr, int len, int type); | |
102 | int score_target_remove_watchpoint (CORE_ADDR addr, int len, int type); | |
103 | int score_target_insert_hw_breakpoint (struct gdbarch *gdbarch, struct bp_target_info * bp_tgt); | |
104 | int score_target_remove_hw_breakpoint (struct gdbarch *gdbarch, struct bp_target_info * bp_tgt); | |
105 | ||
106 | #define TARGET_HAS_HARDWARE_WATCHPOINTS | |
107 | ||
108 | #ifdef TARGET_CAN_USE_HARDWARE_WATCHPOINT | |
109 | #undef TARGET_CAN_USE_HARDWARE_WATCHPOINT | |
110 | ||
111 | #define TARGET_CAN_USE_HARDWARE_WATCHPOINT(type, cnt, ot) \ | |
112 | score_target_can_use_watch(type, cnt, ot) | |
113 | #endif | |
114 | ||
115 | #ifdef STOPPED_BY_WATCHPOINT | |
116 | #undef STOPPED_BY_WATCHPOINT | |
117 | ||
118 | #define STOPPED_BY_WATCHPOINT(w) \ | |
119 | score_stopped_by_watch() | |
120 | #endif | |
121 | ||
122 | #ifdef target_insert_watchpoint | |
123 | #undef target_insert_watchpoint | |
124 | ||
125 | #define target_insert_watchpoint(addr, len, type) \ | |
126 | score_target_insert_watchpoint (addr, len, type) | |
127 | #endif | |
128 | ||
129 | #ifdef target_remove_watchpoint | |
130 | #undef target_remove_watchpoint | |
131 | ||
132 | #define target_remove_watchpoint(addr, len, type) \ | |
133 | score_target_remove_watchpoint (addr, len, type) | |
134 | #endif | |
135 | ||
136 | #ifdef target_insert_hw_breakpoint | |
137 | #undef target_insert_hw_breakpoint | |
138 | ||
139 | #define target_insert_hw_breakpoint(gdbarch, bp_tgt) \ | |
140 | score_target_insert_hw_breakpoint (gdbarch, bp_tgt) | |
141 | #endif | |
142 | ||
143 | #ifdef target_remove_hw_breakpoint | |
144 | #undef target_remove_hw_breakpoint | |
145 | ||
146 | #define target_remove_hw_breakpoint(gdbarch, bp_tgt) \ | |
147 | score_target_remove_hw_breakpoint (gdbarch, bp_tgt) | |
148 | #endif | |
149 | ||
150 | #endif /* WITH_SIM */ | |
151 | ||
27fd2f50 | 152 | #endif /* SCORE_TDEP_H */ |