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[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
CommitLineData
85a453d5 1/* Target-dependent code for Renesas Super-H, for GDB.
0fd88904 2
197e01b6 3 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
0fd88904 4 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
c906108c 5
c5aa993b 6 This file is part of GDB.
c906108c 7
c5aa993b
JM		 8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
c906108c 12
c5aa993b
JM		 13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
c906108c 17
c5aa993b
JM		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
197e01b6
EZ		 20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
c906108c
SS		 22
23/*
c5aa993b
JM		 24 Contributed by Steve Chamberlain
25 sac@cygnus.com
c906108c
SS		 26 */
27
28#include "defs.h"
29#include "frame.h"
1c0159e0
CV		 30#include "frame-base.h"
31#include "frame-unwind.h"
32#include "dwarf2-frame.h"
c906108c 33#include "symtab.h"
c906108c
SS		 34#include "gdbtypes.h"
35#include "gdbcmd.h"
36#include "gdbcore.h"
37#include "value.h"
38#include "dis-asm.h"
73c1f219 39#include "inferior.h"
c906108c 40#include "gdb_string.h"
1c0159e0 41#include "gdb_assert.h"
b4a20239 42#include "arch-utils.h"
fb409745 43#include "floatformat.h"
4e052eda 44#include "regcache.h"
d16aafd8 45#include "doublest.h"
4be87837 46#include "osabi.h"
dda63807 47#include "reggroups.h"
c906108c 48
ab3b8126
JT		 49#include "sh-tdep.h"
50
d658f924 51#include "elf-bfd.h"
1a8629c7
MS		 52#include "solib-svr4.h"
53
55ff77ac 54/* sh flags */
283150cd
EZ		 55#include "elf/sh.h"
56/* registers numbers shared with the simulator */
1c922164 57#include "gdb/sim-sh.h"
283150cd 58
55ff77ac 59static void (*sh_show_regs) (void);
cc17453a 60
da962468 61#define SH_NUM_REGS 67
88e04cc1 62
1c0159e0 63struct sh_frame_cache
cc17453a 64{
1c0159e0
CV		 65 /* Base address. */
66 CORE_ADDR base;
67 LONGEST sp_offset;
68 CORE_ADDR pc;
69
70 /* Flag showing that a frame has been created in the prologue code. */
71 int uses_fp;
72
73 /* Saved registers. */
74 CORE_ADDR saved_regs[SH_NUM_REGS];
75 CORE_ADDR saved_sp;
63978407 76};
c906108c 77
fa88f677 78static const char *
cc17453a
EZ		 79sh_sh_register_name (int reg_nr)
80{
617daa0e
CV		 81 static char *register_names[] = {
82 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
83 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
84 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
85 "", "",
86 "", "", "", "", "", "", "", "",
87 "", "", "", "", "", "", "", "",
88 "", "",
89 "", "", "", "", "", "", "", "",
90 "", "", "", "", "", "", "", "",
da962468 91 "", "", "", "", "", "", "", "",
cc17453a
EZ		 92 };
93 if (reg_nr < 0)
94 return NULL;
95 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
96 return NULL;
97 return register_names[reg_nr];
98}
99
fa88f677 100static const char *
cc17453a
EZ		 101sh_sh3_register_name (int reg_nr)
102{
617daa0e
CV		 103 static char *register_names[] = {
104 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
105 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
106 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
107 "", "",
108 "", "", "", "", "", "", "", "",
109 "", "", "", "", "", "", "", "",
110 "ssr", "spc",
cc17453a
EZ		 111 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
112 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
da962468 113 "", "", "", "", "", "", "", "",
cc17453a
EZ		 114 };
115 if (reg_nr < 0)
116 return NULL;
117 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
118 return NULL;
119 return register_names[reg_nr];
120}
121
fa88f677 122static const char *
cc17453a
EZ		 123sh_sh3e_register_name (int reg_nr)
124{
617daa0e
CV		 125 static char *register_names[] = {
126 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
127 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
128 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
cc17453a 129 "fpul", "fpscr",
617daa0e
CV		 130 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
131 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
132 "ssr", "spc",
cc17453a
EZ		 133 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
134 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468 135 "", "", "", "", "", "", "", "",
cc17453a
EZ		 136 };
137 if (reg_nr < 0)
138 return NULL;
139 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
140 return NULL;
141 return register_names[reg_nr];
142}
143
2d188dd3
NC		 144static const char *
145sh_sh2e_register_name (int reg_nr)
146{
617daa0e
CV		 147 static char *register_names[] = {
148 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
149 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
150 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
2d188dd3 151 "fpul", "fpscr",
617daa0e
CV		 152 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
153 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
154 "", "",
2d188dd3
NC		 155 "", "", "", "", "", "", "", "",
156 "", "", "", "", "", "", "", "",
da962468
CV		 157 "", "", "", "", "", "", "", "",
158 };
159 if (reg_nr < 0)
160 return NULL;
161 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
162 return NULL;
163 return register_names[reg_nr];
164}
165
166static const char *
167sh_sh2a_register_name (int reg_nr)
168{
169 static char *register_names[] = {
170 /* general registers 0-15 */
171 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
172 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
173 /* 16 - 22 */
174 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
175 /* 23, 24 */
176 "fpul", "fpscr",
177 /* floating point registers 25 - 40 */
178 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
179 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
180 /* 41, 42 */
181 "", "",
182 /* 43 - 62. Banked registers. The bank number used is determined by
183 the bank register (63). */
184 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
185 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
186 "machb", "ivnb", "prb", "gbrb", "maclb",
187 /* 63: register bank number, not a real register but used to
188 communicate the register bank currently get/set. This register
189 is hidden to the user, who manipulates it using the pseudo
190 register called "bank" (67). See below. */
191 "",
192 /* 64 - 66 */
193 "ibcr", "ibnr", "tbr",
194 /* 67: register bank number, the user visible pseudo register. */
195 "bank",
196 /* double precision (pseudo) 68 - 75 */
197 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
198 };
199 if (reg_nr < 0)
200 return NULL;
201 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
202 return NULL;
203 return register_names[reg_nr];
204}
205
206static const char *
207sh_sh2a_nofpu_register_name (int reg_nr)
208{
209 static char *register_names[] = {
210 /* general registers 0-15 */
211 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
212 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
213 /* 16 - 22 */
214 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
215 /* 23, 24 */
216 "", "",
217 /* floating point registers 25 - 40 */
218 "", "", "", "", "", "", "", "",
219 "", "", "", "", "", "", "", "",
220 /* 41, 42 */
221 "", "",
222 /* 43 - 62. Banked registers. The bank number used is determined by
223 the bank register (63). */
224 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
225 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
226 "machb", "ivnb", "prb", "gbrb", "maclb",
227 /* 63: register bank number, not a real register but used to
228 communicate the register bank currently get/set. This register
229 is hidden to the user, who manipulates it using the pseudo
230 register called "bank" (67). See below. */
231 "",
232 /* 64 - 66 */
233 "ibcr", "ibnr", "tbr",
234 /* 67: register bank number, the user visible pseudo register. */
235 "bank",
236 /* double precision (pseudo) 68 - 75 */
237 "", "", "", "", "", "", "", "",
2d188dd3
NC		 238 };
239 if (reg_nr < 0)
240 return NULL;
241 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
242 return NULL;
243 return register_names[reg_nr];
244}
245
fa88f677 246static const char *
cc17453a
EZ		 247sh_sh_dsp_register_name (int reg_nr)
248{
617daa0e
CV		 249 static char *register_names[] = {
250 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
251 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
252 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
253 "", "dsr",
254 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
255 "y0", "y1", "", "", "", "", "", "mod",
256 "", "",
257 "rs", "re", "", "", "", "", "", "",
258 "", "", "", "", "", "", "", "",
da962468 259 "", "", "", "", "", "", "", "",
cc17453a
EZ		 260 };
261 if (reg_nr < 0)
262 return NULL;
263 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
264 return NULL;
265 return register_names[reg_nr];
266}
267
fa88f677 268static const char *
cc17453a
EZ		 269sh_sh3_dsp_register_name (int reg_nr)
270{
617daa0e
CV		 271 static char *register_names[] = {
272 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
273 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
274 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
275 "", "dsr",
276 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
277 "y0", "y1", "", "", "", "", "", "mod",
278 "ssr", "spc",
279 "rs", "re", "", "", "", "", "", "",
026a72f8
CV		 280 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
281 "", "", "", "", "", "", "", "",
da962468 282 "", "", "", "", "", "", "", "",
cc17453a
EZ		 283 };
284 if (reg_nr < 0)
285 return NULL;
286 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
287 return NULL;
288 return register_names[reg_nr];
289}
290
fa88f677 291static const char *
53116e27
EZ		 292sh_sh4_register_name (int reg_nr)
293{
617daa0e 294 static char *register_names[] = {
a38d2a54 295 /* general registers 0-15 */
617daa0e
CV		 296 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
297 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
a38d2a54 298 /* 16 - 22 */
617daa0e 299 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
a38d2a54 300 /* 23, 24 */
53116e27 301 "fpul", "fpscr",
a38d2a54 302 /* floating point registers 25 - 40 */
617daa0e
CV		 303 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
304 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
a38d2a54 305 /* 41, 42 */
617daa0e 306 "ssr", "spc",
a38d2a54 307 /* bank 0 43 - 50 */
53116e27 308 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
a38d2a54 309 /* bank 1 51 - 58 */
53116e27 310 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468
CV		 311 "", "", "", "", "", "", "", "",
312 /* pseudo bank register. */
313 "",
a38d2a54 314 /* double precision (pseudo) 59 - 66 */
617daa0e 315 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
a38d2a54 316 /* vectors (pseudo) 67 - 70 */
617daa0e 317 "fv0", "fv4", "fv8", "fv12",
a38d2a54
EZ		 318 /* FIXME: missing XF 71 - 86 */
319 /* FIXME: missing XD 87 - 94 */
53116e27
EZ		 320 };
321 if (reg_nr < 0)
322 return NULL;
323 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
324 return NULL;
325 return register_names[reg_nr];
326}
327
474e5826
CV		 328static const char *
329sh_sh4_nofpu_register_name (int reg_nr)
330{
331 static char *register_names[] = {
332 /* general registers 0-15 */
333 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
334 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
335 /* 16 - 22 */
336 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
337 /* 23, 24 */
338 "", "",
339 /* floating point registers 25 - 40 -- not for nofpu target */
340 "", "", "", "", "", "", "", "",
341 "", "", "", "", "", "", "", "",
342 /* 41, 42 */
343 "ssr", "spc",
344 /* bank 0 43 - 50 */
345 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
346 /* bank 1 51 - 58 */
347 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468
CV		 348 "", "", "", "", "", "", "", "",
349 /* pseudo bank register. */
350 "",
474e5826
CV		 351 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
352 "", "", "", "", "", "", "", "",
353 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
354 "", "", "", "",
355 };
356 if (reg_nr < 0)
357 return NULL;
358 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
359 return NULL;
360 return register_names[reg_nr];
361}
362
363static const char *
364sh_sh4al_dsp_register_name (int reg_nr)
365{
366 static char *register_names[] = {
367 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
368 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
369 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
370 "", "dsr",
371 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
372 "y0", "y1", "", "", "", "", "", "mod",
373 "ssr", "spc",
374 "rs", "re", "", "", "", "", "", "",
026a72f8
CV		 375 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
376 "", "", "", "", "", "", "", "",
da962468 377 "", "", "", "", "", "", "", "",
474e5826
CV		 378 };
379 if (reg_nr < 0)
380 return NULL;
381 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
382 return NULL;
383 return register_names[reg_nr];
384}
385
3117ed25 386static const unsigned char *
fba45db2 387sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
cc17453a
EZ		 388{
389 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
617daa0e
CV		 390 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
391
cc17453a
EZ		 392 *lenptr = sizeof (breakpoint);
393 return breakpoint;
394}
c906108c
SS		 395
396/* Prologue looks like
1c0159e0
CV		 397 mov.l r14,@-r15
398 sts.l pr,@-r15
399 mov.l <regs>,@-r15
400 sub <room_for_loca_vars>,r15
401 mov r15,r14
8db62801 402
1c0159e0 403 Actually it can be more complicated than this but that's it, basically.
c5aa993b 404 */
c906108c 405
1c0159e0
CV		 406#define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
407#define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
408
5f883edd
FF		 409/* JSR @Rm 0100mmmm00001011 */
410#define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
411
8db62801
EZ		 412/* STS.L PR,@-r15 0100111100100010
413 r15-4-->r15, PR-->(r15) */
c906108c 414#define IS_STS(x) ((x) == 0x4f22)
8db62801 415
03131d99
CV		 416/* STS.L MACL,@-r15 0100111100010010
417 r15-4-->r15, MACL-->(r15) */
418#define IS_MACL_STS(x) ((x) == 0x4f12)
419
8db62801
EZ		 420/* MOV.L Rm,@-r15 00101111mmmm0110
421 r15-4-->r15, Rm-->(R15) */
c906108c 422#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 423
8db62801
EZ		 424/* MOV r15,r14 0110111011110011
425 r15-->r14 */
c906108c 426#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ		 427
428/* ADD #imm,r15 01111111iiiiiiii
429 r15+imm-->r15 */
1c0159e0 430#define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 431
c906108c
SS		 432#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
433#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ		 434
435/* ADD r3,r15 0011111100111100
436 r15+r3-->r15 */
c906108c 437#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ		 438
439/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
8db62801 440 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
8db62801 441 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
f2ea0907
CV		 442/* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
443 make this entirely clear. */
1c0159e0
CV		 444/* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
445#define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
446
447/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
448#define IS_MOV_ARG_TO_REG(x) \
449 (((x) & 0xf00f) == 0x6003 && \
450 ((x) & 0x00f0) >= 0x0040 && \
451 ((x) & 0x00f0) <= 0x0070)
452/* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
453#define IS_MOV_ARG_TO_IND_R14(x) \
454 (((x) & 0xff0f) == 0x2e02 && \
455 ((x) & 0x00f0) >= 0x0040 && \
456 ((x) & 0x00f0) <= 0x0070)
457/* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
458#define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
459 (((x) & 0xff00) == 0x1e00 && \
460 ((x) & 0x00f0) >= 0x0040 && \
461 ((x) & 0x00f0) <= 0x0070)
462
463/* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
464#define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
465/* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
466#define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
03131d99
CV		 467/* MOVI20 #imm20,Rn 0000nnnniiii0000 */
468#define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
1c0159e0
CV		 469/* SUB Rn,R15 00111111nnnn1000 */
470#define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
8db62801 471
1c0159e0 472#define FPSCR_SZ (1 << 20)
cc17453a 473
1c0159e0
CV		 474/* The following instructions are used for epilogue testing. */
475#define IS_RESTORE_FP(x) ((x) == 0x6ef6)
476#define IS_RTS(x) ((x) == 0x000b)
477#define IS_LDS(x) ((x) == 0x4f26)
03131d99 478#define IS_MACL_LDS(x) ((x) == 0x4f16)
1c0159e0
CV		 479#define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
480#define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
481#define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
cc17453a 482
cc17453a
EZ		 483/* Disassemble an instruction. */
484static int
617daa0e 485gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
c906108c 486{
1c509ca8
JR		 487 info->endian = TARGET_BYTE_ORDER;
488 return print_insn_sh (memaddr, info);
283150cd
EZ		 489}
490
cc17453a 491static CORE_ADDR
1c0159e0
CV		 492sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
493 struct sh_frame_cache *cache)
617daa0e 494{
1c0159e0
CV		 495 ULONGEST inst;
496 CORE_ADDR opc;
497 int offset;
498 int sav_offset = 0;
c906108c 499 int r3_val = 0;
1c0159e0 500 int reg, sav_reg = -1;
cc17453a 501
1c0159e0
CV		 502 if (pc >= current_pc)
503 return current_pc;
cc17453a 504
1c0159e0 505 cache->uses_fp = 0;
cc17453a
EZ		 506 for (opc = pc + (2 * 28); pc < opc; pc += 2)
507 {
1c0159e0 508 inst = read_memory_unsigned_integer (pc, 2);
cc17453a 509 /* See where the registers will be saved to */
f2ea0907 510 if (IS_PUSH (inst))
cc17453a 511 {
1c0159e0
CV		 512 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
513 cache->sp_offset += 4;
cc17453a 514 }
f2ea0907 515 else if (IS_STS (inst))
cc17453a 516 {
1c0159e0
CV		 517 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
518 cache->sp_offset += 4;
cc17453a 519 }
03131d99
CV		 520 else if (IS_MACL_STS (inst))
521 {
522 cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
523 cache->sp_offset += 4;
524 }
f2ea0907 525 else if (IS_MOV_R3 (inst))
cc17453a 526 {
f2ea0907 527 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
cc17453a 528 }
f2ea0907 529 else if (IS_SHLL_R3 (inst))
cc17453a
EZ		 530 {
531 r3_val <<= 1;
532 }
f2ea0907 533 else if (IS_ADD_R3SP (inst))
cc17453a 534 {
1c0159e0 535 cache->sp_offset += -r3_val;
cc17453a 536 }
f2ea0907 537 else if (IS_ADD_IMM_SP (inst))
cc17453a 538 {
1c0159e0
CV		 539 offset = ((inst & 0xff) ^ 0x80) - 0x80;
540 cache->sp_offset -= offset;
c906108c 541 }
1c0159e0 542 else if (IS_MOVW_PCREL_TO_REG (inst))
617daa0e 543 {
1c0159e0
CV		 544 if (sav_reg < 0)
545 {
546 reg = GET_TARGET_REG (inst);
547 if (reg < 14)
548 {
549 sav_reg = reg;
a2b4a96c 550 offset = (inst & 0xff) << 1;
1c0159e0 551 sav_offset =
a2b4a96c 552 read_memory_integer ((pc + 4) + offset, 2);
1c0159e0
CV		 553 }
554 }
c906108c 555 }
1c0159e0 556 else if (IS_MOVL_PCREL_TO_REG (inst))
617daa0e 557 {
1c0159e0
CV		 558 if (sav_reg < 0)
559 {
a2b4a96c 560 reg = GET_TARGET_REG (inst);
1c0159e0
CV		 561 if (reg < 14)
562 {
563 sav_reg = reg;
a2b4a96c 564 offset = (inst & 0xff) << 2;
1c0159e0 565 sav_offset =
a2b4a96c 566 read_memory_integer (((pc & 0xfffffffc) + 4) + offset, 4);
1c0159e0
CV		 567 }
568 }
c906108c 569 }
03131d99
CV		 570 else if (IS_MOVI20 (inst))
571 {
572 if (sav_reg < 0)
573 {
574 reg = GET_TARGET_REG (inst);
575 if (reg < 14)
576 {
577 sav_reg = reg;
578 sav_offset = GET_SOURCE_REG (inst) << 16;
579 /* MOVI20 is a 32 bit instruction! */
580 pc += 2;
581 sav_offset |= read_memory_unsigned_integer (pc, 2);
582 /* Now sav_offset contains an unsigned 20 bit value.
583 It must still get sign extended. */
584 if (sav_offset & 0x00080000)
585 sav_offset |= 0xfff00000;
586 }
587 }
588 }
1c0159e0 589 else if (IS_SUB_REG_FROM_SP (inst))
617daa0e 590 {
1c0159e0
CV		 591 reg = GET_SOURCE_REG (inst);
592 if (sav_reg > 0 && reg == sav_reg)
593 {
594 sav_reg = -1;
595 }
596 cache->sp_offset += sav_offset;
c906108c 597 }
f2ea0907 598 else if (IS_FPUSH (inst))
c906108c 599 {
f2ea0907 600 if (read_register (FPSCR_REGNUM) & FPSCR_SZ)
c906108c 601 {
1c0159e0 602 cache->sp_offset += 8;
c906108c
SS		 603 }
604 else
605 {
1c0159e0 606 cache->sp_offset += 4;
c906108c
SS		 607 }
608 }
f2ea0907 609 else if (IS_MOV_SP_FP (inst))
617daa0e 610 {
960ccd7d 611 cache->uses_fp = 1;
1c0159e0
CV		 612 /* At this point, only allow argument register moves to other
613 registers or argument register moves to @(X,fp) which are
614 moving the register arguments onto the stack area allocated
615 by a former add somenumber to SP call. Don't allow moving
616 to an fp indirect address above fp + cache->sp_offset. */
617 pc += 2;
618 for (opc = pc + 12; pc < opc; pc += 2)
619 {
620 inst = read_memory_integer (pc, 2);
621 if (IS_MOV_ARG_TO_IND_R14 (inst))
617daa0e 622 {
1c0159e0
CV		 623 reg = GET_SOURCE_REG (inst);
624 if (cache->sp_offset > 0)
617daa0e 625 cache->saved_regs[reg] = cache->sp_offset;
1c0159e0
CV		 626 }
627 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
617daa0e 628 {
1c0159e0
CV		 629 reg = GET_SOURCE_REG (inst);
630 offset = (inst & 0xf) * 4;
631 if (cache->sp_offset > offset)
632 cache->saved_regs[reg] = cache->sp_offset - offset;
633 }
634 else if (IS_MOV_ARG_TO_REG (inst))
617daa0e 635 continue;
1c0159e0
CV		 636 else
637 break;
638 }
639 break;
640 }
5f883edd
FF		 641 else if (IS_JSR (inst))
642 {
643 /* We have found a jsr that has been scheduled into the prologue.
644 If we continue the scan and return a pc someplace after this,
645 then setting a breakpoint on this function will cause it to
646 appear to be called after the function it is calling via the
647 jsr, which will be very confusing. Most likely the next
648 instruction is going to be IS_MOV_SP_FP in the delay slot. If
649 so, note that before returning the current pc. */
650 inst = read_memory_integer (pc + 2, 2);
651 if (IS_MOV_SP_FP (inst))
652 cache->uses_fp = 1;
653 break;
654 }
617daa0e
CV		 655#if 0 /* This used to just stop when it found an instruction that
656 was not considered part of the prologue. Now, we just
657 keep going looking for likely instructions. */
c906108c
SS		 658 else
659 break;
2bfa91ee 660#endif
c906108c
SS		 661 }
662
1c0159e0
CV		 663 return pc;
664}
c906108c 665
1c0159e0 666/* Skip any prologue before the guts of a function */
c906108c 667
1c0159e0
CV		 668/* Skip the prologue using the debug information. If this fails we'll
669 fall back on the 'guess' method below. */
670static CORE_ADDR
671after_prologue (CORE_ADDR pc)
672{
673 struct symtab_and_line sal;
674 CORE_ADDR func_addr, func_end;
c906108c 675
1c0159e0
CV		 676 /* If we can not find the symbol in the partial symbol table, then
677 there is no hope we can determine the function's start address
678 with this code. */
679 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
680 return 0;
c906108c 681
1c0159e0
CV		 682 /* Get the line associated with FUNC_ADDR. */
683 sal = find_pc_line (func_addr, 0);
684
685 /* There are only two cases to consider. First, the end of the source line
686 is within the function bounds. In that case we return the end of the
687 source line. Second is the end of the source line extends beyond the
688 bounds of the current function. We need to use the slow code to
689 examine instructions in that case. */
690 if (sal.end < func_end)
691 return sal.end;
692 else
693 return 0;
c906108c
SS		 694}
695
1c0159e0
CV		 696static CORE_ADDR
697sh_skip_prologue (CORE_ADDR start_pc)
c906108c 698{
1c0159e0
CV		 699 CORE_ADDR pc;
700 struct sh_frame_cache cache;
701
702 /* See if we can determine the end of the prologue via the symbol table.
703 If so, then return either PC, or the PC after the prologue, whichever
704 is greater. */
705 pc = after_prologue (start_pc);
cc17453a 706
1c0159e0
CV		 707 /* If after_prologue returned a useful address, then use it. Else
708 fall back on the instruction skipping code. */
709 if (pc)
710 return max (pc, start_pc);
c906108c 711
1c0159e0
CV		 712 cache.sp_offset = -4;
713 pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache);
714 if (!cache.uses_fp)
715 return start_pc;
c906108c 716
1c0159e0
CV		 717 return pc;
718}
719
2e952408 720/* The ABI says:
9a5cef92
EZ		 721
722 Aggregate types not bigger than 8 bytes that have the same size and
723 alignment as one of the integer scalar types are returned in the
724 same registers as the integer type they match.
725
726 For example, a 2-byte aligned structure with size 2 bytes has the
727 same size and alignment as a short int, and will be returned in R0.
728 A 4-byte aligned structure with size 8 bytes has the same size and
729 alignment as a long long int, and will be returned in R0 and R1.
730
731 When an aggregate type is returned in R0 and R1, R0 contains the
732 first four bytes of the aggregate, and R1 contains the
733 remainder. If the size of the aggregate type is not a multiple of 4
734 bytes, the aggregate is tail-padded up to a multiple of 4
735 bytes. The value of the padding is undefined. For little-endian
736 targets the padding will appear at the most significant end of the
737 last element, for big-endian targets the padding appears at the
738 least significant end of the last element.
739
740 All other aggregate types are returned by address. The caller
741 function passes the address of an area large enough to hold the
742 aggregate value in R2. The called function stores the result in
7fe958be 743 this location.
9a5cef92
EZ		 744
745 To reiterate, structs smaller than 8 bytes could also be returned
746 in memory, if they don't pass the "same size and alignment as an
747 integer type" rule.
748
749 For example, in
750
751 struct s { char c[3]; } wibble;
752 struct s foo(void) { return wibble; }
753
754 the return value from foo() will be in memory, not
755 in R0, because there is no 3-byte integer type.
756
7fe958be
EZ		 757 Similarly, in
758
759 struct s { char c[2]; } wibble;
760 struct s foo(void) { return wibble; }
761
762 because a struct containing two chars has alignment 1, that matches
763 type char, but size 2, that matches type short. There's no integer
764 type that has alignment 1 and size 2, so the struct is returned in
765 memory.
766
9a5cef92
EZ		 767*/
768
1c0159e0
CV		 769static int
770sh_use_struct_convention (int gcc_p, struct type *type)
771{
772 int len = TYPE_LENGTH (type);
773 int nelem = TYPE_NFIELDS (type);
3f997a97
CV		 774
775 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
776 fit in two registers anyway) use struct convention. */
777 if (len != 1 && len != 2 && len != 4 && len != 8)
778 return 1;
779
780 /* Scalar types and aggregate types with exactly one field are aligned
781 by definition. They are returned in registers. */
782 if (nelem <= 1)
783 return 0;
784
785 /* If the first field in the aggregate has the same length as the entire
786 aggregate type, the type is returned in registers. */
787 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
788 return 0;
789
790 /* If the size of the aggregate is 8 bytes and the first field is
791 of size 4 bytes its alignment is equal to long long's alignment,
792 so it's returned in registers. */
793 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
794 return 0;
795
796 /* Otherwise use struct convention. */
797 return 1;
283150cd
EZ		 798}
799
cc17453a
EZ		 800/* Extract from an array REGBUF containing the (raw) register state
801 the address in which a function should return its structure value,
802 as a CORE_ADDR (or an expression that can be used as one). */
b3df3fff 803static CORE_ADDR
48db5a3c 804sh_extract_struct_value_address (struct regcache *regcache)
cc17453a 805{
48db5a3c 806 ULONGEST addr;
1c0159e0 807
48db5a3c
CV		 808 regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
809 return addr;
cc17453a
EZ		 810}
811
19f59343
MS		 812static CORE_ADDR
813sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
814{
815 return sp & ~3;
816}
817
55ff77ac 818/* Function: push_dummy_call (formerly push_arguments)
c906108c
SS		 819 Setup the function arguments for calling a function in the inferior.
820
85a453d5 821 On the Renesas SH architecture, there are four registers (R4 to R7)
c906108c
SS		 822 which are dedicated for passing function arguments. Up to the first
823 four arguments (depending on size) may go into these registers.
824 The rest go on the stack.
825
6df2bf50
MS		 826 MVS: Except on SH variants that have floating point registers.
827 In that case, float and double arguments are passed in the same
828 manner, but using FP registers instead of GP registers.
829
c906108c
SS		 830 Arguments that are smaller than 4 bytes will still take up a whole
831 register or a whole 32-bit word on the stack, and will be
832 right-justified in the register or the stack word. This includes
833 chars, shorts, and small aggregate types.
834
835 Arguments that are larger than 4 bytes may be split between two or
836 more registers. If there are not enough registers free, an argument
837 may be passed partly in a register (or registers), and partly on the
838 stack. This includes doubles, long longs, and larger aggregates.
839 As far as I know, there is no upper limit to the size of aggregates
840 that will be passed in this way; in other words, the convention of
841 passing a pointer to a large aggregate instead of a copy is not used.
842
6df2bf50 843 MVS: The above appears to be true for the SH variants that do not
55ff77ac 844 have an FPU, however those that have an FPU appear to copy the
6df2bf50
MS		 845 aggregate argument onto the stack (and not place it in registers)
846 if it is larger than 16 bytes (four GP registers).
847
c906108c
SS		 848 An exceptional case exists for struct arguments (and possibly other
849 aggregates such as arrays) if the size is larger than 4 bytes but
850 not a multiple of 4 bytes. In this case the argument is never split
851 between the registers and the stack, but instead is copied in its
852 entirety onto the stack, AND also copied into as many registers as
853 there is room for. In other words, space in registers permitting,
854 two copies of the same argument are passed in. As far as I can tell,
855 only the one on the stack is used, although that may be a function
856 of the level of compiler optimization. I suspect this is a compiler
857 bug. Arguments of these odd sizes are left-justified within the
858 word (as opposed to arguments smaller than 4 bytes, which are
859 right-justified).
c5aa993b 860
c906108c
SS		 861 If the function is to return an aggregate type such as a struct, it
862 is either returned in the normal return value register R0 (if its
863 size is no greater than one byte), or else the caller must allocate
864 space into which the callee will copy the return value (if the size
865 is greater than one byte). In this case, a pointer to the return
866 value location is passed into the callee in register R2, which does
867 not displace any of the other arguments passed in via registers R4
868 to R7. */
869
e5e33cd9
CV		 870/* Helper function to justify value in register according to endianess. */
871static char *
872sh_justify_value_in_reg (struct value *val, int len)
873{
874 static char valbuf[4];
875
617daa0e 876 memset (valbuf, 0, sizeof (valbuf));
e5e33cd9
CV		 877 if (len < 4)
878 {
879 /* value gets right-justified in the register or stack word */
880 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
0fd88904 881 memcpy (valbuf + (4 - len), (char *) value_contents (val), len);
e5e33cd9 882 else
0fd88904 883 memcpy (valbuf, (char *) value_contents (val), len);
e5e33cd9
CV		 884 return valbuf;
885 }
0fd88904 886 return (char *) value_contents (val);
617daa0e 887}
e5e33cd9
CV		 888
889/* Helper function to eval number of bytes to allocate on stack. */
890static CORE_ADDR
891sh_stack_allocsize (int nargs, struct value **args)
892{
893 int stack_alloc = 0;
894 while (nargs-- > 0)
4991999e 895 stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3);
e5e33cd9
CV		 896 return stack_alloc;
897}
898
899/* Helper functions for getting the float arguments right. Registers usage
900 depends on the ABI and the endianess. The comments should enlighten how
901 it's intended to work. */
902
903/* This array stores which of the float arg registers are already in use. */
904static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
905
906/* This function just resets the above array to "no reg used so far". */
907static void
908sh_init_flt_argreg (void)
909{
910 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
911}
912
913/* This function returns the next register to use for float arg passing.
914 It returns either a valid value between FLOAT_ARG0_REGNUM and
915 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
916 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
917
918 Note that register number 0 in flt_argreg_array corresponds with the
919 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
920 29) the parity of the register number is preserved, which is important
921 for the double register passing test (see the "argreg & 1" test below). */
922static int
923sh_next_flt_argreg (int len)
924{
925 int argreg;
926
927 /* First search for the next free register. */
617daa0e
CV		 928 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
929 ++argreg)
e5e33cd9
CV		 930 if (!flt_argreg_array[argreg])
931 break;
932
933 /* No register left? */
934 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
935 return FLOAT_ARGLAST_REGNUM + 1;
936
937 if (len == 8)
938 {
939 /* Doubles are always starting in a even register number. */
940 if (argreg & 1)
617daa0e 941 {
e5e33cd9
CV		 942 flt_argreg_array[argreg] = 1;
943
944 ++argreg;
945
617daa0e 946 /* No register left? */
e5e33cd9
CV		 947 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
948 return FLOAT_ARGLAST_REGNUM + 1;
949 }
950 /* Also mark the next register as used. */
951 flt_argreg_array[argreg + 1] = 1;
952 }
953 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
954 {
955 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
956 if (!flt_argreg_array[argreg + 1])
957 ++argreg;
958 }
959 flt_argreg_array[argreg] = 1;
960 return FLOAT_ARG0_REGNUM + argreg;
961}
962
afce3d2a
CV		 963/* Helper function which figures out, if a type is treated like a float type.
964
2e952408 965 The FPU ABIs have a special way how to treat types as float types.
afce3d2a
CV		 966 Structures with exactly one member, which is of type float or double, are
967 treated exactly as the base types float or double:
968
969 struct sf {
970 float f;
971 };
972
973 struct sd {
974 double d;
975 };
976
977 are handled the same way as just
978
979 float f;
980
981 double d;
982
983 As a result, arguments of these struct types are pushed into floating point
984 registers exactly as floats or doubles, using the same decision algorithm.
985
986 The same is valid if these types are used as function return types. The
987 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
988 or even using struct convention as it is for other structs. */
989
990static int
991sh_treat_as_flt_p (struct type *type)
992{
993 int len = TYPE_LENGTH (type);
994
995 /* Ordinary float types are obviously treated as float. */
996 if (TYPE_CODE (type) == TYPE_CODE_FLT)
997 return 1;
998 /* Otherwise non-struct types are not treated as float. */
999 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
1000 return 0;
1001 /* Otherwise structs with more than one memeber are not treated as float. */
1002 if (TYPE_NFIELDS (type) != 1)
1003 return 0;
1004 /* Otherwise if the type of that member is float, the whole type is
1005 treated as float. */
1006 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
1007 return 1;
1008 /* Otherwise it's not treated as float. */
1009 return 0;
1010}
1011
cc17453a 1012static CORE_ADDR
617daa0e 1013sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
7d9b040b 1014 struct value *function,
617daa0e 1015 struct regcache *regcache,
6df2bf50 1016 CORE_ADDR bp_addr, int nargs,
617daa0e 1017 struct value **args,
6df2bf50
MS		 1018 CORE_ADDR sp, int struct_return,
1019 CORE_ADDR struct_addr)
1020{
e5e33cd9
CV		 1021 int stack_offset = 0;
1022 int argreg = ARG0_REGNUM;
8748518b 1023 int flt_argreg = 0;
6df2bf50
MS		 1024 int argnum;
1025 struct type *type;
1026 CORE_ADDR regval;
1027 char *val;
8748518b 1028 int len, reg_size = 0;
afce3d2a
CV		 1029 int pass_on_stack = 0;
1030 int treat_as_flt;
6df2bf50
MS		 1031
1032 /* first force sp to a 4-byte alignment */
1033 sp = sh_frame_align (gdbarch, sp);
1034
6df2bf50 1035 if (struct_return)
1c0159e0 1036 regcache_cooked_write_unsigned (regcache,
617daa0e 1037 STRUCT_RETURN_REGNUM, struct_addr);
6df2bf50 1038
e5e33cd9
CV		 1039 /* make room on stack for args */
1040 sp -= sh_stack_allocsize (nargs, args);
1041
1042 /* Initialize float argument mechanism. */
1043 sh_init_flt_argreg ();
6df2bf50
MS		 1044
1045 /* Now load as many as possible of the first arguments into
1046 registers, and push the rest onto the stack. There are 16 bytes
1047 in four registers available. Loop thru args from first to last. */
e5e33cd9 1048 for (argnum = 0; argnum < nargs; argnum++)
6df2bf50 1049 {
4991999e 1050 type = value_type (args[argnum]);
6df2bf50 1051 len = TYPE_LENGTH (type);
e5e33cd9
CV		 1052 val = sh_justify_value_in_reg (args[argnum], len);
1053
1054 /* Some decisions have to be made how various types are handled.
1055 This also differs in different ABIs. */
1056 pass_on_stack = 0;
e5e33cd9
CV		 1057
1058 /* Find out the next register to use for a floating point value. */
afce3d2a
CV		 1059 treat_as_flt = sh_treat_as_flt_p (type);
1060 if (treat_as_flt)
617daa0e 1061 flt_argreg = sh_next_flt_argreg (len);
afce3d2a
CV		 1062 /* In contrast to non-FPU CPUs, arguments are never split between
1063 registers and stack. If an argument doesn't fit in the remaining
1064 registers it's always pushed entirely on the stack. */
1065 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
1066 pass_on_stack = 1;
48db5a3c 1067
6df2bf50
MS		 1068 while (len > 0)
1069 {
afce3d2a
CV		 1070 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
1071 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
1072 || pass_on_stack)))
617daa0e 1073 {
afce3d2a 1074 /* The data goes entirely on the stack, 4-byte aligned. */
e5e33cd9
CV		 1075 reg_size = (len + 3) & ~3;
1076 write_memory (sp + stack_offset, val, reg_size);
1077 stack_offset += reg_size;
6df2bf50 1078 }
afce3d2a 1079 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
6df2bf50 1080 {
e5e33cd9
CV		 1081 /* Argument goes in a float argument register. */
1082 reg_size = register_size (gdbarch, flt_argreg);
1083 regval = extract_unsigned_integer (val, reg_size);
2e952408
CV		 1084 /* In little endian mode, float types taking two registers
1085 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1086 be stored swapped in the argument registers. The below
1087 code first writes the first 32 bits in the next but one
1088 register, increments the val and len values accordingly
1089 and then proceeds as normal by writing the second 32 bits
1090 into the next register. */
1091 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE
1092 && TYPE_LENGTH (type) == 2 * reg_size)
1093 {
1094 regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
1095 regval);
1096 val += reg_size;
1097 len -= reg_size;
1098 regval = extract_unsigned_integer (val, reg_size);
1099 }
6df2bf50
MS		 1100 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
1101 }
afce3d2a 1102 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
e5e33cd9 1103 {
6df2bf50 1104 /* there's room in a register */
e5e33cd9
CV		 1105 reg_size = register_size (gdbarch, argreg);
1106 regval = extract_unsigned_integer (val, reg_size);
6df2bf50
MS		 1107 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1108 }
afce3d2a 1109 /* Store the value one register at a time or in one step on stack. */
e5e33cd9
CV		 1110 len -= reg_size;
1111 val += reg_size;
6df2bf50
MS		 1112 }
1113 }
1114
1115 /* Store return address. */
55ff77ac 1116 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
6df2bf50
MS		 1117
1118 /* Update stack pointer. */
1119 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1120
1121 return sp;
1122}
1123
1124static CORE_ADDR
617daa0e 1125sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
7d9b040b 1126 struct value *function,
617daa0e
CV		 1127 struct regcache *regcache,
1128 CORE_ADDR bp_addr,
1129 int nargs, struct value **args,
1130 CORE_ADDR sp, int struct_return,
6df2bf50 1131 CORE_ADDR struct_addr)
c906108c 1132{
e5e33cd9
CV		 1133 int stack_offset = 0;
1134 int argreg = ARG0_REGNUM;
c906108c
SS		 1135 int argnum;
1136 struct type *type;
1137 CORE_ADDR regval;
1138 char *val;
e5e33cd9 1139 int len, reg_size;
c906108c
SS		 1140
1141 /* first force sp to a 4-byte alignment */
19f59343 1142 sp = sh_frame_align (gdbarch, sp);
c906108c 1143
c906108c 1144 if (struct_return)
55ff77ac 1145 regcache_cooked_write_unsigned (regcache,
617daa0e 1146 STRUCT_RETURN_REGNUM, struct_addr);
c906108c 1147
e5e33cd9
CV		 1148 /* make room on stack for args */
1149 sp -= sh_stack_allocsize (nargs, args);
c906108c 1150
c906108c
SS		 1151 /* Now load as many as possible of the first arguments into
1152 registers, and push the rest onto the stack. There are 16 bytes
1153 in four registers available. Loop thru args from first to last. */
e5e33cd9 1154 for (argnum = 0; argnum < nargs; argnum++)
617daa0e 1155 {
4991999e 1156 type = value_type (args[argnum]);
c5aa993b 1157 len = TYPE_LENGTH (type);
e5e33cd9 1158 val = sh_justify_value_in_reg (args[argnum], len);
c906108c 1159
c906108c
SS		 1160 while (len > 0)
1161 {
e5e33cd9 1162 if (argreg > ARGLAST_REGNUM)
617daa0e 1163 {
e5e33cd9
CV		 1164 /* The remainder of the data goes entirely on the stack,
1165 4-byte aligned. */
1166 reg_size = (len + 3) & ~3;
1167 write_memory (sp + stack_offset, val, reg_size);
617daa0e 1168 stack_offset += reg_size;
c906108c 1169 }
e5e33cd9 1170 else if (argreg <= ARGLAST_REGNUM)
617daa0e 1171 {
3bbfbb92 1172 /* there's room in a register */
e5e33cd9
CV		 1173 reg_size = register_size (gdbarch, argreg);
1174 regval = extract_unsigned_integer (val, reg_size);
48db5a3c 1175 regcache_cooked_write_unsigned (regcache, argreg++, regval);
c906108c 1176 }
e5e33cd9
CV		 1177 /* Store the value reg_size bytes at a time. This means that things
1178 larger than reg_size bytes may go partly in registers and partly
c906108c 1179 on the stack. */
e5e33cd9
CV		 1180 len -= reg_size;
1181 val += reg_size;
c906108c
SS		 1182 }
1183 }
48db5a3c
CV		 1184
1185 /* Store return address. */
55ff77ac 1186 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
48db5a3c
CV		 1187
1188 /* Update stack pointer. */
1189 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1190
c906108c
SS		 1191 return sp;
1192}
1193
cc17453a
EZ		 1194/* Find a function's return value in the appropriate registers (in
1195 regbuf), and copy it into valbuf. Extract from an array REGBUF
1196 containing the (raw) register state a function return value of type
1197 TYPE, and copy that, in virtual format, into VALBUF. */
1198static void
3ffc5b9b
CV		 1199sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache,
1200 void *valbuf)
c906108c 1201{
cc17453a 1202 int len = TYPE_LENGTH (type);
3116c80a
EZ		 1203 int return_register = R0_REGNUM;
1204 int offset;
617daa0e 1205
cc17453a 1206 if (len <= 4)
3116c80a 1207 {
48db5a3c
CV		 1208 ULONGEST c;
1209
1210 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1211 store_unsigned_integer (valbuf, len, c);
3116c80a 1212 }
48db5a3c 1213 else if (len == 8)
3116c80a 1214 {
48db5a3c
CV		 1215 int i, regnum = R0_REGNUM;
1216 for (i = 0; i < len; i += 4)
617daa0e 1217 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
3116c80a
EZ		 1218 }
1219 else
8a3fe4f8 1220 error (_("bad size for return value"));
3116c80a
EZ		 1221}
1222
1223static void
3ffc5b9b
CV		 1224sh_extract_return_value_fpu (struct type *type, struct regcache *regcache,
1225 void *valbuf)
3116c80a 1226{
afce3d2a 1227 if (sh_treat_as_flt_p (type))
3116c80a 1228 {
48db5a3c
CV		 1229 int len = TYPE_LENGTH (type);
1230 int i, regnum = FP0_REGNUM;
1231 for (i = 0; i < len; i += 4)
2e952408
CV		 1232 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1233 regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i);
1234 else
1235 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
3116c80a 1236 }
cc17453a 1237 else
3ffc5b9b 1238 sh_extract_return_value_nofpu (type, regcache, valbuf);
cc17453a 1239}
c906108c 1240
cc17453a
EZ		 1241/* Write into appropriate registers a function return value
1242 of type TYPE, given in virtual format.
1243 If the architecture is sh4 or sh3e, store a function's return value
1244 in the R0 general register or in the FP0 floating point register,
1245 depending on the type of the return value. In all the other cases
3bbfbb92 1246 the result is stored in r0, left-justified. */
cc17453a 1247static void
3ffc5b9b
CV		 1248sh_store_return_value_nofpu (struct type *type, struct regcache *regcache,
1249 const void *valbuf)
cc17453a 1250{
48db5a3c
CV		 1251 ULONGEST val;
1252 int len = TYPE_LENGTH (type);
d19b71be 1253
48db5a3c 1254 if (len <= 4)
d19b71be 1255 {
48db5a3c
CV		 1256 val = extract_unsigned_integer (valbuf, len);
1257 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
d19b71be
MS		 1258 }
1259 else
48db5a3c
CV		 1260 {
1261 int i, regnum = R0_REGNUM;
1262 for (i = 0; i < len; i += 4)
617daa0e 1263 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
48db5a3c 1264 }
cc17453a 1265}
c906108c 1266
cc17453a 1267static void
3ffc5b9b
CV		 1268sh_store_return_value_fpu (struct type *type, struct regcache *regcache,
1269 const void *valbuf)
cc17453a 1270{
afce3d2a 1271 if (sh_treat_as_flt_p (type))
48db5a3c
CV		 1272 {
1273 int len = TYPE_LENGTH (type);
1274 int i, regnum = FP0_REGNUM;
1275 for (i = 0; i < len; i += 4)
c8a3b559
CV		 1276 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1277 regcache_raw_write (regcache, regnum++,
1278 (char *) valbuf + len - 4 - i);
1279 else
1280 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
48db5a3c 1281 }
cc17453a 1282 else
3ffc5b9b 1283 sh_store_return_value_nofpu (type, regcache, valbuf);
c906108c
SS		 1284}
1285
c0409442
CV		 1286static enum return_value_convention
1287sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *type,
1288 struct regcache *regcache,
18cf8b5b 1289 gdb_byte *readbuf, const gdb_byte *writebuf)
c0409442
CV		 1290{
1291 if (sh_use_struct_convention (0, type))
1292 return RETURN_VALUE_STRUCT_CONVENTION;
1293 if (writebuf)
3ffc5b9b 1294 sh_store_return_value_nofpu (type, regcache, writebuf);
c0409442 1295 else if (readbuf)
3ffc5b9b 1296 sh_extract_return_value_nofpu (type, regcache, readbuf);
c0409442
CV		 1297 return RETURN_VALUE_REGISTER_CONVENTION;
1298}
1299
1300static enum return_value_convention
1301sh_return_value_fpu (struct gdbarch *gdbarch, struct type *type,
1302 struct regcache *regcache,
18cf8b5b 1303 gdb_byte *readbuf, const gdb_byte *writebuf)
c0409442
CV		 1304{
1305 if (sh_use_struct_convention (0, type))
1306 return RETURN_VALUE_STRUCT_CONVENTION;
1307 if (writebuf)
3ffc5b9b 1308 sh_store_return_value_fpu (type, regcache, writebuf);
c0409442 1309 else if (readbuf)
3ffc5b9b 1310 sh_extract_return_value_fpu (type, regcache, readbuf);
c0409442
CV		 1311 return RETURN_VALUE_REGISTER_CONVENTION;
1312}
1313
c906108c
SS		 1314/* Print the registers in a form similar to the E7000 */
1315
1316static void
fba45db2 1317sh_generic_show_regs (void)
c906108c 1318{
a6b0a3f3 1319 printf_filtered (" PC %s SR %08lx PR %08lx MACH %08lx\n",
cc17453a 1320 paddr (read_register (PC_REGNUM)),
55ff77ac
CV		 1321 (long) read_register (SR_REGNUM),
1322 (long) read_register (PR_REGNUM),
a6b0a3f3 1323 (long) read_register (MACH_REGNUM));
cc17453a 1324
a6b0a3f3
AS		 1325 printf_filtered (
1326 " GBR %08lx VBR %08lx MACL %08lx\n",
cc17453a 1327 (long) read_register (GBR_REGNUM),
a6b0a3f3
AS		 1328 (long) read_register (VBR_REGNUM),
1329 (long) read_register (MACL_REGNUM));
cc17453a 1330
617daa0e 1331 printf_filtered
a6b0a3f3 1332 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV		 1333 (long) read_register (0), (long) read_register (1),
1334 (long) read_register (2), (long) read_register (3),
1335 (long) read_register (4), (long) read_register (5),
1336 (long) read_register (6), (long) read_register (7));
a6b0a3f3 1337 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV		 1338 (long) read_register (8), (long) read_register (9),
1339 (long) read_register (10), (long) read_register (11),
1340 (long) read_register (12), (long) read_register (13),
1341 (long) read_register (14), (long) read_register (15));
cc17453a 1342}
c906108c 1343
cc17453a 1344static void
fba45db2 1345sh3_show_regs (void)
cc17453a 1346{
a6b0a3f3 1347 printf_filtered (" PC %s SR %08lx PR %08lx MACH %08lx\n",
d4f3574e 1348 paddr (read_register (PC_REGNUM)),
55ff77ac
CV		 1349 (long) read_register (SR_REGNUM),
1350 (long) read_register (PR_REGNUM),
a6b0a3f3 1351 (long) read_register (MACH_REGNUM));
d4f3574e 1352
a6b0a3f3
AS		 1353 printf_filtered (
1354 " GBR %08lx VBR %08lx MACL %08lx\n",
d4f3574e 1355 (long) read_register (GBR_REGNUM),
a6b0a3f3
AS		 1356 (long) read_register (VBR_REGNUM),
1357 (long) read_register (MACL_REGNUM));
1358 printf_filtered (" SSR %08lx SPC %08lx\n",
617daa0e 1359 (long) read_register (SSR_REGNUM),
f2ea0907 1360 (long) read_register (SPC_REGNUM));
c906108c 1361
617daa0e 1362 printf_filtered
a6b0a3f3 1363 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV		 1364 (long) read_register (0), (long) read_register (1),
1365 (long) read_register (2), (long) read_register (3),
1366 (long) read_register (4), (long) read_register (5),
1367 (long) read_register (6), (long) read_register (7));
a6b0a3f3 1368 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV		 1369 (long) read_register (8), (long) read_register (9),
1370 (long) read_register (10), (long) read_register (11),
1371 (long) read_register (12), (long) read_register (13),
1372 (long) read_register (14), (long) read_register (15));
c906108c
SS		 1373}
1374
53116e27 1375
2d188dd3
NC		 1376static void
1377sh2e_show_regs (void)
1378{
a6b0a3f3 1379 printf_filtered (" PC %s SR %08lx PR %08lx MACH %08lx\n",
2d188dd3
NC		 1380 paddr (read_register (PC_REGNUM)),
1381 (long) read_register (SR_REGNUM),
1382 (long) read_register (PR_REGNUM),
a6b0a3f3 1383 (long) read_register (MACH_REGNUM));
2d188dd3 1384
a6b0a3f3
AS		 1385 printf_filtered (
1386 " GBR %08lx VBR %08lx MACL %08lx\n",
2d188dd3 1387 (long) read_register (GBR_REGNUM),
a6b0a3f3
AS		 1388 (long) read_register (VBR_REGNUM),
1389 (long) read_register (MACL_REGNUM));
1390 printf_filtered (
1391 " SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1392 (long) read_register (SSR_REGNUM),
1393 (long) read_register (SPC_REGNUM),
617daa0e
CV		 1394 (long) read_register (FPUL_REGNUM),
1395 (long) read_register (FPSCR_REGNUM));
1396
1397 printf_filtered
a6b0a3f3 1398 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV		 1399 (long) read_register (0), (long) read_register (1),
1400 (long) read_register (2), (long) read_register (3),
1401 (long) read_register (4), (long) read_register (5),
1402 (long) read_register (6), (long) read_register (7));
a6b0a3f3 1403 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV		 1404 (long) read_register (8), (long) read_register (9),
1405 (long) read_register (10), (long) read_register (11),
1406 (long) read_register (12), (long) read_register (13),
1407 (long) read_register (14), (long) read_register (15));
1408
a6b0a3f3
AS		 1409 printf_filtered ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1410 (long) read_register (FP0_REGNUM + 0),
1411 (long) read_register (FP0_REGNUM + 1),
1412 (long) read_register (FP0_REGNUM + 2),
1413 (long) read_register (FP0_REGNUM + 3),
1414 (long) read_register (FP0_REGNUM + 4),
1415 (long) read_register (FP0_REGNUM + 5),
1416 (long) read_register (FP0_REGNUM + 6),
1417 (long) read_register (FP0_REGNUM + 7));
1418 printf_filtered ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1419 (long) read_register (FP0_REGNUM + 8),
1420 (long) read_register (FP0_REGNUM + 9),
1421 (long) read_register (FP0_REGNUM + 10),
1422 (long) read_register (FP0_REGNUM + 11),
1423 (long) read_register (FP0_REGNUM + 12),
1424 (long) read_register (FP0_REGNUM + 13),
1425 (long) read_register (FP0_REGNUM + 14),
1426 (long) read_register (FP0_REGNUM + 15));
2d188dd3
NC		 1427}
1428
da962468
CV		 1429static void
1430sh2a_show_regs (void)
1431{
1432 int pr = read_register (FPSCR_REGNUM) & 0x80000;
a6b0a3f3 1433 printf_filtered (" PC %s SR %08lx PR %08lx MACH %08lx\n",
da962468
CV		 1434 paddr (read_register (PC_REGNUM)),
1435 (long) read_register (SR_REGNUM),
1436 (long) read_register (PR_REGNUM),
a6b0a3f3 1437 (long) read_register (MACH_REGNUM));
da962468 1438
a6b0a3f3
AS		 1439 printf_filtered (
1440 " GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
da962468
CV		 1441 (long) read_register (GBR_REGNUM),
1442 (long) read_register (VBR_REGNUM),
a6b0a3f3
AS		 1443 (long) read_register (TBR_REGNUM),
1444 (long) read_register (MACL_REGNUM));
1445 printf_filtered (
1446 " SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1447 (long) read_register (SSR_REGNUM),
1448 (long) read_register (SPC_REGNUM),
da962468
CV		 1449 (long) read_register (FPUL_REGNUM),
1450 (long) read_register (FPSCR_REGNUM));
1451
a6b0a3f3 1452 printf_filtered ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
da962468
CV		 1453 (long) read_register (0), (long) read_register (1),
1454 (long) read_register (2), (long) read_register (3),
1455 (long) read_register (4), (long) read_register (5),
1456 (long) read_register (6), (long) read_register (7));
a6b0a3f3 1457 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
da962468
CV		 1458 (long) read_register (8), (long) read_register (9),
1459 (long) read_register (10), (long) read_register (11),
1460 (long) read_register (12), (long) read_register (13),
1461 (long) read_register (14), (long) read_register (15));
1462
a6b0a3f3
AS		 1463 printf_filtered (
1464 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1465 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
da962468
CV		 1466 (long) read_register (FP0_REGNUM + 0),
1467 (long) read_register (FP0_REGNUM + 1),
1468 (long) read_register (FP0_REGNUM + 2),
1469 (long) read_register (FP0_REGNUM + 3),
1470 (long) read_register (FP0_REGNUM + 4),
1471 (long) read_register (FP0_REGNUM + 5),
1472 (long) read_register (FP0_REGNUM + 6),
1473 (long) read_register (FP0_REGNUM + 7));
a6b0a3f3
AS		 1474 printf_filtered (
1475 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1476 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
da962468
CV		 1477 (long) read_register (FP0_REGNUM + 8),
1478 (long) read_register (FP0_REGNUM + 9),
1479 (long) read_register (FP0_REGNUM + 10),
1480 (long) read_register (FP0_REGNUM + 11),
1481 (long) read_register (FP0_REGNUM + 12),
1482 (long) read_register (FP0_REGNUM + 13),
1483 (long) read_register (FP0_REGNUM + 14),
1484 (long) read_register (FP0_REGNUM + 15));
1485 printf_filtered ("BANK=%-3d\n", (int) read_register (BANK_REGNUM));
a6b0a3f3
AS		 1486 printf_filtered (
1487 "R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
da962468
CV		 1488 (long) read_register (R0_BANK0_REGNUM + 0),
1489 (long) read_register (R0_BANK0_REGNUM + 1),
1490 (long) read_register (R0_BANK0_REGNUM + 2),
1491 (long) read_register (R0_BANK0_REGNUM + 3),
1492 (long) read_register (R0_BANK0_REGNUM + 4),
1493 (long) read_register (R0_BANK0_REGNUM + 5),
1494 (long) read_register (R0_BANK0_REGNUM + 6),
1495 (long) read_register (R0_BANK0_REGNUM + 7));
a6b0a3f3 1496 printf_filtered ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
da962468
CV		 1497 (long) read_register (R0_BANK0_REGNUM + 8),
1498 (long) read_register (R0_BANK0_REGNUM + 9),
1499 (long) read_register (R0_BANK0_REGNUM + 10),
1500 (long) read_register (R0_BANK0_REGNUM + 11),
1501 (long) read_register (R0_BANK0_REGNUM + 12),
1502 (long) read_register (R0_BANK0_REGNUM + 13),
1503 (long) read_register (R0_BANK0_REGNUM + 14));
1504 printf_filtered ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1505 (long) read_register (R0_BANK0_REGNUM + 15),
1506 (long) read_register (R0_BANK0_REGNUM + 16),
1507 (long) read_register (R0_BANK0_REGNUM + 17),
1508 (long) read_register (R0_BANK0_REGNUM + 18),
1509 (long) read_register (R0_BANK0_REGNUM + 19));
1510}
1511
1512static void
1513sh2a_nofpu_show_regs (void)
1514{
1515 int pr = read_register (FPSCR_REGNUM) & 0x80000;
a6b0a3f3 1516 printf_filtered (" PC %s SR %08lx PR %08lx MACH %08lx\n",
da962468
CV		 1517 paddr (read_register (PC_REGNUM)),
1518 (long) read_register (SR_REGNUM),
1519 (long) read_register (PR_REGNUM),
a6b0a3f3 1520 (long) read_register (MACH_REGNUM));
da962468 1521
a6b0a3f3
AS		 1522 printf_filtered (
1523 " GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
da962468
CV		 1524 (long) read_register (GBR_REGNUM),
1525 (long) read_register (VBR_REGNUM),
a6b0a3f3
AS		 1526 (long) read_register (TBR_REGNUM),
1527 (long) read_register (MACL_REGNUM));
1528 printf_filtered (
1529 " SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1530 (long) read_register (SSR_REGNUM),
1531 (long) read_register (SPC_REGNUM),
da962468
CV		 1532 (long) read_register (FPUL_REGNUM),
1533 (long) read_register (FPSCR_REGNUM));
1534
a6b0a3f3 1535 printf_filtered ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
da962468
CV		 1536 (long) read_register (0), (long) read_register (1),
1537 (long) read_register (2), (long) read_register (3),
1538 (long) read_register (4), (long) read_register (5),
1539 (long) read_register (6), (long) read_register (7));
a6b0a3f3 1540 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
da962468
CV		 1541 (long) read_register (8), (long) read_register (9),
1542 (long) read_register (10), (long) read_register (11),
1543 (long) read_register (12), (long) read_register (13),
1544 (long) read_register (14), (long) read_register (15));
1545
1546 printf_filtered ("BANK=%-3d\n", (int) read_register (BANK_REGNUM));
a6b0a3f3
AS		 1547 printf_filtered (
1548 "R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
da962468
CV		 1549 (long) read_register (R0_BANK0_REGNUM + 0),
1550 (long) read_register (R0_BANK0_REGNUM + 1),
1551 (long) read_register (R0_BANK0_REGNUM + 2),
1552 (long) read_register (R0_BANK0_REGNUM + 3),
1553 (long) read_register (R0_BANK0_REGNUM + 4),
1554 (long) read_register (R0_BANK0_REGNUM + 5),
1555 (long) read_register (R0_BANK0_REGNUM + 6),
1556 (long) read_register (R0_BANK0_REGNUM + 7));
a6b0a3f3 1557 printf_filtered ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
da962468
CV		 1558 (long) read_register (R0_BANK0_REGNUM + 8),
1559 (long) read_register (R0_BANK0_REGNUM + 9),
1560 (long) read_register (R0_BANK0_REGNUM + 10),
1561 (long) read_register (R0_BANK0_REGNUM + 11),
1562 (long) read_register (R0_BANK0_REGNUM + 12),
1563 (long) read_register (R0_BANK0_REGNUM + 13),
1564 (long) read_register (R0_BANK0_REGNUM + 14));
1565 printf_filtered ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1566 (long) read_register (R0_BANK0_REGNUM + 15),
1567 (long) read_register (R0_BANK0_REGNUM + 16),
1568 (long) read_register (R0_BANK0_REGNUM + 17),
1569 (long) read_register (R0_BANK0_REGNUM + 18),
1570 (long) read_register (R0_BANK0_REGNUM + 19));
1571}
1572
cc17453a 1573static void
fba45db2 1574sh3e_show_regs (void)
cc17453a 1575{
a6b0a3f3 1576 printf_filtered (" PC %s SR %08lx PR %08lx MACH %08lx\n",
cc17453a 1577 paddr (read_register (PC_REGNUM)),
55ff77ac
CV		 1578 (long) read_register (SR_REGNUM),
1579 (long) read_register (PR_REGNUM),
a6b0a3f3 1580 (long) read_register (MACH_REGNUM));
cc17453a 1581
a6b0a3f3
AS		 1582 printf_filtered (
1583 " GBR %08lx VBR %08lx MACL %08lx\n",
cc17453a 1584 (long) read_register (GBR_REGNUM),
a6b0a3f3
AS		 1585 (long) read_register (VBR_REGNUM),
1586 (long) read_register (MACL_REGNUM));
1587 printf_filtered (
1588 " SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
f2ea0907 1589 (long) read_register (SSR_REGNUM),
a6b0a3f3 1590 (long) read_register (SPC_REGNUM),
f2ea0907
CV		 1591 (long) read_register (FPUL_REGNUM),
1592 (long) read_register (FPSCR_REGNUM));
c906108c 1593
617daa0e 1594 printf_filtered
a6b0a3f3 1595 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV		 1596 (long) read_register (0), (long) read_register (1),
1597 (long) read_register (2), (long) read_register (3),
1598 (long) read_register (4), (long) read_register (5),
1599 (long) read_register (6), (long) read_register (7));
a6b0a3f3 1600 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV		 1601 (long) read_register (8), (long) read_register (9),
1602 (long) read_register (10), (long) read_register (11),
1603 (long) read_register (12), (long) read_register (13),
1604 (long) read_register (14), (long) read_register (15));
1605
a6b0a3f3
AS		 1606 printf_filtered ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1607 (long) read_register (FP0_REGNUM + 0),
1608 (long) read_register (FP0_REGNUM + 1),
1609 (long) read_register (FP0_REGNUM + 2),
1610 (long) read_register (FP0_REGNUM + 3),
1611 (long) read_register (FP0_REGNUM + 4),
1612 (long) read_register (FP0_REGNUM + 5),
1613 (long) read_register (FP0_REGNUM + 6),
1614 (long) read_register (FP0_REGNUM + 7));
1615 printf_filtered ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1616 (long) read_register (FP0_REGNUM + 8),
1617 (long) read_register (FP0_REGNUM + 9),
1618 (long) read_register (FP0_REGNUM + 10),
1619 (long) read_register (FP0_REGNUM + 11),
1620 (long) read_register (FP0_REGNUM + 12),
1621 (long) read_register (FP0_REGNUM + 13),
1622 (long) read_register (FP0_REGNUM + 14),
1623 (long) read_register (FP0_REGNUM + 15));
cc17453a
EZ		 1624}
1625
1626static void
fba45db2 1627sh3_dsp_show_regs (void)
c906108c 1628{
a6b0a3f3 1629 printf_filtered (" PC %s SR %08lx PR %08lx MACH %08lx\n",
cc17453a 1630 paddr (read_register (PC_REGNUM)),
55ff77ac
CV		 1631 (long) read_register (SR_REGNUM),
1632 (long) read_register (PR_REGNUM),
a6b0a3f3 1633 (long) read_register (MACH_REGNUM));
c906108c 1634
a6b0a3f3
AS		 1635 printf_filtered (
1636 " GBR %08lx VBR %08lx MACL %08lx\n",
cc17453a 1637 (long) read_register (GBR_REGNUM),
a6b0a3f3
AS		 1638 (long) read_register (VBR_REGNUM),
1639 (long) read_register (MACL_REGNUM));
cc17453a 1640
a6b0a3f3 1641 printf_filtered (" SSR %08lx SPC %08lx DSR %08lx\n",
f2ea0907 1642 (long) read_register (SSR_REGNUM),
a6b0a3f3
AS		 1643 (long) read_register (SPC_REGNUM),
1644 (long) read_register (DSR_REGNUM));
617daa0e
CV		 1645
1646 printf_filtered
a6b0a3f3 1647 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV		 1648 (long) read_register (0), (long) read_register (1),
1649 (long) read_register (2), (long) read_register (3),
1650 (long) read_register (4), (long) read_register (5),
1651 (long) read_register (6), (long) read_register (7));
a6b0a3f3 1652 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV		 1653 (long) read_register (8), (long) read_register (9),
1654 (long) read_register (10), (long) read_register (11),
1655 (long) read_register (12), (long) read_register (13),
1656 (long) read_register (14), (long) read_register (15));
1657
1658 printf_filtered
1659 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1660 (long) read_register (A0G_REGNUM) & 0xff,
1661 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1662 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1663 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
cc17453a 1664 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
f2ea0907
CV		 1665 (long) read_register (A1G_REGNUM) & 0xff,
1666 (long) read_register (A1_REGNUM),
1667 (long) read_register (M1_REGNUM),
1668 (long) read_register (X1_REGNUM),
1669 (long) read_register (Y1_REGNUM),
1670 (long) read_register (RE_REGNUM));
c906108c
SS		 1671}
1672
cc17453a 1673static void
fba45db2 1674sh4_show_regs (void)
cc17453a 1675{
f2ea0907 1676 int pr = read_register (FPSCR_REGNUM) & 0x80000;
a6b0a3f3 1677 printf_filtered (" PC %s SR %08lx PR %08lx MACH %08lx\n",
cc17453a 1678 paddr (read_register (PC_REGNUM)),
55ff77ac
CV		 1679 (long) read_register (SR_REGNUM),
1680 (long) read_register (PR_REGNUM),
a6b0a3f3 1681 (long) read_register (MACH_REGNUM));
cc17453a 1682
a6b0a3f3
AS		 1683 printf_filtered (
1684 " GBR %08lx VBR %08lx MACL %08lx\n",
cc17453a 1685 (long) read_register (GBR_REGNUM),
a6b0a3f3
AS		 1686 (long) read_register (VBR_REGNUM),
1687 (long) read_register (MACL_REGNUM));
1688 printf_filtered (
1689 " SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
f2ea0907 1690 (long) read_register (SSR_REGNUM),
a6b0a3f3 1691 (long) read_register (SPC_REGNUM),
f2ea0907
CV		 1692 (long) read_register (FPUL_REGNUM),
1693 (long) read_register (FPSCR_REGNUM));
cc17453a 1694
a6b0a3f3
AS		 1695 printf_filtered ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1696 (long) read_register (0), (long) read_register (1),
1697 (long) read_register (2), (long) read_register (3),
1698 (long) read_register (4), (long) read_register (5),
1699 (long) read_register (6), (long) read_register (7));
1700 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV		 1701 (long) read_register (8), (long) read_register (9),
1702 (long) read_register (10), (long) read_register (11),
1703 (long) read_register (12), (long) read_register (13),
1704 (long) read_register (14), (long) read_register (15));
cc17453a 1705
a6b0a3f3
AS		 1706 printf_filtered (
1707 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1708 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
cc17453a
EZ		 1709 (long) read_register (FP0_REGNUM + 0),
1710 (long) read_register (FP0_REGNUM + 1),
1711 (long) read_register (FP0_REGNUM + 2),
1712 (long) read_register (FP0_REGNUM + 3),
1713 (long) read_register (FP0_REGNUM + 4),
1714 (long) read_register (FP0_REGNUM + 5),
1715 (long) read_register (FP0_REGNUM + 6),
1716 (long) read_register (FP0_REGNUM + 7));
a6b0a3f3
AS		 1717 printf_filtered (
1718 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1719 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
cc17453a
EZ		 1720 (long) read_register (FP0_REGNUM + 8),
1721 (long) read_register (FP0_REGNUM + 9),
1722 (long) read_register (FP0_REGNUM + 10),
1723 (long) read_register (FP0_REGNUM + 11),
1724 (long) read_register (FP0_REGNUM + 12),
1725 (long) read_register (FP0_REGNUM + 13),
1726 (long) read_register (FP0_REGNUM + 14),
1727 (long) read_register (FP0_REGNUM + 15));
1728}
1729
474e5826
CV		 1730static void
1731sh4_nofpu_show_regs (void)
1732{
a6b0a3f3 1733 printf_filtered (" PC %s SR %08lx PR %08lx MACH %08lx\n",
474e5826
CV		 1734 paddr (read_register (PC_REGNUM)),
1735 (long) read_register (SR_REGNUM),
1736 (long) read_register (PR_REGNUM),
a6b0a3f3 1737 (long) read_register (MACH_REGNUM));
474e5826 1738
a6b0a3f3
AS		 1739 printf_filtered (
1740 " GBR %08lx VBR %08lx MACL %08lx\n",
474e5826 1741 (long) read_register (GBR_REGNUM),
a6b0a3f3
AS		 1742 (long) read_register (VBR_REGNUM),
1743 (long) read_register (MACL_REGNUM));
1744 printf_filtered (
1745 " SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
474e5826 1746 (long) read_register (SSR_REGNUM),
a6b0a3f3
AS		 1747 (long) read_register (SPC_REGNUM),
1748 (long) read_register (FPUL_REGNUM),
1749 (long) read_register (FPSCR_REGNUM));
474e5826 1750
a6b0a3f3
AS		 1751 printf_filtered ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1752 (long) read_register (0), (long) read_register (1),
1753 (long) read_register (2), (long) read_register (3),
1754 (long) read_register (4), (long) read_register (5),
1755 (long) read_register (6), (long) read_register (7));
1756 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
474e5826
CV		 1757 (long) read_register (8), (long) read_register (9),
1758 (long) read_register (10), (long) read_register (11),
1759 (long) read_register (12), (long) read_register (13),
1760 (long) read_register (14), (long) read_register (15));
1761}
1762
cc17453a 1763static void
fba45db2 1764sh_dsp_show_regs (void)
cc17453a 1765{
a6b0a3f3
AS		 1766
1767 printf_filtered (" PC %s SR %08lx PR %08lx MACH %08lx\n",
cc17453a 1768 paddr (read_register (PC_REGNUM)),
55ff77ac
CV		 1769 (long) read_register (SR_REGNUM),
1770 (long) read_register (PR_REGNUM),
a6b0a3f3 1771 (long) read_register (MACH_REGNUM));
cc17453a 1772
a6b0a3f3
AS		 1773 printf_filtered (
1774 " GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n",
cc17453a 1775 (long) read_register (GBR_REGNUM),
a6b0a3f3
AS		 1776 (long) read_register (VBR_REGNUM),
1777 (long) read_register (DSR_REGNUM),
1778 (long) read_register (MACL_REGNUM));
617daa0e
CV		 1779
1780 printf_filtered
a6b0a3f3 1781 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV		 1782 (long) read_register (0), (long) read_register (1),
1783 (long) read_register (2), (long) read_register (3),
1784 (long) read_register (4), (long) read_register (5),
1785 (long) read_register (6), (long) read_register (7));
a6b0a3f3 1786 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV		 1787 (long) read_register (8), (long) read_register (9),
1788 (long) read_register (10), (long) read_register (11),
1789 (long) read_register (12), (long) read_register (13),
1790 (long) read_register (14), (long) read_register (15));
1791
1792 printf_filtered
1793 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1794 (long) read_register (A0G_REGNUM) & 0xff,
1795 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1796 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1797 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
cc17453a 1798 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
f2ea0907
CV		 1799 (long) read_register (A1G_REGNUM) & 0xff,
1800 (long) read_register (A1_REGNUM),
1801 (long) read_register (M1_REGNUM),
1802 (long) read_register (X1_REGNUM),
1803 (long) read_register (Y1_REGNUM),
1804 (long) read_register (RE_REGNUM));
cc17453a
EZ		 1805}
1806
a78f21af
AC		 1807static void
1808sh_show_regs_command (char *args, int from_tty)
53116e27
EZ		 1809{
1810 if (sh_show_regs)
617daa0e 1811 (*sh_show_regs) ();
53116e27
EZ		 1812}
1813
da962468
CV		 1814static struct type *
1815sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
1816{
1817 if ((reg_nr >= FP0_REGNUM
1818 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1819 return builtin_type_float;
1820 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1821 return builtin_type_double;
1822 else
1823 return builtin_type_int;
1824}
1825
cc17453a
EZ		 1826/* Return the GDB type object for the "standard" data type
1827 of data in register N. */
cc17453a 1828static struct type *
48db5a3c 1829sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a
EZ		 1830{
1831 if ((reg_nr >= FP0_REGNUM
617daa0e 1832 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
cc17453a 1833 return builtin_type_float;
8db62801 1834 else
cc17453a
EZ		 1835 return builtin_type_int;
1836}
1837
7f4dbe94
EZ		 1838static struct type *
1839sh_sh4_build_float_register_type (int high)
1840{
1841 struct type *temp;
1842
1843 temp = create_range_type (NULL, builtin_type_int, 0, high);
1844 return create_array_type (NULL, builtin_type_float, temp);
1845}
1846
53116e27 1847static struct type *
48db5a3c 1848sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
53116e27
EZ		 1849{
1850 if ((reg_nr >= FP0_REGNUM
617daa0e 1851 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
53116e27 1852 return builtin_type_float;
617daa0e 1853 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
53116e27 1854 return builtin_type_double;
617daa0e 1855 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27
EZ		 1856 return sh_sh4_build_float_register_type (3);
1857 else
1858 return builtin_type_int;
1859}
1860
cc17453a 1861static struct type *
48db5a3c 1862sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a
EZ		 1863{
1864 return builtin_type_int;
1865}
1866
dda63807
AS		 1867/* Is a register in a reggroup?
1868 The default code in reggroup.c doesn't identify system registers, some
1869 float registers or any of the vector registers.
1870 TODO: sh2a and dsp registers. */
1871int
1872sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
1873 struct reggroup *reggroup)
1874{
1875 if (REGISTER_NAME (regnum) == NULL
1876 || *REGISTER_NAME (regnum) == '\0')
1877 return 0;
1878
1879 if (reggroup == float_reggroup
1880 && (regnum == FPUL_REGNUM
1881 || regnum == FPSCR_REGNUM))
1882 return 1;
1883
1884 if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
1885 {
1886 if (reggroup == vector_reggroup || reggroup == float_reggroup)
1887 return 1;
1888 if (reggroup == general_reggroup)
1889 return 0;
1890 }
1891
1892 if (regnum == VBR_REGNUM
1893 || regnum == SR_REGNUM
1894 || regnum == FPSCR_REGNUM
1895 || regnum == SSR_REGNUM
1896 || regnum == SPC_REGNUM)
1897 {
1898 if (reggroup == system_reggroup)
1899 return 1;
1900 if (reggroup == general_reggroup)
1901 return 0;
1902 }
1903
1904 /* The default code can cope with any other registers. */
1905 return default_register_reggroup_p (gdbarch, regnum, reggroup);
1906}
1907
fb409745
EZ		 1908/* On the sh4, the DRi pseudo registers are problematic if the target
1909 is little endian. When the user writes one of those registers, for
1910 instance with 'ser var $dr0=1', we want the double to be stored
1911 like this:
1912 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1913 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1914
1915 This corresponds to little endian byte order & big endian word
1916 order. However if we let gdb write the register w/o conversion, it
1917 will write fr0 and fr1 this way:
1918 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1919 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1920 because it will consider fr0 and fr1 as a single LE stretch of memory.
1921
1922 To achieve what we want we must force gdb to store things in
1923 floatformat_ieee_double_littlebyte_bigword (which is defined in
1924 include/floatformat.h and libiberty/floatformat.c.
1925
1926 In case the target is big endian, there is no problem, the
1927 raw bytes will look like:
1928 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1929 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1930
1931 The other pseudo registers (the FVs) also don't pose a problem
1932 because they are stored as 4 individual FP elements. */
1933
7bd872fe 1934static void
b66ba949
CV		 1935sh_register_convert_to_virtual (int regnum, struct type *type,
1936 char *from, char *to)
55ff77ac 1937{
617daa0e 1938 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
283150cd
EZ		 1939 {
1940 DOUBLEST val;
617daa0e
CV		 1941 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1942 from, &val);
55ff77ac 1943 store_typed_floating (to, type, val);
283150cd
EZ		 1944 }
1945 else
617daa0e
CV		 1946 error
1947 ("sh_register_convert_to_virtual called with non DR register number");
283150cd
EZ		 1948}
1949
1950static void
b66ba949
CV		 1951sh_register_convert_to_raw (struct type *type, int regnum,
1952 const void *from, void *to)
283150cd 1953{
617daa0e 1954 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
283150cd 1955 {
48db5a3c 1956 DOUBLEST val = extract_typed_floating (from, type);
617daa0e
CV		 1957 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1958 &val, to);
283150cd
EZ		 1959 }
1960 else
8a3fe4f8 1961 error (_("sh_register_convert_to_raw called with non DR register number"));
283150cd
EZ		 1962}
1963
1c0159e0
CV		 1964/* For vectors of 4 floating point registers. */
1965static int
1966fv_reg_base_num (int fv_regnum)
1967{
1968 int fp_regnum;
1969
617daa0e 1970 fp_regnum = FP0_REGNUM + (fv_regnum - FV0_REGNUM) * 4;
1c0159e0
CV		 1971 return fp_regnum;
1972}
1973
1974/* For double precision floating point registers, i.e 2 fp regs.*/
1975static int
1976dr_reg_base_num (int dr_regnum)
1977{
1978 int fp_regnum;
1979
617daa0e 1980 fp_regnum = FP0_REGNUM + (dr_regnum - DR0_REGNUM) * 2;
1c0159e0
CV		 1981 return fp_regnum;
1982}
1983
a78f21af 1984static void
d8124050 1985sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
18cf8b5b 1986 int reg_nr, gdb_byte *buffer)
53116e27
EZ		 1987{
1988 int base_regnum, portion;
d9d9c31f 1989 char temp_buffer[MAX_REGISTER_SIZE];
53116e27 1990
9bed62d7
CV		 1991 if (reg_nr == PSEUDO_BANK_REGNUM)
1992 regcache_raw_read (regcache, BANK_REGNUM, buffer);
1993 else
617daa0e 1994 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
7bd872fe
EZ		 1995 {
1996 base_regnum = dr_reg_base_num (reg_nr);
1997
617daa0e 1998 /* Build the value in the provided buffer. */
7bd872fe
EZ		 1999 /* Read the real regs for which this one is an alias. */
2000 for (portion = 0; portion < 2; portion++)
617daa0e 2001 regcache_raw_read (regcache, base_regnum + portion,
0818c12a 2002 (temp_buffer
617daa0e
CV		 2003 + register_size (gdbarch,
2004 base_regnum) * portion));
7bd872fe 2005 /* We must pay attention to the endiannes. */
b66ba949
CV		 2006 sh_register_convert_to_virtual (reg_nr,
2007 gdbarch_register_type (gdbarch, reg_nr),
2008 temp_buffer, buffer);
7bd872fe 2009 }
617daa0e 2010 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27 2011 {
7bd872fe
EZ		 2012 base_regnum = fv_reg_base_num (reg_nr);
2013
2014 /* Read the real regs for which this one is an alias. */
2015 for (portion = 0; portion < 4; portion++)
617daa0e 2016 regcache_raw_read (regcache, base_regnum + portion,
d8124050 2017 ((char *) buffer
617daa0e
CV		 2018 + register_size (gdbarch,
2019 base_regnum) * portion));
53116e27
EZ		 2020 }
2021}
2022
a78f21af 2023static void
d8124050 2024sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
18cf8b5b 2025 int reg_nr, const gdb_byte *buffer)
53116e27
EZ		 2026{
2027 int base_regnum, portion;
d9d9c31f 2028 char temp_buffer[MAX_REGISTER_SIZE];
53116e27 2029
9bed62d7
CV		 2030 if (reg_nr == PSEUDO_BANK_REGNUM)
2031 {
2032 /* When the bank register is written to, the whole register bank
2033 is switched and all values in the bank registers must be read
2034 from the target/sim again. We're just invalidating the regcache
2035 so that a re-read happens next time it's necessary. */
2036 int bregnum;
2037
2038 regcache_raw_write (regcache, BANK_REGNUM, buffer);
2039 for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum)
2040 set_register_cached (bregnum, 0);
2041 }
2042 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
53116e27
EZ		 2043 {
2044 base_regnum = dr_reg_base_num (reg_nr);
2045
7bd872fe 2046 /* We must pay attention to the endiannes. */
b66ba949
CV		 2047 sh_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
2048 reg_nr, buffer, temp_buffer);
7bd872fe 2049
53116e27
EZ		 2050 /* Write the real regs for which this one is an alias. */
2051 for (portion = 0; portion < 2; portion++)
617daa0e 2052 regcache_raw_write (regcache, base_regnum + portion,
0818c12a 2053 (temp_buffer
617daa0e
CV		 2054 + register_size (gdbarch,
2055 base_regnum) * portion));
53116e27 2056 }
617daa0e 2057 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27
EZ		 2058 {
2059 base_regnum = fv_reg_base_num (reg_nr);
2060
2061 /* Write the real regs for which this one is an alias. */
2062 for (portion = 0; portion < 4; portion++)
d8124050
AC		 2063 regcache_raw_write (regcache, base_regnum + portion,
2064 ((char *) buffer
617daa0e
CV		 2065 + register_size (gdbarch,
2066 base_regnum) * portion));
53116e27
EZ		 2067 }
2068}
2069
2f14585c
JR		 2070static int
2071sh_dsp_register_sim_regno (int nr)
2072{
2073 if (legacy_register_sim_regno (nr) < 0)
2074 return legacy_register_sim_regno (nr);
f2ea0907
CV		 2075 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
2076 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
2077 if (nr == MOD_REGNUM)
2f14585c 2078 return SIM_SH_MOD_REGNUM;
f2ea0907 2079 if (nr == RS_REGNUM)
2f14585c 2080 return SIM_SH_RS_REGNUM;
f2ea0907 2081 if (nr == RE_REGNUM)
2f14585c 2082 return SIM_SH_RE_REGNUM;
76cd2bd9
CV		 2083 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
2084 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2f14585c
JR		 2085 return nr;
2086}
1c0159e0 2087
da962468
CV		 2088static int
2089sh_sh2a_register_sim_regno (int nr)
2090{
2091 switch (nr)
2092 {
2093 case TBR_REGNUM:
2094 return SIM_SH_TBR_REGNUM;
2095 case IBNR_REGNUM:
2096 return SIM_SH_IBNR_REGNUM;
2097 case IBCR_REGNUM:
2098 return SIM_SH_IBCR_REGNUM;
2099 case BANK_REGNUM:
2100 return SIM_SH_BANK_REGNUM;
2101 case MACLB_REGNUM:
2102 return SIM_SH_BANK_MACL_REGNUM;
2103 case GBRB_REGNUM:
2104 return SIM_SH_BANK_GBR_REGNUM;
2105 case PRB_REGNUM:
2106 return SIM_SH_BANK_PR_REGNUM;
2107 case IVNB_REGNUM:
2108 return SIM_SH_BANK_IVN_REGNUM;
2109 case MACHB_REGNUM:
2110 return SIM_SH_BANK_MACH_REGNUM;
2111 default:
2112 break;
2113 }
2114 return legacy_register_sim_regno (nr);
2115}
2116
357d3800
AS		 2117/* Set up the register unwinding such that call-clobbered registers are
2118 not displayed in frames >0 because the true value is not certain.
2119 The 'undefined' registers will show up as 'not available' unless the
2120 CFI says otherwise.
2121
2122 This function is currently set up for SH4 and compatible only. */
2123
2124static void
2125sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
aff37fc1
DM		 2126 struct dwarf2_frame_state_reg *reg,
2127 struct frame_info *next_frame)
357d3800
AS		 2128{
2129 /* Mark the PC as the destination for the return address. */
2130 if (regnum == PC_REGNUM)
2131 reg->how = DWARF2_FRAME_REG_RA;
2132
2133 /* Mark the stack pointer as the call frame address. */
2134 else if (regnum == SP_REGNUM)
2135 reg->how = DWARF2_FRAME_REG_CFA;
2136
2137 /* The above was taken from the default init_reg in dwarf2-frame.c
2138 while the below is SH specific. */
2139
2140 /* Caller save registers. */
2141 else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7)
2142 || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11)
2143 || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5)
2144 || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2)
2145 || (regnum == MACH_REGNUM)
2146 || (regnum == MACL_REGNUM)
2147 || (regnum == FPUL_REGNUM)
2148 || (regnum == SR_REGNUM))
2149 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2150
2151 /* Callee save registers. */
2152 else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15)
2153 || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15)
2154 || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8)
2155 || (regnum == FV0_REGNUM+3))
2156 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
2157
2158 /* Other registers. These are not in the ABI and may or may not
2159 mean anything in frames >0 so don't show them. */
2160 else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15)
2161 || (regnum == GBR_REGNUM)
2162 || (regnum == VBR_REGNUM)
2163 || (regnum == FPSCR_REGNUM)
2164 || (regnum == SSR_REGNUM)
2165 || (regnum == SPC_REGNUM))
2166 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2167}
2168
1c0159e0
CV		 2169static struct sh_frame_cache *
2170sh_alloc_frame_cache (void)
2171{
2172 struct sh_frame_cache *cache;
2173 int i;
2174
2175 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
2176
2177 /* Base address. */
2178 cache->base = 0;
2179 cache->saved_sp = 0;
2180 cache->sp_offset = 0;
2181 cache->pc = 0;
2182
2183 /* Frameless until proven otherwise. */
2184 cache->uses_fp = 0;
617daa0e 2185
1c0159e0
CV		 2186 /* Saved registers. We initialize these to -1 since zero is a valid
2187 offset (that's where fp is supposed to be stored). */
2188 for (i = 0; i < SH_NUM_REGS; i++)
2189 {
2190 cache->saved_regs[i] = -1;
2191 }
617daa0e 2192
1c0159e0 2193 return cache;
617daa0e 2194}
1c0159e0
CV		 2195
2196static struct sh_frame_cache *
2197sh_frame_cache (struct frame_info *next_frame, void **this_cache)
2198{
2199 struct sh_frame_cache *cache;
2200 CORE_ADDR current_pc;
2201 int i;
2202
2203 if (*this_cache)
2204 return *this_cache;
2205
2206 cache = sh_alloc_frame_cache ();
2207 *this_cache = cache;
2208
2209 /* In principle, for normal frames, fp holds the frame pointer,
2210 which holds the base address for the current stack frame.
2211 However, for functions that don't need it, the frame pointer is
2212 optional. For these "frameless" functions the frame pointer is
2213 actually the frame pointer of the calling frame. */
2214 cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
2215 if (cache->base == 0)
2216 return cache;
2217
2218 cache->pc = frame_func_unwind (next_frame);
2219 current_pc = frame_pc_unwind (next_frame);
2220 if (cache->pc != 0)
2221 sh_analyze_prologue (cache->pc, current_pc, cache);
617daa0e 2222
1c0159e0
CV		 2223 if (!cache->uses_fp)
2224 {
2225 /* We didn't find a valid frame, which means that CACHE->base
2226 currently holds the frame pointer for our calling frame. If
2227 we're at the start of a function, or somewhere half-way its
2228 prologue, the function's frame probably hasn't been fully
2229 setup yet. Try to reconstruct the base address for the stack
2230 frame by looking at the stack pointer. For truly "frameless"
2231 functions this might work too. */
2232 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2233 }
2234
2235 /* Now that we have the base address for the stack frame we can
2236 calculate the value of sp in the calling frame. */
2237 cache->saved_sp = cache->base + cache->sp_offset;
2238
2239 /* Adjust all the saved registers such that they contain addresses
2240 instead of offsets. */
2241 for (i = 0; i < SH_NUM_REGS; i++)
2242 if (cache->saved_regs[i] != -1)
2243 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
2244
2245 return cache;
2246}
2247
2248static void
2249sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
2250 int regnum, int *optimizedp,
2251 enum lval_type *lvalp, CORE_ADDR *addrp,
18cf8b5b 2252 int *realnump, gdb_byte *valuep)
1c0159e0
CV		 2253{
2254 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2255
2256 gdb_assert (regnum >= 0);
2257
2258 if (regnum == SP_REGNUM && cache->saved_sp)
2259 {
2260 *optimizedp = 0;
2261 *lvalp = not_lval;
2262 *addrp = 0;
2263 *realnump = -1;
2264 if (valuep)
617daa0e
CV		 2265 {
2266 /* Store the value. */
2267 store_unsigned_integer (valuep, 4, cache->saved_sp);
2268 }
1c0159e0
CV		 2269 return;
2270 }
2271
2272 /* The PC of the previous frame is stored in the PR register of
2273 the current frame. Frob regnum so that we pull the value from
2274 the correct place. */
2275 if (regnum == PC_REGNUM)
2276 regnum = PR_REGNUM;
2277
2278 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
2279 {
2280 *optimizedp = 0;
2281 *lvalp = lval_memory;
2282 *addrp = cache->saved_regs[regnum];
2283 *realnump = -1;
2284 if (valuep)
617daa0e
CV		 2285 {
2286 /* Read the value in from memory. */
2287 read_memory (*addrp, valuep,
2288 register_size (current_gdbarch, regnum));
2289 }
1c0159e0
CV		 2290 return;
2291 }
2292
00b25ff3
AC		 2293 *optimizedp = 0;
2294 *lvalp = lval_register;
2295 *addrp = 0;
2296 *realnump = regnum;
2297 if (valuep)
2298 frame_unwind_register (next_frame, (*realnump), valuep);
1c0159e0
CV		 2299}
2300
2301static void
2302sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
617daa0e
CV		 2303 struct frame_id *this_id)
2304{
1c0159e0
CV		 2305 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2306
2307 /* This marks the outermost frame. */
2308 if (cache->base == 0)
2309 return;
2310
2311 *this_id = frame_id_build (cache->saved_sp, cache->pc);
617daa0e 2312}
1c0159e0 2313
617daa0e 2314static const struct frame_unwind sh_frame_unwind = {
1c0159e0
CV		 2315 NORMAL_FRAME,
2316 sh_frame_this_id,
2317 sh_frame_prev_register
2318};
2319
2320static const struct frame_unwind *
2321sh_frame_sniffer (struct frame_info *next_frame)
2322{
2323 return &sh_frame_unwind;
2324}
2325
2326static CORE_ADDR
2327sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2328{
2329 return frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2330}
2331
2332static CORE_ADDR
2333sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2334{
2335 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2336}
2337
2338static struct frame_id
2339sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2340{
2341 return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
2342 frame_pc_unwind (next_frame));
2343}
2344
2345static CORE_ADDR
2346sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
617daa0e 2347{
1c0159e0 2348 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
617daa0e 2349
1c0159e0
CV		 2350 return cache->base;
2351}
617daa0e
CV		 2352
2353static const struct frame_base sh_frame_base = {
1c0159e0
CV		 2354 &sh_frame_unwind,
2355 sh_frame_base_address,
2356 sh_frame_base_address,
2357 sh_frame_base_address
617daa0e 2358};
1c0159e0
CV		 2359
2360/* The epilogue is defined here as the area at the end of a function,
2361 either on the `ret' instruction itself or after an instruction which
2362 destroys the function's stack frame. */
2363static int
2364sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2365{
2366 CORE_ADDR func_addr = 0, func_end = 0;
2367
2368 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2369 {
2370 ULONGEST inst;
2371 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2372 for a nop and some fixed data (e.g. big offsets) which are
617daa0e
CV		 2373 unfortunately also treated as part of the function (which
2374 means, they are below func_end. */
1c0159e0
CV		 2375 CORE_ADDR addr = func_end - 28;
2376 if (addr < func_addr + 4)
617daa0e 2377 addr = func_addr + 4;
1c0159e0
CV		 2378 if (pc < addr)
2379 return 0;
2380
2381 /* First search forward until hitting an rts. */
2382 while (addr < func_end
617daa0e 2383 && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
1c0159e0
CV		 2384 addr += 2;
2385 if (addr >= func_end)
617daa0e 2386 return 0;
1c0159e0
CV		 2387
2388 /* At this point we should find a mov.l @r15+,r14 instruction,
2389 either before or after the rts. If not, then the function has
617daa0e 2390 probably no "normal" epilogue and we bail out here. */
1c0159e0
CV		 2391 inst = read_memory_unsigned_integer (addr - 2, 2);
2392 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
617daa0e 2393 addr -= 2;
1c0159e0
CV		 2394 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
2395 return 0;
2396
1c0159e0 2397 inst = read_memory_unsigned_integer (addr - 2, 2);
03131d99
CV		 2398
2399 /* Step over possible lds.l @r15+,macl. */
2400 if (IS_MACL_LDS (inst))
2401 {
2402 addr -= 2;
2403 inst = read_memory_unsigned_integer (addr - 2, 2);
2404 }
2405
2406 /* Step over possible lds.l @r15+,pr. */
1c0159e0 2407 if (IS_LDS (inst))
617daa0e 2408 {
1c0159e0
CV		 2409 addr -= 2;
2410 inst = read_memory_unsigned_integer (addr - 2, 2);
2411 }
2412
2413 /* Step over possible mov r14,r15. */
2414 if (IS_MOV_FP_SP (inst))
617daa0e 2415 {
1c0159e0
CV		 2416 addr -= 2;
2417 inst = read_memory_unsigned_integer (addr - 2, 2);
2418 }
2419
2420 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2421 instructions. */
2422 while (addr > func_addr + 4
617daa0e 2423 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
1c0159e0
CV		 2424 {
2425 addr -= 2;
2426 inst = read_memory_unsigned_integer (addr - 2, 2);
2427 }
2428
03131d99
CV		 2429 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2430 That's allowed for the epilogue. */
2431 if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
2432 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
2433 && addr > func_addr + 6
2434 && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2)))
2435 addr -= 4;
2436
1c0159e0
CV		 2437 if (pc >= addr)
2438 return 1;
2439 }
2440 return 0;
2441}
ccf00f21 2442\f
cc17453a
EZ		 2443
2444static struct gdbarch *
fba45db2 2445sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
cc17453a 2446{
cc17453a 2447 struct gdbarch *gdbarch;
d658f924 2448
55ff77ac
CV		 2449 sh_show_regs = sh_generic_show_regs;
2450 switch (info.bfd_arch_info->mach)
2451 {
617daa0e
CV		 2452 case bfd_mach_sh2e:
2453 sh_show_regs = sh2e_show_regs;
2454 break;
da962468
CV		 2455 case bfd_mach_sh2a:
2456 sh_show_regs = sh2a_show_regs;
2457 break;
2458 case bfd_mach_sh2a_nofpu:
2459 sh_show_regs = sh2a_nofpu_show_regs;
2460 break;
617daa0e
CV		 2461 case bfd_mach_sh_dsp:
2462 sh_show_regs = sh_dsp_show_regs;
2463 break;
55ff77ac 2464
617daa0e
CV		 2465 case bfd_mach_sh3:
2466 sh_show_regs = sh3_show_regs;
2467 break;
55ff77ac 2468
617daa0e
CV		 2469 case bfd_mach_sh3e:
2470 sh_show_regs = sh3e_show_regs;
2471 break;
55ff77ac 2472
617daa0e 2473 case bfd_mach_sh3_dsp:
474e5826 2474 case bfd_mach_sh4al_dsp:
617daa0e
CV		 2475 sh_show_regs = sh3_dsp_show_regs;
2476 break;
55ff77ac 2477
617daa0e 2478 case bfd_mach_sh4:
474e5826 2479 case bfd_mach_sh4a:
617daa0e
CV		 2480 sh_show_regs = sh4_show_regs;
2481 break;
55ff77ac 2482
474e5826
CV		 2483 case bfd_mach_sh4_nofpu:
2484 case bfd_mach_sh4a_nofpu:
2485 sh_show_regs = sh4_nofpu_show_regs;
2486 break;
2487
617daa0e
CV		 2488 case bfd_mach_sh5:
2489 sh_show_regs = sh64_show_regs;
2490 /* SH5 is handled entirely in sh64-tdep.c */
2491 return sh64_gdbarch_init (info, arches);
55ff77ac
CV		 2492 }
2493
4be87837
DJ		 2494 /* If there is already a candidate, use it. */
2495 arches = gdbarch_list_lookup_by_info (arches, &info);
2496 if (arches != NULL)
2497 return arches->gdbarch;
cc17453a
EZ		 2498
2499 /* None found, create a new architecture from the information
2500 provided. */
f2ea0907 2501 gdbarch = gdbarch_alloc (&info, NULL);
cc17453a 2502
48db5a3c
CV		 2503 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2504 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
ec920329 2505 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c
CV		 2506 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2507 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2508 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2509 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
a38d2a54 2510 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c 2511
f2ea0907 2512 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
a38d2a54 2513 set_gdbarch_sp_regnum (gdbarch, 15);
a38d2a54 2514 set_gdbarch_pc_regnum (gdbarch, 16);
48db5a3c
CV		 2515 set_gdbarch_fp0_regnum (gdbarch, -1);
2516 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2517
1c0159e0 2518 set_gdbarch_register_type (gdbarch, sh_default_register_type);
dda63807 2519 set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p);
1c0159e0 2520
eaf90c5d 2521 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
48db5a3c 2522
2bf0cb65 2523 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2f14585c 2524 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
48db5a3c
CV		 2525
2526 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2527
c0409442
CV		 2528 set_gdbarch_return_value (gdbarch, sh_return_value_nofpu);
2529 set_gdbarch_deprecated_extract_struct_value_address (gdbarch,
2530 sh_extract_struct_value_address);
1c0159e0 2531
48db5a3c
CV		 2532 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2533 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
48db5a3c 2534
1c0159e0
CV		 2535 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2536
48db5a3c
CV		 2537 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2538
19f59343 2539 set_gdbarch_frame_align (gdbarch, sh_frame_align);
1c0159e0
CV		 2540 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2541 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2542 set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2543 frame_base_set_default (gdbarch, &sh_frame_base);
2544
617daa0e 2545 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
cc17453a 2546
357d3800
AS		 2547 dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg);
2548
cc17453a 2549 switch (info.bfd_arch_info->mach)
8db62801 2550 {
cc17453a 2551 case bfd_mach_sh:
48db5a3c 2552 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
cc17453a 2553 break;
1c0159e0 2554
cc17453a 2555 case bfd_mach_sh2:
48db5a3c 2556 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
617daa0e 2557 break;
1c0159e0 2558
2d188dd3 2559 case bfd_mach_sh2e:
48db5a3c
CV		 2560 /* doubles on sh2e and sh3e are actually 4 byte. */
2561 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2562
2563 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
48db5a3c 2564 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2d188dd3 2565 set_gdbarch_fp0_regnum (gdbarch, 25);
c0409442 2566 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 2567 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2d188dd3 2568 break;
1c0159e0 2569
da962468
CV		 2570 case bfd_mach_sh2a:
2571 set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
2572 set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
2573 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2574
2575 set_gdbarch_fp0_regnum (gdbarch, 25);
2576 set_gdbarch_num_pseudo_regs (gdbarch, 9);
2577 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2578 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
c0409442 2579 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
da962468
CV		 2580 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2581 break;
2582
2583 case bfd_mach_sh2a_nofpu:
2584 set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
2585 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2586
2587 set_gdbarch_num_pseudo_regs (gdbarch, 1);
2588 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2589 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2590 break;
2591
cc17453a 2592 case bfd_mach_sh_dsp:
48db5a3c 2593 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2f14585c 2594 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a 2595 break;
1c0159e0 2596
cc17453a 2597 case bfd_mach_sh3:
4e6cbc38
AS		 2598 case bfd_mach_sh3_nommu:
2599 case bfd_mach_sh2a_nofpu_or_sh3_nommu:
48db5a3c 2600 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
cc17453a 2601 break;
1c0159e0 2602
cc17453a 2603 case bfd_mach_sh3e:
4e6cbc38 2604 case bfd_mach_sh2a_or_sh3e:
48db5a3c
CV		 2605 /* doubles on sh2e and sh3e are actually 4 byte. */
2606 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2607
2608 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
48db5a3c 2609 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
cc17453a 2610 set_gdbarch_fp0_regnum (gdbarch, 25);
c0409442 2611 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 2612 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
cc17453a 2613 break;
1c0159e0 2614
cc17453a 2615 case bfd_mach_sh3_dsp:
48db5a3c 2616 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
48db5a3c 2617 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a 2618 break;
1c0159e0 2619
cc17453a 2620 case bfd_mach_sh4:
474e5826 2621 case bfd_mach_sh4a:
48db5a3c 2622 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
48db5a3c 2623 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
cc17453a 2624 set_gdbarch_fp0_regnum (gdbarch, 25);
da962468 2625 set_gdbarch_num_pseudo_regs (gdbarch, 13);
d8124050
AC		 2626 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2627 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
c0409442 2628 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 2629 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
cc17453a 2630 break;
1c0159e0 2631
474e5826
CV		 2632 case bfd_mach_sh4_nofpu:
2633 case bfd_mach_sh4a_nofpu:
4e6cbc38
AS		 2634 case bfd_mach_sh4_nommu_nofpu:
2635 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
2636 case bfd_mach_sh2a_or_sh4:
474e5826
CV		 2637 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
2638 break;
2639
2640 case bfd_mach_sh4al_dsp:
2641 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
2642 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2643 break;
2644
cc17453a 2645 default:
b58cbbf2 2646 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
cc17453a 2647 break;
8db62801 2648 }
cc17453a 2649
4be87837
DJ		 2650 /* Hook in ABI-specific overrides, if they have been registered. */
2651 gdbarch_init_osabi (info, gdbarch);
d658f924 2652
1c0159e0
CV		 2653 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2654 frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2655
cc17453a 2656 return gdbarch;
8db62801
EZ		 2657}
2658
617daa0e 2659extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
a78f21af 2660
c906108c 2661void
fba45db2 2662_initialize_sh_tdep (void)
c906108c
SS		 2663{
2664 struct cmd_list_element *c;
617daa0e 2665
f2ea0907 2666 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
c906108c 2667
1bedd215 2668 add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers"));
c906108c 2669}
GDB Binutils - Deliverables
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