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2009-10-23 Tristan Gingold <gingold@adacore.com>
[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
CommitLineData
85a453d5 1/* Target-dependent code for Renesas Super-H, for GDB.
0fd88904 2
6aba47ca 3 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
0fb0cc75 4 2003, 2004, 2005, 2007, 2008, 2009 Free Software Foundation, Inc.
c906108c 5
c5aa993b 6 This file is part of GDB.
c906108c 7
c5aa993b
JM		 8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
a9762ec7 10 the Free Software Foundation; either version 3 of the License, or
c5aa993b 11 (at your option) any later version.
c906108c 12
c5aa993b
JM		 13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
c906108c 17
c5aa993b 18 You should have received a copy of the GNU General Public License
a9762ec7 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c
SS		 20
21/*
c5aa993b
JM		 22 Contributed by Steve Chamberlain
23 sac@cygnus.com
c906108c
SS		 24 */
25
26#include "defs.h"
27#include "frame.h"
1c0159e0
CV		 28#include "frame-base.h"
29#include "frame-unwind.h"
30#include "dwarf2-frame.h"
c906108c 31#include "symtab.h"
c906108c
SS		 32#include "gdbtypes.h"
33#include "gdbcmd.h"
34#include "gdbcore.h"
35#include "value.h"
36#include "dis-asm.h"
73c1f219 37#include "inferior.h"
c906108c 38#include "gdb_string.h"
1c0159e0 39#include "gdb_assert.h"
b4a20239 40#include "arch-utils.h"
fb409745 41#include "floatformat.h"
4e052eda 42#include "regcache.h"
d16aafd8 43#include "doublest.h"
4be87837 44#include "osabi.h"
dda63807 45#include "reggroups.h"
c9ac0a72 46#include "regset.h"
c906108c 47
ab3b8126
JT		 48#include "sh-tdep.h"
49
d658f924 50#include "elf-bfd.h"
1a8629c7
MS		 51#include "solib-svr4.h"
52
55ff77ac 53/* sh flags */
283150cd 54#include "elf/sh.h"
fa8f86ff 55#include "dwarf2.h"
283150cd 56/* registers numbers shared with the simulator */
1c922164 57#include "gdb/sim-sh.h"
283150cd 58
c055b101
CV		 59/* List of "set sh ..." and "show sh ..." commands. */
60static struct cmd_list_element *setshcmdlist = NULL;
61static struct cmd_list_element *showshcmdlist = NULL;
62
63static const char sh_cc_gcc[] = "gcc";
64static const char sh_cc_renesas[] = "renesas";
65static const char *sh_cc_enum[] = {
66 sh_cc_gcc,
67 sh_cc_renesas,
68 NULL
69};
70
71static const char *sh_active_calling_convention = sh_cc_gcc;
72
c458d6db 73static void (*sh_show_regs) (struct frame_info *);
cc17453a 74
da962468 75#define SH_NUM_REGS 67
88e04cc1 76
1c0159e0 77struct sh_frame_cache
cc17453a 78{
1c0159e0
CV		 79 /* Base address. */
80 CORE_ADDR base;
81 LONGEST sp_offset;
82 CORE_ADDR pc;
83
84 /* Flag showing that a frame has been created in the prologue code. */
85 int uses_fp;
86
87 /* Saved registers. */
88 CORE_ADDR saved_regs[SH_NUM_REGS];
89 CORE_ADDR saved_sp;
63978407 90};
c906108c 91
c055b101
CV		 92static int
93sh_is_renesas_calling_convention (struct type *func_type)
94{
95 return ((func_type
96 && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh)
97 || sh_active_calling_convention == sh_cc_renesas);
98}
99
fa88f677 100static const char *
d93859e2 101sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 102{
617daa0e
CV		 103 static char *register_names[] = {
104 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
105 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
106 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
107 "", "",
108 "", "", "", "", "", "", "", "",
109 "", "", "", "", "", "", "", "",
110 "", "",
111 "", "", "", "", "", "", "", "",
112 "", "", "", "", "", "", "", "",
da962468 113 "", "", "", "", "", "", "", "",
cc17453a
EZ		 114 };
115 if (reg_nr < 0)
116 return NULL;
117 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
118 return NULL;
119 return register_names[reg_nr];
120}
121
fa88f677 122static const char *
d93859e2 123sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 124{
617daa0e
CV		 125 static char *register_names[] = {
126 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
127 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
128 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
129 "", "",
130 "", "", "", "", "", "", "", "",
131 "", "", "", "", "", "", "", "",
132 "ssr", "spc",
cc17453a
EZ		 133 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
134 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
da962468 135 "", "", "", "", "", "", "", "",
cc17453a
EZ		 136 };
137 if (reg_nr < 0)
138 return NULL;
139 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
140 return NULL;
141 return register_names[reg_nr];
142}
143
fa88f677 144static const char *
d93859e2 145sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 146{
617daa0e
CV		 147 static char *register_names[] = {
148 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
149 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
150 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
cc17453a 151 "fpul", "fpscr",
617daa0e
CV		 152 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
153 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
154 "ssr", "spc",
cc17453a
EZ		 155 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
156 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468 157 "", "", "", "", "", "", "", "",
cc17453a
EZ		 158 };
159 if (reg_nr < 0)
160 return NULL;
161 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
162 return NULL;
163 return register_names[reg_nr];
164}
165
2d188dd3 166static const char *
d93859e2 167sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr)
2d188dd3 168{
617daa0e
CV		 169 static char *register_names[] = {
170 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
171 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
172 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
2d188dd3 173 "fpul", "fpscr",
617daa0e
CV		 174 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
175 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
176 "", "",
2d188dd3
NC		 177 "", "", "", "", "", "", "", "",
178 "", "", "", "", "", "", "", "",
da962468
CV		 179 "", "", "", "", "", "", "", "",
180 };
181 if (reg_nr < 0)
182 return NULL;
183 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
184 return NULL;
185 return register_names[reg_nr];
186}
187
188static const char *
d93859e2 189sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr)
da962468
CV		 190{
191 static char *register_names[] = {
192 /* general registers 0-15 */
193 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
194 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
195 /* 16 - 22 */
196 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
197 /* 23, 24 */
198 "fpul", "fpscr",
199 /* floating point registers 25 - 40 */
200 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
201 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
202 /* 41, 42 */
203 "", "",
204 /* 43 - 62. Banked registers. The bank number used is determined by
205 the bank register (63). */
206 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
207 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
208 "machb", "ivnb", "prb", "gbrb", "maclb",
209 /* 63: register bank number, not a real register but used to
210 communicate the register bank currently get/set. This register
211 is hidden to the user, who manipulates it using the pseudo
212 register called "bank" (67). See below. */
213 "",
214 /* 64 - 66 */
215 "ibcr", "ibnr", "tbr",
216 /* 67: register bank number, the user visible pseudo register. */
217 "bank",
218 /* double precision (pseudo) 68 - 75 */
219 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
220 };
221 if (reg_nr < 0)
222 return NULL;
223 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
224 return NULL;
225 return register_names[reg_nr];
226}
227
228static const char *
d93859e2 229sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
da962468
CV		 230{
231 static char *register_names[] = {
232 /* general registers 0-15 */
233 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
234 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
235 /* 16 - 22 */
236 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
237 /* 23, 24 */
238 "", "",
239 /* floating point registers 25 - 40 */
240 "", "", "", "", "", "", "", "",
241 "", "", "", "", "", "", "", "",
242 /* 41, 42 */
243 "", "",
244 /* 43 - 62. Banked registers. The bank number used is determined by
245 the bank register (63). */
246 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
247 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
248 "machb", "ivnb", "prb", "gbrb", "maclb",
249 /* 63: register bank number, not a real register but used to
250 communicate the register bank currently get/set. This register
251 is hidden to the user, who manipulates it using the pseudo
252 register called "bank" (67). See below. */
253 "",
254 /* 64 - 66 */
255 "ibcr", "ibnr", "tbr",
256 /* 67: register bank number, the user visible pseudo register. */
257 "bank",
258 /* double precision (pseudo) 68 - 75 */
259 "", "", "", "", "", "", "", "",
2d188dd3
NC		 260 };
261 if (reg_nr < 0)
262 return NULL;
263 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
264 return NULL;
265 return register_names[reg_nr];
266}
267
fa88f677 268static const char *
d93859e2 269sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 270{
617daa0e
CV		 271 static char *register_names[] = {
272 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
273 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
274 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
275 "", "dsr",
276 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
277 "y0", "y1", "", "", "", "", "", "mod",
278 "", "",
279 "rs", "re", "", "", "", "", "", "",
280 "", "", "", "", "", "", "", "",
da962468 281 "", "", "", "", "", "", "", "",
cc17453a
EZ		 282 };
283 if (reg_nr < 0)
284 return NULL;
285 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
286 return NULL;
287 return register_names[reg_nr];
288}
289
fa88f677 290static const char *
d93859e2 291sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 292{
617daa0e
CV		 293 static char *register_names[] = {
294 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
295 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
296 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
297 "", "dsr",
298 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
299 "y0", "y1", "", "", "", "", "", "mod",
300 "ssr", "spc",
301 "rs", "re", "", "", "", "", "", "",
026a72f8
CV		 302 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
303 "", "", "", "", "", "", "", "",
da962468 304 "", "", "", "", "", "", "", "",
cc17453a
EZ		 305 };
306 if (reg_nr < 0)
307 return NULL;
308 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
309 return NULL;
310 return register_names[reg_nr];
311}
312
fa88f677 313static const char *
d93859e2 314sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr)
53116e27 315{
617daa0e 316 static char *register_names[] = {
a38d2a54 317 /* general registers 0-15 */
617daa0e
CV		 318 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
319 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
a38d2a54 320 /* 16 - 22 */
617daa0e 321 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
a38d2a54 322 /* 23, 24 */
53116e27 323 "fpul", "fpscr",
a38d2a54 324 /* floating point registers 25 - 40 */
617daa0e
CV		 325 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
326 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
a38d2a54 327 /* 41, 42 */
617daa0e 328 "ssr", "spc",
a38d2a54 329 /* bank 0 43 - 50 */
53116e27 330 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
a38d2a54 331 /* bank 1 51 - 58 */
53116e27 332 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468
CV		 333 "", "", "", "", "", "", "", "",
334 /* pseudo bank register. */
335 "",
a38d2a54 336 /* double precision (pseudo) 59 - 66 */
617daa0e 337 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
a38d2a54 338 /* vectors (pseudo) 67 - 70 */
617daa0e 339 "fv0", "fv4", "fv8", "fv12",
a38d2a54
EZ		 340 /* FIXME: missing XF 71 - 86 */
341 /* FIXME: missing XD 87 - 94 */
53116e27
EZ		 342 };
343 if (reg_nr < 0)
344 return NULL;
345 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
346 return NULL;
347 return register_names[reg_nr];
348}
349
474e5826 350static const char *
d93859e2 351sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
474e5826
CV		 352{
353 static char *register_names[] = {
354 /* general registers 0-15 */
355 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
356 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
357 /* 16 - 22 */
358 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
359 /* 23, 24 */
360 "", "",
361 /* floating point registers 25 - 40 -- not for nofpu target */
362 "", "", "", "", "", "", "", "",
363 "", "", "", "", "", "", "", "",
364 /* 41, 42 */
365 "ssr", "spc",
366 /* bank 0 43 - 50 */
367 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
368 /* bank 1 51 - 58 */
369 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468
CV		 370 "", "", "", "", "", "", "", "",
371 /* pseudo bank register. */
372 "",
474e5826
CV		 373 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
374 "", "", "", "", "", "", "", "",
375 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
376 "", "", "", "",
377 };
378 if (reg_nr < 0)
379 return NULL;
380 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
381 return NULL;
382 return register_names[reg_nr];
383}
384
385static const char *
d93859e2 386sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
474e5826
CV		 387{
388 static char *register_names[] = {
389 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
390 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
391 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
392 "", "dsr",
393 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
394 "y0", "y1", "", "", "", "", "", "mod",
395 "ssr", "spc",
396 "rs", "re", "", "", "", "", "", "",
026a72f8
CV		 397 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
398 "", "", "", "", "", "", "", "",
da962468 399 "", "", "", "", "", "", "", "",
474e5826
CV		 400 };
401 if (reg_nr < 0)
402 return NULL;
403 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
404 return NULL;
405 return register_names[reg_nr];
406}
407
3117ed25 408static const unsigned char *
67d57894 409sh_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
cc17453a
EZ		 410{
411 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
617daa0e
CV		 412 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
413
bac718a6
UW		 414 /* For remote stub targets, trapa #20 is used. */
415 if (strcmp (target_shortname, "remote") == 0)
416 {
417 static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 };
418 static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 };
419
67d57894 420 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
bac718a6
UW		 421 {
422 *lenptr = sizeof (big_remote_breakpoint);
423 return big_remote_breakpoint;
424 }
425 else
426 {
427 *lenptr = sizeof (little_remote_breakpoint);
428 return little_remote_breakpoint;
429 }
430 }
431
cc17453a
EZ		 432 *lenptr = sizeof (breakpoint);
433 return breakpoint;
434}
c906108c
SS		 435
436/* Prologue looks like
1c0159e0
CV		 437 mov.l r14,@-r15
438 sts.l pr,@-r15
439 mov.l <regs>,@-r15
440 sub <room_for_loca_vars>,r15
441 mov r15,r14
8db62801 442
1c0159e0 443 Actually it can be more complicated than this but that's it, basically.
c5aa993b 444 */
c906108c 445
1c0159e0
CV		 446#define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
447#define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
448
5f883edd
FF		 449/* JSR @Rm 0100mmmm00001011 */
450#define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
451
8db62801
EZ		 452/* STS.L PR,@-r15 0100111100100010
453 r15-4-->r15, PR-->(r15) */
c906108c 454#define IS_STS(x) ((x) == 0x4f22)
8db62801 455
03131d99
CV		 456/* STS.L MACL,@-r15 0100111100010010
457 r15-4-->r15, MACL-->(r15) */
458#define IS_MACL_STS(x) ((x) == 0x4f12)
459
8db62801
EZ		 460/* MOV.L Rm,@-r15 00101111mmmm0110
461 r15-4-->r15, Rm-->(R15) */
c906108c 462#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 463
8db62801
EZ		 464/* MOV r15,r14 0110111011110011
465 r15-->r14 */
c906108c 466#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ		 467
468/* ADD #imm,r15 01111111iiiiiiii
469 r15+imm-->r15 */
1c0159e0 470#define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 471
c906108c
SS		 472#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
473#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ		 474
475/* ADD r3,r15 0011111100111100
476 r15+r3-->r15 */
c906108c 477#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ		 478
479/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
8db62801 480 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
8db62801 481 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
f2ea0907
CV		 482/* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
483 make this entirely clear. */
1c0159e0
CV		 484/* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
485#define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
486
487/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
488#define IS_MOV_ARG_TO_REG(x) \
489 (((x) & 0xf00f) == 0x6003 && \
490 ((x) & 0x00f0) >= 0x0040 && \
491 ((x) & 0x00f0) <= 0x0070)
492/* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
493#define IS_MOV_ARG_TO_IND_R14(x) \
494 (((x) & 0xff0f) == 0x2e02 && \
495 ((x) & 0x00f0) >= 0x0040 && \
496 ((x) & 0x00f0) <= 0x0070)
497/* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
498#define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
499 (((x) & 0xff00) == 0x1e00 && \
500 ((x) & 0x00f0) >= 0x0040 && \
501 ((x) & 0x00f0) <= 0x0070)
502
503/* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
504#define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
505/* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
506#define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
03131d99
CV		 507/* MOVI20 #imm20,Rn 0000nnnniiii0000 */
508#define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
1c0159e0
CV		 509/* SUB Rn,R15 00111111nnnn1000 */
510#define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
8db62801 511
1c0159e0 512#define FPSCR_SZ (1 << 20)
cc17453a 513
1c0159e0
CV		 514/* The following instructions are used for epilogue testing. */
515#define IS_RESTORE_FP(x) ((x) == 0x6ef6)
516#define IS_RTS(x) ((x) == 0x000b)
517#define IS_LDS(x) ((x) == 0x4f26)
03131d99 518#define IS_MACL_LDS(x) ((x) == 0x4f16)
1c0159e0
CV		 519#define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
520#define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
521#define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
cc17453a 522
cc17453a 523static CORE_ADDR
e17a4113
UW		 524sh_analyze_prologue (struct gdbarch *gdbarch,
525 CORE_ADDR pc, CORE_ADDR current_pc,
d2ca4222 526 struct sh_frame_cache *cache, ULONGEST fpscr)
617daa0e 527{
e17a4113 528 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1c0159e0
CV		 529 ULONGEST inst;
530 CORE_ADDR opc;
531 int offset;
532 int sav_offset = 0;
c906108c 533 int r3_val = 0;
1c0159e0 534 int reg, sav_reg = -1;
cc17453a 535
1c0159e0
CV		 536 if (pc >= current_pc)
537 return current_pc;
cc17453a 538
1c0159e0 539 cache->uses_fp = 0;
cc17453a
EZ		 540 for (opc = pc + (2 * 28); pc < opc; pc += 2)
541 {
e17a4113 542 inst = read_memory_unsigned_integer (pc, 2, byte_order);
cc17453a 543 /* See where the registers will be saved to */
f2ea0907 544 if (IS_PUSH (inst))
cc17453a 545 {
1c0159e0
CV		 546 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
547 cache->sp_offset += 4;
cc17453a 548 }
f2ea0907 549 else if (IS_STS (inst))
cc17453a 550 {
1c0159e0
CV		 551 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
552 cache->sp_offset += 4;
cc17453a 553 }
03131d99
CV		 554 else if (IS_MACL_STS (inst))
555 {
556 cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
557 cache->sp_offset += 4;
558 }
f2ea0907 559 else if (IS_MOV_R3 (inst))
cc17453a 560 {
f2ea0907 561 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
cc17453a 562 }
f2ea0907 563 else if (IS_SHLL_R3 (inst))
cc17453a
EZ		 564 {
565 r3_val <<= 1;
566 }
f2ea0907 567 else if (IS_ADD_R3SP (inst))
cc17453a 568 {
1c0159e0 569 cache->sp_offset += -r3_val;
cc17453a 570 }
f2ea0907 571 else if (IS_ADD_IMM_SP (inst))
cc17453a 572 {
1c0159e0
CV		 573 offset = ((inst & 0xff) ^ 0x80) - 0x80;
574 cache->sp_offset -= offset;
c906108c 575 }
1c0159e0 576 else if (IS_MOVW_PCREL_TO_REG (inst))
617daa0e 577 {
1c0159e0
CV		 578 if (sav_reg < 0)
579 {
580 reg = GET_TARGET_REG (inst);
581 if (reg < 14)
582 {
583 sav_reg = reg;
a2b4a96c 584 offset = (inst & 0xff) << 1;
1c0159e0 585 sav_offset =
e17a4113 586 read_memory_integer ((pc + 4) + offset, 2, byte_order);
1c0159e0
CV		 587 }
588 }
c906108c 589 }
1c0159e0 590 else if (IS_MOVL_PCREL_TO_REG (inst))
617daa0e 591 {
1c0159e0
CV		 592 if (sav_reg < 0)
593 {
a2b4a96c 594 reg = GET_TARGET_REG (inst);
1c0159e0
CV		 595 if (reg < 14)
596 {
597 sav_reg = reg;
a2b4a96c 598 offset = (inst & 0xff) << 2;
1c0159e0 599 sav_offset =
e17a4113
UW		 600 read_memory_integer (((pc & 0xfffffffc) + 4) + offset,
601 4, byte_order);
1c0159e0
CV		 602 }
603 }
c906108c 604 }
03131d99
CV		 605 else if (IS_MOVI20 (inst))
606 {
607 if (sav_reg < 0)
608 {
609 reg = GET_TARGET_REG (inst);
610 if (reg < 14)
611 {
612 sav_reg = reg;
613 sav_offset = GET_SOURCE_REG (inst) << 16;
614 /* MOVI20 is a 32 bit instruction! */
615 pc += 2;
e17a4113
UW		 616 sav_offset
617 |= read_memory_unsigned_integer (pc, 2, byte_order);
03131d99
CV		 618 /* Now sav_offset contains an unsigned 20 bit value.
619 It must still get sign extended. */
620 if (sav_offset & 0x00080000)
621 sav_offset |= 0xfff00000;
622 }
623 }
624 }
1c0159e0 625 else if (IS_SUB_REG_FROM_SP (inst))
617daa0e 626 {
1c0159e0
CV		 627 reg = GET_SOURCE_REG (inst);
628 if (sav_reg > 0 && reg == sav_reg)
629 {
630 sav_reg = -1;
631 }
632 cache->sp_offset += sav_offset;
c906108c 633 }
f2ea0907 634 else if (IS_FPUSH (inst))
c906108c 635 {
d2ca4222 636 if (fpscr & FPSCR_SZ)
c906108c 637 {
1c0159e0 638 cache->sp_offset += 8;
c906108c
SS		 639 }
640 else
641 {
1c0159e0 642 cache->sp_offset += 4;
c906108c
SS		 643 }
644 }
f2ea0907 645 else if (IS_MOV_SP_FP (inst))
617daa0e 646 {
960ccd7d 647 cache->uses_fp = 1;
1c0159e0
CV		 648 /* At this point, only allow argument register moves to other
649 registers or argument register moves to @(X,fp) which are
650 moving the register arguments onto the stack area allocated
651 by a former add somenumber to SP call. Don't allow moving
652 to an fp indirect address above fp + cache->sp_offset. */
653 pc += 2;
654 for (opc = pc + 12; pc < opc; pc += 2)
655 {
e17a4113 656 inst = read_memory_integer (pc, 2, byte_order);
1c0159e0 657 if (IS_MOV_ARG_TO_IND_R14 (inst))
617daa0e 658 {
1c0159e0
CV		 659 reg = GET_SOURCE_REG (inst);
660 if (cache->sp_offset > 0)
617daa0e 661 cache->saved_regs[reg] = cache->sp_offset;
1c0159e0
CV		 662 }
663 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
617daa0e 664 {
1c0159e0
CV		 665 reg = GET_SOURCE_REG (inst);
666 offset = (inst & 0xf) * 4;
667 if (cache->sp_offset > offset)
668 cache->saved_regs[reg] = cache->sp_offset - offset;
669 }
670 else if (IS_MOV_ARG_TO_REG (inst))
617daa0e 671 continue;
1c0159e0
CV		 672 else
673 break;
674 }
675 break;
676 }
5f883edd
FF		 677 else if (IS_JSR (inst))
678 {
679 /* We have found a jsr that has been scheduled into the prologue.
680 If we continue the scan and return a pc someplace after this,
681 then setting a breakpoint on this function will cause it to
682 appear to be called after the function it is calling via the
683 jsr, which will be very confusing. Most likely the next
684 instruction is going to be IS_MOV_SP_FP in the delay slot. If
685 so, note that before returning the current pc. */
e17a4113 686 inst = read_memory_integer (pc + 2, 2, byte_order);
5f883edd
FF		 687 if (IS_MOV_SP_FP (inst))
688 cache->uses_fp = 1;
689 break;
690 }
617daa0e
CV		 691#if 0 /* This used to just stop when it found an instruction that
692 was not considered part of the prologue. Now, we just
693 keep going looking for likely instructions. */
c906108c
SS		 694 else
695 break;
2bfa91ee 696#endif
c906108c
SS		 697 }
698
1c0159e0
CV		 699 return pc;
700}
c906108c 701
1c0159e0 702/* Skip any prologue before the guts of a function */
c906108c 703
1c0159e0
CV		 704/* Skip the prologue using the debug information. If this fails we'll
705 fall back on the 'guess' method below. */
706static CORE_ADDR
707after_prologue (CORE_ADDR pc)
708{
709 struct symtab_and_line sal;
710 CORE_ADDR func_addr, func_end;
c906108c 711
1c0159e0
CV		 712 /* If we can not find the symbol in the partial symbol table, then
713 there is no hope we can determine the function's start address
714 with this code. */
715 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
716 return 0;
c906108c 717
1c0159e0
CV		 718 /* Get the line associated with FUNC_ADDR. */
719 sal = find_pc_line (func_addr, 0);
720
721 /* There are only two cases to consider. First, the end of the source line
722 is within the function bounds. In that case we return the end of the
723 source line. Second is the end of the source line extends beyond the
724 bounds of the current function. We need to use the slow code to
725 examine instructions in that case. */
726 if (sal.end < func_end)
727 return sal.end;
728 else
729 return 0;
c906108c
SS		 730}
731
1c0159e0 732static CORE_ADDR
6093d2eb 733sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
c906108c 734{
1c0159e0
CV		 735 CORE_ADDR pc;
736 struct sh_frame_cache cache;
737
738 /* See if we can determine the end of the prologue via the symbol table.
739 If so, then return either PC, or the PC after the prologue, whichever
740 is greater. */
741 pc = after_prologue (start_pc);
cc17453a 742
1c0159e0
CV		 743 /* If after_prologue returned a useful address, then use it. Else
744 fall back on the instruction skipping code. */
745 if (pc)
746 return max (pc, start_pc);
c906108c 747
1c0159e0 748 cache.sp_offset = -4;
e17a4113 749 pc = sh_analyze_prologue (gdbarch, start_pc, (CORE_ADDR) -1, &cache, 0);
1c0159e0
CV		 750 if (!cache.uses_fp)
751 return start_pc;
c906108c 752
1c0159e0
CV		 753 return pc;
754}
755
2e952408 756/* The ABI says:
9a5cef92
EZ		 757
758 Aggregate types not bigger than 8 bytes that have the same size and
759 alignment as one of the integer scalar types are returned in the
760 same registers as the integer type they match.
761
762 For example, a 2-byte aligned structure with size 2 bytes has the
763 same size and alignment as a short int, and will be returned in R0.
764 A 4-byte aligned structure with size 8 bytes has the same size and
765 alignment as a long long int, and will be returned in R0 and R1.
766
767 When an aggregate type is returned in R0 and R1, R0 contains the
768 first four bytes of the aggregate, and R1 contains the
769 remainder. If the size of the aggregate type is not a multiple of 4
770 bytes, the aggregate is tail-padded up to a multiple of 4
771 bytes. The value of the padding is undefined. For little-endian
772 targets the padding will appear at the most significant end of the
773 last element, for big-endian targets the padding appears at the
774 least significant end of the last element.
775
776 All other aggregate types are returned by address. The caller
777 function passes the address of an area large enough to hold the
778 aggregate value in R2. The called function stores the result in
7fe958be 779 this location.
9a5cef92
EZ		 780
781 To reiterate, structs smaller than 8 bytes could also be returned
782 in memory, if they don't pass the "same size and alignment as an
783 integer type" rule.
784
785 For example, in
786
787 struct s { char c[3]; } wibble;
788 struct s foo(void) { return wibble; }
789
790 the return value from foo() will be in memory, not
791 in R0, because there is no 3-byte integer type.
792
7fe958be
EZ		 793 Similarly, in
794
795 struct s { char c[2]; } wibble;
796 struct s foo(void) { return wibble; }
797
798 because a struct containing two chars has alignment 1, that matches
799 type char, but size 2, that matches type short. There's no integer
800 type that has alignment 1 and size 2, so the struct is returned in
801 memory.
802
9a5cef92
EZ		 803*/
804
1c0159e0 805static int
c055b101 806sh_use_struct_convention (int renesas_abi, struct type *type)
1c0159e0
CV		 807{
808 int len = TYPE_LENGTH (type);
809 int nelem = TYPE_NFIELDS (type);
3f997a97 810
c055b101
CV		 811 /* The Renesas ABI returns aggregate types always on stack. */
812 if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT
813 || TYPE_CODE (type) == TYPE_CODE_UNION))
814 return 1;
815
3f997a97
CV		 816 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
817 fit in two registers anyway) use struct convention. */
818 if (len != 1 && len != 2 && len != 4 && len != 8)
819 return 1;
820
821 /* Scalar types and aggregate types with exactly one field are aligned
822 by definition. They are returned in registers. */
823 if (nelem <= 1)
824 return 0;
825
826 /* If the first field in the aggregate has the same length as the entire
827 aggregate type, the type is returned in registers. */
828 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
829 return 0;
830
831 /* If the size of the aggregate is 8 bytes and the first field is
832 of size 4 bytes its alignment is equal to long long's alignment,
833 so it's returned in registers. */
834 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
835 return 0;
836
837 /* Otherwise use struct convention. */
838 return 1;
283150cd
EZ		 839}
840
c055b101
CV		 841static int
842sh_use_struct_convention_nofpu (int renesas_abi, struct type *type)
843{
844 /* The Renesas ABI returns long longs/doubles etc. always on stack. */
845 if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8)
846 return 1;
847 return sh_use_struct_convention (renesas_abi, type);
848}
849
19f59343
MS		 850static CORE_ADDR
851sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
852{
853 return sp & ~3;
854}
855
55ff77ac 856/* Function: push_dummy_call (formerly push_arguments)
c906108c
SS		 857 Setup the function arguments for calling a function in the inferior.
858
85a453d5 859 On the Renesas SH architecture, there are four registers (R4 to R7)
c906108c
SS		 860 which are dedicated for passing function arguments. Up to the first
861 four arguments (depending on size) may go into these registers.
862 The rest go on the stack.
863
6df2bf50
MS		 864 MVS: Except on SH variants that have floating point registers.
865 In that case, float and double arguments are passed in the same
866 manner, but using FP registers instead of GP registers.
867
c906108c
SS		 868 Arguments that are smaller than 4 bytes will still take up a whole
869 register or a whole 32-bit word on the stack, and will be
870 right-justified in the register or the stack word. This includes
871 chars, shorts, and small aggregate types.
872
873 Arguments that are larger than 4 bytes may be split between two or
874 more registers. If there are not enough registers free, an argument
875 may be passed partly in a register (or registers), and partly on the
876 stack. This includes doubles, long longs, and larger aggregates.
877 As far as I know, there is no upper limit to the size of aggregates
878 that will be passed in this way; in other words, the convention of
879 passing a pointer to a large aggregate instead of a copy is not used.
880
6df2bf50 881 MVS: The above appears to be true for the SH variants that do not
55ff77ac 882 have an FPU, however those that have an FPU appear to copy the
6df2bf50
MS		 883 aggregate argument onto the stack (and not place it in registers)
884 if it is larger than 16 bytes (four GP registers).
885
c906108c
SS		 886 An exceptional case exists for struct arguments (and possibly other
887 aggregates such as arrays) if the size is larger than 4 bytes but
888 not a multiple of 4 bytes. In this case the argument is never split
889 between the registers and the stack, but instead is copied in its
890 entirety onto the stack, AND also copied into as many registers as
891 there is room for. In other words, space in registers permitting,
892 two copies of the same argument are passed in. As far as I can tell,
893 only the one on the stack is used, although that may be a function
894 of the level of compiler optimization. I suspect this is a compiler
895 bug. Arguments of these odd sizes are left-justified within the
896 word (as opposed to arguments smaller than 4 bytes, which are
897 right-justified).
c5aa993b 898
c906108c
SS		 899 If the function is to return an aggregate type such as a struct, it
900 is either returned in the normal return value register R0 (if its
901 size is no greater than one byte), or else the caller must allocate
902 space into which the callee will copy the return value (if the size
903 is greater than one byte). In this case, a pointer to the return
904 value location is passed into the callee in register R2, which does
905 not displace any of the other arguments passed in via registers R4
906 to R7. */
907
e5e33cd9
CV		 908/* Helper function to justify value in register according to endianess. */
909static char *
d93859e2 910sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len)
e5e33cd9
CV		 911{
912 static char valbuf[4];
913
617daa0e 914 memset (valbuf, 0, sizeof (valbuf));
e5e33cd9
CV		 915 if (len < 4)
916 {
917 /* value gets right-justified in the register or stack word */
d93859e2 918 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
0fd88904 919 memcpy (valbuf + (4 - len), (char *) value_contents (val), len);
e5e33cd9 920 else
0fd88904 921 memcpy (valbuf, (char *) value_contents (val), len);
e5e33cd9
CV		 922 return valbuf;
923 }
0fd88904 924 return (char *) value_contents (val);
617daa0e 925}
e5e33cd9
CV		 926
927/* Helper function to eval number of bytes to allocate on stack. */
928static CORE_ADDR
929sh_stack_allocsize (int nargs, struct value **args)
930{
931 int stack_alloc = 0;
932 while (nargs-- > 0)
4991999e 933 stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3);
e5e33cd9
CV		 934 return stack_alloc;
935}
936
937/* Helper functions for getting the float arguments right. Registers usage
938 depends on the ABI and the endianess. The comments should enlighten how
939 it's intended to work. */
940
941/* This array stores which of the float arg registers are already in use. */
942static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
943
944/* This function just resets the above array to "no reg used so far". */
945static void
946sh_init_flt_argreg (void)
947{
948 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
949}
950
951/* This function returns the next register to use for float arg passing.
952 It returns either a valid value between FLOAT_ARG0_REGNUM and
953 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
954 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
955
956 Note that register number 0 in flt_argreg_array corresponds with the
957 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
958 29) the parity of the register number is preserved, which is important
959 for the double register passing test (see the "argreg & 1" test below). */
960static int
c055b101 961sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type)
e5e33cd9
CV		 962{
963 int argreg;
964
965 /* First search for the next free register. */
617daa0e
CV		 966 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
967 ++argreg)
e5e33cd9
CV		 968 if (!flt_argreg_array[argreg])
969 break;
970
971 /* No register left? */
972 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
973 return FLOAT_ARGLAST_REGNUM + 1;
974
975 if (len == 8)
976 {
977 /* Doubles are always starting in a even register number. */
978 if (argreg & 1)
617daa0e 979 {
c055b101
CV		 980 /* In gcc ABI, the skipped register is lost for further argument
981 passing now. Not so in Renesas ABI. */
982 if (!sh_is_renesas_calling_convention (func_type))
983 flt_argreg_array[argreg] = 1;
e5e33cd9
CV		 984
985 ++argreg;
986
617daa0e 987 /* No register left? */
e5e33cd9
CV		 988 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
989 return FLOAT_ARGLAST_REGNUM + 1;
990 }
991 /* Also mark the next register as used. */
992 flt_argreg_array[argreg + 1] = 1;
993 }
c055b101
CV		 994 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
995 && !sh_is_renesas_calling_convention (func_type))
e5e33cd9
CV		 996 {
997 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
998 if (!flt_argreg_array[argreg + 1])
999 ++argreg;
1000 }
1001 flt_argreg_array[argreg] = 1;
1002 return FLOAT_ARG0_REGNUM + argreg;
1003}
1004
afce3d2a
CV		 1005/* Helper function which figures out, if a type is treated like a float type.
1006
2e952408 1007 The FPU ABIs have a special way how to treat types as float types.
afce3d2a
CV		 1008 Structures with exactly one member, which is of type float or double, are
1009 treated exactly as the base types float or double:
1010
1011 struct sf {
1012 float f;
1013 };
1014
1015 struct sd {
1016 double d;
1017 };
1018
1019 are handled the same way as just
1020
1021 float f;
1022
1023 double d;
1024
1025 As a result, arguments of these struct types are pushed into floating point
1026 registers exactly as floats or doubles, using the same decision algorithm.
1027
1028 The same is valid if these types are used as function return types. The
1029 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1030 or even using struct convention as it is for other structs. */
1031
1032static int
1033sh_treat_as_flt_p (struct type *type)
1034{
1035 int len = TYPE_LENGTH (type);
1036
1037 /* Ordinary float types are obviously treated as float. */
1038 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1039 return 1;
1040 /* Otherwise non-struct types are not treated as float. */
1041 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
1042 return 0;
1043 /* Otherwise structs with more than one memeber are not treated as float. */
1044 if (TYPE_NFIELDS (type) != 1)
1045 return 0;
1046 /* Otherwise if the type of that member is float, the whole type is
1047 treated as float. */
1048 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
1049 return 1;
1050 /* Otherwise it's not treated as float. */
1051 return 0;
1052}
1053
cc17453a 1054static CORE_ADDR
617daa0e 1055sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
7d9b040b 1056 struct value *function,
617daa0e 1057 struct regcache *regcache,
6df2bf50 1058 CORE_ADDR bp_addr, int nargs,
617daa0e 1059 struct value **args,
6df2bf50
MS		 1060 CORE_ADDR sp, int struct_return,
1061 CORE_ADDR struct_addr)
1062{
e17a4113 1063 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e5e33cd9
CV		 1064 int stack_offset = 0;
1065 int argreg = ARG0_REGNUM;
8748518b 1066 int flt_argreg = 0;
6df2bf50 1067 int argnum;
c055b101 1068 struct type *func_type = value_type (function);
6df2bf50
MS		 1069 struct type *type;
1070 CORE_ADDR regval;
1071 char *val;
8748518b 1072 int len, reg_size = 0;
afce3d2a
CV		 1073 int pass_on_stack = 0;
1074 int treat_as_flt;
c055b101
CV		 1075 int last_reg_arg = INT_MAX;
1076
1077 /* The Renesas ABI expects all varargs arguments, plus the last
1078 non-vararg argument to be on the stack, no matter how many
1079 registers have been used so far. */
1080 if (sh_is_renesas_calling_convention (func_type)
876cecd0 1081 && TYPE_VARARGS (func_type))
c055b101 1082 last_reg_arg = TYPE_NFIELDS (func_type) - 2;
6df2bf50
MS		 1083
1084 /* first force sp to a 4-byte alignment */
1085 sp = sh_frame_align (gdbarch, sp);
1086
e5e33cd9
CV		 1087 /* make room on stack for args */
1088 sp -= sh_stack_allocsize (nargs, args);
1089
1090 /* Initialize float argument mechanism. */
1091 sh_init_flt_argreg ();
6df2bf50
MS		 1092
1093 /* Now load as many as possible of the first arguments into
1094 registers, and push the rest onto the stack. There are 16 bytes
1095 in four registers available. Loop thru args from first to last. */
e5e33cd9 1096 for (argnum = 0; argnum < nargs; argnum++)
6df2bf50 1097 {
4991999e 1098 type = value_type (args[argnum]);
6df2bf50 1099 len = TYPE_LENGTH (type);
d93859e2 1100 val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
e5e33cd9
CV		 1101
1102 /* Some decisions have to be made how various types are handled.
1103 This also differs in different ABIs. */
1104 pass_on_stack = 0;
e5e33cd9
CV		 1105
1106 /* Find out the next register to use for a floating point value. */
afce3d2a
CV		 1107 treat_as_flt = sh_treat_as_flt_p (type);
1108 if (treat_as_flt)
c055b101
CV		 1109 flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type);
1110 /* In Renesas ABI, long longs and aggregate types are always passed
1111 on stack. */
1112 else if (sh_is_renesas_calling_convention (func_type)
1113 && ((TYPE_CODE (type) == TYPE_CODE_INT && len == 8)
1114 || TYPE_CODE (type) == TYPE_CODE_STRUCT
1115 || TYPE_CODE (type) == TYPE_CODE_UNION))
1116 pass_on_stack = 1;
afce3d2a
CV		 1117 /* In contrast to non-FPU CPUs, arguments are never split between
1118 registers and stack. If an argument doesn't fit in the remaining
1119 registers it's always pushed entirely on the stack. */
1120 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
1121 pass_on_stack = 1;
48db5a3c 1122
6df2bf50
MS		 1123 while (len > 0)
1124 {
afce3d2a
CV		 1125 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
1126 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
c055b101
CV		 1127 || pass_on_stack))
1128 || argnum > last_reg_arg)
617daa0e 1129 {
afce3d2a 1130 /* The data goes entirely on the stack, 4-byte aligned. */
e5e33cd9
CV		 1131 reg_size = (len + 3) & ~3;
1132 write_memory (sp + stack_offset, val, reg_size);
1133 stack_offset += reg_size;
6df2bf50 1134 }
afce3d2a 1135 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
6df2bf50 1136 {
e5e33cd9
CV		 1137 /* Argument goes in a float argument register. */
1138 reg_size = register_size (gdbarch, flt_argreg);
e17a4113 1139 regval = extract_unsigned_integer (val, reg_size, byte_order);
2e952408
CV		 1140 /* In little endian mode, float types taking two registers
1141 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1142 be stored swapped in the argument registers. The below
1143 code first writes the first 32 bits in the next but one
1144 register, increments the val and len values accordingly
1145 and then proceeds as normal by writing the second 32 bits
1146 into the next register. */
b47193f7 1147 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
2e952408
CV		 1148 && TYPE_LENGTH (type) == 2 * reg_size)
1149 {
1150 regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
1151 regval);
1152 val += reg_size;
1153 len -= reg_size;
e17a4113 1154 regval = extract_unsigned_integer (val, reg_size, byte_order);
2e952408 1155 }
6df2bf50
MS		 1156 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
1157 }
afce3d2a 1158 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
e5e33cd9 1159 {
6df2bf50 1160 /* there's room in a register */
e5e33cd9 1161 reg_size = register_size (gdbarch, argreg);
e17a4113 1162 regval = extract_unsigned_integer (val, reg_size, byte_order);
6df2bf50
MS		 1163 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1164 }
afce3d2a 1165 /* Store the value one register at a time or in one step on stack. */
e5e33cd9
CV		 1166 len -= reg_size;
1167 val += reg_size;
6df2bf50
MS		 1168 }
1169 }
1170
c055b101
CV		 1171 if (struct_return)
1172 {
1173 if (sh_is_renesas_calling_convention (func_type))
1174 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1175 the stack and store the struct return address there. */
e17a4113 1176 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
c055b101
CV		 1177 else
1178 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1179 its own dedicated register. */
1180 regcache_cooked_write_unsigned (regcache,
1181 STRUCT_RETURN_REGNUM, struct_addr);
1182 }
1183
6df2bf50 1184 /* Store return address. */
55ff77ac 1185 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
6df2bf50
MS		 1186
1187 /* Update stack pointer. */
3e8c568d 1188 regcache_cooked_write_unsigned (regcache,
b47193f7 1189 gdbarch_sp_regnum (gdbarch), sp);
6df2bf50
MS		 1190
1191 return sp;
1192}
1193
1194static CORE_ADDR
617daa0e 1195sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
7d9b040b 1196 struct value *function,
617daa0e
CV		 1197 struct regcache *regcache,
1198 CORE_ADDR bp_addr,
1199 int nargs, struct value **args,
1200 CORE_ADDR sp, int struct_return,
6df2bf50 1201 CORE_ADDR struct_addr)
c906108c 1202{
e17a4113 1203 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e5e33cd9
CV		 1204 int stack_offset = 0;
1205 int argreg = ARG0_REGNUM;
c906108c 1206 int argnum;
c055b101 1207 struct type *func_type = value_type (function);
c906108c
SS		 1208 struct type *type;
1209 CORE_ADDR regval;
1210 char *val;
c055b101
CV		 1211 int len, reg_size = 0;
1212 int pass_on_stack = 0;
1213 int last_reg_arg = INT_MAX;
1214
1215 /* The Renesas ABI expects all varargs arguments, plus the last
1216 non-vararg argument to be on the stack, no matter how many
1217 registers have been used so far. */
1218 if (sh_is_renesas_calling_convention (func_type)
876cecd0 1219 && TYPE_VARARGS (func_type))
c055b101 1220 last_reg_arg = TYPE_NFIELDS (func_type) - 2;
c906108c
SS		 1221
1222 /* first force sp to a 4-byte alignment */
19f59343 1223 sp = sh_frame_align (gdbarch, sp);
c906108c 1224
e5e33cd9
CV		 1225 /* make room on stack for args */
1226 sp -= sh_stack_allocsize (nargs, args);
c906108c 1227
c906108c
SS		 1228 /* Now load as many as possible of the first arguments into
1229 registers, and push the rest onto the stack. There are 16 bytes
1230 in four registers available. Loop thru args from first to last. */
e5e33cd9 1231 for (argnum = 0; argnum < nargs; argnum++)
617daa0e 1232 {
4991999e 1233 type = value_type (args[argnum]);
c5aa993b 1234 len = TYPE_LENGTH (type);
d93859e2 1235 val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
c906108c 1236
c055b101
CV		 1237 /* Some decisions have to be made how various types are handled.
1238 This also differs in different ABIs. */
1239 pass_on_stack = 0;
1240 /* Renesas ABI pushes doubles and long longs entirely on stack.
1241 Same goes for aggregate types. */
1242 if (sh_is_renesas_calling_convention (func_type)
1243 && ((TYPE_CODE (type) == TYPE_CODE_INT && len >= 8)
1244 || (TYPE_CODE (type) == TYPE_CODE_FLT && len >= 8)
1245 || TYPE_CODE (type) == TYPE_CODE_STRUCT
1246 || TYPE_CODE (type) == TYPE_CODE_UNION))
1247 pass_on_stack = 1;
c906108c
SS		 1248 while (len > 0)
1249 {
c055b101
CV		 1250 if (argreg > ARGLAST_REGNUM || pass_on_stack
1251 || argnum > last_reg_arg)
617daa0e 1252 {
e5e33cd9
CV		 1253 /* The remainder of the data goes entirely on the stack,
1254 4-byte aligned. */
1255 reg_size = (len + 3) & ~3;
1256 write_memory (sp + stack_offset, val, reg_size);
617daa0e 1257 stack_offset += reg_size;
c906108c 1258 }
e5e33cd9 1259 else if (argreg <= ARGLAST_REGNUM)
617daa0e 1260 {
3bbfbb92 1261 /* there's room in a register */
e5e33cd9 1262 reg_size = register_size (gdbarch, argreg);
e17a4113 1263 regval = extract_unsigned_integer (val, reg_size, byte_order);
48db5a3c 1264 regcache_cooked_write_unsigned (regcache, argreg++, regval);
c906108c 1265 }
e5e33cd9
CV		 1266 /* Store the value reg_size bytes at a time. This means that things
1267 larger than reg_size bytes may go partly in registers and partly
c906108c 1268 on the stack. */
e5e33cd9
CV		 1269 len -= reg_size;
1270 val += reg_size;
c906108c
SS		 1271 }
1272 }
48db5a3c 1273
c055b101
CV		 1274 if (struct_return)
1275 {
1276 if (sh_is_renesas_calling_convention (func_type))
1277 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1278 the stack and store the struct return address there. */
e17a4113 1279 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
c055b101
CV		 1280 else
1281 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1282 its own dedicated register. */
1283 regcache_cooked_write_unsigned (regcache,
1284 STRUCT_RETURN_REGNUM, struct_addr);
1285 }
1286
48db5a3c 1287 /* Store return address. */
55ff77ac 1288 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
48db5a3c
CV		 1289
1290 /* Update stack pointer. */
3e8c568d 1291 regcache_cooked_write_unsigned (regcache,
b47193f7 1292 gdbarch_sp_regnum (gdbarch), sp);
48db5a3c 1293
c906108c
SS		 1294 return sp;
1295}
1296
cc17453a
EZ		 1297/* Find a function's return value in the appropriate registers (in
1298 regbuf), and copy it into valbuf. Extract from an array REGBUF
1299 containing the (raw) register state a function return value of type
1300 TYPE, and copy that, in virtual format, into VALBUF. */
1301static void
3ffc5b9b
CV		 1302sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache,
1303 void *valbuf)
c906108c 1304{
e17a4113
UW		 1305 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1306 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
cc17453a 1307 int len = TYPE_LENGTH (type);
3116c80a
EZ		 1308 int return_register = R0_REGNUM;
1309 int offset;
617daa0e 1310
cc17453a 1311 if (len <= 4)
3116c80a 1312 {
48db5a3c
CV		 1313 ULONGEST c;
1314
1315 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
e17a4113 1316 store_unsigned_integer (valbuf, len, byte_order, c);
3116c80a 1317 }
48db5a3c 1318 else if (len == 8)
3116c80a 1319 {
48db5a3c
CV		 1320 int i, regnum = R0_REGNUM;
1321 for (i = 0; i < len; i += 4)
617daa0e 1322 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
3116c80a
EZ		 1323 }
1324 else
8a3fe4f8 1325 error (_("bad size for return value"));
3116c80a
EZ		 1326}
1327
1328static void
3ffc5b9b
CV		 1329sh_extract_return_value_fpu (struct type *type, struct regcache *regcache,
1330 void *valbuf)
3116c80a 1331{
d93859e2 1332 struct gdbarch *gdbarch = get_regcache_arch (regcache);
afce3d2a 1333 if (sh_treat_as_flt_p (type))
3116c80a 1334 {
48db5a3c 1335 int len = TYPE_LENGTH (type);
d93859e2 1336 int i, regnum = gdbarch_fp0_regnum (gdbarch);
48db5a3c 1337 for (i = 0; i < len; i += 4)
d93859e2 1338 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
2e952408
CV		 1339 regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i);
1340 else
1341 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
3116c80a 1342 }
cc17453a 1343 else
3ffc5b9b 1344 sh_extract_return_value_nofpu (type, regcache, valbuf);
cc17453a 1345}
c906108c 1346
cc17453a
EZ		 1347/* Write into appropriate registers a function return value
1348 of type TYPE, given in virtual format.
1349 If the architecture is sh4 or sh3e, store a function's return value
1350 in the R0 general register or in the FP0 floating point register,
1351 depending on the type of the return value. In all the other cases
3bbfbb92 1352 the result is stored in r0, left-justified. */
cc17453a 1353static void
3ffc5b9b
CV		 1354sh_store_return_value_nofpu (struct type *type, struct regcache *regcache,
1355 const void *valbuf)
cc17453a 1356{
e17a4113
UW		 1357 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1358 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
48db5a3c
CV		 1359 ULONGEST val;
1360 int len = TYPE_LENGTH (type);
d19b71be 1361
48db5a3c 1362 if (len <= 4)
d19b71be 1363 {
e17a4113 1364 val = extract_unsigned_integer (valbuf, len, byte_order);
48db5a3c 1365 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
d19b71be
MS		 1366 }
1367 else
48db5a3c
CV		 1368 {
1369 int i, regnum = R0_REGNUM;
1370 for (i = 0; i < len; i += 4)
617daa0e 1371 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
48db5a3c 1372 }
cc17453a 1373}
c906108c 1374
cc17453a 1375static void
3ffc5b9b
CV		 1376sh_store_return_value_fpu (struct type *type, struct regcache *regcache,
1377 const void *valbuf)
cc17453a 1378{
d93859e2 1379 struct gdbarch *gdbarch = get_regcache_arch (regcache);
afce3d2a 1380 if (sh_treat_as_flt_p (type))
48db5a3c
CV		 1381 {
1382 int len = TYPE_LENGTH (type);
d93859e2 1383 int i, regnum = gdbarch_fp0_regnum (gdbarch);
48db5a3c 1384 for (i = 0; i < len; i += 4)
d93859e2 1385 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
c8a3b559
CV		 1386 regcache_raw_write (regcache, regnum++,
1387 (char *) valbuf + len - 4 - i);
1388 else
1389 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
48db5a3c 1390 }
cc17453a 1391 else
3ffc5b9b 1392 sh_store_return_value_nofpu (type, regcache, valbuf);
c906108c
SS		 1393}
1394
c0409442 1395static enum return_value_convention
c055b101
CV		 1396sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *func_type,
1397 struct type *type, struct regcache *regcache,
18cf8b5b 1398 gdb_byte *readbuf, const gdb_byte *writebuf)
c0409442 1399{
c055b101
CV		 1400 if (sh_use_struct_convention_nofpu (
1401 sh_is_renesas_calling_convention (func_type), type))
c0409442
CV		 1402 return RETURN_VALUE_STRUCT_CONVENTION;
1403 if (writebuf)
3ffc5b9b 1404 sh_store_return_value_nofpu (type, regcache, writebuf);
c0409442 1405 else if (readbuf)
3ffc5b9b 1406 sh_extract_return_value_nofpu (type, regcache, readbuf);
c0409442
CV		 1407 return RETURN_VALUE_REGISTER_CONVENTION;
1408}
1409
1410static enum return_value_convention
c055b101
CV		 1411sh_return_value_fpu (struct gdbarch *gdbarch, struct type *func_type,
1412 struct type *type, struct regcache *regcache,
18cf8b5b 1413 gdb_byte *readbuf, const gdb_byte *writebuf)
c0409442 1414{
c055b101
CV		 1415 if (sh_use_struct_convention (
1416 sh_is_renesas_calling_convention (func_type), type))
c0409442
CV		 1417 return RETURN_VALUE_STRUCT_CONVENTION;
1418 if (writebuf)
3ffc5b9b 1419 sh_store_return_value_fpu (type, regcache, writebuf);
c0409442 1420 else if (readbuf)
3ffc5b9b 1421 sh_extract_return_value_fpu (type, regcache, readbuf);
c0409442
CV		 1422 return RETURN_VALUE_REGISTER_CONVENTION;
1423}
1424
c906108c
SS		 1425/* Print the registers in a form similar to the E7000 */
1426
1427static void
c458d6db 1428sh_generic_show_regs (struct frame_info *frame)
c906108c 1429{
c458d6db
UW		 1430 printf_filtered
1431 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1432 phex (get_frame_register_unsigned (frame,
1433 gdbarch_pc_regnum
1434 (get_frame_arch (frame))), 4),
c458d6db
UW		 1435 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1436 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1437 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
cc17453a 1438
c458d6db
UW		 1439 printf_filtered
1440 (" GBR %08lx VBR %08lx MACL %08lx\n",
1441 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1442 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1443 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
cc17453a 1444
617daa0e 1445 printf_filtered
a6b0a3f3 1446 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1447 (long) get_frame_register_unsigned (frame, 0),
1448 (long) get_frame_register_unsigned (frame, 1),
1449 (long) get_frame_register_unsigned (frame, 2),
1450 (long) get_frame_register_unsigned (frame, 3),
1451 (long) get_frame_register_unsigned (frame, 4),
1452 (long) get_frame_register_unsigned (frame, 5),
1453 (long) get_frame_register_unsigned (frame, 6),
1454 (long) get_frame_register_unsigned (frame, 7));
1455 printf_filtered
1456 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1457 (long) get_frame_register_unsigned (frame, 8),
1458 (long) get_frame_register_unsigned (frame, 9),
1459 (long) get_frame_register_unsigned (frame, 10),
1460 (long) get_frame_register_unsigned (frame, 11),
1461 (long) get_frame_register_unsigned (frame, 12),
1462 (long) get_frame_register_unsigned (frame, 13),
1463 (long) get_frame_register_unsigned (frame, 14),
1464 (long) get_frame_register_unsigned (frame, 15));
cc17453a 1465}
c906108c 1466
cc17453a 1467static void
c458d6db 1468sh3_show_regs (struct frame_info *frame)
cc17453a 1469{
c458d6db
UW		 1470 printf_filtered
1471 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1472 phex (get_frame_register_unsigned (frame,
1473 gdbarch_pc_regnum
1474 (get_frame_arch (frame))), 4),
c458d6db
UW		 1475 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1476 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1477 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1478
1479 printf_filtered
1480 (" GBR %08lx VBR %08lx MACL %08lx\n",
1481 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1482 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1483 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1484 printf_filtered
1485 (" SSR %08lx SPC %08lx\n",
1486 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1487 (long) get_frame_register_unsigned (frame, SPC_REGNUM));
c906108c 1488
617daa0e 1489 printf_filtered
a6b0a3f3 1490 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1491 (long) get_frame_register_unsigned (frame, 0),
1492 (long) get_frame_register_unsigned (frame, 1),
1493 (long) get_frame_register_unsigned (frame, 2),
1494 (long) get_frame_register_unsigned (frame, 3),
1495 (long) get_frame_register_unsigned (frame, 4),
1496 (long) get_frame_register_unsigned (frame, 5),
1497 (long) get_frame_register_unsigned (frame, 6),
1498 (long) get_frame_register_unsigned (frame, 7));
1499 printf_filtered
1500 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1501 (long) get_frame_register_unsigned (frame, 8),
1502 (long) get_frame_register_unsigned (frame, 9),
1503 (long) get_frame_register_unsigned (frame, 10),
1504 (long) get_frame_register_unsigned (frame, 11),
1505 (long) get_frame_register_unsigned (frame, 12),
1506 (long) get_frame_register_unsigned (frame, 13),
1507 (long) get_frame_register_unsigned (frame, 14),
1508 (long) get_frame_register_unsigned (frame, 15));
c906108c
SS		 1509}
1510
2d188dd3 1511static void
c458d6db 1512sh2e_show_regs (struct frame_info *frame)
2d188dd3 1513{
b47193f7 1514 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1515 printf_filtered
1516 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1517 phex (get_frame_register_unsigned (frame,
1518 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1519 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1520 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1521 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1522
1523 printf_filtered
1524 (" GBR %08lx VBR %08lx MACL %08lx\n",
1525 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1526 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1527 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1528 printf_filtered
1529 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1530 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1531 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1532 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1533 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
617daa0e
CV		 1534
1535 printf_filtered
a6b0a3f3 1536 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1537 (long) get_frame_register_unsigned (frame, 0),
1538 (long) get_frame_register_unsigned (frame, 1),
1539 (long) get_frame_register_unsigned (frame, 2),
1540 (long) get_frame_register_unsigned (frame, 3),
1541 (long) get_frame_register_unsigned (frame, 4),
1542 (long) get_frame_register_unsigned (frame, 5),
1543 (long) get_frame_register_unsigned (frame, 6),
1544 (long) get_frame_register_unsigned (frame, 7));
1545 printf_filtered
1546 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1547 (long) get_frame_register_unsigned (frame, 8),
1548 (long) get_frame_register_unsigned (frame, 9),
1549 (long) get_frame_register_unsigned (frame, 10),
1550 (long) get_frame_register_unsigned (frame, 11),
1551 (long) get_frame_register_unsigned (frame, 12),
1552 (long) get_frame_register_unsigned (frame, 13),
1553 (long) get_frame_register_unsigned (frame, 14),
1554 (long) get_frame_register_unsigned (frame, 15));
1555
1556 printf_filtered
1557 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1558 (long) get_frame_register_unsigned
b47193f7 1559 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1560 (long) get_frame_register_unsigned
b47193f7 1561 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1562 (long) get_frame_register_unsigned
b47193f7 1563 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1564 (long) get_frame_register_unsigned
b47193f7 1565 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1566 (long) get_frame_register_unsigned
b47193f7 1567 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1568 (long) get_frame_register_unsigned
b47193f7 1569 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1570 (long) get_frame_register_unsigned
b47193f7 1571 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1572 (long) get_frame_register_unsigned
b47193f7 1573 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 1574 printf_filtered
1575 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1576 (long) get_frame_register_unsigned
b47193f7 1577 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 1578 (long) get_frame_register_unsigned
b47193f7 1579 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 1580 (long) get_frame_register_unsigned
b47193f7 1581 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 1582 (long) get_frame_register_unsigned
b47193f7 1583 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 1584 (long) get_frame_register_unsigned
b47193f7 1585 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 1586 (long) get_frame_register_unsigned
b47193f7 1587 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 1588 (long) get_frame_register_unsigned
b47193f7 1589 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 1590 (long) get_frame_register_unsigned
b47193f7 1591 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
2d188dd3
NC		 1592}
1593
da962468 1594static void
c458d6db 1595sh2a_show_regs (struct frame_info *frame)
da962468 1596{
b47193f7 1597 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1598 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1599
1600 printf_filtered
1601 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1602 phex (get_frame_register_unsigned (frame,
1603 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1604 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1605 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1606 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1607
1608 printf_filtered
1609 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1610 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1611 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1612 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1613 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1614 printf_filtered
1615 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1616 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1617 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1618 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1619 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1620
1621 printf_filtered
1622 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1623 (long) get_frame_register_unsigned (frame, 0),
1624 (long) get_frame_register_unsigned (frame, 1),
1625 (long) get_frame_register_unsigned (frame, 2),
1626 (long) get_frame_register_unsigned (frame, 3),
1627 (long) get_frame_register_unsigned (frame, 4),
1628 (long) get_frame_register_unsigned (frame, 5),
1629 (long) get_frame_register_unsigned (frame, 6),
1630 (long) get_frame_register_unsigned (frame, 7));
1631 printf_filtered
1632 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1633 (long) get_frame_register_unsigned (frame, 8),
1634 (long) get_frame_register_unsigned (frame, 9),
1635 (long) get_frame_register_unsigned (frame, 10),
1636 (long) get_frame_register_unsigned (frame, 11),
1637 (long) get_frame_register_unsigned (frame, 12),
1638 (long) get_frame_register_unsigned (frame, 13),
1639 (long) get_frame_register_unsigned (frame, 14),
1640 (long) get_frame_register_unsigned (frame, 15));
1641
1642 printf_filtered
1643 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1644 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1645 (long) get_frame_register_unsigned
b47193f7 1646 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1647 (long) get_frame_register_unsigned
b47193f7 1648 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1649 (long) get_frame_register_unsigned
b47193f7 1650 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1651 (long) get_frame_register_unsigned
b47193f7 1652 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1653 (long) get_frame_register_unsigned
b47193f7 1654 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1655 (long) get_frame_register_unsigned
b47193f7 1656 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1657 (long) get_frame_register_unsigned
b47193f7 1658 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1659 (long) get_frame_register_unsigned
b47193f7 1660 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 1661 printf_filtered
1662 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1663 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1664 (long) get_frame_register_unsigned
b47193f7 1665 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 1666 (long) get_frame_register_unsigned
b47193f7 1667 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 1668 (long) get_frame_register_unsigned
b47193f7 1669 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 1670 (long) get_frame_register_unsigned
b47193f7 1671 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 1672 (long) get_frame_register_unsigned
b47193f7 1673 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 1674 (long) get_frame_register_unsigned
b47193f7 1675 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 1676 (long) get_frame_register_unsigned
b47193f7 1677 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 1678 (long) get_frame_register_unsigned
b47193f7 1679 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
c458d6db
UW		 1680 printf_filtered
1681 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1682 printf_filtered
1683 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1684 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1685 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1686 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1687 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1688 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1689 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1690 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1691 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1692 printf_filtered
1693 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1694 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1695 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1696 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1697 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1698 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1699 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1700 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1701 printf_filtered
1702 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1703 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1704 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1705 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1706 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1707 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
da962468
CV		 1708}
1709
1710static void
c458d6db 1711sh2a_nofpu_show_regs (struct frame_info *frame)
da962468 1712{
c458d6db
UW		 1713 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1714
1715 printf_filtered
1716 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1717 phex (get_frame_register_unsigned (frame,
1718 gdbarch_pc_regnum
1719 (get_frame_arch (frame))), 4),
c458d6db
UW		 1720 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1721 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1722 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1723
1724 printf_filtered
1725 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1726 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1727 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1728 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1729 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1730 printf_filtered
1731 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1732 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1733 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1734 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1735 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1736
1737 printf_filtered
1738 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1739 (long) get_frame_register_unsigned (frame, 0),
1740 (long) get_frame_register_unsigned (frame, 1),
1741 (long) get_frame_register_unsigned (frame, 2),
1742 (long) get_frame_register_unsigned (frame, 3),
1743 (long) get_frame_register_unsigned (frame, 4),
1744 (long) get_frame_register_unsigned (frame, 5),
1745 (long) get_frame_register_unsigned (frame, 6),
1746 (long) get_frame_register_unsigned (frame, 7));
1747 printf_filtered
1748 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1749 (long) get_frame_register_unsigned (frame, 8),
1750 (long) get_frame_register_unsigned (frame, 9),
1751 (long) get_frame_register_unsigned (frame, 10),
1752 (long) get_frame_register_unsigned (frame, 11),
1753 (long) get_frame_register_unsigned (frame, 12),
1754 (long) get_frame_register_unsigned (frame, 13),
1755 (long) get_frame_register_unsigned (frame, 14),
1756 (long) get_frame_register_unsigned (frame, 15));
1757
1758 printf_filtered
1759 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1760 printf_filtered
1761 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1762 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1763 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1764 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1765 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1766 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1767 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1768 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1769 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1770 printf_filtered
1771 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1772 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1773 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1774 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1775 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1776 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1777 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1778 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1779 printf_filtered
1780 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1781 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1782 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1783 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1784 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1785 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
da962468
CV		 1786}
1787
cc17453a 1788static void
c458d6db 1789sh3e_show_regs (struct frame_info *frame)
cc17453a 1790{
b47193f7 1791 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1792 printf_filtered
1793 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1794 phex (get_frame_register_unsigned (frame,
1795 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1796 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1797 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1798 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1799
1800 printf_filtered
1801 (" GBR %08lx VBR %08lx MACL %08lx\n",
1802 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1803 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1804 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1805 printf_filtered
1806 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1807 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1808 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1809 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1810 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
c906108c 1811
617daa0e 1812 printf_filtered
a6b0a3f3 1813 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1814 (long) get_frame_register_unsigned (frame, 0),
1815 (long) get_frame_register_unsigned (frame, 1),
1816 (long) get_frame_register_unsigned (frame, 2),
1817 (long) get_frame_register_unsigned (frame, 3),
1818 (long) get_frame_register_unsigned (frame, 4),
1819 (long) get_frame_register_unsigned (frame, 5),
1820 (long) get_frame_register_unsigned (frame, 6),
1821 (long) get_frame_register_unsigned (frame, 7));
1822 printf_filtered
1823 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1824 (long) get_frame_register_unsigned (frame, 8),
1825 (long) get_frame_register_unsigned (frame, 9),
1826 (long) get_frame_register_unsigned (frame, 10),
1827 (long) get_frame_register_unsigned (frame, 11),
1828 (long) get_frame_register_unsigned (frame, 12),
1829 (long) get_frame_register_unsigned (frame, 13),
1830 (long) get_frame_register_unsigned (frame, 14),
1831 (long) get_frame_register_unsigned (frame, 15));
1832
1833 printf_filtered
1834 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1835 (long) get_frame_register_unsigned
b47193f7 1836 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1837 (long) get_frame_register_unsigned
b47193f7 1838 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1839 (long) get_frame_register_unsigned
b47193f7 1840 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1841 (long) get_frame_register_unsigned
b47193f7 1842 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1843 (long) get_frame_register_unsigned
b47193f7 1844 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1845 (long) get_frame_register_unsigned
b47193f7 1846 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1847 (long) get_frame_register_unsigned
b47193f7 1848 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1849 (long) get_frame_register_unsigned
b47193f7 1850 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 1851 printf_filtered
1852 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1853 (long) get_frame_register_unsigned
b47193f7 1854 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 1855 (long) get_frame_register_unsigned
b47193f7 1856 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 1857 (long) get_frame_register_unsigned
b47193f7 1858 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 1859 (long) get_frame_register_unsigned
b47193f7 1860 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 1861 (long) get_frame_register_unsigned
b47193f7 1862 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 1863 (long) get_frame_register_unsigned
b47193f7 1864 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 1865 (long) get_frame_register_unsigned
b47193f7 1866 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 1867 (long) get_frame_register_unsigned
b47193f7 1868 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
cc17453a
EZ		 1869}
1870
1871static void
c458d6db 1872sh3_dsp_show_regs (struct frame_info *frame)
c906108c 1873{
c458d6db
UW		 1874 printf_filtered
1875 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1876 phex (get_frame_register_unsigned (frame,
1877 gdbarch_pc_regnum
1878 (get_frame_arch (frame))), 4),
c458d6db
UW		 1879 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1880 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1881 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
c906108c 1882
c458d6db
UW		 1883 printf_filtered
1884 (" GBR %08lx VBR %08lx MACL %08lx\n",
1885 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1886 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1887 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
cc17453a 1888
c458d6db
UW		 1889 printf_filtered
1890 (" SSR %08lx SPC %08lx DSR %08lx\n",
1891 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1892 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1893 (long) get_frame_register_unsigned (frame, DSR_REGNUM));
617daa0e
CV		 1894
1895 printf_filtered
a6b0a3f3 1896 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1897 (long) get_frame_register_unsigned (frame, 0),
1898 (long) get_frame_register_unsigned (frame, 1),
1899 (long) get_frame_register_unsigned (frame, 2),
1900 (long) get_frame_register_unsigned (frame, 3),
1901 (long) get_frame_register_unsigned (frame, 4),
1902 (long) get_frame_register_unsigned (frame, 5),
1903 (long) get_frame_register_unsigned (frame, 6),
1904 (long) get_frame_register_unsigned (frame, 7));
1905 printf_filtered
1906 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1907 (long) get_frame_register_unsigned (frame, 8),
1908 (long) get_frame_register_unsigned (frame, 9),
1909 (long) get_frame_register_unsigned (frame, 10),
1910 (long) get_frame_register_unsigned (frame, 11),
1911 (long) get_frame_register_unsigned (frame, 12),
1912 (long) get_frame_register_unsigned (frame, 13),
1913 (long) get_frame_register_unsigned (frame, 14),
1914 (long) get_frame_register_unsigned (frame, 15));
617daa0e
CV		 1915
1916 printf_filtered
1917 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
c458d6db
UW		 1918 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
1919 (long) get_frame_register_unsigned (frame, A0_REGNUM),
1920 (long) get_frame_register_unsigned (frame, M0_REGNUM),
1921 (long) get_frame_register_unsigned (frame, X0_REGNUM),
1922 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
1923 (long) get_frame_register_unsigned (frame, RS_REGNUM),
1924 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
1925 printf_filtered
1926 ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1927 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
1928 (long) get_frame_register_unsigned (frame, A1_REGNUM),
1929 (long) get_frame_register_unsigned (frame, M1_REGNUM),
1930 (long) get_frame_register_unsigned (frame, X1_REGNUM),
1931 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
1932 (long) get_frame_register_unsigned (frame, RE_REGNUM));
c906108c
SS		 1933}
1934
cc17453a 1935static void
c458d6db 1936sh4_show_regs (struct frame_info *frame)
cc17453a 1937{
b47193f7 1938 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1939 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1940
1941 printf_filtered
1942 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1943 phex (get_frame_register_unsigned (frame,
1944 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1945 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1946 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1947 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1948
1949 printf_filtered
1950 (" GBR %08lx VBR %08lx MACL %08lx\n",
1951 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1952 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1953 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1954 printf_filtered
1955 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1956 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1957 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1958 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1959 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1960
1961 printf_filtered
1962 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1963 (long) get_frame_register_unsigned (frame, 0),
1964 (long) get_frame_register_unsigned (frame, 1),
1965 (long) get_frame_register_unsigned (frame, 2),
1966 (long) get_frame_register_unsigned (frame, 3),
1967 (long) get_frame_register_unsigned (frame, 4),
1968 (long) get_frame_register_unsigned (frame, 5),
1969 (long) get_frame_register_unsigned (frame, 6),
1970 (long) get_frame_register_unsigned (frame, 7));
1971 printf_filtered
1972 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1973 (long) get_frame_register_unsigned (frame, 8),
1974 (long) get_frame_register_unsigned (frame, 9),
1975 (long) get_frame_register_unsigned (frame, 10),
1976 (long) get_frame_register_unsigned (frame, 11),
1977 (long) get_frame_register_unsigned (frame, 12),
1978 (long) get_frame_register_unsigned (frame, 13),
1979 (long) get_frame_register_unsigned (frame, 14),
1980 (long) get_frame_register_unsigned (frame, 15));
1981
1982 printf_filtered
1983 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1984 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1985 (long) get_frame_register_unsigned
b47193f7 1986 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1987 (long) get_frame_register_unsigned
b47193f7 1988 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1989 (long) get_frame_register_unsigned
b47193f7 1990 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1991 (long) get_frame_register_unsigned
b47193f7 1992 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1993 (long) get_frame_register_unsigned
b47193f7 1994 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1995 (long) get_frame_register_unsigned
b47193f7 1996 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1997 (long) get_frame_register_unsigned
b47193f7 1998 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1999 (long) get_frame_register_unsigned
b47193f7 2000 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 2001 printf_filtered
2002 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2003 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 2004 (long) get_frame_register_unsigned
b47193f7 2005 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 2006 (long) get_frame_register_unsigned
b47193f7 2007 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 2008 (long) get_frame_register_unsigned
b47193f7 2009 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 2010 (long) get_frame_register_unsigned
b47193f7 2011 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 2012 (long) get_frame_register_unsigned
b47193f7 2013 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 2014 (long) get_frame_register_unsigned
b47193f7 2015 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 2016 (long) get_frame_register_unsigned
b47193f7 2017 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 2018 (long) get_frame_register_unsigned
b47193f7 2019 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
cc17453a
EZ		 2020}
2021
474e5826 2022static void
c458d6db 2023sh4_nofpu_show_regs (struct frame_info *frame)
474e5826 2024{
c458d6db
UW		 2025 printf_filtered
2026 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 2027 phex (get_frame_register_unsigned (frame,
2028 gdbarch_pc_regnum
2029 (get_frame_arch (frame))), 4),
c458d6db
UW		 2030 (long) get_frame_register_unsigned (frame, SR_REGNUM),
2031 (long) get_frame_register_unsigned (frame, PR_REGNUM),
2032 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
2033
2034 printf_filtered
2035 (" GBR %08lx VBR %08lx MACL %08lx\n",
2036 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2037 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2038 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
2039 printf_filtered
2040 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
2041 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
2042 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
2043 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
2044 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
2045
2046 printf_filtered
2047 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2048 (long) get_frame_register_unsigned (frame, 0),
2049 (long) get_frame_register_unsigned (frame, 1),
2050 (long) get_frame_register_unsigned (frame, 2),
2051 (long) get_frame_register_unsigned (frame, 3),
2052 (long) get_frame_register_unsigned (frame, 4),
2053 (long) get_frame_register_unsigned (frame, 5),
2054 (long) get_frame_register_unsigned (frame, 6),
2055 (long) get_frame_register_unsigned (frame, 7));
2056 printf_filtered
2057 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2058 (long) get_frame_register_unsigned (frame, 8),
2059 (long) get_frame_register_unsigned (frame, 9),
2060 (long) get_frame_register_unsigned (frame, 10),
2061 (long) get_frame_register_unsigned (frame, 11),
2062 (long) get_frame_register_unsigned (frame, 12),
2063 (long) get_frame_register_unsigned (frame, 13),
2064 (long) get_frame_register_unsigned (frame, 14),
2065 (long) get_frame_register_unsigned (frame, 15));
474e5826
CV		 2066}
2067
cc17453a 2068static void
c458d6db 2069sh_dsp_show_regs (struct frame_info *frame)
cc17453a 2070{
c458d6db
UW		 2071 printf_filtered
2072 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 2073 phex (get_frame_register_unsigned (frame,
2074 gdbarch_pc_regnum
2075 (get_frame_arch (frame))), 4),
c458d6db
UW		 2076 (long) get_frame_register_unsigned (frame, SR_REGNUM),
2077 (long) get_frame_register_unsigned (frame, PR_REGNUM),
2078 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
a6b0a3f3 2079
c458d6db
UW		 2080 printf_filtered
2081 (" GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n",
2082 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2083 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2084 (long) get_frame_register_unsigned (frame, DSR_REGNUM),
2085 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
617daa0e
CV		 2086
2087 printf_filtered
a6b0a3f3 2088 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 2089 (long) get_frame_register_unsigned (frame, 0),
2090 (long) get_frame_register_unsigned (frame, 1),
2091 (long) get_frame_register_unsigned (frame, 2),
2092 (long) get_frame_register_unsigned (frame, 3),
2093 (long) get_frame_register_unsigned (frame, 4),
2094 (long) get_frame_register_unsigned (frame, 5),
2095 (long) get_frame_register_unsigned (frame, 6),
2096 (long) get_frame_register_unsigned (frame, 7));
2097 printf_filtered
2098 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2099 (long) get_frame_register_unsigned (frame, 8),
2100 (long) get_frame_register_unsigned (frame, 9),
2101 (long) get_frame_register_unsigned (frame, 10),
2102 (long) get_frame_register_unsigned (frame, 11),
2103 (long) get_frame_register_unsigned (frame, 12),
2104 (long) get_frame_register_unsigned (frame, 13),
2105 (long) get_frame_register_unsigned (frame, 14),
2106 (long) get_frame_register_unsigned (frame, 15));
617daa0e
CV		 2107
2108 printf_filtered
2109 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
c458d6db
UW		 2110 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
2111 (long) get_frame_register_unsigned (frame, A0_REGNUM),
2112 (long) get_frame_register_unsigned (frame, M0_REGNUM),
2113 (long) get_frame_register_unsigned (frame, X0_REGNUM),
2114 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
2115 (long) get_frame_register_unsigned (frame, RS_REGNUM),
2116 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
cc17453a 2117 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
c458d6db
UW		 2118 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
2119 (long) get_frame_register_unsigned (frame, A1_REGNUM),
2120 (long) get_frame_register_unsigned (frame, M1_REGNUM),
2121 (long) get_frame_register_unsigned (frame, X1_REGNUM),
2122 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
2123 (long) get_frame_register_unsigned (frame, RE_REGNUM));
cc17453a
EZ		 2124}
2125
a78f21af
AC		 2126static void
2127sh_show_regs_command (char *args, int from_tty)
53116e27
EZ		 2128{
2129 if (sh_show_regs)
c458d6db 2130 (*sh_show_regs) (get_current_frame ());
53116e27
EZ		 2131}
2132
da962468
CV		 2133static struct type *
2134sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
2135{
b47193f7 2136 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
da962468 2137 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
0dfff4cb 2138 return builtin_type (gdbarch)->builtin_float;
da962468 2139 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
0dfff4cb 2140 return builtin_type (gdbarch)->builtin_double;
da962468 2141 else
0dfff4cb 2142 return builtin_type (gdbarch)->builtin_int;
da962468
CV		 2143}
2144
cc17453a
EZ		 2145/* Return the GDB type object for the "standard" data type
2146 of data in register N. */
cc17453a 2147static struct type *
48db5a3c 2148sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a 2149{
b47193f7 2150 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
617daa0e 2151 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
0dfff4cb 2152 return builtin_type (gdbarch)->builtin_float;
8db62801 2153 else
0dfff4cb 2154 return builtin_type (gdbarch)->builtin_int;
cc17453a
EZ		 2155}
2156
7f4dbe94 2157static struct type *
0dfff4cb 2158sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high)
7f4dbe94 2159{
e3506a9f
UW		 2160 return lookup_array_range_type (builtin_type (gdbarch)->builtin_float,
2161 0, high);
7f4dbe94
EZ		 2162}
2163
53116e27 2164static struct type *
48db5a3c 2165sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
53116e27 2166{
b47193f7 2167 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
617daa0e 2168 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
0dfff4cb 2169 return builtin_type (gdbarch)->builtin_float;
617daa0e 2170 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
0dfff4cb 2171 return builtin_type (gdbarch)->builtin_double;
617daa0e 2172 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
0dfff4cb 2173 return sh_sh4_build_float_register_type (gdbarch, 3);
53116e27 2174 else
0dfff4cb 2175 return builtin_type (gdbarch)->builtin_int;
53116e27
EZ		 2176}
2177
cc17453a 2178static struct type *
48db5a3c 2179sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a 2180{
0dfff4cb 2181 return builtin_type (gdbarch)->builtin_int;
cc17453a
EZ		 2182}
2183
dda63807
AS		 2184/* Is a register in a reggroup?
2185 The default code in reggroup.c doesn't identify system registers, some
2186 float registers or any of the vector registers.
2187 TODO: sh2a and dsp registers. */
63807e1d 2188static int
dda63807
AS		 2189sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2190 struct reggroup *reggroup)
2191{
b47193f7
UW		 2192 if (gdbarch_register_name (gdbarch, regnum) == NULL
2193 || *gdbarch_register_name (gdbarch, regnum) == '\0')
dda63807
AS		 2194 return 0;
2195
2196 if (reggroup == float_reggroup
2197 && (regnum == FPUL_REGNUM
2198 || regnum == FPSCR_REGNUM))
2199 return 1;
2200
2201 if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
2202 {
2203 if (reggroup == vector_reggroup || reggroup == float_reggroup)
2204 return 1;
2205 if (reggroup == general_reggroup)
2206 return 0;
2207 }
2208
2209 if (regnum == VBR_REGNUM
2210 || regnum == SR_REGNUM
2211 || regnum == FPSCR_REGNUM
2212 || regnum == SSR_REGNUM
2213 || regnum == SPC_REGNUM)
2214 {
2215 if (reggroup == system_reggroup)
2216 return 1;
2217 if (reggroup == general_reggroup)
2218 return 0;
2219 }
2220
2221 /* The default code can cope with any other registers. */
2222 return default_register_reggroup_p (gdbarch, regnum, reggroup);
2223}
2224
fb409745
EZ		 2225/* On the sh4, the DRi pseudo registers are problematic if the target
2226 is little endian. When the user writes one of those registers, for
2227 instance with 'ser var $dr0=1', we want the double to be stored
2228 like this:
2229 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2230 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2231
2232 This corresponds to little endian byte order & big endian word
2233 order. However if we let gdb write the register w/o conversion, it
2234 will write fr0 and fr1 this way:
2235 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2236 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2237 because it will consider fr0 and fr1 as a single LE stretch of memory.
2238
2239 To achieve what we want we must force gdb to store things in
2240 floatformat_ieee_double_littlebyte_bigword (which is defined in
2241 include/floatformat.h and libiberty/floatformat.c.
2242
2243 In case the target is big endian, there is no problem, the
2244 raw bytes will look like:
2245 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
2246 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2247
2248 The other pseudo registers (the FVs) also don't pose a problem
2249 because they are stored as 4 individual FP elements. */
2250
7bd872fe 2251static void
b66ba949
CV		 2252sh_register_convert_to_virtual (int regnum, struct type *type,
2253 char *from, char *to)
55ff77ac 2254{
617daa0e 2255 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
283150cd
EZ		 2256 {
2257 DOUBLEST val;
617daa0e
CV		 2258 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2259 from, &val);
55ff77ac 2260 store_typed_floating (to, type, val);
283150cd
EZ		 2261 }
2262 else
617daa0e
CV		 2263 error
2264 ("sh_register_convert_to_virtual called with non DR register number");
283150cd
EZ		 2265}
2266
2267static void
b66ba949
CV		 2268sh_register_convert_to_raw (struct type *type, int regnum,
2269 const void *from, void *to)
283150cd 2270{
617daa0e 2271 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
283150cd 2272 {
48db5a3c 2273 DOUBLEST val = extract_typed_floating (from, type);
617daa0e
CV		 2274 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2275 &val, to);
283150cd
EZ		 2276 }
2277 else
8a3fe4f8 2278 error (_("sh_register_convert_to_raw called with non DR register number"));
283150cd
EZ		 2279}
2280
1c0159e0
CV		 2281/* For vectors of 4 floating point registers. */
2282static int
d93859e2 2283fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum)
1c0159e0
CV		 2284{
2285 int fp_regnum;
2286
d93859e2 2287 fp_regnum = gdbarch_fp0_regnum (gdbarch)
3e8c568d 2288 + (fv_regnum - FV0_REGNUM) * 4;
1c0159e0
CV		 2289 return fp_regnum;
2290}
2291
2292/* For double precision floating point registers, i.e 2 fp regs.*/
2293static int
d93859e2 2294dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum)
1c0159e0
CV		 2295{
2296 int fp_regnum;
2297
d93859e2 2298 fp_regnum = gdbarch_fp0_regnum (gdbarch)
3e8c568d 2299 + (dr_regnum - DR0_REGNUM) * 2;
1c0159e0
CV		 2300 return fp_regnum;
2301}
2302
a78f21af 2303static void
d8124050 2304sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
18cf8b5b 2305 int reg_nr, gdb_byte *buffer)
53116e27
EZ		 2306{
2307 int base_regnum, portion;
d9d9c31f 2308 char temp_buffer[MAX_REGISTER_SIZE];
53116e27 2309
9bed62d7
CV		 2310 if (reg_nr == PSEUDO_BANK_REGNUM)
2311 regcache_raw_read (regcache, BANK_REGNUM, buffer);
2312 else
617daa0e 2313 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
7bd872fe 2314 {
d93859e2 2315 base_regnum = dr_reg_base_num (gdbarch, reg_nr);
7bd872fe 2316
617daa0e 2317 /* Build the value in the provided buffer. */
7bd872fe
EZ		 2318 /* Read the real regs for which this one is an alias. */
2319 for (portion = 0; portion < 2; portion++)
617daa0e 2320 regcache_raw_read (regcache, base_regnum + portion,
0818c12a 2321 (temp_buffer
617daa0e
CV		 2322 + register_size (gdbarch,
2323 base_regnum) * portion));
7bd872fe 2324 /* We must pay attention to the endiannes. */
b66ba949 2325 sh_register_convert_to_virtual (reg_nr,
7b9ee6a8 2326 register_type (gdbarch, reg_nr),
b66ba949 2327 temp_buffer, buffer);
7bd872fe 2328 }
617daa0e 2329 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27 2330 {
d93859e2 2331 base_regnum = fv_reg_base_num (gdbarch, reg_nr);
7bd872fe
EZ		 2332
2333 /* Read the real regs for which this one is an alias. */
2334 for (portion = 0; portion < 4; portion++)
617daa0e 2335 regcache_raw_read (regcache, base_regnum + portion,
d8124050 2336 ((char *) buffer
617daa0e
CV		 2337 + register_size (gdbarch,
2338 base_regnum) * portion));
53116e27
EZ		 2339 }
2340}
2341
a78f21af 2342static void
d8124050 2343sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
18cf8b5b 2344 int reg_nr, const gdb_byte *buffer)
53116e27
EZ		 2345{
2346 int base_regnum, portion;
d9d9c31f 2347 char temp_buffer[MAX_REGISTER_SIZE];
53116e27 2348
9bed62d7
CV		 2349 if (reg_nr == PSEUDO_BANK_REGNUM)
2350 {
2351 /* When the bank register is written to, the whole register bank
2352 is switched and all values in the bank registers must be read
2353 from the target/sim again. We're just invalidating the regcache
2354 so that a re-read happens next time it's necessary. */
2355 int bregnum;
2356
2357 regcache_raw_write (regcache, BANK_REGNUM, buffer);
2358 for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum)
9c5ea4d9 2359 regcache_invalidate (regcache, bregnum);
9bed62d7
CV		 2360 }
2361 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
53116e27 2362 {
d93859e2 2363 base_regnum = dr_reg_base_num (gdbarch, reg_nr);
53116e27 2364
7bd872fe 2365 /* We must pay attention to the endiannes. */
7b9ee6a8 2366 sh_register_convert_to_raw (register_type (gdbarch, reg_nr),
b66ba949 2367 reg_nr, buffer, temp_buffer);
7bd872fe 2368
53116e27
EZ		 2369 /* Write the real regs for which this one is an alias. */
2370 for (portion = 0; portion < 2; portion++)
617daa0e 2371 regcache_raw_write (regcache, base_regnum + portion,
0818c12a 2372 (temp_buffer
617daa0e
CV		 2373 + register_size (gdbarch,
2374 base_regnum) * portion));
53116e27 2375 }
617daa0e 2376 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27 2377 {
d93859e2 2378 base_regnum = fv_reg_base_num (gdbarch, reg_nr);
53116e27
EZ		 2379
2380 /* Write the real regs for which this one is an alias. */
2381 for (portion = 0; portion < 4; portion++)
d8124050
AC		 2382 regcache_raw_write (regcache, base_regnum + portion,
2383 ((char *) buffer
617daa0e
CV		 2384 + register_size (gdbarch,
2385 base_regnum) * portion));
53116e27
EZ		 2386 }
2387}
2388
2f14585c 2389static int
e7faf938 2390sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr)
2f14585c 2391{
e7faf938
MD		 2392 if (legacy_register_sim_regno (gdbarch, nr) < 0)
2393 return legacy_register_sim_regno (gdbarch, nr);
f2ea0907
CV		 2394 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
2395 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
2396 if (nr == MOD_REGNUM)
2f14585c 2397 return SIM_SH_MOD_REGNUM;
f2ea0907 2398 if (nr == RS_REGNUM)
2f14585c 2399 return SIM_SH_RS_REGNUM;
f2ea0907 2400 if (nr == RE_REGNUM)
2f14585c 2401 return SIM_SH_RE_REGNUM;
76cd2bd9
CV		 2402 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
2403 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2f14585c
JR		 2404 return nr;
2405}
1c0159e0 2406
da962468 2407static int
e7faf938 2408sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr)
da962468
CV		 2409{
2410 switch (nr)
2411 {
2412 case TBR_REGNUM:
2413 return SIM_SH_TBR_REGNUM;
2414 case IBNR_REGNUM:
2415 return SIM_SH_IBNR_REGNUM;
2416 case IBCR_REGNUM:
2417 return SIM_SH_IBCR_REGNUM;
2418 case BANK_REGNUM:
2419 return SIM_SH_BANK_REGNUM;
2420 case MACLB_REGNUM:
2421 return SIM_SH_BANK_MACL_REGNUM;
2422 case GBRB_REGNUM:
2423 return SIM_SH_BANK_GBR_REGNUM;
2424 case PRB_REGNUM:
2425 return SIM_SH_BANK_PR_REGNUM;
2426 case IVNB_REGNUM:
2427 return SIM_SH_BANK_IVN_REGNUM;
2428 case MACHB_REGNUM:
2429 return SIM_SH_BANK_MACH_REGNUM;
2430 default:
2431 break;
2432 }
e7faf938 2433 return legacy_register_sim_regno (gdbarch, nr);
da962468
CV		 2434}
2435
357d3800
AS		 2436/* Set up the register unwinding such that call-clobbered registers are
2437 not displayed in frames >0 because the true value is not certain.
2438 The 'undefined' registers will show up as 'not available' unless the
2439 CFI says otherwise.
2440
2441 This function is currently set up for SH4 and compatible only. */
2442
2443static void
2444sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
aff37fc1 2445 struct dwarf2_frame_state_reg *reg,
4a4e5149 2446 struct frame_info *this_frame)
357d3800
AS		 2447{
2448 /* Mark the PC as the destination for the return address. */
b47193f7 2449 if (regnum == gdbarch_pc_regnum (gdbarch))
357d3800
AS		 2450 reg->how = DWARF2_FRAME_REG_RA;
2451
2452 /* Mark the stack pointer as the call frame address. */
b47193f7 2453 else if (regnum == gdbarch_sp_regnum (gdbarch))
357d3800
AS		 2454 reg->how = DWARF2_FRAME_REG_CFA;
2455
2456 /* The above was taken from the default init_reg in dwarf2-frame.c
2457 while the below is SH specific. */
2458
2459 /* Caller save registers. */
2460 else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7)
2461 || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11)
2462 || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5)
2463 || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2)
2464 || (regnum == MACH_REGNUM)
2465 || (regnum == MACL_REGNUM)
2466 || (regnum == FPUL_REGNUM)
2467 || (regnum == SR_REGNUM))
2468 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2469
2470 /* Callee save registers. */
2471 else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15)
2472 || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15)
2473 || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8)
2474 || (regnum == FV0_REGNUM+3))
2475 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
2476
2477 /* Other registers. These are not in the ABI and may or may not
2478 mean anything in frames >0 so don't show them. */
2479 else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15)
2480 || (regnum == GBR_REGNUM)
2481 || (regnum == VBR_REGNUM)
2482 || (regnum == FPSCR_REGNUM)
2483 || (regnum == SSR_REGNUM)
2484 || (regnum == SPC_REGNUM))
2485 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2486}
2487
1c0159e0
CV		 2488static struct sh_frame_cache *
2489sh_alloc_frame_cache (void)
2490{
2491 struct sh_frame_cache *cache;
2492 int i;
2493
2494 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
2495
2496 /* Base address. */
2497 cache->base = 0;
2498 cache->saved_sp = 0;
2499 cache->sp_offset = 0;
2500 cache->pc = 0;
2501
2502 /* Frameless until proven otherwise. */
2503 cache->uses_fp = 0;
617daa0e 2504
1c0159e0
CV		 2505 /* Saved registers. We initialize these to -1 since zero is a valid
2506 offset (that's where fp is supposed to be stored). */
2507 for (i = 0; i < SH_NUM_REGS; i++)
2508 {
2509 cache->saved_regs[i] = -1;
2510 }
617daa0e 2511
1c0159e0 2512 return cache;
617daa0e 2513}
1c0159e0
CV		 2514
2515static struct sh_frame_cache *
94afd7a6 2516sh_frame_cache (struct frame_info *this_frame, void **this_cache)
1c0159e0 2517{
e17a4113 2518 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1c0159e0
CV		 2519 struct sh_frame_cache *cache;
2520 CORE_ADDR current_pc;
2521 int i;
2522
2523 if (*this_cache)
2524 return *this_cache;
2525
2526 cache = sh_alloc_frame_cache ();
2527 *this_cache = cache;
2528
2529 /* In principle, for normal frames, fp holds the frame pointer,
2530 which holds the base address for the current stack frame.
2531 However, for functions that don't need it, the frame pointer is
2532 optional. For these "frameless" functions the frame pointer is
2533 actually the frame pointer of the calling frame. */
94afd7a6 2534 cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM);
1c0159e0
CV		 2535 if (cache->base == 0)
2536 return cache;
2537
94afd7a6
UW		 2538 cache->pc = get_frame_func (this_frame);
2539 current_pc = get_frame_pc (this_frame);
1c0159e0 2540 if (cache->pc != 0)
d2ca4222
UW		 2541 {
2542 ULONGEST fpscr;
94afd7a6 2543 fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM);
e17a4113 2544 sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, fpscr);
d2ca4222 2545 }
617daa0e 2546
1c0159e0
CV		 2547 if (!cache->uses_fp)
2548 {
2549 /* We didn't find a valid frame, which means that CACHE->base
2550 currently holds the frame pointer for our calling frame. If
2551 we're at the start of a function, or somewhere half-way its
2552 prologue, the function's frame probably hasn't been fully
2553 setup yet. Try to reconstruct the base address for the stack
2554 frame by looking at the stack pointer. For truly "frameless"
2555 functions this might work too. */
94afd7a6 2556 cache->base = get_frame_register_unsigned
e17a4113 2557 (this_frame, gdbarch_sp_regnum (gdbarch));
1c0159e0
CV		 2558 }
2559
2560 /* Now that we have the base address for the stack frame we can
2561 calculate the value of sp in the calling frame. */
2562 cache->saved_sp = cache->base + cache->sp_offset;
2563
2564 /* Adjust all the saved registers such that they contain addresses
2565 instead of offsets. */
2566 for (i = 0; i < SH_NUM_REGS; i++)
2567 if (cache->saved_regs[i] != -1)
2568 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
2569
2570 return cache;
2571}
2572
94afd7a6
UW		 2573static struct value *
2574sh_frame_prev_register (struct frame_info *this_frame,
2575 void **this_cache, int regnum)
1c0159e0 2576{
94afd7a6
UW		 2577 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2578 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
1c0159e0
CV		 2579
2580 gdb_assert (regnum >= 0);
2581
b47193f7 2582 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
94afd7a6 2583 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
1c0159e0
CV		 2584
2585 /* The PC of the previous frame is stored in the PR register of
2586 the current frame. Frob regnum so that we pull the value from
2587 the correct place. */
b47193f7 2588 if (regnum == gdbarch_pc_regnum (gdbarch))
1c0159e0
CV		 2589 regnum = PR_REGNUM;
2590
2591 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
94afd7a6
UW		 2592 return frame_unwind_got_memory (this_frame, regnum,
2593 cache->saved_regs[regnum]);
1c0159e0 2594
94afd7a6 2595 return frame_unwind_got_register (this_frame, regnum, regnum);
1c0159e0
CV		 2596}
2597
2598static void
94afd7a6 2599sh_frame_this_id (struct frame_info *this_frame, void **this_cache,
617daa0e
CV		 2600 struct frame_id *this_id)
2601{
94afd7a6 2602 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
1c0159e0
CV		 2603
2604 /* This marks the outermost frame. */
2605 if (cache->base == 0)
2606 return;
2607
2608 *this_id = frame_id_build (cache->saved_sp, cache->pc);
617daa0e 2609}
1c0159e0 2610
617daa0e 2611static const struct frame_unwind sh_frame_unwind = {
1c0159e0
CV		 2612 NORMAL_FRAME,
2613 sh_frame_this_id,
94afd7a6
UW		 2614 sh_frame_prev_register,
2615 NULL,
2616 default_frame_sniffer
1c0159e0
CV		 2617};
2618
1c0159e0
CV		 2619static CORE_ADDR
2620sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2621{
3e8c568d 2622 return frame_unwind_register_unsigned (next_frame,
b47193f7 2623 gdbarch_sp_regnum (gdbarch));
1c0159e0
CV		 2624}
2625
2626static CORE_ADDR
2627sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2628{
3e8c568d 2629 return frame_unwind_register_unsigned (next_frame,
b47193f7 2630 gdbarch_pc_regnum (gdbarch));
1c0159e0
CV		 2631}
2632
2633static struct frame_id
94afd7a6 2634sh_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1c0159e0 2635{
94afd7a6
UW		 2636 CORE_ADDR sp = get_frame_register_unsigned (this_frame,
2637 gdbarch_sp_regnum (gdbarch));
2638 return frame_id_build (sp, get_frame_pc (this_frame));
1c0159e0
CV		 2639}
2640
2641static CORE_ADDR
94afd7a6 2642sh_frame_base_address (struct frame_info *this_frame, void **this_cache)
617daa0e 2643{
94afd7a6 2644 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
617daa0e 2645
1c0159e0
CV		 2646 return cache->base;
2647}
617daa0e
CV		 2648
2649static const struct frame_base sh_frame_base = {
1c0159e0
CV		 2650 &sh_frame_unwind,
2651 sh_frame_base_address,
2652 sh_frame_base_address,
2653 sh_frame_base_address
617daa0e 2654};
1c0159e0
CV		 2655
2656/* The epilogue is defined here as the area at the end of a function,
2657 either on the `ret' instruction itself or after an instruction which
2658 destroys the function's stack frame. */
2659static int
2660sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2661{
e17a4113 2662 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1c0159e0
CV		 2663 CORE_ADDR func_addr = 0, func_end = 0;
2664
2665 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2666 {
2667 ULONGEST inst;
2668 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2669 for a nop and some fixed data (e.g. big offsets) which are
617daa0e
CV		 2670 unfortunately also treated as part of the function (which
2671 means, they are below func_end. */
1c0159e0
CV		 2672 CORE_ADDR addr = func_end - 28;
2673 if (addr < func_addr + 4)
617daa0e 2674 addr = func_addr + 4;
1c0159e0
CV		 2675 if (pc < addr)
2676 return 0;
2677
2678 /* First search forward until hitting an rts. */
2679 while (addr < func_end
e17a4113 2680 && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order)))
1c0159e0
CV		 2681 addr += 2;
2682 if (addr >= func_end)
617daa0e 2683 return 0;
1c0159e0
CV		 2684
2685 /* At this point we should find a mov.l @r15+,r14 instruction,
2686 either before or after the rts. If not, then the function has
617daa0e 2687 probably no "normal" epilogue and we bail out here. */
e17a4113
UW		 2688 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2689 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2,
2690 byte_order)))
617daa0e 2691 addr -= 2;
e17a4113
UW		 2692 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2,
2693 byte_order)))
1c0159e0
CV		 2694 return 0;
2695
e17a4113 2696 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
03131d99
CV		 2697
2698 /* Step over possible lds.l @r15+,macl. */
2699 if (IS_MACL_LDS (inst))
2700 {
2701 addr -= 2;
e17a4113 2702 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
03131d99
CV		 2703 }
2704
2705 /* Step over possible lds.l @r15+,pr. */
1c0159e0 2706 if (IS_LDS (inst))
617daa0e 2707 {
1c0159e0 2708 addr -= 2;
e17a4113 2709 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
1c0159e0
CV		 2710 }
2711
2712 /* Step over possible mov r14,r15. */
2713 if (IS_MOV_FP_SP (inst))
617daa0e 2714 {
1c0159e0 2715 addr -= 2;
e17a4113 2716 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
1c0159e0
CV		 2717 }
2718
2719 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2720 instructions. */
2721 while (addr > func_addr + 4
617daa0e 2722 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
1c0159e0
CV		 2723 {
2724 addr -= 2;
e17a4113 2725 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
1c0159e0
CV		 2726 }
2727
03131d99
CV		 2728 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2729 That's allowed for the epilogue. */
2730 if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
2731 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
2732 && addr > func_addr + 6
e17a4113
UW		 2733 && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2,
2734 byte_order)))
03131d99
CV		 2735 addr -= 4;
2736
1c0159e0
CV		 2737 if (pc >= addr)
2738 return 1;
2739 }
2740 return 0;
2741}
c9ac0a72
AS		 2742
2743
2744/* Supply register REGNUM from the buffer specified by REGS and LEN
2745 in the register set REGSET to register cache REGCACHE.
2746 REGTABLE specifies where each register can be found in REGS.
2747 If REGNUM is -1, do this for all registers in REGSET. */
2748
2749void
2750sh_corefile_supply_regset (const struct regset *regset,
2751 struct regcache *regcache,
2752 int regnum, const void *regs, size_t len)
2753{
2754 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2755 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2756 const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
2757 ? tdep->core_gregmap
2758 : tdep->core_fpregmap);
2759 int i;
2760
2761 for (i = 0; regmap[i].regnum != -1; i++)
2762 {
2763 if ((regnum == -1 || regnum == regmap[i].regnum)
2764 && regmap[i].offset + 4 <= len)
2765 regcache_raw_supply (regcache, regmap[i].regnum,
2766 (char *)regs + regmap[i].offset);
2767 }
2768}
2769
2770/* Collect register REGNUM in the register set REGSET from register cache
2771 REGCACHE into the buffer specified by REGS and LEN.
2772 REGTABLE specifies where each register can be found in REGS.
2773 If REGNUM is -1, do this for all registers in REGSET. */
2774
2775void
2776sh_corefile_collect_regset (const struct regset *regset,
2777 const struct regcache *regcache,
2778 int regnum, void *regs, size_t len)
2779{
2780 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2781 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2782 const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
2783 ? tdep->core_gregmap
2784 : tdep->core_fpregmap);
2785 int i;
2786
2787 for (i = 0; regmap[i].regnum != -1; i++)
2788 {
2789 if ((regnum == -1 || regnum == regmap[i].regnum)
2790 && regmap[i].offset + 4 <= len)
2791 regcache_raw_collect (regcache, regmap[i].regnum,
2792 (char *)regs + regmap[i].offset);
2793 }
2794}
2795
2796/* The following two regsets have the same contents, so it is tempting to
2797 unify them, but they are distiguished by their address, so don't. */
2798
2799struct regset sh_corefile_gregset =
2800{
2801 NULL,
2802 sh_corefile_supply_regset,
2803 sh_corefile_collect_regset
2804};
2805
2806static struct regset sh_corefile_fpregset =
2807{
2808 NULL,
2809 sh_corefile_supply_regset,
2810 sh_corefile_collect_regset
2811};
2812
2813static const struct regset *
2814sh_regset_from_core_section (struct gdbarch *gdbarch, const char *sect_name,
2815 size_t sect_size)
2816{
2817 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2818
2819 if (tdep->core_gregmap && strcmp (sect_name, ".reg") == 0)
2820 return &sh_corefile_gregset;
2821
2822 if (tdep->core_fpregmap && strcmp (sect_name, ".reg2") == 0)
2823 return &sh_corefile_fpregset;
2824
2825 return NULL;
2826}
ccf00f21 2827\f
cc17453a
EZ		 2828
2829static struct gdbarch *
fba45db2 2830sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
cc17453a 2831{
cc17453a 2832 struct gdbarch *gdbarch;
c9ac0a72 2833 struct gdbarch_tdep *tdep;
d658f924 2834
55ff77ac
CV		 2835 sh_show_regs = sh_generic_show_regs;
2836 switch (info.bfd_arch_info->mach)
2837 {
617daa0e
CV		 2838 case bfd_mach_sh2e:
2839 sh_show_regs = sh2e_show_regs;
2840 break;
da962468
CV		 2841 case bfd_mach_sh2a:
2842 sh_show_regs = sh2a_show_regs;
2843 break;
2844 case bfd_mach_sh2a_nofpu:
2845 sh_show_regs = sh2a_nofpu_show_regs;
2846 break;
617daa0e
CV		 2847 case bfd_mach_sh_dsp:
2848 sh_show_regs = sh_dsp_show_regs;
2849 break;
55ff77ac 2850
617daa0e 2851 case bfd_mach_sh3:
46e8a76b
AS		 2852 case bfd_mach_sh3_nommu:
2853 case bfd_mach_sh2a_nofpu_or_sh3_nommu:
617daa0e
CV		 2854 sh_show_regs = sh3_show_regs;
2855 break;
55ff77ac 2856
617daa0e 2857 case bfd_mach_sh3e:
46e8a76b 2858 case bfd_mach_sh2a_or_sh3e:
617daa0e
CV		 2859 sh_show_regs = sh3e_show_regs;
2860 break;
55ff77ac 2861
617daa0e 2862 case bfd_mach_sh3_dsp:
474e5826 2863 case bfd_mach_sh4al_dsp:
617daa0e
CV		 2864 sh_show_regs = sh3_dsp_show_regs;
2865 break;
55ff77ac 2866
617daa0e 2867 case bfd_mach_sh4:
474e5826 2868 case bfd_mach_sh4a:
46e8a76b 2869 case bfd_mach_sh2a_or_sh4:
617daa0e
CV		 2870 sh_show_regs = sh4_show_regs;
2871 break;
55ff77ac 2872
474e5826 2873 case bfd_mach_sh4_nofpu:
46e8a76b 2874 case bfd_mach_sh4_nommu_nofpu:
474e5826 2875 case bfd_mach_sh4a_nofpu:
46e8a76b 2876 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
474e5826
CV		 2877 sh_show_regs = sh4_nofpu_show_regs;
2878 break;
2879
617daa0e
CV		 2880 case bfd_mach_sh5:
2881 sh_show_regs = sh64_show_regs;
2882 /* SH5 is handled entirely in sh64-tdep.c */
2883 return sh64_gdbarch_init (info, arches);
55ff77ac
CV		 2884 }
2885
4be87837
DJ		 2886 /* If there is already a candidate, use it. */
2887 arches = gdbarch_list_lookup_by_info (arches, &info);
2888 if (arches != NULL)
2889 return arches->gdbarch;
cc17453a
EZ		 2890
2891 /* None found, create a new architecture from the information
2892 provided. */
c9ac0a72
AS		 2893 tdep = XZALLOC (struct gdbarch_tdep);
2894 gdbarch = gdbarch_alloc (&info, tdep);
cc17453a 2895
48db5a3c
CV		 2896 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2897 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
ec920329 2898 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c
CV		 2899 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2900 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2901 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2902 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
a38d2a54 2903 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c 2904
f2ea0907 2905 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
a38d2a54 2906 set_gdbarch_sp_regnum (gdbarch, 15);
a38d2a54 2907 set_gdbarch_pc_regnum (gdbarch, 16);
48db5a3c
CV		 2908 set_gdbarch_fp0_regnum (gdbarch, -1);
2909 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2910
1c0159e0 2911 set_gdbarch_register_type (gdbarch, sh_default_register_type);
dda63807 2912 set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p);
1c0159e0 2913
eaf90c5d 2914 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
48db5a3c 2915
9dae60cc 2916 set_gdbarch_print_insn (gdbarch, print_insn_sh);
2f14585c 2917 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
48db5a3c 2918
c0409442 2919 set_gdbarch_return_value (gdbarch, sh_return_value_nofpu);
1c0159e0 2920
48db5a3c
CV		 2921 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2922 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
48db5a3c 2923
1c0159e0
CV		 2924 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2925
48db5a3c
CV		 2926 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2927
19f59343 2928 set_gdbarch_frame_align (gdbarch, sh_frame_align);
1c0159e0
CV		 2929 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2930 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
94afd7a6 2931 set_gdbarch_dummy_id (gdbarch, sh_dummy_id);
1c0159e0
CV		 2932 frame_base_set_default (gdbarch, &sh_frame_base);
2933
617daa0e 2934 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
cc17453a 2935
357d3800
AS		 2936 dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg);
2937
c9ac0a72
AS		 2938 set_gdbarch_regset_from_core_section (gdbarch, sh_regset_from_core_section);
2939
cc17453a 2940 switch (info.bfd_arch_info->mach)
8db62801 2941 {
cc17453a 2942 case bfd_mach_sh:
48db5a3c 2943 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
cc17453a 2944 break;
1c0159e0 2945
cc17453a 2946 case bfd_mach_sh2:
48db5a3c 2947 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
617daa0e 2948 break;
1c0159e0 2949
2d188dd3 2950 case bfd_mach_sh2e:
48db5a3c
CV		 2951 /* doubles on sh2e and sh3e are actually 4 byte. */
2952 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2953
2954 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
48db5a3c 2955 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2d188dd3 2956 set_gdbarch_fp0_regnum (gdbarch, 25);
c0409442 2957 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 2958 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2d188dd3 2959 break;
1c0159e0 2960
da962468
CV		 2961 case bfd_mach_sh2a:
2962 set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
2963 set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
2964 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2965
2966 set_gdbarch_fp0_regnum (gdbarch, 25);
2967 set_gdbarch_num_pseudo_regs (gdbarch, 9);
2968 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2969 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
c0409442 2970 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
da962468
CV		 2971 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2972 break;
2973
2974 case bfd_mach_sh2a_nofpu:
2975 set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
2976 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2977
2978 set_gdbarch_num_pseudo_regs (gdbarch, 1);
2979 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2980 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2981 break;
2982
cc17453a 2983 case bfd_mach_sh_dsp:
48db5a3c 2984 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2f14585c 2985 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a 2986 break;
1c0159e0 2987
cc17453a 2988 case bfd_mach_sh3:
4e6cbc38
AS		 2989 case bfd_mach_sh3_nommu:
2990 case bfd_mach_sh2a_nofpu_or_sh3_nommu:
48db5a3c 2991 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
cc17453a 2992 break;
1c0159e0 2993
cc17453a 2994 case bfd_mach_sh3e:
4e6cbc38 2995 case bfd_mach_sh2a_or_sh3e:
48db5a3c
CV		 2996 /* doubles on sh2e and sh3e are actually 4 byte. */
2997 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2998
2999 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
48db5a3c 3000 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
cc17453a 3001 set_gdbarch_fp0_regnum (gdbarch, 25);
c0409442 3002 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 3003 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
cc17453a 3004 break;
1c0159e0 3005
cc17453a 3006 case bfd_mach_sh3_dsp:
48db5a3c 3007 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
48db5a3c 3008 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a 3009 break;
1c0159e0 3010
cc17453a 3011 case bfd_mach_sh4:
474e5826 3012 case bfd_mach_sh4a:
46e8a76b 3013 case bfd_mach_sh2a_or_sh4:
48db5a3c 3014 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
48db5a3c 3015 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
cc17453a 3016 set_gdbarch_fp0_regnum (gdbarch, 25);
da962468 3017 set_gdbarch_num_pseudo_regs (gdbarch, 13);
d8124050
AC		 3018 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
3019 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
c0409442 3020 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 3021 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
cc17453a 3022 break;
1c0159e0 3023
474e5826
CV		 3024 case bfd_mach_sh4_nofpu:
3025 case bfd_mach_sh4a_nofpu:
4e6cbc38
AS		 3026 case bfd_mach_sh4_nommu_nofpu:
3027 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
474e5826
CV		 3028 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
3029 break;
3030
3031 case bfd_mach_sh4al_dsp:
3032 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
3033 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
3034 break;
3035
cc17453a 3036 default:
b58cbbf2 3037 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
cc17453a 3038 break;
8db62801 3039 }
cc17453a 3040
4be87837
DJ		 3041 /* Hook in ABI-specific overrides, if they have been registered. */
3042 gdbarch_init_osabi (info, gdbarch);
d658f924 3043
94afd7a6
UW		 3044 dwarf2_append_unwinders (gdbarch);
3045 frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind);
1c0159e0 3046
cc17453a 3047 return gdbarch;
8db62801
EZ		 3048}
3049
c055b101
CV		 3050static void
3051show_sh_command (char *args, int from_tty)
3052{
3053 help_list (showshcmdlist, "show sh ", all_commands, gdb_stdout);
3054}
3055
3056static void
3057set_sh_command (char *args, int from_tty)
3058{
3059 printf_unfiltered
3060 ("\"set sh\" must be followed by an appropriate subcommand.\n");
3061 help_list (setshcmdlist, "set sh ", all_commands, gdb_stdout);
3062}
3063
617daa0e 3064extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
a78f21af 3065
c906108c 3066void
fba45db2 3067_initialize_sh_tdep (void)
c906108c
SS		 3068{
3069 struct cmd_list_element *c;
617daa0e 3070
f2ea0907 3071 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
c906108c 3072
1bedd215 3073 add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers"));
c055b101
CV		 3074
3075 add_prefix_cmd ("sh", no_class, set_sh_command, "SH specific commands.",
3076 &setshcmdlist, "set sh ", 0, &setlist);
3077 add_prefix_cmd ("sh", no_class, show_sh_command, "SH specific commands.",
3078 &showshcmdlist, "show sh ", 0, &showlist);
3079
3080 add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum,
3081 &sh_active_calling_convention,
3082 _("Set calling convention used when calling target "
3083 "functions from GDB."),
3084 _("Show calling convention used when calling target "
3085 "functions from GDB."),
3086 _("gcc - Use GCC calling convention (default).\n"
3087 "renesas - Enforce Renesas calling convention."),
3088 NULL, NULL,
3089 &setshcmdlist, &showshcmdlist);
c906108c 3090}
GDB Binutils - Deliverables
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