Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for Hitachi Super-H, for GDB. |
1e698235 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 |
3116c80a | 3 | Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
21 | |
22 | /* | |
c5aa993b JM |
23 | Contributed by Steve Chamberlain |
24 | sac@cygnus.com | |
c906108c SS |
25 | */ |
26 | ||
27 | #include "defs.h" | |
28 | #include "frame.h" | |
c906108c SS |
29 | #include "symtab.h" |
30 | #include "symfile.h" | |
31 | #include "gdbtypes.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "gdbcore.h" | |
34 | #include "value.h" | |
35 | #include "dis-asm.h" | |
73c1f219 | 36 | #include "inferior.h" |
c906108c | 37 | #include "gdb_string.h" |
b4a20239 | 38 | #include "arch-utils.h" |
fb409745 | 39 | #include "floatformat.h" |
4e052eda | 40 | #include "regcache.h" |
d16aafd8 | 41 | #include "doublest.h" |
4be87837 | 42 | #include "osabi.h" |
c906108c | 43 | |
ab3b8126 JT |
44 | #include "sh-tdep.h" |
45 | ||
d658f924 | 46 | #include "elf-bfd.h" |
1a8629c7 MS |
47 | #include "solib-svr4.h" |
48 | ||
283150cd EZ |
49 | /* sh64 flags */ |
50 | #include "elf/sh.h" | |
51 | /* registers numbers shared with the simulator */ | |
1c922164 | 52 | #include "gdb/sim-sh.h" |
283150cd | 53 | |
53116e27 | 54 | void (*sh_show_regs) (void); |
3bbfbb92 EZ |
55 | CORE_ADDR (*skip_prologue_hard_way) (CORE_ADDR); |
56 | void (*do_pseudo_register) (int); | |
cc17453a | 57 | |
88e04cc1 EZ |
58 | #define SH_DEFAULT_NUM_REGS 59 |
59 | ||
cc17453a EZ |
60 | /* Define other aspects of the stack frame. |
61 | we keep a copy of the worked out return pc lying around, since it | |
62 | is a useful bit of info */ | |
63 | ||
64 | struct frame_extra_info | |
65 | { | |
66 | CORE_ADDR return_pc; | |
67 | int leaf_function; | |
68 | int f_offset; | |
63978407 | 69 | }; |
c906108c | 70 | |
fa88f677 | 71 | static const char * |
cc17453a | 72 | sh_generic_register_name (int reg_nr) |
c5aa993b | 73 | { |
cc17453a | 74 | static char *register_names[] = |
c5aa993b | 75 | { |
cc17453a EZ |
76 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
77 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
78 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
79 | "fpul", "fpscr", | |
80 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
81 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
82 | "ssr", "spc", | |
83 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
84 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
85 | }; | |
86 | if (reg_nr < 0) | |
87 | return NULL; | |
88 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
89 | return NULL; | |
90 | return register_names[reg_nr]; | |
91 | } | |
92 | ||
fa88f677 | 93 | static const char * |
cc17453a EZ |
94 | sh_sh_register_name (int reg_nr) |
95 | { | |
96 | static char *register_names[] = | |
63978407 | 97 | { |
cc17453a EZ |
98 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
99 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
100 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
101 | "", "", | |
102 | "", "", "", "", "", "", "", "", | |
103 | "", "", "", "", "", "", "", "", | |
104 | "", "", | |
105 | "", "", "", "", "", "", "", "", | |
106 | "", "", "", "", "", "", "", "", | |
107 | }; | |
108 | if (reg_nr < 0) | |
109 | return NULL; | |
110 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
111 | return NULL; | |
112 | return register_names[reg_nr]; | |
113 | } | |
114 | ||
fa88f677 | 115 | static const char * |
cc17453a EZ |
116 | sh_sh3_register_name (int reg_nr) |
117 | { | |
118 | static char *register_names[] = | |
c5aa993b | 119 | { |
cc17453a EZ |
120 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
121 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
122 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
123 | "", "", | |
124 | "", "", "", "", "", "", "", "", | |
125 | "", "", "", "", "", "", "", "", | |
126 | "ssr", "spc", | |
127 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
128 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1" | |
129 | }; | |
130 | if (reg_nr < 0) | |
131 | return NULL; | |
132 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
133 | return NULL; | |
134 | return register_names[reg_nr]; | |
135 | } | |
136 | ||
fa88f677 | 137 | static const char * |
cc17453a EZ |
138 | sh_sh3e_register_name (int reg_nr) |
139 | { | |
140 | static char *register_names[] = | |
63978407 | 141 | { |
cc17453a EZ |
142 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
143 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
144 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
145 | "fpul", "fpscr", | |
146 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
147 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
148 | "ssr", "spc", | |
149 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
150 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
151 | }; | |
152 | if (reg_nr < 0) | |
153 | return NULL; | |
154 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
155 | return NULL; | |
156 | return register_names[reg_nr]; | |
157 | } | |
158 | ||
fa88f677 | 159 | static const char * |
cc17453a EZ |
160 | sh_sh_dsp_register_name (int reg_nr) |
161 | { | |
162 | static char *register_names[] = | |
c5aa993b | 163 | { |
cc17453a EZ |
164 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
165 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
166 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
167 | "", "dsr", | |
168 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
169 | "y0", "y1", "", "", "", "", "", "mod", | |
170 | "", "", | |
171 | "rs", "re", "", "", "", "", "", "", | |
172 | "", "", "", "", "", "", "", "", | |
173 | }; | |
174 | if (reg_nr < 0) | |
175 | return NULL; | |
176 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
177 | return NULL; | |
178 | return register_names[reg_nr]; | |
179 | } | |
180 | ||
fa88f677 | 181 | static const char * |
cc17453a EZ |
182 | sh_sh3_dsp_register_name (int reg_nr) |
183 | { | |
184 | static char *register_names[] = | |
c5aa993b | 185 | { |
cc17453a EZ |
186 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
187 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
188 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
189 | "", "dsr", | |
190 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
191 | "y0", "y1", "", "", "", "", "", "mod", | |
192 | "ssr", "spc", | |
193 | "rs", "re", "", "", "", "", "", "", | |
194 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b" | |
195 | "", "", "", "", "", "", "", "", | |
196 | }; | |
197 | if (reg_nr < 0) | |
198 | return NULL; | |
199 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
200 | return NULL; | |
201 | return register_names[reg_nr]; | |
202 | } | |
203 | ||
fa88f677 | 204 | static const char * |
53116e27 EZ |
205 | sh_sh4_register_name (int reg_nr) |
206 | { | |
207 | static char *register_names[] = | |
208 | { | |
a38d2a54 | 209 | /* general registers 0-15 */ |
53116e27 EZ |
210 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
211 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
a38d2a54 | 212 | /* 16 - 22 */ |
53116e27 | 213 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", |
a38d2a54 | 214 | /* 23, 24 */ |
53116e27 | 215 | "fpul", "fpscr", |
a38d2a54 | 216 | /* floating point registers 25 - 40 */ |
53116e27 EZ |
217 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
218 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
a38d2a54 | 219 | /* 41, 42 */ |
53116e27 | 220 | "ssr", "spc", |
a38d2a54 | 221 | /* bank 0 43 - 50 */ |
53116e27 | 222 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
a38d2a54 | 223 | /* bank 1 51 - 58 */ |
53116e27 | 224 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", |
a38d2a54 | 225 | /* double precision (pseudo) 59 - 66 */ |
fe9f384f | 226 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", |
a38d2a54 | 227 | /* vectors (pseudo) 67 - 70 */ |
fe9f384f | 228 | "fv0", "fv4", "fv8", "fv12", |
a38d2a54 EZ |
229 | /* FIXME: missing XF 71 - 86 */ |
230 | /* FIXME: missing XD 87 - 94 */ | |
53116e27 EZ |
231 | }; |
232 | if (reg_nr < 0) | |
233 | return NULL; | |
234 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
235 | return NULL; | |
236 | return register_names[reg_nr]; | |
237 | } | |
238 | ||
fa88f677 | 239 | static const char * |
283150cd EZ |
240 | sh_sh64_register_name (int reg_nr) |
241 | { | |
242 | static char *register_names[] = | |
243 | { | |
244 | /* SH MEDIA MODE (ISA 32) */ | |
245 | /* general registers (64-bit) 0-63 */ | |
246 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
247 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
248 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
249 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
250 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", | |
251 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", | |
252 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", | |
253 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", | |
254 | ||
255 | /* pc (64-bit) 64 */ | |
256 | "pc", | |
257 | ||
258 | /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */ | |
259 | "sr", "ssr", "spc", | |
260 | ||
261 | /* target registers (64-bit) 68-75*/ | |
262 | "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", | |
263 | ||
264 | /* floating point state control register (32-bit) 76 */ | |
265 | "fpscr", | |
266 | ||
267 | /* single precision floating point registers (32-bit) 77-140*/ | |
268 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
269 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
270 | "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", | |
271 | "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", | |
272 | "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", | |
273 | "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", | |
274 | "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", | |
275 | "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", | |
276 | ||
277 | /* double precision registers (pseudo) 141-172 */ | |
278 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", | |
279 | "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", | |
280 | "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", | |
281 | "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62", | |
282 | ||
283 | /* floating point pairs (pseudo) 173-204*/ | |
284 | "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14", | |
285 | "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30", | |
286 | "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46", | |
287 | "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62", | |
288 | ||
289 | /* floating point vectors (4 floating point regs) (pseudo) 205-220*/ | |
290 | "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28", | |
291 | "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60", | |
292 | ||
293 | /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/ | |
294 | "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c", | |
295 | "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c", | |
296 | "pc_c", | |
297 | "gbr_c", "mach_c", "macl_c", "pr_c", "t_c", | |
298 | "fpscr_c", "fpul_c", | |
299 | "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c", | |
300 | "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c", | |
301 | "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c", | |
302 | "fv0_c", "fv4_c", "fv8_c", "fv12_c", | |
303 | /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/ | |
304 | }; | |
305 | ||
306 | if (reg_nr < 0) | |
307 | return NULL; | |
308 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
309 | return NULL; | |
310 | return register_names[reg_nr]; | |
311 | } | |
312 | ||
313 | #define NUM_PSEUDO_REGS_SH_MEDIA 80 | |
314 | #define NUM_PSEUDO_REGS_SH_COMPACT 51 | |
315 | ||
3117ed25 | 316 | static const unsigned char * |
fba45db2 | 317 | sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
cc17453a EZ |
318 | { |
319 | /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */ | |
320 | static unsigned char breakpoint[] = {0xc3, 0xc3}; | |
321 | ||
322 | *lenptr = sizeof (breakpoint); | |
323 | return breakpoint; | |
324 | } | |
c906108c | 325 | |
283150cd EZ |
326 | /* Macros and functions for setting and testing a bit in a minimal |
327 | symbol that marks it as 32-bit function. The MSB of the minimal | |
328 | symbol's "info" field is used for this purpose. This field is | |
329 | already being used to store the symbol size, so the assumption is | |
330 | that the symbol size cannot exceed 2^31. | |
331 | ||
332 | ELF_MAKE_MSYMBOL_SPECIAL | |
333 | tests whether an ELF symbol is "special", i.e. refers | |
334 | to a 32-bit function, and sets a "special" bit in a | |
335 | minimal symbol to mark it as a 32-bit function | |
336 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol | |
337 | MSYMBOL_SIZE returns the size of the minimal symbol, i.e. | |
338 | the "info" field with the "special" bit masked out */ | |
339 | ||
340 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
341 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
342 | ||
343 | void | |
344 | sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
345 | { | |
346 | if (msym == NULL) | |
347 | return; | |
348 | ||
349 | if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32) | |
350 | { | |
351 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
352 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
353 | } | |
354 | } | |
355 | ||
356 | /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here | |
357 | are some macros to test, set, or clear bit 0 of addresses. */ | |
358 | #define IS_ISA32_ADDR(addr) ((addr) & 1) | |
359 | #define MAKE_ISA32_ADDR(addr) ((addr) | 1) | |
360 | #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1) | |
361 | ||
362 | static int | |
363 | pc_is_isa32 (bfd_vma memaddr) | |
364 | { | |
365 | struct minimal_symbol *sym; | |
366 | ||
367 | /* If bit 0 of the address is set, assume this is a | |
368 | ISA32 (shmedia) address. */ | |
369 | if (IS_ISA32_ADDR (memaddr)) | |
370 | return 1; | |
371 | ||
372 | /* A flag indicating that this is a ISA32 function is stored by elfread.c in | |
373 | the high bit of the info field. Use this to decide if the function is | |
374 | ISA16 or ISA32. */ | |
375 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
376 | if (sym) | |
377 | return MSYMBOL_IS_SPECIAL (sym); | |
378 | else | |
379 | return 0; | |
380 | } | |
381 | ||
382 | static const unsigned char * | |
383 | sh_sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) | |
384 | { | |
385 | /* The BRK instruction for shmedia is | |
386 | 01101111 11110101 11111111 11110000 | |
387 | which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0 | |
388 | and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */ | |
389 | ||
390 | /* The BRK instruction for shcompact is | |
391 | 00000000 00111011 | |
392 | which translates in big endian mode to 0x0, 0x3b | |
393 | and in little endian mode to 0x3b, 0x0*/ | |
394 | ||
395 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
396 | { | |
397 | if (pc_is_isa32 (*pcptr)) | |
398 | { | |
399 | static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0}; | |
400 | *pcptr = UNMAKE_ISA32_ADDR (*pcptr); | |
401 | *lenptr = sizeof (big_breakpoint_media); | |
402 | return big_breakpoint_media; | |
403 | } | |
404 | else | |
405 | { | |
406 | static unsigned char big_breakpoint_compact[] = {0x0, 0x3b}; | |
407 | *lenptr = sizeof (big_breakpoint_compact); | |
408 | return big_breakpoint_compact; | |
409 | } | |
410 | } | |
411 | else | |
412 | { | |
413 | if (pc_is_isa32 (*pcptr)) | |
414 | { | |
415 | static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f}; | |
416 | *pcptr = UNMAKE_ISA32_ADDR (*pcptr); | |
417 | *lenptr = sizeof (little_breakpoint_media); | |
418 | return little_breakpoint_media; | |
419 | } | |
420 | else | |
421 | { | |
422 | static unsigned char little_breakpoint_compact[] = {0x3b, 0x0}; | |
423 | *lenptr = sizeof (little_breakpoint_compact); | |
424 | return little_breakpoint_compact; | |
425 | } | |
426 | } | |
427 | } | |
428 | ||
c906108c | 429 | /* Prologue looks like |
c5aa993b JM |
430 | [mov.l <regs>,@-r15]... |
431 | [sts.l pr,@-r15] | |
432 | [mov.l r14,@-r15] | |
433 | [mov r15,r14] | |
8db62801 EZ |
434 | |
435 | Actually it can be more complicated than this. For instance, with | |
436 | newer gcc's: | |
437 | ||
438 | mov.l r14,@-r15 | |
439 | add #-12,r15 | |
440 | mov r15,r14 | |
441 | mov r4,r1 | |
442 | mov r5,r2 | |
443 | mov.l r6,@(4,r14) | |
444 | mov.l r7,@(8,r14) | |
445 | mov.b r1,@r14 | |
446 | mov r14,r1 | |
447 | mov r14,r1 | |
448 | add #2,r1 | |
449 | mov.w r2,@r1 | |
450 | ||
c5aa993b | 451 | */ |
c906108c | 452 | |
283150cd EZ |
453 | /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000 |
454 | with l=1 and n = 18 0110101111110001010010100aaa0000 */ | |
455 | #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00) | |
456 | ||
457 | /* STS.L PR,@-r0 0100000000100010 | |
458 | r0-4-->r0, PR-->(r0) */ | |
459 | #define IS_STS_R0(x) ((x) == 0x4022) | |
460 | ||
461 | /* STS PR, Rm 0000mmmm00101010 | |
462 | PR-->Rm */ | |
463 | #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a) | |
464 | ||
465 | /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd | |
466 | Rm-->(dispx4+r15) */ | |
467 | #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00) | |
468 | ||
469 | /* MOV.L R14,@(disp,r15) 000111111110dddd | |
470 | R14-->(dispx4+r15) */ | |
471 | #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0) | |
472 | ||
473 | /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000 | |
474 | R18-->(dispx8+R14) */ | |
475 | #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120) | |
476 | ||
477 | /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000 | |
478 | R18-->(dispx8+R15) */ | |
479 | #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120) | |
480 | ||
481 | /* ST.L R15, disp, R18 101010001111dddddddddd0100100000 | |
482 | R18-->(dispx4+R15) */ | |
483 | #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120) | |
484 | ||
485 | /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000 | |
486 | R14-->(dispx8+R15) */ | |
487 | #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0) | |
488 | ||
489 | /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000 | |
490 | R14-->(dispx4+R15) */ | |
491 | #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0) | |
492 | ||
493 | /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000 | |
494 | R15 + imm --> R15 */ | |
495 | #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0) | |
496 | ||
497 | /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000 | |
498 | R15 + imm --> R15 */ | |
499 | #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0) | |
500 | ||
501 | /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000 | |
502 | R15 + R63 --> R14 */ | |
503 | #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0) | |
504 | ||
505 | /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000 | |
506 | R15 + R63 --> R14 */ | |
507 | #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0) | |
508 | ||
509 | #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x)) | |
510 | ||
511 | /* MOV #imm, R0 1110 0000 ssss ssss | |
512 | #imm-->R0 */ | |
513 | #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000) | |
514 | ||
515 | /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */ | |
516 | #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000) | |
517 | ||
518 | /* ADD r15,r0 0011 0000 1111 1100 | |
519 | r15+r0-->r0 */ | |
520 | #define IS_ADD_SP_R0(x) ((x) == 0x30fc) | |
521 | ||
522 | /* MOV.L R14 @-R0 0010 0000 1110 0110 | |
523 | R14-->(R0-4), R0-4-->R0 */ | |
524 | #define IS_MOV_R14_R0(x) ((x) == 0x20e6) | |
525 | ||
526 | /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000 | |
527 | where Rm is one of r2-r9 which are the argument registers. */ | |
528 | /* FIXME: Recognize the float and double register moves too! */ | |
529 | #define IS_MEDIA_IND_ARG_MOV(x) \ | |
530 | ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000)) | |
531 | ||
532 | /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000 | |
533 | or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000 | |
534 | where Rm is one of r2-r9 which are the argument registers. */ | |
535 | #define IS_MEDIA_ARG_MOV(x) \ | |
536 | (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \ | |
537 | && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090)) | |
538 | ||
539 | /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/ | |
540 | /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/ | |
541 | /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/ | |
542 | /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/ | |
543 | /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/ | |
544 | #define IS_MEDIA_MOV_TO_R14(x) \ | |
545 | ((((x) & 0xfffffc0f) == 0xa0e00000) \ | |
546 | || (((x) & 0xfffffc0f) == 0xa4e00000) \ | |
547 | || (((x) & 0xfffffc0f) == 0xa8e00000) \ | |
548 | || (((x) & 0xfffffc0f) == 0xb4e00000) \ | |
549 | || (((x) & 0xfffffc0f) == 0xbce00000)) | |
550 | ||
551 | /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011 | |
552 | where Rm is r2-r9 */ | |
553 | #define IS_COMPACT_IND_ARG_MOV(x) \ | |
554 | ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090)) | |
555 | ||
556 | /* compact direct arg move! | |
557 | MOV.L Rn, @r14 0010 1110 mmmm 0010 */ | |
558 | #define IS_COMPACT_ARG_MOV(x) \ | |
559 | (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090)) | |
560 | ||
561 | /* MOV.B Rm, @R14 0010 1110 mmmm 0000 | |
562 | MOV.W Rm, @R14 0010 1110 mmmm 0001 */ | |
563 | #define IS_COMPACT_MOV_TO_R14(x) \ | |
564 | ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01)) | |
565 | ||
566 | #define IS_JSR_R0(x) ((x) == 0x400b) | |
567 | #define IS_NOP(x) ((x) == 0x0009) | |
568 | ||
569 | ||
8db62801 EZ |
570 | /* STS.L PR,@-r15 0100111100100010 |
571 | r15-4-->r15, PR-->(r15) */ | |
c906108c | 572 | #define IS_STS(x) ((x) == 0x4f22) |
8db62801 EZ |
573 | |
574 | /* MOV.L Rm,@-r15 00101111mmmm0110 | |
575 | r15-4-->r15, Rm-->(R15) */ | |
c906108c | 576 | #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) |
8db62801 | 577 | |
c906108c | 578 | #define GET_PUSHED_REG(x) (((x) >> 4) & 0xf) |
8db62801 EZ |
579 | |
580 | /* MOV r15,r14 0110111011110011 | |
581 | r15-->r14 */ | |
c906108c | 582 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) |
8db62801 EZ |
583 | |
584 | /* ADD #imm,r15 01111111iiiiiiii | |
585 | r15+imm-->r15 */ | |
c906108c | 586 | #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00) |
8db62801 | 587 | |
c906108c SS |
588 | #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) |
589 | #define IS_SHLL_R3(x) ((x) == 0x4300) | |
8db62801 EZ |
590 | |
591 | /* ADD r3,r15 0011111100111100 | |
592 | r15+r3-->r15 */ | |
c906108c | 593 | #define IS_ADD_R3SP(x) ((x) == 0x3f3c) |
8db62801 EZ |
594 | |
595 | /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011 | |
8db62801 | 596 | FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011 |
8db62801 | 597 | FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */ |
c906108c | 598 | #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) |
c906108c | 599 | |
8db62801 | 600 | /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 |
8db62801 | 601 | MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd |
8db62801 EZ |
602 | MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010 |
603 | where Rm is one of r4,r5,r6,r7 which are the argument registers. */ | |
604 | #define IS_ARG_MOV(x) \ | |
605 | (((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \ | |
cc17453a EZ |
606 | || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \ |
607 | || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))) | |
8db62801 EZ |
608 | |
609 | /* MOV.L Rm,@(disp,r14) 00011110mmmmdddd | |
610 | Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */ | |
3bbfbb92 | 611 | #define IS_MOV_TO_R14(x) \ |
cc17453a | 612 | ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) |
8db62801 EZ |
613 | |
614 | #define FPSCR_SZ (1 << 20) | |
c906108c | 615 | |
c906108c SS |
616 | /* Skip any prologue before the guts of a function */ |
617 | ||
8db62801 EZ |
618 | /* Skip the prologue using the debug information. If this fails we'll |
619 | fall back on the 'guess' method below. */ | |
620 | static CORE_ADDR | |
fba45db2 | 621 | after_prologue (CORE_ADDR pc) |
8db62801 EZ |
622 | { |
623 | struct symtab_and_line sal; | |
624 | CORE_ADDR func_addr, func_end; | |
625 | ||
626 | /* If we can not find the symbol in the partial symbol table, then | |
627 | there is no hope we can determine the function's start address | |
628 | with this code. */ | |
629 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
630 | return 0; | |
631 | ||
632 | /* Get the line associated with FUNC_ADDR. */ | |
633 | sal = find_pc_line (func_addr, 0); | |
634 | ||
635 | /* There are only two cases to consider. First, the end of the source line | |
636 | is within the function bounds. In that case we return the end of the | |
637 | source line. Second is the end of the source line extends beyond the | |
638 | bounds of the current function. We need to use the slow code to | |
639 | examine instructions in that case. */ | |
640 | if (sal.end < func_end) | |
641 | return sal.end; | |
642 | else | |
643 | return 0; | |
644 | } | |
645 | ||
646 | /* Here we look at each instruction in the function, and try to guess | |
647 | where the prologue ends. Unfortunately this is not always | |
648 | accurate. */ | |
649 | static CORE_ADDR | |
3bbfbb92 | 650 | sh_skip_prologue_hard_way (CORE_ADDR start_pc) |
c906108c | 651 | { |
2bfa91ee | 652 | CORE_ADDR here, end; |
8db62801 | 653 | int updated_fp = 0; |
2bfa91ee EZ |
654 | |
655 | if (!start_pc) | |
656 | return 0; | |
657 | ||
658 | for (here = start_pc, end = start_pc + (2 * 28); here < end;) | |
c906108c | 659 | { |
2bfa91ee EZ |
660 | int w = read_memory_integer (here, 2); |
661 | here += 2; | |
662 | if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w) | |
8db62801 | 663 | || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w) |
3bbfbb92 | 664 | || IS_ARG_MOV (w) || IS_MOV_TO_R14 (w)) |
2bfa91ee EZ |
665 | { |
666 | start_pc = here; | |
2bfa91ee | 667 | } |
8db62801 EZ |
668 | else if (IS_MOV_SP_FP (w)) |
669 | { | |
670 | start_pc = here; | |
671 | updated_fp = 1; | |
672 | } | |
673 | else | |
674 | /* Don't bail out yet, if we are before the copy of sp. */ | |
675 | if (updated_fp) | |
676 | break; | |
c906108c SS |
677 | } |
678 | ||
679 | return start_pc; | |
680 | } | |
681 | ||
283150cd EZ |
682 | static CORE_ADDR |
683 | look_for_args_moves (CORE_ADDR start_pc, int media_mode) | |
684 | { | |
685 | CORE_ADDR here, end; | |
686 | int w; | |
687 | int insn_size = (media_mode ? 4 : 2); | |
688 | ||
689 | for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) | |
690 | { | |
691 | if (media_mode) | |
692 | { | |
693 | w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size); | |
694 | here += insn_size; | |
695 | if (IS_MEDIA_IND_ARG_MOV (w)) | |
696 | { | |
697 | /* This must be followed by a store to r14, so the argument | |
698 | is where the debug info says it is. This can happen after | |
699 | the SP has been saved, unfortunately. */ | |
700 | ||
701 | int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here), | |
702 | insn_size); | |
703 | here += insn_size; | |
704 | if (IS_MEDIA_MOV_TO_R14 (next_insn)) | |
705 | start_pc = here; | |
706 | } | |
707 | else if (IS_MEDIA_ARG_MOV (w)) | |
708 | { | |
709 | /* These instructions store directly the argument in r14. */ | |
710 | start_pc = here; | |
711 | } | |
712 | else | |
713 | break; | |
714 | } | |
715 | else | |
716 | { | |
717 | w = read_memory_integer (here, insn_size); | |
718 | w = w & 0xffff; | |
719 | here += insn_size; | |
720 | if (IS_COMPACT_IND_ARG_MOV (w)) | |
721 | { | |
722 | /* This must be followed by a store to r14, so the argument | |
723 | is where the debug info says it is. This can happen after | |
724 | the SP has been saved, unfortunately. */ | |
725 | ||
726 | int next_insn = 0xffff & read_memory_integer (here, insn_size); | |
727 | here += insn_size; | |
728 | if (IS_COMPACT_MOV_TO_R14 (next_insn)) | |
729 | start_pc = here; | |
730 | } | |
731 | else if (IS_COMPACT_ARG_MOV (w)) | |
732 | { | |
733 | /* These instructions store directly the argument in r14. */ | |
734 | start_pc = here; | |
735 | } | |
736 | else if (IS_MOVL_R0 (w)) | |
737 | { | |
738 | /* There is a function that gcc calls to get the arguments | |
739 | passed correctly to the function. Only after this | |
740 | function call the arguments will be found at the place | |
741 | where they are supposed to be. This happens in case the | |
742 | argument has to be stored into a 64-bit register (for | |
743 | instance doubles, long longs). SHcompact doesn't have | |
744 | access to the full 64-bits, so we store the register in | |
745 | stack slot and store the address of the stack slot in | |
746 | the register, then do a call through a wrapper that | |
747 | loads the memory value into the register. A SHcompact | |
748 | callee calls an argument decoder | |
749 | (GCC_shcompact_incoming_args) that stores the 64-bit | |
750 | value in a stack slot and stores the address of the | |
751 | stack slot in the register. GCC thinks the argument is | |
752 | just passed by transparent reference, but this is only | |
753 | true after the argument decoder is called. Such a call | |
754 | needs to be considered part of the prologue. */ | |
755 | ||
756 | /* This must be followed by a JSR @r0 instruction and by | |
757 | a NOP instruction. After these, the prologue is over! */ | |
758 | ||
759 | int next_insn = 0xffff & read_memory_integer (here, insn_size); | |
760 | here += insn_size; | |
761 | if (IS_JSR_R0 (next_insn)) | |
762 | { | |
763 | next_insn = 0xffff & read_memory_integer (here, insn_size); | |
764 | here += insn_size; | |
765 | ||
766 | if (IS_NOP (next_insn)) | |
767 | start_pc = here; | |
768 | } | |
769 | } | |
770 | else | |
771 | break; | |
772 | } | |
773 | } | |
774 | ||
775 | return start_pc; | |
776 | } | |
777 | ||
778 | static CORE_ADDR | |
779 | sh64_skip_prologue_hard_way (CORE_ADDR start_pc) | |
780 | { | |
781 | CORE_ADDR here, end; | |
782 | int updated_fp = 0; | |
783 | int insn_size = 4; | |
784 | int media_mode = 1; | |
785 | ||
786 | if (!start_pc) | |
787 | return 0; | |
788 | ||
789 | if (pc_is_isa32 (start_pc) == 0) | |
790 | { | |
791 | insn_size = 2; | |
792 | media_mode = 0; | |
793 | } | |
794 | ||
795 | for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) | |
796 | { | |
797 | ||
798 | if (media_mode) | |
799 | { | |
800 | int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size); | |
801 | here += insn_size; | |
802 | if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w) | |
803 | || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w) | |
804 | || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w)) | |
805 | { | |
806 | start_pc = here; | |
807 | } | |
808 | else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w)) | |
809 | { | |
810 | start_pc = here; | |
811 | updated_fp = 1; | |
812 | } | |
813 | else | |
814 | if (updated_fp) | |
815 | { | |
816 | /* Don't bail out yet, we may have arguments stored in | |
817 | registers here, according to the debug info, so that | |
818 | gdb can print the frames correctly. */ | |
819 | start_pc = look_for_args_moves (here - insn_size, media_mode); | |
820 | break; | |
821 | } | |
822 | } | |
823 | else | |
824 | { | |
825 | int w = 0xffff & read_memory_integer (here, insn_size); | |
826 | here += insn_size; | |
827 | ||
828 | if (IS_STS_R0 (w) || IS_STS_PR (w) | |
829 | || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w) | |
830 | || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w)) | |
831 | { | |
832 | start_pc = here; | |
833 | } | |
834 | else if (IS_MOV_SP_FP (w)) | |
835 | { | |
836 | start_pc = here; | |
837 | updated_fp = 1; | |
838 | } | |
839 | else | |
840 | if (updated_fp) | |
841 | { | |
842 | /* Don't bail out yet, we may have arguments stored in | |
843 | registers here, according to the debug info, so that | |
844 | gdb can print the frames correctly. */ | |
845 | start_pc = look_for_args_moves (here - insn_size, media_mode); | |
846 | break; | |
847 | } | |
848 | } | |
849 | } | |
850 | ||
851 | return start_pc; | |
852 | } | |
853 | ||
cc17453a | 854 | static CORE_ADDR |
fba45db2 | 855 | sh_skip_prologue (CORE_ADDR pc) |
8db62801 EZ |
856 | { |
857 | CORE_ADDR post_prologue_pc; | |
858 | ||
859 | /* See if we can determine the end of the prologue via the symbol table. | |
860 | If so, then return either PC, or the PC after the prologue, whichever | |
861 | is greater. */ | |
8db62801 EZ |
862 | post_prologue_pc = after_prologue (pc); |
863 | ||
864 | /* If after_prologue returned a useful address, then use it. Else | |
865 | fall back on the instruction skipping code. */ | |
866 | if (post_prologue_pc != 0) | |
867 | return max (pc, post_prologue_pc); | |
868 | else | |
869 | return (skip_prologue_hard_way (pc)); | |
870 | } | |
871 | ||
cc17453a EZ |
872 | /* Immediately after a function call, return the saved pc. |
873 | Can't always go through the frames for this because on some machines | |
874 | the new frame is not set up until the new function executes | |
875 | some instructions. | |
876 | ||
877 | The return address is the value saved in the PR register + 4 */ | |
878 | static CORE_ADDR | |
fba45db2 | 879 | sh_saved_pc_after_call (struct frame_info *frame) |
cc17453a | 880 | { |
3bbfbb92 | 881 | return (ADDR_BITS_REMOVE (read_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM))); |
cc17453a EZ |
882 | } |
883 | ||
884 | /* Should call_function allocate stack space for a struct return? */ | |
885 | static int | |
fba45db2 | 886 | sh_use_struct_convention (int gcc_p, struct type *type) |
cc17453a | 887 | { |
7079c36c | 888 | #if 0 |
cc17453a | 889 | return (TYPE_LENGTH (type) > 1); |
7079c36c CV |
890 | #else |
891 | int len = TYPE_LENGTH (type); | |
892 | int nelem = TYPE_NFIELDS (type); | |
893 | return ((len != 1 && len != 2 && len != 4 && len != 8) || nelem != 1) && | |
894 | (len != 8 || TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) != 4); | |
895 | #endif | |
cc17453a EZ |
896 | } |
897 | ||
283150cd EZ |
898 | static int |
899 | sh64_use_struct_convention (int gcc_p, struct type *type) | |
900 | { | |
901 | return (TYPE_LENGTH (type) > 8); | |
902 | } | |
903 | ||
cc17453a EZ |
904 | /* Store the address of the place in which to copy the structure the |
905 | subroutine will return. This is called from call_function. | |
906 | ||
3bbfbb92 | 907 | We store structs through a pointer passed in R2 */ |
cc17453a | 908 | static void |
fba45db2 | 909 | sh_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) |
cc17453a EZ |
910 | { |
911 | write_register (STRUCT_RETURN_REGNUM, (addr)); | |
912 | } | |
c906108c | 913 | |
cc17453a EZ |
914 | /* Disassemble an instruction. */ |
915 | static int | |
fba45db2 | 916 | gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info) |
c906108c | 917 | { |
1c509ca8 JR |
918 | info->endian = TARGET_BYTE_ORDER; |
919 | return print_insn_sh (memaddr, info); | |
283150cd EZ |
920 | } |
921 | ||
a5afb99f AC |
922 | /* Given a GDB frame, determine the address of the calling function's |
923 | frame. This will be used to create a new GDB frame struct, and | |
924 | then INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC will be | |
925 | called for the new frame. | |
c906108c SS |
926 | |
927 | For us, the frame address is its stack pointer value, so we look up | |
928 | the function prologue to determine the caller's sp value, and return it. */ | |
cc17453a | 929 | static CORE_ADDR |
fba45db2 | 930 | sh_frame_chain (struct frame_info *frame) |
c906108c | 931 | { |
1e2330ba AC |
932 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), |
933 | get_frame_base (frame), | |
934 | get_frame_base (frame))) | |
935 | return get_frame_base (frame); /* dummy frame same as caller's frame */ | |
50abf9e5 | 936 | if (get_frame_pc (frame) && !inside_entry_file (get_frame_pc (frame))) |
da50a4b7 AC |
937 | return read_memory_integer (get_frame_base (frame) |
938 | + get_frame_extra_info (frame)->f_offset, 4); | |
c906108c SS |
939 | else |
940 | return 0; | |
941 | } | |
942 | ||
283150cd EZ |
943 | /* Given a register number RN as it appears in an assembly |
944 | instruction, find the corresponding register number in the GDB | |
945 | scheme. */ | |
946 | static int | |
947 | translate_insn_rn (int rn, int media_mode) | |
948 | { | |
949 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
950 | ||
951 | /* FIXME: this assumes that the number rn is for a not pseudo | |
952 | register only. */ | |
953 | if (media_mode) | |
954 | return rn; | |
955 | else | |
956 | { | |
957 | /* These registers don't have a corresponding compact one. */ | |
958 | /* FIXME: This is probably not enough. */ | |
959 | #if 0 | |
960 | if ((rn >= 16 && rn <= 63) || (rn >= 93 && rn <= 140)) | |
961 | return rn; | |
962 | #endif | |
963 | if (rn >= 0 && rn <= tdep->R0_C_REGNUM) | |
964 | return tdep->R0_C_REGNUM + rn; | |
965 | else | |
966 | return rn; | |
967 | } | |
968 | } | |
969 | ||
970 | static CORE_ADDR | |
971 | sh64_frame_chain (struct frame_info *frame) | |
972 | { | |
1e2330ba AC |
973 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), |
974 | get_frame_base (frame), | |
975 | get_frame_base (frame))) | |
976 | return get_frame_base (frame); /* dummy frame same as caller's frame */ | |
50abf9e5 | 977 | if (get_frame_pc (frame) && !inside_entry_file (get_frame_pc (frame))) |
283150cd | 978 | { |
50abf9e5 | 979 | int media_mode = pc_is_isa32 (get_frame_pc (frame)); |
283150cd EZ |
980 | int size; |
981 | if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32) | |
982 | size = 4; | |
983 | else | |
984 | size = REGISTER_RAW_SIZE (translate_insn_rn (FP_REGNUM, media_mode)); | |
da50a4b7 AC |
985 | return read_memory_integer (get_frame_base (frame) |
986 | + get_frame_extra_info (frame)->f_offset, | |
987 | size); | |
283150cd EZ |
988 | } |
989 | else | |
990 | return 0; | |
991 | } | |
992 | ||
c906108c SS |
993 | /* Find REGNUM on the stack. Otherwise, it's in an active register. One thing |
994 | we might want to do here is to check REGNUM against the clobber mask, and | |
995 | somehow flag it as invalid if it isn't saved on the stack somewhere. This | |
996 | would provide a graceful failure mode when trying to get the value of | |
997 | caller-saves registers for an inner frame. */ | |
cc17453a | 998 | static CORE_ADDR |
fba45db2 | 999 | sh_find_callers_reg (struct frame_info *fi, int regnum) |
c906108c | 1000 | { |
11c02a10 | 1001 | for (; fi; fi = get_next_frame (fi)) |
1e2330ba AC |
1002 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi), |
1003 | get_frame_base (fi))) | |
c906108c | 1004 | /* When the caller requests PR from the dummy frame, we return PC because |
c5aa993b | 1005 | that's where the previous routine appears to have done a call from. */ |
1e2330ba AC |
1006 | return deprecated_read_register_dummy (get_frame_pc (fi), |
1007 | get_frame_base (fi), regnum); | |
c5aa993b | 1008 | else |
c906108c | 1009 | { |
cc17453a | 1010 | FRAME_INIT_SAVED_REGS (fi); |
50abf9e5 | 1011 | if (!get_frame_pc (fi)) |
2bfa91ee | 1012 | return 0; |
b2fb4676 AC |
1013 | if (get_frame_saved_regs (fi)[regnum] != 0) |
1014 | return read_memory_integer (get_frame_saved_regs (fi)[regnum], | |
c5aa993b | 1015 | REGISTER_RAW_SIZE (regnum)); |
c906108c SS |
1016 | } |
1017 | return read_register (regnum); | |
1018 | } | |
1019 | ||
283150cd EZ |
1020 | static CORE_ADDR |
1021 | sh64_get_saved_pr (struct frame_info *fi, int pr_regnum) | |
1022 | { | |
1023 | int media_mode = 0; | |
1024 | ||
11c02a10 | 1025 | for (; fi; fi = get_next_frame (fi)) |
1e2330ba AC |
1026 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi), |
1027 | get_frame_base (fi))) | |
283150cd EZ |
1028 | /* When the caller requests PR from the dummy frame, we return PC because |
1029 | that's where the previous routine appears to have done a call from. */ | |
1e2330ba AC |
1030 | return deprecated_read_register_dummy (get_frame_pc (fi), |
1031 | get_frame_base (fi), pr_regnum); | |
283150cd EZ |
1032 | else |
1033 | { | |
1034 | FRAME_INIT_SAVED_REGS (fi); | |
50abf9e5 | 1035 | if (!get_frame_pc (fi)) |
283150cd EZ |
1036 | return 0; |
1037 | ||
50abf9e5 | 1038 | media_mode = pc_is_isa32 (get_frame_pc (fi)); |
283150cd | 1039 | |
b2fb4676 | 1040 | if (get_frame_saved_regs (fi)[pr_regnum] != 0) |
283150cd EZ |
1041 | { |
1042 | int gdb_reg_num = translate_insn_rn (pr_regnum, media_mode); | |
1043 | int size = ((gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32) | |
1044 | ? 4 | |
1045 | : REGISTER_RAW_SIZE (gdb_reg_num)); | |
b2fb4676 | 1046 | return read_memory_integer (get_frame_saved_regs (fi)[pr_regnum], size); |
283150cd EZ |
1047 | } |
1048 | } | |
1049 | return read_register (pr_regnum); | |
1050 | } | |
1051 | ||
c906108c SS |
1052 | /* Put here the code to store, into a struct frame_saved_regs, the |
1053 | addresses of the saved registers of frame described by FRAME_INFO. | |
1054 | This includes special registers such as pc and fp saved in special | |
1055 | ways in the stack frame. sp is even more special: the address we | |
1056 | return for it IS the sp for the next frame. */ | |
cc17453a | 1057 | static void |
fba45db2 | 1058 | sh_nofp_frame_init_saved_regs (struct frame_info *fi) |
c906108c | 1059 | { |
e7d717c0 | 1060 | int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof(int)); |
c906108c SS |
1061 | int rn; |
1062 | int have_fp = 0; | |
1063 | int depth; | |
1064 | int pc; | |
1065 | int opc; | |
1066 | int insn; | |
1067 | int r3_val = 0; | |
1e2330ba AC |
1068 | char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), |
1069 | get_frame_base (fi)); | |
cc17453a | 1070 | |
b2fb4676 | 1071 | if (get_frame_saved_regs (fi) == NULL) |
cc17453a EZ |
1072 | frame_saved_regs_zalloc (fi); |
1073 | else | |
b2fb4676 | 1074 | memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS); |
cc17453a EZ |
1075 | |
1076 | if (dummy_regs) | |
1077 | { | |
1078 | /* DANGER! This is ONLY going to work if the char buffer format of | |
1079 | the saved registers is byte-for-byte identical to the | |
1080 | CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */ | |
7b5849cc | 1081 | memcpy (get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS); |
cc17453a EZ |
1082 | return; |
1083 | } | |
1084 | ||
da50a4b7 AC |
1085 | get_frame_extra_info (fi)->leaf_function = 1; |
1086 | get_frame_extra_info (fi)->f_offset = 0; | |
cc17453a | 1087 | |
cd4bffcf | 1088 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) |
cc17453a EZ |
1089 | where[rn] = -1; |
1090 | ||
1091 | depth = 0; | |
1092 | ||
1093 | /* Loop around examining the prologue insns until we find something | |
1094 | that does not appear to be part of the prologue. But give up | |
1095 | after 20 of them, since we're getting silly then. */ | |
1096 | ||
50abf9e5 | 1097 | pc = get_pc_function_start (get_frame_pc (fi)); |
cc17453a EZ |
1098 | if (!pc) |
1099 | { | |
50abf9e5 | 1100 | deprecated_update_frame_pc_hack (fi, 0); |
cc17453a EZ |
1101 | return; |
1102 | } | |
1103 | ||
1104 | for (opc = pc + (2 * 28); pc < opc; pc += 2) | |
1105 | { | |
1106 | insn = read_memory_integer (pc, 2); | |
1107 | /* See where the registers will be saved to */ | |
1108 | if (IS_PUSH (insn)) | |
1109 | { | |
1110 | rn = GET_PUSHED_REG (insn); | |
1111 | where[rn] = depth; | |
1112 | depth += 4; | |
1113 | } | |
1114 | else if (IS_STS (insn)) | |
1115 | { | |
3bbfbb92 | 1116 | where[gdbarch_tdep (current_gdbarch)->PR_REGNUM] = depth; |
cc17453a | 1117 | /* If we're storing the pr then this isn't a leaf */ |
da50a4b7 | 1118 | get_frame_extra_info (fi)->leaf_function = 0; |
cc17453a EZ |
1119 | depth += 4; |
1120 | } | |
1121 | else if (IS_MOV_R3 (insn)) | |
1122 | { | |
1123 | r3_val = ((insn & 0xff) ^ 0x80) - 0x80; | |
1124 | } | |
1125 | else if (IS_SHLL_R3 (insn)) | |
1126 | { | |
1127 | r3_val <<= 1; | |
1128 | } | |
1129 | else if (IS_ADD_R3SP (insn)) | |
1130 | { | |
1131 | depth += -r3_val; | |
1132 | } | |
1133 | else if (IS_ADD_SP (insn)) | |
1134 | { | |
1135 | depth -= ((insn & 0xff) ^ 0x80) - 0x80; | |
1136 | } | |
1137 | else if (IS_MOV_SP_FP (insn)) | |
1138 | break; | |
1139 | #if 0 /* This used to just stop when it found an instruction that | |
1140 | was not considered part of the prologue. Now, we just | |
1141 | keep going looking for likely instructions. */ | |
1142 | else | |
1143 | break; | |
1144 | #endif | |
1145 | } | |
1146 | ||
1147 | /* Now we know how deep things are, we can work out their addresses */ | |
1148 | ||
cd4bffcf | 1149 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) |
cc17453a EZ |
1150 | { |
1151 | if (where[rn] >= 0) | |
1152 | { | |
1153 | if (rn == FP_REGNUM) | |
1154 | have_fp = 1; | |
c906108c | 1155 | |
1e2330ba | 1156 | get_frame_saved_regs (fi)[rn] = get_frame_base (fi) - where[rn] + depth - 4; |
cc17453a EZ |
1157 | } |
1158 | else | |
1159 | { | |
b2fb4676 | 1160 | get_frame_saved_regs (fi)[rn] = 0; |
cc17453a EZ |
1161 | } |
1162 | } | |
1163 | ||
1164 | if (have_fp) | |
1165 | { | |
b2fb4676 | 1166 | get_frame_saved_regs (fi)[SP_REGNUM] = read_memory_integer (get_frame_saved_regs (fi)[FP_REGNUM], 4); |
cc17453a EZ |
1167 | } |
1168 | else | |
1169 | { | |
1e2330ba | 1170 | get_frame_saved_regs (fi)[SP_REGNUM] = get_frame_base (fi) - 4; |
cc17453a EZ |
1171 | } |
1172 | ||
da50a4b7 | 1173 | get_frame_extra_info (fi)->f_offset = depth - where[FP_REGNUM] - 4; |
cc17453a EZ |
1174 | /* Work out the return pc - either from the saved pr or the pr |
1175 | value */ | |
1176 | } | |
1177 | ||
3bbfbb92 EZ |
1178 | /* For vectors of 4 floating point registers. */ |
1179 | static int | |
1180 | fv_reg_base_num (int fv_regnum) | |
1181 | { | |
1182 | int fp_regnum; | |
1183 | ||
1184 | fp_regnum = FP0_REGNUM + | |
1185 | (fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM) * 4; | |
1186 | return fp_regnum; | |
1187 | } | |
1188 | ||
1189 | /* For double precision floating point registers, i.e 2 fp regs.*/ | |
1190 | static int | |
1191 | dr_reg_base_num (int dr_regnum) | |
1192 | { | |
1193 | int fp_regnum; | |
1194 | ||
1195 | fp_regnum = FP0_REGNUM + | |
1196 | (dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM) * 2; | |
1197 | return fp_regnum; | |
1198 | } | |
1199 | ||
283150cd EZ |
1200 | /* For pairs of floating point registers */ |
1201 | static int | |
1202 | fpp_reg_base_num (int fpp_regnum) | |
1203 | { | |
1204 | int fp_regnum; | |
1205 | ||
1206 | fp_regnum = FP0_REGNUM + | |
1207 | (fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM) * 2; | |
1208 | return fp_regnum; | |
1209 | } | |
1210 | ||
1211 | static int | |
1212 | is_media_pseudo (int rn) | |
1213 | { | |
1214 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1215 | ||
1216 | return (rn >= tdep->DR0_REGNUM | |
1217 | && rn <= tdep->FV_LAST_REGNUM); | |
1218 | } | |
1219 | ||
1220 | int | |
1221 | sh64_get_gdb_regnum (int gcc_regnum, CORE_ADDR pc) | |
1222 | { | |
1223 | return translate_insn_rn (gcc_regnum, pc_is_isa32 (pc)); | |
1224 | } | |
1225 | ||
1226 | static int | |
1227 | sh64_media_reg_base_num (int reg_nr) | |
1228 | { | |
1229 | int base_regnum = -1; | |
1230 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1231 | ||
1232 | if (reg_nr >= tdep->DR0_REGNUM | |
1233 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
1234 | base_regnum = dr_reg_base_num (reg_nr); | |
1235 | ||
1236 | else if (reg_nr >= tdep->FPP0_REGNUM | |
1237 | && reg_nr <= tdep->FPP_LAST_REGNUM) | |
1238 | base_regnum = fpp_reg_base_num (reg_nr); | |
1239 | ||
1240 | else if (reg_nr >= tdep->FV0_REGNUM | |
1241 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
1242 | base_regnum = fv_reg_base_num (reg_nr); | |
1243 | ||
1244 | return base_regnum; | |
1245 | } | |
1246 | ||
1247 | /* *INDENT-OFF* */ | |
1248 | /* | |
1249 | SH COMPACT MODE (ISA 16) (all pseudo) 221-272 | |
1250 | GDB_REGNUM BASE_REGNUM | |
1251 | r0_c 221 0 | |
1252 | r1_c 222 1 | |
1253 | r2_c 223 2 | |
1254 | r3_c 224 3 | |
1255 | r4_c 225 4 | |
1256 | r5_c 226 5 | |
1257 | r6_c 227 6 | |
1258 | r7_c 228 7 | |
1259 | r8_c 229 8 | |
1260 | r9_c 230 9 | |
1261 | r10_c 231 10 | |
1262 | r11_c 232 11 | |
1263 | r12_c 233 12 | |
1264 | r13_c 234 13 | |
1265 | r14_c 235 14 | |
1266 | r15_c 236 15 | |
1267 | ||
1268 | pc_c 237 64 | |
1269 | gbr_c 238 16 | |
1270 | mach_c 239 17 | |
1271 | macl_c 240 17 | |
1272 | pr_c 241 18 | |
1273 | t_c 242 19 | |
1274 | fpscr_c 243 76 | |
1275 | fpul_c 244 109 | |
1276 | ||
1277 | fr0_c 245 77 | |
1278 | fr1_c 246 78 | |
1279 | fr2_c 247 79 | |
1280 | fr3_c 248 80 | |
1281 | fr4_c 249 81 | |
1282 | fr5_c 250 82 | |
1283 | fr6_c 251 83 | |
1284 | fr7_c 252 84 | |
1285 | fr8_c 253 85 | |
1286 | fr9_c 254 86 | |
1287 | fr10_c 255 87 | |
1288 | fr11_c 256 88 | |
1289 | fr12_c 257 89 | |
1290 | fr13_c 258 90 | |
1291 | fr14_c 259 91 | |
1292 | fr15_c 260 92 | |
1293 | ||
1294 | dr0_c 261 77 | |
1295 | dr2_c 262 79 | |
1296 | dr4_c 263 81 | |
1297 | dr6_c 264 83 | |
1298 | dr8_c 265 85 | |
1299 | dr10_c 266 87 | |
1300 | dr12_c 267 89 | |
1301 | dr14_c 268 91 | |
1302 | ||
1303 | fv0_c 269 77 | |
1304 | fv4_c 270 81 | |
1305 | fv8_c 271 85 | |
1306 | fv12_c 272 91 | |
1307 | */ | |
1308 | /* *INDENT-ON* */ | |
1309 | static int | |
1310 | sh64_compact_reg_base_num (int reg_nr) | |
1311 | { | |
1312 | int base_regnum = -1; | |
1313 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1314 | ||
1315 | /* general register N maps to general register N */ | |
1316 | if (reg_nr >= tdep->R0_C_REGNUM | |
1317 | && reg_nr <= tdep->R_LAST_C_REGNUM) | |
1318 | base_regnum = reg_nr - tdep->R0_C_REGNUM; | |
1319 | ||
1320 | /* floating point register N maps to floating point register N */ | |
1321 | else if (reg_nr >= tdep->FP0_C_REGNUM | |
1322 | && reg_nr <= tdep->FP_LAST_C_REGNUM) | |
1323 | base_regnum = reg_nr - tdep->FP0_C_REGNUM + FP0_REGNUM; | |
1324 | ||
1325 | /* double prec register N maps to base regnum for double prec register N */ | |
1326 | else if (reg_nr >= tdep->DR0_C_REGNUM | |
1327 | && reg_nr <= tdep->DR_LAST_C_REGNUM) | |
1328 | base_regnum = dr_reg_base_num (tdep->DR0_REGNUM | |
1329 | + reg_nr - tdep->DR0_C_REGNUM); | |
1330 | ||
1331 | /* vector N maps to base regnum for vector register N */ | |
1332 | else if (reg_nr >= tdep->FV0_C_REGNUM | |
1333 | && reg_nr <= tdep->FV_LAST_C_REGNUM) | |
1334 | base_regnum = fv_reg_base_num (tdep->FV0_REGNUM | |
1335 | + reg_nr - tdep->FV0_C_REGNUM); | |
1336 | ||
1337 | else if (reg_nr == tdep->PC_C_REGNUM) | |
1338 | base_regnum = PC_REGNUM; | |
1339 | ||
1340 | else if (reg_nr == tdep->GBR_C_REGNUM) | |
1341 | base_regnum = 16; | |
1342 | ||
1343 | else if (reg_nr == tdep->MACH_C_REGNUM | |
1344 | || reg_nr == tdep->MACL_C_REGNUM) | |
1345 | base_regnum = 17; | |
1346 | ||
1347 | else if (reg_nr == tdep->PR_C_REGNUM) | |
1348 | base_regnum = 18; | |
1349 | ||
1350 | else if (reg_nr == tdep->T_C_REGNUM) | |
1351 | base_regnum = 19; | |
1352 | ||
1353 | else if (reg_nr == tdep->FPSCR_C_REGNUM) | |
1354 | base_regnum = tdep->FPSCR_REGNUM; /*???? this register is a mess. */ | |
1355 | ||
1356 | else if (reg_nr == tdep->FPUL_C_REGNUM) | |
1357 | base_regnum = FP0_REGNUM + 32; | |
1358 | ||
1359 | return base_regnum; | |
1360 | } | |
1361 | ||
1362 | /* Given a register number RN (according to the gdb scheme) , return | |
1363 | its corresponding architectural register. In media mode, only a | |
1364 | subset of the registers is pseudo registers. For compact mode, all | |
1365 | the registers are pseudo. */ | |
1366 | static int | |
1367 | translate_rn_to_arch_reg_num (int rn, int media_mode) | |
1368 | { | |
1369 | ||
1370 | if (media_mode) | |
1371 | { | |
1372 | if (!is_media_pseudo (rn)) | |
1373 | return rn; | |
1374 | else | |
1375 | return sh64_media_reg_base_num (rn); | |
1376 | } | |
1377 | else | |
1378 | /* All compact registers are pseudo. */ | |
1379 | return sh64_compact_reg_base_num (rn); | |
1380 | } | |
1381 | ||
1382 | static int | |
1383 | sign_extend (int value, int bits) | |
1384 | { | |
1385 | value = value & ((1 << bits) - 1); | |
1386 | return (value & (1 << (bits - 1)) | |
1387 | ? value | (~((1 << bits) - 1)) | |
1388 | : value); | |
1389 | } | |
1390 | ||
cc17453a | 1391 | static void |
283150cd | 1392 | sh64_nofp_frame_init_saved_regs (struct frame_info *fi) |
cc17453a | 1393 | { |
ddde02bd | 1394 | int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int)); |
cc17453a EZ |
1395 | int rn; |
1396 | int have_fp = 0; | |
283150cd EZ |
1397 | int fp_regnum; |
1398 | int sp_regnum; | |
1399 | int depth; | |
1400 | int pc; | |
1401 | int opc; | |
1402 | int insn; | |
1403 | int r0_val = 0; | |
1404 | int media_mode = 0; | |
1405 | int insn_size; | |
1406 | int gdb_register_number; | |
1407 | int register_number; | |
1e2330ba | 1408 | char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), get_frame_base (fi)); |
283150cd EZ |
1409 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
1410 | ||
b2fb4676 | 1411 | if (get_frame_saved_regs (fi) == NULL) |
283150cd EZ |
1412 | frame_saved_regs_zalloc (fi); |
1413 | else | |
b2fb4676 | 1414 | memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS); |
283150cd EZ |
1415 | |
1416 | if (dummy_regs) | |
1417 | { | |
1418 | /* DANGER! This is ONLY going to work if the char buffer format of | |
1419 | the saved registers is byte-for-byte identical to the | |
1420 | CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */ | |
7b5849cc | 1421 | memcpy (get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS); |
283150cd EZ |
1422 | return; |
1423 | } | |
1424 | ||
da50a4b7 AC |
1425 | get_frame_extra_info (fi)->leaf_function = 1; |
1426 | get_frame_extra_info (fi)->f_offset = 0; | |
283150cd EZ |
1427 | |
1428 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) | |
1429 | where[rn] = -1; | |
1430 | ||
1431 | depth = 0; | |
1432 | ||
1433 | /* Loop around examining the prologue insns until we find something | |
1434 | that does not appear to be part of the prologue. But give up | |
1435 | after 20 of them, since we're getting silly then. */ | |
1436 | ||
50abf9e5 | 1437 | pc = get_pc_function_start (get_frame_pc (fi)); |
283150cd EZ |
1438 | if (!pc) |
1439 | { | |
50abf9e5 | 1440 | deprecated_update_frame_pc_hack (fi, 0); |
283150cd EZ |
1441 | return; |
1442 | } | |
1443 | ||
1444 | if (pc_is_isa32 (pc)) | |
1445 | { | |
1446 | media_mode = 1; | |
1447 | insn_size = 4; | |
1448 | } | |
1449 | else | |
1450 | { | |
1451 | media_mode = 0; | |
1452 | insn_size = 2; | |
1453 | } | |
1454 | ||
1455 | /* The frame pointer register is general register 14 in shmedia and | |
1456 | shcompact modes. In sh compact it is a pseudo register. Same goes | |
1457 | for the stack pointer register, which is register 15. */ | |
1458 | fp_regnum = translate_insn_rn (FP_REGNUM, media_mode); | |
1459 | sp_regnum = translate_insn_rn (SP_REGNUM, media_mode); | |
1460 | ||
1461 | for (opc = pc + (insn_size * 28); pc < opc; pc += insn_size) | |
1462 | { | |
1463 | insn = read_memory_integer (media_mode ? UNMAKE_ISA32_ADDR (pc) : pc, | |
1464 | insn_size); | |
1465 | ||
1466 | if (media_mode == 0) | |
1467 | { | |
1468 | if (IS_STS_PR (insn)) | |
1469 | { | |
1470 | int next_insn = read_memory_integer (pc + insn_size, insn_size); | |
1471 | if (IS_MOV_TO_R15 (next_insn)) | |
1472 | { | |
1473 | int reg_nr = tdep->PR_C_REGNUM; | |
1474 | ||
1475 | where[reg_nr] = depth - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2); | |
da50a4b7 | 1476 | get_frame_extra_info (fi)->leaf_function = 0; |
283150cd EZ |
1477 | pc += insn_size; |
1478 | } | |
1479 | } | |
1480 | else if (IS_MOV_R14 (insn)) | |
1481 | { | |
1482 | where[fp_regnum] = depth - ((((insn & 0xf) ^ 0x8) - 0x8) << 2); | |
1483 | } | |
1484 | ||
1485 | else if (IS_MOV_R0 (insn)) | |
1486 | { | |
1487 | /* Put in R0 the offset from SP at which to store some | |
1488 | registers. We are interested in this value, because it | |
1489 | will tell us where the given registers are stored within | |
1490 | the frame. */ | |
1491 | r0_val = ((insn & 0xff) ^ 0x80) - 0x80; | |
1492 | } | |
1493 | else if (IS_ADD_SP_R0 (insn)) | |
1494 | { | |
1495 | /* This instruction still prepares r0, but we don't care. | |
1496 | We already have the offset in r0_val. */ | |
1497 | } | |
1498 | else if (IS_STS_R0 (insn)) | |
1499 | { | |
1500 | /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/ | |
1501 | int reg_nr = tdep->PR_C_REGNUM; | |
1502 | where[reg_nr] = depth - (r0_val - 4); | |
1503 | r0_val -= 4; | |
da50a4b7 | 1504 | get_frame_extra_info (fi)->leaf_function = 0; |
283150cd EZ |
1505 | } |
1506 | else if (IS_MOV_R14_R0 (insn)) | |
1507 | { | |
1508 | /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */ | |
1509 | where[fp_regnum] = depth - (r0_val - 4); | |
1510 | r0_val -= 4; | |
1511 | } | |
1512 | ||
1513 | else if (IS_ADD_SP (insn)) | |
1514 | { | |
1515 | depth -= ((insn & 0xff) ^ 0x80) - 0x80; | |
1516 | } | |
1517 | else if (IS_MOV_SP_FP (insn)) | |
1518 | break; | |
1519 | } | |
1520 | else | |
1521 | { | |
1522 | if (IS_ADDIL_SP_MEDIA (insn) | |
1523 | || IS_ADDI_SP_MEDIA (insn)) | |
1524 | { | |
1525 | depth -= sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9); | |
1526 | } | |
1527 | ||
1528 | else if (IS_STQ_R18_R15 (insn)) | |
1529 | { | |
1530 | where[tdep->PR_REGNUM] = | |
1531 | depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3); | |
da50a4b7 | 1532 | get_frame_extra_info (fi)->leaf_function = 0; |
283150cd EZ |
1533 | } |
1534 | ||
1535 | else if (IS_STL_R18_R15 (insn)) | |
1536 | { | |
1537 | where[tdep->PR_REGNUM] = | |
1538 | depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2); | |
da50a4b7 | 1539 | get_frame_extra_info (fi)->leaf_function = 0; |
283150cd EZ |
1540 | } |
1541 | ||
1542 | else if (IS_STQ_R14_R15 (insn)) | |
1543 | { | |
1544 | where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3); | |
1545 | } | |
1546 | ||
1547 | else if (IS_STL_R14_R15 (insn)) | |
1548 | { | |
1549 | where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2); | |
1550 | } | |
1551 | ||
1552 | else if (IS_MOV_SP_FP_MEDIA (insn)) | |
1553 | break; | |
1554 | } | |
1555 | } | |
1556 | ||
1557 | /* Now we know how deep things are, we can work out their addresses. */ | |
1558 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) | |
1559 | { | |
1560 | register_number = translate_rn_to_arch_reg_num (rn, media_mode); | |
1561 | ||
1562 | if (where[rn] >= 0) | |
1563 | { | |
1564 | if (rn == fp_regnum) | |
1565 | have_fp = 1; | |
1566 | ||
1567 | /* Watch out! saved_regs is only for the real registers, and | |
1568 | doesn't include space for the pseudo registers. */ | |
1e2330ba | 1569 | get_frame_saved_regs (fi)[register_number]= get_frame_base (fi) - where[rn] + depth; |
283150cd EZ |
1570 | |
1571 | } | |
1572 | else | |
b2fb4676 | 1573 | get_frame_saved_regs (fi)[register_number] = 0; |
283150cd EZ |
1574 | } |
1575 | ||
1576 | if (have_fp) | |
1577 | { | |
1578 | /* SP_REGNUM is 15. For shmedia 15 is the real register. For | |
1579 | shcompact 15 is the arch register corresponding to the pseudo | |
1580 | register r15 which still is the SP register. */ | |
1581 | /* The place on the stack where fp is stored contains the sp of | |
1582 | the caller. */ | |
1583 | /* Again, saved_registers contains only space for the real registers, | |
1584 | so we store in FP_REGNUM position. */ | |
1585 | int size; | |
1586 | if (tdep->sh_abi == SH_ABI_32) | |
1587 | size = 4; | |
1588 | else | |
1589 | size = REGISTER_RAW_SIZE (fp_regnum); | |
b2fb4676 | 1590 | get_frame_saved_regs (fi)[sp_regnum] = read_memory_integer (get_frame_saved_regs (fi)[fp_regnum], size); |
283150cd EZ |
1591 | } |
1592 | else | |
1e2330ba | 1593 | get_frame_saved_regs (fi)[sp_regnum] = get_frame_base (fi); |
283150cd | 1594 | |
da50a4b7 | 1595 | get_frame_extra_info (fi)->f_offset = depth - where[fp_regnum]; |
283150cd EZ |
1596 | } |
1597 | ||
1598 | static void | |
1599 | sh_fp_frame_init_saved_regs (struct frame_info *fi) | |
1600 | { | |
ddde02bd | 1601 | int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int)); |
283150cd EZ |
1602 | int rn; |
1603 | int have_fp = 0; | |
cc17453a EZ |
1604 | int depth; |
1605 | int pc; | |
1606 | int opc; | |
1607 | int insn; | |
1608 | int r3_val = 0; | |
1e2330ba | 1609 | char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), get_frame_base (fi)); |
f81353e4 | 1610 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
cc17453a | 1611 | |
b2fb4676 | 1612 | if (get_frame_saved_regs (fi) == NULL) |
cc17453a EZ |
1613 | frame_saved_regs_zalloc (fi); |
1614 | else | |
b2fb4676 | 1615 | memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS); |
cc17453a | 1616 | |
c906108c SS |
1617 | if (dummy_regs) |
1618 | { | |
1619 | /* DANGER! This is ONLY going to work if the char buffer format of | |
c5aa993b JM |
1620 | the saved registers is byte-for-byte identical to the |
1621 | CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */ | |
7b5849cc | 1622 | memcpy (get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
1623 | return; |
1624 | } | |
1625 | ||
da50a4b7 AC |
1626 | get_frame_extra_info (fi)->leaf_function = 1; |
1627 | get_frame_extra_info (fi)->f_offset = 0; | |
c906108c | 1628 | |
cd4bffcf | 1629 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) |
c906108c SS |
1630 | where[rn] = -1; |
1631 | ||
1632 | depth = 0; | |
1633 | ||
1634 | /* Loop around examining the prologue insns until we find something | |
1635 | that does not appear to be part of the prologue. But give up | |
1636 | after 20 of them, since we're getting silly then. */ | |
1637 | ||
50abf9e5 | 1638 | pc = get_pc_function_start (get_frame_pc (fi)); |
2bfa91ee | 1639 | if (!pc) |
c906108c | 1640 | { |
50abf9e5 | 1641 | deprecated_update_frame_pc_hack (fi, 0); |
2bfa91ee EZ |
1642 | return; |
1643 | } | |
1644 | ||
1645 | for (opc = pc + (2 * 28); pc < opc; pc += 2) | |
1646 | { | |
1647 | insn = read_memory_integer (pc, 2); | |
c906108c SS |
1648 | /* See where the registers will be saved to */ |
1649 | if (IS_PUSH (insn)) | |
1650 | { | |
c906108c SS |
1651 | rn = GET_PUSHED_REG (insn); |
1652 | where[rn] = depth; | |
c906108c SS |
1653 | depth += 4; |
1654 | } | |
1655 | else if (IS_STS (insn)) | |
1656 | { | |
f81353e4 | 1657 | where[tdep->PR_REGNUM] = depth; |
c906108c | 1658 | /* If we're storing the pr then this isn't a leaf */ |
da50a4b7 | 1659 | get_frame_extra_info (fi)->leaf_function = 0; |
c906108c SS |
1660 | depth += 4; |
1661 | } | |
1662 | else if (IS_MOV_R3 (insn)) | |
1663 | { | |
1664 | r3_val = ((insn & 0xff) ^ 0x80) - 0x80; | |
c906108c SS |
1665 | } |
1666 | else if (IS_SHLL_R3 (insn)) | |
1667 | { | |
1668 | r3_val <<= 1; | |
c906108c SS |
1669 | } |
1670 | else if (IS_ADD_R3SP (insn)) | |
1671 | { | |
1672 | depth += -r3_val; | |
c906108c SS |
1673 | } |
1674 | else if (IS_ADD_SP (insn)) | |
1675 | { | |
c906108c | 1676 | depth -= ((insn & 0xff) ^ 0x80) - 0x80; |
c906108c SS |
1677 | } |
1678 | else if (IS_FMOV (insn)) | |
1679 | { | |
f81353e4 | 1680 | if (read_register (tdep->FPSCR_REGNUM) & FPSCR_SZ) |
c906108c SS |
1681 | { |
1682 | depth += 8; | |
1683 | } | |
1684 | else | |
1685 | { | |
1686 | depth += 4; | |
1687 | } | |
1688 | } | |
2bfa91ee EZ |
1689 | else if (IS_MOV_SP_FP (insn)) |
1690 | break; | |
1691 | #if 0 /* This used to just stop when it found an instruction that | |
1692 | was not considered part of the prologue. Now, we just | |
1693 | keep going looking for likely instructions. */ | |
c906108c SS |
1694 | else |
1695 | break; | |
2bfa91ee | 1696 | #endif |
c906108c SS |
1697 | } |
1698 | ||
1699 | /* Now we know how deep things are, we can work out their addresses */ | |
1700 | ||
cd4bffcf | 1701 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) |
c906108c SS |
1702 | { |
1703 | if (where[rn] >= 0) | |
1704 | { | |
1705 | if (rn == FP_REGNUM) | |
1706 | have_fp = 1; | |
1707 | ||
1e2330ba | 1708 | get_frame_saved_regs (fi)[rn] = get_frame_base (fi) - where[rn] + depth - 4; |
c906108c SS |
1709 | } |
1710 | else | |
1711 | { | |
b2fb4676 | 1712 | get_frame_saved_regs (fi)[rn] = 0; |
c906108c SS |
1713 | } |
1714 | } | |
1715 | ||
1716 | if (have_fp) | |
1717 | { | |
b2fb4676 AC |
1718 | get_frame_saved_regs (fi)[SP_REGNUM] = |
1719 | read_memory_integer (get_frame_saved_regs (fi)[FP_REGNUM], 4); | |
c906108c SS |
1720 | } |
1721 | else | |
1722 | { | |
1e2330ba | 1723 | get_frame_saved_regs (fi)[SP_REGNUM] = get_frame_base (fi) - 4; |
c906108c SS |
1724 | } |
1725 | ||
da50a4b7 | 1726 | get_frame_extra_info (fi)->f_offset = depth - where[FP_REGNUM] - 4; |
c906108c SS |
1727 | /* Work out the return pc - either from the saved pr or the pr |
1728 | value */ | |
1729 | } | |
1730 | ||
cc17453a EZ |
1731 | /* Initialize the extra info saved in a FRAME */ |
1732 | static void | |
fba45db2 | 1733 | sh_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c | 1734 | { |
cc17453a | 1735 | |
a00a19e9 | 1736 | frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info)); |
c906108c | 1737 | |
11c02a10 AC |
1738 | if (get_next_frame (fi)) |
1739 | deprecated_update_frame_pc_hack (fi, FRAME_SAVED_PC (get_next_frame (fi))); | |
c906108c | 1740 | |
1e2330ba AC |
1741 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi), |
1742 | get_frame_base (fi))) | |
c906108c SS |
1743 | { |
1744 | /* We need to setup fi->frame here because run_stack_dummy gets it wrong | |
c5aa993b | 1745 | by assuming it's always FP. */ |
1e2330ba | 1746 | deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), get_frame_base (fi), |
8ccd593b | 1747 | SP_REGNUM)); |
da50a4b7 | 1748 | get_frame_extra_info (fi)->return_pc = deprecated_read_register_dummy (get_frame_pc (fi), |
1e2330ba | 1749 | get_frame_base (fi), |
135c175f | 1750 | PC_REGNUM); |
da50a4b7 AC |
1751 | get_frame_extra_info (fi)->f_offset = -(CALL_DUMMY_LENGTH + 4); |
1752 | get_frame_extra_info (fi)->leaf_function = 0; | |
c906108c SS |
1753 | return; |
1754 | } | |
1755 | else | |
1756 | { | |
cc17453a | 1757 | FRAME_INIT_SAVED_REGS (fi); |
da50a4b7 | 1758 | get_frame_extra_info (fi)->return_pc = |
cd4bffcf | 1759 | sh_find_callers_reg (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM); |
c906108c SS |
1760 | } |
1761 | } | |
1762 | ||
283150cd EZ |
1763 | static void |
1764 | sh64_init_extra_frame_info (int fromleaf, struct frame_info *fi) | |
1765 | { | |
50abf9e5 | 1766 | int media_mode = pc_is_isa32 (get_frame_pc (fi)); |
283150cd | 1767 | |
a00a19e9 | 1768 | frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info)); |
283150cd | 1769 | |
11c02a10 AC |
1770 | if (get_next_frame (fi)) |
1771 | deprecated_update_frame_pc_hack (fi, FRAME_SAVED_PC (get_next_frame (fi))); | |
283150cd | 1772 | |
1e2330ba AC |
1773 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi), |
1774 | get_frame_base (fi))) | |
283150cd EZ |
1775 | { |
1776 | /* We need to setup fi->frame here because run_stack_dummy gets it wrong | |
1777 | by assuming it's always FP. */ | |
1e2330ba | 1778 | deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), get_frame_base (fi), SP_REGNUM)); |
da50a4b7 | 1779 | get_frame_extra_info (fi)->return_pc = |
1e2330ba AC |
1780 | deprecated_read_register_dummy (get_frame_pc (fi), |
1781 | get_frame_base (fi), PC_REGNUM); | |
da50a4b7 AC |
1782 | get_frame_extra_info (fi)->f_offset = -(CALL_DUMMY_LENGTH + 4); |
1783 | get_frame_extra_info (fi)->leaf_function = 0; | |
283150cd EZ |
1784 | return; |
1785 | } | |
1786 | else | |
1787 | { | |
1788 | FRAME_INIT_SAVED_REGS (fi); | |
da50a4b7 | 1789 | get_frame_extra_info (fi)->return_pc = |
283150cd EZ |
1790 | sh64_get_saved_pr (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM); |
1791 | } | |
1792 | } | |
1793 | ||
1794 | void | |
1795 | sh64_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp, | |
1796 | struct frame_info *frame, int regnum, | |
1797 | enum lval_type *lval) | |
1798 | { | |
1799 | int media_mode; | |
1800 | int live_regnum = regnum; | |
1801 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1802 | ||
1803 | if (!target_has_registers) | |
1804 | error ("No registers."); | |
1805 | ||
1806 | /* Normal systems don't optimize out things with register numbers. */ | |
1807 | if (optimized != NULL) | |
1808 | *optimized = 0; | |
1809 | ||
1810 | if (addrp) /* default assumption: not found in memory */ | |
1811 | *addrp = 0; | |
1812 | ||
1813 | if (raw_buffer) | |
1814 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
1815 | ||
1816 | /* We must do this here, before the following while loop changes | |
1817 | frame, and makes it NULL. If this is a media register number, | |
1818 | but we are in compact mode, it will become the corresponding | |
1819 | compact pseudo register. If there is no corresponding compact | |
1820 | pseudo-register what do we do?*/ | |
50abf9e5 | 1821 | media_mode = pc_is_isa32 (get_frame_pc (frame)); |
283150cd EZ |
1822 | live_regnum = translate_insn_rn (regnum, media_mode); |
1823 | ||
1824 | /* Note: since the current frame's registers could only have been | |
1825 | saved by frames INTERIOR TO the current frame, we skip examining | |
1826 | the current frame itself: otherwise, we would be getting the | |
1827 | previous frame's registers which were saved by the current frame. */ | |
1828 | ||
11c02a10 | 1829 | while (frame && ((frame = get_next_frame (frame)) != NULL)) |
283150cd | 1830 | { |
1e2330ba AC |
1831 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), |
1832 | get_frame_base (frame), | |
1833 | get_frame_base (frame))) | |
283150cd EZ |
1834 | { |
1835 | if (lval) /* found it in a CALL_DUMMY frame */ | |
1836 | *lval = not_lval; | |
1837 | if (raw_buffer) | |
1838 | memcpy (raw_buffer, | |
1e2330ba | 1839 | (deprecated_generic_find_dummy_frame (get_frame_pc (frame), get_frame_base (frame)) |
da130f98 | 1840 | + REGISTER_BYTE (regnum)), |
283150cd EZ |
1841 | REGISTER_RAW_SIZE (regnum)); |
1842 | return; | |
1843 | } | |
1844 | ||
1845 | FRAME_INIT_SAVED_REGS (frame); | |
b2fb4676 AC |
1846 | if (get_frame_saved_regs (frame) != NULL |
1847 | && get_frame_saved_regs (frame)[regnum] != 0) | |
283150cd EZ |
1848 | { |
1849 | if (lval) /* found it saved on the stack */ | |
1850 | *lval = lval_memory; | |
1851 | if (regnum == SP_REGNUM) | |
1852 | { | |
1853 | if (raw_buffer) /* SP register treated specially */ | |
1854 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), | |
b2fb4676 | 1855 | get_frame_saved_regs (frame)[regnum]); |
283150cd EZ |
1856 | } |
1857 | else | |
1858 | { /* any other register */ | |
1859 | ||
1860 | if (addrp) | |
b2fb4676 | 1861 | *addrp = get_frame_saved_regs (frame)[regnum]; |
283150cd EZ |
1862 | if (raw_buffer) |
1863 | { | |
1864 | int size; | |
1865 | if (tdep->sh_abi == SH_ABI_32 | |
1866 | && (live_regnum == FP_REGNUM | |
1867 | || live_regnum == tdep->PR_REGNUM)) | |
1868 | size = 4; | |
1869 | else | |
1870 | size = REGISTER_RAW_SIZE (live_regnum); | |
1871 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
b2fb4676 | 1872 | read_memory (get_frame_saved_regs (frame)[regnum], raw_buffer, size); |
283150cd | 1873 | else |
b2fb4676 | 1874 | read_memory (get_frame_saved_regs (frame)[regnum], |
283150cd EZ |
1875 | raw_buffer |
1876 | + REGISTER_RAW_SIZE (live_regnum) | |
1877 | - size, | |
1878 | size); | |
1879 | } | |
1880 | } | |
1881 | return; | |
1882 | } | |
1883 | } | |
1884 | ||
1885 | /* If we get thru the loop to this point, it means the register was | |
1886 | not saved in any frame. Return the actual live-register value. */ | |
1887 | ||
1888 | if (lval) /* found it in a live register */ | |
1889 | *lval = lval_register; | |
1890 | if (addrp) | |
1891 | *addrp = REGISTER_BYTE (live_regnum); | |
1892 | if (raw_buffer) | |
4caf0990 | 1893 | deprecated_read_register_gen (live_regnum, raw_buffer); |
283150cd EZ |
1894 | } |
1895 | ||
cc17453a EZ |
1896 | /* Extract from an array REGBUF containing the (raw) register state |
1897 | the address in which a function should return its structure value, | |
1898 | as a CORE_ADDR (or an expression that can be used as one). */ | |
b3df3fff | 1899 | static CORE_ADDR |
0c8053b6 | 1900 | sh_extract_struct_value_address (char *regbuf) |
cc17453a EZ |
1901 | { |
1902 | return (extract_address ((regbuf), REGISTER_RAW_SIZE (0))); | |
1903 | } | |
1904 | ||
283150cd EZ |
1905 | static CORE_ADDR |
1906 | sh64_extract_struct_value_address (char *regbuf) | |
1907 | { | |
1908 | return (extract_address ((regbuf + REGISTER_BYTE (STRUCT_RETURN_REGNUM)), | |
1909 | REGISTER_RAW_SIZE (STRUCT_RETURN_REGNUM))); | |
1910 | } | |
1911 | ||
cc17453a | 1912 | static CORE_ADDR |
fba45db2 | 1913 | sh_frame_saved_pc (struct frame_info *frame) |
cc17453a | 1914 | { |
da50a4b7 | 1915 | return (get_frame_extra_info (frame)->return_pc); |
cc17453a EZ |
1916 | } |
1917 | ||
c906108c SS |
1918 | /* Discard from the stack the innermost frame, |
1919 | restoring all saved registers. */ | |
cc17453a | 1920 | static void |
fba45db2 | 1921 | sh_pop_frame (void) |
c906108c SS |
1922 | { |
1923 | register struct frame_info *frame = get_current_frame (); | |
1924 | register CORE_ADDR fp; | |
1925 | register int regnum; | |
c906108c | 1926 | |
1e2330ba AC |
1927 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), |
1928 | get_frame_base (frame), | |
1929 | get_frame_base (frame))) | |
c906108c SS |
1930 | generic_pop_dummy_frame (); |
1931 | else | |
c5aa993b | 1932 | { |
c193f6ac | 1933 | fp = get_frame_base (frame); |
cc17453a | 1934 | FRAME_INIT_SAVED_REGS (frame); |
c906108c | 1935 | |
c5aa993b | 1936 | /* Copy regs from where they were saved in the frame */ |
cd4bffcf | 1937 | for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
b2fb4676 | 1938 | if (get_frame_saved_regs (frame)[regnum]) |
cd4bffcf | 1939 | write_register (regnum, |
b2fb4676 | 1940 | read_memory_integer (get_frame_saved_regs (frame)[regnum], 4)); |
c906108c | 1941 | |
da50a4b7 | 1942 | write_register (PC_REGNUM, get_frame_extra_info (frame)->return_pc); |
c5aa993b JM |
1943 | write_register (SP_REGNUM, fp + 4); |
1944 | } | |
c906108c SS |
1945 | flush_cached_frames (); |
1946 | } | |
1947 | ||
283150cd EZ |
1948 | /* Used in the 'return' command. */ |
1949 | static void | |
1950 | sh64_pop_frame (void) | |
1951 | { | |
1952 | register struct frame_info *frame = get_current_frame (); | |
1953 | register CORE_ADDR fp; | |
1954 | register int regnum; | |
1955 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1956 | ||
50abf9e5 | 1957 | int media_mode = pc_is_isa32 (get_frame_pc (frame)); |
283150cd | 1958 | |
1e2330ba AC |
1959 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), |
1960 | get_frame_base (frame), | |
1961 | get_frame_base (frame))) | |
283150cd EZ |
1962 | generic_pop_dummy_frame (); |
1963 | else | |
1964 | { | |
c193f6ac | 1965 | fp = get_frame_base (frame); |
283150cd EZ |
1966 | FRAME_INIT_SAVED_REGS (frame); |
1967 | ||
1968 | /* Copy regs from where they were saved in the frame */ | |
1969 | for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) | |
b2fb4676 | 1970 | if (get_frame_saved_regs (frame)[regnum]) |
283150cd EZ |
1971 | { |
1972 | int size; | |
1973 | if (tdep->sh_abi == SH_ABI_32 | |
1974 | && (regnum == FP_REGNUM | |
1975 | || regnum == tdep->PR_REGNUM)) | |
1976 | size = 4; | |
1977 | else | |
1978 | size = REGISTER_RAW_SIZE (translate_insn_rn (regnum, | |
1979 | media_mode)); | |
1980 | write_register (regnum, | |
b2fb4676 | 1981 | read_memory_integer (get_frame_saved_regs (frame)[regnum], |
283150cd EZ |
1982 | size)); |
1983 | } | |
1984 | ||
da50a4b7 | 1985 | write_register (PC_REGNUM, get_frame_extra_info (frame)->return_pc); |
283150cd EZ |
1986 | write_register (SP_REGNUM, fp + 8); |
1987 | } | |
1988 | flush_cached_frames (); | |
1989 | } | |
1990 | ||
c906108c SS |
1991 | /* Function: push_arguments |
1992 | Setup the function arguments for calling a function in the inferior. | |
1993 | ||
1994 | On the Hitachi SH architecture, there are four registers (R4 to R7) | |
1995 | which are dedicated for passing function arguments. Up to the first | |
1996 | four arguments (depending on size) may go into these registers. | |
1997 | The rest go on the stack. | |
1998 | ||
1999 | Arguments that are smaller than 4 bytes will still take up a whole | |
2000 | register or a whole 32-bit word on the stack, and will be | |
2001 | right-justified in the register or the stack word. This includes | |
2002 | chars, shorts, and small aggregate types. | |
2003 | ||
2004 | Arguments that are larger than 4 bytes may be split between two or | |
2005 | more registers. If there are not enough registers free, an argument | |
2006 | may be passed partly in a register (or registers), and partly on the | |
2007 | stack. This includes doubles, long longs, and larger aggregates. | |
2008 | As far as I know, there is no upper limit to the size of aggregates | |
2009 | that will be passed in this way; in other words, the convention of | |
2010 | passing a pointer to a large aggregate instead of a copy is not used. | |
2011 | ||
2012 | An exceptional case exists for struct arguments (and possibly other | |
2013 | aggregates such as arrays) if the size is larger than 4 bytes but | |
2014 | not a multiple of 4 bytes. In this case the argument is never split | |
2015 | between the registers and the stack, but instead is copied in its | |
2016 | entirety onto the stack, AND also copied into as many registers as | |
2017 | there is room for. In other words, space in registers permitting, | |
2018 | two copies of the same argument are passed in. As far as I can tell, | |
2019 | only the one on the stack is used, although that may be a function | |
2020 | of the level of compiler optimization. I suspect this is a compiler | |
2021 | bug. Arguments of these odd sizes are left-justified within the | |
2022 | word (as opposed to arguments smaller than 4 bytes, which are | |
2023 | right-justified). | |
c5aa993b | 2024 | |
c906108c SS |
2025 | If the function is to return an aggregate type such as a struct, it |
2026 | is either returned in the normal return value register R0 (if its | |
2027 | size is no greater than one byte), or else the caller must allocate | |
2028 | space into which the callee will copy the return value (if the size | |
2029 | is greater than one byte). In this case, a pointer to the return | |
2030 | value location is passed into the callee in register R2, which does | |
2031 | not displace any of the other arguments passed in via registers R4 | |
2032 | to R7. */ | |
2033 | ||
cc17453a | 2034 | static CORE_ADDR |
34e9d9bb | 2035 | sh_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
3bbfbb92 | 2036 | int struct_return, CORE_ADDR struct_addr) |
c906108c SS |
2037 | { |
2038 | int stack_offset, stack_alloc; | |
2039 | int argreg; | |
2040 | int argnum; | |
2041 | struct type *type; | |
2042 | CORE_ADDR regval; | |
2043 | char *val; | |
2044 | char valbuf[4]; | |
2045 | int len; | |
2046 | int odd_sized_struct; | |
f81353e4 | 2047 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
2048 | |
2049 | /* first force sp to a 4-byte alignment */ | |
2050 | sp = sp & ~3; | |
2051 | ||
2052 | /* The "struct return pointer" pseudo-argument has its own dedicated | |
2053 | register */ | |
2054 | if (struct_return) | |
c5aa993b | 2055 | write_register (STRUCT_RETURN_REGNUM, struct_addr); |
c906108c SS |
2056 | |
2057 | /* Now make sure there's space on the stack */ | |
cc17453a | 2058 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) |
c5aa993b JM |
2059 | stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3); |
2060 | sp -= stack_alloc; /* make room on stack for args */ | |
c906108c | 2061 | |
c906108c SS |
2062 | /* Now load as many as possible of the first arguments into |
2063 | registers, and push the rest onto the stack. There are 16 bytes | |
2064 | in four registers available. Loop thru args from first to last. */ | |
2065 | ||
f81353e4 | 2066 | argreg = tdep->ARG0_REGNUM; |
c906108c SS |
2067 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) |
2068 | { | |
2069 | type = VALUE_TYPE (args[argnum]); | |
c5aa993b JM |
2070 | len = TYPE_LENGTH (type); |
2071 | memset (valbuf, 0, sizeof (valbuf)); | |
c906108c | 2072 | if (len < 4) |
cc17453a EZ |
2073 | { |
2074 | /* value gets right-justified in the register or stack word */ | |
7079c36c CV |
2075 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
2076 | memcpy (valbuf + (4 - len), | |
2077 | (char *) VALUE_CONTENTS (args[argnum]), len); | |
2078 | else | |
2079 | memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len); | |
c5aa993b JM |
2080 | val = valbuf; |
2081 | } | |
c906108c | 2082 | else |
c5aa993b | 2083 | val = (char *) VALUE_CONTENTS (args[argnum]); |
c906108c SS |
2084 | |
2085 | if (len > 4 && (len & 3) != 0) | |
c5aa993b JM |
2086 | odd_sized_struct = 1; /* such structs go entirely on stack */ |
2087 | else | |
c906108c SS |
2088 | odd_sized_struct = 0; |
2089 | while (len > 0) | |
2090 | { | |
f81353e4 | 2091 | if (argreg > tdep->ARGLAST_REGNUM |
3bbfbb92 EZ |
2092 | || odd_sized_struct) |
2093 | { | |
2094 | /* must go on the stack */ | |
c906108c SS |
2095 | write_memory (sp + stack_offset, val, 4); |
2096 | stack_offset += 4; | |
2097 | } | |
2098 | /* NOTE WELL!!!!! This is not an "else if" clause!!! | |
2099 | That's because some *&^%$ things get passed on the stack | |
2100 | AND in the registers! */ | |
f81353e4 | 2101 | if (argreg <= tdep->ARGLAST_REGNUM) |
3bbfbb92 EZ |
2102 | { |
2103 | /* there's room in a register */ | |
c5aa993b | 2104 | regval = extract_address (val, REGISTER_RAW_SIZE (argreg)); |
c906108c SS |
2105 | write_register (argreg++, regval); |
2106 | } | |
2107 | /* Store the value 4 bytes at a time. This means that things | |
2108 | larger than 4 bytes may go partly in registers and partly | |
2109 | on the stack. */ | |
c5aa993b JM |
2110 | len -= REGISTER_RAW_SIZE (argreg); |
2111 | val += REGISTER_RAW_SIZE (argreg); | |
c906108c SS |
2112 | } |
2113 | } | |
2114 | return sp; | |
2115 | } | |
2116 | ||
283150cd EZ |
2117 | /* R2-R9 for integer types and integer equivalent (char, pointers) and |
2118 | non-scalar (struct, union) elements (even if the elements are | |
2119 | floats). | |
2120 | FR0-FR11 for single precision floating point (float) | |
2121 | DR0-DR10 for double precision floating point (double) | |
2122 | ||
2123 | If a float is argument number 3 (for instance) and arguments number | |
2124 | 1,2, and 4 are integer, the mapping will be: | |
2125 | arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used. | |
2126 | ||
2127 | If a float is argument number 10 (for instance) and arguments number | |
2128 | 1 through 10 are integer, the mapping will be: | |
2129 | arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8, | |
2130 | arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP). | |
2131 | I.e. there is hole in the stack. | |
2132 | ||
2133 | Different rules apply for variable arguments functions, and for functions | |
2134 | for which the prototype is not known. */ | |
2135 | ||
2136 | static CORE_ADDR | |
2137 | sh64_push_arguments (int nargs, struct value **args, CORE_ADDR sp, | |
2138 | int struct_return, CORE_ADDR struct_addr) | |
2139 | { | |
2140 | int stack_offset, stack_alloc; | |
2141 | int int_argreg; | |
2142 | int float_argreg; | |
2143 | int double_argreg; | |
2144 | int float_arg_index = 0; | |
2145 | int double_arg_index = 0; | |
2146 | int argnum; | |
2147 | struct type *type; | |
2148 | CORE_ADDR regval; | |
2149 | char *val; | |
2150 | char valbuf[8]; | |
2151 | char valbuf_tmp[8]; | |
2152 | int len; | |
2153 | int argreg_size; | |
2154 | int fp_args[12]; | |
2155 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2156 | ||
2157 | memset (fp_args, 0, sizeof (fp_args)); | |
2158 | ||
2159 | /* first force sp to a 8-byte alignment */ | |
2160 | sp = sp & ~7; | |
2161 | ||
2162 | /* The "struct return pointer" pseudo-argument has its own dedicated | |
2163 | register */ | |
2164 | ||
2165 | if (struct_return) | |
2166 | write_register (STRUCT_RETURN_REGNUM, struct_addr); | |
2167 | ||
2168 | /* Now make sure there's space on the stack */ | |
2169 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) | |
2170 | stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 7) & ~7); | |
2171 | sp -= stack_alloc; /* make room on stack for args */ | |
2172 | ||
2173 | /* Now load as many as possible of the first arguments into | |
2174 | registers, and push the rest onto the stack. There are 64 bytes | |
2175 | in eight registers available. Loop thru args from first to last. */ | |
2176 | ||
2177 | int_argreg = tdep->ARG0_REGNUM; | |
2178 | float_argreg = FP0_REGNUM; | |
2179 | double_argreg = tdep->DR0_REGNUM; | |
2180 | ||
2181 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
2182 | { | |
2183 | type = VALUE_TYPE (args[argnum]); | |
2184 | len = TYPE_LENGTH (type); | |
2185 | memset (valbuf, 0, sizeof (valbuf)); | |
2186 | ||
2187 | if (TYPE_CODE (type) != TYPE_CODE_FLT) | |
2188 | { | |
2189 | argreg_size = REGISTER_RAW_SIZE (int_argreg); | |
2190 | ||
2191 | if (len < argreg_size) | |
2192 | { | |
2193 | /* value gets right-justified in the register or stack word */ | |
2194 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2195 | memcpy (valbuf + argreg_size - len, | |
2196 | (char *) VALUE_CONTENTS (args[argnum]), len); | |
2197 | else | |
2198 | memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len); | |
2199 | ||
2200 | val = valbuf; | |
2201 | } | |
2202 | else | |
2203 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
2204 | ||
2205 | while (len > 0) | |
2206 | { | |
2207 | if (int_argreg > tdep->ARGLAST_REGNUM) | |
2208 | { | |
2209 | /* must go on the stack */ | |
2210 | write_memory (sp + stack_offset, val, argreg_size); | |
2211 | stack_offset += 8;/*argreg_size;*/ | |
2212 | } | |
2213 | /* NOTE WELL!!!!! This is not an "else if" clause!!! | |
2214 | That's because some *&^%$ things get passed on the stack | |
2215 | AND in the registers! */ | |
2216 | if (int_argreg <= tdep->ARGLAST_REGNUM) | |
2217 | { | |
2218 | /* there's room in a register */ | |
2219 | regval = extract_address (val, argreg_size); | |
2220 | write_register (int_argreg, regval); | |
2221 | } | |
2222 | /* Store the value 8 bytes at a time. This means that | |
2223 | things larger than 8 bytes may go partly in registers | |
2224 | and partly on the stack. FIXME: argreg is incremented | |
2225 | before we use its size. */ | |
2226 | len -= argreg_size; | |
2227 | val += argreg_size; | |
2228 | int_argreg++; | |
2229 | } | |
2230 | } | |
2231 | else | |
2232 | { | |
2233 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
2234 | if (len == 4) | |
2235 | { | |
2236 | /* Where is it going to be stored? */ | |
2237 | while (fp_args[float_arg_index]) | |
2238 | float_arg_index ++; | |
2239 | ||
2240 | /* Now float_argreg points to the register where it | |
2241 | should be stored. Are we still within the allowed | |
2242 | register set? */ | |
2243 | if (float_arg_index <= tdep->FLOAT_ARGLAST_REGNUM) | |
2244 | { | |
2245 | /* Goes in FR0...FR11 */ | |
4caf0990 AC |
2246 | deprecated_write_register_gen (FP0_REGNUM + float_arg_index, |
2247 | val); | |
283150cd EZ |
2248 | fp_args[float_arg_index] = 1; |
2249 | /* Skip the corresponding general argument register. */ | |
2250 | int_argreg ++; | |
2251 | } | |
2252 | else | |
2253 | ; | |
2254 | /* Store it as the integers, 8 bytes at the time, if | |
2255 | necessary spilling on the stack. */ | |
2256 | ||
2257 | } | |
2258 | else if (len == 8) | |
2259 | { | |
2260 | /* Where is it going to be stored? */ | |
2261 | while (fp_args[double_arg_index]) | |
2262 | double_arg_index += 2; | |
2263 | /* Now double_argreg points to the register | |
2264 | where it should be stored. | |
2265 | Are we still within the allowed register set? */ | |
2266 | if (double_arg_index < tdep->FLOAT_ARGLAST_REGNUM) | |
2267 | { | |
2268 | /* Goes in DR0...DR10 */ | |
2269 | /* The numbering of the DRi registers is consecutive, | |
2270 | i.e. includes odd numbers. */ | |
2271 | int double_register_offset = double_arg_index / 2; | |
2272 | int regnum = tdep->DR0_REGNUM + | |
2273 | double_register_offset; | |
2274 | #if 0 | |
2275 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
2276 | { | |
2277 | memset (valbuf_tmp, 0, sizeof (valbuf_tmp)); | |
2278 | REGISTER_CONVERT_TO_VIRTUAL (regnum, | |
2279 | type, val, valbuf_tmp); | |
2280 | val = valbuf_tmp; | |
2281 | } | |
2282 | #endif | |
2283 | /* Note: must use write_register_gen here instead | |
0818c12a AC |
2284 | of regcache_raw_write, because |
2285 | regcache_raw_write works only for real | |
2286 | registers, not pseudo. write_register_gen will | |
2287 | call the gdbarch function to do register | |
2288 | writes, and that will properly know how to deal | |
2289 | with pseudoregs. */ | |
4caf0990 | 2290 | deprecated_write_register_gen (regnum, val); |
283150cd EZ |
2291 | fp_args[double_arg_index] = 1; |
2292 | fp_args[double_arg_index + 1] = 1; | |
2293 | /* Skip the corresponding general argument register. */ | |
2294 | int_argreg ++; | |
2295 | } | |
2296 | else | |
2297 | ; | |
2298 | /* Store it as the integers, 8 bytes at the time, if | |
2299 | necessary spilling on the stack. */ | |
2300 | } | |
2301 | } | |
2302 | } | |
2303 | return sp; | |
2304 | } | |
2305 | ||
c906108c SS |
2306 | /* Function: push_return_address (pc) |
2307 | Set up the return address for the inferior function call. | |
2308 | Needed for targets where we don't actually execute a JSR/BSR instruction */ | |
2309 | ||
cc17453a | 2310 | static CORE_ADDR |
fba45db2 | 2311 | sh_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
c906108c | 2312 | { |
283150cd EZ |
2313 | write_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM, |
2314 | CALL_DUMMY_ADDRESS ()); | |
c906108c SS |
2315 | return sp; |
2316 | } | |
2317 | ||
2318 | /* Function: fix_call_dummy | |
2319 | Poke the callee function's address into the destination part of | |
2320 | the CALL_DUMMY. The address is actually stored in a data word | |
2321 | following the actualy CALL_DUMMY instructions, which will load | |
2322 | it into a register using PC-relative addressing. This function | |
2323 | expects the CALL_DUMMY to look like this: | |
2324 | ||
c5aa993b JM |
2325 | mov.w @(2,PC), R8 |
2326 | jsr @R8 | |
2327 | nop | |
2328 | trap | |
2329 | <destination> | |
2330 | */ | |
c906108c SS |
2331 | |
2332 | #if 0 | |
2333 | void | |
fba45db2 | 2334 | sh_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, |
ea7c478f | 2335 | struct value **args, struct type *type, int gcc_p) |
c906108c SS |
2336 | { |
2337 | *(unsigned long *) (dummy + 8) = fun; | |
2338 | } | |
2339 | #endif | |
2340 | ||
cc17453a EZ |
2341 | /* Find a function's return value in the appropriate registers (in |
2342 | regbuf), and copy it into valbuf. Extract from an array REGBUF | |
2343 | containing the (raw) register state a function return value of type | |
2344 | TYPE, and copy that, in virtual format, into VALBUF. */ | |
2345 | static void | |
fba45db2 | 2346 | sh_extract_return_value (struct type *type, char *regbuf, char *valbuf) |
c906108c | 2347 | { |
cc17453a | 2348 | int len = TYPE_LENGTH (type); |
3116c80a EZ |
2349 | int return_register = R0_REGNUM; |
2350 | int offset; | |
2351 | ||
cc17453a | 2352 | if (len <= 4) |
3116c80a | 2353 | { |
d7449b42 | 2354 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
3116c80a EZ |
2355 | offset = REGISTER_BYTE (return_register) + 4 - len; |
2356 | else | |
2357 | offset = REGISTER_BYTE (return_register); | |
2358 | memcpy (valbuf, regbuf + offset, len); | |
2359 | } | |
cc17453a | 2360 | else if (len <= 8) |
3116c80a | 2361 | { |
d7449b42 | 2362 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
3116c80a EZ |
2363 | offset = REGISTER_BYTE (return_register) + 8 - len; |
2364 | else | |
2365 | offset = REGISTER_BYTE (return_register); | |
2366 | memcpy (valbuf, regbuf + offset, len); | |
2367 | } | |
2368 | else | |
2369 | error ("bad size for return value"); | |
2370 | } | |
2371 | ||
2372 | static void | |
2373 | sh3e_sh4_extract_return_value (struct type *type, char *regbuf, char *valbuf) | |
2374 | { | |
2375 | int return_register; | |
2376 | int offset; | |
2377 | int len = TYPE_LENGTH (type); | |
2378 | ||
2379 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2380 | return_register = FP0_REGNUM; | |
2381 | else | |
2382 | return_register = R0_REGNUM; | |
2383 | ||
2384 | if (len == 8 && TYPE_CODE (type) == TYPE_CODE_FLT) | |
2385 | { | |
2386 | DOUBLEST val; | |
778eb05e | 2387 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) |
3116c80a EZ |
2388 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, |
2389 | (char *) regbuf + REGISTER_BYTE (return_register), | |
2390 | &val); | |
2391 | else | |
2392 | floatformat_to_doublest (&floatformat_ieee_double_big, | |
2393 | (char *) regbuf + REGISTER_BYTE (return_register), | |
2394 | &val); | |
2395 | store_floating (valbuf, len, val); | |
2396 | } | |
2397 | else if (len <= 4) | |
2398 | { | |
d7449b42 | 2399 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
3116c80a EZ |
2400 | offset = REGISTER_BYTE (return_register) + 4 - len; |
2401 | else | |
2402 | offset = REGISTER_BYTE (return_register); | |
2403 | memcpy (valbuf, regbuf + offset, len); | |
2404 | } | |
2405 | else if (len <= 8) | |
2406 | { | |
d7449b42 | 2407 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
3116c80a EZ |
2408 | offset = REGISTER_BYTE (return_register) + 8 - len; |
2409 | else | |
2410 | offset = REGISTER_BYTE (return_register); | |
2411 | memcpy (valbuf, regbuf + offset, len); | |
2412 | } | |
cc17453a EZ |
2413 | else |
2414 | error ("bad size for return value"); | |
2415 | } | |
c906108c | 2416 | |
283150cd EZ |
2417 | static void |
2418 | sh64_extract_return_value (struct type *type, char *regbuf, char *valbuf) | |
2419 | { | |
2420 | int offset; | |
2421 | int return_register; | |
2422 | int len = TYPE_LENGTH (type); | |
2423 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2424 | ||
2425 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2426 | { | |
2427 | if (len == 4) | |
2428 | { | |
2429 | /* Return value stored in FP0_REGNUM */ | |
2430 | return_register = FP0_REGNUM; | |
2431 | offset = REGISTER_BYTE (return_register); | |
2432 | memcpy (valbuf, (char *) regbuf + offset, len); | |
2433 | } | |
2434 | else if (len == 8) | |
2435 | { | |
2436 | /* return value stored in DR0_REGNUM */ | |
2437 | DOUBLEST val; | |
2438 | ||
2439 | return_register = tdep->DR0_REGNUM; | |
2440 | offset = REGISTER_BYTE (return_register); | |
2441 | ||
2442 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
2443 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, | |
2444 | (char *) regbuf + offset, &val); | |
2445 | else | |
2446 | floatformat_to_doublest (&floatformat_ieee_double_big, | |
2447 | (char *) regbuf + offset, &val); | |
2448 | store_floating (valbuf, len, val); | |
2449 | } | |
2450 | } | |
2451 | else | |
2452 | { | |
2453 | if (len <= 8) | |
2454 | { | |
2455 | /* Result is in register 2. If smaller than 8 bytes, it is padded | |
2456 | at the most significant end. */ | |
2457 | return_register = tdep->RETURN_REGNUM; | |
2458 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2459 | offset = REGISTER_BYTE (return_register) + | |
2460 | REGISTER_RAW_SIZE (return_register) - len; | |
2461 | else | |
2462 | offset = REGISTER_BYTE (return_register); | |
2463 | memcpy (valbuf, (char *) regbuf + offset, len); | |
2464 | } | |
2465 | else | |
2466 | error ("bad size for return value"); | |
2467 | } | |
2468 | } | |
2469 | ||
cc17453a EZ |
2470 | /* Write into appropriate registers a function return value |
2471 | of type TYPE, given in virtual format. | |
2472 | If the architecture is sh4 or sh3e, store a function's return value | |
2473 | in the R0 general register or in the FP0 floating point register, | |
2474 | depending on the type of the return value. In all the other cases | |
3bbfbb92 | 2475 | the result is stored in r0, left-justified. */ |
cc17453a EZ |
2476 | static void |
2477 | sh_default_store_return_value (struct type *type, char *valbuf) | |
2478 | { | |
d19b71be MS |
2479 | char buf[32]; /* more than enough... */ |
2480 | ||
2481 | if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (R0_REGNUM)) | |
2482 | { | |
2483 | /* Add leading zeros to the value. */ | |
2484 | memset (buf, 0, REGISTER_RAW_SIZE (R0_REGNUM)); | |
7079c36c CV |
2485 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
2486 | memcpy (buf + REGISTER_RAW_SIZE (R0_REGNUM) - TYPE_LENGTH (type), | |
2487 | valbuf, TYPE_LENGTH (type)); | |
2488 | else | |
2489 | memcpy (buf, valbuf, TYPE_LENGTH (type)); | |
73937e03 AC |
2490 | deprecated_write_register_bytes (REGISTER_BYTE (R0_REGNUM), buf, |
2491 | REGISTER_RAW_SIZE (R0_REGNUM)); | |
d19b71be MS |
2492 | } |
2493 | else | |
73937e03 AC |
2494 | deprecated_write_register_bytes (REGISTER_BYTE (R0_REGNUM), valbuf, |
2495 | TYPE_LENGTH (type)); | |
cc17453a | 2496 | } |
c906108c | 2497 | |
cc17453a EZ |
2498 | static void |
2499 | sh3e_sh4_store_return_value (struct type *type, char *valbuf) | |
2500 | { | |
2501 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
73937e03 AC |
2502 | deprecated_write_register_bytes (REGISTER_BYTE (FP0_REGNUM), |
2503 | valbuf, TYPE_LENGTH (type)); | |
cc17453a | 2504 | else |
d19b71be | 2505 | sh_default_store_return_value (type, valbuf); |
c906108c SS |
2506 | } |
2507 | ||
283150cd EZ |
2508 | static void |
2509 | sh64_store_return_value (struct type *type, char *valbuf) | |
2510 | { | |
2511 | char buf[64]; /* more than enough... */ | |
2512 | int len = TYPE_LENGTH (type); | |
2513 | ||
2514 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2515 | { | |
2516 | if (len == 4) | |
2517 | { | |
2518 | /* Return value stored in FP0_REGNUM */ | |
4caf0990 | 2519 | deprecated_write_register_gen (FP0_REGNUM, valbuf); |
283150cd EZ |
2520 | } |
2521 | if (len == 8) | |
2522 | { | |
2523 | /* return value stored in DR0_REGNUM */ | |
2524 | /* FIXME: Implement */ | |
2525 | } | |
2526 | } | |
2527 | else | |
2528 | { | |
2529 | int return_register = gdbarch_tdep (current_gdbarch)->RETURN_REGNUM; | |
2530 | int offset = 0; | |
2531 | ||
2532 | if (len <= REGISTER_RAW_SIZE (return_register)) | |
2533 | { | |
2534 | /* Pad with zeros. */ | |
2535 | memset (buf, 0, REGISTER_RAW_SIZE (return_register)); | |
2536 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
2537 | offset = 0; /*REGISTER_RAW_SIZE (return_register) - len;*/ | |
2538 | else | |
2539 | offset = REGISTER_RAW_SIZE (return_register) - len; | |
2540 | ||
2541 | memcpy (buf + offset, valbuf, len); | |
4caf0990 | 2542 | deprecated_write_register_gen (return_register, buf); |
283150cd EZ |
2543 | } |
2544 | else | |
4caf0990 | 2545 | deprecated_write_register_gen (return_register, valbuf); |
283150cd EZ |
2546 | } |
2547 | } | |
2548 | ||
c906108c SS |
2549 | /* Print the registers in a form similar to the E7000 */ |
2550 | ||
2551 | static void | |
fba45db2 | 2552 | sh_generic_show_regs (void) |
c906108c | 2553 | { |
f81353e4 EZ |
2554 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2555 | ||
cc17453a EZ |
2556 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
2557 | paddr (read_register (PC_REGNUM)), | |
f81353e4 EZ |
2558 | (long) read_register (tdep->SR_REGNUM), |
2559 | (long) read_register (tdep->PR_REGNUM), | |
cc17453a EZ |
2560 | (long) read_register (MACH_REGNUM), |
2561 | (long) read_register (MACL_REGNUM)); | |
2562 | ||
2563 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
2564 | (long) read_register (GBR_REGNUM), | |
2565 | (long) read_register (VBR_REGNUM)); | |
2566 | ||
2567 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2568 | (long) read_register (0), | |
2569 | (long) read_register (1), | |
2570 | (long) read_register (2), | |
2571 | (long) read_register (3), | |
2572 | (long) read_register (4), | |
2573 | (long) read_register (5), | |
2574 | (long) read_register (6), | |
2575 | (long) read_register (7)); | |
2576 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2577 | (long) read_register (8), | |
2578 | (long) read_register (9), | |
2579 | (long) read_register (10), | |
2580 | (long) read_register (11), | |
2581 | (long) read_register (12), | |
2582 | (long) read_register (13), | |
2583 | (long) read_register (14), | |
2584 | (long) read_register (15)); | |
2585 | } | |
c906108c | 2586 | |
cc17453a | 2587 | static void |
fba45db2 | 2588 | sh3_show_regs (void) |
cc17453a | 2589 | { |
f81353e4 EZ |
2590 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2591 | ||
d4f3574e SS |
2592 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
2593 | paddr (read_register (PC_REGNUM)), | |
f81353e4 EZ |
2594 | (long) read_register (tdep->SR_REGNUM), |
2595 | (long) read_register (tdep->PR_REGNUM), | |
d4f3574e SS |
2596 | (long) read_register (MACH_REGNUM), |
2597 | (long) read_register (MACL_REGNUM)); | |
2598 | ||
2599 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
2600 | (long) read_register (GBR_REGNUM), | |
2601 | (long) read_register (VBR_REGNUM)); | |
cc17453a | 2602 | printf_filtered (" SSR=%08lx SPC=%08lx", |
f81353e4 EZ |
2603 | (long) read_register (tdep->SSR_REGNUM), |
2604 | (long) read_register (tdep->SPC_REGNUM)); | |
c906108c | 2605 | |
d4f3574e SS |
2606 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
2607 | (long) read_register (0), | |
2608 | (long) read_register (1), | |
2609 | (long) read_register (2), | |
2610 | (long) read_register (3), | |
2611 | (long) read_register (4), | |
2612 | (long) read_register (5), | |
2613 | (long) read_register (6), | |
2614 | (long) read_register (7)); | |
2615 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2616 | (long) read_register (8), | |
2617 | (long) read_register (9), | |
2618 | (long) read_register (10), | |
2619 | (long) read_register (11), | |
2620 | (long) read_register (12), | |
2621 | (long) read_register (13), | |
2622 | (long) read_register (14), | |
2623 | (long) read_register (15)); | |
c906108c SS |
2624 | } |
2625 | ||
53116e27 | 2626 | |
cc17453a | 2627 | static void |
fba45db2 | 2628 | sh3e_show_regs (void) |
cc17453a | 2629 | { |
f81353e4 EZ |
2630 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2631 | ||
cc17453a EZ |
2632 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
2633 | paddr (read_register (PC_REGNUM)), | |
f81353e4 EZ |
2634 | (long) read_register (tdep->SR_REGNUM), |
2635 | (long) read_register (tdep->PR_REGNUM), | |
cc17453a EZ |
2636 | (long) read_register (MACH_REGNUM), |
2637 | (long) read_register (MACL_REGNUM)); | |
2638 | ||
2639 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
2640 | (long) read_register (GBR_REGNUM), | |
2641 | (long) read_register (VBR_REGNUM)); | |
2642 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
f81353e4 EZ |
2643 | (long) read_register (tdep->SSR_REGNUM), |
2644 | (long) read_register (tdep->SPC_REGNUM)); | |
cc17453a | 2645 | printf_filtered (" FPUL=%08lx FPSCR=%08lx", |
f81353e4 EZ |
2646 | (long) read_register (tdep->FPUL_REGNUM), |
2647 | (long) read_register (tdep->FPSCR_REGNUM)); | |
c906108c | 2648 | |
cc17453a EZ |
2649 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
2650 | (long) read_register (0), | |
2651 | (long) read_register (1), | |
2652 | (long) read_register (2), | |
2653 | (long) read_register (3), | |
2654 | (long) read_register (4), | |
2655 | (long) read_register (5), | |
2656 | (long) read_register (6), | |
2657 | (long) read_register (7)); | |
2658 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2659 | (long) read_register (8), | |
2660 | (long) read_register (9), | |
2661 | (long) read_register (10), | |
2662 | (long) read_register (11), | |
2663 | (long) read_register (12), | |
2664 | (long) read_register (13), | |
2665 | (long) read_register (14), | |
2666 | (long) read_register (15)); | |
2667 | ||
2668 | printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
2669 | (long) read_register (FP0_REGNUM + 0), | |
2670 | (long) read_register (FP0_REGNUM + 1), | |
2671 | (long) read_register (FP0_REGNUM + 2), | |
2672 | (long) read_register (FP0_REGNUM + 3), | |
2673 | (long) read_register (FP0_REGNUM + 4), | |
2674 | (long) read_register (FP0_REGNUM + 5), | |
2675 | (long) read_register (FP0_REGNUM + 6), | |
2676 | (long) read_register (FP0_REGNUM + 7)); | |
2677 | printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
2678 | (long) read_register (FP0_REGNUM + 8), | |
2679 | (long) read_register (FP0_REGNUM + 9), | |
2680 | (long) read_register (FP0_REGNUM + 10), | |
2681 | (long) read_register (FP0_REGNUM + 11), | |
2682 | (long) read_register (FP0_REGNUM + 12), | |
2683 | (long) read_register (FP0_REGNUM + 13), | |
2684 | (long) read_register (FP0_REGNUM + 14), | |
2685 | (long) read_register (FP0_REGNUM + 15)); | |
2686 | } | |
2687 | ||
2688 | static void | |
fba45db2 | 2689 | sh3_dsp_show_regs (void) |
c906108c | 2690 | { |
f81353e4 EZ |
2691 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2692 | ||
cc17453a EZ |
2693 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
2694 | paddr (read_register (PC_REGNUM)), | |
f81353e4 EZ |
2695 | (long) read_register (tdep->SR_REGNUM), |
2696 | (long) read_register (tdep->PR_REGNUM), | |
cc17453a EZ |
2697 | (long) read_register (MACH_REGNUM), |
2698 | (long) read_register (MACL_REGNUM)); | |
c906108c | 2699 | |
cc17453a EZ |
2700 | printf_filtered ("GBR=%08lx VBR=%08lx", |
2701 | (long) read_register (GBR_REGNUM), | |
2702 | (long) read_register (VBR_REGNUM)); | |
2703 | ||
2704 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
f81353e4 EZ |
2705 | (long) read_register (tdep->SSR_REGNUM), |
2706 | (long) read_register (tdep->SPC_REGNUM)); | |
cc17453a EZ |
2707 | |
2708 | printf_filtered (" DSR=%08lx", | |
f81353e4 | 2709 | (long) read_register (tdep->DSR_REGNUM)); |
cc17453a EZ |
2710 | |
2711 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2712 | (long) read_register (0), | |
2713 | (long) read_register (1), | |
2714 | (long) read_register (2), | |
2715 | (long) read_register (3), | |
2716 | (long) read_register (4), | |
2717 | (long) read_register (5), | |
2718 | (long) read_register (6), | |
2719 | (long) read_register (7)); | |
2720 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2721 | (long) read_register (8), | |
2722 | (long) read_register (9), | |
2723 | (long) read_register (10), | |
2724 | (long) read_register (11), | |
2725 | (long) read_register (12), | |
2726 | (long) read_register (13), | |
2727 | (long) read_register (14), | |
2728 | (long) read_register (15)); | |
2729 | ||
2730 | printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", | |
f81353e4 EZ |
2731 | (long) read_register (tdep->A0G_REGNUM) & 0xff, |
2732 | (long) read_register (tdep->A0_REGNUM), | |
2733 | (long) read_register (tdep->M0_REGNUM), | |
2734 | (long) read_register (tdep->X0_REGNUM), | |
2735 | (long) read_register (tdep->Y0_REGNUM), | |
2736 | (long) read_register (tdep->RS_REGNUM), | |
2737 | (long) read_register (tdep->MOD_REGNUM)); | |
cc17453a | 2738 | printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", |
f81353e4 EZ |
2739 | (long) read_register (tdep->A1G_REGNUM) & 0xff, |
2740 | (long) read_register (tdep->A1_REGNUM), | |
2741 | (long) read_register (tdep->M1_REGNUM), | |
2742 | (long) read_register (tdep->X1_REGNUM), | |
2743 | (long) read_register (tdep->Y1_REGNUM), | |
2744 | (long) read_register (tdep->RE_REGNUM)); | |
c906108c SS |
2745 | } |
2746 | ||
cc17453a | 2747 | static void |
fba45db2 | 2748 | sh4_show_regs (void) |
cc17453a | 2749 | { |
f81353e4 EZ |
2750 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2751 | ||
2752 | int pr = read_register (tdep->FPSCR_REGNUM) & 0x80000; | |
cc17453a EZ |
2753 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
2754 | paddr (read_register (PC_REGNUM)), | |
f81353e4 EZ |
2755 | (long) read_register (tdep->SR_REGNUM), |
2756 | (long) read_register (tdep->PR_REGNUM), | |
cc17453a EZ |
2757 | (long) read_register (MACH_REGNUM), |
2758 | (long) read_register (MACL_REGNUM)); | |
2759 | ||
2760 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
2761 | (long) read_register (GBR_REGNUM), | |
2762 | (long) read_register (VBR_REGNUM)); | |
2763 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
f81353e4 EZ |
2764 | (long) read_register (tdep->SSR_REGNUM), |
2765 | (long) read_register (tdep->SPC_REGNUM)); | |
cc17453a | 2766 | printf_filtered (" FPUL=%08lx FPSCR=%08lx", |
f81353e4 EZ |
2767 | (long) read_register (tdep->FPUL_REGNUM), |
2768 | (long) read_register (tdep->FPSCR_REGNUM)); | |
cc17453a EZ |
2769 | |
2770 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2771 | (long) read_register (0), | |
2772 | (long) read_register (1), | |
2773 | (long) read_register (2), | |
2774 | (long) read_register (3), | |
2775 | (long) read_register (4), | |
2776 | (long) read_register (5), | |
2777 | (long) read_register (6), | |
2778 | (long) read_register (7)); | |
2779 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2780 | (long) read_register (8), | |
2781 | (long) read_register (9), | |
2782 | (long) read_register (10), | |
2783 | (long) read_register (11), | |
2784 | (long) read_register (12), | |
2785 | (long) read_register (13), | |
2786 | (long) read_register (14), | |
2787 | (long) read_register (15)); | |
2788 | ||
2789 | printf_filtered ((pr | |
2790 | ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
2791 | : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
2792 | (long) read_register (FP0_REGNUM + 0), | |
2793 | (long) read_register (FP0_REGNUM + 1), | |
2794 | (long) read_register (FP0_REGNUM + 2), | |
2795 | (long) read_register (FP0_REGNUM + 3), | |
2796 | (long) read_register (FP0_REGNUM + 4), | |
2797 | (long) read_register (FP0_REGNUM + 5), | |
2798 | (long) read_register (FP0_REGNUM + 6), | |
2799 | (long) read_register (FP0_REGNUM + 7)); | |
2800 | printf_filtered ((pr | |
2801 | ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
2802 | : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
2803 | (long) read_register (FP0_REGNUM + 8), | |
2804 | (long) read_register (FP0_REGNUM + 9), | |
2805 | (long) read_register (FP0_REGNUM + 10), | |
2806 | (long) read_register (FP0_REGNUM + 11), | |
2807 | (long) read_register (FP0_REGNUM + 12), | |
2808 | (long) read_register (FP0_REGNUM + 13), | |
2809 | (long) read_register (FP0_REGNUM + 14), | |
2810 | (long) read_register (FP0_REGNUM + 15)); | |
2811 | } | |
2812 | ||
2813 | static void | |
fba45db2 | 2814 | sh_dsp_show_regs (void) |
cc17453a | 2815 | { |
f81353e4 EZ |
2816 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2817 | ||
cc17453a EZ |
2818 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
2819 | paddr (read_register (PC_REGNUM)), | |
f81353e4 EZ |
2820 | (long) read_register (tdep->SR_REGNUM), |
2821 | (long) read_register (tdep->PR_REGNUM), | |
cc17453a EZ |
2822 | (long) read_register (MACH_REGNUM), |
2823 | (long) read_register (MACL_REGNUM)); | |
2824 | ||
2825 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
2826 | (long) read_register (GBR_REGNUM), | |
2827 | (long) read_register (VBR_REGNUM)); | |
2828 | ||
2829 | printf_filtered (" DSR=%08lx", | |
f81353e4 | 2830 | (long) read_register (tdep->DSR_REGNUM)); |
cc17453a EZ |
2831 | |
2832 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2833 | (long) read_register (0), | |
2834 | (long) read_register (1), | |
2835 | (long) read_register (2), | |
2836 | (long) read_register (3), | |
2837 | (long) read_register (4), | |
2838 | (long) read_register (5), | |
2839 | (long) read_register (6), | |
2840 | (long) read_register (7)); | |
2841 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2842 | (long) read_register (8), | |
2843 | (long) read_register (9), | |
2844 | (long) read_register (10), | |
2845 | (long) read_register (11), | |
2846 | (long) read_register (12), | |
2847 | (long) read_register (13), | |
2848 | (long) read_register (14), | |
2849 | (long) read_register (15)); | |
2850 | ||
2851 | printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", | |
f81353e4 EZ |
2852 | (long) read_register (tdep->A0G_REGNUM) & 0xff, |
2853 | (long) read_register (tdep->A0_REGNUM), | |
2854 | (long) read_register (tdep->M0_REGNUM), | |
2855 | (long) read_register (tdep->X0_REGNUM), | |
2856 | (long) read_register (tdep->Y0_REGNUM), | |
2857 | (long) read_register (tdep->RS_REGNUM), | |
2858 | (long) read_register (tdep->MOD_REGNUM)); | |
cc17453a | 2859 | printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", |
f81353e4 EZ |
2860 | (long) read_register (tdep->A1G_REGNUM) & 0xff, |
2861 | (long) read_register (tdep->A1_REGNUM), | |
2862 | (long) read_register (tdep->M1_REGNUM), | |
2863 | (long) read_register (tdep->X1_REGNUM), | |
2864 | (long) read_register (tdep->Y1_REGNUM), | |
2865 | (long) read_register (tdep->RE_REGNUM)); | |
cc17453a EZ |
2866 | } |
2867 | ||
283150cd EZ |
2868 | static void |
2869 | sh64_show_media_regs (void) | |
2870 | { | |
2871 | int i; | |
2872 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2873 | ||
2874 | printf_filtered ("PC=%s SR=%016llx \n", | |
2875 | paddr (read_register (PC_REGNUM)), | |
2876 | (long long) read_register (tdep->SR_REGNUM)); | |
2877 | ||
2878 | printf_filtered ("SSR=%016llx SPC=%016llx \n", | |
2879 | (long long) read_register (tdep->SSR_REGNUM), | |
2880 | (long long) read_register (tdep->SPC_REGNUM)); | |
2881 | printf_filtered ("FPSCR=%016lx\n ", | |
2882 | (long) read_register (tdep->FPSCR_REGNUM)); | |
2883 | ||
2884 | for (i = 0; i < 64; i = i + 4) | |
2885 | printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n", | |
2886 | i, i + 3, | |
2887 | (long long) read_register (i + 0), | |
2888 | (long long) read_register (i + 1), | |
2889 | (long long) read_register (i + 2), | |
2890 | (long long) read_register (i + 3)); | |
2891 | ||
2892 | printf_filtered ("\n"); | |
2893 | ||
2894 | for (i = 0; i < 64; i = i + 8) | |
2895 | printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2896 | i, i + 7, | |
2897 | (long) read_register (FP0_REGNUM + i + 0), | |
2898 | (long) read_register (FP0_REGNUM + i + 1), | |
2899 | (long) read_register (FP0_REGNUM + i + 2), | |
2900 | (long) read_register (FP0_REGNUM + i + 3), | |
2901 | (long) read_register (FP0_REGNUM + i + 4), | |
2902 | (long) read_register (FP0_REGNUM + i + 5), | |
2903 | (long) read_register (FP0_REGNUM + i + 6), | |
2904 | (long) read_register (FP0_REGNUM + i + 7)); | |
2905 | } | |
2906 | ||
2907 | static void | |
2908 | sh64_show_compact_regs (void) | |
2909 | { | |
2910 | int i; | |
2911 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2912 | ||
2913 | printf_filtered ("PC=%s \n", | |
2914 | paddr (read_register (tdep->PC_C_REGNUM))); | |
2915 | ||
2916 | printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n", | |
2917 | (long) read_register (tdep->GBR_C_REGNUM), | |
2918 | (long) read_register (tdep->MACH_C_REGNUM), | |
2919 | (long) read_register (tdep->MACL_C_REGNUM), | |
2920 | (long) read_register (tdep->PR_C_REGNUM), | |
2921 | (long) read_register (tdep->T_C_REGNUM)); | |
2922 | printf_filtered ("FPSCR=%08lx FPUL=%08lx\n", | |
2923 | (long) read_register (tdep->FPSCR_REGNUM), | |
2924 | (long) read_register (tdep->FPUL_REGNUM)); | |
2925 | ||
2926 | for (i = 0; i < 16; i = i + 4) | |
2927 | printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n", | |
2928 | i, i + 3, | |
2929 | (long) read_register (i + 0), | |
2930 | (long) read_register (i + 1), | |
2931 | (long) read_register (i + 2), | |
2932 | (long) read_register (i + 3)); | |
2933 | ||
2934 | printf_filtered ("\n"); | |
2935 | ||
2936 | for (i = 0; i < 16; i = i + 8) | |
2937 | printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2938 | i, i + 7, | |
2939 | (long) read_register (FP0_REGNUM + i + 0), | |
2940 | (long) read_register (FP0_REGNUM + i + 1), | |
2941 | (long) read_register (FP0_REGNUM + i + 2), | |
2942 | (long) read_register (FP0_REGNUM + i + 3), | |
2943 | (long) read_register (FP0_REGNUM + i + 4), | |
2944 | (long) read_register (FP0_REGNUM + i + 5), | |
2945 | (long) read_register (FP0_REGNUM + i + 6), | |
2946 | (long) read_register (FP0_REGNUM + i + 7)); | |
2947 | } | |
2948 | ||
2949 | /*FIXME!!! This only shows the registers for shmedia, excluding the | |
2950 | pseudo registers. */ | |
2951 | static void | |
2952 | sh64_show_regs (void) | |
2953 | { | |
50abf9e5 | 2954 | if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame))) |
283150cd EZ |
2955 | sh64_show_media_regs (); |
2956 | else | |
2957 | sh64_show_compact_regs (); | |
2958 | } | |
2959 | ||
53116e27 EZ |
2960 | void sh_show_regs_command (char *args, int from_tty) |
2961 | { | |
2962 | if (sh_show_regs) | |
2963 | (*sh_show_regs)(); | |
2964 | } | |
2965 | ||
cc17453a EZ |
2966 | /* Index within `registers' of the first byte of the space for |
2967 | register N. */ | |
2968 | static int | |
fba45db2 | 2969 | sh_default_register_byte (int reg_nr) |
8db62801 | 2970 | { |
cc17453a EZ |
2971 | return (reg_nr * 4); |
2972 | } | |
2973 | ||
53116e27 | 2974 | static int |
fba45db2 | 2975 | sh_sh4_register_byte (int reg_nr) |
53116e27 | 2976 | { |
f81353e4 EZ |
2977 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2978 | ||
2979 | if (reg_nr >= tdep->DR0_REGNUM | |
2980 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
53116e27 | 2981 | return (dr_reg_base_num (reg_nr) * 4); |
f81353e4 EZ |
2982 | else if (reg_nr >= tdep->FV0_REGNUM |
2983 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
53116e27 EZ |
2984 | return (fv_reg_base_num (reg_nr) * 4); |
2985 | else | |
2986 | return (reg_nr * 4); | |
2987 | } | |
2988 | ||
283150cd EZ |
2989 | /* *INDENT-OFF* */ |
2990 | /* | |
2991 | SH MEDIA MODE (ISA 32) | |
2992 | general registers (64-bit) 0-63 | |
2993 | 0 r0, r1, r2, r3, r4, r5, r6, r7, | |
2994 | 64 r8, r9, r10, r11, r12, r13, r14, r15, | |
2995 | 128 r16, r17, r18, r19, r20, r21, r22, r23, | |
2996 | 192 r24, r25, r26, r27, r28, r29, r30, r31, | |
2997 | 256 r32, r33, r34, r35, r36, r37, r38, r39, | |
2998 | 320 r40, r41, r42, r43, r44, r45, r46, r47, | |
2999 | 384 r48, r49, r50, r51, r52, r53, r54, r55, | |
3000 | 448 r56, r57, r58, r59, r60, r61, r62, r63, | |
3001 | ||
3002 | pc (64-bit) 64 | |
3003 | 512 pc, | |
3004 | ||
3005 | status reg., saved status reg., saved pc reg. (64-bit) 65-67 | |
3006 | 520 sr, ssr, spc, | |
3007 | ||
3008 | target registers (64-bit) 68-75 | |
3009 | 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7, | |
3010 | ||
3011 | floating point state control register (32-bit) 76 | |
3012 | 608 fpscr, | |
3013 | ||
3014 | single precision floating point registers (32-bit) 77-140 | |
3015 | 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, | |
3016 | 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15, | |
3017 | 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23, | |
3018 | 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31, | |
3019 | 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39, | |
3020 | 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47, | |
3021 | 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55, | |
3022 | 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63, | |
3023 | ||
3024 | TOTAL SPACE FOR REGISTERS: 868 bytes | |
3025 | ||
3026 | From here on they are all pseudo registers: no memory allocated. | |
3027 | REGISTER_BYTE returns the register byte for the base register. | |
3028 | ||
3029 | double precision registers (pseudo) 141-172 | |
3030 | dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14, | |
3031 | dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30, | |
3032 | dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46, | |
3033 | dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62, | |
3034 | ||
3035 | floating point pairs (pseudo) 173-204 | |
3036 | fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14, | |
3037 | fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30, | |
3038 | fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46, | |
3039 | fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62, | |
3040 | ||
3041 | floating point vectors (4 floating point regs) (pseudo) 205-220 | |
3042 | fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28, | |
3043 | fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60, | |
3044 | ||
3045 | SH COMPACT MODE (ISA 16) (all pseudo) 221-272 | |
3046 | r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c, | |
3047 | r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c, | |
3048 | pc_c, | |
3049 | gbr_c, mach_c, macl_c, pr_c, t_c, | |
3050 | fpscr_c, fpul_c, | |
3051 | fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c, | |
3052 | fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c | |
3053 | dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c | |
3054 | fv0_c, fv4_c, fv8_c, fv12_c | |
3055 | */ | |
3056 | /* *INDENT-ON* */ | |
3057 | static int | |
3058 | sh_sh64_register_byte (int reg_nr) | |
3059 | { | |
3060 | int base_regnum = -1; | |
3061 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3062 | ||
3063 | /* If it is a pseudo register, get the number of the first floating | |
3064 | point register that is part of it. */ | |
3065 | if (reg_nr >= tdep->DR0_REGNUM | |
3066 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
3067 | base_regnum = dr_reg_base_num (reg_nr); | |
3068 | ||
3069 | else if (reg_nr >= tdep->FPP0_REGNUM | |
3070 | && reg_nr <= tdep->FPP_LAST_REGNUM) | |
3071 | base_regnum = fpp_reg_base_num (reg_nr); | |
3072 | ||
3073 | else if (reg_nr >= tdep->FV0_REGNUM | |
3074 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
3075 | base_regnum = fv_reg_base_num (reg_nr); | |
3076 | ||
3077 | /* sh compact pseudo register. FPSCR is a pathological case, need to | |
3078 | treat it as special. */ | |
3079 | else if ((reg_nr >= tdep->R0_C_REGNUM | |
3080 | && reg_nr <= tdep->FV_LAST_C_REGNUM) | |
3081 | && reg_nr != tdep->FPSCR_C_REGNUM) | |
3082 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3083 | ||
3084 | /* Now return the offset in bytes within the register cache. */ | |
3085 | /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */ | |
3086 | if (reg_nr >= tdep->DR0_REGNUM | |
3087 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
3088 | return (base_regnum - FP0_REGNUM + 1) * 4 | |
3089 | + (tdep->TR7_REGNUM + 1) * 8; | |
3090 | ||
3091 | /* sh compact pseudo register: general register */ | |
3092 | if ((reg_nr >= tdep->R0_C_REGNUM | |
3093 | && reg_nr <= tdep->R_LAST_C_REGNUM)) | |
3094 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3095 | ? base_regnum * 8 + 4 | |
3096 | : base_regnum * 8); | |
3097 | ||
3098 | /* sh compact pseudo register: */ | |
3099 | if (reg_nr == tdep->PC_C_REGNUM | |
3100 | || reg_nr == tdep->GBR_C_REGNUM | |
3101 | || reg_nr == tdep->MACL_C_REGNUM | |
3102 | || reg_nr == tdep->PR_C_REGNUM) | |
3103 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3104 | ? base_regnum * 8 + 4 | |
3105 | : base_regnum * 8); | |
3106 | ||
3107 | if (reg_nr == tdep->MACH_C_REGNUM) | |
3108 | return base_regnum * 8; | |
3109 | ||
3110 | if (reg_nr == tdep->T_C_REGNUM) | |
3111 | return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */ | |
3112 | ||
3113 | /* sh compact pseudo register: floating point register */ | |
3114 | else if (reg_nr >=tdep->FP0_C_REGNUM | |
3115 | && reg_nr <= tdep->FV_LAST_C_REGNUM) | |
3116 | return (base_regnum - FP0_REGNUM) * 4 | |
3117 | + (tdep->TR7_REGNUM + 1) * 8 + 4; | |
3118 | ||
3119 | else if (reg_nr == tdep->FPSCR_C_REGNUM) | |
3120 | /* This is complicated, for now return the beginning of the | |
3121 | architectural FPSCR register. */ | |
3122 | return (tdep->TR7_REGNUM + 1) * 8; | |
3123 | ||
3124 | else if (reg_nr == tdep->FPUL_C_REGNUM) | |
3125 | return ((base_regnum - FP0_REGNUM) * 4 + | |
3126 | (tdep->TR7_REGNUM + 1) * 8 + 4); | |
3127 | ||
3128 | /* It is not a pseudo register. */ | |
3129 | /* It is a 64 bit register. */ | |
3130 | else if (reg_nr <= tdep->TR7_REGNUM) | |
3131 | return reg_nr * 8; | |
3132 | ||
3133 | /* It is a 32 bit register. */ | |
3134 | else | |
3135 | if (reg_nr == tdep->FPSCR_REGNUM) | |
3136 | return (tdep->FPSCR_REGNUM * 8); | |
3137 | ||
3138 | /* It is floating point 32-bit register */ | |
3139 | else | |
3140 | return ((tdep->TR7_REGNUM + 1) * 8 | |
3141 | + (reg_nr - FP0_REGNUM + 1) * 4); | |
3142 | } | |
3143 | ||
cc17453a EZ |
3144 | /* Number of bytes of storage in the actual machine representation for |
3145 | register REG_NR. */ | |
3146 | static int | |
fba45db2 | 3147 | sh_default_register_raw_size (int reg_nr) |
cc17453a EZ |
3148 | { |
3149 | return 4; | |
3150 | } | |
3151 | ||
53116e27 | 3152 | static int |
fba45db2 | 3153 | sh_sh4_register_raw_size (int reg_nr) |
53116e27 | 3154 | { |
f81353e4 EZ |
3155 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3156 | ||
3157 | if (reg_nr >= tdep->DR0_REGNUM | |
3158 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
53116e27 | 3159 | return 8; |
f81353e4 EZ |
3160 | else if (reg_nr >= tdep->FV0_REGNUM |
3161 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
53116e27 EZ |
3162 | return 16; |
3163 | else | |
3164 | return 4; | |
3165 | } | |
3166 | ||
283150cd EZ |
3167 | static int |
3168 | sh_sh64_register_raw_size (int reg_nr) | |
3169 | { | |
3170 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3171 | ||
3172 | if ((reg_nr >= tdep->DR0_REGNUM | |
3173 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
3174 | || (reg_nr >= tdep->FPP0_REGNUM | |
3175 | && reg_nr <= tdep->FPP_LAST_REGNUM) | |
3176 | || (reg_nr >= tdep->DR0_C_REGNUM | |
3177 | && reg_nr <= tdep->DR_LAST_C_REGNUM) | |
3178 | || (reg_nr <= tdep->TR7_REGNUM)) | |
3179 | return 8; | |
3180 | ||
3181 | else if ((reg_nr >= tdep->FV0_REGNUM | |
3182 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
3183 | || (reg_nr >= tdep->FV0_C_REGNUM | |
3184 | && reg_nr <= tdep->FV_LAST_C_REGNUM)) | |
3185 | return 16; | |
3186 | ||
3187 | else /* this covers also the 32-bit SH compact registers. */ | |
3188 | return 4; | |
3189 | } | |
3190 | ||
cc17453a EZ |
3191 | /* Number of bytes of storage in the program's representation |
3192 | for register N. */ | |
3193 | static int | |
fba45db2 | 3194 | sh_register_virtual_size (int reg_nr) |
cc17453a EZ |
3195 | { |
3196 | return 4; | |
3197 | } | |
3198 | ||
283150cd EZ |
3199 | /* ??????? FIXME */ |
3200 | static int | |
3201 | sh_sh64_register_virtual_size (int reg_nr) | |
3202 | { | |
3203 | if (reg_nr >= FP0_REGNUM | |
3204 | && reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM) | |
3205 | return 4; | |
3206 | else | |
3207 | return 8; | |
3208 | } | |
3209 | ||
cc17453a EZ |
3210 | /* Return the GDB type object for the "standard" data type |
3211 | of data in register N. */ | |
cc17453a | 3212 | static struct type * |
fba45db2 | 3213 | sh_sh3e_register_virtual_type (int reg_nr) |
cc17453a | 3214 | { |
f81353e4 EZ |
3215 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3216 | ||
cc17453a | 3217 | if ((reg_nr >= FP0_REGNUM |
f81353e4 EZ |
3218 | && (reg_nr <= tdep->FP_LAST_REGNUM)) |
3219 | || (reg_nr == tdep->FPUL_REGNUM)) | |
cc17453a | 3220 | return builtin_type_float; |
8db62801 | 3221 | else |
cc17453a EZ |
3222 | return builtin_type_int; |
3223 | } | |
3224 | ||
7f4dbe94 EZ |
3225 | static struct type * |
3226 | sh_sh4_build_float_register_type (int high) | |
3227 | { | |
3228 | struct type *temp; | |
3229 | ||
3230 | temp = create_range_type (NULL, builtin_type_int, 0, high); | |
3231 | return create_array_type (NULL, builtin_type_float, temp); | |
3232 | } | |
3233 | ||
53116e27 | 3234 | static struct type * |
fba45db2 | 3235 | sh_sh4_register_virtual_type (int reg_nr) |
53116e27 | 3236 | { |
f81353e4 EZ |
3237 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3238 | ||
53116e27 | 3239 | if ((reg_nr >= FP0_REGNUM |
f81353e4 EZ |
3240 | && (reg_nr <= tdep->FP_LAST_REGNUM)) |
3241 | || (reg_nr == tdep->FPUL_REGNUM)) | |
53116e27 | 3242 | return builtin_type_float; |
f81353e4 EZ |
3243 | else if (reg_nr >= tdep->DR0_REGNUM |
3244 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
53116e27 | 3245 | return builtin_type_double; |
f81353e4 EZ |
3246 | else if (reg_nr >= tdep->FV0_REGNUM |
3247 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
53116e27 EZ |
3248 | return sh_sh4_build_float_register_type (3); |
3249 | else | |
3250 | return builtin_type_int; | |
3251 | } | |
3252 | ||
283150cd EZ |
3253 | static struct type * |
3254 | sh_sh64_register_virtual_type (int reg_nr) | |
3255 | { | |
3256 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3257 | ||
3258 | if ((reg_nr >= FP0_REGNUM | |
3259 | && reg_nr <= tdep->FP_LAST_REGNUM) | |
3260 | || (reg_nr >= tdep->FP0_C_REGNUM | |
3261 | && reg_nr <= tdep->FP_LAST_C_REGNUM)) | |
3262 | return builtin_type_float; | |
3263 | else if ((reg_nr >= tdep->DR0_REGNUM | |
3264 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
3265 | || (reg_nr >= tdep->DR0_C_REGNUM | |
3266 | && reg_nr <= tdep->DR_LAST_C_REGNUM)) | |
3267 | return builtin_type_double; | |
3268 | else if (reg_nr >= tdep->FPP0_REGNUM | |
3269 | && reg_nr <= tdep->FPP_LAST_REGNUM) | |
3270 | return sh_sh4_build_float_register_type (1); | |
3271 | else if ((reg_nr >= tdep->FV0_REGNUM | |
3272 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
3273 | ||(reg_nr >= tdep->FV0_C_REGNUM | |
3274 | && reg_nr <= tdep->FV_LAST_C_REGNUM)) | |
3275 | return sh_sh4_build_float_register_type (3); | |
3276 | else if (reg_nr == tdep->FPSCR_REGNUM) | |
3277 | return builtin_type_int; | |
3278 | else if (reg_nr >= tdep->R0_C_REGNUM | |
3279 | && reg_nr < tdep->FP0_C_REGNUM) | |
3280 | return builtin_type_int; | |
3281 | else | |
3282 | return builtin_type_long_long; | |
3283 | } | |
3284 | ||
cc17453a | 3285 | static struct type * |
fba45db2 | 3286 | sh_default_register_virtual_type (int reg_nr) |
cc17453a EZ |
3287 | { |
3288 | return builtin_type_int; | |
3289 | } | |
3290 | ||
fb409745 EZ |
3291 | /* On the sh4, the DRi pseudo registers are problematic if the target |
3292 | is little endian. When the user writes one of those registers, for | |
3293 | instance with 'ser var $dr0=1', we want the double to be stored | |
3294 | like this: | |
3295 | fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
3296 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
3297 | ||
3298 | This corresponds to little endian byte order & big endian word | |
3299 | order. However if we let gdb write the register w/o conversion, it | |
3300 | will write fr0 and fr1 this way: | |
3301 | fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
3302 | fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
3303 | because it will consider fr0 and fr1 as a single LE stretch of memory. | |
3304 | ||
3305 | To achieve what we want we must force gdb to store things in | |
3306 | floatformat_ieee_double_littlebyte_bigword (which is defined in | |
3307 | include/floatformat.h and libiberty/floatformat.c. | |
3308 | ||
3309 | In case the target is big endian, there is no problem, the | |
3310 | raw bytes will look like: | |
3311 | fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00 | |
3312 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
3313 | ||
3314 | The other pseudo registers (the FVs) also don't pose a problem | |
3315 | because they are stored as 4 individual FP elements. */ | |
3316 | ||
7bd872fe | 3317 | static void |
fb409745 EZ |
3318 | sh_sh4_register_convert_to_virtual (int regnum, struct type *type, |
3319 | char *from, char *to) | |
3320 | { | |
f81353e4 EZ |
3321 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3322 | ||
3323 | if (regnum >= tdep->DR0_REGNUM | |
3324 | && regnum <= tdep->DR_LAST_REGNUM) | |
fb409745 EZ |
3325 | { |
3326 | DOUBLEST val; | |
3327 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val); | |
3bbfbb92 | 3328 | store_floating (to, TYPE_LENGTH (type), val); |
fb409745 EZ |
3329 | } |
3330 | else | |
3bbfbb92 | 3331 | error ("sh_register_convert_to_virtual called with non DR register number"); |
fb409745 EZ |
3332 | } |
3333 | ||
283150cd EZ |
3334 | void |
3335 | sh_sh64_register_convert_to_virtual (int regnum, struct type *type, | |
3336 | char *from, char *to) | |
3337 | { | |
3338 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3339 | ||
3340 | if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE) | |
3341 | { | |
3342 | /* It is a no-op. */ | |
3343 | memcpy (to, from, REGISTER_RAW_SIZE (regnum)); | |
3344 | return; | |
3345 | } | |
3346 | ||
3347 | if ((regnum >= tdep->DR0_REGNUM | |
3348 | && regnum <= tdep->DR_LAST_REGNUM) | |
3349 | || (regnum >= tdep->DR0_C_REGNUM | |
3350 | && regnum <= tdep->DR_LAST_C_REGNUM)) | |
3351 | { | |
3352 | DOUBLEST val; | |
3353 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val); | |
3354 | store_floating(to, TYPE_LENGTH(type), val); | |
3355 | } | |
3356 | else | |
3357 | error("sh_register_convert_to_virtual called with non DR register number"); | |
3358 | } | |
3359 | ||
3360 | static void | |
3361 | sh_sh4_register_convert_to_raw (struct type *type, int regnum, | |
d8124050 | 3362 | const void *from, void *to) |
283150cd EZ |
3363 | { |
3364 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3365 | ||
3366 | if (regnum >= tdep->DR0_REGNUM | |
3367 | && regnum <= tdep->DR_LAST_REGNUM) | |
3368 | { | |
3369 | DOUBLEST val = extract_floating (from, TYPE_LENGTH(type)); | |
3370 | floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to); | |
3371 | } | |
3372 | else | |
3373 | error("sh_register_convert_to_raw called with non DR register number"); | |
3374 | } | |
3375 | ||
3376 | void | |
3377 | sh_sh64_register_convert_to_raw (struct type *type, int regnum, | |
d8124050 | 3378 | const void *from, void *to) |
fb409745 | 3379 | { |
f81353e4 EZ |
3380 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3381 | ||
283150cd EZ |
3382 | if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE) |
3383 | { | |
3384 | /* It is a no-op. */ | |
3385 | memcpy (to, from, REGISTER_RAW_SIZE (regnum)); | |
3386 | return; | |
3387 | } | |
3388 | ||
3389 | if ((regnum >= tdep->DR0_REGNUM | |
3390 | && regnum <= tdep->DR_LAST_REGNUM) | |
3391 | || (regnum >= tdep->DR0_C_REGNUM | |
3392 | && regnum <= tdep->DR_LAST_C_REGNUM)) | |
fb409745 EZ |
3393 | { |
3394 | DOUBLEST val = extract_floating (from, TYPE_LENGTH(type)); | |
3395 | floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to); | |
3396 | } | |
3397 | else | |
3398 | error("sh_register_convert_to_raw called with non DR register number"); | |
3399 | } | |
3400 | ||
53116e27 | 3401 | void |
d8124050 AC |
3402 | sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
3403 | int reg_nr, void *buffer) | |
53116e27 EZ |
3404 | { |
3405 | int base_regnum, portion; | |
7bd872fe | 3406 | char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE); |
d8124050 | 3407 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
53116e27 | 3408 | |
7bd872fe EZ |
3409 | if (reg_nr >= tdep->DR0_REGNUM |
3410 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
3411 | { | |
3412 | base_regnum = dr_reg_base_num (reg_nr); | |
3413 | ||
3414 | /* Build the value in the provided buffer. */ | |
3415 | /* Read the real regs for which this one is an alias. */ | |
3416 | for (portion = 0; portion < 2; portion++) | |
d8124050 | 3417 | regcache_raw_read (regcache, base_regnum + portion, |
0818c12a AC |
3418 | (temp_buffer |
3419 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
7bd872fe EZ |
3420 | /* We must pay attention to the endiannes. */ |
3421 | sh_sh4_register_convert_to_virtual (reg_nr, | |
3422 | REGISTER_VIRTUAL_TYPE (reg_nr), | |
3423 | temp_buffer, buffer); | |
3424 | } | |
3425 | else if (reg_nr >= tdep->FV0_REGNUM | |
3426 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
53116e27 | 3427 | { |
7bd872fe EZ |
3428 | base_regnum = fv_reg_base_num (reg_nr); |
3429 | ||
3430 | /* Read the real regs for which this one is an alias. */ | |
3431 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
3432 | regcache_raw_read (regcache, base_regnum + portion, |
3433 | ((char *) buffer | |
3434 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
53116e27 EZ |
3435 | } |
3436 | } | |
3437 | ||
7bd872fe | 3438 | static void |
d8124050 AC |
3439 | sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
3440 | int reg_nr, void *buffer) | |
283150cd EZ |
3441 | { |
3442 | int base_regnum; | |
3443 | int portion; | |
3444 | int offset = 0; | |
3445 | char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE); | |
d8124050 | 3446 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
283150cd EZ |
3447 | |
3448 | if (reg_nr >= tdep->DR0_REGNUM | |
3449 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
3450 | { | |
3451 | base_regnum = dr_reg_base_num (reg_nr); | |
3452 | ||
3453 | /* Build the value in the provided buffer. */ | |
3454 | /* DR regs are double precision registers obtained by | |
3455 | concatenating 2 single precision floating point registers. */ | |
3456 | for (portion = 0; portion < 2; portion++) | |
d8124050 | 3457 | regcache_raw_read (regcache, base_regnum + portion, |
0818c12a AC |
3458 | (temp_buffer |
3459 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
283150cd EZ |
3460 | |
3461 | /* We must pay attention to the endiannes. */ | |
3462 | sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr), | |
3463 | temp_buffer, buffer); | |
3464 | ||
3465 | } | |
3466 | ||
3467 | else if (reg_nr >= tdep->FPP0_REGNUM | |
3468 | && reg_nr <= tdep->FPP_LAST_REGNUM) | |
3469 | { | |
3470 | base_regnum = fpp_reg_base_num (reg_nr); | |
3471 | ||
3472 | /* Build the value in the provided buffer. */ | |
3473 | /* FPP regs are pairs of single precision registers obtained by | |
3474 | concatenating 2 single precision floating point registers. */ | |
3475 | for (portion = 0; portion < 2; portion++) | |
d8124050 AC |
3476 | regcache_raw_read (regcache, base_regnum + portion, |
3477 | ((char *) buffer | |
0818c12a | 3478 | + REGISTER_RAW_SIZE (base_regnum) * portion)); |
283150cd EZ |
3479 | } |
3480 | ||
3481 | else if (reg_nr >= tdep->FV0_REGNUM | |
3482 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
3483 | { | |
3484 | base_regnum = fv_reg_base_num (reg_nr); | |
3485 | ||
3486 | /* Build the value in the provided buffer. */ | |
3487 | /* FV regs are vectors of single precision registers obtained by | |
3488 | concatenating 4 single precision floating point registers. */ | |
3489 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
3490 | regcache_raw_read (regcache, base_regnum + portion, |
3491 | ((char *) buffer | |
0818c12a | 3492 | + REGISTER_RAW_SIZE (base_regnum) * portion)); |
283150cd EZ |
3493 | } |
3494 | ||
3495 | /* sh compact pseudo registers. 1-to-1 with a shmedia register */ | |
3496 | else if (reg_nr >= tdep->R0_C_REGNUM | |
3497 | && reg_nr <= tdep->T_C_REGNUM) | |
3498 | { | |
3499 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3500 | ||
3501 | /* Build the value in the provided buffer. */ | |
d8124050 | 3502 | regcache_raw_read (regcache, base_regnum, temp_buffer); |
283150cd EZ |
3503 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
3504 | offset = 4; | |
3505 | memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/ | |
3506 | } | |
3507 | ||
3508 | else if (reg_nr >= tdep->FP0_C_REGNUM | |
3509 | && reg_nr <= tdep->FP_LAST_C_REGNUM) | |
3510 | { | |
3511 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3512 | ||
3513 | /* Build the value in the provided buffer. */ | |
3514 | /* Floating point registers map 1-1 to the media fp regs, | |
3515 | they have the same size and endienness. */ | |
d8124050 | 3516 | regcache_raw_read (regcache, base_regnum, buffer); |
283150cd EZ |
3517 | } |
3518 | ||
3519 | else if (reg_nr >= tdep->DR0_C_REGNUM | |
3520 | && reg_nr <= tdep->DR_LAST_C_REGNUM) | |
3521 | { | |
3522 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3523 | ||
3524 | /* DR_C regs are double precision registers obtained by | |
3525 | concatenating 2 single precision floating point registers. */ | |
3526 | for (portion = 0; portion < 2; portion++) | |
d8124050 | 3527 | regcache_raw_read (regcache, base_regnum + portion, |
0818c12a AC |
3528 | (temp_buffer |
3529 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
283150cd EZ |
3530 | |
3531 | /* We must pay attention to the endiannes. */ | |
3532 | sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr), | |
3533 | temp_buffer, buffer); | |
3534 | } | |
3535 | ||
3536 | else if (reg_nr >= tdep->FV0_C_REGNUM | |
3537 | && reg_nr <= tdep->FV_LAST_C_REGNUM) | |
3538 | { | |
3539 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3540 | ||
3541 | /* Build the value in the provided buffer. */ | |
3542 | /* FV_C regs are vectors of single precision registers obtained by | |
3543 | concatenating 4 single precision floating point registers. */ | |
3544 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
3545 | regcache_raw_read (regcache, base_regnum + portion, |
3546 | ((char *) buffer | |
0818c12a | 3547 | + REGISTER_RAW_SIZE (base_regnum) * portion)); |
283150cd EZ |
3548 | } |
3549 | ||
3550 | else if (reg_nr == tdep->FPSCR_C_REGNUM) | |
3551 | { | |
3552 | int fpscr_base_regnum; | |
3553 | int sr_base_regnum; | |
3554 | unsigned int fpscr_value; | |
3555 | unsigned int sr_value; | |
3556 | unsigned int fpscr_c_value; | |
3557 | unsigned int fpscr_c_part1_value; | |
3558 | unsigned int fpscr_c_part2_value; | |
3559 | ||
3560 | fpscr_base_regnum = tdep->FPSCR_REGNUM; | |
3561 | sr_base_regnum = tdep->SR_REGNUM; | |
3562 | ||
3563 | /* Build the value in the provided buffer. */ | |
3564 | /* FPSCR_C is a very weird register that contains sparse bits | |
3565 | from the FPSCR and the SR architectural registers. | |
3566 | Specifically: */ | |
3567 | /* *INDENT-OFF* */ | |
3568 | /* | |
3569 | FPSRC_C bit | |
3570 | 0 Bit 0 of FPSCR | |
3571 | 1 reserved | |
3572 | 2-17 Bit 2-18 of FPSCR | |
3573 | 18-20 Bits 12,13,14 of SR | |
3574 | 21-31 reserved | |
3575 | */ | |
3576 | /* *INDENT-ON* */ | |
3577 | /* Get FPSCR into a local buffer */ | |
d8124050 | 3578 | regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer); |
283150cd EZ |
3579 | /* Get value as an int. */ |
3580 | fpscr_value = extract_unsigned_integer (temp_buffer, 4); | |
3581 | /* Get SR into a local buffer */ | |
d8124050 | 3582 | regcache_raw_read (regcache, sr_base_regnum, temp_buffer); |
283150cd EZ |
3583 | /* Get value as an int. */ |
3584 | sr_value = extract_unsigned_integer (temp_buffer, 4); | |
3585 | /* Build the new value. */ | |
3586 | fpscr_c_part1_value = fpscr_value & 0x3fffd; | |
3587 | fpscr_c_part2_value = (sr_value & 0x7000) << 6; | |
3588 | fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value; | |
3589 | /* Store that in out buffer!!! */ | |
3590 | store_unsigned_integer (buffer, 4, fpscr_c_value); | |
3591 | /* FIXME There is surely an endianness gotcha here. */ | |
3592 | } | |
3593 | ||
3594 | else if (reg_nr == tdep->FPUL_C_REGNUM) | |
3595 | { | |
3596 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3597 | ||
3598 | /* FPUL_C register is floating point register 32, | |
3599 | same size, same endianness. */ | |
d8124050 | 3600 | regcache_raw_read (regcache, base_regnum, buffer); |
283150cd EZ |
3601 | } |
3602 | } | |
3603 | ||
53116e27 | 3604 | void |
d8124050 AC |
3605 | sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
3606 | int reg_nr, const void *buffer) | |
53116e27 EZ |
3607 | { |
3608 | int base_regnum, portion; | |
7bd872fe | 3609 | char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE); |
d8124050 | 3610 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
53116e27 | 3611 | |
f81353e4 EZ |
3612 | if (reg_nr >= tdep->DR0_REGNUM |
3613 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
53116e27 EZ |
3614 | { |
3615 | base_regnum = dr_reg_base_num (reg_nr); | |
3616 | ||
7bd872fe EZ |
3617 | /* We must pay attention to the endiannes. */ |
3618 | sh_sh4_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr, | |
3619 | buffer, temp_buffer); | |
3620 | ||
53116e27 EZ |
3621 | /* Write the real regs for which this one is an alias. */ |
3622 | for (portion = 0; portion < 2; portion++) | |
d8124050 | 3623 | regcache_raw_write (regcache, base_regnum + portion, |
0818c12a AC |
3624 | (temp_buffer |
3625 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
53116e27 | 3626 | } |
f81353e4 EZ |
3627 | else if (reg_nr >= tdep->FV0_REGNUM |
3628 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
53116e27 EZ |
3629 | { |
3630 | base_regnum = fv_reg_base_num (reg_nr); | |
3631 | ||
3632 | /* Write the real regs for which this one is an alias. */ | |
3633 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
3634 | regcache_raw_write (regcache, base_regnum + portion, |
3635 | ((char *) buffer | |
0818c12a | 3636 | + REGISTER_RAW_SIZE (base_regnum) * portion)); |
53116e27 EZ |
3637 | } |
3638 | } | |
3639 | ||
283150cd | 3640 | void |
d8124050 AC |
3641 | sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
3642 | int reg_nr, const void *buffer) | |
283150cd EZ |
3643 | { |
3644 | int base_regnum, portion; | |
3645 | int offset; | |
3646 | char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE); | |
d8124050 | 3647 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
283150cd EZ |
3648 | |
3649 | if (reg_nr >= tdep->DR0_REGNUM | |
3650 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
3651 | { | |
3652 | base_regnum = dr_reg_base_num (reg_nr); | |
3653 | /* We must pay attention to the endiannes. */ | |
3654 | sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr, | |
3655 | buffer, temp_buffer); | |
3656 | ||
3657 | ||
3658 | /* Write the real regs for which this one is an alias. */ | |
3659 | for (portion = 0; portion < 2; portion++) | |
d8124050 | 3660 | regcache_raw_write (regcache, base_regnum + portion, |
0818c12a AC |
3661 | (temp_buffer |
3662 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
283150cd EZ |
3663 | } |
3664 | ||
3665 | else if (reg_nr >= tdep->FPP0_REGNUM | |
3666 | && reg_nr <= tdep->FPP_LAST_REGNUM) | |
3667 | { | |
3668 | base_regnum = fpp_reg_base_num (reg_nr); | |
3669 | ||
3670 | /* Write the real regs for which this one is an alias. */ | |
3671 | for (portion = 0; portion < 2; portion++) | |
d8124050 AC |
3672 | regcache_raw_write (regcache, base_regnum + portion, |
3673 | ((char *) buffer | |
0818c12a | 3674 | + REGISTER_RAW_SIZE (base_regnum) * portion)); |
283150cd EZ |
3675 | } |
3676 | ||
3677 | else if (reg_nr >= tdep->FV0_REGNUM | |
3678 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
3679 | { | |
3680 | base_regnum = fv_reg_base_num (reg_nr); | |
3681 | ||
3682 | /* Write the real regs for which this one is an alias. */ | |
3683 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
3684 | regcache_raw_write (regcache, base_regnum + portion, |
3685 | ((char *) buffer | |
0818c12a | 3686 | + REGISTER_RAW_SIZE (base_regnum) * portion)); |
283150cd EZ |
3687 | } |
3688 | ||
3689 | /* sh compact general pseudo registers. 1-to-1 with a shmedia | |
3690 | register but only 4 bytes of it. */ | |
3691 | else if (reg_nr >= tdep->R0_C_REGNUM | |
3692 | && reg_nr <= tdep->T_C_REGNUM) | |
3693 | { | |
3694 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3695 | /* reg_nr is 32 bit here, and base_regnum is 64 bits. */ | |
3696 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3697 | offset = 4; | |
3698 | else | |
3699 | offset = 0; | |
3700 | /* Let's read the value of the base register into a temporary | |
3701 | buffer, so that overwriting the last four bytes with the new | |
3702 | value of the pseudo will leave the upper 4 bytes unchanged. */ | |
d8124050 | 3703 | regcache_raw_read (regcache, base_regnum, temp_buffer); |
283150cd EZ |
3704 | /* Write as an 8 byte quantity */ |
3705 | memcpy (temp_buffer + offset, buffer, 4); | |
d8124050 | 3706 | regcache_raw_write (regcache, base_regnum, temp_buffer); |
283150cd EZ |
3707 | } |
3708 | ||
3709 | /* sh floating point compact pseudo registers. 1-to-1 with a shmedia | |
3710 | registers. Both are 4 bytes. */ | |
3711 | else if (reg_nr >= tdep->FP0_C_REGNUM | |
3712 | && reg_nr <= tdep->FP_LAST_C_REGNUM) | |
3713 | { | |
3714 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
d8124050 | 3715 | regcache_raw_write (regcache, base_regnum, buffer); |
283150cd EZ |
3716 | } |
3717 | ||
3718 | else if (reg_nr >= tdep->DR0_C_REGNUM | |
3719 | && reg_nr <= tdep->DR_LAST_C_REGNUM) | |
3720 | { | |
3721 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3722 | for (portion = 0; portion < 2; portion++) | |
3723 | { | |
3724 | /* We must pay attention to the endiannes. */ | |
3725 | sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr, | |
3726 | buffer, temp_buffer); | |
3727 | ||
d8124050 | 3728 | regcache_raw_write (regcache, base_regnum + portion, |
0818c12a AC |
3729 | (temp_buffer |
3730 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
283150cd EZ |
3731 | } |
3732 | } | |
3733 | ||
3734 | else if (reg_nr >= tdep->FV0_C_REGNUM | |
3735 | && reg_nr <= tdep->FV_LAST_C_REGNUM) | |
3736 | { | |
3737 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3738 | ||
3739 | for (portion = 0; portion < 4; portion++) | |
3740 | { | |
d8124050 AC |
3741 | regcache_raw_write (regcache, base_regnum + portion, |
3742 | ((char *) buffer | |
0818c12a | 3743 | + REGISTER_RAW_SIZE (base_regnum) * portion)); |
283150cd EZ |
3744 | } |
3745 | } | |
3746 | ||
3747 | else if (reg_nr == tdep->FPSCR_C_REGNUM) | |
3748 | { | |
3749 | int fpscr_base_regnum; | |
3750 | int sr_base_regnum; | |
3751 | unsigned int fpscr_value; | |
3752 | unsigned int sr_value; | |
3753 | unsigned int old_fpscr_value; | |
3754 | unsigned int old_sr_value; | |
3755 | unsigned int fpscr_c_value; | |
3756 | unsigned int fpscr_mask; | |
3757 | unsigned int sr_mask; | |
3758 | ||
3759 | fpscr_base_regnum = tdep->FPSCR_REGNUM; | |
3760 | sr_base_regnum = tdep->SR_REGNUM; | |
3761 | ||
3762 | /* FPSCR_C is a very weird register that contains sparse bits | |
3763 | from the FPSCR and the SR architectural registers. | |
3764 | Specifically: */ | |
3765 | /* *INDENT-OFF* */ | |
3766 | /* | |
3767 | FPSRC_C bit | |
3768 | 0 Bit 0 of FPSCR | |
3769 | 1 reserved | |
3770 | 2-17 Bit 2-18 of FPSCR | |
3771 | 18-20 Bits 12,13,14 of SR | |
3772 | 21-31 reserved | |
3773 | */ | |
3774 | /* *INDENT-ON* */ | |
3775 | /* Get value as an int. */ | |
3776 | fpscr_c_value = extract_unsigned_integer (buffer, 4); | |
3777 | ||
3778 | /* Build the new values. */ | |
3779 | fpscr_mask = 0x0003fffd; | |
3780 | sr_mask = 0x001c0000; | |
3781 | ||
3782 | fpscr_value = fpscr_c_value & fpscr_mask; | |
3783 | sr_value = (fpscr_value & sr_mask) >> 6; | |
3784 | ||
d8124050 | 3785 | regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer); |
283150cd EZ |
3786 | old_fpscr_value = extract_unsigned_integer (temp_buffer, 4); |
3787 | old_fpscr_value &= 0xfffc0002; | |
3788 | fpscr_value |= old_fpscr_value; | |
3789 | store_unsigned_integer (temp_buffer, 4, fpscr_value); | |
d8124050 | 3790 | regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer); |
283150cd | 3791 | |
d8124050 | 3792 | regcache_raw_read (regcache, sr_base_regnum, temp_buffer); |
283150cd EZ |
3793 | old_sr_value = extract_unsigned_integer (temp_buffer, 4); |
3794 | old_sr_value &= 0xffff8fff; | |
3795 | sr_value |= old_sr_value; | |
3796 | store_unsigned_integer (temp_buffer, 4, sr_value); | |
d8124050 | 3797 | regcache_raw_write (regcache, sr_base_regnum, temp_buffer); |
283150cd EZ |
3798 | } |
3799 | ||
3800 | else if (reg_nr == tdep->FPUL_C_REGNUM) | |
3801 | { | |
3802 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
d8124050 | 3803 | regcache_raw_write (regcache, base_regnum, buffer); |
283150cd EZ |
3804 | } |
3805 | } | |
3806 | ||
3bbfbb92 | 3807 | /* Floating point vector of 4 float registers. */ |
53116e27 EZ |
3808 | static void |
3809 | do_fv_register_info (int fv_regnum) | |
3810 | { | |
3811 | int first_fp_reg_num = fv_reg_base_num (fv_regnum); | |
3812 | printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", | |
3813 | fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM, | |
3814 | (int) read_register (first_fp_reg_num), | |
3815 | (int) read_register (first_fp_reg_num + 1), | |
3816 | (int) read_register (first_fp_reg_num + 2), | |
3817 | (int) read_register (first_fp_reg_num + 3)); | |
3818 | } | |
3819 | ||
283150cd EZ |
3820 | /* Floating point vector of 4 float registers, compact mode. */ |
3821 | static void | |
3822 | do_fv_c_register_info (int fv_regnum) | |
3823 | { | |
3824 | int first_fp_reg_num = sh64_compact_reg_base_num (fv_regnum); | |
3825 | printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", | |
3826 | fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_C_REGNUM, | |
3827 | (int) read_register (first_fp_reg_num), | |
3828 | (int) read_register (first_fp_reg_num + 1), | |
3829 | (int) read_register (first_fp_reg_num + 2), | |
3830 | (int) read_register (first_fp_reg_num + 3)); | |
3831 | } | |
3832 | ||
3833 | /* Pairs of single regs. The DR are instead double precision | |
3834 | registers. */ | |
3835 | static void | |
3836 | do_fpp_register_info (int fpp_regnum) | |
3837 | { | |
3838 | int first_fp_reg_num = fpp_reg_base_num (fpp_regnum); | |
3839 | ||
3840 | printf_filtered ("fpp%d\t0x%08x\t0x%08x\n", | |
3841 | fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM, | |
3842 | (int) read_register (first_fp_reg_num), | |
3843 | (int) read_register (first_fp_reg_num + 1)); | |
3844 | } | |
3845 | ||
3bbfbb92 | 3846 | /* Double precision registers. */ |
53116e27 EZ |
3847 | static void |
3848 | do_dr_register_info (int dr_regnum) | |
3849 | { | |
3850 | int first_fp_reg_num = dr_reg_base_num (dr_regnum); | |
3851 | ||
3852 | printf_filtered ("dr%d\t0x%08x%08x\n", | |
3853 | dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM, | |
3854 | (int) read_register (first_fp_reg_num), | |
3855 | (int) read_register (first_fp_reg_num + 1)); | |
3856 | } | |
3857 | ||
283150cd EZ |
3858 | /* Double precision registers, compact mode. */ |
3859 | static void | |
3860 | do_dr_c_register_info (int dr_regnum) | |
3861 | { | |
3862 | int first_fp_reg_num = sh64_compact_reg_base_num (dr_regnum); | |
3863 | ||
3864 | printf_filtered ("dr%d_c\t0x%08x%08x\n", | |
3865 | dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_C_REGNUM, | |
3866 | (int) read_register (first_fp_reg_num), | |
3867 | (int) read_register (first_fp_reg_num +1)); | |
3868 | } | |
3869 | ||
3870 | /* General register in compact mode. */ | |
3871 | static void | |
3872 | do_r_c_register_info (int r_c_regnum) | |
3873 | { | |
3874 | int regnum = sh64_compact_reg_base_num (r_c_regnum); | |
3875 | ||
3876 | printf_filtered ("r%d_c\t0x%08x\n", | |
3877 | r_c_regnum - gdbarch_tdep (current_gdbarch)->R0_C_REGNUM, | |
3878 | /*FIXME!!!*/ (int) read_register (regnum)); | |
3879 | } | |
3880 | ||
3881 | /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE | |
3882 | shmedia REGISTERS. */ | |
3883 | /* Control registers, compact mode. */ | |
3884 | static void | |
3885 | do_cr_c_register_info (int cr_c_regnum) | |
3886 | { | |
3887 | switch (cr_c_regnum) | |
3888 | { | |
3889 | case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
3890 | break; | |
3891 | case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
3892 | break; | |
3893 | case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
3894 | break; | |
3895 | case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
3896 | break; | |
3897 | case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
3898 | break; | |
3899 | case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
3900 | break; | |
3901 | case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
3902 | break; | |
3903 | case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum)); | |
3904 | break; | |
3905 | } | |
3906 | } | |
3907 | ||
53116e27 EZ |
3908 | static void |
3909 | sh_do_pseudo_register (int regnum) | |
3910 | { | |
f81353e4 EZ |
3911 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3912 | ||
53116e27 | 3913 | if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS) |
8e65ff28 AC |
3914 | internal_error (__FILE__, __LINE__, |
3915 | "Invalid pseudo register number %d\n", regnum); | |
f81353e4 EZ |
3916 | else if (regnum >= tdep->DR0_REGNUM |
3917 | && regnum < tdep->DR_LAST_REGNUM) | |
53116e27 | 3918 | do_dr_register_info (regnum); |
f81353e4 EZ |
3919 | else if (regnum >= tdep->FV0_REGNUM |
3920 | && regnum <= tdep->FV_LAST_REGNUM) | |
53116e27 EZ |
3921 | do_fv_register_info (regnum); |
3922 | } | |
3923 | ||
53116e27 EZ |
3924 | static void |
3925 | sh_do_fp_register (int regnum) | |
3926 | { /* do values for FP (float) regs */ | |
3927 | char *raw_buffer; | |
3928 | double flt; /* double extracted from raw hex data */ | |
3929 | int inv; | |
3930 | int j; | |
3931 | ||
3932 | /* Allocate space for the float. */ | |
3933 | raw_buffer = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM)); | |
3934 | ||
3935 | /* Get the data in raw format. */ | |
6e7f8b9c | 3936 | if (!frame_register_read (deprecated_selected_frame, regnum, raw_buffer)) |
53116e27 EZ |
3937 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
3938 | ||
3939 | /* Get the register as a number */ | |
3940 | flt = unpack_double (builtin_type_float, raw_buffer, &inv); | |
3941 | ||
3942 | /* Print the name and some spaces. */ | |
3943 | fputs_filtered (REGISTER_NAME (regnum), gdb_stdout); | |
3944 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout); | |
3945 | ||
3946 | /* Print the value. */ | |
93d56215 AC |
3947 | if (inv) |
3948 | printf_filtered ("<invalid float>"); | |
3949 | else | |
3950 | printf_filtered ("%-10.9g", flt); | |
53116e27 EZ |
3951 | |
3952 | /* Print the fp register as hex. */ | |
3953 | printf_filtered ("\t(raw 0x"); | |
3954 | for (j = 0; j < REGISTER_RAW_SIZE (regnum); j++) | |
3955 | { | |
d7449b42 | 3956 | register int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j |
53116e27 EZ |
3957 | : REGISTER_RAW_SIZE (regnum) - 1 - j; |
3958 | printf_filtered ("%02x", (unsigned char) raw_buffer[idx]); | |
3959 | } | |
3960 | printf_filtered (")"); | |
3961 | printf_filtered ("\n"); | |
3962 | } | |
3963 | ||
283150cd EZ |
3964 | static void |
3965 | sh64_do_pseudo_register (int regnum) | |
3966 | { | |
3967 | /* All the sh64-compact mode registers are pseudo registers. */ | |
3968 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3969 | ||
3970 | if (regnum < NUM_REGS | |
3971 | || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT) | |
3972 | internal_error (__FILE__, __LINE__, | |
3973 | "Invalid pseudo register number %d\n", regnum); | |
3974 | ||
3975 | else if ((regnum >= tdep->DR0_REGNUM | |
3976 | && regnum <= tdep->DR_LAST_REGNUM)) | |
3977 | do_dr_register_info (regnum); | |
3978 | ||
3979 | else if ((regnum >= tdep->DR0_C_REGNUM | |
3980 | && regnum <= tdep->DR_LAST_C_REGNUM)) | |
3981 | do_dr_c_register_info (regnum); | |
3982 | ||
3983 | else if ((regnum >= tdep->FV0_REGNUM | |
3984 | && regnum <= tdep->FV_LAST_REGNUM)) | |
3985 | do_fv_register_info (regnum); | |
3986 | ||
3987 | else if ((regnum >= tdep->FV0_C_REGNUM | |
3988 | && regnum <= tdep->FV_LAST_C_REGNUM)) | |
3989 | do_fv_c_register_info (regnum); | |
3990 | ||
3991 | else if (regnum >= tdep->FPP0_REGNUM | |
3992 | && regnum <= tdep->FPP_LAST_REGNUM) | |
3993 | do_fpp_register_info (regnum); | |
3994 | ||
3995 | else if (regnum >= tdep->R0_C_REGNUM | |
3996 | && regnum <= tdep->R_LAST_C_REGNUM) | |
3997 | do_r_c_register_info (regnum); /* FIXME, this function will not print the right format */ | |
3998 | ||
3999 | else if (regnum >= tdep->FP0_C_REGNUM | |
4000 | && regnum <= tdep->FP_LAST_C_REGNUM) | |
4001 | sh_do_fp_register (regnum); /* this should work also for pseudoregs */ | |
4002 | ||
4003 | else if (regnum >= tdep->PC_C_REGNUM | |
4004 | && regnum <= tdep->FPUL_C_REGNUM) | |
4005 | do_cr_c_register_info (regnum); | |
4006 | ||
4007 | } | |
4008 | ||
53116e27 EZ |
4009 | static void |
4010 | sh_do_register (int regnum) | |
4011 | { | |
4012 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; | |
4013 | ||
4014 | fputs_filtered (REGISTER_NAME (regnum), gdb_stdout); | |
4015 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout); | |
4016 | ||
4017 | /* Get the data in raw format. */ | |
6e7f8b9c | 4018 | if (!frame_register_read (deprecated_selected_frame, regnum, raw_buffer)) |
53116e27 EZ |
4019 | printf_filtered ("*value not available*\n"); |
4020 | ||
4021 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0, | |
4022 | gdb_stdout, 'x', 1, 0, Val_pretty_default); | |
4023 | printf_filtered ("\t"); | |
4024 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0, | |
4025 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
4026 | printf_filtered ("\n"); | |
4027 | } | |
4028 | ||
4029 | static void | |
4030 | sh_print_register (int regnum) | |
4031 | { | |
4032 | if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS) | |
8e65ff28 AC |
4033 | internal_error (__FILE__, __LINE__, |
4034 | "Invalid register number %d\n", regnum); | |
53116e27 | 4035 | |
e30839fe | 4036 | else if (regnum >= 0 && regnum < NUM_REGS) |
53116e27 EZ |
4037 | { |
4038 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) | |
4039 | sh_do_fp_register (regnum); /* FP regs */ | |
4040 | else | |
4041 | sh_do_register (regnum); /* All other regs */ | |
4042 | } | |
4043 | ||
4044 | else if (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
3bbfbb92 | 4045 | do_pseudo_register (regnum); |
53116e27 EZ |
4046 | } |
4047 | ||
4048 | void | |
4049 | sh_do_registers_info (int regnum, int fpregs) | |
4050 | { | |
4051 | if (regnum != -1) /* do one specified register */ | |
4052 | { | |
4053 | if (*(REGISTER_NAME (regnum)) == '\0') | |
4054 | error ("Not a valid register for the current processor type"); | |
4055 | ||
4056 | sh_print_register (regnum); | |
4057 | } | |
4058 | else | |
4059 | /* do all (or most) registers */ | |
4060 | { | |
4061 | regnum = 0; | |
4062 | while (regnum < NUM_REGS) | |
4063 | { | |
4064 | /* If the register name is empty, it is undefined for this | |
4065 | processor, so don't display anything. */ | |
4066 | if (REGISTER_NAME (regnum) == NULL | |
4067 | || *(REGISTER_NAME (regnum)) == '\0') | |
4068 | { | |
4069 | regnum++; | |
4070 | continue; | |
4071 | } | |
4072 | ||
4073 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) | |
4074 | { | |
4075 | if (fpregs) | |
4076 | { | |
4077 | /* true for "INFO ALL-REGISTERS" command */ | |
4078 | sh_do_fp_register (regnum); /* FP regs */ | |
4079 | regnum ++; | |
4080 | } | |
4081 | else | |
e6c42fda | 4082 | regnum += (gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */ |
53116e27 EZ |
4083 | } |
4084 | else | |
4085 | { | |
4086 | sh_do_register (regnum); /* All other regs */ | |
4087 | regnum++; | |
4088 | } | |
4089 | } | |
4090 | ||
4091 | if (fpregs) | |
4092 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
4093 | { | |
3bbfbb92 | 4094 | do_pseudo_register (regnum); |
53116e27 EZ |
4095 | regnum++; |
4096 | } | |
4097 | } | |
4098 | } | |
4099 | ||
283150cd EZ |
4100 | void |
4101 | sh_compact_do_registers_info (int regnum, int fpregs) | |
4102 | { | |
4103 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
4104 | if (regnum != -1) /* do one specified register */ | |
4105 | { | |
4106 | if (*(REGISTER_NAME (regnum)) == '\0') | |
4107 | error ("Not a valid register for the current processor type"); | |
4108 | ||
4109 | if (regnum >= 0 && regnum < tdep->R0_C_REGNUM) | |
4110 | error ("Not a valid register for the current processor mode."); | |
4111 | ||
4112 | sh_print_register (regnum); | |
4113 | } | |
4114 | else | |
4115 | /* do all compact registers */ | |
4116 | { | |
4117 | regnum = tdep->R0_C_REGNUM; | |
4118 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
4119 | { | |
4120 | do_pseudo_register (regnum); | |
4121 | regnum++; | |
4122 | } | |
4123 | } | |
4124 | } | |
4125 | ||
4126 | void | |
4127 | sh64_do_registers_info (int regnum, int fpregs) | |
4128 | { | |
50abf9e5 | 4129 | if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame))) |
283150cd EZ |
4130 | sh_do_registers_info (regnum, fpregs); |
4131 | else | |
4132 | sh_compact_do_registers_info (regnum, fpregs); | |
4133 | } | |
4134 | ||
1a8629c7 MS |
4135 | #ifdef SVR4_SHARED_LIBS |
4136 | ||
4137 | /* Fetch (and possibly build) an appropriate link_map_offsets structure | |
4138 | for native i386 linux targets using the struct offsets defined in | |
4139 | link.h (but without actual reference to that file). | |
4140 | ||
4141 | This makes it possible to access i386-linux shared libraries from | |
4142 | a gdb that was not built on an i386-linux host (for cross debugging). | |
4143 | */ | |
4144 | ||
4145 | struct link_map_offsets * | |
4146 | sh_linux_svr4_fetch_link_map_offsets (void) | |
4147 | { | |
4148 | static struct link_map_offsets lmo; | |
4149 | static struct link_map_offsets *lmp = 0; | |
4150 | ||
4151 | if (lmp == 0) | |
4152 | { | |
4153 | lmp = &lmo; | |
4154 | ||
4155 | lmo.r_debug_size = 8; /* 20 not actual size but all we need */ | |
4156 | ||
4157 | lmo.r_map_offset = 4; | |
4158 | lmo.r_map_size = 4; | |
4159 | ||
4160 | lmo.link_map_size = 20; /* 552 not actual size but all we need */ | |
4161 | ||
4162 | lmo.l_addr_offset = 0; | |
4163 | lmo.l_addr_size = 4; | |
4164 | ||
4165 | lmo.l_name_offset = 4; | |
4166 | lmo.l_name_size = 4; | |
4167 | ||
4168 | lmo.l_next_offset = 12; | |
4169 | lmo.l_next_size = 4; | |
4170 | ||
4171 | lmo.l_prev_offset = 16; | |
4172 | lmo.l_prev_size = 4; | |
4173 | } | |
4174 | ||
4175 | return lmp; | |
4176 | } | |
4177 | #endif /* SVR4_SHARED_LIBS */ | |
4178 | ||
2f14585c JR |
4179 | \f |
4180 | enum | |
4181 | { | |
4182 | DSP_DSR_REGNUM = 24, | |
4183 | DSP_A0G_REGNUM, | |
4184 | DSP_A0_REGNUM, | |
4185 | DSP_A1G_REGNUM, | |
4186 | DSP_A1_REGNUM, | |
4187 | DSP_M0_REGNUM, | |
4188 | DSP_M1_REGNUM, | |
4189 | DSP_X0_REGNUM, | |
4190 | DSP_X1_REGNUM, | |
4191 | DSP_Y0_REGNUM, | |
4192 | DSP_Y1_REGNUM, | |
4193 | ||
4194 | DSP_MOD_REGNUM = 40, | |
4195 | ||
4196 | DSP_RS_REGNUM = 43, | |
4197 | DSP_RE_REGNUM, | |
4198 | ||
4199 | DSP_R0_BANK_REGNUM = 51, | |
4200 | DSP_R7_BANK_REGNUM = DSP_R0_BANK_REGNUM + 7 | |
4201 | }; | |
4202 | ||
4203 | static int | |
4204 | sh_dsp_register_sim_regno (int nr) | |
4205 | { | |
4206 | if (legacy_register_sim_regno (nr) < 0) | |
4207 | return legacy_register_sim_regno (nr); | |
4208 | if (nr >= DSP_DSR_REGNUM && nr < DSP_Y1_REGNUM) | |
4209 | return nr - DSP_DSR_REGNUM + SIM_SH_DSR_REGNUM; | |
4210 | if (nr == DSP_MOD_REGNUM) | |
4211 | return SIM_SH_MOD_REGNUM; | |
4212 | if (nr == DSP_RS_REGNUM) | |
4213 | return SIM_SH_RS_REGNUM; | |
4214 | if (nr == DSP_RE_REGNUM) | |
4215 | return SIM_SH_RE_REGNUM; | |
4216 | if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM) | |
4217 | return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM; | |
4218 | return nr; | |
4219 | } | |
d658f924 | 4220 | \f |
cc17453a EZ |
4221 | static gdbarch_init_ftype sh_gdbarch_init; |
4222 | ||
4223 | static struct gdbarch * | |
fba45db2 | 4224 | sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
cc17453a EZ |
4225 | { |
4226 | static LONGEST sh_call_dummy_words[] = {0}; | |
4227 | struct gdbarch *gdbarch; | |
4228 | struct gdbarch_tdep *tdep; | |
4229 | gdbarch_register_name_ftype *sh_register_name; | |
ebba8386 | 4230 | gdbarch_deprecated_store_return_value_ftype *sh_store_return_value; |
cc17453a | 4231 | gdbarch_register_virtual_type_ftype *sh_register_virtual_type; |
d658f924 | 4232 | |
4be87837 DJ |
4233 | /* If there is already a candidate, use it. */ |
4234 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
4235 | if (arches != NULL) | |
4236 | return arches->gdbarch; | |
cc17453a EZ |
4237 | |
4238 | /* None found, create a new architecture from the information | |
4239 | provided. */ | |
4240 | tdep = XMALLOC (struct gdbarch_tdep); | |
4241 | gdbarch = gdbarch_alloc (&info, tdep); | |
4242 | ||
a5afb99f AC |
4243 | /* NOTE: cagney/2002-12-06: This can be deleted when this arch is |
4244 | ready to unwind the PC first (see frame.c:get_prev_frame()). */ | |
4245 | set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_default); | |
4246 | ||
cc17453a EZ |
4247 | /* Initialize the register numbers that are not common to all the |
4248 | variants to -1, if necessary thse will be overwritten in the case | |
4249 | statement below. */ | |
4250 | tdep->FPUL_REGNUM = -1; | |
4251 | tdep->FPSCR_REGNUM = -1; | |
3bbfbb92 | 4252 | tdep->PR_REGNUM = 17; |
c62a7c7b | 4253 | tdep->SR_REGNUM = 22; |
cc17453a | 4254 | tdep->DSR_REGNUM = -1; |
e6c42fda | 4255 | tdep->FP_LAST_REGNUM = -1; |
cc17453a EZ |
4256 | tdep->A0G_REGNUM = -1; |
4257 | tdep->A0_REGNUM = -1; | |
4258 | tdep->A1G_REGNUM = -1; | |
4259 | tdep->A1_REGNUM = -1; | |
4260 | tdep->M0_REGNUM = -1; | |
4261 | tdep->M1_REGNUM = -1; | |
4262 | tdep->X0_REGNUM = -1; | |
4263 | tdep->X1_REGNUM = -1; | |
4264 | tdep->Y0_REGNUM = -1; | |
4265 | tdep->Y1_REGNUM = -1; | |
4266 | tdep->MOD_REGNUM = -1; | |
4267 | tdep->RS_REGNUM = -1; | |
4268 | tdep->RE_REGNUM = -1; | |
4269 | tdep->SSR_REGNUM = -1; | |
4270 | tdep->SPC_REGNUM = -1; | |
53116e27 | 4271 | tdep->DR0_REGNUM = -1; |
e6c42fda | 4272 | tdep->DR_LAST_REGNUM = -1; |
53116e27 | 4273 | tdep->FV0_REGNUM = -1; |
e6c42fda | 4274 | tdep->FV_LAST_REGNUM = -1; |
3bbfbb92 EZ |
4275 | tdep->ARG0_REGNUM = 4; |
4276 | tdep->ARGLAST_REGNUM = 7; | |
4277 | tdep->RETURN_REGNUM = 0; | |
4278 | tdep->FLOAT_ARGLAST_REGNUM = -1; | |
a38d2a54 | 4279 | |
283150cd EZ |
4280 | tdep->sh_abi = SH_ABI_UNKNOWN; |
4281 | ||
cc17453a | 4282 | set_gdbarch_fp0_regnum (gdbarch, -1); |
53116e27 EZ |
4283 | set_gdbarch_num_pseudo_regs (gdbarch, 0); |
4284 | set_gdbarch_max_register_raw_size (gdbarch, 4); | |
4285 | set_gdbarch_max_register_virtual_size (gdbarch, 4); | |
ec920329 | 4286 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
a38d2a54 | 4287 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
88e04cc1 | 4288 | set_gdbarch_num_regs (gdbarch, SH_DEFAULT_NUM_REGS); |
a38d2a54 EZ |
4289 | set_gdbarch_sp_regnum (gdbarch, 15); |
4290 | set_gdbarch_fp_regnum (gdbarch, 14); | |
4291 | set_gdbarch_pc_regnum (gdbarch, 16); | |
4292 | set_gdbarch_register_size (gdbarch, 4); | |
88e04cc1 | 4293 | set_gdbarch_register_bytes (gdbarch, SH_DEFAULT_NUM_REGS * 4); |
903ad3a6 | 4294 | set_gdbarch_deprecated_do_registers_info (gdbarch, sh_do_registers_info); |
eaf90c5d | 4295 | set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc); |
3bbfbb92 | 4296 | set_gdbarch_frame_chain (gdbarch, sh_frame_chain); |
bdcdd535 | 4297 | set_gdbarch_get_saved_register (gdbarch, deprecated_generic_get_saved_register); |
3bbfbb92 | 4298 | set_gdbarch_init_extra_frame_info (gdbarch, sh_init_extra_frame_info); |
26e9b323 | 4299 | set_gdbarch_deprecated_extract_return_value (gdbarch, sh_extract_return_value); |
3bbfbb92 EZ |
4300 | set_gdbarch_push_arguments (gdbarch, sh_push_arguments); |
4301 | set_gdbarch_store_struct_return (gdbarch, sh_store_struct_return); | |
4302 | set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention); | |
26e9b323 | 4303 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh_extract_struct_value_address); |
3bbfbb92 | 4304 | set_gdbarch_pop_frame (gdbarch, sh_pop_frame); |
2bf0cb65 | 4305 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh); |
2f14585c | 4306 | set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); |
3bbfbb92 EZ |
4307 | skip_prologue_hard_way = sh_skip_prologue_hard_way; |
4308 | do_pseudo_register = sh_do_pseudo_register; | |
cc17453a EZ |
4309 | |
4310 | switch (info.bfd_arch_info->mach) | |
8db62801 | 4311 | { |
cc17453a EZ |
4312 | case bfd_mach_sh: |
4313 | sh_register_name = sh_sh_register_name; | |
4314 | sh_show_regs = sh_generic_show_regs; | |
4315 | sh_store_return_value = sh_default_store_return_value; | |
4316 | sh_register_virtual_type = sh_default_register_virtual_type; | |
4317 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
53116e27 EZ |
4318 | set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); |
4319 | set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); | |
4320 | set_gdbarch_register_byte (gdbarch, sh_default_register_byte); | |
cc17453a EZ |
4321 | break; |
4322 | case bfd_mach_sh2: | |
4323 | sh_register_name = sh_sh_register_name; | |
4324 | sh_show_regs = sh_generic_show_regs; | |
4325 | sh_store_return_value = sh_default_store_return_value; | |
4326 | sh_register_virtual_type = sh_default_register_virtual_type; | |
4327 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
53116e27 EZ |
4328 | set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); |
4329 | set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); | |
4330 | set_gdbarch_register_byte (gdbarch, sh_default_register_byte); | |
cc17453a EZ |
4331 | break; |
4332 | case bfd_mach_sh_dsp: | |
4333 | sh_register_name = sh_sh_dsp_register_name; | |
4334 | sh_show_regs = sh_dsp_show_regs; | |
4335 | sh_store_return_value = sh_default_store_return_value; | |
4336 | sh_register_virtual_type = sh_default_register_virtual_type; | |
4337 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
53116e27 EZ |
4338 | set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); |
4339 | set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); | |
4340 | set_gdbarch_register_byte (gdbarch, sh_default_register_byte); | |
2f14585c | 4341 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a EZ |
4342 | tdep->DSR_REGNUM = 24; |
4343 | tdep->A0G_REGNUM = 25; | |
4344 | tdep->A0_REGNUM = 26; | |
4345 | tdep->A1G_REGNUM = 27; | |
4346 | tdep->A1_REGNUM = 28; | |
4347 | tdep->M0_REGNUM = 29; | |
4348 | tdep->M1_REGNUM = 30; | |
4349 | tdep->X0_REGNUM = 31; | |
4350 | tdep->X1_REGNUM = 32; | |
4351 | tdep->Y0_REGNUM = 33; | |
4352 | tdep->Y1_REGNUM = 34; | |
4353 | tdep->MOD_REGNUM = 40; | |
4354 | tdep->RS_REGNUM = 43; | |
4355 | tdep->RE_REGNUM = 44; | |
4356 | break; | |
4357 | case bfd_mach_sh3: | |
4358 | sh_register_name = sh_sh3_register_name; | |
4359 | sh_show_regs = sh3_show_regs; | |
4360 | sh_store_return_value = sh_default_store_return_value; | |
4361 | sh_register_virtual_type = sh_default_register_virtual_type; | |
4362 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
53116e27 EZ |
4363 | set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); |
4364 | set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); | |
4365 | set_gdbarch_register_byte (gdbarch, sh_default_register_byte); | |
cc17453a EZ |
4366 | tdep->SSR_REGNUM = 41; |
4367 | tdep->SPC_REGNUM = 42; | |
4368 | break; | |
4369 | case bfd_mach_sh3e: | |
4370 | sh_register_name = sh_sh3e_register_name; | |
4371 | sh_show_regs = sh3e_show_regs; | |
4372 | sh_store_return_value = sh3e_sh4_store_return_value; | |
4373 | sh_register_virtual_type = sh_sh3e_register_virtual_type; | |
4374 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs); | |
53116e27 EZ |
4375 | set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); |
4376 | set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); | |
4377 | set_gdbarch_register_byte (gdbarch, sh_default_register_byte); | |
26e9b323 | 4378 | set_gdbarch_deprecated_extract_return_value (gdbarch, sh3e_sh4_extract_return_value); |
cc17453a EZ |
4379 | set_gdbarch_fp0_regnum (gdbarch, 25); |
4380 | tdep->FPUL_REGNUM = 23; | |
4381 | tdep->FPSCR_REGNUM = 24; | |
e6c42fda | 4382 | tdep->FP_LAST_REGNUM = 40; |
cc17453a EZ |
4383 | tdep->SSR_REGNUM = 41; |
4384 | tdep->SPC_REGNUM = 42; | |
4385 | break; | |
4386 | case bfd_mach_sh3_dsp: | |
4387 | sh_register_name = sh_sh3_dsp_register_name; | |
4388 | sh_show_regs = sh3_dsp_show_regs; | |
4389 | sh_store_return_value = sh_default_store_return_value; | |
4390 | sh_register_virtual_type = sh_default_register_virtual_type; | |
4391 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
53116e27 EZ |
4392 | set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); |
4393 | set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); | |
4394 | set_gdbarch_register_byte (gdbarch, sh_default_register_byte); | |
cc17453a EZ |
4395 | tdep->DSR_REGNUM = 24; |
4396 | tdep->A0G_REGNUM = 25; | |
4397 | tdep->A0_REGNUM = 26; | |
4398 | tdep->A1G_REGNUM = 27; | |
4399 | tdep->A1_REGNUM = 28; | |
4400 | tdep->M0_REGNUM = 29; | |
4401 | tdep->M1_REGNUM = 30; | |
4402 | tdep->X0_REGNUM = 31; | |
4403 | tdep->X1_REGNUM = 32; | |
4404 | tdep->Y0_REGNUM = 33; | |
4405 | tdep->Y1_REGNUM = 34; | |
4406 | tdep->MOD_REGNUM = 40; | |
4407 | tdep->RS_REGNUM = 43; | |
4408 | tdep->RE_REGNUM = 44; | |
4409 | tdep->SSR_REGNUM = 41; | |
4410 | tdep->SPC_REGNUM = 42; | |
4411 | break; | |
4412 | case bfd_mach_sh4: | |
53116e27 EZ |
4413 | sh_register_name = sh_sh4_register_name; |
4414 | sh_show_regs = sh4_show_regs; | |
cc17453a | 4415 | sh_store_return_value = sh3e_sh4_store_return_value; |
53116e27 | 4416 | sh_register_virtual_type = sh_sh4_register_virtual_type; |
cc17453a | 4417 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs); |
26e9b323 | 4418 | set_gdbarch_deprecated_extract_return_value (gdbarch, sh3e_sh4_extract_return_value); |
cc17453a | 4419 | set_gdbarch_fp0_regnum (gdbarch, 25); |
53116e27 EZ |
4420 | set_gdbarch_register_raw_size (gdbarch, sh_sh4_register_raw_size); |
4421 | set_gdbarch_register_virtual_size (gdbarch, sh_sh4_register_raw_size); | |
4422 | set_gdbarch_register_byte (gdbarch, sh_sh4_register_byte); | |
4423 | set_gdbarch_num_pseudo_regs (gdbarch, 12); | |
4424 | set_gdbarch_max_register_raw_size (gdbarch, 4 * 4); | |
4425 | set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4); | |
d8124050 AC |
4426 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); |
4427 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
cc17453a EZ |
4428 | tdep->FPUL_REGNUM = 23; |
4429 | tdep->FPSCR_REGNUM = 24; | |
e6c42fda | 4430 | tdep->FP_LAST_REGNUM = 40; |
cc17453a EZ |
4431 | tdep->SSR_REGNUM = 41; |
4432 | tdep->SPC_REGNUM = 42; | |
53116e27 | 4433 | tdep->DR0_REGNUM = 59; |
e6c42fda | 4434 | tdep->DR_LAST_REGNUM = 66; |
53116e27 | 4435 | tdep->FV0_REGNUM = 67; |
e6c42fda | 4436 | tdep->FV_LAST_REGNUM = 70; |
cc17453a | 4437 | break; |
283150cd EZ |
4438 | case bfd_mach_sh5: |
4439 | tdep->PR_REGNUM = 18; | |
4440 | tdep->SR_REGNUM = 65; | |
4441 | tdep->FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM; | |
4442 | tdep->FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1; | |
4443 | tdep->SSR_REGNUM = SIM_SH64_SSR_REGNUM; | |
4444 | tdep->SPC_REGNUM = SIM_SH64_SPC_REGNUM; | |
4445 | tdep->TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7; | |
4446 | tdep->FPP0_REGNUM = 173; | |
4447 | tdep->FPP_LAST_REGNUM = 204; | |
4448 | tdep->DR0_REGNUM = 141; | |
4449 | tdep->DR_LAST_REGNUM = 172; | |
4450 | tdep->FV0_REGNUM = 205; | |
4451 | tdep->FV_LAST_REGNUM = 220; | |
4452 | tdep->R0_C_REGNUM = 221; | |
4453 | tdep->R_LAST_C_REGNUM = 236; | |
4454 | tdep->PC_C_REGNUM = 237; | |
4455 | tdep->GBR_C_REGNUM = 238; | |
4456 | tdep->MACH_C_REGNUM = 239; | |
4457 | tdep->MACL_C_REGNUM = 240; | |
4458 | tdep->PR_C_REGNUM = 241; | |
4459 | tdep->T_C_REGNUM = 242; | |
4460 | tdep->FPSCR_C_REGNUM = 243; | |
4461 | tdep->FPUL_C_REGNUM = 244; | |
4462 | tdep->FP0_C_REGNUM = 245; | |
4463 | tdep->FP_LAST_C_REGNUM = 260; | |
4464 | tdep->DR0_C_REGNUM = 261; | |
4465 | tdep->DR_LAST_C_REGNUM = 268; | |
4466 | tdep->FV0_C_REGNUM = 269; | |
4467 | tdep->FV_LAST_C_REGNUM = 272; | |
4468 | tdep->ARG0_REGNUM = 2; | |
4469 | tdep->ARGLAST_REGNUM = 9; | |
4470 | tdep->RETURN_REGNUM = 2; | |
4471 | tdep->FLOAT_ARGLAST_REGNUM = 11; | |
4472 | ||
4473 | set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT); | |
4474 | set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM); | |
4475 | set_gdbarch_pc_regnum (gdbarch, 64); | |
4476 | ||
4477 | /* Determine the ABI */ | |
4478 | if (bfd_get_arch_size (info.abfd) == 64) | |
4479 | { | |
4480 | /* If the ABI is the 64-bit one, it can only be sh-media. */ | |
4481 | tdep->sh_abi = SH_ABI_64; | |
4482 | set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4483 | set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4484 | } | |
4485 | else | |
4486 | { | |
4487 | /* If the ABI is the 32-bit one it could be either media or | |
4488 | compact. */ | |
4489 | tdep->sh_abi = SH_ABI_32; | |
4490 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
4491 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
4492 | } | |
4493 | ||
4494 | /* the number of real registers is the same whether we are in | |
4495 | ISA16(compact) or ISA32(media). */ | |
4496 | set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS); | |
4497 | set_gdbarch_register_size (gdbarch, 8); /*????*/ | |
4498 | set_gdbarch_register_bytes (gdbarch, | |
4499 | ((SIM_SH64_NR_FP_REGS + 1) * 4) | |
4500 | + (SIM_SH64_NR_REGS - SIM_SH64_NR_FP_REGS -1) * 8); | |
4501 | ||
4502 | sh_register_name = sh_sh64_register_name; | |
4503 | sh_show_regs = sh64_show_regs; | |
4504 | sh_register_virtual_type = sh_sh64_register_virtual_type; | |
4505 | sh_store_return_value = sh64_store_return_value; | |
4506 | skip_prologue_hard_way = sh64_skip_prologue_hard_way; | |
4507 | do_pseudo_register = sh64_do_pseudo_register; | |
283150cd EZ |
4508 | set_gdbarch_register_raw_size (gdbarch, sh_sh64_register_raw_size); |
4509 | set_gdbarch_register_virtual_size (gdbarch, sh_sh64_register_raw_size); | |
4510 | set_gdbarch_register_byte (gdbarch, sh_sh64_register_byte); | |
4511 | /* This seems awfully wrong!*/ | |
4512 | /*set_gdbarch_max_register_raw_size (gdbarch, 8);*/ | |
4513 | /* should include the size of the pseudo regs. */ | |
4514 | set_gdbarch_max_register_raw_size (gdbarch, 4 * 4); | |
4515 | /* Or should that go in the virtual_size? */ | |
4516 | /*set_gdbarch_max_register_virtual_size (gdbarch, 8);*/ | |
4517 | set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4); | |
d8124050 AC |
4518 | set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read); |
4519 | set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write); | |
283150cd | 4520 | |
903ad3a6 | 4521 | set_gdbarch_deprecated_do_registers_info (gdbarch, sh64_do_registers_info); |
283150cd EZ |
4522 | set_gdbarch_frame_init_saved_regs (gdbarch, sh64_nofp_frame_init_saved_regs); |
4523 | set_gdbarch_breakpoint_from_pc (gdbarch, sh_sh64_breakpoint_from_pc); | |
4524 | set_gdbarch_init_extra_frame_info (gdbarch, sh64_init_extra_frame_info); | |
4525 | set_gdbarch_frame_chain (gdbarch, sh64_frame_chain); | |
4526 | set_gdbarch_get_saved_register (gdbarch, sh64_get_saved_register); | |
26e9b323 | 4527 | set_gdbarch_deprecated_extract_return_value (gdbarch, sh64_extract_return_value); |
283150cd EZ |
4528 | set_gdbarch_push_arguments (gdbarch, sh64_push_arguments); |
4529 | /*set_gdbarch_store_struct_return (gdbarch, sh64_store_struct_return);*/ | |
26e9b323 | 4530 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh64_extract_struct_value_address); |
283150cd EZ |
4531 | set_gdbarch_use_struct_convention (gdbarch, sh64_use_struct_convention); |
4532 | set_gdbarch_pop_frame (gdbarch, sh64_pop_frame); | |
4533 | set_gdbarch_elf_make_msymbol_special (gdbarch, | |
4534 | sh64_elf_make_msymbol_special); | |
4535 | break; | |
cc17453a EZ |
4536 | default: |
4537 | sh_register_name = sh_generic_register_name; | |
4538 | sh_show_regs = sh_generic_show_regs; | |
4539 | sh_store_return_value = sh_default_store_return_value; | |
4540 | sh_register_virtual_type = sh_default_register_virtual_type; | |
4541 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
53116e27 EZ |
4542 | set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); |
4543 | set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); | |
4544 | set_gdbarch_register_byte (gdbarch, sh_default_register_byte); | |
cc17453a | 4545 | break; |
8db62801 | 4546 | } |
cc17453a EZ |
4547 | |
4548 | set_gdbarch_read_pc (gdbarch, generic_target_read_pc); | |
4549 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); | |
4550 | set_gdbarch_read_fp (gdbarch, generic_target_read_fp); | |
cc17453a EZ |
4551 | set_gdbarch_read_sp (gdbarch, generic_target_read_sp); |
4552 | set_gdbarch_write_sp (gdbarch, generic_target_write_sp); | |
4553 | ||
cc17453a | 4554 | set_gdbarch_register_name (gdbarch, sh_register_name); |
cc17453a EZ |
4555 | set_gdbarch_register_virtual_type (gdbarch, sh_register_virtual_type); |
4556 | ||
cc17453a EZ |
4557 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
4558 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
cc17453a EZ |
4559 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
4560 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
4561 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
7079c36c | 4562 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
cc17453a | 4563 | |
cc17453a | 4564 | set_gdbarch_call_dummy_length (gdbarch, 0); |
cc17453a EZ |
4565 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); |
4566 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); /*???*/ | |
4567 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
4568 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
cc17453a EZ |
4569 | set_gdbarch_call_dummy_words (gdbarch, sh_call_dummy_words); |
4570 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (sh_call_dummy_words)); | |
4571 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
4572 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
cc17453a | 4573 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); |
cc17453a | 4574 | |
cc17453a EZ |
4575 | set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); |
4576 | set_gdbarch_push_return_address (gdbarch, sh_push_return_address); | |
4577 | ||
ebba8386 | 4578 | set_gdbarch_deprecated_store_return_value (gdbarch, sh_store_return_value); |
cc17453a EZ |
4579 | set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue); |
4580 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
4581 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
4582 | set_gdbarch_function_start_offset (gdbarch, 0); | |
cc17453a EZ |
4583 | |
4584 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
4585 | set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); | |
cc17453a | 4586 | set_gdbarch_frame_saved_pc (gdbarch, sh_frame_saved_pc); |
cc17453a EZ |
4587 | set_gdbarch_saved_pc_after_call (gdbarch, sh_saved_pc_after_call); |
4588 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); | |
4589 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); | |
cc17453a | 4590 | |
4be87837 DJ |
4591 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4592 | gdbarch_init_osabi (info, gdbarch); | |
d658f924 | 4593 | |
cc17453a | 4594 | return gdbarch; |
8db62801 EZ |
4595 | } |
4596 | ||
d658f924 JT |
4597 | static void |
4598 | sh_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
4599 | { | |
4600 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
4601 | ||
4602 | if (tdep == NULL) | |
4603 | return; | |
4604 | ||
4be87837 | 4605 | /* FIXME: dump the rest of gdbarch_tdep. */ |
d658f924 JT |
4606 | } |
4607 | ||
c906108c | 4608 | void |
fba45db2 | 4609 | _initialize_sh_tdep (void) |
c906108c SS |
4610 | { |
4611 | struct cmd_list_element *c; | |
cc17453a | 4612 | |
d658f924 | 4613 | gdbarch_register (bfd_arch_sh, sh_gdbarch_init, sh_dump_tdep); |
c906108c | 4614 | |
53116e27 | 4615 | add_com ("regs", class_vars, sh_show_regs_command, "Print all registers"); |
c906108c | 4616 | } |