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2000-12-11 Michael Snyder <msnyder@cleaver.cygnus.com>
[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
CommitLineData
c906108c 1/* Target-dependent code for Hitachi Super-H, for GDB.
b4a20239
AC		 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 2000 Free Software
3 Foundation, Inc.
c906108c 4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM		 7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
c906108c 11
c5aa993b
JM		 12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b
JM		 17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
c906108c
SS		 21
22/*
c5aa993b
JM		 23 Contributed by Steve Chamberlain
24 sac@cygnus.com
c906108c
SS		 25 */
26
27#include "defs.h"
28#include "frame.h"
29#include "obstack.h"
30#include "symtab.h"
31#include "symfile.h"
32#include "gdbtypes.h"
33#include "gdbcmd.h"
34#include "gdbcore.h"
35#include "value.h"
36#include "dis-asm.h"
37#include "inferior.h" /* for BEFORE_TEXT_END etc. */
38#include "gdb_string.h"
b4a20239 39#include "arch-utils.h"
fb409745 40#include "floatformat.h"
c906108c 41
1a8629c7
MS		 42#include "solib-svr4.h"
43
cc17453a
EZ		 44#undef XMALLOC
45#define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE)))
46
53116e27
EZ		 47
48/* Frame interpretation related functions. */
cc17453a
EZ		 49static gdbarch_breakpoint_from_pc_ftype sh_breakpoint_from_pc;
50static gdbarch_frame_chain_ftype sh_frame_chain;
51static gdbarch_frame_saved_pc_ftype sh_frame_saved_pc;
52static gdbarch_skip_prologue_ftype sh_skip_prologue;
53116e27 53
cc17453a
EZ		 54static gdbarch_frame_init_saved_regs_ftype sh_nofp_frame_init_saved_regs;
55static gdbarch_frame_init_saved_regs_ftype sh_fp_frame_init_saved_regs;
53116e27
EZ		 56static gdbarch_init_extra_frame_info_ftype sh_init_extra_frame_info;
57static gdbarch_pop_frame_ftype sh_pop_frame;
58static gdbarch_saved_pc_after_call_ftype sh_saved_pc_after_call;
59static gdbarch_frame_args_address_ftype sh_frame_args_address;
60static gdbarch_frame_locals_address_ftype sh_frame_locals_address;
61
62/* Function call related functions. */
cc17453a
EZ		 63static gdbarch_extract_return_value_ftype sh_extract_return_value;
64static gdbarch_extract_struct_value_address_ftype sh_extract_struct_value_address;
65static gdbarch_use_struct_convention_ftype sh_use_struct_convention;
cc17453a
EZ		 66static gdbarch_store_struct_return_ftype sh_store_struct_return;
67static gdbarch_push_arguments_ftype sh_push_arguments;
68static gdbarch_push_return_address_ftype sh_push_return_address;
53116e27
EZ		 69static gdbarch_coerce_float_to_double_ftype sh_coerce_float_to_double;
70static gdbarch_store_return_value_ftype sh_default_store_return_value;
71static gdbarch_store_return_value_ftype sh3e_sh4_store_return_value;
cc17453a
EZ		 72
73static gdbarch_register_name_ftype sh_generic_register_name;
74static gdbarch_register_name_ftype sh_sh_register_name;
75static gdbarch_register_name_ftype sh_sh3_register_name;
76static gdbarch_register_name_ftype sh_sh3e_register_name;
77static gdbarch_register_name_ftype sh_sh_dsp_register_name;
78static gdbarch_register_name_ftype sh_sh3_dsp_register_name;
79
53116e27
EZ		 80/* Registers display related functions */
81static gdbarch_register_raw_size_ftype sh_default_register_raw_size;
82static gdbarch_register_raw_size_ftype sh_sh4_register_raw_size;
cc17453a 83
cc17453a 84static gdbarch_register_virtual_size_ftype sh_register_virtual_size;
53116e27
EZ		 85
86static gdbarch_register_byte_ftype sh_default_register_byte;
87static gdbarch_register_byte_ftype sh_sh4_register_byte;
88
cc17453a 89static gdbarch_register_virtual_type_ftype sh_sh3e_register_virtual_type;
53116e27 90static gdbarch_register_virtual_type_ftype sh_sh4_register_virtual_type;
cc17453a
EZ		 91static gdbarch_register_virtual_type_ftype sh_default_register_virtual_type;
92
53116e27
EZ		 93static void sh_generic_show_regs (void);
94static void sh3_show_regs (void);
95static void sh3e_show_regs (void);
96static void sh3_dsp_show_regs (void);
97static void sh_dsp_show_regs (void);
98static void sh4_show_regs (void);
99static void sh_show_regs_command (char *, int);
100
101static struct type *sh_sh4_build_float_register_type (int high);
102
103static gdbarch_fetch_pseudo_register_ftype sh_fetch_pseudo_register;
104static gdbarch_store_pseudo_register_ftype sh_store_pseudo_register;
105static int fv_reg_base_num (int);
106static int dr_reg_base_num (int);
107static void do_fv_register_info (int fv_regnum);
108static void do_dr_register_info (int dr_regnum);
109static void sh_do_pseudo_register (int regnum);
110static void sh_do_fp_register (int regnum);
111static void sh_do_register (int regnum);
112static void sh_print_register (int regnum);
113
114void (*sh_show_regs) (void);
e6c42fda 115int (*print_sh_insn) (bfd_vma, disassemble_info*);
cc17453a 116
cc17453a
EZ		 117/* Define other aspects of the stack frame.
118 we keep a copy of the worked out return pc lying around, since it
119 is a useful bit of info */
120
121struct frame_extra_info
122{
123 CORE_ADDR return_pc;
124 int leaf_function;
125 int f_offset;
63978407 126};
c906108c 127
cc17453a 128#if 0
091be84d
CF		 129#ifdef _WIN32_WCE
130char **sh_register_names = sh3_reg_names;
131#else
c906108c 132char **sh_register_names = sh_generic_reg_names;
091be84d 133#endif
cc17453a 134#endif
c906108c 135
cc17453a
EZ		 136static char *
137sh_generic_register_name (int reg_nr)
c5aa993b 138{
cc17453a 139 static char *register_names[] =
c5aa993b 140 {
cc17453a
EZ		 141 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
142 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
143 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
144 "fpul", "fpscr",
145 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
146 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
147 "ssr", "spc",
148 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
149 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
150 };
151 if (reg_nr < 0)
152 return NULL;
153 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
154 return NULL;
155 return register_names[reg_nr];
156}
157
158static char *
159sh_sh_register_name (int reg_nr)
160{
161 static char *register_names[] =
63978407 162 {
cc17453a
EZ		 163 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
164 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
165 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
166 "", "",
167 "", "", "", "", "", "", "", "",
168 "", "", "", "", "", "", "", "",
169 "", "",
170 "", "", "", "", "", "", "", "",
171 "", "", "", "", "", "", "", "",
172 };
173 if (reg_nr < 0)
174 return NULL;
175 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
176 return NULL;
177 return register_names[reg_nr];
178}
179
180static char *
181sh_sh3_register_name (int reg_nr)
182{
183 static char *register_names[] =
c5aa993b 184 {
cc17453a
EZ		 185 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
186 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
187 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
188 "", "",
189 "", "", "", "", "", "", "", "",
190 "", "", "", "", "", "", "", "",
191 "ssr", "spc",
192 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
193 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
194 };
195 if (reg_nr < 0)
196 return NULL;
197 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
198 return NULL;
199 return register_names[reg_nr];
200}
201
202static char *
203sh_sh3e_register_name (int reg_nr)
204{
205 static char *register_names[] =
63978407 206 {
cc17453a
EZ		 207 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
208 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
209 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
210 "fpul", "fpscr",
211 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
212 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
213 "ssr", "spc",
214 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
215 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
216 };
217 if (reg_nr < 0)
218 return NULL;
219 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
220 return NULL;
221 return register_names[reg_nr];
222}
223
224static char *
225sh_sh_dsp_register_name (int reg_nr)
226{
227 static char *register_names[] =
c5aa993b 228 {
cc17453a
EZ		 229 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
230 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
231 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
232 "", "dsr",
233 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
234 "y0", "y1", "", "", "", "", "", "mod",
235 "", "",
236 "rs", "re", "", "", "", "", "", "",
237 "", "", "", "", "", "", "", "",
238 };
239 if (reg_nr < 0)
240 return NULL;
241 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
242 return NULL;
243 return register_names[reg_nr];
244}
245
246static char *
247sh_sh3_dsp_register_name (int reg_nr)
248{
249 static char *register_names[] =
c5aa993b 250 {
cc17453a
EZ		 251 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
252 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
253 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
254 "", "dsr",
255 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
256 "y0", "y1", "", "", "", "", "", "mod",
257 "ssr", "spc",
258 "rs", "re", "", "", "", "", "", "",
259 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
260 "", "", "", "", "", "", "", "",
261 };
262 if (reg_nr < 0)
263 return NULL;
264 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
265 return NULL;
266 return register_names[reg_nr];
267}
268
53116e27
EZ		 269static char *
270sh_sh4_register_name (int reg_nr)
271{
272 static char *register_names[] =
273 {
274 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
275 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
276 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
277 "fpul", "fpscr",
278 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
279 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
280 "ssr", "spc",
281 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
282 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
fe9f384f
EZ		 283 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
284 "fv0", "fv4", "fv8", "fv12",
53116e27
EZ		 285 };
286 if (reg_nr < 0)
287 return NULL;
288 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
289 return NULL;
290 return register_names[reg_nr];
291}
292
cc17453a 293static unsigned char *
fba45db2 294sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
cc17453a
EZ		 295{
296 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
297 static unsigned char breakpoint[] = {0xc3, 0xc3};
298
299 *lenptr = sizeof (breakpoint);
300 return breakpoint;
301}
c906108c
SS		 302
303/* Prologue looks like
c5aa993b
JM		 304 [mov.l <regs>,@-r15]...
305 [sts.l pr,@-r15]
306 [mov.l r14,@-r15]
307 [mov r15,r14]
8db62801
EZ		 308
309 Actually it can be more complicated than this. For instance, with
310 newer gcc's:
311
312 mov.l r14,@-r15
313 add #-12,r15
314 mov r15,r14
315 mov r4,r1
316 mov r5,r2
317 mov.l r6,@(4,r14)
318 mov.l r7,@(8,r14)
319 mov.b r1,@r14
320 mov r14,r1
321 mov r14,r1
322 add #2,r1
323 mov.w r2,@r1
324
c5aa993b 325 */
c906108c 326
8db62801
EZ		 327/* STS.L PR,@-r15 0100111100100010
328 r15-4-->r15, PR-->(r15) */
c906108c 329#define IS_STS(x) ((x) == 0x4f22)
8db62801
EZ		 330
331/* MOV.L Rm,@-r15 00101111mmmm0110
332 r15-4-->r15, Rm-->(R15) */
c906108c 333#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 334
c906108c 335#define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
8db62801
EZ		 336
337/* MOV r15,r14 0110111011110011
338 r15-->r14 */
c906108c 339#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ		 340
341/* ADD #imm,r15 01111111iiiiiiii
342 r15+imm-->r15 */
c906108c 343#define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 344
c906108c
SS		 345#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
346#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ		 347
348/* ADD r3,r15 0011111100111100
349 r15+r3-->r15 */
c906108c 350#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ		 351
352/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
8db62801 353 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
8db62801 354 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
c906108c 355#define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
c906108c 356
8db62801 357/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
8db62801 358 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
8db62801
EZ		 359 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
360 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
361#define IS_ARG_MOV(x) \
362(((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
cc17453a
EZ		 363 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
364 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
8db62801
EZ		 365
366/* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
367 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
368#define IS_MOV_R14(x) \
cc17453a 369 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
8db62801
EZ		 370
371#define FPSCR_SZ (1 << 20)
c906108c 372
c906108c
SS		 373/* Skip any prologue before the guts of a function */
374
8db62801
EZ		 375/* Skip the prologue using the debug information. If this fails we'll
376 fall back on the 'guess' method below. */
377static CORE_ADDR
fba45db2 378after_prologue (CORE_ADDR pc)
8db62801
EZ		 379{
380 struct symtab_and_line sal;
381 CORE_ADDR func_addr, func_end;
382
383 /* If we can not find the symbol in the partial symbol table, then
384 there is no hope we can determine the function's start address
385 with this code. */
386 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
387 return 0;
388
389 /* Get the line associated with FUNC_ADDR. */
390 sal = find_pc_line (func_addr, 0);
391
392 /* There are only two cases to consider. First, the end of the source line
393 is within the function bounds. In that case we return the end of the
394 source line. Second is the end of the source line extends beyond the
395 bounds of the current function. We need to use the slow code to
396 examine instructions in that case. */
397 if (sal.end < func_end)
398 return sal.end;
399 else
400 return 0;
401}
402
403/* Here we look at each instruction in the function, and try to guess
404 where the prologue ends. Unfortunately this is not always
405 accurate. */
406static CORE_ADDR
fba45db2 407skip_prologue_hard_way (CORE_ADDR start_pc)
c906108c 408{
2bfa91ee 409 CORE_ADDR here, end;
8db62801 410 int updated_fp = 0;
2bfa91ee
EZ		 411
412 if (!start_pc)
413 return 0;
414
415 for (here = start_pc, end = start_pc + (2 * 28); here < end;)
c906108c 416 {
2bfa91ee
EZ		 417 int w = read_memory_integer (here, 2);
418 here += 2;
419 if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w)
8db62801
EZ		 420 || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w)
421 || IS_ARG_MOV (w) || IS_MOV_R14 (w))
2bfa91ee
EZ		 422 {
423 start_pc = here;
2bfa91ee 424 }
8db62801
EZ		 425 else if (IS_MOV_SP_FP (w))
426 {
427 start_pc = here;
428 updated_fp = 1;
429 }
430 else
431 /* Don't bail out yet, if we are before the copy of sp. */
432 if (updated_fp)
433 break;
c906108c
SS		 434 }
435
436 return start_pc;
437}
438
cc17453a 439static CORE_ADDR
fba45db2 440sh_skip_prologue (CORE_ADDR pc)
8db62801
EZ		 441{
442 CORE_ADDR post_prologue_pc;
443
444 /* See if we can determine the end of the prologue via the symbol table.
445 If so, then return either PC, or the PC after the prologue, whichever
446 is greater. */
447
448 post_prologue_pc = after_prologue (pc);
449
450 /* If after_prologue returned a useful address, then use it. Else
451 fall back on the instruction skipping code. */
452 if (post_prologue_pc != 0)
453 return max (pc, post_prologue_pc);
454 else
455 return (skip_prologue_hard_way (pc));
456}
457
cc17453a
EZ		 458/* Immediately after a function call, return the saved pc.
459 Can't always go through the frames for this because on some machines
460 the new frame is not set up until the new function executes
461 some instructions.
462
463 The return address is the value saved in the PR register + 4 */
464static CORE_ADDR
fba45db2 465sh_saved_pc_after_call (struct frame_info *frame)
cc17453a
EZ		 466{
467 return (ADDR_BITS_REMOVE(read_register(PR_REGNUM)));
468}
469
470/* Should call_function allocate stack space for a struct return? */
471static int
fba45db2 472sh_use_struct_convention (int gcc_p, struct type *type)
cc17453a
EZ		 473{
474 return (TYPE_LENGTH (type) > 1);
475}
476
477/* Store the address of the place in which to copy the structure the
478 subroutine will return. This is called from call_function.
479
480 We store structs through a pointer passed in R0 */
481static void
fba45db2 482sh_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
cc17453a
EZ		 483{
484 write_register (STRUCT_RETURN_REGNUM, (addr));
485}
c906108c 486
cc17453a
EZ		 487/* Disassemble an instruction. */
488static int
fba45db2 489gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
c906108c
SS		 490{
491 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
492 return print_insn_sh (memaddr, info);
493 else
494 return print_insn_shl (memaddr, info);
495}
496
497/* Given a GDB frame, determine the address of the calling function's frame.
498 This will be used to create a new GDB frame struct, and then
499 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
500
501 For us, the frame address is its stack pointer value, so we look up
502 the function prologue to determine the caller's sp value, and return it. */
cc17453a 503static CORE_ADDR
fba45db2 504sh_frame_chain (struct frame_info *frame)
c906108c
SS		 505{
506 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
507 return frame->frame; /* dummy frame same as caller's frame */
2bfa91ee 508 if (frame->pc && !inside_entry_file (frame->pc))
cc17453a 509 return read_memory_integer (FRAME_FP (frame) + frame->extra_info->f_offset, 4);
c906108c
SS		 510 else
511 return 0;
512}
513
514/* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
515 we might want to do here is to check REGNUM against the clobber mask, and
516 somehow flag it as invalid if it isn't saved on the stack somewhere. This
517 would provide a graceful failure mode when trying to get the value of
518 caller-saves registers for an inner frame. */
519
cc17453a 520static CORE_ADDR
fba45db2 521sh_find_callers_reg (struct frame_info *fi, int regnum)
c906108c 522{
c906108c
SS		 523 for (; fi; fi = fi->next)
524 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
525 /* When the caller requests PR from the dummy frame, we return PC because
c5aa993b 526 that's where the previous routine appears to have done a call from. */
c906108c 527 return generic_read_register_dummy (fi->pc, fi->frame, regnum);
c5aa993b 528 else
c906108c 529 {
cc17453a 530 FRAME_INIT_SAVED_REGS (fi);
2bfa91ee
EZ		 531 if (!fi->pc)
532 return 0;
cc17453a
EZ		 533 if (fi->saved_regs[regnum] != 0)
534 return read_memory_integer (fi->saved_regs[regnum],
c5aa993b 535 REGISTER_RAW_SIZE (regnum));
c906108c
SS		 536 }
537 return read_register (regnum);
538}
539
540/* Put here the code to store, into a struct frame_saved_regs, the
541 addresses of the saved registers of frame described by FRAME_INFO.
542 This includes special registers such as pc and fp saved in special
543 ways in the stack frame. sp is even more special: the address we
544 return for it IS the sp for the next frame. */
cc17453a 545static void
fba45db2 546sh_nofp_frame_init_saved_regs (struct frame_info *fi)
c906108c
SS		 547{
548 int where[NUM_REGS];
549 int rn;
550 int have_fp = 0;
551 int depth;
552 int pc;
553 int opc;
554 int insn;
555 int r3_val = 0;
c5aa993b 556 char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
cc17453a
EZ		 557
558 if (fi->saved_regs == NULL)
559 frame_saved_regs_zalloc (fi);
560 else
561 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
562
563 if (dummy_regs)
564 {
565 /* DANGER! This is ONLY going to work if the char buffer format of
566 the saved registers is byte-for-byte identical to the
567 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
568 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
569 return;
570 }
571
572 fi->extra_info->leaf_function = 1;
573 fi->extra_info->f_offset = 0;
574
575 for (rn = 0; rn < NUM_REGS; rn++)
576 where[rn] = -1;
577
578 depth = 0;
579
580 /* Loop around examining the prologue insns until we find something
581 that does not appear to be part of the prologue. But give up
582 after 20 of them, since we're getting silly then. */
583
584 pc = get_pc_function_start (fi->pc);
585 if (!pc)
586 {
587 fi->pc = 0;
588 return;
589 }
590
591 for (opc = pc + (2 * 28); pc < opc; pc += 2)
592 {
593 insn = read_memory_integer (pc, 2);
594 /* See where the registers will be saved to */
595 if (IS_PUSH (insn))
596 {
597 rn = GET_PUSHED_REG (insn);
598 where[rn] = depth;
599 depth += 4;
600 }
601 else if (IS_STS (insn))
602 {
603 where[PR_REGNUM] = depth;
604 /* If we're storing the pr then this isn't a leaf */
605 fi->extra_info->leaf_function = 0;
606 depth += 4;
607 }
608 else if (IS_MOV_R3 (insn))
609 {
610 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
611 }
612 else if (IS_SHLL_R3 (insn))
613 {
614 r3_val <<= 1;
615 }
616 else if (IS_ADD_R3SP (insn))
617 {
618 depth += -r3_val;
619 }
620 else if (IS_ADD_SP (insn))
621 {
622 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
623 }
624 else if (IS_MOV_SP_FP (insn))
625 break;
626#if 0 /* This used to just stop when it found an instruction that
627 was not considered part of the prologue. Now, we just
628 keep going looking for likely instructions. */
629 else
630 break;
631#endif
632 }
633
634 /* Now we know how deep things are, we can work out their addresses */
635
636 for (rn = 0; rn < NUM_REGS; rn++)
637 {
638 if (where[rn] >= 0)
639 {
640 if (rn == FP_REGNUM)
641 have_fp = 1;
c906108c 642
cc17453a
EZ		 643 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
644 }
645 else
646 {
647 fi->saved_regs[rn] = 0;
648 }
649 }
650
651 if (have_fp)
652 {
653 fi->saved_regs[SP_REGNUM] = read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
654 }
655 else
656 {
657 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
658 }
659
660 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
661 /* Work out the return pc - either from the saved pr or the pr
662 value */
663}
664
665static void
fba45db2 666sh_fp_frame_init_saved_regs (struct frame_info *fi)
cc17453a
EZ		 667{
668 int where[NUM_REGS];
669 int rn;
670 int have_fp = 0;
671 int depth;
672 int pc;
673 int opc;
674 int insn;
675 int r3_val = 0;
676 char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
677
678 if (fi->saved_regs == NULL)
679 frame_saved_regs_zalloc (fi);
680 else
681 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
682
c906108c
SS		 683 if (dummy_regs)
684 {
685 /* DANGER! This is ONLY going to work if the char buffer format of
c5aa993b
JM		 686 the saved registers is byte-for-byte identical to the
687 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
cc17453a 688 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
c906108c
SS		 689 return;
690 }
691
cc17453a
EZ		 692 fi->extra_info->leaf_function = 1;
693 fi->extra_info->f_offset = 0;
c906108c
SS		 694
695 for (rn = 0; rn < NUM_REGS; rn++)
696 where[rn] = -1;
697
698 depth = 0;
699
700 /* Loop around examining the prologue insns until we find something
701 that does not appear to be part of the prologue. But give up
702 after 20 of them, since we're getting silly then. */
703
2bfa91ee
EZ		 704 pc = get_pc_function_start (fi->pc);
705 if (!pc)
c906108c 706 {
2bfa91ee
EZ		 707 fi->pc = 0;
708 return;
709 }
710
711 for (opc = pc + (2 * 28); pc < opc; pc += 2)
712 {
713 insn = read_memory_integer (pc, 2);
c906108c
SS		 714 /* See where the registers will be saved to */
715 if (IS_PUSH (insn))
716 {
c906108c
SS		 717 rn = GET_PUSHED_REG (insn);
718 where[rn] = depth;
c906108c
SS		 719 depth += 4;
720 }
721 else if (IS_STS (insn))
722 {
c906108c 723 where[PR_REGNUM] = depth;
c906108c 724 /* If we're storing the pr then this isn't a leaf */
cc17453a 725 fi->extra_info->leaf_function = 0;
c906108c
SS		 726 depth += 4;
727 }
728 else if (IS_MOV_R3 (insn))
729 {
730 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 731 }
732 else if (IS_SHLL_R3 (insn))
733 {
734 r3_val <<= 1;
c906108c
SS		 735 }
736 else if (IS_ADD_R3SP (insn))
737 {
738 depth += -r3_val;
c906108c
SS		 739 }
740 else if (IS_ADD_SP (insn))
741 {
c906108c 742 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 743 }
744 else if (IS_FMOV (insn))
745 {
cc17453a 746 if (read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM) & FPSCR_SZ)
c906108c
SS		 747 {
748 depth += 8;
749 }
750 else
751 {
752 depth += 4;
753 }
754 }
2bfa91ee
EZ		 755 else if (IS_MOV_SP_FP (insn))
756 break;
757#if 0 /* This used to just stop when it found an instruction that
758 was not considered part of the prologue. Now, we just
759 keep going looking for likely instructions. */
c906108c
SS		 760 else
761 break;
2bfa91ee 762#endif
c906108c
SS		 763 }
764
765 /* Now we know how deep things are, we can work out their addresses */
766
767 for (rn = 0; rn < NUM_REGS; rn++)
768 {
769 if (where[rn] >= 0)
770 {
771 if (rn == FP_REGNUM)
772 have_fp = 1;
773
cc17453a 774 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
c906108c
SS		 775 }
776 else
777 {
cc17453a 778 fi->saved_regs[rn] = 0;
c906108c
SS		 779 }
780 }
781
782 if (have_fp)
783 {
cc17453a 784 fi->saved_regs[SP_REGNUM] = read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
c906108c
SS		 785 }
786 else
787 {
cc17453a 788 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
c906108c
SS		 789 }
790
cc17453a 791 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
c906108c
SS		 792 /* Work out the return pc - either from the saved pr or the pr
793 value */
794}
795
cc17453a
EZ		 796/* Initialize the extra info saved in a FRAME */
797static void
fba45db2 798sh_init_extra_frame_info (int fromleaf, struct frame_info *fi)
c906108c 799{
cc17453a
EZ		 800
801 fi->extra_info = (struct frame_extra_info *)
802 frame_obstack_alloc (sizeof (struct frame_extra_info));
c906108c
SS		 803
804 if (fi->next)
805 fi->pc = FRAME_SAVED_PC (fi->next);
806
807 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
808 {
809 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
c5aa993b
JM		 810 by assuming it's always FP. */
811 fi->frame = generic_read_register_dummy (fi->pc, fi->frame,
812 SP_REGNUM);
cc17453a
EZ		 813 fi->extra_info->return_pc = generic_read_register_dummy (fi->pc, fi->frame,
814 PC_REGNUM);
815 fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4);
816 fi->extra_info->leaf_function = 0;
c906108c
SS		 817 return;
818 }
819 else
820 {
cc17453a
EZ		 821 FRAME_INIT_SAVED_REGS (fi);
822 fi->extra_info->return_pc = sh_find_callers_reg (fi, PR_REGNUM);
c906108c
SS		 823 }
824}
825
cc17453a
EZ		 826/* Extract from an array REGBUF containing the (raw) register state
827 the address in which a function should return its structure value,
828 as a CORE_ADDR (or an expression that can be used as one). */
b3df3fff 829static CORE_ADDR
0c8053b6 830sh_extract_struct_value_address (char *regbuf)
cc17453a
EZ		 831{
832 return (extract_address ((regbuf), REGISTER_RAW_SIZE (0)));
833}
834
835static CORE_ADDR
fba45db2 836sh_frame_saved_pc (struct frame_info *frame)
cc17453a
EZ		 837{
838 return ((frame)->extra_info->return_pc);
839}
840
841static CORE_ADDR
fba45db2 842sh_frame_args_address (struct frame_info *fi)
cc17453a
EZ		 843{
844 return (fi)->frame;
845}
846
847static CORE_ADDR
fba45db2 848sh_frame_locals_address (struct frame_info *fi)
cc17453a
EZ		 849{
850 return (fi)->frame;
851}
852
c906108c
SS		 853/* Discard from the stack the innermost frame,
854 restoring all saved registers. */
cc17453a 855static void
fba45db2 856sh_pop_frame (void)
c906108c
SS		 857{
858 register struct frame_info *frame = get_current_frame ();
859 register CORE_ADDR fp;
860 register int regnum;
c906108c
SS		 861
862 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
863 generic_pop_dummy_frame ();
864 else
c5aa993b
JM		 865 {
866 fp = FRAME_FP (frame);
cc17453a 867 FRAME_INIT_SAVED_REGS (frame);
c906108c 868
c5aa993b
JM		 869 /* Copy regs from where they were saved in the frame */
870 for (regnum = 0; regnum < NUM_REGS; regnum++)
cc17453a
EZ		 871 if (frame->saved_regs[regnum])
872 write_register (regnum, read_memory_integer (frame->saved_regs[regnum], 4));
c906108c 873
cc17453a 874 write_register (PC_REGNUM, frame->extra_info->return_pc);
c5aa993b
JM		 875 write_register (SP_REGNUM, fp + 4);
876 }
c906108c
SS		 877 flush_cached_frames ();
878}
879
880/* Function: push_arguments
881 Setup the function arguments for calling a function in the inferior.
882
883 On the Hitachi SH architecture, there are four registers (R4 to R7)
884 which are dedicated for passing function arguments. Up to the first
885 four arguments (depending on size) may go into these registers.
886 The rest go on the stack.
887
888 Arguments that are smaller than 4 bytes will still take up a whole
889 register or a whole 32-bit word on the stack, and will be
890 right-justified in the register or the stack word. This includes
891 chars, shorts, and small aggregate types.
892
893 Arguments that are larger than 4 bytes may be split between two or
894 more registers. If there are not enough registers free, an argument
895 may be passed partly in a register (or registers), and partly on the
896 stack. This includes doubles, long longs, and larger aggregates.
897 As far as I know, there is no upper limit to the size of aggregates
898 that will be passed in this way; in other words, the convention of
899 passing a pointer to a large aggregate instead of a copy is not used.
900
901 An exceptional case exists for struct arguments (and possibly other
902 aggregates such as arrays) if the size is larger than 4 bytes but
903 not a multiple of 4 bytes. In this case the argument is never split
904 between the registers and the stack, but instead is copied in its
905 entirety onto the stack, AND also copied into as many registers as
906 there is room for. In other words, space in registers permitting,
907 two copies of the same argument are passed in. As far as I can tell,
908 only the one on the stack is used, although that may be a function
909 of the level of compiler optimization. I suspect this is a compiler
910 bug. Arguments of these odd sizes are left-justified within the
911 word (as opposed to arguments smaller than 4 bytes, which are
912 right-justified).
c5aa993b 913
c906108c
SS		 914 If the function is to return an aggregate type such as a struct, it
915 is either returned in the normal return value register R0 (if its
916 size is no greater than one byte), or else the caller must allocate
917 space into which the callee will copy the return value (if the size
918 is greater than one byte). In this case, a pointer to the return
919 value location is passed into the callee in register R2, which does
920 not displace any of the other arguments passed in via registers R4
921 to R7. */
922
cc17453a 923static CORE_ADDR
34e9d9bb
EZ		 924sh_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
925 int struct_return, CORE_ADDR struct_addr)
c906108c
SS		 926{
927 int stack_offset, stack_alloc;
928 int argreg;
929 int argnum;
930 struct type *type;
931 CORE_ADDR regval;
932 char *val;
933 char valbuf[4];
934 int len;
935 int odd_sized_struct;
936
937 /* first force sp to a 4-byte alignment */
938 sp = sp & ~3;
939
940 /* The "struct return pointer" pseudo-argument has its own dedicated
941 register */
942 if (struct_return)
c5aa993b 943 write_register (STRUCT_RETURN_REGNUM, struct_addr);
c906108c
SS		 944
945 /* Now make sure there's space on the stack */
cc17453a 946 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
c5aa993b
JM		 947 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
948 sp -= stack_alloc; /* make room on stack for args */
c906108c 949
c906108c
SS		 950 /* Now load as many as possible of the first arguments into
951 registers, and push the rest onto the stack. There are 16 bytes
952 in four registers available. Loop thru args from first to last. */
953
954 argreg = ARG0_REGNUM;
955 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
956 {
957 type = VALUE_TYPE (args[argnum]);
c5aa993b
JM		 958 len = TYPE_LENGTH (type);
959 memset (valbuf, 0, sizeof (valbuf));
c906108c 960 if (len < 4)
cc17453a
EZ		 961 {
962 /* value gets right-justified in the register or stack word */
c5aa993b
JM		 963 memcpy (valbuf + (4 - len),
964 (char *) VALUE_CONTENTS (args[argnum]), len);
965 val = valbuf;
966 }
c906108c 967 else
c5aa993b 968 val = (char *) VALUE_CONTENTS (args[argnum]);
c906108c
SS		 969
970 if (len > 4 && (len & 3) != 0)
c5aa993b
JM		 971 odd_sized_struct = 1; /* such structs go entirely on stack */
972 else
c906108c
SS		 973 odd_sized_struct = 0;
974 while (len > 0)
975 {
976 if (argreg > ARGLAST_REGNUM || odd_sized_struct)
c5aa993b 977 { /* must go on the stack */
c906108c
SS		 978 write_memory (sp + stack_offset, val, 4);
979 stack_offset += 4;
980 }
981 /* NOTE WELL!!!!! This is not an "else if" clause!!!
982 That's because some *&^%$ things get passed on the stack
983 AND in the registers! */
984 if (argreg <= ARGLAST_REGNUM)
c5aa993b
JM		 985 { /* there's room in a register */
986 regval = extract_address (val, REGISTER_RAW_SIZE (argreg));
c906108c
SS		 987 write_register (argreg++, regval);
988 }
989 /* Store the value 4 bytes at a time. This means that things
990 larger than 4 bytes may go partly in registers and partly
991 on the stack. */
c5aa993b
JM		 992 len -= REGISTER_RAW_SIZE (argreg);
993 val += REGISTER_RAW_SIZE (argreg);
c906108c
SS		 994 }
995 }
996 return sp;
997}
998
999/* Function: push_return_address (pc)
1000 Set up the return address for the inferior function call.
1001 Needed for targets where we don't actually execute a JSR/BSR instruction */
1002
cc17453a 1003static CORE_ADDR
fba45db2 1004sh_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
c906108c
SS		 1005{
1006 write_register (PR_REGNUM, CALL_DUMMY_ADDRESS ());
1007 return sp;
1008}
1009
1010/* Function: fix_call_dummy
1011 Poke the callee function's address into the destination part of
1012 the CALL_DUMMY. The address is actually stored in a data word
1013 following the actualy CALL_DUMMY instructions, which will load
1014 it into a register using PC-relative addressing. This function
1015 expects the CALL_DUMMY to look like this:
1016
c5aa993b
JM		 1017 mov.w @(2,PC), R8
1018 jsr @R8
1019 nop
1020 trap
1021 <destination>
1022 */
c906108c
SS		 1023
1024#if 0
1025void
fba45db2
KB		 1026sh_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
1027 value_ptr *args, struct type *type, int gcc_p)
c906108c
SS		 1028{
1029 *(unsigned long *) (dummy + 8) = fun;
1030}
1031#endif
1032
cc17453a
EZ		 1033static int
1034sh_coerce_float_to_double (struct type *formal, struct type *actual)
1035{
1036 return 1;
1037}
c906108c 1038
cc17453a
EZ		 1039/* Find a function's return value in the appropriate registers (in
1040 regbuf), and copy it into valbuf. Extract from an array REGBUF
1041 containing the (raw) register state a function return value of type
1042 TYPE, and copy that, in virtual format, into VALBUF. */
1043static void
fba45db2 1044sh_extract_return_value (struct type *type, char *regbuf, char *valbuf)
c906108c 1045{
cc17453a 1046 int len = TYPE_LENGTH (type);
c906108c 1047
cc17453a
EZ		 1048 if (len <= 4)
1049 memcpy (valbuf, ((char *) regbuf) + 4 - len, len);
1050 else if (len <= 8)
1051 memcpy (valbuf, ((char *) regbuf) + 8 - len, len);
1052 else
1053 error ("bad size for return value");
1054}
c906108c 1055
cc17453a
EZ		 1056/* Write into appropriate registers a function return value
1057 of type TYPE, given in virtual format.
1058 If the architecture is sh4 or sh3e, store a function's return value
1059 in the R0 general register or in the FP0 floating point register,
1060 depending on the type of the return value. In all the other cases
1061 the result is stored in r0. */
1062static void
1063sh_default_store_return_value (struct type *type, char *valbuf)
1064{
1065 write_register_bytes (REGISTER_BYTE (0),
1066 valbuf, TYPE_LENGTH (type));
1067}
c906108c 1068
cc17453a
EZ		 1069static void
1070sh3e_sh4_store_return_value (struct type *type, char *valbuf)
1071{
1072 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1073 write_register_bytes (REGISTER_BYTE (FP0_REGNUM),
1074 valbuf, TYPE_LENGTH (type));
1075 else
1076 write_register_bytes (REGISTER_BYTE (0),
1077 valbuf, TYPE_LENGTH (type));
c906108c
SS		 1078}
1079
cc17453a 1080
c906108c
SS		 1081/* Print the registers in a form similar to the E7000 */
1082
1083static void
fba45db2 1084sh_generic_show_regs (void)
c906108c 1085{
cc17453a
EZ		 1086 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1087 paddr (read_register (PC_REGNUM)),
1088 (long) read_register (SR_REGNUM),
1089 (long) read_register (PR_REGNUM),
1090 (long) read_register (MACH_REGNUM),
1091 (long) read_register (MACL_REGNUM));
1092
1093 printf_filtered ("GBR=%08lx VBR=%08lx",
1094 (long) read_register (GBR_REGNUM),
1095 (long) read_register (VBR_REGNUM));
1096
1097 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1098 (long) read_register (0),
1099 (long) read_register (1),
1100 (long) read_register (2),
1101 (long) read_register (3),
1102 (long) read_register (4),
1103 (long) read_register (5),
1104 (long) read_register (6),
1105 (long) read_register (7));
1106 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1107 (long) read_register (8),
1108 (long) read_register (9),
1109 (long) read_register (10),
1110 (long) read_register (11),
1111 (long) read_register (12),
1112 (long) read_register (13),
1113 (long) read_register (14),
1114 (long) read_register (15));
1115}
c906108c 1116
cc17453a 1117static void
fba45db2 1118sh3_show_regs (void)
cc17453a 1119{
d4f3574e
SS		 1120 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1121 paddr (read_register (PC_REGNUM)),
1122 (long) read_register (SR_REGNUM),
1123 (long) read_register (PR_REGNUM),
1124 (long) read_register (MACH_REGNUM),
1125 (long) read_register (MACL_REGNUM));
1126
1127 printf_filtered ("GBR=%08lx VBR=%08lx",
1128 (long) read_register (GBR_REGNUM),
1129 (long) read_register (VBR_REGNUM));
cc17453a
EZ		 1130 printf_filtered (" SSR=%08lx SPC=%08lx",
1131 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1132 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
c906108c 1133
d4f3574e
SS		 1134 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1135 (long) read_register (0),
1136 (long) read_register (1),
1137 (long) read_register (2),
1138 (long) read_register (3),
1139 (long) read_register (4),
1140 (long) read_register (5),
1141 (long) read_register (6),
1142 (long) read_register (7));
1143 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1144 (long) read_register (8),
1145 (long) read_register (9),
1146 (long) read_register (10),
1147 (long) read_register (11),
1148 (long) read_register (12),
1149 (long) read_register (13),
1150 (long) read_register (14),
1151 (long) read_register (15));
c906108c
SS		 1152}
1153
53116e27 1154
cc17453a 1155static void
fba45db2 1156sh3e_show_regs (void)
cc17453a
EZ		 1157{
1158 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1159 paddr (read_register (PC_REGNUM)),
1160 (long) read_register (SR_REGNUM),
1161 (long) read_register (PR_REGNUM),
1162 (long) read_register (MACH_REGNUM),
1163 (long) read_register (MACL_REGNUM));
1164
1165 printf_filtered ("GBR=%08lx VBR=%08lx",
1166 (long) read_register (GBR_REGNUM),
1167 (long) read_register (VBR_REGNUM));
1168 printf_filtered (" SSR=%08lx SPC=%08lx",
1169 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1170 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
1171 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1172 (long) read_register (gdbarch_tdep (current_gdbarch)->FPUL_REGNUM),
1173 (long) read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM));
c906108c 1174
cc17453a
EZ		 1175 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1176 (long) read_register (0),
1177 (long) read_register (1),
1178 (long) read_register (2),
1179 (long) read_register (3),
1180 (long) read_register (4),
1181 (long) read_register (5),
1182 (long) read_register (6),
1183 (long) read_register (7));
1184 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1185 (long) read_register (8),
1186 (long) read_register (9),
1187 (long) read_register (10),
1188 (long) read_register (11),
1189 (long) read_register (12),
1190 (long) read_register (13),
1191 (long) read_register (14),
1192 (long) read_register (15));
1193
1194 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1195 (long) read_register (FP0_REGNUM + 0),
1196 (long) read_register (FP0_REGNUM + 1),
1197 (long) read_register (FP0_REGNUM + 2),
1198 (long) read_register (FP0_REGNUM + 3),
1199 (long) read_register (FP0_REGNUM + 4),
1200 (long) read_register (FP0_REGNUM + 5),
1201 (long) read_register (FP0_REGNUM + 6),
1202 (long) read_register (FP0_REGNUM + 7));
1203 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1204 (long) read_register (FP0_REGNUM + 8),
1205 (long) read_register (FP0_REGNUM + 9),
1206 (long) read_register (FP0_REGNUM + 10),
1207 (long) read_register (FP0_REGNUM + 11),
1208 (long) read_register (FP0_REGNUM + 12),
1209 (long) read_register (FP0_REGNUM + 13),
1210 (long) read_register (FP0_REGNUM + 14),
1211 (long) read_register (FP0_REGNUM + 15));
1212}
1213
1214static void
fba45db2 1215sh3_dsp_show_regs (void)
c906108c 1216{
cc17453a
EZ		 1217 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1218 paddr (read_register (PC_REGNUM)),
1219 (long) read_register (SR_REGNUM),
1220 (long) read_register (PR_REGNUM),
1221 (long) read_register (MACH_REGNUM),
1222 (long) read_register (MACL_REGNUM));
c906108c 1223
cc17453a
EZ		 1224 printf_filtered ("GBR=%08lx VBR=%08lx",
1225 (long) read_register (GBR_REGNUM),
1226 (long) read_register (VBR_REGNUM));
1227
1228 printf_filtered (" SSR=%08lx SPC=%08lx",
1229 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1230 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
1231
1232 printf_filtered (" DSR=%08lx",
1233 (long) read_register (gdbarch_tdep (current_gdbarch)->DSR_REGNUM));
1234
1235 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1236 (long) read_register (0),
1237 (long) read_register (1),
1238 (long) read_register (2),
1239 (long) read_register (3),
1240 (long) read_register (4),
1241 (long) read_register (5),
1242 (long) read_register (6),
1243 (long) read_register (7));
1244 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1245 (long) read_register (8),
1246 (long) read_register (9),
1247 (long) read_register (10),
1248 (long) read_register (11),
1249 (long) read_register (12),
1250 (long) read_register (13),
1251 (long) read_register (14),
1252 (long) read_register (15));
1253
1254 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1255 (long) read_register (gdbarch_tdep (current_gdbarch)->A0G_REGNUM) & 0xff,
1256 (long) read_register (gdbarch_tdep (current_gdbarch)->A0_REGNUM),
1257 (long) read_register (gdbarch_tdep (current_gdbarch)->M0_REGNUM),
1258 (long) read_register (gdbarch_tdep (current_gdbarch)->X0_REGNUM),
1259 (long) read_register (gdbarch_tdep (current_gdbarch)->Y0_REGNUM),
1260 (long) read_register (gdbarch_tdep (current_gdbarch)->RS_REGNUM),
1261 (long) read_register (gdbarch_tdep (current_gdbarch)->MOD_REGNUM));
1262 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1263 (long) read_register (gdbarch_tdep (current_gdbarch)->A1G_REGNUM) & 0xff,
1264 (long) read_register (gdbarch_tdep (current_gdbarch)->A1_REGNUM),
1265 (long) read_register (gdbarch_tdep (current_gdbarch)->M1_REGNUM),
1266 (long) read_register (gdbarch_tdep (current_gdbarch)->X1_REGNUM),
1267 (long) read_register (gdbarch_tdep (current_gdbarch)->Y1_REGNUM),
1268 (long) read_register (gdbarch_tdep (current_gdbarch)->RE_REGNUM));
c906108c
SS		 1269}
1270
cc17453a 1271static void
fba45db2 1272sh4_show_regs (void)
cc17453a
EZ		 1273{
1274 int pr = read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM) & 0x80000;
1275 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1276 paddr (read_register (PC_REGNUM)),
1277 (long) read_register (SR_REGNUM),
1278 (long) read_register (PR_REGNUM),
1279 (long) read_register (MACH_REGNUM),
1280 (long) read_register (MACL_REGNUM));
1281
1282 printf_filtered ("GBR=%08lx VBR=%08lx",
1283 (long) read_register (GBR_REGNUM),
1284 (long) read_register (VBR_REGNUM));
1285 printf_filtered (" SSR=%08lx SPC=%08lx",
1286 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1287 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
1288 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1289 (long) read_register (gdbarch_tdep (current_gdbarch)->FPUL_REGNUM),
1290 (long) read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM));
1291
1292 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1293 (long) read_register (0),
1294 (long) read_register (1),
1295 (long) read_register (2),
1296 (long) read_register (3),
1297 (long) read_register (4),
1298 (long) read_register (5),
1299 (long) read_register (6),
1300 (long) read_register (7));
1301 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1302 (long) read_register (8),
1303 (long) read_register (9),
1304 (long) read_register (10),
1305 (long) read_register (11),
1306 (long) read_register (12),
1307 (long) read_register (13),
1308 (long) read_register (14),
1309 (long) read_register (15));
1310
1311 printf_filtered ((pr
1312 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1313 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1314 (long) read_register (FP0_REGNUM + 0),
1315 (long) read_register (FP0_REGNUM + 1),
1316 (long) read_register (FP0_REGNUM + 2),
1317 (long) read_register (FP0_REGNUM + 3),
1318 (long) read_register (FP0_REGNUM + 4),
1319 (long) read_register (FP0_REGNUM + 5),
1320 (long) read_register (FP0_REGNUM + 6),
1321 (long) read_register (FP0_REGNUM + 7));
1322 printf_filtered ((pr
1323 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1324 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1325 (long) read_register (FP0_REGNUM + 8),
1326 (long) read_register (FP0_REGNUM + 9),
1327 (long) read_register (FP0_REGNUM + 10),
1328 (long) read_register (FP0_REGNUM + 11),
1329 (long) read_register (FP0_REGNUM + 12),
1330 (long) read_register (FP0_REGNUM + 13),
1331 (long) read_register (FP0_REGNUM + 14),
1332 (long) read_register (FP0_REGNUM + 15));
1333}
1334
1335static void
fba45db2 1336sh_dsp_show_regs (void)
cc17453a
EZ		 1337{
1338 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1339 paddr (read_register (PC_REGNUM)),
1340 (long) read_register (SR_REGNUM),
1341 (long) read_register (PR_REGNUM),
1342 (long) read_register (MACH_REGNUM),
1343 (long) read_register (MACL_REGNUM));
1344
1345 printf_filtered ("GBR=%08lx VBR=%08lx",
1346 (long) read_register (GBR_REGNUM),
1347 (long) read_register (VBR_REGNUM));
1348
1349 printf_filtered (" DSR=%08lx",
1350 (long) read_register (gdbarch_tdep (current_gdbarch)->DSR_REGNUM));
1351
1352 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1353 (long) read_register (0),
1354 (long) read_register (1),
1355 (long) read_register (2),
1356 (long) read_register (3),
1357 (long) read_register (4),
1358 (long) read_register (5),
1359 (long) read_register (6),
1360 (long) read_register (7));
1361 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1362 (long) read_register (8),
1363 (long) read_register (9),
1364 (long) read_register (10),
1365 (long) read_register (11),
1366 (long) read_register (12),
1367 (long) read_register (13),
1368 (long) read_register (14),
1369 (long) read_register (15));
1370
1371 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1372 (long) read_register (gdbarch_tdep (current_gdbarch)->A0G_REGNUM) & 0xff,
1373 (long) read_register (gdbarch_tdep (current_gdbarch)->A0_REGNUM),
1374 (long) read_register (gdbarch_tdep (current_gdbarch)->M0_REGNUM),
1375 (long) read_register (gdbarch_tdep (current_gdbarch)->X0_REGNUM),
1376 (long) read_register (gdbarch_tdep (current_gdbarch)->Y0_REGNUM),
1377 (long) read_register (gdbarch_tdep (current_gdbarch)->RS_REGNUM),
1378 (long) read_register (gdbarch_tdep (current_gdbarch)->MOD_REGNUM));
1379 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1380 (long) read_register (gdbarch_tdep (current_gdbarch)->A1G_REGNUM) & 0xff,
1381 (long) read_register (gdbarch_tdep (current_gdbarch)->A1_REGNUM),
1382 (long) read_register (gdbarch_tdep (current_gdbarch)->M1_REGNUM),
1383 (long) read_register (gdbarch_tdep (current_gdbarch)->X1_REGNUM),
1384 (long) read_register (gdbarch_tdep (current_gdbarch)->Y1_REGNUM),
1385 (long) read_register (gdbarch_tdep (current_gdbarch)->RE_REGNUM));
1386}
1387
53116e27
EZ		 1388void sh_show_regs_command (char *args, int from_tty)
1389{
1390 if (sh_show_regs)
1391 (*sh_show_regs)();
1392}
1393
cc17453a
EZ		 1394/* Index within `registers' of the first byte of the space for
1395 register N. */
1396static int
fba45db2 1397sh_default_register_byte (int reg_nr)
8db62801 1398{
cc17453a
EZ		 1399 return (reg_nr * 4);
1400}
1401
53116e27 1402static int
fba45db2 1403sh_sh4_register_byte (int reg_nr)
53116e27
EZ		 1404{
1405 if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1406 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27
EZ		 1407 return (dr_reg_base_num (reg_nr) * 4);
1408 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
e6c42fda 1409 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1410 return (fv_reg_base_num (reg_nr) * 4);
1411 else
1412 return (reg_nr * 4);
1413}
1414
cc17453a
EZ		 1415/* Number of bytes of storage in the actual machine representation for
1416 register REG_NR. */
1417static int
fba45db2 1418sh_default_register_raw_size (int reg_nr)
cc17453a
EZ		 1419{
1420 return 4;
1421}
1422
53116e27 1423static int
fba45db2 1424sh_sh4_register_raw_size (int reg_nr)
53116e27
EZ		 1425{
1426 if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1427 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27
EZ		 1428 return 8;
1429 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
e6c42fda 1430 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1431 return 16;
1432 else
1433 return 4;
1434}
1435
cc17453a
EZ		 1436/* Number of bytes of storage in the program's representation
1437 for register N. */
1438static int
fba45db2 1439sh_register_virtual_size (int reg_nr)
cc17453a
EZ		 1440{
1441 return 4;
1442}
1443
1444/* Return the GDB type object for the "standard" data type
1445 of data in register N. */
1446
1447static struct type *
fba45db2 1448sh_sh3e_register_virtual_type (int reg_nr)
cc17453a
EZ		 1449{
1450 if ((reg_nr >= FP0_REGNUM
e6c42fda 1451 && (reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM))
cc17453a
EZ		 1452 || (reg_nr == gdbarch_tdep (current_gdbarch)->FPUL_REGNUM))
1453 return builtin_type_float;
8db62801 1454 else
cc17453a
EZ		 1455 return builtin_type_int;
1456}
1457
53116e27 1458static struct type *
fba45db2 1459sh_sh4_register_virtual_type (int reg_nr)
53116e27
EZ		 1460{
1461 if ((reg_nr >= FP0_REGNUM
e6c42fda 1462 && (reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM))
53116e27
EZ		 1463 || (reg_nr == gdbarch_tdep (current_gdbarch)->FPUL_REGNUM))
1464 return builtin_type_float;
1465 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1466 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27
EZ		 1467 return builtin_type_double;
1468 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
e6c42fda 1469 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1470 return sh_sh4_build_float_register_type (3);
1471 else
1472 return builtin_type_int;
1473}
1474
1475static struct type *
1476sh_sh4_build_float_register_type (int high)
1477{
1478 struct type *temp;
1479
1480 temp = create_range_type (NULL, builtin_type_int, 0, high);
1481 return create_array_type (NULL, builtin_type_float, temp);
1482}
1483
cc17453a 1484static struct type *
fba45db2 1485sh_default_register_virtual_type (int reg_nr)
cc17453a
EZ		 1486{
1487 return builtin_type_int;
1488}
1489
fb409745
EZ		 1490/* On the sh4, the DRi pseudo registers are problematic if the target
1491 is little endian. When the user writes one of those registers, for
1492 instance with 'ser var $dr0=1', we want the double to be stored
1493 like this:
1494 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1495 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1496
1497 This corresponds to little endian byte order & big endian word
1498 order. However if we let gdb write the register w/o conversion, it
1499 will write fr0 and fr1 this way:
1500 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1501 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1502 because it will consider fr0 and fr1 as a single LE stretch of memory.
1503
1504 To achieve what we want we must force gdb to store things in
1505 floatformat_ieee_double_littlebyte_bigword (which is defined in
1506 include/floatformat.h and libiberty/floatformat.c.
1507
1508 In case the target is big endian, there is no problem, the
1509 raw bytes will look like:
1510 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1511 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1512
1513 The other pseudo registers (the FVs) also don't pose a problem
1514 because they are stored as 4 individual FP elements. */
1515
1516int
1517sh_sh4_register_convertible (int nr)
1518{
1519 if (TARGET_BYTE_ORDER == LITTLE_ENDIAN)
1520 return (gdbarch_tdep (current_gdbarch)->DR0_REGNUM <= nr
e6c42fda 1521 && nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM);
fb409745
EZ		 1522 else
1523 return 0;
1524}
1525
1526void
1527sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
1528 char *from, char *to)
1529{
1530 if (regnum >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1531 && regnum <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
fb409745
EZ		 1532 {
1533 DOUBLEST val;
1534 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
1535 store_floating(to, TYPE_LENGTH(type), val);
1536 }
1537 else
1538 error("sh_register_convert_to_virtual called with non DR register number");
1539}
1540
1541void
1542sh_sh4_register_convert_to_raw (struct type *type, int regnum,
1543 char *from, char *to)
1544{
1545 if (regnum >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1546 && regnum <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
fb409745
EZ		 1547 {
1548 DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
1549 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
1550 }
1551 else
1552 error("sh_register_convert_to_raw called with non DR register number");
1553}
1554
53116e27
EZ		 1555void
1556sh_fetch_pseudo_register (int reg_nr)
1557{
1558 int base_regnum, portion;
1559
1560 if (!register_cached (reg_nr))
1561 {
1562 if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1563 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27
EZ		 1564 {
1565 base_regnum = dr_reg_base_num (reg_nr);
1566
1567 /* Read the real regs for which this one is an alias. */
1568 for (portion = 0; portion < 2; portion++)
1569 if (!register_cached (base_regnum + portion))
1570 target_fetch_registers (base_regnum + portion);
1571 }
1572 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
e6c42fda 1573 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1574 {
1575 base_regnum = fv_reg_base_num (reg_nr);
1576
1577 /* Read the real regs for which this one is an alias. */
1578 for (portion = 0; portion < 4; portion++)
1579 if (!register_cached (base_regnum + portion))
1580 target_fetch_registers (base_regnum + portion);
1581
1582 }
1583 register_valid [reg_nr] = 1;
1584 }
1585}
1586
1587void
1588sh_store_pseudo_register (int reg_nr)
1589{
1590 int base_regnum, portion;
1591
1592 if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1593 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27
EZ		 1594 {
1595 base_regnum = dr_reg_base_num (reg_nr);
1596
1597 /* Write the real regs for which this one is an alias. */
1598 for (portion = 0; portion < 2; portion++)
1599 {
1600 register_valid[base_regnum + portion] = 1;
1601 target_store_registers (base_regnum + portion);
1602 }
1603 }
1604 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
e6c42fda 1605 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1606 {
1607 base_regnum = fv_reg_base_num (reg_nr);
1608
1609 /* Write the real regs for which this one is an alias. */
1610 for (portion = 0; portion < 4; portion++)
1611 {
1612 register_valid[base_regnum + portion] = 1;
1613 target_store_registers (base_regnum + portion);
1614 }
1615 }
1616}
1617
1618static int
1619fv_reg_base_num (int fv_regnum)
1620{
1621 int fp_regnum;
1622
1623 fp_regnum = FP0_REGNUM +
1624 (fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM) * 4;
1625 return fp_regnum;
1626}
1627
1628static int
1629dr_reg_base_num (int dr_regnum)
1630{
1631 int fp_regnum;
1632
1633 fp_regnum = FP0_REGNUM +
1634 (dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM) * 2;
1635 return fp_regnum;
1636}
1637
1638static void
1639do_fv_register_info (int fv_regnum)
1640{
1641 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
1642 printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1643 fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM,
1644 (int) read_register (first_fp_reg_num),
1645 (int) read_register (first_fp_reg_num + 1),
1646 (int) read_register (first_fp_reg_num + 2),
1647 (int) read_register (first_fp_reg_num + 3));
1648}
1649
1650static void
1651do_dr_register_info (int dr_regnum)
1652{
1653 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1654
1655 printf_filtered ("dr%d\t0x%08x%08x\n",
1656 dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM,
1657 (int) read_register (first_fp_reg_num),
1658 (int) read_register (first_fp_reg_num + 1));
1659}
1660
1661static void
1662sh_do_pseudo_register (int regnum)
1663{
1664 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
8e1a459b 1665 internal_error ("Invalid pseudo register number %d\n", regnum);
53116e27
EZ		 1666 else if (regnum >= NUM_REGS &&
1667 regnum < gdbarch_tdep (current_gdbarch)->FV0_REGNUM)
1668 do_dr_register_info (regnum);
1669 else if (regnum >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM &&
e6c42fda 1670 regnum <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1671 do_fv_register_info (regnum);
1672}
1673
1674
1675static void
1676sh_do_fp_register (int regnum)
1677{ /* do values for FP (float) regs */
1678 char *raw_buffer;
1679 double flt; /* double extracted from raw hex data */
1680 int inv;
1681 int j;
1682
1683 /* Allocate space for the float. */
1684 raw_buffer = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM));
1685
1686 /* Get the data in raw format. */
1687 if (read_relative_register_raw_bytes (regnum, raw_buffer))
1688 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1689
1690 /* Get the register as a number */
1691 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1692
1693 /* Print the name and some spaces. */
1694 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
1695 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
1696
1697 /* Print the value. */
1698 printf_filtered (inv ? "<invalid float>" : "%-10.9g", flt);
1699
1700 /* Print the fp register as hex. */
1701 printf_filtered ("\t(raw 0x");
1702 for (j = 0; j < REGISTER_RAW_SIZE (regnum); j++)
1703 {
1704 register int idx = TARGET_BYTE_ORDER == BIG_ENDIAN ? j
1705 : REGISTER_RAW_SIZE (regnum) - 1 - j;
1706 printf_filtered ("%02x", (unsigned char) raw_buffer[idx]);
1707 }
1708 printf_filtered (")");
1709 printf_filtered ("\n");
1710}
1711
1712static void
1713sh_do_register (int regnum)
1714{
1715 char raw_buffer[MAX_REGISTER_RAW_SIZE];
1716
1717 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
1718 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
1719
1720 /* Get the data in raw format. */
1721 if (read_relative_register_raw_bytes (regnum, raw_buffer))
1722 printf_filtered ("*value not available*\n");
1723
1724 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
1725 gdb_stdout, 'x', 1, 0, Val_pretty_default);
1726 printf_filtered ("\t");
1727 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
1728 gdb_stdout, 0, 1, 0, Val_pretty_default);
1729 printf_filtered ("\n");
1730}
1731
1732static void
1733sh_print_register (int regnum)
1734{
1735 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1736 internal_error ("Invalid register number %d\n", regnum);
1737
1738 else if (regnum > 0 && regnum < NUM_REGS)
1739 {
1740 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
1741 sh_do_fp_register (regnum); /* FP regs */
1742 else
1743 sh_do_register (regnum); /* All other regs */
1744 }
1745
1746 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1747 sh_do_pseudo_register (regnum);
1748}
1749
1750void
1751sh_do_registers_info (int regnum, int fpregs)
1752{
1753 if (regnum != -1) /* do one specified register */
1754 {
1755 if (*(REGISTER_NAME (regnum)) == '\0')
1756 error ("Not a valid register for the current processor type");
1757
1758 sh_print_register (regnum);
1759 }
1760 else
1761 /* do all (or most) registers */
1762 {
1763 regnum = 0;
1764 while (regnum < NUM_REGS)
1765 {
1766 /* If the register name is empty, it is undefined for this
1767 processor, so don't display anything. */
1768 if (REGISTER_NAME (regnum) == NULL
1769 || *(REGISTER_NAME (regnum)) == '\0')
1770 {
1771 regnum++;
1772 continue;
1773 }
1774
1775 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
1776 {
1777 if (fpregs)
1778 {
1779 /* true for "INFO ALL-REGISTERS" command */
1780 sh_do_fp_register (regnum); /* FP regs */
1781 regnum ++;
1782 }
1783 else
e6c42fda 1784 regnum += (gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
53116e27
EZ		 1785 }
1786 else
1787 {
1788 sh_do_register (regnum); /* All other regs */
1789 regnum++;
1790 }
1791 }
1792
1793 if (fpregs)
1794 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1795 {
1796 sh_do_pseudo_register (regnum);
1797 regnum++;
1798 }
1799 }
1800}
1801
1a8629c7
MS		 1802#ifdef SVR4_SHARED_LIBS
1803
1804/* Fetch (and possibly build) an appropriate link_map_offsets structure
1805 for native i386 linux targets using the struct offsets defined in
1806 link.h (but without actual reference to that file).
1807
1808 This makes it possible to access i386-linux shared libraries from
1809 a gdb that was not built on an i386-linux host (for cross debugging).
1810 */
1811
1812struct link_map_offsets *
1813sh_linux_svr4_fetch_link_map_offsets (void)
1814{
1815 static struct link_map_offsets lmo;
1816 static struct link_map_offsets *lmp = 0;
1817
1818 if (lmp == 0)
1819 {
1820 lmp = &lmo;
1821
1822 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
1823
1824 lmo.r_map_offset = 4;
1825 lmo.r_map_size = 4;
1826
1827 lmo.link_map_size = 20; /* 552 not actual size but all we need */
1828
1829 lmo.l_addr_offset = 0;
1830 lmo.l_addr_size = 4;
1831
1832 lmo.l_name_offset = 4;
1833 lmo.l_name_size = 4;
1834
1835 lmo.l_next_offset = 12;
1836 lmo.l_next_size = 4;
1837
1838 lmo.l_prev_offset = 16;
1839 lmo.l_prev_size = 4;
1840 }
1841
1842 return lmp;
1843}
1844#endif /* SVR4_SHARED_LIBS */
1845
cc17453a
EZ		 1846static gdbarch_init_ftype sh_gdbarch_init;
1847
1848static struct gdbarch *
fba45db2 1849sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
cc17453a
EZ		 1850{
1851 static LONGEST sh_call_dummy_words[] = {0};
1852 struct gdbarch *gdbarch;
1853 struct gdbarch_tdep *tdep;
1854 gdbarch_register_name_ftype *sh_register_name;
1855 gdbarch_store_return_value_ftype *sh_store_return_value;
1856 gdbarch_register_virtual_type_ftype *sh_register_virtual_type;
1857
1858 /* Find a candidate among the list of pre-declared architectures. */
1859 arches = gdbarch_list_lookup_by_info (arches, &info);
1860 if (arches != NULL)
1861 return arches->gdbarch;
1862
1863 /* None found, create a new architecture from the information
1864 provided. */
1865 tdep = XMALLOC (struct gdbarch_tdep);
1866 gdbarch = gdbarch_alloc (&info, tdep);
1867
1868 /* Initialize the register numbers that are not common to all the
1869 variants to -1, if necessary thse will be overwritten in the case
1870 statement below. */
1871 tdep->FPUL_REGNUM = -1;
1872 tdep->FPSCR_REGNUM = -1;
1873 tdep->DSR_REGNUM = -1;
e6c42fda 1874 tdep->FP_LAST_REGNUM = -1;
cc17453a
EZ		 1875 tdep->A0G_REGNUM = -1;
1876 tdep->A0_REGNUM = -1;
1877 tdep->A1G_REGNUM = -1;
1878 tdep->A1_REGNUM = -1;
1879 tdep->M0_REGNUM = -1;
1880 tdep->M1_REGNUM = -1;
1881 tdep->X0_REGNUM = -1;
1882 tdep->X1_REGNUM = -1;
1883 tdep->Y0_REGNUM = -1;
1884 tdep->Y1_REGNUM = -1;
1885 tdep->MOD_REGNUM = -1;
1886 tdep->RS_REGNUM = -1;
1887 tdep->RE_REGNUM = -1;
1888 tdep->SSR_REGNUM = -1;
1889 tdep->SPC_REGNUM = -1;
53116e27 1890 tdep->DR0_REGNUM = -1;
e6c42fda 1891 tdep->DR_LAST_REGNUM = -1;
53116e27 1892 tdep->FV0_REGNUM = -1;
e6c42fda 1893 tdep->FV_LAST_REGNUM = -1;
cc17453a 1894 set_gdbarch_fp0_regnum (gdbarch, -1);
53116e27
EZ		 1895 set_gdbarch_num_pseudo_regs (gdbarch, 0);
1896 set_gdbarch_max_register_raw_size (gdbarch, 4);
1897 set_gdbarch_max_register_virtual_size (gdbarch, 4);
e6c42fda 1898 print_sh_insn = gdb_print_insn_sh;
cc17453a
EZ		 1899
1900 switch (info.bfd_arch_info->mach)
8db62801 1901 {
cc17453a
EZ		 1902 case bfd_mach_sh:
1903 sh_register_name = sh_sh_register_name;
1904 sh_show_regs = sh_generic_show_regs;
1905 sh_store_return_value = sh_default_store_return_value;
1906 sh_register_virtual_type = sh_default_register_virtual_type;
1907 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1908 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1909 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1910 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1911 break;
1912 case bfd_mach_sh2:
1913 sh_register_name = sh_sh_register_name;
1914 sh_show_regs = sh_generic_show_regs;
1915 sh_store_return_value = sh_default_store_return_value;
1916 sh_register_virtual_type = sh_default_register_virtual_type;
1917 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1918 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1919 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1920 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1921 break;
1922 case bfd_mach_sh_dsp:
1923 sh_register_name = sh_sh_dsp_register_name;
1924 sh_show_regs = sh_dsp_show_regs;
1925 sh_store_return_value = sh_default_store_return_value;
1926 sh_register_virtual_type = sh_default_register_virtual_type;
1927 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1928 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1929 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1930 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1931 tdep->DSR_REGNUM = 24;
1932 tdep->A0G_REGNUM = 25;
1933 tdep->A0_REGNUM = 26;
1934 tdep->A1G_REGNUM = 27;
1935 tdep->A1_REGNUM = 28;
1936 tdep->M0_REGNUM = 29;
1937 tdep->M1_REGNUM = 30;
1938 tdep->X0_REGNUM = 31;
1939 tdep->X1_REGNUM = 32;
1940 tdep->Y0_REGNUM = 33;
1941 tdep->Y1_REGNUM = 34;
1942 tdep->MOD_REGNUM = 40;
1943 tdep->RS_REGNUM = 43;
1944 tdep->RE_REGNUM = 44;
1945 break;
1946 case bfd_mach_sh3:
1947 sh_register_name = sh_sh3_register_name;
1948 sh_show_regs = sh3_show_regs;
1949 sh_store_return_value = sh_default_store_return_value;
1950 sh_register_virtual_type = sh_default_register_virtual_type;
1951 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1952 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1953 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1954 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1955 tdep->SSR_REGNUM = 41;
1956 tdep->SPC_REGNUM = 42;
1957 break;
1958 case bfd_mach_sh3e:
1959 sh_register_name = sh_sh3e_register_name;
1960 sh_show_regs = sh3e_show_regs;
1961 sh_store_return_value = sh3e_sh4_store_return_value;
1962 sh_register_virtual_type = sh_sh3e_register_virtual_type;
1963 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
53116e27
EZ		 1964 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1965 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1966 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1967 set_gdbarch_fp0_regnum (gdbarch, 25);
1968 tdep->FPUL_REGNUM = 23;
1969 tdep->FPSCR_REGNUM = 24;
e6c42fda 1970 tdep->FP_LAST_REGNUM = 40;
cc17453a
EZ		 1971 tdep->SSR_REGNUM = 41;
1972 tdep->SPC_REGNUM = 42;
1973 break;
1974 case bfd_mach_sh3_dsp:
1975 sh_register_name = sh_sh3_dsp_register_name;
1976 sh_show_regs = sh3_dsp_show_regs;
1977 sh_store_return_value = sh_default_store_return_value;
1978 sh_register_virtual_type = sh_default_register_virtual_type;
1979 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1980 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1981 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1982 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1983 tdep->DSR_REGNUM = 24;
1984 tdep->A0G_REGNUM = 25;
1985 tdep->A0_REGNUM = 26;
1986 tdep->A1G_REGNUM = 27;
1987 tdep->A1_REGNUM = 28;
1988 tdep->M0_REGNUM = 29;
1989 tdep->M1_REGNUM = 30;
1990 tdep->X0_REGNUM = 31;
1991 tdep->X1_REGNUM = 32;
1992 tdep->Y0_REGNUM = 33;
1993 tdep->Y1_REGNUM = 34;
1994 tdep->MOD_REGNUM = 40;
1995 tdep->RS_REGNUM = 43;
1996 tdep->RE_REGNUM = 44;
1997 tdep->SSR_REGNUM = 41;
1998 tdep->SPC_REGNUM = 42;
1999 break;
2000 case bfd_mach_sh4:
53116e27
EZ		 2001 sh_register_name = sh_sh4_register_name;
2002 sh_show_regs = sh4_show_regs;
cc17453a 2003 sh_store_return_value = sh3e_sh4_store_return_value;
53116e27 2004 sh_register_virtual_type = sh_sh4_register_virtual_type;
cc17453a
EZ		 2005 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
2006 set_gdbarch_fp0_regnum (gdbarch, 25);
53116e27
EZ		 2007 set_gdbarch_register_raw_size (gdbarch, sh_sh4_register_raw_size);
2008 set_gdbarch_register_virtual_size (gdbarch, sh_sh4_register_raw_size);
2009 set_gdbarch_register_byte (gdbarch, sh_sh4_register_byte);
2010 set_gdbarch_num_pseudo_regs (gdbarch, 12);
2011 set_gdbarch_max_register_raw_size (gdbarch, 4 * 4);
2012 set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4);
fb409745
EZ		 2013 set_gdbarch_register_convert_to_raw (gdbarch, sh_sh4_register_convert_to_raw);
2014 set_gdbarch_register_convert_to_virtual (gdbarch, sh_sh4_register_convert_to_virtual);
2015 set_gdbarch_register_convertible (gdbarch, sh_sh4_register_convertible);
cc17453a
EZ		 2016 tdep->FPUL_REGNUM = 23;
2017 tdep->FPSCR_REGNUM = 24;
e6c42fda 2018 tdep->FP_LAST_REGNUM = 40;
cc17453a
EZ		 2019 tdep->SSR_REGNUM = 41;
2020 tdep->SPC_REGNUM = 42;
53116e27 2021 tdep->DR0_REGNUM = 59;
e6c42fda 2022 tdep->DR_LAST_REGNUM = 66;
53116e27 2023 tdep->FV0_REGNUM = 67;
e6c42fda 2024 tdep->FV_LAST_REGNUM = 70;
cc17453a
EZ		 2025 break;
2026 default:
2027 sh_register_name = sh_generic_register_name;
2028 sh_show_regs = sh_generic_show_regs;
2029 sh_store_return_value = sh_default_store_return_value;
2030 sh_register_virtual_type = sh_default_register_virtual_type;
2031 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 2032 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
2033 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
2034 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a 2035 break;
8db62801 2036 }
cc17453a
EZ		 2037
2038 set_gdbarch_read_pc (gdbarch, generic_target_read_pc);
2039 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2040 set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
2041 set_gdbarch_write_fp (gdbarch, generic_target_write_fp);
2042 set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
2043 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
2044
2045 set_gdbarch_num_regs (gdbarch, 59);
2046 set_gdbarch_sp_regnum (gdbarch, 15);
2047 set_gdbarch_fp_regnum (gdbarch, 14);
2048 set_gdbarch_pc_regnum (gdbarch, 16);
2049 set_gdbarch_register_name (gdbarch, sh_register_name);
2050 set_gdbarch_register_size (gdbarch, 4);
2051 set_gdbarch_register_bytes (gdbarch, NUM_REGS * 4);
cc17453a
EZ		 2052 set_gdbarch_register_virtual_type (gdbarch, sh_register_virtual_type);
2053
2054 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2055 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2056 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2057 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2058 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2059 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2060 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2061 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
2062
2063 set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
2064 set_gdbarch_call_dummy_length (gdbarch, 0);
2065 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
2066 set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
2067 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); /*???*/
2068 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
2069 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
2070 set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
2071 set_gdbarch_call_dummy_words (gdbarch, sh_call_dummy_words);
2072 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (sh_call_dummy_words));
2073 set_gdbarch_call_dummy_p (gdbarch, 1);
2074 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
2075 set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
2076 set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
2077 set_gdbarch_coerce_float_to_double (gdbarch,
2078 sh_coerce_float_to_double);
2079
2080 set_gdbarch_extract_return_value (gdbarch, sh_extract_return_value);
2081 set_gdbarch_push_arguments (gdbarch, sh_push_arguments);
2082 set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
2083 set_gdbarch_push_return_address (gdbarch, sh_push_return_address);
2084
2085 set_gdbarch_store_struct_return (gdbarch, sh_store_struct_return);
2086 set_gdbarch_store_return_value (gdbarch, sh_store_return_value);
2087 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
2088 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
2089 set_gdbarch_init_extra_frame_info (gdbarch, sh_init_extra_frame_info);
2090 set_gdbarch_pop_frame (gdbarch, sh_pop_frame);
2091 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2092 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2093 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2094 set_gdbarch_function_start_offset (gdbarch, 0);
2095 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2096
53116e27
EZ		 2097 set_gdbarch_fetch_pseudo_register (gdbarch, sh_fetch_pseudo_register);
2098 set_gdbarch_store_pseudo_register (gdbarch, sh_store_pseudo_register);
cc17453a
EZ		 2099 set_gdbarch_frame_args_skip (gdbarch, 0);
2100 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
2101 set_gdbarch_frame_chain (gdbarch, sh_frame_chain);
2102 set_gdbarch_frame_chain_valid (gdbarch, generic_file_frame_chain_valid);
2103 set_gdbarch_frame_saved_pc (gdbarch, sh_frame_saved_pc);
2104 set_gdbarch_frame_args_address (gdbarch, sh_frame_args_address);
2105 set_gdbarch_frame_locals_address (gdbarch, sh_frame_locals_address);
2106 set_gdbarch_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
2107 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
2108 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2109 set_gdbarch_ieee_float (gdbarch, 1);
2110
2111 return gdbarch;
8db62801
EZ		 2112}
2113
c906108c 2114void
fba45db2 2115_initialize_sh_tdep (void)
c906108c
SS		 2116{
2117 struct cmd_list_element *c;
cc17453a
EZ		 2118
2119 register_gdbarch_init (bfd_arch_sh, sh_gdbarch_init);
e6c42fda 2120 tm_print_insn = print_sh_insn;
c906108c 2121
53116e27 2122 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
c906108c 2123}
GDB Binutils - Deliverables
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