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[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
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c906108c 1/* Target-dependent code for Hitachi Super-H, for GDB.
b4a20239
AC		 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 2000 Free Software
3 Foundation, Inc.
c906108c 4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM		 7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
c906108c 11
c5aa993b
JM		 12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b
JM		 17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
c906108c
SS		 21
22/*
c5aa993b
JM		 23 Contributed by Steve Chamberlain
24 sac@cygnus.com
c906108c
SS		 25 */
26
27#include "defs.h"
28#include "frame.h"
29#include "obstack.h"
30#include "symtab.h"
31#include "symfile.h"
32#include "gdbtypes.h"
33#include "gdbcmd.h"
34#include "gdbcore.h"
35#include "value.h"
36#include "dis-asm.h"
37#include "inferior.h" /* for BEFORE_TEXT_END etc. */
38#include "gdb_string.h"
b4a20239 39#include "arch-utils.h"
fb409745 40#include "floatformat.h"
c906108c 41
cc17453a
EZ		 42#undef XMALLOC
43#define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE)))
44
53116e27
EZ		 45
46/* Frame interpretation related functions. */
cc17453a
EZ		 47static gdbarch_breakpoint_from_pc_ftype sh_breakpoint_from_pc;
48static gdbarch_frame_chain_ftype sh_frame_chain;
49static gdbarch_frame_saved_pc_ftype sh_frame_saved_pc;
50static gdbarch_skip_prologue_ftype sh_skip_prologue;
53116e27 51
cc17453a
EZ		 52static gdbarch_frame_init_saved_regs_ftype sh_nofp_frame_init_saved_regs;
53static gdbarch_frame_init_saved_regs_ftype sh_fp_frame_init_saved_regs;
53116e27
EZ		 54static gdbarch_init_extra_frame_info_ftype sh_init_extra_frame_info;
55static gdbarch_pop_frame_ftype sh_pop_frame;
56static gdbarch_saved_pc_after_call_ftype sh_saved_pc_after_call;
57static gdbarch_frame_args_address_ftype sh_frame_args_address;
58static gdbarch_frame_locals_address_ftype sh_frame_locals_address;
59
60/* Function call related functions. */
cc17453a
EZ		 61static gdbarch_extract_return_value_ftype sh_extract_return_value;
62static gdbarch_extract_struct_value_address_ftype sh_extract_struct_value_address;
63static gdbarch_use_struct_convention_ftype sh_use_struct_convention;
cc17453a
EZ		 64static gdbarch_store_struct_return_ftype sh_store_struct_return;
65static gdbarch_push_arguments_ftype sh_push_arguments;
66static gdbarch_push_return_address_ftype sh_push_return_address;
53116e27
EZ		 67static gdbarch_coerce_float_to_double_ftype sh_coerce_float_to_double;
68static gdbarch_store_return_value_ftype sh_default_store_return_value;
69static gdbarch_store_return_value_ftype sh3e_sh4_store_return_value;
cc17453a
EZ		 70
71static gdbarch_register_name_ftype sh_generic_register_name;
72static gdbarch_register_name_ftype sh_sh_register_name;
73static gdbarch_register_name_ftype sh_sh3_register_name;
74static gdbarch_register_name_ftype sh_sh3e_register_name;
75static gdbarch_register_name_ftype sh_sh_dsp_register_name;
76static gdbarch_register_name_ftype sh_sh3_dsp_register_name;
77
53116e27
EZ		 78/* Registers display related functions */
79static gdbarch_register_raw_size_ftype sh_default_register_raw_size;
80static gdbarch_register_raw_size_ftype sh_sh4_register_raw_size;
cc17453a 81
cc17453a 82static gdbarch_register_virtual_size_ftype sh_register_virtual_size;
53116e27
EZ		 83
84static gdbarch_register_byte_ftype sh_default_register_byte;
85static gdbarch_register_byte_ftype sh_sh4_register_byte;
86
cc17453a 87static gdbarch_register_virtual_type_ftype sh_sh3e_register_virtual_type;
53116e27 88static gdbarch_register_virtual_type_ftype sh_sh4_register_virtual_type;
cc17453a
EZ		 89static gdbarch_register_virtual_type_ftype sh_default_register_virtual_type;
90
53116e27
EZ		 91static void sh_generic_show_regs (void);
92static void sh3_show_regs (void);
93static void sh3e_show_regs (void);
94static void sh3_dsp_show_regs (void);
95static void sh_dsp_show_regs (void);
96static void sh4_show_regs (void);
97static void sh_show_regs_command (char *, int);
98
99static struct type *sh_sh4_build_float_register_type (int high);
100
101static gdbarch_fetch_pseudo_register_ftype sh_fetch_pseudo_register;
102static gdbarch_store_pseudo_register_ftype sh_store_pseudo_register;
103static int fv_reg_base_num (int);
104static int dr_reg_base_num (int);
105static void do_fv_register_info (int fv_regnum);
106static void do_dr_register_info (int dr_regnum);
107static void sh_do_pseudo_register (int regnum);
108static void sh_do_fp_register (int regnum);
109static void sh_do_register (int regnum);
110static void sh_print_register (int regnum);
111
112void (*sh_show_regs) (void);
113
cc17453a 114
cc17453a
EZ		 115/* Define other aspects of the stack frame.
116 we keep a copy of the worked out return pc lying around, since it
117 is a useful bit of info */
118
119struct frame_extra_info
120{
121 CORE_ADDR return_pc;
122 int leaf_function;
123 int f_offset;
63978407 124};
c906108c 125
cc17453a 126#if 0
091be84d
CF		 127#ifdef _WIN32_WCE
128char **sh_register_names = sh3_reg_names;
129#else
c906108c 130char **sh_register_names = sh_generic_reg_names;
091be84d 131#endif
cc17453a 132#endif
c906108c 133
cc17453a
EZ		 134static char *
135sh_generic_register_name (int reg_nr)
c5aa993b 136{
cc17453a 137 static char *register_names[] =
c5aa993b 138 {
cc17453a
EZ		 139 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
140 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
141 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
142 "fpul", "fpscr",
143 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
144 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
145 "ssr", "spc",
146 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
147 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
148 };
149 if (reg_nr < 0)
150 return NULL;
151 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
152 return NULL;
153 return register_names[reg_nr];
154}
155
156static char *
157sh_sh_register_name (int reg_nr)
158{
159 static char *register_names[] =
63978407 160 {
cc17453a
EZ		 161 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
162 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
163 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
164 "", "",
165 "", "", "", "", "", "", "", "",
166 "", "", "", "", "", "", "", "",
167 "", "",
168 "", "", "", "", "", "", "", "",
169 "", "", "", "", "", "", "", "",
170 };
171 if (reg_nr < 0)
172 return NULL;
173 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
174 return NULL;
175 return register_names[reg_nr];
176}
177
178static char *
179sh_sh3_register_name (int reg_nr)
180{
181 static char *register_names[] =
c5aa993b 182 {
cc17453a
EZ		 183 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
184 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
185 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
186 "", "",
187 "", "", "", "", "", "", "", "",
188 "", "", "", "", "", "", "", "",
189 "ssr", "spc",
190 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
191 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
192 };
193 if (reg_nr < 0)
194 return NULL;
195 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
196 return NULL;
197 return register_names[reg_nr];
198}
199
200static char *
201sh_sh3e_register_name (int reg_nr)
202{
203 static char *register_names[] =
63978407 204 {
cc17453a
EZ		 205 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
206 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
207 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
208 "fpul", "fpscr",
209 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
210 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
211 "ssr", "spc",
212 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
213 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
214 };
215 if (reg_nr < 0)
216 return NULL;
217 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
218 return NULL;
219 return register_names[reg_nr];
220}
221
222static char *
223sh_sh_dsp_register_name (int reg_nr)
224{
225 static char *register_names[] =
c5aa993b 226 {
cc17453a
EZ		 227 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
228 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
229 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
230 "", "dsr",
231 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
232 "y0", "y1", "", "", "", "", "", "mod",
233 "", "",
234 "rs", "re", "", "", "", "", "", "",
235 "", "", "", "", "", "", "", "",
236 };
237 if (reg_nr < 0)
238 return NULL;
239 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
240 return NULL;
241 return register_names[reg_nr];
242}
243
244static char *
245sh_sh3_dsp_register_name (int reg_nr)
246{
247 static char *register_names[] =
c5aa993b 248 {
cc17453a
EZ		 249 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
250 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
251 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
252 "", "dsr",
253 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
254 "y0", "y1", "", "", "", "", "", "mod",
255 "ssr", "spc",
256 "rs", "re", "", "", "", "", "", "",
257 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
258 "", "", "", "", "", "", "", "",
259 };
260 if (reg_nr < 0)
261 return NULL;
262 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
263 return NULL;
264 return register_names[reg_nr];
265}
266
53116e27
EZ		 267static char *
268sh_sh4_register_name (int reg_nr)
269{
270 static char *register_names[] =
271 {
272 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
273 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
274 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
275 "fpul", "fpscr",
276 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
277 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
278 "ssr", "spc",
279 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
280 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
fe9f384f
EZ		 281 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
282 "fv0", "fv4", "fv8", "fv12",
53116e27
EZ		 283 };
284 if (reg_nr < 0)
285 return NULL;
286 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
287 return NULL;
288 return register_names[reg_nr];
289}
290
cc17453a
EZ		 291static unsigned char *
292sh_breakpoint_from_pc (pcptr, lenptr)
293 CORE_ADDR *pcptr;
294 int *lenptr;
295{
296 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
297 static unsigned char breakpoint[] = {0xc3, 0xc3};
298
299 *lenptr = sizeof (breakpoint);
300 return breakpoint;
301}
c906108c
SS		 302
303/* Prologue looks like
c5aa993b
JM		 304 [mov.l <regs>,@-r15]...
305 [sts.l pr,@-r15]
306 [mov.l r14,@-r15]
307 [mov r15,r14]
8db62801
EZ		 308
309 Actually it can be more complicated than this. For instance, with
310 newer gcc's:
311
312 mov.l r14,@-r15
313 add #-12,r15
314 mov r15,r14
315 mov r4,r1
316 mov r5,r2
317 mov.l r6,@(4,r14)
318 mov.l r7,@(8,r14)
319 mov.b r1,@r14
320 mov r14,r1
321 mov r14,r1
322 add #2,r1
323 mov.w r2,@r1
324
c5aa993b 325 */
c906108c 326
8db62801
EZ		 327/* STS.L PR,@-r15 0100111100100010
328 r15-4-->r15, PR-->(r15) */
c906108c 329#define IS_STS(x) ((x) == 0x4f22)
8db62801
EZ		 330
331/* MOV.L Rm,@-r15 00101111mmmm0110
332 r15-4-->r15, Rm-->(R15) */
c906108c 333#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 334
c906108c 335#define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
8db62801
EZ		 336
337/* MOV r15,r14 0110111011110011
338 r15-->r14 */
c906108c 339#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ		 340
341/* ADD #imm,r15 01111111iiiiiiii
342 r15+imm-->r15 */
c906108c 343#define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 344
c906108c
SS		 345#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
346#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ		 347
348/* ADD r3,r15 0011111100111100
349 r15+r3-->r15 */
c906108c 350#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ		 351
352/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
8db62801 353 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
8db62801 354 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
c906108c 355#define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
c906108c 356
8db62801 357/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
8db62801 358 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
8db62801
EZ		 359 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
360 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
361#define IS_ARG_MOV(x) \
362(((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
cc17453a
EZ		 363 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
364 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
8db62801
EZ		 365
366/* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
367 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
368#define IS_MOV_R14(x) \
cc17453a 369 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
8db62801
EZ		 370
371#define FPSCR_SZ (1 << 20)
c906108c 372
c906108c
SS		 373/* Skip any prologue before the guts of a function */
374
8db62801
EZ		 375/* Skip the prologue using the debug information. If this fails we'll
376 fall back on the 'guess' method below. */
377static CORE_ADDR
378after_prologue (pc)
379 CORE_ADDR pc;
380{
381 struct symtab_and_line sal;
382 CORE_ADDR func_addr, func_end;
383
384 /* If we can not find the symbol in the partial symbol table, then
385 there is no hope we can determine the function's start address
386 with this code. */
387 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
388 return 0;
389
390 /* Get the line associated with FUNC_ADDR. */
391 sal = find_pc_line (func_addr, 0);
392
393 /* There are only two cases to consider. First, the end of the source line
394 is within the function bounds. In that case we return the end of the
395 source line. Second is the end of the source line extends beyond the
396 bounds of the current function. We need to use the slow code to
397 examine instructions in that case. */
398 if (sal.end < func_end)
399 return sal.end;
400 else
401 return 0;
402}
403
404/* Here we look at each instruction in the function, and try to guess
405 where the prologue ends. Unfortunately this is not always
406 accurate. */
407static CORE_ADDR
408skip_prologue_hard_way (start_pc)
c906108c
SS		 409 CORE_ADDR start_pc;
410{
2bfa91ee 411 CORE_ADDR here, end;
8db62801 412 int updated_fp = 0;
2bfa91ee
EZ		 413
414 if (!start_pc)
415 return 0;
416
417 for (here = start_pc, end = start_pc + (2 * 28); here < end;)
c906108c 418 {
2bfa91ee
EZ		 419 int w = read_memory_integer (here, 2);
420 here += 2;
421 if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w)
8db62801
EZ		 422 || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w)
423 || IS_ARG_MOV (w) || IS_MOV_R14 (w))
2bfa91ee
EZ		 424 {
425 start_pc = here;
2bfa91ee 426 }
8db62801
EZ		 427 else if (IS_MOV_SP_FP (w))
428 {
429 start_pc = here;
430 updated_fp = 1;
431 }
432 else
433 /* Don't bail out yet, if we are before the copy of sp. */
434 if (updated_fp)
435 break;
c906108c
SS		 436 }
437
438 return start_pc;
439}
440
cc17453a 441static CORE_ADDR
8db62801
EZ		 442sh_skip_prologue (pc)
443 CORE_ADDR pc;
444{
445 CORE_ADDR post_prologue_pc;
446
447 /* See if we can determine the end of the prologue via the symbol table.
448 If so, then return either PC, or the PC after the prologue, whichever
449 is greater. */
450
451 post_prologue_pc = after_prologue (pc);
452
453 /* If after_prologue returned a useful address, then use it. Else
454 fall back on the instruction skipping code. */
455 if (post_prologue_pc != 0)
456 return max (pc, post_prologue_pc);
457 else
458 return (skip_prologue_hard_way (pc));
459}
460
cc17453a
EZ		 461/* Immediately after a function call, return the saved pc.
462 Can't always go through the frames for this because on some machines
463 the new frame is not set up until the new function executes
464 some instructions.
465
466 The return address is the value saved in the PR register + 4 */
467static CORE_ADDR
468sh_saved_pc_after_call (frame)
469 struct frame_info *frame;
470{
471 return (ADDR_BITS_REMOVE(read_register(PR_REGNUM)));
472}
473
474/* Should call_function allocate stack space for a struct return? */
475static int
476sh_use_struct_convention (gcc_p, type)
477 int gcc_p;
478 struct type *type;
479{
480 return (TYPE_LENGTH (type) > 1);
481}
482
483/* Store the address of the place in which to copy the structure the
484 subroutine will return. This is called from call_function.
485
486 We store structs through a pointer passed in R0 */
487static void
488sh_store_struct_return (addr, sp)
489 CORE_ADDR addr;
490 CORE_ADDR sp;
491{
492 write_register (STRUCT_RETURN_REGNUM, (addr));
493}
c906108c 494
cc17453a
EZ		 495/* Disassemble an instruction. */
496static int
c906108c
SS		 497gdb_print_insn_sh (memaddr, info)
498 bfd_vma memaddr;
499 disassemble_info *info;
500{
501 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
502 return print_insn_sh (memaddr, info);
503 else
504 return print_insn_shl (memaddr, info);
505}
506
507/* Given a GDB frame, determine the address of the calling function's frame.
508 This will be used to create a new GDB frame struct, and then
509 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
510
511 For us, the frame address is its stack pointer value, so we look up
512 the function prologue to determine the caller's sp value, and return it. */
cc17453a 513static CORE_ADDR
c906108c
SS		 514sh_frame_chain (frame)
515 struct frame_info *frame;
516{
517 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
518 return frame->frame; /* dummy frame same as caller's frame */
2bfa91ee 519 if (frame->pc && !inside_entry_file (frame->pc))
cc17453a 520 return read_memory_integer (FRAME_FP (frame) + frame->extra_info->f_offset, 4);
c906108c
SS		 521 else
522 return 0;
523}
524
525/* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
526 we might want to do here is to check REGNUM against the clobber mask, and
527 somehow flag it as invalid if it isn't saved on the stack somewhere. This
528 would provide a graceful failure mode when trying to get the value of
529 caller-saves registers for an inner frame. */
530
cc17453a 531static CORE_ADDR
c906108c
SS		 532sh_find_callers_reg (fi, regnum)
533 struct frame_info *fi;
534 int regnum;
535{
c906108c
SS		 536 for (; fi; fi = fi->next)
537 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
538 /* When the caller requests PR from the dummy frame, we return PC because
c5aa993b 539 that's where the previous routine appears to have done a call from. */
c906108c 540 return generic_read_register_dummy (fi->pc, fi->frame, regnum);
c5aa993b 541 else
c906108c 542 {
cc17453a 543 FRAME_INIT_SAVED_REGS (fi);
2bfa91ee
EZ		 544 if (!fi->pc)
545 return 0;
cc17453a
EZ		 546 if (fi->saved_regs[regnum] != 0)
547 return read_memory_integer (fi->saved_regs[regnum],
c5aa993b 548 REGISTER_RAW_SIZE (regnum));
c906108c
SS		 549 }
550 return read_register (regnum);
551}
552
553/* Put here the code to store, into a struct frame_saved_regs, the
554 addresses of the saved registers of frame described by FRAME_INFO.
555 This includes special registers such as pc and fp saved in special
556 ways in the stack frame. sp is even more special: the address we
557 return for it IS the sp for the next frame. */
cc17453a
EZ		 558static void
559sh_nofp_frame_init_saved_regs (fi)
c906108c 560 struct frame_info *fi;
c906108c
SS		 561{
562 int where[NUM_REGS];
563 int rn;
564 int have_fp = 0;
565 int depth;
566 int pc;
567 int opc;
568 int insn;
569 int r3_val = 0;
c5aa993b 570 char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
cc17453a
EZ		 571
572 if (fi->saved_regs == NULL)
573 frame_saved_regs_zalloc (fi);
574 else
575 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
576
577 if (dummy_regs)
578 {
579 /* DANGER! This is ONLY going to work if the char buffer format of
580 the saved registers is byte-for-byte identical to the
581 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
582 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
583 return;
584 }
585
586 fi->extra_info->leaf_function = 1;
587 fi->extra_info->f_offset = 0;
588
589 for (rn = 0; rn < NUM_REGS; rn++)
590 where[rn] = -1;
591
592 depth = 0;
593
594 /* Loop around examining the prologue insns until we find something
595 that does not appear to be part of the prologue. But give up
596 after 20 of them, since we're getting silly then. */
597
598 pc = get_pc_function_start (fi->pc);
599 if (!pc)
600 {
601 fi->pc = 0;
602 return;
603 }
604
605 for (opc = pc + (2 * 28); pc < opc; pc += 2)
606 {
607 insn = read_memory_integer (pc, 2);
608 /* See where the registers will be saved to */
609 if (IS_PUSH (insn))
610 {
611 rn = GET_PUSHED_REG (insn);
612 where[rn] = depth;
613 depth += 4;
614 }
615 else if (IS_STS (insn))
616 {
617 where[PR_REGNUM] = depth;
618 /* If we're storing the pr then this isn't a leaf */
619 fi->extra_info->leaf_function = 0;
620 depth += 4;
621 }
622 else if (IS_MOV_R3 (insn))
623 {
624 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
625 }
626 else if (IS_SHLL_R3 (insn))
627 {
628 r3_val <<= 1;
629 }
630 else if (IS_ADD_R3SP (insn))
631 {
632 depth += -r3_val;
633 }
634 else if (IS_ADD_SP (insn))
635 {
636 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
637 }
638 else if (IS_MOV_SP_FP (insn))
639 break;
640#if 0 /* This used to just stop when it found an instruction that
641 was not considered part of the prologue. Now, we just
642 keep going looking for likely instructions. */
643 else
644 break;
645#endif
646 }
647
648 /* Now we know how deep things are, we can work out their addresses */
649
650 for (rn = 0; rn < NUM_REGS; rn++)
651 {
652 if (where[rn] >= 0)
653 {
654 if (rn == FP_REGNUM)
655 have_fp = 1;
c906108c 656
cc17453a
EZ		 657 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
658 }
659 else
660 {
661 fi->saved_regs[rn] = 0;
662 }
663 }
664
665 if (have_fp)
666 {
667 fi->saved_regs[SP_REGNUM] = read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
668 }
669 else
670 {
671 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
672 }
673
674 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
675 /* Work out the return pc - either from the saved pr or the pr
676 value */
677}
678
679static void
680sh_fp_frame_init_saved_regs (fi)
681 struct frame_info *fi;
682{
683 int where[NUM_REGS];
684 int rn;
685 int have_fp = 0;
686 int depth;
687 int pc;
688 int opc;
689 int insn;
690 int r3_val = 0;
691 char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
692
693 if (fi->saved_regs == NULL)
694 frame_saved_regs_zalloc (fi);
695 else
696 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
697
c906108c
SS		 698 if (dummy_regs)
699 {
700 /* DANGER! This is ONLY going to work if the char buffer format of
c5aa993b
JM		 701 the saved registers is byte-for-byte identical to the
702 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
cc17453a 703 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
c906108c
SS		 704 return;
705 }
706
cc17453a
EZ		 707 fi->extra_info->leaf_function = 1;
708 fi->extra_info->f_offset = 0;
c906108c
SS		 709
710 for (rn = 0; rn < NUM_REGS; rn++)
711 where[rn] = -1;
712
713 depth = 0;
714
715 /* Loop around examining the prologue insns until we find something
716 that does not appear to be part of the prologue. But give up
717 after 20 of them, since we're getting silly then. */
718
2bfa91ee
EZ		 719 pc = get_pc_function_start (fi->pc);
720 if (!pc)
c906108c 721 {
2bfa91ee
EZ		 722 fi->pc = 0;
723 return;
724 }
725
726 for (opc = pc + (2 * 28); pc < opc; pc += 2)
727 {
728 insn = read_memory_integer (pc, 2);
c906108c
SS		 729 /* See where the registers will be saved to */
730 if (IS_PUSH (insn))
731 {
c906108c
SS		 732 rn = GET_PUSHED_REG (insn);
733 where[rn] = depth;
c906108c
SS		 734 depth += 4;
735 }
736 else if (IS_STS (insn))
737 {
c906108c 738 where[PR_REGNUM] = depth;
c906108c 739 /* If we're storing the pr then this isn't a leaf */
cc17453a 740 fi->extra_info->leaf_function = 0;
c906108c
SS		 741 depth += 4;
742 }
743 else if (IS_MOV_R3 (insn))
744 {
745 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 746 }
747 else if (IS_SHLL_R3 (insn))
748 {
749 r3_val <<= 1;
c906108c
SS		 750 }
751 else if (IS_ADD_R3SP (insn))
752 {
753 depth += -r3_val;
c906108c
SS		 754 }
755 else if (IS_ADD_SP (insn))
756 {
c906108c 757 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 758 }
759 else if (IS_FMOV (insn))
760 {
cc17453a 761 if (read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM) & FPSCR_SZ)
c906108c
SS		 762 {
763 depth += 8;
764 }
765 else
766 {
767 depth += 4;
768 }
769 }
2bfa91ee
EZ		 770 else if (IS_MOV_SP_FP (insn))
771 break;
772#if 0 /* This used to just stop when it found an instruction that
773 was not considered part of the prologue. Now, we just
774 keep going looking for likely instructions. */
c906108c
SS		 775 else
776 break;
2bfa91ee 777#endif
c906108c
SS		 778 }
779
780 /* Now we know how deep things are, we can work out their addresses */
781
782 for (rn = 0; rn < NUM_REGS; rn++)
783 {
784 if (where[rn] >= 0)
785 {
786 if (rn == FP_REGNUM)
787 have_fp = 1;
788
cc17453a 789 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
c906108c
SS		 790 }
791 else
792 {
cc17453a 793 fi->saved_regs[rn] = 0;
c906108c
SS		 794 }
795 }
796
797 if (have_fp)
798 {
cc17453a 799 fi->saved_regs[SP_REGNUM] = read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
c906108c
SS		 800 }
801 else
802 {
cc17453a 803 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
c906108c
SS		 804 }
805
cc17453a 806 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
c906108c
SS		 807 /* Work out the return pc - either from the saved pr or the pr
808 value */
809}
810
cc17453a
EZ		 811/* Initialize the extra info saved in a FRAME */
812static void
c906108c
SS		 813sh_init_extra_frame_info (fromleaf, fi)
814 int fromleaf;
815 struct frame_info *fi;
816{
cc17453a
EZ		 817
818 fi->extra_info = (struct frame_extra_info *)
819 frame_obstack_alloc (sizeof (struct frame_extra_info));
c906108c
SS		 820
821 if (fi->next)
822 fi->pc = FRAME_SAVED_PC (fi->next);
823
824 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
825 {
826 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
c5aa993b
JM		 827 by assuming it's always FP. */
828 fi->frame = generic_read_register_dummy (fi->pc, fi->frame,
829 SP_REGNUM);
cc17453a
EZ		 830 fi->extra_info->return_pc = generic_read_register_dummy (fi->pc, fi->frame,
831 PC_REGNUM);
832 fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4);
833 fi->extra_info->leaf_function = 0;
c906108c
SS		 834 return;
835 }
836 else
837 {
cc17453a
EZ		 838 FRAME_INIT_SAVED_REGS (fi);
839 fi->extra_info->return_pc = sh_find_callers_reg (fi, PR_REGNUM);
c906108c
SS		 840 }
841}
842
cc17453a
EZ		 843/* Extract from an array REGBUF containing the (raw) register state
844 the address in which a function should return its structure value,
845 as a CORE_ADDR (or an expression that can be used as one). */
846CORE_ADDR
847static sh_extract_struct_value_address (regbuf)
848 char *regbuf;
849{
850 return (extract_address ((regbuf), REGISTER_RAW_SIZE (0)));
851}
852
853static CORE_ADDR
854sh_frame_saved_pc (frame)
855 struct frame_info *frame;
856{
857 return ((frame)->extra_info->return_pc);
858}
859
860static CORE_ADDR
861sh_frame_args_address (fi)
862 struct frame_info *fi;
863{
864 return (fi)->frame;
865}
866
867static CORE_ADDR
868sh_frame_locals_address (fi)
869 struct frame_info *fi;
870{
871 return (fi)->frame;
872}
873
c906108c
SS		 874/* Discard from the stack the innermost frame,
875 restoring all saved registers. */
cc17453a 876static void
c906108c
SS		 877sh_pop_frame ()
878{
879 register struct frame_info *frame = get_current_frame ();
880 register CORE_ADDR fp;
881 register int regnum;
c906108c
SS		 882
883 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
884 generic_pop_dummy_frame ();
885 else
c5aa993b
JM		 886 {
887 fp = FRAME_FP (frame);
cc17453a 888 FRAME_INIT_SAVED_REGS (frame);
c906108c 889
c5aa993b
JM		 890 /* Copy regs from where they were saved in the frame */
891 for (regnum = 0; regnum < NUM_REGS; regnum++)
cc17453a
EZ		 892 if (frame->saved_regs[regnum])
893 write_register (regnum, read_memory_integer (frame->saved_regs[regnum], 4));
c906108c 894
cc17453a 895 write_register (PC_REGNUM, frame->extra_info->return_pc);
c5aa993b
JM		 896 write_register (SP_REGNUM, fp + 4);
897 }
c906108c
SS		 898 flush_cached_frames ();
899}
900
901/* Function: push_arguments
902 Setup the function arguments for calling a function in the inferior.
903
904 On the Hitachi SH architecture, there are four registers (R4 to R7)
905 which are dedicated for passing function arguments. Up to the first
906 four arguments (depending on size) may go into these registers.
907 The rest go on the stack.
908
909 Arguments that are smaller than 4 bytes will still take up a whole
910 register or a whole 32-bit word on the stack, and will be
911 right-justified in the register or the stack word. This includes
912 chars, shorts, and small aggregate types.
913
914 Arguments that are larger than 4 bytes may be split between two or
915 more registers. If there are not enough registers free, an argument
916 may be passed partly in a register (or registers), and partly on the
917 stack. This includes doubles, long longs, and larger aggregates.
918 As far as I know, there is no upper limit to the size of aggregates
919 that will be passed in this way; in other words, the convention of
920 passing a pointer to a large aggregate instead of a copy is not used.
921
922 An exceptional case exists for struct arguments (and possibly other
923 aggregates such as arrays) if the size is larger than 4 bytes but
924 not a multiple of 4 bytes. In this case the argument is never split
925 between the registers and the stack, but instead is copied in its
926 entirety onto the stack, AND also copied into as many registers as
927 there is room for. In other words, space in registers permitting,
928 two copies of the same argument are passed in. As far as I can tell,
929 only the one on the stack is used, although that may be a function
930 of the level of compiler optimization. I suspect this is a compiler
931 bug. Arguments of these odd sizes are left-justified within the
932 word (as opposed to arguments smaller than 4 bytes, which are
933 right-justified).
c5aa993b 934
c906108c
SS		 935 If the function is to return an aggregate type such as a struct, it
936 is either returned in the normal return value register R0 (if its
937 size is no greater than one byte), or else the caller must allocate
938 space into which the callee will copy the return value (if the size
939 is greater than one byte). In this case, a pointer to the return
940 value location is passed into the callee in register R2, which does
941 not displace any of the other arguments passed in via registers R4
942 to R7. */
943
cc17453a 944static CORE_ADDR
c906108c
SS		 945sh_push_arguments (nargs, args, sp, struct_return, struct_addr)
946 int nargs;
947 value_ptr *args;
948 CORE_ADDR sp;
949 unsigned char struct_return;
950 CORE_ADDR struct_addr;
951{
952 int stack_offset, stack_alloc;
953 int argreg;
954 int argnum;
955 struct type *type;
956 CORE_ADDR regval;
957 char *val;
958 char valbuf[4];
959 int len;
960 int odd_sized_struct;
961
962 /* first force sp to a 4-byte alignment */
963 sp = sp & ~3;
964
965 /* The "struct return pointer" pseudo-argument has its own dedicated
966 register */
967 if (struct_return)
c5aa993b 968 write_register (STRUCT_RETURN_REGNUM, struct_addr);
c906108c
SS		 969
970 /* Now make sure there's space on the stack */
cc17453a 971 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
c5aa993b
JM		 972 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
973 sp -= stack_alloc; /* make room on stack for args */
c906108c 974
c906108c
SS		 975 /* Now load as many as possible of the first arguments into
976 registers, and push the rest onto the stack. There are 16 bytes
977 in four registers available. Loop thru args from first to last. */
978
979 argreg = ARG0_REGNUM;
980 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
981 {
982 type = VALUE_TYPE (args[argnum]);
c5aa993b
JM		 983 len = TYPE_LENGTH (type);
984 memset (valbuf, 0, sizeof (valbuf));
c906108c 985 if (len < 4)
cc17453a
EZ		 986 {
987 /* value gets right-justified in the register or stack word */
c5aa993b
JM		 988 memcpy (valbuf + (4 - len),
989 (char *) VALUE_CONTENTS (args[argnum]), len);
990 val = valbuf;
991 }
c906108c 992 else
c5aa993b 993 val = (char *) VALUE_CONTENTS (args[argnum]);
c906108c
SS		 994
995 if (len > 4 && (len & 3) != 0)
c5aa993b
JM		 996 odd_sized_struct = 1; /* such structs go entirely on stack */
997 else
c906108c
SS		 998 odd_sized_struct = 0;
999 while (len > 0)
1000 {
1001 if (argreg > ARGLAST_REGNUM || odd_sized_struct)
c5aa993b 1002 { /* must go on the stack */
c906108c
SS		 1003 write_memory (sp + stack_offset, val, 4);
1004 stack_offset += 4;
1005 }
1006 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1007 That's because some *&^%$ things get passed on the stack
1008 AND in the registers! */
1009 if (argreg <= ARGLAST_REGNUM)
c5aa993b
JM		 1010 { /* there's room in a register */
1011 regval = extract_address (val, REGISTER_RAW_SIZE (argreg));
c906108c
SS		 1012 write_register (argreg++, regval);
1013 }
1014 /* Store the value 4 bytes at a time. This means that things
1015 larger than 4 bytes may go partly in registers and partly
1016 on the stack. */
c5aa993b
JM		 1017 len -= REGISTER_RAW_SIZE (argreg);
1018 val += REGISTER_RAW_SIZE (argreg);
c906108c
SS		 1019 }
1020 }
1021 return sp;
1022}
1023
1024/* Function: push_return_address (pc)
1025 Set up the return address for the inferior function call.
1026 Needed for targets where we don't actually execute a JSR/BSR instruction */
1027
cc17453a 1028static CORE_ADDR
c906108c
SS		 1029sh_push_return_address (pc, sp)
1030 CORE_ADDR pc;
1031 CORE_ADDR sp;
1032{
1033 write_register (PR_REGNUM, CALL_DUMMY_ADDRESS ());
1034 return sp;
1035}
1036
1037/* Function: fix_call_dummy
1038 Poke the callee function's address into the destination part of
1039 the CALL_DUMMY. The address is actually stored in a data word
1040 following the actualy CALL_DUMMY instructions, which will load
1041 it into a register using PC-relative addressing. This function
1042 expects the CALL_DUMMY to look like this:
1043
c5aa993b
JM		 1044 mov.w @(2,PC), R8
1045 jsr @R8
1046 nop
1047 trap
1048 <destination>
1049 */
c906108c
SS		 1050
1051#if 0
1052void
1053sh_fix_call_dummy (dummy, pc, fun, nargs, args, type, gcc_p)
1054 char *dummy;
1055 CORE_ADDR pc;
1056 CORE_ADDR fun;
1057 int nargs;
1058 value_ptr *args;
1059 struct type *type;
1060 int gcc_p;
1061{
1062 *(unsigned long *) (dummy + 8) = fun;
1063}
1064#endif
1065
cc17453a
EZ		 1066static int
1067sh_coerce_float_to_double (struct type *formal, struct type *actual)
1068{
1069 return 1;
1070}
c906108c 1071
cc17453a
EZ		 1072/* Find a function's return value in the appropriate registers (in
1073 regbuf), and copy it into valbuf. Extract from an array REGBUF
1074 containing the (raw) register state a function return value of type
1075 TYPE, and copy that, in virtual format, into VALBUF. */
1076static void
1077sh_extract_return_value (type, regbuf, valbuf)
1078 struct type *type;
1079 char *regbuf;
1080 char *valbuf;
c906108c 1081{
cc17453a 1082 int len = TYPE_LENGTH (type);
c906108c 1083
cc17453a
EZ		 1084 if (len <= 4)
1085 memcpy (valbuf, ((char *) regbuf) + 4 - len, len);
1086 else if (len <= 8)
1087 memcpy (valbuf, ((char *) regbuf) + 8 - len, len);
1088 else
1089 error ("bad size for return value");
1090}
c906108c 1091
cc17453a
EZ		 1092/* Write into appropriate registers a function return value
1093 of type TYPE, given in virtual format.
1094 If the architecture is sh4 or sh3e, store a function's return value
1095 in the R0 general register or in the FP0 floating point register,
1096 depending on the type of the return value. In all the other cases
1097 the result is stored in r0. */
1098static void
1099sh_default_store_return_value (struct type *type, char *valbuf)
1100{
1101 write_register_bytes (REGISTER_BYTE (0),
1102 valbuf, TYPE_LENGTH (type));
1103}
c906108c 1104
cc17453a
EZ		 1105static void
1106sh3e_sh4_store_return_value (struct type *type, char *valbuf)
1107{
1108 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1109 write_register_bytes (REGISTER_BYTE (FP0_REGNUM),
1110 valbuf, TYPE_LENGTH (type));
1111 else
1112 write_register_bytes (REGISTER_BYTE (0),
1113 valbuf, TYPE_LENGTH (type));
c906108c
SS		 1114}
1115
cc17453a 1116
c906108c
SS		 1117/* Print the registers in a form similar to the E7000 */
1118
1119static void
53116e27 1120sh_generic_show_regs ()
c906108c 1121{
cc17453a
EZ		 1122 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1123 paddr (read_register (PC_REGNUM)),
1124 (long) read_register (SR_REGNUM),
1125 (long) read_register (PR_REGNUM),
1126 (long) read_register (MACH_REGNUM),
1127 (long) read_register (MACL_REGNUM));
1128
1129 printf_filtered ("GBR=%08lx VBR=%08lx",
1130 (long) read_register (GBR_REGNUM),
1131 (long) read_register (VBR_REGNUM));
1132
1133 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1134 (long) read_register (0),
1135 (long) read_register (1),
1136 (long) read_register (2),
1137 (long) read_register (3),
1138 (long) read_register (4),
1139 (long) read_register (5),
1140 (long) read_register (6),
1141 (long) read_register (7));
1142 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1143 (long) read_register (8),
1144 (long) read_register (9),
1145 (long) read_register (10),
1146 (long) read_register (11),
1147 (long) read_register (12),
1148 (long) read_register (13),
1149 (long) read_register (14),
1150 (long) read_register (15));
1151}
c906108c 1152
cc17453a 1153static void
53116e27 1154sh3_show_regs ()
cc17453a 1155{
d4f3574e
SS		 1156 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1157 paddr (read_register (PC_REGNUM)),
1158 (long) read_register (SR_REGNUM),
1159 (long) read_register (PR_REGNUM),
1160 (long) read_register (MACH_REGNUM),
1161 (long) read_register (MACL_REGNUM));
1162
1163 printf_filtered ("GBR=%08lx VBR=%08lx",
1164 (long) read_register (GBR_REGNUM),
1165 (long) read_register (VBR_REGNUM));
cc17453a
EZ		 1166 printf_filtered (" SSR=%08lx SPC=%08lx",
1167 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1168 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
c906108c 1169
d4f3574e
SS		 1170 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1171 (long) read_register (0),
1172 (long) read_register (1),
1173 (long) read_register (2),
1174 (long) read_register (3),
1175 (long) read_register (4),
1176 (long) read_register (5),
1177 (long) read_register (6),
1178 (long) read_register (7));
1179 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1180 (long) read_register (8),
1181 (long) read_register (9),
1182 (long) read_register (10),
1183 (long) read_register (11),
1184 (long) read_register (12),
1185 (long) read_register (13),
1186 (long) read_register (14),
1187 (long) read_register (15));
c906108c
SS		 1188}
1189
53116e27 1190
cc17453a 1191static void
53116e27 1192sh3e_show_regs ()
cc17453a
EZ		 1193{
1194 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1195 paddr (read_register (PC_REGNUM)),
1196 (long) read_register (SR_REGNUM),
1197 (long) read_register (PR_REGNUM),
1198 (long) read_register (MACH_REGNUM),
1199 (long) read_register (MACL_REGNUM));
1200
1201 printf_filtered ("GBR=%08lx VBR=%08lx",
1202 (long) read_register (GBR_REGNUM),
1203 (long) read_register (VBR_REGNUM));
1204 printf_filtered (" SSR=%08lx SPC=%08lx",
1205 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1206 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
1207 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1208 (long) read_register (gdbarch_tdep (current_gdbarch)->FPUL_REGNUM),
1209 (long) read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM));
c906108c 1210
cc17453a
EZ		 1211 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1212 (long) read_register (0),
1213 (long) read_register (1),
1214 (long) read_register (2),
1215 (long) read_register (3),
1216 (long) read_register (4),
1217 (long) read_register (5),
1218 (long) read_register (6),
1219 (long) read_register (7));
1220 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1221 (long) read_register (8),
1222 (long) read_register (9),
1223 (long) read_register (10),
1224 (long) read_register (11),
1225 (long) read_register (12),
1226 (long) read_register (13),
1227 (long) read_register (14),
1228 (long) read_register (15));
1229
1230 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1231 (long) read_register (FP0_REGNUM + 0),
1232 (long) read_register (FP0_REGNUM + 1),
1233 (long) read_register (FP0_REGNUM + 2),
1234 (long) read_register (FP0_REGNUM + 3),
1235 (long) read_register (FP0_REGNUM + 4),
1236 (long) read_register (FP0_REGNUM + 5),
1237 (long) read_register (FP0_REGNUM + 6),
1238 (long) read_register (FP0_REGNUM + 7));
1239 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1240 (long) read_register (FP0_REGNUM + 8),
1241 (long) read_register (FP0_REGNUM + 9),
1242 (long) read_register (FP0_REGNUM + 10),
1243 (long) read_register (FP0_REGNUM + 11),
1244 (long) read_register (FP0_REGNUM + 12),
1245 (long) read_register (FP0_REGNUM + 13),
1246 (long) read_register (FP0_REGNUM + 14),
1247 (long) read_register (FP0_REGNUM + 15));
1248}
1249
1250static void
53116e27 1251sh3_dsp_show_regs ()
c906108c 1252{
cc17453a
EZ		 1253 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1254 paddr (read_register (PC_REGNUM)),
1255 (long) read_register (SR_REGNUM),
1256 (long) read_register (PR_REGNUM),
1257 (long) read_register (MACH_REGNUM),
1258 (long) read_register (MACL_REGNUM));
c906108c 1259
cc17453a
EZ		 1260 printf_filtered ("GBR=%08lx VBR=%08lx",
1261 (long) read_register (GBR_REGNUM),
1262 (long) read_register (VBR_REGNUM));
1263
1264 printf_filtered (" SSR=%08lx SPC=%08lx",
1265 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1266 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
1267
1268 printf_filtered (" DSR=%08lx",
1269 (long) read_register (gdbarch_tdep (current_gdbarch)->DSR_REGNUM));
1270
1271 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1272 (long) read_register (0),
1273 (long) read_register (1),
1274 (long) read_register (2),
1275 (long) read_register (3),
1276 (long) read_register (4),
1277 (long) read_register (5),
1278 (long) read_register (6),
1279 (long) read_register (7));
1280 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1281 (long) read_register (8),
1282 (long) read_register (9),
1283 (long) read_register (10),
1284 (long) read_register (11),
1285 (long) read_register (12),
1286 (long) read_register (13),
1287 (long) read_register (14),
1288 (long) read_register (15));
1289
1290 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1291 (long) read_register (gdbarch_tdep (current_gdbarch)->A0G_REGNUM) & 0xff,
1292 (long) read_register (gdbarch_tdep (current_gdbarch)->A0_REGNUM),
1293 (long) read_register (gdbarch_tdep (current_gdbarch)->M0_REGNUM),
1294 (long) read_register (gdbarch_tdep (current_gdbarch)->X0_REGNUM),
1295 (long) read_register (gdbarch_tdep (current_gdbarch)->Y0_REGNUM),
1296 (long) read_register (gdbarch_tdep (current_gdbarch)->RS_REGNUM),
1297 (long) read_register (gdbarch_tdep (current_gdbarch)->MOD_REGNUM));
1298 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1299 (long) read_register (gdbarch_tdep (current_gdbarch)->A1G_REGNUM) & 0xff,
1300 (long) read_register (gdbarch_tdep (current_gdbarch)->A1_REGNUM),
1301 (long) read_register (gdbarch_tdep (current_gdbarch)->M1_REGNUM),
1302 (long) read_register (gdbarch_tdep (current_gdbarch)->X1_REGNUM),
1303 (long) read_register (gdbarch_tdep (current_gdbarch)->Y1_REGNUM),
1304 (long) read_register (gdbarch_tdep (current_gdbarch)->RE_REGNUM));
c906108c
SS		 1305}
1306
cc17453a 1307static void
53116e27 1308sh4_show_regs ()
cc17453a
EZ		 1309{
1310 int pr = read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM) & 0x80000;
1311 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1312 paddr (read_register (PC_REGNUM)),
1313 (long) read_register (SR_REGNUM),
1314 (long) read_register (PR_REGNUM),
1315 (long) read_register (MACH_REGNUM),
1316 (long) read_register (MACL_REGNUM));
1317
1318 printf_filtered ("GBR=%08lx VBR=%08lx",
1319 (long) read_register (GBR_REGNUM),
1320 (long) read_register (VBR_REGNUM));
1321 printf_filtered (" SSR=%08lx SPC=%08lx",
1322 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1323 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
1324 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1325 (long) read_register (gdbarch_tdep (current_gdbarch)->FPUL_REGNUM),
1326 (long) read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM));
1327
1328 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1329 (long) read_register (0),
1330 (long) read_register (1),
1331 (long) read_register (2),
1332 (long) read_register (3),
1333 (long) read_register (4),
1334 (long) read_register (5),
1335 (long) read_register (6),
1336 (long) read_register (7));
1337 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1338 (long) read_register (8),
1339 (long) read_register (9),
1340 (long) read_register (10),
1341 (long) read_register (11),
1342 (long) read_register (12),
1343 (long) read_register (13),
1344 (long) read_register (14),
1345 (long) read_register (15));
1346
1347 printf_filtered ((pr
1348 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1349 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1350 (long) read_register (FP0_REGNUM + 0),
1351 (long) read_register (FP0_REGNUM + 1),
1352 (long) read_register (FP0_REGNUM + 2),
1353 (long) read_register (FP0_REGNUM + 3),
1354 (long) read_register (FP0_REGNUM + 4),
1355 (long) read_register (FP0_REGNUM + 5),
1356 (long) read_register (FP0_REGNUM + 6),
1357 (long) read_register (FP0_REGNUM + 7));
1358 printf_filtered ((pr
1359 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1360 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1361 (long) read_register (FP0_REGNUM + 8),
1362 (long) read_register (FP0_REGNUM + 9),
1363 (long) read_register (FP0_REGNUM + 10),
1364 (long) read_register (FP0_REGNUM + 11),
1365 (long) read_register (FP0_REGNUM + 12),
1366 (long) read_register (FP0_REGNUM + 13),
1367 (long) read_register (FP0_REGNUM + 14),
1368 (long) read_register (FP0_REGNUM + 15));
1369}
1370
1371static void
53116e27 1372sh_dsp_show_regs ()
cc17453a
EZ		 1373{
1374 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1375 paddr (read_register (PC_REGNUM)),
1376 (long) read_register (SR_REGNUM),
1377 (long) read_register (PR_REGNUM),
1378 (long) read_register (MACH_REGNUM),
1379 (long) read_register (MACL_REGNUM));
1380
1381 printf_filtered ("GBR=%08lx VBR=%08lx",
1382 (long) read_register (GBR_REGNUM),
1383 (long) read_register (VBR_REGNUM));
1384
1385 printf_filtered (" DSR=%08lx",
1386 (long) read_register (gdbarch_tdep (current_gdbarch)->DSR_REGNUM));
1387
1388 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1389 (long) read_register (0),
1390 (long) read_register (1),
1391 (long) read_register (2),
1392 (long) read_register (3),
1393 (long) read_register (4),
1394 (long) read_register (5),
1395 (long) read_register (6),
1396 (long) read_register (7));
1397 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1398 (long) read_register (8),
1399 (long) read_register (9),
1400 (long) read_register (10),
1401 (long) read_register (11),
1402 (long) read_register (12),
1403 (long) read_register (13),
1404 (long) read_register (14),
1405 (long) read_register (15));
1406
1407 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1408 (long) read_register (gdbarch_tdep (current_gdbarch)->A0G_REGNUM) & 0xff,
1409 (long) read_register (gdbarch_tdep (current_gdbarch)->A0_REGNUM),
1410 (long) read_register (gdbarch_tdep (current_gdbarch)->M0_REGNUM),
1411 (long) read_register (gdbarch_tdep (current_gdbarch)->X0_REGNUM),
1412 (long) read_register (gdbarch_tdep (current_gdbarch)->Y0_REGNUM),
1413 (long) read_register (gdbarch_tdep (current_gdbarch)->RS_REGNUM),
1414 (long) read_register (gdbarch_tdep (current_gdbarch)->MOD_REGNUM));
1415 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1416 (long) read_register (gdbarch_tdep (current_gdbarch)->A1G_REGNUM) & 0xff,
1417 (long) read_register (gdbarch_tdep (current_gdbarch)->A1_REGNUM),
1418 (long) read_register (gdbarch_tdep (current_gdbarch)->M1_REGNUM),
1419 (long) read_register (gdbarch_tdep (current_gdbarch)->X1_REGNUM),
1420 (long) read_register (gdbarch_tdep (current_gdbarch)->Y1_REGNUM),
1421 (long) read_register (gdbarch_tdep (current_gdbarch)->RE_REGNUM));
1422}
1423
53116e27
EZ		 1424void sh_show_regs_command (char *args, int from_tty)
1425{
1426 if (sh_show_regs)
1427 (*sh_show_regs)();
1428}
1429
cc17453a
EZ		 1430/* Index within `registers' of the first byte of the space for
1431 register N. */
1432static int
53116e27 1433sh_default_register_byte (reg_nr)
cc17453a 1434 int reg_nr;
8db62801 1435{
cc17453a
EZ		 1436 return (reg_nr * 4);
1437}
1438
53116e27
EZ		 1439static int
1440sh_sh4_register_byte (reg_nr)
1441 int reg_nr;
1442{
1443 if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
fe9f384f 1444 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR14_REGNUM)
53116e27
EZ		 1445 return (dr_reg_base_num (reg_nr) * 4);
1446 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
fe9f384f 1447 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV12_REGNUM)
53116e27
EZ		 1448 return (fv_reg_base_num (reg_nr) * 4);
1449 else
1450 return (reg_nr * 4);
1451}
1452
cc17453a
EZ		 1453/* Number of bytes of storage in the actual machine representation for
1454 register REG_NR. */
1455static int
53116e27 1456sh_default_register_raw_size (reg_nr)
cc17453a
EZ		 1457 int reg_nr;
1458{
1459 return 4;
1460}
1461
53116e27
EZ		 1462static int
1463sh_sh4_register_raw_size (reg_nr)
1464 int reg_nr;
1465{
1466 if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
fe9f384f 1467 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR14_REGNUM)
53116e27
EZ		 1468 return 8;
1469 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
fe9f384f 1470 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV12_REGNUM)
53116e27
EZ		 1471 return 16;
1472 else
1473 return 4;
1474}
1475
cc17453a
EZ		 1476/* Number of bytes of storage in the program's representation
1477 for register N. */
1478static int
1479sh_register_virtual_size (reg_nr)
1480 int reg_nr;
1481{
1482 return 4;
1483}
1484
1485/* Return the GDB type object for the "standard" data type
1486 of data in register N. */
1487
1488static struct type *
1489sh_sh3e_register_virtual_type (reg_nr)
1490 int reg_nr;
1491{
1492 if ((reg_nr >= FP0_REGNUM
1493 && (reg_nr <= gdbarch_tdep (current_gdbarch)->FP15_REGNUM))
1494 || (reg_nr == gdbarch_tdep (current_gdbarch)->FPUL_REGNUM))
1495 return builtin_type_float;
8db62801 1496 else
cc17453a
EZ		 1497 return builtin_type_int;
1498}
1499
53116e27
EZ		 1500static struct type *
1501sh_sh4_register_virtual_type (reg_nr)
1502 int reg_nr;
1503{
1504 if ((reg_nr >= FP0_REGNUM
1505 && (reg_nr <= gdbarch_tdep (current_gdbarch)->FP15_REGNUM))
1506 || (reg_nr == gdbarch_tdep (current_gdbarch)->FPUL_REGNUM))
1507 return builtin_type_float;
1508 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
fe9f384f 1509 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR14_REGNUM)
53116e27
EZ		 1510 return builtin_type_double;
1511 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
fe9f384f 1512 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV12_REGNUM)
53116e27
EZ		 1513 return sh_sh4_build_float_register_type (3);
1514 else
1515 return builtin_type_int;
1516}
1517
1518static struct type *
1519sh_sh4_build_float_register_type (int high)
1520{
1521 struct type *temp;
1522
1523 temp = create_range_type (NULL, builtin_type_int, 0, high);
1524 return create_array_type (NULL, builtin_type_float, temp);
1525}
1526
cc17453a
EZ		 1527static struct type *
1528sh_default_register_virtual_type (reg_nr)
1529 int reg_nr;
1530{
1531 return builtin_type_int;
1532}
1533
fb409745
EZ		 1534/* On the sh4, the DRi pseudo registers are problematic if the target
1535 is little endian. When the user writes one of those registers, for
1536 instance with 'ser var $dr0=1', we want the double to be stored
1537 like this:
1538 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1539 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1540
1541 This corresponds to little endian byte order & big endian word
1542 order. However if we let gdb write the register w/o conversion, it
1543 will write fr0 and fr1 this way:
1544 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1545 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1546 because it will consider fr0 and fr1 as a single LE stretch of memory.
1547
1548 To achieve what we want we must force gdb to store things in
1549 floatformat_ieee_double_littlebyte_bigword (which is defined in
1550 include/floatformat.h and libiberty/floatformat.c.
1551
1552 In case the target is big endian, there is no problem, the
1553 raw bytes will look like:
1554 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1555 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1556
1557 The other pseudo registers (the FVs) also don't pose a problem
1558 because they are stored as 4 individual FP elements. */
1559
1560int
1561sh_sh4_register_convertible (int nr)
1562{
1563 if (TARGET_BYTE_ORDER == LITTLE_ENDIAN)
1564 return (gdbarch_tdep (current_gdbarch)->DR0_REGNUM <= nr
1565 && nr <= gdbarch_tdep (current_gdbarch)->DR14_REGNUM);
1566 else
1567 return 0;
1568}
1569
1570void
1571sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
1572 char *from, char *to)
1573{
1574 if (regnum >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
1575 && regnum <= gdbarch_tdep (current_gdbarch)->DR14_REGNUM)
1576 {
1577 DOUBLEST val;
1578 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
1579 store_floating(to, TYPE_LENGTH(type), val);
1580 }
1581 else
1582 error("sh_register_convert_to_virtual called with non DR register number");
1583}
1584
1585void
1586sh_sh4_register_convert_to_raw (struct type *type, int regnum,
1587 char *from, char *to)
1588{
1589 if (regnum >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
1590 && regnum <= gdbarch_tdep (current_gdbarch)->DR14_REGNUM)
1591 {
1592 DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
1593 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
1594 }
1595 else
1596 error("sh_register_convert_to_raw called with non DR register number");
1597}
1598
53116e27
EZ		 1599void
1600sh_fetch_pseudo_register (int reg_nr)
1601{
1602 int base_regnum, portion;
1603
1604 if (!register_cached (reg_nr))
1605 {
1606 if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
fe9f384f 1607 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR14_REGNUM)
53116e27
EZ		 1608 {
1609 base_regnum = dr_reg_base_num (reg_nr);
1610
1611 /* Read the real regs for which this one is an alias. */
1612 for (portion = 0; portion < 2; portion++)
1613 if (!register_cached (base_regnum + portion))
1614 target_fetch_registers (base_regnum + portion);
1615 }
1616 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
fe9f384f 1617 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV12_REGNUM)
53116e27
EZ		 1618 {
1619 base_regnum = fv_reg_base_num (reg_nr);
1620
1621 /* Read the real regs for which this one is an alias. */
1622 for (portion = 0; portion < 4; portion++)
1623 if (!register_cached (base_regnum + portion))
1624 target_fetch_registers (base_regnum + portion);
1625
1626 }
1627 register_valid [reg_nr] = 1;
1628 }
1629}
1630
1631void
1632sh_store_pseudo_register (int reg_nr)
1633{
1634 int base_regnum, portion;
1635
1636 if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
fe9f384f 1637 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR14_REGNUM)
53116e27
EZ		 1638 {
1639 base_regnum = dr_reg_base_num (reg_nr);
1640
1641 /* Write the real regs for which this one is an alias. */
1642 for (portion = 0; portion < 2; portion++)
1643 {
1644 register_valid[base_regnum + portion] = 1;
1645 target_store_registers (base_regnum + portion);
1646 }
1647 }
1648 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
fe9f384f 1649 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV12_REGNUM)
53116e27
EZ		 1650 {
1651 base_regnum = fv_reg_base_num (reg_nr);
1652
1653 /* Write the real regs for which this one is an alias. */
1654 for (portion = 0; portion < 4; portion++)
1655 {
1656 register_valid[base_regnum + portion] = 1;
1657 target_store_registers (base_regnum + portion);
1658 }
1659 }
1660}
1661
1662static int
1663fv_reg_base_num (int fv_regnum)
1664{
1665 int fp_regnum;
1666
1667 fp_regnum = FP0_REGNUM +
1668 (fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM) * 4;
1669 return fp_regnum;
1670}
1671
1672static int
1673dr_reg_base_num (int dr_regnum)
1674{
1675 int fp_regnum;
1676
1677 fp_regnum = FP0_REGNUM +
1678 (dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM) * 2;
1679 return fp_regnum;
1680}
1681
1682static void
1683do_fv_register_info (int fv_regnum)
1684{
1685 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
1686 printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1687 fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM,
1688 (int) read_register (first_fp_reg_num),
1689 (int) read_register (first_fp_reg_num + 1),
1690 (int) read_register (first_fp_reg_num + 2),
1691 (int) read_register (first_fp_reg_num + 3));
1692}
1693
1694static void
1695do_dr_register_info (int dr_regnum)
1696{
1697 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1698
1699 printf_filtered ("dr%d\t0x%08x%08x\n",
1700 dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM,
1701 (int) read_register (first_fp_reg_num),
1702 (int) read_register (first_fp_reg_num + 1));
1703}
1704
1705static void
1706sh_do_pseudo_register (int regnum)
1707{
1708 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1709 internal_error ("Invalid pasudo register number %d\n", regnum);
1710 else if (regnum >= NUM_REGS &&
1711 regnum < gdbarch_tdep (current_gdbarch)->FV0_REGNUM)
1712 do_dr_register_info (regnum);
1713 else if (regnum >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM &&
fe9f384f 1714 regnum <= gdbarch_tdep (current_gdbarch)->FV12_REGNUM)
53116e27
EZ		 1715 do_fv_register_info (regnum);
1716}
1717
1718
1719static void
1720sh_do_fp_register (int regnum)
1721{ /* do values for FP (float) regs */
1722 char *raw_buffer;
1723 double flt; /* double extracted from raw hex data */
1724 int inv;
1725 int j;
1726
1727 /* Allocate space for the float. */
1728 raw_buffer = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM));
1729
1730 /* Get the data in raw format. */
1731 if (read_relative_register_raw_bytes (regnum, raw_buffer))
1732 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1733
1734 /* Get the register as a number */
1735 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1736
1737 /* Print the name and some spaces. */
1738 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
1739 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
1740
1741 /* Print the value. */
1742 printf_filtered (inv ? "<invalid float>" : "%-10.9g", flt);
1743
1744 /* Print the fp register as hex. */
1745 printf_filtered ("\t(raw 0x");
1746 for (j = 0; j < REGISTER_RAW_SIZE (regnum); j++)
1747 {
1748 register int idx = TARGET_BYTE_ORDER == BIG_ENDIAN ? j
1749 : REGISTER_RAW_SIZE (regnum) - 1 - j;
1750 printf_filtered ("%02x", (unsigned char) raw_buffer[idx]);
1751 }
1752 printf_filtered (")");
1753 printf_filtered ("\n");
1754}
1755
1756static void
1757sh_do_register (int regnum)
1758{
1759 char raw_buffer[MAX_REGISTER_RAW_SIZE];
1760
1761 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
1762 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
1763
1764 /* Get the data in raw format. */
1765 if (read_relative_register_raw_bytes (regnum, raw_buffer))
1766 printf_filtered ("*value not available*\n");
1767
1768 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
1769 gdb_stdout, 'x', 1, 0, Val_pretty_default);
1770 printf_filtered ("\t");
1771 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
1772 gdb_stdout, 0, 1, 0, Val_pretty_default);
1773 printf_filtered ("\n");
1774}
1775
1776static void
1777sh_print_register (int regnum)
1778{
1779 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1780 internal_error ("Invalid register number %d\n", regnum);
1781
1782 else if (regnum > 0 && regnum < NUM_REGS)
1783 {
1784 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
1785 sh_do_fp_register (regnum); /* FP regs */
1786 else
1787 sh_do_register (regnum); /* All other regs */
1788 }
1789
1790 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1791 sh_do_pseudo_register (regnum);
1792}
1793
1794void
1795sh_do_registers_info (int regnum, int fpregs)
1796{
1797 if (regnum != -1) /* do one specified register */
1798 {
1799 if (*(REGISTER_NAME (regnum)) == '\0')
1800 error ("Not a valid register for the current processor type");
1801
1802 sh_print_register (regnum);
1803 }
1804 else
1805 /* do all (or most) registers */
1806 {
1807 regnum = 0;
1808 while (regnum < NUM_REGS)
1809 {
1810 /* If the register name is empty, it is undefined for this
1811 processor, so don't display anything. */
1812 if (REGISTER_NAME (regnum) == NULL
1813 || *(REGISTER_NAME (regnum)) == '\0')
1814 {
1815 regnum++;
1816 continue;
1817 }
1818
1819 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
1820 {
1821 if (fpregs)
1822 {
1823 /* true for "INFO ALL-REGISTERS" command */
1824 sh_do_fp_register (regnum); /* FP regs */
1825 regnum ++;
1826 }
1827 else
1828 regnum += (gdbarch_tdep (current_gdbarch)->FP15_REGNUM - FP0_REGNUM); /* skip FP regs */
1829 }
1830 else
1831 {
1832 sh_do_register (regnum); /* All other regs */
1833 regnum++;
1834 }
1835 }
1836
1837 if (fpregs)
1838 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1839 {
1840 sh_do_pseudo_register (regnum);
1841 regnum++;
1842 }
1843 }
1844}
1845
cc17453a
EZ		 1846static gdbarch_init_ftype sh_gdbarch_init;
1847
1848static struct gdbarch *
1849sh_gdbarch_init (info, arches)
1850 struct gdbarch_info info;
1851 struct gdbarch_list *arches;
1852{
1853 static LONGEST sh_call_dummy_words[] = {0};
1854 struct gdbarch *gdbarch;
1855 struct gdbarch_tdep *tdep;
1856 gdbarch_register_name_ftype *sh_register_name;
1857 gdbarch_store_return_value_ftype *sh_store_return_value;
1858 gdbarch_register_virtual_type_ftype *sh_register_virtual_type;
1859
1860 /* Find a candidate among the list of pre-declared architectures. */
1861 arches = gdbarch_list_lookup_by_info (arches, &info);
1862 if (arches != NULL)
1863 return arches->gdbarch;
1864
1865 /* None found, create a new architecture from the information
1866 provided. */
1867 tdep = XMALLOC (struct gdbarch_tdep);
1868 gdbarch = gdbarch_alloc (&info, tdep);
1869
1870 /* Initialize the register numbers that are not common to all the
1871 variants to -1, if necessary thse will be overwritten in the case
1872 statement below. */
1873 tdep->FPUL_REGNUM = -1;
1874 tdep->FPSCR_REGNUM = -1;
1875 tdep->DSR_REGNUM = -1;
1876 tdep->FP15_REGNUM = -1;
1877 tdep->A0G_REGNUM = -1;
1878 tdep->A0_REGNUM = -1;
1879 tdep->A1G_REGNUM = -1;
1880 tdep->A1_REGNUM = -1;
1881 tdep->M0_REGNUM = -1;
1882 tdep->M1_REGNUM = -1;
1883 tdep->X0_REGNUM = -1;
1884 tdep->X1_REGNUM = -1;
1885 tdep->Y0_REGNUM = -1;
1886 tdep->Y1_REGNUM = -1;
1887 tdep->MOD_REGNUM = -1;
1888 tdep->RS_REGNUM = -1;
1889 tdep->RE_REGNUM = -1;
1890 tdep->SSR_REGNUM = -1;
1891 tdep->SPC_REGNUM = -1;
53116e27 1892 tdep->DR0_REGNUM = -1;
53116e27 1893 tdep->DR2_REGNUM = -1;
53116e27 1894 tdep->DR4_REGNUM = -1;
53116e27 1895 tdep->DR6_REGNUM = -1;
fe9f384f
EZ		 1896 tdep->DR8_REGNUM = -1;
1897 tdep->DR10_REGNUM = -1;
1898 tdep->DR12_REGNUM = -1;
1899 tdep->DR14_REGNUM = -1;
53116e27 1900 tdep->FV0_REGNUM = -1;
fe9f384f
EZ		 1901 tdep->FV4_REGNUM = -1;
1902 tdep->FV8_REGNUM = -1;
1903 tdep->FV12_REGNUM = -1;
cc17453a 1904 set_gdbarch_fp0_regnum (gdbarch, -1);
53116e27
EZ		 1905 set_gdbarch_num_pseudo_regs (gdbarch, 0);
1906 set_gdbarch_max_register_raw_size (gdbarch, 4);
1907 set_gdbarch_max_register_virtual_size (gdbarch, 4);
cc17453a
EZ		 1908
1909 switch (info.bfd_arch_info->mach)
8db62801 1910 {
cc17453a
EZ		 1911 case bfd_mach_sh:
1912 sh_register_name = sh_sh_register_name;
1913 sh_show_regs = sh_generic_show_regs;
1914 sh_store_return_value = sh_default_store_return_value;
1915 sh_register_virtual_type = sh_default_register_virtual_type;
1916 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1917 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1918 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1919 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1920 break;
1921 case bfd_mach_sh2:
1922 sh_register_name = sh_sh_register_name;
1923 sh_show_regs = sh_generic_show_regs;
1924 sh_store_return_value = sh_default_store_return_value;
1925 sh_register_virtual_type = sh_default_register_virtual_type;
1926 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1927 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1928 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1929 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1930 break;
1931 case bfd_mach_sh_dsp:
1932 sh_register_name = sh_sh_dsp_register_name;
1933 sh_show_regs = sh_dsp_show_regs;
1934 sh_store_return_value = sh_default_store_return_value;
1935 sh_register_virtual_type = sh_default_register_virtual_type;
1936 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1937 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1938 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1939 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1940 tdep->DSR_REGNUM = 24;
1941 tdep->A0G_REGNUM = 25;
1942 tdep->A0_REGNUM = 26;
1943 tdep->A1G_REGNUM = 27;
1944 tdep->A1_REGNUM = 28;
1945 tdep->M0_REGNUM = 29;
1946 tdep->M1_REGNUM = 30;
1947 tdep->X0_REGNUM = 31;
1948 tdep->X1_REGNUM = 32;
1949 tdep->Y0_REGNUM = 33;
1950 tdep->Y1_REGNUM = 34;
1951 tdep->MOD_REGNUM = 40;
1952 tdep->RS_REGNUM = 43;
1953 tdep->RE_REGNUM = 44;
1954 break;
1955 case bfd_mach_sh3:
1956 sh_register_name = sh_sh3_register_name;
1957 sh_show_regs = sh3_show_regs;
1958 sh_store_return_value = sh_default_store_return_value;
1959 sh_register_virtual_type = sh_default_register_virtual_type;
1960 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1961 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1962 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1963 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1964 tdep->SSR_REGNUM = 41;
1965 tdep->SPC_REGNUM = 42;
1966 break;
1967 case bfd_mach_sh3e:
1968 sh_register_name = sh_sh3e_register_name;
1969 sh_show_regs = sh3e_show_regs;
1970 sh_store_return_value = sh3e_sh4_store_return_value;
1971 sh_register_virtual_type = sh_sh3e_register_virtual_type;
1972 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
53116e27
EZ		 1973 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1974 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1975 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1976 set_gdbarch_fp0_regnum (gdbarch, 25);
1977 tdep->FPUL_REGNUM = 23;
1978 tdep->FPSCR_REGNUM = 24;
1979 tdep->FP15_REGNUM = 40;
1980 tdep->SSR_REGNUM = 41;
1981 tdep->SPC_REGNUM = 42;
1982 break;
1983 case bfd_mach_sh3_dsp:
1984 sh_register_name = sh_sh3_dsp_register_name;
1985 sh_show_regs = sh3_dsp_show_regs;
1986 sh_store_return_value = sh_default_store_return_value;
1987 sh_register_virtual_type = sh_default_register_virtual_type;
1988 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1989 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1990 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1991 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1992 tdep->DSR_REGNUM = 24;
1993 tdep->A0G_REGNUM = 25;
1994 tdep->A0_REGNUM = 26;
1995 tdep->A1G_REGNUM = 27;
1996 tdep->A1_REGNUM = 28;
1997 tdep->M0_REGNUM = 29;
1998 tdep->M1_REGNUM = 30;
1999 tdep->X0_REGNUM = 31;
2000 tdep->X1_REGNUM = 32;
2001 tdep->Y0_REGNUM = 33;
2002 tdep->Y1_REGNUM = 34;
2003 tdep->MOD_REGNUM = 40;
2004 tdep->RS_REGNUM = 43;
2005 tdep->RE_REGNUM = 44;
2006 tdep->SSR_REGNUM = 41;
2007 tdep->SPC_REGNUM = 42;
2008 break;
2009 case bfd_mach_sh4:
53116e27
EZ		 2010 sh_register_name = sh_sh4_register_name;
2011 sh_show_regs = sh4_show_regs;
cc17453a 2012 sh_store_return_value = sh3e_sh4_store_return_value;
53116e27 2013 sh_register_virtual_type = sh_sh4_register_virtual_type;
cc17453a
EZ		 2014 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
2015 set_gdbarch_fp0_regnum (gdbarch, 25);
53116e27
EZ		 2016 set_gdbarch_register_raw_size (gdbarch, sh_sh4_register_raw_size);
2017 set_gdbarch_register_virtual_size (gdbarch, sh_sh4_register_raw_size);
2018 set_gdbarch_register_byte (gdbarch, sh_sh4_register_byte);
2019 set_gdbarch_num_pseudo_regs (gdbarch, 12);
2020 set_gdbarch_max_register_raw_size (gdbarch, 4 * 4);
2021 set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4);
fb409745
EZ		 2022 set_gdbarch_register_convert_to_raw (gdbarch, sh_sh4_register_convert_to_raw);
2023 set_gdbarch_register_convert_to_virtual (gdbarch, sh_sh4_register_convert_to_virtual);
2024 set_gdbarch_register_convertible (gdbarch, sh_sh4_register_convertible);
cc17453a
EZ		 2025 tdep->FPUL_REGNUM = 23;
2026 tdep->FPSCR_REGNUM = 24;
2027 tdep->FP15_REGNUM = 40;
2028 tdep->SSR_REGNUM = 41;
2029 tdep->SPC_REGNUM = 42;
53116e27 2030 tdep->DR0_REGNUM = 59;
fe9f384f
EZ		 2031 tdep->DR2_REGNUM = 60;
2032 tdep->DR4_REGNUM = 61;
2033 tdep->DR6_REGNUM = 62;
2034 tdep->DR8_REGNUM = 63;
2035 tdep->DR10_REGNUM = 64;
2036 tdep->DR12_REGNUM = 65;
2037 tdep->DR14_REGNUM = 66;
53116e27 2038 tdep->FV0_REGNUM = 67;
fe9f384f
EZ		 2039 tdep->FV4_REGNUM = 68;
2040 tdep->FV8_REGNUM = 69;
2041 tdep->FV12_REGNUM = 70;
cc17453a
EZ		 2042 break;
2043 default:
2044 sh_register_name = sh_generic_register_name;
2045 sh_show_regs = sh_generic_show_regs;
2046 sh_store_return_value = sh_default_store_return_value;
2047 sh_register_virtual_type = sh_default_register_virtual_type;
2048 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 2049 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
2050 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
2051 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a 2052 break;
8db62801 2053 }
cc17453a
EZ		 2054
2055 set_gdbarch_read_pc (gdbarch, generic_target_read_pc);
2056 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2057 set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
2058 set_gdbarch_write_fp (gdbarch, generic_target_write_fp);
2059 set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
2060 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
2061
2062 set_gdbarch_num_regs (gdbarch, 59);
2063 set_gdbarch_sp_regnum (gdbarch, 15);
2064 set_gdbarch_fp_regnum (gdbarch, 14);
2065 set_gdbarch_pc_regnum (gdbarch, 16);
2066 set_gdbarch_register_name (gdbarch, sh_register_name);
2067 set_gdbarch_register_size (gdbarch, 4);
2068 set_gdbarch_register_bytes (gdbarch, NUM_REGS * 4);
cc17453a
EZ		 2069 set_gdbarch_register_virtual_type (gdbarch, sh_register_virtual_type);
2070
2071 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2072 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2073 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2074 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2075 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2076 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2077 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2078 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
2079
2080 set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
2081 set_gdbarch_call_dummy_length (gdbarch, 0);
2082 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
2083 set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
2084 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); /*???*/
2085 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
2086 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
2087 set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
2088 set_gdbarch_call_dummy_words (gdbarch, sh_call_dummy_words);
2089 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (sh_call_dummy_words));
2090 set_gdbarch_call_dummy_p (gdbarch, 1);
2091 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
2092 set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
2093 set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
2094 set_gdbarch_coerce_float_to_double (gdbarch,
2095 sh_coerce_float_to_double);
2096
2097 set_gdbarch_extract_return_value (gdbarch, sh_extract_return_value);
2098 set_gdbarch_push_arguments (gdbarch, sh_push_arguments);
2099 set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
2100 set_gdbarch_push_return_address (gdbarch, sh_push_return_address);
2101
2102 set_gdbarch_store_struct_return (gdbarch, sh_store_struct_return);
2103 set_gdbarch_store_return_value (gdbarch, sh_store_return_value);
2104 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
2105 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
2106 set_gdbarch_init_extra_frame_info (gdbarch, sh_init_extra_frame_info);
2107 set_gdbarch_pop_frame (gdbarch, sh_pop_frame);
2108 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2109 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2110 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2111 set_gdbarch_function_start_offset (gdbarch, 0);
2112 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2113
53116e27
EZ		 2114 set_gdbarch_fetch_pseudo_register (gdbarch, sh_fetch_pseudo_register);
2115 set_gdbarch_store_pseudo_register (gdbarch, sh_store_pseudo_register);
cc17453a
EZ		 2116 set_gdbarch_frame_args_skip (gdbarch, 0);
2117 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
2118 set_gdbarch_frame_chain (gdbarch, sh_frame_chain);
2119 set_gdbarch_frame_chain_valid (gdbarch, generic_file_frame_chain_valid);
2120 set_gdbarch_frame_saved_pc (gdbarch, sh_frame_saved_pc);
2121 set_gdbarch_frame_args_address (gdbarch, sh_frame_args_address);
2122 set_gdbarch_frame_locals_address (gdbarch, sh_frame_locals_address);
2123 set_gdbarch_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
2124 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
2125 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2126 set_gdbarch_ieee_float (gdbarch, 1);
2127
2128 return gdbarch;
8db62801
EZ		 2129}
2130
c906108c
SS		 2131void
2132_initialize_sh_tdep ()
2133{
2134 struct cmd_list_element *c;
cc17453a
EZ		 2135
2136 register_gdbarch_init (bfd_arch_sh, sh_gdbarch_init);
c906108c
SS		 2137 tm_print_insn = gdb_print_insn_sh;
2138
53116e27 2139 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
c906108c 2140}
GDB Binutils - Deliverables
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