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Remove prototypes for obsolete static functions.
[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
CommitLineData
c906108c 1/* Target-dependent code for Hitachi Super-H, for GDB.
b4a20239
AC		 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 2000 Free Software
3 Foundation, Inc.
c906108c 4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM		 7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
c906108c 11
c5aa993b
JM		 12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b
JM		 17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
c906108c
SS		 21
22/*
c5aa993b
JM		 23 Contributed by Steve Chamberlain
24 sac@cygnus.com
c906108c
SS		 25 */
26
27#include "defs.h"
28#include "frame.h"
29#include "obstack.h"
30#include "symtab.h"
31#include "symfile.h"
32#include "gdbtypes.h"
33#include "gdbcmd.h"
34#include "gdbcore.h"
35#include "value.h"
36#include "dis-asm.h"
37#include "inferior.h" /* for BEFORE_TEXT_END etc. */
38#include "gdb_string.h"
b4a20239 39#include "arch-utils.h"
fb409745 40#include "floatformat.h"
c906108c 41
1a8629c7
MS		 42#include "solib-svr4.h"
43
cc17453a
EZ		 44#undef XMALLOC
45#define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE)))
46
53116e27
EZ		 47
48/* Frame interpretation related functions. */
cc17453a
EZ		 49static gdbarch_breakpoint_from_pc_ftype sh_breakpoint_from_pc;
50static gdbarch_frame_chain_ftype sh_frame_chain;
51static gdbarch_frame_saved_pc_ftype sh_frame_saved_pc;
52static gdbarch_skip_prologue_ftype sh_skip_prologue;
53116e27 53
cc17453a
EZ		 54static gdbarch_frame_init_saved_regs_ftype sh_nofp_frame_init_saved_regs;
55static gdbarch_frame_init_saved_regs_ftype sh_fp_frame_init_saved_regs;
53116e27
EZ		 56static gdbarch_init_extra_frame_info_ftype sh_init_extra_frame_info;
57static gdbarch_pop_frame_ftype sh_pop_frame;
58static gdbarch_saved_pc_after_call_ftype sh_saved_pc_after_call;
53116e27
EZ		 59
60/* Function call related functions. */
cc17453a
EZ		 61static gdbarch_extract_return_value_ftype sh_extract_return_value;
62static gdbarch_extract_struct_value_address_ftype sh_extract_struct_value_address;
63static gdbarch_use_struct_convention_ftype sh_use_struct_convention;
cc17453a
EZ		 64static gdbarch_store_struct_return_ftype sh_store_struct_return;
65static gdbarch_push_arguments_ftype sh_push_arguments;
66static gdbarch_push_return_address_ftype sh_push_return_address;
53116e27
EZ		 67static gdbarch_coerce_float_to_double_ftype sh_coerce_float_to_double;
68static gdbarch_store_return_value_ftype sh_default_store_return_value;
69static gdbarch_store_return_value_ftype sh3e_sh4_store_return_value;
cc17453a
EZ		 70
71static gdbarch_register_name_ftype sh_generic_register_name;
72static gdbarch_register_name_ftype sh_sh_register_name;
73static gdbarch_register_name_ftype sh_sh3_register_name;
74static gdbarch_register_name_ftype sh_sh3e_register_name;
75static gdbarch_register_name_ftype sh_sh_dsp_register_name;
76static gdbarch_register_name_ftype sh_sh3_dsp_register_name;
77
53116e27
EZ		 78/* Registers display related functions */
79static gdbarch_register_raw_size_ftype sh_default_register_raw_size;
80static gdbarch_register_raw_size_ftype sh_sh4_register_raw_size;
cc17453a 81
cc17453a 82static gdbarch_register_virtual_size_ftype sh_register_virtual_size;
53116e27
EZ		 83
84static gdbarch_register_byte_ftype sh_default_register_byte;
85static gdbarch_register_byte_ftype sh_sh4_register_byte;
86
cc17453a 87static gdbarch_register_virtual_type_ftype sh_sh3e_register_virtual_type;
53116e27 88static gdbarch_register_virtual_type_ftype sh_sh4_register_virtual_type;
cc17453a
EZ		 89static gdbarch_register_virtual_type_ftype sh_default_register_virtual_type;
90
53116e27
EZ		 91static void sh_generic_show_regs (void);
92static void sh3_show_regs (void);
93static void sh3e_show_regs (void);
94static void sh3_dsp_show_regs (void);
95static void sh_dsp_show_regs (void);
96static void sh4_show_regs (void);
97static void sh_show_regs_command (char *, int);
98
99static struct type *sh_sh4_build_float_register_type (int high);
100
101static gdbarch_fetch_pseudo_register_ftype sh_fetch_pseudo_register;
102static gdbarch_store_pseudo_register_ftype sh_store_pseudo_register;
103static int fv_reg_base_num (int);
104static int dr_reg_base_num (int);
c5f7d19c 105static gdbarch_do_registers_info_ftype sh_do_registers_info;
53116e27
EZ		 106static void do_fv_register_info (int fv_regnum);
107static void do_dr_register_info (int dr_regnum);
108static void sh_do_pseudo_register (int regnum);
109static void sh_do_fp_register (int regnum);
110static void sh_do_register (int regnum);
111static void sh_print_register (int regnum);
112
113void (*sh_show_regs) (void);
e6c42fda 114int (*print_sh_insn) (bfd_vma, disassemble_info*);
cc17453a 115
cc17453a
EZ		 116/* Define other aspects of the stack frame.
117 we keep a copy of the worked out return pc lying around, since it
118 is a useful bit of info */
119
120struct frame_extra_info
121{
122 CORE_ADDR return_pc;
123 int leaf_function;
124 int f_offset;
63978407 125};
c906108c 126
cc17453a 127#if 0
091be84d
CF		 128#ifdef _WIN32_WCE
129char **sh_register_names = sh3_reg_names;
130#else
c906108c 131char **sh_register_names = sh_generic_reg_names;
091be84d 132#endif
cc17453a 133#endif
c906108c 134
cc17453a
EZ		 135static char *
136sh_generic_register_name (int reg_nr)
c5aa993b 137{
cc17453a 138 static char *register_names[] =
c5aa993b 139 {
cc17453a
EZ		 140 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
141 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
142 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
143 "fpul", "fpscr",
144 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
145 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
146 "ssr", "spc",
147 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
148 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
149 };
150 if (reg_nr < 0)
151 return NULL;
152 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
153 return NULL;
154 return register_names[reg_nr];
155}
156
157static char *
158sh_sh_register_name (int reg_nr)
159{
160 static char *register_names[] =
63978407 161 {
cc17453a
EZ		 162 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
163 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
164 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
165 "", "",
166 "", "", "", "", "", "", "", "",
167 "", "", "", "", "", "", "", "",
168 "", "",
169 "", "", "", "", "", "", "", "",
170 "", "", "", "", "", "", "", "",
171 };
172 if (reg_nr < 0)
173 return NULL;
174 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
175 return NULL;
176 return register_names[reg_nr];
177}
178
179static char *
180sh_sh3_register_name (int reg_nr)
181{
182 static char *register_names[] =
c5aa993b 183 {
cc17453a
EZ		 184 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
185 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
186 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
187 "", "",
188 "", "", "", "", "", "", "", "",
189 "", "", "", "", "", "", "", "",
190 "ssr", "spc",
191 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
192 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
193 };
194 if (reg_nr < 0)
195 return NULL;
196 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
197 return NULL;
198 return register_names[reg_nr];
199}
200
201static char *
202sh_sh3e_register_name (int reg_nr)
203{
204 static char *register_names[] =
63978407 205 {
cc17453a
EZ		 206 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
207 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
208 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
209 "fpul", "fpscr",
210 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
211 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
212 "ssr", "spc",
213 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
214 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
215 };
216 if (reg_nr < 0)
217 return NULL;
218 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
219 return NULL;
220 return register_names[reg_nr];
221}
222
223static char *
224sh_sh_dsp_register_name (int reg_nr)
225{
226 static char *register_names[] =
c5aa993b 227 {
cc17453a
EZ		 228 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
229 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
230 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
231 "", "dsr",
232 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
233 "y0", "y1", "", "", "", "", "", "mod",
234 "", "",
235 "rs", "re", "", "", "", "", "", "",
236 "", "", "", "", "", "", "", "",
237 };
238 if (reg_nr < 0)
239 return NULL;
240 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
241 return NULL;
242 return register_names[reg_nr];
243}
244
245static char *
246sh_sh3_dsp_register_name (int reg_nr)
247{
248 static char *register_names[] =
c5aa993b 249 {
cc17453a
EZ		 250 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
251 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
252 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
253 "", "dsr",
254 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
255 "y0", "y1", "", "", "", "", "", "mod",
256 "ssr", "spc",
257 "rs", "re", "", "", "", "", "", "",
258 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
259 "", "", "", "", "", "", "", "",
260 };
261 if (reg_nr < 0)
262 return NULL;
263 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
264 return NULL;
265 return register_names[reg_nr];
266}
267
53116e27
EZ		 268static char *
269sh_sh4_register_name (int reg_nr)
270{
271 static char *register_names[] =
272 {
a38d2a54 273 /* general registers 0-15 */
53116e27
EZ		 274 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
275 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
a38d2a54 276 /* 16 - 22 */
53116e27 277 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
a38d2a54 278 /* 23, 24 */
53116e27 279 "fpul", "fpscr",
a38d2a54 280 /* floating point registers 25 - 40 */
53116e27
EZ		 281 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
282 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
a38d2a54 283 /* 41, 42 */
53116e27 284 "ssr", "spc",
a38d2a54 285 /* bank 0 43 - 50 */
53116e27 286 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
a38d2a54 287 /* bank 1 51 - 58 */
53116e27 288 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
a38d2a54 289 /* double precision (pseudo) 59 - 66 */
fe9f384f 290 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
a38d2a54 291 /* vectors (pseudo) 67 - 70 */
fe9f384f 292 "fv0", "fv4", "fv8", "fv12",
a38d2a54
EZ		 293 /* FIXME: missing XF 71 - 86 */
294 /* FIXME: missing XD 87 - 94 */
53116e27
EZ		 295 };
296 if (reg_nr < 0)
297 return NULL;
298 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
299 return NULL;
300 return register_names[reg_nr];
301}
302
cc17453a 303static unsigned char *
fba45db2 304sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
cc17453a
EZ		 305{
306 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
307 static unsigned char breakpoint[] = {0xc3, 0xc3};
308
309 *lenptr = sizeof (breakpoint);
310 return breakpoint;
311}
c906108c
SS		 312
313/* Prologue looks like
c5aa993b
JM		 314 [mov.l <regs>,@-r15]...
315 [sts.l pr,@-r15]
316 [mov.l r14,@-r15]
317 [mov r15,r14]
8db62801
EZ		 318
319 Actually it can be more complicated than this. For instance, with
320 newer gcc's:
321
322 mov.l r14,@-r15
323 add #-12,r15
324 mov r15,r14
325 mov r4,r1
326 mov r5,r2
327 mov.l r6,@(4,r14)
328 mov.l r7,@(8,r14)
329 mov.b r1,@r14
330 mov r14,r1
331 mov r14,r1
332 add #2,r1
333 mov.w r2,@r1
334
c5aa993b 335 */
c906108c 336
8db62801
EZ		 337/* STS.L PR,@-r15 0100111100100010
338 r15-4-->r15, PR-->(r15) */
c906108c 339#define IS_STS(x) ((x) == 0x4f22)
8db62801
EZ		 340
341/* MOV.L Rm,@-r15 00101111mmmm0110
342 r15-4-->r15, Rm-->(R15) */
c906108c 343#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 344
c906108c 345#define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
8db62801
EZ		 346
347/* MOV r15,r14 0110111011110011
348 r15-->r14 */
c906108c 349#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ		 350
351/* ADD #imm,r15 01111111iiiiiiii
352 r15+imm-->r15 */
c906108c 353#define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 354
c906108c
SS		 355#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
356#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ		 357
358/* ADD r3,r15 0011111100111100
359 r15+r3-->r15 */
c906108c 360#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ		 361
362/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
8db62801 363 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
8db62801 364 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
c906108c 365#define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
c906108c 366
8db62801 367/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
8db62801 368 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
8db62801
EZ		 369 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
370 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
371#define IS_ARG_MOV(x) \
372(((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
cc17453a
EZ		 373 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
374 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
8db62801
EZ		 375
376/* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
377 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
378#define IS_MOV_R14(x) \
cc17453a 379 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
8db62801
EZ		 380
381#define FPSCR_SZ (1 << 20)
c906108c 382
c906108c
SS		 383/* Skip any prologue before the guts of a function */
384
8db62801
EZ		 385/* Skip the prologue using the debug information. If this fails we'll
386 fall back on the 'guess' method below. */
387static CORE_ADDR
fba45db2 388after_prologue (CORE_ADDR pc)
8db62801
EZ		 389{
390 struct symtab_and_line sal;
391 CORE_ADDR func_addr, func_end;
392
393 /* If we can not find the symbol in the partial symbol table, then
394 there is no hope we can determine the function's start address
395 with this code. */
396 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
397 return 0;
398
399 /* Get the line associated with FUNC_ADDR. */
400 sal = find_pc_line (func_addr, 0);
401
402 /* There are only two cases to consider. First, the end of the source line
403 is within the function bounds. In that case we return the end of the
404 source line. Second is the end of the source line extends beyond the
405 bounds of the current function. We need to use the slow code to
406 examine instructions in that case. */
407 if (sal.end < func_end)
408 return sal.end;
409 else
410 return 0;
411}
412
413/* Here we look at each instruction in the function, and try to guess
414 where the prologue ends. Unfortunately this is not always
415 accurate. */
416static CORE_ADDR
fba45db2 417skip_prologue_hard_way (CORE_ADDR start_pc)
c906108c 418{
2bfa91ee 419 CORE_ADDR here, end;
8db62801 420 int updated_fp = 0;
2bfa91ee
EZ		 421
422 if (!start_pc)
423 return 0;
424
425 for (here = start_pc, end = start_pc + (2 * 28); here < end;)
c906108c 426 {
2bfa91ee
EZ		 427 int w = read_memory_integer (here, 2);
428 here += 2;
429 if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w)
8db62801
EZ		 430 || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w)
431 || IS_ARG_MOV (w) || IS_MOV_R14 (w))
2bfa91ee
EZ		 432 {
433 start_pc = here;
2bfa91ee 434 }
8db62801
EZ		 435 else if (IS_MOV_SP_FP (w))
436 {
437 start_pc = here;
438 updated_fp = 1;
439 }
440 else
441 /* Don't bail out yet, if we are before the copy of sp. */
442 if (updated_fp)
443 break;
c906108c
SS		 444 }
445
446 return start_pc;
447}
448
cc17453a 449static CORE_ADDR
fba45db2 450sh_skip_prologue (CORE_ADDR pc)
8db62801
EZ		 451{
452 CORE_ADDR post_prologue_pc;
453
454 /* See if we can determine the end of the prologue via the symbol table.
455 If so, then return either PC, or the PC after the prologue, whichever
456 is greater. */
457
458 post_prologue_pc = after_prologue (pc);
459
460 /* If after_prologue returned a useful address, then use it. Else
461 fall back on the instruction skipping code. */
462 if (post_prologue_pc != 0)
463 return max (pc, post_prologue_pc);
464 else
465 return (skip_prologue_hard_way (pc));
466}
467
cc17453a
EZ		 468/* Immediately after a function call, return the saved pc.
469 Can't always go through the frames for this because on some machines
470 the new frame is not set up until the new function executes
471 some instructions.
472
473 The return address is the value saved in the PR register + 4 */
474static CORE_ADDR
fba45db2 475sh_saved_pc_after_call (struct frame_info *frame)
cc17453a
EZ		 476{
477 return (ADDR_BITS_REMOVE(read_register(PR_REGNUM)));
478}
479
480/* Should call_function allocate stack space for a struct return? */
481static int
fba45db2 482sh_use_struct_convention (int gcc_p, struct type *type)
cc17453a
EZ		 483{
484 return (TYPE_LENGTH (type) > 1);
485}
486
487/* Store the address of the place in which to copy the structure the
488 subroutine will return. This is called from call_function.
489
490 We store structs through a pointer passed in R0 */
491static void
fba45db2 492sh_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
cc17453a
EZ		 493{
494 write_register (STRUCT_RETURN_REGNUM, (addr));
495}
c906108c 496
cc17453a
EZ		 497/* Disassemble an instruction. */
498static int
fba45db2 499gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
c906108c
SS		 500{
501 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
502 return print_insn_sh (memaddr, info);
503 else
504 return print_insn_shl (memaddr, info);
505}
506
507/* Given a GDB frame, determine the address of the calling function's frame.
508 This will be used to create a new GDB frame struct, and then
509 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
510
511 For us, the frame address is its stack pointer value, so we look up
512 the function prologue to determine the caller's sp value, and return it. */
cc17453a 513static CORE_ADDR
fba45db2 514sh_frame_chain (struct frame_info *frame)
c906108c
SS		 515{
516 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
517 return frame->frame; /* dummy frame same as caller's frame */
2bfa91ee 518 if (frame->pc && !inside_entry_file (frame->pc))
cc17453a 519 return read_memory_integer (FRAME_FP (frame) + frame->extra_info->f_offset, 4);
c906108c
SS		 520 else
521 return 0;
522}
523
524/* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
525 we might want to do here is to check REGNUM against the clobber mask, and
526 somehow flag it as invalid if it isn't saved on the stack somewhere. This
527 would provide a graceful failure mode when trying to get the value of
528 caller-saves registers for an inner frame. */
529
cc17453a 530static CORE_ADDR
fba45db2 531sh_find_callers_reg (struct frame_info *fi, int regnum)
c906108c 532{
c906108c
SS		 533 for (; fi; fi = fi->next)
534 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
535 /* When the caller requests PR from the dummy frame, we return PC because
c5aa993b 536 that's where the previous routine appears to have done a call from. */
c906108c 537 return generic_read_register_dummy (fi->pc, fi->frame, regnum);
c5aa993b 538 else
c906108c 539 {
cc17453a 540 FRAME_INIT_SAVED_REGS (fi);
2bfa91ee
EZ		 541 if (!fi->pc)
542 return 0;
cc17453a
EZ		 543 if (fi->saved_regs[regnum] != 0)
544 return read_memory_integer (fi->saved_regs[regnum],
c5aa993b 545 REGISTER_RAW_SIZE (regnum));
c906108c
SS		 546 }
547 return read_register (regnum);
548}
549
550/* Put here the code to store, into a struct frame_saved_regs, the
551 addresses of the saved registers of frame described by FRAME_INFO.
552 This includes special registers such as pc and fp saved in special
553 ways in the stack frame. sp is even more special: the address we
554 return for it IS the sp for the next frame. */
cc17453a 555static void
fba45db2 556sh_nofp_frame_init_saved_regs (struct frame_info *fi)
c906108c
SS		 557{
558 int where[NUM_REGS];
559 int rn;
560 int have_fp = 0;
561 int depth;
562 int pc;
563 int opc;
564 int insn;
565 int r3_val = 0;
c5aa993b 566 char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
cc17453a
EZ		 567
568 if (fi->saved_regs == NULL)
569 frame_saved_regs_zalloc (fi);
570 else
571 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
572
573 if (dummy_regs)
574 {
575 /* DANGER! This is ONLY going to work if the char buffer format of
576 the saved registers is byte-for-byte identical to the
577 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
578 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
579 return;
580 }
581
582 fi->extra_info->leaf_function = 1;
583 fi->extra_info->f_offset = 0;
584
585 for (rn = 0; rn < NUM_REGS; rn++)
586 where[rn] = -1;
587
588 depth = 0;
589
590 /* Loop around examining the prologue insns until we find something
591 that does not appear to be part of the prologue. But give up
592 after 20 of them, since we're getting silly then. */
593
594 pc = get_pc_function_start (fi->pc);
595 if (!pc)
596 {
597 fi->pc = 0;
598 return;
599 }
600
601 for (opc = pc + (2 * 28); pc < opc; pc += 2)
602 {
603 insn = read_memory_integer (pc, 2);
604 /* See where the registers will be saved to */
605 if (IS_PUSH (insn))
606 {
607 rn = GET_PUSHED_REG (insn);
608 where[rn] = depth;
609 depth += 4;
610 }
611 else if (IS_STS (insn))
612 {
613 where[PR_REGNUM] = depth;
614 /* If we're storing the pr then this isn't a leaf */
615 fi->extra_info->leaf_function = 0;
616 depth += 4;
617 }
618 else if (IS_MOV_R3 (insn))
619 {
620 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
621 }
622 else if (IS_SHLL_R3 (insn))
623 {
624 r3_val <<= 1;
625 }
626 else if (IS_ADD_R3SP (insn))
627 {
628 depth += -r3_val;
629 }
630 else if (IS_ADD_SP (insn))
631 {
632 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
633 }
634 else if (IS_MOV_SP_FP (insn))
635 break;
636#if 0 /* This used to just stop when it found an instruction that
637 was not considered part of the prologue. Now, we just
638 keep going looking for likely instructions. */
639 else
640 break;
641#endif
642 }
643
644 /* Now we know how deep things are, we can work out their addresses */
645
646 for (rn = 0; rn < NUM_REGS; rn++)
647 {
648 if (where[rn] >= 0)
649 {
650 if (rn == FP_REGNUM)
651 have_fp = 1;
c906108c 652
cc17453a
EZ		 653 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
654 }
655 else
656 {
657 fi->saved_regs[rn] = 0;
658 }
659 }
660
661 if (have_fp)
662 {
663 fi->saved_regs[SP_REGNUM] = read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
664 }
665 else
666 {
667 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
668 }
669
670 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
671 /* Work out the return pc - either from the saved pr or the pr
672 value */
673}
674
675static void
fba45db2 676sh_fp_frame_init_saved_regs (struct frame_info *fi)
cc17453a
EZ		 677{
678 int where[NUM_REGS];
679 int rn;
680 int have_fp = 0;
681 int depth;
682 int pc;
683 int opc;
684 int insn;
685 int r3_val = 0;
686 char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
687
688 if (fi->saved_regs == NULL)
689 frame_saved_regs_zalloc (fi);
690 else
691 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
692
c906108c
SS		 693 if (dummy_regs)
694 {
695 /* DANGER! This is ONLY going to work if the char buffer format of
c5aa993b
JM		 696 the saved registers is byte-for-byte identical to the
697 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
cc17453a 698 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
c906108c
SS		 699 return;
700 }
701
cc17453a
EZ		 702 fi->extra_info->leaf_function = 1;
703 fi->extra_info->f_offset = 0;
c906108c
SS		 704
705 for (rn = 0; rn < NUM_REGS; rn++)
706 where[rn] = -1;
707
708 depth = 0;
709
710 /* Loop around examining the prologue insns until we find something
711 that does not appear to be part of the prologue. But give up
712 after 20 of them, since we're getting silly then. */
713
2bfa91ee
EZ		 714 pc = get_pc_function_start (fi->pc);
715 if (!pc)
c906108c 716 {
2bfa91ee
EZ		 717 fi->pc = 0;
718 return;
719 }
720
721 for (opc = pc + (2 * 28); pc < opc; pc += 2)
722 {
723 insn = read_memory_integer (pc, 2);
c906108c
SS		 724 /* See where the registers will be saved to */
725 if (IS_PUSH (insn))
726 {
c906108c
SS		 727 rn = GET_PUSHED_REG (insn);
728 where[rn] = depth;
c906108c
SS		 729 depth += 4;
730 }
731 else if (IS_STS (insn))
732 {
c906108c 733 where[PR_REGNUM] = depth;
c906108c 734 /* If we're storing the pr then this isn't a leaf */
cc17453a 735 fi->extra_info->leaf_function = 0;
c906108c
SS		 736 depth += 4;
737 }
738 else if (IS_MOV_R3 (insn))
739 {
740 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 741 }
742 else if (IS_SHLL_R3 (insn))
743 {
744 r3_val <<= 1;
c906108c
SS		 745 }
746 else if (IS_ADD_R3SP (insn))
747 {
748 depth += -r3_val;
c906108c
SS		 749 }
750 else if (IS_ADD_SP (insn))
751 {
c906108c 752 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 753 }
754 else if (IS_FMOV (insn))
755 {
cc17453a 756 if (read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM) & FPSCR_SZ)
c906108c
SS		 757 {
758 depth += 8;
759 }
760 else
761 {
762 depth += 4;
763 }
764 }
2bfa91ee
EZ		 765 else if (IS_MOV_SP_FP (insn))
766 break;
767#if 0 /* This used to just stop when it found an instruction that
768 was not considered part of the prologue. Now, we just
769 keep going looking for likely instructions. */
c906108c
SS		 770 else
771 break;
2bfa91ee 772#endif
c906108c
SS		 773 }
774
775 /* Now we know how deep things are, we can work out their addresses */
776
777 for (rn = 0; rn < NUM_REGS; rn++)
778 {
779 if (where[rn] >= 0)
780 {
781 if (rn == FP_REGNUM)
782 have_fp = 1;
783
cc17453a 784 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
c906108c
SS		 785 }
786 else
787 {
cc17453a 788 fi->saved_regs[rn] = 0;
c906108c
SS		 789 }
790 }
791
792 if (have_fp)
793 {
cc17453a 794 fi->saved_regs[SP_REGNUM] = read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
c906108c
SS		 795 }
796 else
797 {
cc17453a 798 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
c906108c
SS		 799 }
800
cc17453a 801 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
c906108c
SS		 802 /* Work out the return pc - either from the saved pr or the pr
803 value */
804}
805
cc17453a
EZ		 806/* Initialize the extra info saved in a FRAME */
807static void
fba45db2 808sh_init_extra_frame_info (int fromleaf, struct frame_info *fi)
c906108c 809{
cc17453a
EZ		 810
811 fi->extra_info = (struct frame_extra_info *)
812 frame_obstack_alloc (sizeof (struct frame_extra_info));
c906108c
SS		 813
814 if (fi->next)
815 fi->pc = FRAME_SAVED_PC (fi->next);
816
817 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
818 {
819 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
c5aa993b
JM		 820 by assuming it's always FP. */
821 fi->frame = generic_read_register_dummy (fi->pc, fi->frame,
822 SP_REGNUM);
cc17453a
EZ		 823 fi->extra_info->return_pc = generic_read_register_dummy (fi->pc, fi->frame,
824 PC_REGNUM);
825 fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4);
826 fi->extra_info->leaf_function = 0;
c906108c
SS		 827 return;
828 }
829 else
830 {
cc17453a
EZ		 831 FRAME_INIT_SAVED_REGS (fi);
832 fi->extra_info->return_pc = sh_find_callers_reg (fi, PR_REGNUM);
c906108c
SS		 833 }
834}
835
cc17453a
EZ		 836/* Extract from an array REGBUF containing the (raw) register state
837 the address in which a function should return its structure value,
838 as a CORE_ADDR (or an expression that can be used as one). */
b3df3fff 839static CORE_ADDR
0c8053b6 840sh_extract_struct_value_address (char *regbuf)
cc17453a
EZ		 841{
842 return (extract_address ((regbuf), REGISTER_RAW_SIZE (0)));
843}
844
845static CORE_ADDR
fba45db2 846sh_frame_saved_pc (struct frame_info *frame)
cc17453a
EZ		 847{
848 return ((frame)->extra_info->return_pc);
849}
850
c906108c
SS		 851/* Discard from the stack the innermost frame,
852 restoring all saved registers. */
cc17453a 853static void
fba45db2 854sh_pop_frame (void)
c906108c
SS		 855{
856 register struct frame_info *frame = get_current_frame ();
857 register CORE_ADDR fp;
858 register int regnum;
c906108c
SS		 859
860 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
861 generic_pop_dummy_frame ();
862 else
c5aa993b
JM		 863 {
864 fp = FRAME_FP (frame);
cc17453a 865 FRAME_INIT_SAVED_REGS (frame);
c906108c 866
c5aa993b
JM		 867 /* Copy regs from where they were saved in the frame */
868 for (regnum = 0; regnum < NUM_REGS; regnum++)
cc17453a
EZ		 869 if (frame->saved_regs[regnum])
870 write_register (regnum, read_memory_integer (frame->saved_regs[regnum], 4));
c906108c 871
cc17453a 872 write_register (PC_REGNUM, frame->extra_info->return_pc);
c5aa993b
JM		 873 write_register (SP_REGNUM, fp + 4);
874 }
c906108c
SS		 875 flush_cached_frames ();
876}
877
878/* Function: push_arguments
879 Setup the function arguments for calling a function in the inferior.
880
881 On the Hitachi SH architecture, there are four registers (R4 to R7)
882 which are dedicated for passing function arguments. Up to the first
883 four arguments (depending on size) may go into these registers.
884 The rest go on the stack.
885
886 Arguments that are smaller than 4 bytes will still take up a whole
887 register or a whole 32-bit word on the stack, and will be
888 right-justified in the register or the stack word. This includes
889 chars, shorts, and small aggregate types.
890
891 Arguments that are larger than 4 bytes may be split between two or
892 more registers. If there are not enough registers free, an argument
893 may be passed partly in a register (or registers), and partly on the
894 stack. This includes doubles, long longs, and larger aggregates.
895 As far as I know, there is no upper limit to the size of aggregates
896 that will be passed in this way; in other words, the convention of
897 passing a pointer to a large aggregate instead of a copy is not used.
898
899 An exceptional case exists for struct arguments (and possibly other
900 aggregates such as arrays) if the size is larger than 4 bytes but
901 not a multiple of 4 bytes. In this case the argument is never split
902 between the registers and the stack, but instead is copied in its
903 entirety onto the stack, AND also copied into as many registers as
904 there is room for. In other words, space in registers permitting,
905 two copies of the same argument are passed in. As far as I can tell,
906 only the one on the stack is used, although that may be a function
907 of the level of compiler optimization. I suspect this is a compiler
908 bug. Arguments of these odd sizes are left-justified within the
909 word (as opposed to arguments smaller than 4 bytes, which are
910 right-justified).
c5aa993b 911
c906108c
SS		 912 If the function is to return an aggregate type such as a struct, it
913 is either returned in the normal return value register R0 (if its
914 size is no greater than one byte), or else the caller must allocate
915 space into which the callee will copy the return value (if the size
916 is greater than one byte). In this case, a pointer to the return
917 value location is passed into the callee in register R2, which does
918 not displace any of the other arguments passed in via registers R4
919 to R7. */
920
cc17453a 921static CORE_ADDR
34e9d9bb
EZ		 922sh_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
923 int struct_return, CORE_ADDR struct_addr)
c906108c
SS		 924{
925 int stack_offset, stack_alloc;
926 int argreg;
927 int argnum;
928 struct type *type;
929 CORE_ADDR regval;
930 char *val;
931 char valbuf[4];
932 int len;
933 int odd_sized_struct;
934
935 /* first force sp to a 4-byte alignment */
936 sp = sp & ~3;
937
938 /* The "struct return pointer" pseudo-argument has its own dedicated
939 register */
940 if (struct_return)
c5aa993b 941 write_register (STRUCT_RETURN_REGNUM, struct_addr);
c906108c
SS		 942
943 /* Now make sure there's space on the stack */
cc17453a 944 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
c5aa993b
JM		 945 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
946 sp -= stack_alloc; /* make room on stack for args */
c906108c 947
c906108c
SS		 948 /* Now load as many as possible of the first arguments into
949 registers, and push the rest onto the stack. There are 16 bytes
950 in four registers available. Loop thru args from first to last. */
951
952 argreg = ARG0_REGNUM;
953 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
954 {
955 type = VALUE_TYPE (args[argnum]);
c5aa993b
JM		 956 len = TYPE_LENGTH (type);
957 memset (valbuf, 0, sizeof (valbuf));
c906108c 958 if (len < 4)
cc17453a
EZ		 959 {
960 /* value gets right-justified in the register or stack word */
c5aa993b
JM		 961 memcpy (valbuf + (4 - len),
962 (char *) VALUE_CONTENTS (args[argnum]), len);
963 val = valbuf;
964 }
c906108c 965 else
c5aa993b 966 val = (char *) VALUE_CONTENTS (args[argnum]);
c906108c
SS		 967
968 if (len > 4 && (len & 3) != 0)
c5aa993b
JM		 969 odd_sized_struct = 1; /* such structs go entirely on stack */
970 else
c906108c
SS		 971 odd_sized_struct = 0;
972 while (len > 0)
973 {
974 if (argreg > ARGLAST_REGNUM || odd_sized_struct)
c5aa993b 975 { /* must go on the stack */
c906108c
SS		 976 write_memory (sp + stack_offset, val, 4);
977 stack_offset += 4;
978 }
979 /* NOTE WELL!!!!! This is not an "else if" clause!!!
980 That's because some *&^%$ things get passed on the stack
981 AND in the registers! */
982 if (argreg <= ARGLAST_REGNUM)
c5aa993b
JM		 983 { /* there's room in a register */
984 regval = extract_address (val, REGISTER_RAW_SIZE (argreg));
c906108c
SS		 985 write_register (argreg++, regval);
986 }
987 /* Store the value 4 bytes at a time. This means that things
988 larger than 4 bytes may go partly in registers and partly
989 on the stack. */
c5aa993b
JM		 990 len -= REGISTER_RAW_SIZE (argreg);
991 val += REGISTER_RAW_SIZE (argreg);
c906108c
SS		 992 }
993 }
994 return sp;
995}
996
997/* Function: push_return_address (pc)
998 Set up the return address for the inferior function call.
999 Needed for targets where we don't actually execute a JSR/BSR instruction */
1000
cc17453a 1001static CORE_ADDR
fba45db2 1002sh_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
c906108c
SS		 1003{
1004 write_register (PR_REGNUM, CALL_DUMMY_ADDRESS ());
1005 return sp;
1006}
1007
1008/* Function: fix_call_dummy
1009 Poke the callee function's address into the destination part of
1010 the CALL_DUMMY. The address is actually stored in a data word
1011 following the actualy CALL_DUMMY instructions, which will load
1012 it into a register using PC-relative addressing. This function
1013 expects the CALL_DUMMY to look like this:
1014
c5aa993b
JM		 1015 mov.w @(2,PC), R8
1016 jsr @R8
1017 nop
1018 trap
1019 <destination>
1020 */
c906108c
SS		 1021
1022#if 0
1023void
fba45db2
KB		 1024sh_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
1025 value_ptr *args, struct type *type, int gcc_p)
c906108c
SS		 1026{
1027 *(unsigned long *) (dummy + 8) = fun;
1028}
1029#endif
1030
cc17453a
EZ		 1031static int
1032sh_coerce_float_to_double (struct type *formal, struct type *actual)
1033{
1034 return 1;
1035}
c906108c 1036
cc17453a
EZ		 1037/* Find a function's return value in the appropriate registers (in
1038 regbuf), and copy it into valbuf. Extract from an array REGBUF
1039 containing the (raw) register state a function return value of type
1040 TYPE, and copy that, in virtual format, into VALBUF. */
1041static void
fba45db2 1042sh_extract_return_value (struct type *type, char *regbuf, char *valbuf)
c906108c 1043{
cc17453a 1044 int len = TYPE_LENGTH (type);
c906108c 1045
cc17453a
EZ		 1046 if (len <= 4)
1047 memcpy (valbuf, ((char *) regbuf) + 4 - len, len);
1048 else if (len <= 8)
1049 memcpy (valbuf, ((char *) regbuf) + 8 - len, len);
1050 else
1051 error ("bad size for return value");
1052}
c906108c 1053
cc17453a
EZ		 1054/* Write into appropriate registers a function return value
1055 of type TYPE, given in virtual format.
1056 If the architecture is sh4 or sh3e, store a function's return value
1057 in the R0 general register or in the FP0 floating point register,
1058 depending on the type of the return value. In all the other cases
1059 the result is stored in r0. */
1060static void
1061sh_default_store_return_value (struct type *type, char *valbuf)
1062{
1063 write_register_bytes (REGISTER_BYTE (0),
1064 valbuf, TYPE_LENGTH (type));
1065}
c906108c 1066
cc17453a
EZ		 1067static void
1068sh3e_sh4_store_return_value (struct type *type, char *valbuf)
1069{
1070 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1071 write_register_bytes (REGISTER_BYTE (FP0_REGNUM),
1072 valbuf, TYPE_LENGTH (type));
1073 else
1074 write_register_bytes (REGISTER_BYTE (0),
1075 valbuf, TYPE_LENGTH (type));
c906108c
SS		 1076}
1077
cc17453a 1078
c906108c
SS		 1079/* Print the registers in a form similar to the E7000 */
1080
1081static void
fba45db2 1082sh_generic_show_regs (void)
c906108c 1083{
cc17453a
EZ		 1084 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1085 paddr (read_register (PC_REGNUM)),
c62a7c7b 1086 (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM),
cc17453a
EZ		 1087 (long) read_register (PR_REGNUM),
1088 (long) read_register (MACH_REGNUM),
1089 (long) read_register (MACL_REGNUM));
1090
1091 printf_filtered ("GBR=%08lx VBR=%08lx",
1092 (long) read_register (GBR_REGNUM),
1093 (long) read_register (VBR_REGNUM));
1094
1095 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1096 (long) read_register (0),
1097 (long) read_register (1),
1098 (long) read_register (2),
1099 (long) read_register (3),
1100 (long) read_register (4),
1101 (long) read_register (5),
1102 (long) read_register (6),
1103 (long) read_register (7));
1104 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1105 (long) read_register (8),
1106 (long) read_register (9),
1107 (long) read_register (10),
1108 (long) read_register (11),
1109 (long) read_register (12),
1110 (long) read_register (13),
1111 (long) read_register (14),
1112 (long) read_register (15));
1113}
c906108c 1114
cc17453a 1115static void
fba45db2 1116sh3_show_regs (void)
cc17453a 1117{
d4f3574e
SS		 1118 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1119 paddr (read_register (PC_REGNUM)),
c62a7c7b 1120 (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM),
d4f3574e
SS		 1121 (long) read_register (PR_REGNUM),
1122 (long) read_register (MACH_REGNUM),
1123 (long) read_register (MACL_REGNUM));
1124
1125 printf_filtered ("GBR=%08lx VBR=%08lx",
1126 (long) read_register (GBR_REGNUM),
1127 (long) read_register (VBR_REGNUM));
cc17453a
EZ		 1128 printf_filtered (" SSR=%08lx SPC=%08lx",
1129 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1130 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
c906108c 1131
d4f3574e
SS		 1132 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1133 (long) read_register (0),
1134 (long) read_register (1),
1135 (long) read_register (2),
1136 (long) read_register (3),
1137 (long) read_register (4),
1138 (long) read_register (5),
1139 (long) read_register (6),
1140 (long) read_register (7));
1141 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1142 (long) read_register (8),
1143 (long) read_register (9),
1144 (long) read_register (10),
1145 (long) read_register (11),
1146 (long) read_register (12),
1147 (long) read_register (13),
1148 (long) read_register (14),
1149 (long) read_register (15));
c906108c
SS		 1150}
1151
53116e27 1152
cc17453a 1153static void
fba45db2 1154sh3e_show_regs (void)
cc17453a
EZ		 1155{
1156 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1157 paddr (read_register (PC_REGNUM)),
c62a7c7b 1158 (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM),
cc17453a
EZ		 1159 (long) read_register (PR_REGNUM),
1160 (long) read_register (MACH_REGNUM),
1161 (long) read_register (MACL_REGNUM));
1162
1163 printf_filtered ("GBR=%08lx VBR=%08lx",
1164 (long) read_register (GBR_REGNUM),
1165 (long) read_register (VBR_REGNUM));
1166 printf_filtered (" SSR=%08lx SPC=%08lx",
1167 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1168 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
1169 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1170 (long) read_register (gdbarch_tdep (current_gdbarch)->FPUL_REGNUM),
1171 (long) read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM));
c906108c 1172
cc17453a
EZ		 1173 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1174 (long) read_register (0),
1175 (long) read_register (1),
1176 (long) read_register (2),
1177 (long) read_register (3),
1178 (long) read_register (4),
1179 (long) read_register (5),
1180 (long) read_register (6),
1181 (long) read_register (7));
1182 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1183 (long) read_register (8),
1184 (long) read_register (9),
1185 (long) read_register (10),
1186 (long) read_register (11),
1187 (long) read_register (12),
1188 (long) read_register (13),
1189 (long) read_register (14),
1190 (long) read_register (15));
1191
1192 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1193 (long) read_register (FP0_REGNUM + 0),
1194 (long) read_register (FP0_REGNUM + 1),
1195 (long) read_register (FP0_REGNUM + 2),
1196 (long) read_register (FP0_REGNUM + 3),
1197 (long) read_register (FP0_REGNUM + 4),
1198 (long) read_register (FP0_REGNUM + 5),
1199 (long) read_register (FP0_REGNUM + 6),
1200 (long) read_register (FP0_REGNUM + 7));
1201 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1202 (long) read_register (FP0_REGNUM + 8),
1203 (long) read_register (FP0_REGNUM + 9),
1204 (long) read_register (FP0_REGNUM + 10),
1205 (long) read_register (FP0_REGNUM + 11),
1206 (long) read_register (FP0_REGNUM + 12),
1207 (long) read_register (FP0_REGNUM + 13),
1208 (long) read_register (FP0_REGNUM + 14),
1209 (long) read_register (FP0_REGNUM + 15));
1210}
1211
1212static void
fba45db2 1213sh3_dsp_show_regs (void)
c906108c 1214{
cc17453a
EZ		 1215 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1216 paddr (read_register (PC_REGNUM)),
c62a7c7b 1217 (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM),
cc17453a
EZ		 1218 (long) read_register (PR_REGNUM),
1219 (long) read_register (MACH_REGNUM),
1220 (long) read_register (MACL_REGNUM));
c906108c 1221
cc17453a
EZ		 1222 printf_filtered ("GBR=%08lx VBR=%08lx",
1223 (long) read_register (GBR_REGNUM),
1224 (long) read_register (VBR_REGNUM));
1225
1226 printf_filtered (" SSR=%08lx SPC=%08lx",
1227 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1228 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
1229
1230 printf_filtered (" DSR=%08lx",
1231 (long) read_register (gdbarch_tdep (current_gdbarch)->DSR_REGNUM));
1232
1233 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1234 (long) read_register (0),
1235 (long) read_register (1),
1236 (long) read_register (2),
1237 (long) read_register (3),
1238 (long) read_register (4),
1239 (long) read_register (5),
1240 (long) read_register (6),
1241 (long) read_register (7));
1242 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1243 (long) read_register (8),
1244 (long) read_register (9),
1245 (long) read_register (10),
1246 (long) read_register (11),
1247 (long) read_register (12),
1248 (long) read_register (13),
1249 (long) read_register (14),
1250 (long) read_register (15));
1251
1252 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1253 (long) read_register (gdbarch_tdep (current_gdbarch)->A0G_REGNUM) & 0xff,
1254 (long) read_register (gdbarch_tdep (current_gdbarch)->A0_REGNUM),
1255 (long) read_register (gdbarch_tdep (current_gdbarch)->M0_REGNUM),
1256 (long) read_register (gdbarch_tdep (current_gdbarch)->X0_REGNUM),
1257 (long) read_register (gdbarch_tdep (current_gdbarch)->Y0_REGNUM),
1258 (long) read_register (gdbarch_tdep (current_gdbarch)->RS_REGNUM),
1259 (long) read_register (gdbarch_tdep (current_gdbarch)->MOD_REGNUM));
1260 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1261 (long) read_register (gdbarch_tdep (current_gdbarch)->A1G_REGNUM) & 0xff,
1262 (long) read_register (gdbarch_tdep (current_gdbarch)->A1_REGNUM),
1263 (long) read_register (gdbarch_tdep (current_gdbarch)->M1_REGNUM),
1264 (long) read_register (gdbarch_tdep (current_gdbarch)->X1_REGNUM),
1265 (long) read_register (gdbarch_tdep (current_gdbarch)->Y1_REGNUM),
1266 (long) read_register (gdbarch_tdep (current_gdbarch)->RE_REGNUM));
c906108c
SS		 1267}
1268
cc17453a 1269static void
fba45db2 1270sh4_show_regs (void)
cc17453a
EZ		 1271{
1272 int pr = read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM) & 0x80000;
1273 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1274 paddr (read_register (PC_REGNUM)),
c62a7c7b 1275 (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM),
cc17453a
EZ		 1276 (long) read_register (PR_REGNUM),
1277 (long) read_register (MACH_REGNUM),
1278 (long) read_register (MACL_REGNUM));
1279
1280 printf_filtered ("GBR=%08lx VBR=%08lx",
1281 (long) read_register (GBR_REGNUM),
1282 (long) read_register (VBR_REGNUM));
1283 printf_filtered (" SSR=%08lx SPC=%08lx",
1284 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1285 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
1286 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1287 (long) read_register (gdbarch_tdep (current_gdbarch)->FPUL_REGNUM),
1288 (long) read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM));
1289
1290 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1291 (long) read_register (0),
1292 (long) read_register (1),
1293 (long) read_register (2),
1294 (long) read_register (3),
1295 (long) read_register (4),
1296 (long) read_register (5),
1297 (long) read_register (6),
1298 (long) read_register (7));
1299 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1300 (long) read_register (8),
1301 (long) read_register (9),
1302 (long) read_register (10),
1303 (long) read_register (11),
1304 (long) read_register (12),
1305 (long) read_register (13),
1306 (long) read_register (14),
1307 (long) read_register (15));
1308
1309 printf_filtered ((pr
1310 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1311 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1312 (long) read_register (FP0_REGNUM + 0),
1313 (long) read_register (FP0_REGNUM + 1),
1314 (long) read_register (FP0_REGNUM + 2),
1315 (long) read_register (FP0_REGNUM + 3),
1316 (long) read_register (FP0_REGNUM + 4),
1317 (long) read_register (FP0_REGNUM + 5),
1318 (long) read_register (FP0_REGNUM + 6),
1319 (long) read_register (FP0_REGNUM + 7));
1320 printf_filtered ((pr
1321 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1322 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1323 (long) read_register (FP0_REGNUM + 8),
1324 (long) read_register (FP0_REGNUM + 9),
1325 (long) read_register (FP0_REGNUM + 10),
1326 (long) read_register (FP0_REGNUM + 11),
1327 (long) read_register (FP0_REGNUM + 12),
1328 (long) read_register (FP0_REGNUM + 13),
1329 (long) read_register (FP0_REGNUM + 14),
1330 (long) read_register (FP0_REGNUM + 15));
1331}
1332
1333static void
fba45db2 1334sh_dsp_show_regs (void)
cc17453a
EZ		 1335{
1336 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1337 paddr (read_register (PC_REGNUM)),
c62a7c7b 1338 (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM),
cc17453a
EZ		 1339 (long) read_register (PR_REGNUM),
1340 (long) read_register (MACH_REGNUM),
1341 (long) read_register (MACL_REGNUM));
1342
1343 printf_filtered ("GBR=%08lx VBR=%08lx",
1344 (long) read_register (GBR_REGNUM),
1345 (long) read_register (VBR_REGNUM));
1346
1347 printf_filtered (" DSR=%08lx",
1348 (long) read_register (gdbarch_tdep (current_gdbarch)->DSR_REGNUM));
1349
1350 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1351 (long) read_register (0),
1352 (long) read_register (1),
1353 (long) read_register (2),
1354 (long) read_register (3),
1355 (long) read_register (4),
1356 (long) read_register (5),
1357 (long) read_register (6),
1358 (long) read_register (7));
1359 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1360 (long) read_register (8),
1361 (long) read_register (9),
1362 (long) read_register (10),
1363 (long) read_register (11),
1364 (long) read_register (12),
1365 (long) read_register (13),
1366 (long) read_register (14),
1367 (long) read_register (15));
1368
1369 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1370 (long) read_register (gdbarch_tdep (current_gdbarch)->A0G_REGNUM) & 0xff,
1371 (long) read_register (gdbarch_tdep (current_gdbarch)->A0_REGNUM),
1372 (long) read_register (gdbarch_tdep (current_gdbarch)->M0_REGNUM),
1373 (long) read_register (gdbarch_tdep (current_gdbarch)->X0_REGNUM),
1374 (long) read_register (gdbarch_tdep (current_gdbarch)->Y0_REGNUM),
1375 (long) read_register (gdbarch_tdep (current_gdbarch)->RS_REGNUM),
1376 (long) read_register (gdbarch_tdep (current_gdbarch)->MOD_REGNUM));
1377 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1378 (long) read_register (gdbarch_tdep (current_gdbarch)->A1G_REGNUM) & 0xff,
1379 (long) read_register (gdbarch_tdep (current_gdbarch)->A1_REGNUM),
1380 (long) read_register (gdbarch_tdep (current_gdbarch)->M1_REGNUM),
1381 (long) read_register (gdbarch_tdep (current_gdbarch)->X1_REGNUM),
1382 (long) read_register (gdbarch_tdep (current_gdbarch)->Y1_REGNUM),
1383 (long) read_register (gdbarch_tdep (current_gdbarch)->RE_REGNUM));
1384}
1385
53116e27
EZ		 1386void sh_show_regs_command (char *args, int from_tty)
1387{
1388 if (sh_show_regs)
1389 (*sh_show_regs)();
1390}
1391
cc17453a
EZ		 1392/* Index within `registers' of the first byte of the space for
1393 register N. */
1394static int
fba45db2 1395sh_default_register_byte (int reg_nr)
8db62801 1396{
cc17453a
EZ		 1397 return (reg_nr * 4);
1398}
1399
53116e27 1400static int
fba45db2 1401sh_sh4_register_byte (int reg_nr)
53116e27
EZ		 1402{
1403 if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1404 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27
EZ		 1405 return (dr_reg_base_num (reg_nr) * 4);
1406 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
e6c42fda 1407 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1408 return (fv_reg_base_num (reg_nr) * 4);
1409 else
1410 return (reg_nr * 4);
1411}
1412
cc17453a
EZ		 1413/* Number of bytes of storage in the actual machine representation for
1414 register REG_NR. */
1415static int
fba45db2 1416sh_default_register_raw_size (int reg_nr)
cc17453a
EZ		 1417{
1418 return 4;
1419}
1420
53116e27 1421static int
fba45db2 1422sh_sh4_register_raw_size (int reg_nr)
53116e27
EZ		 1423{
1424 if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1425 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27
EZ		 1426 return 8;
1427 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
e6c42fda 1428 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1429 return 16;
1430 else
1431 return 4;
1432}
1433
cc17453a
EZ		 1434/* Number of bytes of storage in the program's representation
1435 for register N. */
1436static int
fba45db2 1437sh_register_virtual_size (int reg_nr)
cc17453a
EZ		 1438{
1439 return 4;
1440}
1441
1442/* Return the GDB type object for the "standard" data type
1443 of data in register N. */
1444
1445static struct type *
fba45db2 1446sh_sh3e_register_virtual_type (int reg_nr)
cc17453a
EZ		 1447{
1448 if ((reg_nr >= FP0_REGNUM
e6c42fda 1449 && (reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM))
cc17453a
EZ		 1450 || (reg_nr == gdbarch_tdep (current_gdbarch)->FPUL_REGNUM))
1451 return builtin_type_float;
8db62801 1452 else
cc17453a
EZ		 1453 return builtin_type_int;
1454}
1455
53116e27 1456static struct type *
fba45db2 1457sh_sh4_register_virtual_type (int reg_nr)
53116e27
EZ		 1458{
1459 if ((reg_nr >= FP0_REGNUM
e6c42fda 1460 && (reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM))
53116e27
EZ		 1461 || (reg_nr == gdbarch_tdep (current_gdbarch)->FPUL_REGNUM))
1462 return builtin_type_float;
1463 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1464 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27
EZ		 1465 return builtin_type_double;
1466 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
e6c42fda 1467 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1468 return sh_sh4_build_float_register_type (3);
1469 else
1470 return builtin_type_int;
1471}
1472
1473static struct type *
1474sh_sh4_build_float_register_type (int high)
1475{
1476 struct type *temp;
1477
1478 temp = create_range_type (NULL, builtin_type_int, 0, high);
1479 return create_array_type (NULL, builtin_type_float, temp);
1480}
1481
cc17453a 1482static struct type *
fba45db2 1483sh_default_register_virtual_type (int reg_nr)
cc17453a
EZ		 1484{
1485 return builtin_type_int;
1486}
1487
fb409745
EZ		 1488/* On the sh4, the DRi pseudo registers are problematic if the target
1489 is little endian. When the user writes one of those registers, for
1490 instance with 'ser var $dr0=1', we want the double to be stored
1491 like this:
1492 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1493 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1494
1495 This corresponds to little endian byte order & big endian word
1496 order. However if we let gdb write the register w/o conversion, it
1497 will write fr0 and fr1 this way:
1498 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1499 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1500 because it will consider fr0 and fr1 as a single LE stretch of memory.
1501
1502 To achieve what we want we must force gdb to store things in
1503 floatformat_ieee_double_littlebyte_bigword (which is defined in
1504 include/floatformat.h and libiberty/floatformat.c.
1505
1506 In case the target is big endian, there is no problem, the
1507 raw bytes will look like:
1508 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1509 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1510
1511 The other pseudo registers (the FVs) also don't pose a problem
1512 because they are stored as 4 individual FP elements. */
1513
1514int
1515sh_sh4_register_convertible (int nr)
1516{
1517 if (TARGET_BYTE_ORDER == LITTLE_ENDIAN)
1518 return (gdbarch_tdep (current_gdbarch)->DR0_REGNUM <= nr
e6c42fda 1519 && nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM);
fb409745
EZ		 1520 else
1521 return 0;
1522}
1523
1524void
1525sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
1526 char *from, char *to)
1527{
1528 if (regnum >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1529 && regnum <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
fb409745
EZ		 1530 {
1531 DOUBLEST val;
1532 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
1533 store_floating(to, TYPE_LENGTH(type), val);
1534 }
1535 else
1536 error("sh_register_convert_to_virtual called with non DR register number");
1537}
1538
1539void
1540sh_sh4_register_convert_to_raw (struct type *type, int regnum,
1541 char *from, char *to)
1542{
1543 if (regnum >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1544 && regnum <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
fb409745
EZ		 1545 {
1546 DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
1547 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
1548 }
1549 else
1550 error("sh_register_convert_to_raw called with non DR register number");
1551}
1552
53116e27
EZ		 1553void
1554sh_fetch_pseudo_register (int reg_nr)
1555{
1556 int base_regnum, portion;
1557
1558 if (!register_cached (reg_nr))
1559 {
1560 if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1561 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27
EZ		 1562 {
1563 base_regnum = dr_reg_base_num (reg_nr);
1564
1565 /* Read the real regs for which this one is an alias. */
1566 for (portion = 0; portion < 2; portion++)
1567 if (!register_cached (base_regnum + portion))
1568 target_fetch_registers (base_regnum + portion);
1569 }
1570 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
e6c42fda 1571 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1572 {
1573 base_regnum = fv_reg_base_num (reg_nr);
1574
1575 /* Read the real regs for which this one is an alias. */
1576 for (portion = 0; portion < 4; portion++)
1577 if (!register_cached (base_regnum + portion))
1578 target_fetch_registers (base_regnum + portion);
1579
1580 }
1581 register_valid [reg_nr] = 1;
1582 }
1583}
1584
1585void
1586sh_store_pseudo_register (int reg_nr)
1587{
1588 int base_regnum, portion;
1589
1590 if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1591 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27
EZ		 1592 {
1593 base_regnum = dr_reg_base_num (reg_nr);
1594
1595 /* Write the real regs for which this one is an alias. */
1596 for (portion = 0; portion < 2; portion++)
1597 {
1598 register_valid[base_regnum + portion] = 1;
1599 target_store_registers (base_regnum + portion);
1600 }
1601 }
1602 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
e6c42fda 1603 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1604 {
1605 base_regnum = fv_reg_base_num (reg_nr);
1606
1607 /* Write the real regs for which this one is an alias. */
1608 for (portion = 0; portion < 4; portion++)
1609 {
1610 register_valid[base_regnum + portion] = 1;
1611 target_store_registers (base_regnum + portion);
1612 }
1613 }
1614}
1615
1616static int
1617fv_reg_base_num (int fv_regnum)
1618{
1619 int fp_regnum;
1620
1621 fp_regnum = FP0_REGNUM +
1622 (fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM) * 4;
1623 return fp_regnum;
1624}
1625
1626static int
1627dr_reg_base_num (int dr_regnum)
1628{
1629 int fp_regnum;
1630
1631 fp_regnum = FP0_REGNUM +
1632 (dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM) * 2;
1633 return fp_regnum;
1634}
1635
1636static void
1637do_fv_register_info (int fv_regnum)
1638{
1639 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
1640 printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1641 fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM,
1642 (int) read_register (first_fp_reg_num),
1643 (int) read_register (first_fp_reg_num + 1),
1644 (int) read_register (first_fp_reg_num + 2),
1645 (int) read_register (first_fp_reg_num + 3));
1646}
1647
1648static void
1649do_dr_register_info (int dr_regnum)
1650{
1651 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1652
1653 printf_filtered ("dr%d\t0x%08x%08x\n",
1654 dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM,
1655 (int) read_register (first_fp_reg_num),
1656 (int) read_register (first_fp_reg_num + 1));
1657}
1658
1659static void
1660sh_do_pseudo_register (int regnum)
1661{
1662 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
8e1a459b 1663 internal_error ("Invalid pseudo register number %d\n", regnum);
a38d2a54
EZ		 1664 else if (regnum >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
1665 && regnum < gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27 1666 do_dr_register_info (regnum);
a38d2a54
EZ		 1667 else if (regnum >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
1668 && regnum <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1669 do_fv_register_info (regnum);
1670}
1671
1672
1673static void
1674sh_do_fp_register (int regnum)
1675{ /* do values for FP (float) regs */
1676 char *raw_buffer;
1677 double flt; /* double extracted from raw hex data */
1678 int inv;
1679 int j;
1680
1681 /* Allocate space for the float. */
1682 raw_buffer = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM));
1683
1684 /* Get the data in raw format. */
1685 if (read_relative_register_raw_bytes (regnum, raw_buffer))
1686 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1687
1688 /* Get the register as a number */
1689 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1690
1691 /* Print the name and some spaces. */
1692 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
1693 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
1694
1695 /* Print the value. */
1696 printf_filtered (inv ? "<invalid float>" : "%-10.9g", flt);
1697
1698 /* Print the fp register as hex. */
1699 printf_filtered ("\t(raw 0x");
1700 for (j = 0; j < REGISTER_RAW_SIZE (regnum); j++)
1701 {
1702 register int idx = TARGET_BYTE_ORDER == BIG_ENDIAN ? j
1703 : REGISTER_RAW_SIZE (regnum) - 1 - j;
1704 printf_filtered ("%02x", (unsigned char) raw_buffer[idx]);
1705 }
1706 printf_filtered (")");
1707 printf_filtered ("\n");
1708}
1709
1710static void
1711sh_do_register (int regnum)
1712{
1713 char raw_buffer[MAX_REGISTER_RAW_SIZE];
1714
1715 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
1716 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
1717
1718 /* Get the data in raw format. */
1719 if (read_relative_register_raw_bytes (regnum, raw_buffer))
1720 printf_filtered ("*value not available*\n");
1721
1722 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
1723 gdb_stdout, 'x', 1, 0, Val_pretty_default);
1724 printf_filtered ("\t");
1725 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
1726 gdb_stdout, 0, 1, 0, Val_pretty_default);
1727 printf_filtered ("\n");
1728}
1729
1730static void
1731sh_print_register (int regnum)
1732{
1733 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1734 internal_error ("Invalid register number %d\n", regnum);
1735
e30839fe 1736 else if (regnum >= 0 && regnum < NUM_REGS)
53116e27
EZ		 1737 {
1738 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
1739 sh_do_fp_register (regnum); /* FP regs */
1740 else
1741 sh_do_register (regnum); /* All other regs */
1742 }
1743
1744 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1745 sh_do_pseudo_register (regnum);
1746}
1747
1748void
1749sh_do_registers_info (int regnum, int fpregs)
1750{
1751 if (regnum != -1) /* do one specified register */
1752 {
1753 if (*(REGISTER_NAME (regnum)) == '\0')
1754 error ("Not a valid register for the current processor type");
1755
1756 sh_print_register (regnum);
1757 }
1758 else
1759 /* do all (or most) registers */
1760 {
1761 regnum = 0;
1762 while (regnum < NUM_REGS)
1763 {
1764 /* If the register name is empty, it is undefined for this
1765 processor, so don't display anything. */
1766 if (REGISTER_NAME (regnum) == NULL
1767 || *(REGISTER_NAME (regnum)) == '\0')
1768 {
1769 regnum++;
1770 continue;
1771 }
1772
1773 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
1774 {
1775 if (fpregs)
1776 {
1777 /* true for "INFO ALL-REGISTERS" command */
1778 sh_do_fp_register (regnum); /* FP regs */
1779 regnum ++;
1780 }
1781 else
e6c42fda 1782 regnum += (gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
53116e27
EZ		 1783 }
1784 else
1785 {
1786 sh_do_register (regnum); /* All other regs */
1787 regnum++;
1788 }
1789 }
1790
1791 if (fpregs)
1792 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1793 {
1794 sh_do_pseudo_register (regnum);
1795 regnum++;
1796 }
1797 }
1798}
1799
1a8629c7
MS		 1800#ifdef SVR4_SHARED_LIBS
1801
1802/* Fetch (and possibly build) an appropriate link_map_offsets structure
1803 for native i386 linux targets using the struct offsets defined in
1804 link.h (but without actual reference to that file).
1805
1806 This makes it possible to access i386-linux shared libraries from
1807 a gdb that was not built on an i386-linux host (for cross debugging).
1808 */
1809
1810struct link_map_offsets *
1811sh_linux_svr4_fetch_link_map_offsets (void)
1812{
1813 static struct link_map_offsets lmo;
1814 static struct link_map_offsets *lmp = 0;
1815
1816 if (lmp == 0)
1817 {
1818 lmp = &lmo;
1819
1820 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
1821
1822 lmo.r_map_offset = 4;
1823 lmo.r_map_size = 4;
1824
1825 lmo.link_map_size = 20; /* 552 not actual size but all we need */
1826
1827 lmo.l_addr_offset = 0;
1828 lmo.l_addr_size = 4;
1829
1830 lmo.l_name_offset = 4;
1831 lmo.l_name_size = 4;
1832
1833 lmo.l_next_offset = 12;
1834 lmo.l_next_size = 4;
1835
1836 lmo.l_prev_offset = 16;
1837 lmo.l_prev_size = 4;
1838 }
1839
1840 return lmp;
1841}
1842#endif /* SVR4_SHARED_LIBS */
1843
cc17453a
EZ		 1844static gdbarch_init_ftype sh_gdbarch_init;
1845
1846static struct gdbarch *
fba45db2 1847sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
cc17453a
EZ		 1848{
1849 static LONGEST sh_call_dummy_words[] = {0};
1850 struct gdbarch *gdbarch;
1851 struct gdbarch_tdep *tdep;
1852 gdbarch_register_name_ftype *sh_register_name;
1853 gdbarch_store_return_value_ftype *sh_store_return_value;
1854 gdbarch_register_virtual_type_ftype *sh_register_virtual_type;
1855
1856 /* Find a candidate among the list of pre-declared architectures. */
1857 arches = gdbarch_list_lookup_by_info (arches, &info);
1858 if (arches != NULL)
1859 return arches->gdbarch;
1860
1861 /* None found, create a new architecture from the information
1862 provided. */
1863 tdep = XMALLOC (struct gdbarch_tdep);
1864 gdbarch = gdbarch_alloc (&info, tdep);
1865
1866 /* Initialize the register numbers that are not common to all the
1867 variants to -1, if necessary thse will be overwritten in the case
1868 statement below. */
1869 tdep->FPUL_REGNUM = -1;
1870 tdep->FPSCR_REGNUM = -1;
c62a7c7b 1871 tdep->SR_REGNUM = 22;
cc17453a 1872 tdep->DSR_REGNUM = -1;
e6c42fda 1873 tdep->FP_LAST_REGNUM = -1;
cc17453a
EZ		 1874 tdep->A0G_REGNUM = -1;
1875 tdep->A0_REGNUM = -1;
1876 tdep->A1G_REGNUM = -1;
1877 tdep->A1_REGNUM = -1;
1878 tdep->M0_REGNUM = -1;
1879 tdep->M1_REGNUM = -1;
1880 tdep->X0_REGNUM = -1;
1881 tdep->X1_REGNUM = -1;
1882 tdep->Y0_REGNUM = -1;
1883 tdep->Y1_REGNUM = -1;
1884 tdep->MOD_REGNUM = -1;
1885 tdep->RS_REGNUM = -1;
1886 tdep->RE_REGNUM = -1;
1887 tdep->SSR_REGNUM = -1;
1888 tdep->SPC_REGNUM = -1;
53116e27 1889 tdep->DR0_REGNUM = -1;
e6c42fda 1890 tdep->DR_LAST_REGNUM = -1;
53116e27 1891 tdep->FV0_REGNUM = -1;
e6c42fda 1892 tdep->FV_LAST_REGNUM = -1;
a38d2a54 1893
cc17453a 1894 set_gdbarch_fp0_regnum (gdbarch, -1);
53116e27
EZ		 1895 set_gdbarch_num_pseudo_regs (gdbarch, 0);
1896 set_gdbarch_max_register_raw_size (gdbarch, 4);
1897 set_gdbarch_max_register_virtual_size (gdbarch, 4);
a38d2a54
EZ		 1898 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1899 set_gdbarch_num_regs (gdbarch, 59);
1900 set_gdbarch_sp_regnum (gdbarch, 15);
1901 set_gdbarch_fp_regnum (gdbarch, 14);
1902 set_gdbarch_pc_regnum (gdbarch, 16);
1903 set_gdbarch_register_size (gdbarch, 4);
1904 set_gdbarch_register_bytes (gdbarch, NUM_REGS * 4);
1905 set_gdbarch_fetch_pseudo_register (gdbarch, sh_fetch_pseudo_register);
1906 set_gdbarch_store_pseudo_register (gdbarch, sh_store_pseudo_register);
c5f7d19c 1907 set_gdbarch_do_registers_info (gdbarch, sh_do_registers_info);
eaf90c5d 1908 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
e6c42fda 1909 print_sh_insn = gdb_print_insn_sh;
cc17453a
EZ		 1910
1911 switch (info.bfd_arch_info->mach)
8db62801 1912 {
cc17453a
EZ		 1913 case bfd_mach_sh:
1914 sh_register_name = sh_sh_register_name;
1915 sh_show_regs = sh_generic_show_regs;
1916 sh_store_return_value = sh_default_store_return_value;
1917 sh_register_virtual_type = sh_default_register_virtual_type;
1918 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1919 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1920 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1921 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1922 break;
1923 case bfd_mach_sh2:
1924 sh_register_name = sh_sh_register_name;
1925 sh_show_regs = sh_generic_show_regs;
1926 sh_store_return_value = sh_default_store_return_value;
1927 sh_register_virtual_type = sh_default_register_virtual_type;
1928 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1929 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1930 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1931 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1932 break;
1933 case bfd_mach_sh_dsp:
1934 sh_register_name = sh_sh_dsp_register_name;
1935 sh_show_regs = sh_dsp_show_regs;
1936 sh_store_return_value = sh_default_store_return_value;
1937 sh_register_virtual_type = sh_default_register_virtual_type;
1938 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1939 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1940 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1941 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1942 tdep->DSR_REGNUM = 24;
1943 tdep->A0G_REGNUM = 25;
1944 tdep->A0_REGNUM = 26;
1945 tdep->A1G_REGNUM = 27;
1946 tdep->A1_REGNUM = 28;
1947 tdep->M0_REGNUM = 29;
1948 tdep->M1_REGNUM = 30;
1949 tdep->X0_REGNUM = 31;
1950 tdep->X1_REGNUM = 32;
1951 tdep->Y0_REGNUM = 33;
1952 tdep->Y1_REGNUM = 34;
1953 tdep->MOD_REGNUM = 40;
1954 tdep->RS_REGNUM = 43;
1955 tdep->RE_REGNUM = 44;
1956 break;
1957 case bfd_mach_sh3:
1958 sh_register_name = sh_sh3_register_name;
1959 sh_show_regs = sh3_show_regs;
1960 sh_store_return_value = sh_default_store_return_value;
1961 sh_register_virtual_type = sh_default_register_virtual_type;
1962 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1963 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1964 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1965 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1966 tdep->SSR_REGNUM = 41;
1967 tdep->SPC_REGNUM = 42;
1968 break;
1969 case bfd_mach_sh3e:
1970 sh_register_name = sh_sh3e_register_name;
1971 sh_show_regs = sh3e_show_regs;
1972 sh_store_return_value = sh3e_sh4_store_return_value;
1973 sh_register_virtual_type = sh_sh3e_register_virtual_type;
1974 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
53116e27
EZ		 1975 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1976 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1977 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1978 set_gdbarch_fp0_regnum (gdbarch, 25);
1979 tdep->FPUL_REGNUM = 23;
1980 tdep->FPSCR_REGNUM = 24;
e6c42fda 1981 tdep->FP_LAST_REGNUM = 40;
cc17453a
EZ		 1982 tdep->SSR_REGNUM = 41;
1983 tdep->SPC_REGNUM = 42;
1984 break;
1985 case bfd_mach_sh3_dsp:
1986 sh_register_name = sh_sh3_dsp_register_name;
1987 sh_show_regs = sh3_dsp_show_regs;
1988 sh_store_return_value = sh_default_store_return_value;
1989 sh_register_virtual_type = sh_default_register_virtual_type;
1990 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1991 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1992 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1993 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1994 tdep->DSR_REGNUM = 24;
1995 tdep->A0G_REGNUM = 25;
1996 tdep->A0_REGNUM = 26;
1997 tdep->A1G_REGNUM = 27;
1998 tdep->A1_REGNUM = 28;
1999 tdep->M0_REGNUM = 29;
2000 tdep->M1_REGNUM = 30;
2001 tdep->X0_REGNUM = 31;
2002 tdep->X1_REGNUM = 32;
2003 tdep->Y0_REGNUM = 33;
2004 tdep->Y1_REGNUM = 34;
2005 tdep->MOD_REGNUM = 40;
2006 tdep->RS_REGNUM = 43;
2007 tdep->RE_REGNUM = 44;
2008 tdep->SSR_REGNUM = 41;
2009 tdep->SPC_REGNUM = 42;
2010 break;
2011 case bfd_mach_sh4:
53116e27
EZ		 2012 sh_register_name = sh_sh4_register_name;
2013 sh_show_regs = sh4_show_regs;
cc17453a 2014 sh_store_return_value = sh3e_sh4_store_return_value;
53116e27 2015 sh_register_virtual_type = sh_sh4_register_virtual_type;
cc17453a
EZ		 2016 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
2017 set_gdbarch_fp0_regnum (gdbarch, 25);
53116e27
EZ		 2018 set_gdbarch_register_raw_size (gdbarch, sh_sh4_register_raw_size);
2019 set_gdbarch_register_virtual_size (gdbarch, sh_sh4_register_raw_size);
2020 set_gdbarch_register_byte (gdbarch, sh_sh4_register_byte);
2021 set_gdbarch_num_pseudo_regs (gdbarch, 12);
2022 set_gdbarch_max_register_raw_size (gdbarch, 4 * 4);
2023 set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4);
fb409745
EZ		 2024 set_gdbarch_register_convert_to_raw (gdbarch, sh_sh4_register_convert_to_raw);
2025 set_gdbarch_register_convert_to_virtual (gdbarch, sh_sh4_register_convert_to_virtual);
2026 set_gdbarch_register_convertible (gdbarch, sh_sh4_register_convertible);
cc17453a
EZ		 2027 tdep->FPUL_REGNUM = 23;
2028 tdep->FPSCR_REGNUM = 24;
e6c42fda 2029 tdep->FP_LAST_REGNUM = 40;
cc17453a
EZ		 2030 tdep->SSR_REGNUM = 41;
2031 tdep->SPC_REGNUM = 42;
53116e27 2032 tdep->DR0_REGNUM = 59;
e6c42fda 2033 tdep->DR_LAST_REGNUM = 66;
53116e27 2034 tdep->FV0_REGNUM = 67;
e6c42fda 2035 tdep->FV_LAST_REGNUM = 70;
cc17453a
EZ		 2036 break;
2037 default:
2038 sh_register_name = sh_generic_register_name;
2039 sh_show_regs = sh_generic_show_regs;
2040 sh_store_return_value = sh_default_store_return_value;
2041 sh_register_virtual_type = sh_default_register_virtual_type;
2042 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 2043 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
2044 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
2045 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a 2046 break;
8db62801 2047 }
cc17453a
EZ		 2048
2049 set_gdbarch_read_pc (gdbarch, generic_target_read_pc);
2050 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2051 set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
2052 set_gdbarch_write_fp (gdbarch, generic_target_write_fp);
2053 set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
2054 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
2055
cc17453a 2056 set_gdbarch_register_name (gdbarch, sh_register_name);
cc17453a
EZ		 2057 set_gdbarch_register_virtual_type (gdbarch, sh_register_virtual_type);
2058
cc17453a
EZ		 2059 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2060 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2061 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2062 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2063 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2064 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
a38d2a54 2065 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);/*??should be 8?*/
cc17453a
EZ		 2066
2067 set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
2068 set_gdbarch_call_dummy_length (gdbarch, 0);
2069 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
2070 set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
2071 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); /*???*/
2072 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
2073 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
2074 set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
2075 set_gdbarch_call_dummy_words (gdbarch, sh_call_dummy_words);
2076 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (sh_call_dummy_words));
2077 set_gdbarch_call_dummy_p (gdbarch, 1);
2078 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
2079 set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
2080 set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
2081 set_gdbarch_coerce_float_to_double (gdbarch,
2082 sh_coerce_float_to_double);
2083
2084 set_gdbarch_extract_return_value (gdbarch, sh_extract_return_value);
2085 set_gdbarch_push_arguments (gdbarch, sh_push_arguments);
2086 set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
2087 set_gdbarch_push_return_address (gdbarch, sh_push_return_address);
2088
2089 set_gdbarch_store_struct_return (gdbarch, sh_store_struct_return);
2090 set_gdbarch_store_return_value (gdbarch, sh_store_return_value);
2091 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
2092 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
2093 set_gdbarch_init_extra_frame_info (gdbarch, sh_init_extra_frame_info);
2094 set_gdbarch_pop_frame (gdbarch, sh_pop_frame);
2095 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2096 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2097 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2098 set_gdbarch_function_start_offset (gdbarch, 0);
cc17453a
EZ		 2099
2100 set_gdbarch_frame_args_skip (gdbarch, 0);
2101 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
2102 set_gdbarch_frame_chain (gdbarch, sh_frame_chain);
2103 set_gdbarch_frame_chain_valid (gdbarch, generic_file_frame_chain_valid);
2104 set_gdbarch_frame_saved_pc (gdbarch, sh_frame_saved_pc);
c347ee3e
MS		 2105 set_gdbarch_frame_args_address (gdbarch, default_frame_address);
2106 set_gdbarch_frame_locals_address (gdbarch, default_frame_address);
cc17453a
EZ		 2107 set_gdbarch_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
2108 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
2109 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2110 set_gdbarch_ieee_float (gdbarch, 1);
a38d2a54 2111 tm_print_insn = print_sh_insn;
cc17453a
EZ		 2112
2113 return gdbarch;
8db62801
EZ		 2114}
2115
c906108c 2116void
fba45db2 2117_initialize_sh_tdep (void)
c906108c
SS		 2118{
2119 struct cmd_list_element *c;
cc17453a
EZ		 2120
2121 register_gdbarch_init (bfd_arch_sh, sh_gdbarch_init);
c906108c 2122
53116e27 2123 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
c906108c 2124}
GDB Binutils - Deliverables
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