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dummy commit, get CVS off the branch.
[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
CommitLineData
c906108c 1/* Target-dependent code for Hitachi Super-H, for GDB.
538a76d6 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3116c80a 3 Free Software Foundation, Inc.
c906108c 4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM		 7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
c906108c 11
c5aa993b
JM		 12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b
JM		 17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
c906108c
SS		 21
22/*
c5aa993b
JM		 23 Contributed by Steve Chamberlain
24 sac@cygnus.com
c906108c
SS		 25 */
26
27#include "defs.h"
28#include "frame.h"
c906108c
SS		 29#include "symtab.h"
30#include "symfile.h"
31#include "gdbtypes.h"
32#include "gdbcmd.h"
33#include "gdbcore.h"
34#include "value.h"
35#include "dis-asm.h"
36#include "inferior.h" /* for BEFORE_TEXT_END etc. */
37#include "gdb_string.h"
b4a20239 38#include "arch-utils.h"
fb409745 39#include "floatformat.h"
4e052eda 40#include "regcache.h"
d16aafd8 41#include "doublest.h"
c906108c 42
ab3b8126
JT		 43#include "sh-tdep.h"
44
d658f924 45#include "elf-bfd.h"
1a8629c7
MS		 46#include "solib-svr4.h"
47
283150cd
EZ		 48/* sh64 flags */
49#include "elf/sh.h"
50/* registers numbers shared with the simulator */
1c922164 51#include "gdb/sim-sh.h"
283150cd 52
53116e27 53void (*sh_show_regs) (void);
3bbfbb92
EZ		 54CORE_ADDR (*skip_prologue_hard_way) (CORE_ADDR);
55void (*do_pseudo_register) (int);
cc17453a 56
88e04cc1
EZ		 57#define SH_DEFAULT_NUM_REGS 59
58
cc17453a
EZ		 59/* Define other aspects of the stack frame.
60 we keep a copy of the worked out return pc lying around, since it
61 is a useful bit of info */
62
63struct frame_extra_info
64{
65 CORE_ADDR return_pc;
66 int leaf_function;
67 int f_offset;
63978407 68};
c906108c 69
fa88f677 70static const char *
cc17453a 71sh_generic_register_name (int reg_nr)
c5aa993b 72{
cc17453a 73 static char *register_names[] =
c5aa993b 74 {
cc17453a
EZ		 75 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
76 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
77 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
78 "fpul", "fpscr",
79 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
80 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
81 "ssr", "spc",
82 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
83 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
84 };
85 if (reg_nr < 0)
86 return NULL;
87 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
88 return NULL;
89 return register_names[reg_nr];
90}
91
fa88f677 92static const char *
cc17453a
EZ		 93sh_sh_register_name (int reg_nr)
94{
95 static char *register_names[] =
63978407 96 {
cc17453a
EZ		 97 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
98 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
99 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
100 "", "",
101 "", "", "", "", "", "", "", "",
102 "", "", "", "", "", "", "", "",
103 "", "",
104 "", "", "", "", "", "", "", "",
105 "", "", "", "", "", "", "", "",
106 };
107 if (reg_nr < 0)
108 return NULL;
109 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
110 return NULL;
111 return register_names[reg_nr];
112}
113
fa88f677 114static const char *
cc17453a
EZ		 115sh_sh3_register_name (int reg_nr)
116{
117 static char *register_names[] =
c5aa993b 118 {
cc17453a
EZ		 119 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
120 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
121 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
122 "", "",
123 "", "", "", "", "", "", "", "",
124 "", "", "", "", "", "", "", "",
125 "ssr", "spc",
126 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
127 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
128 };
129 if (reg_nr < 0)
130 return NULL;
131 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
132 return NULL;
133 return register_names[reg_nr];
134}
135
fa88f677 136static const char *
cc17453a
EZ		 137sh_sh3e_register_name (int reg_nr)
138{
139 static char *register_names[] =
63978407 140 {
cc17453a
EZ		 141 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
142 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
143 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
144 "fpul", "fpscr",
145 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
146 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
147 "ssr", "spc",
148 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
149 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
150 };
151 if (reg_nr < 0)
152 return NULL;
153 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
154 return NULL;
155 return register_names[reg_nr];
156}
157
fa88f677 158static const char *
cc17453a
EZ		 159sh_sh_dsp_register_name (int reg_nr)
160{
161 static char *register_names[] =
c5aa993b 162 {
cc17453a
EZ		 163 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
164 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
165 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
166 "", "dsr",
167 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
168 "y0", "y1", "", "", "", "", "", "mod",
169 "", "",
170 "rs", "re", "", "", "", "", "", "",
171 "", "", "", "", "", "", "", "",
172 };
173 if (reg_nr < 0)
174 return NULL;
175 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
176 return NULL;
177 return register_names[reg_nr];
178}
179
fa88f677 180static const char *
cc17453a
EZ		 181sh_sh3_dsp_register_name (int reg_nr)
182{
183 static char *register_names[] =
c5aa993b 184 {
cc17453a
EZ		 185 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
186 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
187 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
188 "", "dsr",
189 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
190 "y0", "y1", "", "", "", "", "", "mod",
191 "ssr", "spc",
192 "rs", "re", "", "", "", "", "", "",
193 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
194 "", "", "", "", "", "", "", "",
195 };
196 if (reg_nr < 0)
197 return NULL;
198 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
199 return NULL;
200 return register_names[reg_nr];
201}
202
fa88f677 203static const char *
53116e27
EZ		 204sh_sh4_register_name (int reg_nr)
205{
206 static char *register_names[] =
207 {
a38d2a54 208 /* general registers 0-15 */
53116e27
EZ		 209 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
210 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
a38d2a54 211 /* 16 - 22 */
53116e27 212 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
a38d2a54 213 /* 23, 24 */
53116e27 214 "fpul", "fpscr",
a38d2a54 215 /* floating point registers 25 - 40 */
53116e27
EZ		 216 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
217 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
a38d2a54 218 /* 41, 42 */
53116e27 219 "ssr", "spc",
a38d2a54 220 /* bank 0 43 - 50 */
53116e27 221 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
a38d2a54 222 /* bank 1 51 - 58 */
53116e27 223 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
a38d2a54 224 /* double precision (pseudo) 59 - 66 */
fe9f384f 225 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
a38d2a54 226 /* vectors (pseudo) 67 - 70 */
fe9f384f 227 "fv0", "fv4", "fv8", "fv12",
a38d2a54
EZ		 228 /* FIXME: missing XF 71 - 86 */
229 /* FIXME: missing XD 87 - 94 */
53116e27
EZ		 230 };
231 if (reg_nr < 0)
232 return NULL;
233 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
234 return NULL;
235 return register_names[reg_nr];
236}
237
fa88f677 238static const char *
283150cd
EZ		 239sh_sh64_register_name (int reg_nr)
240{
241 static char *register_names[] =
242 {
243 /* SH MEDIA MODE (ISA 32) */
244 /* general registers (64-bit) 0-63 */
245 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
246 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
247 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
248 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
249 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
250 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
251 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
252 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
253
254 /* pc (64-bit) 64 */
255 "pc",
256
257 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
258 "sr", "ssr", "spc",
259
260 /* target registers (64-bit) 68-75*/
261 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
262
263 /* floating point state control register (32-bit) 76 */
264 "fpscr",
265
266 /* single precision floating point registers (32-bit) 77-140*/
267 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
268 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
269 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
270 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
271 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
272 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
273 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
274 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
275
276 /* double precision registers (pseudo) 141-172 */
277 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
278 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
279 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
280 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
281
282 /* floating point pairs (pseudo) 173-204*/
283 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
284 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
285 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
286 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
287
288 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
289 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
290 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
291
292 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
293 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
294 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
295 "pc_c",
296 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
297 "fpscr_c", "fpul_c",
298 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
299 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
300 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
301 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
302 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
303 };
304
305 if (reg_nr < 0)
306 return NULL;
307 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
308 return NULL;
309 return register_names[reg_nr];
310}
311
312#define NUM_PSEUDO_REGS_SH_MEDIA 80
313#define NUM_PSEUDO_REGS_SH_COMPACT 51
314
3117ed25 315static const unsigned char *
fba45db2 316sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
cc17453a
EZ		 317{
318 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
319 static unsigned char breakpoint[] = {0xc3, 0xc3};
320
321 *lenptr = sizeof (breakpoint);
322 return breakpoint;
323}
c906108c 324
283150cd
EZ		 325/* Macros and functions for setting and testing a bit in a minimal
326 symbol that marks it as 32-bit function. The MSB of the minimal
327 symbol's "info" field is used for this purpose. This field is
328 already being used to store the symbol size, so the assumption is
329 that the symbol size cannot exceed 2^31.
330
331 ELF_MAKE_MSYMBOL_SPECIAL
332 tests whether an ELF symbol is "special", i.e. refers
333 to a 32-bit function, and sets a "special" bit in a
334 minimal symbol to mark it as a 32-bit function
335 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
336 MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
337 the "info" field with the "special" bit masked out */
338
339#define MSYMBOL_IS_SPECIAL(msym) \
340 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
341
342void
343sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
344{
345 if (msym == NULL)
346 return;
347
348 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
349 {
350 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000);
351 SYMBOL_VALUE_ADDRESS (msym) |= 1;
352 }
353}
354
355/* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
356 are some macros to test, set, or clear bit 0 of addresses. */
357#define IS_ISA32_ADDR(addr) ((addr) & 1)
358#define MAKE_ISA32_ADDR(addr) ((addr) | 1)
359#define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
360
361static int
362pc_is_isa32 (bfd_vma memaddr)
363{
364 struct minimal_symbol *sym;
365
366 /* If bit 0 of the address is set, assume this is a
367 ISA32 (shmedia) address. */
368 if (IS_ISA32_ADDR (memaddr))
369 return 1;
370
371 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
372 the high bit of the info field. Use this to decide if the function is
373 ISA16 or ISA32. */
374 sym = lookup_minimal_symbol_by_pc (memaddr);
375 if (sym)
376 return MSYMBOL_IS_SPECIAL (sym);
377 else
378 return 0;
379}
380
381static const unsigned char *
382sh_sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
383{
384 /* The BRK instruction for shmedia is
385 01101111 11110101 11111111 11110000
386 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
387 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
388
389 /* The BRK instruction for shcompact is
390 00000000 00111011
391 which translates in big endian mode to 0x0, 0x3b
392 and in little endian mode to 0x3b, 0x0*/
393
394 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
395 {
396 if (pc_is_isa32 (*pcptr))
397 {
398 static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0};
399 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
400 *lenptr = sizeof (big_breakpoint_media);
401 return big_breakpoint_media;
402 }
403 else
404 {
405 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
406 *lenptr = sizeof (big_breakpoint_compact);
407 return big_breakpoint_compact;
408 }
409 }
410 else
411 {
412 if (pc_is_isa32 (*pcptr))
413 {
414 static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f};
415 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
416 *lenptr = sizeof (little_breakpoint_media);
417 return little_breakpoint_media;
418 }
419 else
420 {
421 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
422 *lenptr = sizeof (little_breakpoint_compact);
423 return little_breakpoint_compact;
424 }
425 }
426}
427
c906108c 428/* Prologue looks like
c5aa993b
JM		 429 [mov.l <regs>,@-r15]...
430 [sts.l pr,@-r15]
431 [mov.l r14,@-r15]
432 [mov r15,r14]
8db62801
EZ		 433
434 Actually it can be more complicated than this. For instance, with
435 newer gcc's:
436
437 mov.l r14,@-r15
438 add #-12,r15
439 mov r15,r14
440 mov r4,r1
441 mov r5,r2
442 mov.l r6,@(4,r14)
443 mov.l r7,@(8,r14)
444 mov.b r1,@r14
445 mov r14,r1
446 mov r14,r1
447 add #2,r1
448 mov.w r2,@r1
449
c5aa993b 450 */
c906108c 451
283150cd
EZ		 452/* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
453 with l=1 and n = 18 0110101111110001010010100aaa0000 */
454#define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
455
456/* STS.L PR,@-r0 0100000000100010
457 r0-4-->r0, PR-->(r0) */
458#define IS_STS_R0(x) ((x) == 0x4022)
459
460/* STS PR, Rm 0000mmmm00101010
461 PR-->Rm */
462#define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
463
464/* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
465 Rm-->(dispx4+r15) */
466#define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
467
468/* MOV.L R14,@(disp,r15) 000111111110dddd
469 R14-->(dispx4+r15) */
470#define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
471
472/* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
473 R18-->(dispx8+R14) */
474#define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
475
476/* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
477 R18-->(dispx8+R15) */
478#define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
479
480/* ST.L R15, disp, R18 101010001111dddddddddd0100100000
481 R18-->(dispx4+R15) */
482#define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
483
484/* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
485 R14-->(dispx8+R15) */
486#define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
487
488/* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
489 R14-->(dispx4+R15) */
490#define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
491
492/* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
493 R15 + imm --> R15 */
494#define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
495
496/* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
497 R15 + imm --> R15 */
498#define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
499
500/* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
501 R15 + R63 --> R14 */
502#define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
503
504/* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
505 R15 + R63 --> R14 */
506#define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
507
508#define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
509
510/* MOV #imm, R0 1110 0000 ssss ssss
511 #imm-->R0 */
512#define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
513
514/* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
515#define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
516
517/* ADD r15,r0 0011 0000 1111 1100
518 r15+r0-->r0 */
519#define IS_ADD_SP_R0(x) ((x) == 0x30fc)
520
521/* MOV.L R14 @-R0 0010 0000 1110 0110
522 R14-->(R0-4), R0-4-->R0 */
523#define IS_MOV_R14_R0(x) ((x) == 0x20e6)
524
525/* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
526 where Rm is one of r2-r9 which are the argument registers. */
527/* FIXME: Recognize the float and double register moves too! */
528#define IS_MEDIA_IND_ARG_MOV(x) \
529((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
530
531/* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
532 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
533 where Rm is one of r2-r9 which are the argument registers. */
534#define IS_MEDIA_ARG_MOV(x) \
535(((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
536 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
537
538/* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
539/* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
540/* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
541/* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
542/* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
543#define IS_MEDIA_MOV_TO_R14(x) \
544((((x) & 0xfffffc0f) == 0xa0e00000) \
545|| (((x) & 0xfffffc0f) == 0xa4e00000) \
546|| (((x) & 0xfffffc0f) == 0xa8e00000) \
547|| (((x) & 0xfffffc0f) == 0xb4e00000) \
548|| (((x) & 0xfffffc0f) == 0xbce00000))
549
550/* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
551 where Rm is r2-r9 */
552#define IS_COMPACT_IND_ARG_MOV(x) \
553((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
554
555/* compact direct arg move!
556 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
557#define IS_COMPACT_ARG_MOV(x) \
558(((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
559
560/* MOV.B Rm, @R14 0010 1110 mmmm 0000
561 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
562#define IS_COMPACT_MOV_TO_R14(x) \
563((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
564
565#define IS_JSR_R0(x) ((x) == 0x400b)
566#define IS_NOP(x) ((x) == 0x0009)
567
568
8db62801
EZ		 569/* STS.L PR,@-r15 0100111100100010
570 r15-4-->r15, PR-->(r15) */
c906108c 571#define IS_STS(x) ((x) == 0x4f22)
8db62801
EZ		 572
573/* MOV.L Rm,@-r15 00101111mmmm0110
574 r15-4-->r15, Rm-->(R15) */
c906108c 575#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 576
c906108c 577#define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
8db62801
EZ		 578
579/* MOV r15,r14 0110111011110011
580 r15-->r14 */
c906108c 581#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ		 582
583/* ADD #imm,r15 01111111iiiiiiii
584 r15+imm-->r15 */
c906108c 585#define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 586
c906108c
SS		 587#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
588#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ		 589
590/* ADD r3,r15 0011111100111100
591 r15+r3-->r15 */
c906108c 592#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ		 593
594/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
8db62801 595 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
8db62801 596 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
c906108c 597#define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
c906108c 598
8db62801 599/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
8db62801 600 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
8db62801
EZ		 601 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
602 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
603#define IS_ARG_MOV(x) \
604(((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
cc17453a
EZ		 605 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
606 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
8db62801
EZ		 607
608/* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
609 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
3bbfbb92 610#define IS_MOV_TO_R14(x) \
cc17453a 611 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
8db62801
EZ		 612
613#define FPSCR_SZ (1 << 20)
c906108c 614
c906108c
SS		 615/* Skip any prologue before the guts of a function */
616
8db62801
EZ		 617/* Skip the prologue using the debug information. If this fails we'll
618 fall back on the 'guess' method below. */
619static CORE_ADDR
fba45db2 620after_prologue (CORE_ADDR pc)
8db62801
EZ		 621{
622 struct symtab_and_line sal;
623 CORE_ADDR func_addr, func_end;
624
625 /* If we can not find the symbol in the partial symbol table, then
626 there is no hope we can determine the function's start address
627 with this code. */
628 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
629 return 0;
630
631 /* Get the line associated with FUNC_ADDR. */
632 sal = find_pc_line (func_addr, 0);
633
634 /* There are only two cases to consider. First, the end of the source line
635 is within the function bounds. In that case we return the end of the
636 source line. Second is the end of the source line extends beyond the
637 bounds of the current function. We need to use the slow code to
638 examine instructions in that case. */
639 if (sal.end < func_end)
640 return sal.end;
641 else
642 return 0;
643}
644
645/* Here we look at each instruction in the function, and try to guess
646 where the prologue ends. Unfortunately this is not always
647 accurate. */
648static CORE_ADDR
3bbfbb92 649sh_skip_prologue_hard_way (CORE_ADDR start_pc)
c906108c 650{
2bfa91ee 651 CORE_ADDR here, end;
8db62801 652 int updated_fp = 0;
2bfa91ee
EZ		 653
654 if (!start_pc)
655 return 0;
656
657 for (here = start_pc, end = start_pc + (2 * 28); here < end;)
c906108c 658 {
2bfa91ee
EZ		 659 int w = read_memory_integer (here, 2);
660 here += 2;
661 if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w)
8db62801 662 || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w)
3bbfbb92 663 || IS_ARG_MOV (w) || IS_MOV_TO_R14 (w))
2bfa91ee
EZ		 664 {
665 start_pc = here;
2bfa91ee 666 }
8db62801
EZ		 667 else if (IS_MOV_SP_FP (w))
668 {
669 start_pc = here;
670 updated_fp = 1;
671 }
672 else
673 /* Don't bail out yet, if we are before the copy of sp. */
674 if (updated_fp)
675 break;
c906108c
SS		 676 }
677
678 return start_pc;
679}
680
283150cd
EZ		 681static CORE_ADDR
682look_for_args_moves (CORE_ADDR start_pc, int media_mode)
683{
684 CORE_ADDR here, end;
685 int w;
686 int insn_size = (media_mode ? 4 : 2);
687
688 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
689 {
690 if (media_mode)
691 {
692 w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
693 here += insn_size;
694 if (IS_MEDIA_IND_ARG_MOV (w))
695 {
696 /* This must be followed by a store to r14, so the argument
697 is where the debug info says it is. This can happen after
698 the SP has been saved, unfortunately. */
699
700 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
701 insn_size);
702 here += insn_size;
703 if (IS_MEDIA_MOV_TO_R14 (next_insn))
704 start_pc = here;
705 }
706 else if (IS_MEDIA_ARG_MOV (w))
707 {
708 /* These instructions store directly the argument in r14. */
709 start_pc = here;
710 }
711 else
712 break;
713 }
714 else
715 {
716 w = read_memory_integer (here, insn_size);
717 w = w & 0xffff;
718 here += insn_size;
719 if (IS_COMPACT_IND_ARG_MOV (w))
720 {
721 /* This must be followed by a store to r14, so the argument
722 is where the debug info says it is. This can happen after
723 the SP has been saved, unfortunately. */
724
725 int next_insn = 0xffff & read_memory_integer (here, insn_size);
726 here += insn_size;
727 if (IS_COMPACT_MOV_TO_R14 (next_insn))
728 start_pc = here;
729 }
730 else if (IS_COMPACT_ARG_MOV (w))
731 {
732 /* These instructions store directly the argument in r14. */
733 start_pc = here;
734 }
735 else if (IS_MOVL_R0 (w))
736 {
737 /* There is a function that gcc calls to get the arguments
738 passed correctly to the function. Only after this
739 function call the arguments will be found at the place
740 where they are supposed to be. This happens in case the
741 argument has to be stored into a 64-bit register (for
742 instance doubles, long longs). SHcompact doesn't have
743 access to the full 64-bits, so we store the register in
744 stack slot and store the address of the stack slot in
745 the register, then do a call through a wrapper that
746 loads the memory value into the register. A SHcompact
747 callee calls an argument decoder
748 (GCC_shcompact_incoming_args) that stores the 64-bit
749 value in a stack slot and stores the address of the
750 stack slot in the register. GCC thinks the argument is
751 just passed by transparent reference, but this is only
752 true after the argument decoder is called. Such a call
753 needs to be considered part of the prologue. */
754
755 /* This must be followed by a JSR @r0 instruction and by
756 a NOP instruction. After these, the prologue is over! */
757
758 int next_insn = 0xffff & read_memory_integer (here, insn_size);
759 here += insn_size;
760 if (IS_JSR_R0 (next_insn))
761 {
762 next_insn = 0xffff & read_memory_integer (here, insn_size);
763 here += insn_size;
764
765 if (IS_NOP (next_insn))
766 start_pc = here;
767 }
768 }
769 else
770 break;
771 }
772 }
773
774 return start_pc;
775}
776
777static CORE_ADDR
778sh64_skip_prologue_hard_way (CORE_ADDR start_pc)
779{
780 CORE_ADDR here, end;
781 int updated_fp = 0;
782 int insn_size = 4;
783 int media_mode = 1;
784
785 if (!start_pc)
786 return 0;
787
788 if (pc_is_isa32 (start_pc) == 0)
789 {
790 insn_size = 2;
791 media_mode = 0;
792 }
793
794 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
795 {
796
797 if (media_mode)
798 {
799 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
800 here += insn_size;
801 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
802 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
803 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w))
804 {
805 start_pc = here;
806 }
807 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
808 {
809 start_pc = here;
810 updated_fp = 1;
811 }
812 else
813 if (updated_fp)
814 {
815 /* Don't bail out yet, we may have arguments stored in
816 registers here, according to the debug info, so that
817 gdb can print the frames correctly. */
818 start_pc = look_for_args_moves (here - insn_size, media_mode);
819 break;
820 }
821 }
822 else
823 {
824 int w = 0xffff & read_memory_integer (here, insn_size);
825 here += insn_size;
826
827 if (IS_STS_R0 (w) || IS_STS_PR (w)
828 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
829 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
830 {
831 start_pc = here;
832 }
833 else if (IS_MOV_SP_FP (w))
834 {
835 start_pc = here;
836 updated_fp = 1;
837 }
838 else
839 if (updated_fp)
840 {
841 /* Don't bail out yet, we may have arguments stored in
842 registers here, according to the debug info, so that
843 gdb can print the frames correctly. */
844 start_pc = look_for_args_moves (here - insn_size, media_mode);
845 break;
846 }
847 }
848 }
849
850 return start_pc;
851}
852
cc17453a 853static CORE_ADDR
fba45db2 854sh_skip_prologue (CORE_ADDR pc)
8db62801
EZ		 855{
856 CORE_ADDR post_prologue_pc;
857
858 /* See if we can determine the end of the prologue via the symbol table.
859 If so, then return either PC, or the PC after the prologue, whichever
860 is greater. */
8db62801
EZ		 861 post_prologue_pc = after_prologue (pc);
862
863 /* If after_prologue returned a useful address, then use it. Else
864 fall back on the instruction skipping code. */
865 if (post_prologue_pc != 0)
866 return max (pc, post_prologue_pc);
867 else
868 return (skip_prologue_hard_way (pc));
869}
870
cc17453a
EZ		 871/* Immediately after a function call, return the saved pc.
872 Can't always go through the frames for this because on some machines
873 the new frame is not set up until the new function executes
874 some instructions.
875
876 The return address is the value saved in the PR register + 4 */
877static CORE_ADDR
fba45db2 878sh_saved_pc_after_call (struct frame_info *frame)
cc17453a 879{
3bbfbb92 880 return (ADDR_BITS_REMOVE (read_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM)));
cc17453a
EZ		 881}
882
883/* Should call_function allocate stack space for a struct return? */
884static int
fba45db2 885sh_use_struct_convention (int gcc_p, struct type *type)
cc17453a
EZ		 886{
887 return (TYPE_LENGTH (type) > 1);
888}
889
283150cd
EZ		 890static int
891sh64_use_struct_convention (int gcc_p, struct type *type)
892{
893 return (TYPE_LENGTH (type) > 8);
894}
895
cc17453a
EZ		 896/* Store the address of the place in which to copy the structure the
897 subroutine will return. This is called from call_function.
898
3bbfbb92 899 We store structs through a pointer passed in R2 */
cc17453a 900static void
fba45db2 901sh_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
cc17453a
EZ		 902{
903 write_register (STRUCT_RETURN_REGNUM, (addr));
904}
c906108c 905
cc17453a
EZ		 906/* Disassemble an instruction. */
907static int
fba45db2 908gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
c906108c 909{
1c509ca8
JR		 910 info->endian = TARGET_BYTE_ORDER;
911 return print_insn_sh (memaddr, info);
283150cd
EZ		 912}
913
c906108c
SS		 914/* Given a GDB frame, determine the address of the calling function's frame.
915 This will be used to create a new GDB frame struct, and then
916 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
917
918 For us, the frame address is its stack pointer value, so we look up
919 the function prologue to determine the caller's sp value, and return it. */
cc17453a 920static CORE_ADDR
fba45db2 921sh_frame_chain (struct frame_info *frame)
c906108c
SS		 922{
923 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
924 return frame->frame; /* dummy frame same as caller's frame */
2bfa91ee 925 if (frame->pc && !inside_entry_file (frame->pc))
cc17453a 926 return read_memory_integer (FRAME_FP (frame) + frame->extra_info->f_offset, 4);
c906108c
SS		 927 else
928 return 0;
929}
930
283150cd
EZ		 931/* Given a register number RN as it appears in an assembly
932 instruction, find the corresponding register number in the GDB
933 scheme. */
934static int
935translate_insn_rn (int rn, int media_mode)
936{
937 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
938
939 /* FIXME: this assumes that the number rn is for a not pseudo
940 register only. */
941 if (media_mode)
942 return rn;
943 else
944 {
945 /* These registers don't have a corresponding compact one. */
946 /* FIXME: This is probably not enough. */
947#if 0
948 if ((rn >= 16 && rn <= 63) || (rn >= 93 && rn <= 140))
949 return rn;
950#endif
951 if (rn >= 0 && rn <= tdep->R0_C_REGNUM)
952 return tdep->R0_C_REGNUM + rn;
953 else
954 return rn;
955 }
956}
957
958static CORE_ADDR
959sh64_frame_chain (struct frame_info *frame)
960{
961 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
962 return frame->frame; /* dummy frame same as caller's frame */
963 if (frame->pc && !inside_entry_file (frame->pc))
964 {
965 int media_mode = pc_is_isa32 (frame->pc);
966 int size;
967 if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
968 size = 4;
969 else
970 size = REGISTER_RAW_SIZE (translate_insn_rn (FP_REGNUM, media_mode));
971 return read_memory_integer (FRAME_FP (frame) + frame->extra_info->f_offset, size);
972 }
973 else
974 return 0;
975}
976
c906108c
SS		 977/* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
978 we might want to do here is to check REGNUM against the clobber mask, and
979 somehow flag it as invalid if it isn't saved on the stack somewhere. This
980 would provide a graceful failure mode when trying to get the value of
981 caller-saves registers for an inner frame. */
cc17453a 982static CORE_ADDR
fba45db2 983sh_find_callers_reg (struct frame_info *fi, int regnum)
c906108c 984{
c906108c
SS		 985 for (; fi; fi = fi->next)
986 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
987 /* When the caller requests PR from the dummy frame, we return PC because
c5aa993b 988 that's where the previous routine appears to have done a call from. */
c906108c 989 return generic_read_register_dummy (fi->pc, fi->frame, regnum);
c5aa993b 990 else
c906108c 991 {
cc17453a 992 FRAME_INIT_SAVED_REGS (fi);
2bfa91ee
EZ		 993 if (!fi->pc)
994 return 0;
cc17453a
EZ		 995 if (fi->saved_regs[regnum] != 0)
996 return read_memory_integer (fi->saved_regs[regnum],
c5aa993b 997 REGISTER_RAW_SIZE (regnum));
c906108c
SS		 998 }
999 return read_register (regnum);
1000}
1001
283150cd
EZ		 1002static CORE_ADDR
1003sh64_get_saved_pr (struct frame_info *fi, int pr_regnum)
1004{
1005 int media_mode = 0;
1006
1007 for (; fi; fi = fi->next)
1008 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
1009 /* When the caller requests PR from the dummy frame, we return PC because
1010 that's where the previous routine appears to have done a call from. */
1011 return generic_read_register_dummy (fi->pc, fi->frame, pr_regnum);
1012 else
1013 {
1014 FRAME_INIT_SAVED_REGS (fi);
1015 if (!fi->pc)
1016 return 0;
1017
1018 media_mode = pc_is_isa32 (fi->pc);
1019
1020 if (fi->saved_regs[pr_regnum] != 0)
1021 {
1022 int gdb_reg_num = translate_insn_rn (pr_regnum, media_mode);
1023 int size = ((gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
1024 ? 4
1025 : REGISTER_RAW_SIZE (gdb_reg_num));
1026 return read_memory_integer (fi->saved_regs[pr_regnum], size);
1027 }
1028 }
1029 return read_register (pr_regnum);
1030}
1031
c906108c
SS		 1032/* Put here the code to store, into a struct frame_saved_regs, the
1033 addresses of the saved registers of frame described by FRAME_INFO.
1034 This includes special registers such as pc and fp saved in special
1035 ways in the stack frame. sp is even more special: the address we
1036 return for it IS the sp for the next frame. */
cc17453a 1037static void
fba45db2 1038sh_nofp_frame_init_saved_regs (struct frame_info *fi)
c906108c 1039{
e7d717c0 1040 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof(int));
c906108c
SS		 1041 int rn;
1042 int have_fp = 0;
1043 int depth;
1044 int pc;
1045 int opc;
1046 int insn;
1047 int r3_val = 0;
da130f98 1048 char *dummy_regs = deprecated_generic_find_dummy_frame (fi->pc, fi->frame);
cc17453a
EZ		 1049
1050 if (fi->saved_regs == NULL)
1051 frame_saved_regs_zalloc (fi);
1052 else
1053 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
1054
1055 if (dummy_regs)
1056 {
1057 /* DANGER! This is ONLY going to work if the char buffer format of
1058 the saved registers is byte-for-byte identical to the
1059 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1060 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
1061 return;
1062 }
1063
1064 fi->extra_info->leaf_function = 1;
1065 fi->extra_info->f_offset = 0;
1066
cd4bffcf 1067 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
cc17453a
EZ		 1068 where[rn] = -1;
1069
1070 depth = 0;
1071
1072 /* Loop around examining the prologue insns until we find something
1073 that does not appear to be part of the prologue. But give up
1074 after 20 of them, since we're getting silly then. */
1075
1076 pc = get_pc_function_start (fi->pc);
1077 if (!pc)
1078 {
1079 fi->pc = 0;
1080 return;
1081 }
1082
1083 for (opc = pc + (2 * 28); pc < opc; pc += 2)
1084 {
1085 insn = read_memory_integer (pc, 2);
1086 /* See where the registers will be saved to */
1087 if (IS_PUSH (insn))
1088 {
1089 rn = GET_PUSHED_REG (insn);
1090 where[rn] = depth;
1091 depth += 4;
1092 }
1093 else if (IS_STS (insn))
1094 {
3bbfbb92 1095 where[gdbarch_tdep (current_gdbarch)->PR_REGNUM] = depth;
cc17453a
EZ		 1096 /* If we're storing the pr then this isn't a leaf */
1097 fi->extra_info->leaf_function = 0;
1098 depth += 4;
1099 }
1100 else if (IS_MOV_R3 (insn))
1101 {
1102 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
1103 }
1104 else if (IS_SHLL_R3 (insn))
1105 {
1106 r3_val <<= 1;
1107 }
1108 else if (IS_ADD_R3SP (insn))
1109 {
1110 depth += -r3_val;
1111 }
1112 else if (IS_ADD_SP (insn))
1113 {
1114 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1115 }
1116 else if (IS_MOV_SP_FP (insn))
1117 break;
1118#if 0 /* This used to just stop when it found an instruction that
1119 was not considered part of the prologue. Now, we just
1120 keep going looking for likely instructions. */
1121 else
1122 break;
1123#endif
1124 }
1125
1126 /* Now we know how deep things are, we can work out their addresses */
1127
cd4bffcf 1128 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
cc17453a
EZ		 1129 {
1130 if (where[rn] >= 0)
1131 {
1132 if (rn == FP_REGNUM)
1133 have_fp = 1;
c906108c 1134
cc17453a
EZ		 1135 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
1136 }
1137 else
1138 {
1139 fi->saved_regs[rn] = 0;
1140 }
1141 }
1142
1143 if (have_fp)
1144 {
1145 fi->saved_regs[SP_REGNUM] = read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
1146 }
1147 else
1148 {
1149 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
1150 }
1151
1152 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
1153 /* Work out the return pc - either from the saved pr or the pr
1154 value */
1155}
1156
3bbfbb92
EZ		 1157/* For vectors of 4 floating point registers. */
1158static int
1159fv_reg_base_num (int fv_regnum)
1160{
1161 int fp_regnum;
1162
1163 fp_regnum = FP0_REGNUM +
1164 (fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM) * 4;
1165 return fp_regnum;
1166}
1167
1168/* For double precision floating point registers, i.e 2 fp regs.*/
1169static int
1170dr_reg_base_num (int dr_regnum)
1171{
1172 int fp_regnum;
1173
1174 fp_regnum = FP0_REGNUM +
1175 (dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM) * 2;
1176 return fp_regnum;
1177}
1178
283150cd
EZ		 1179/* For pairs of floating point registers */
1180static int
1181fpp_reg_base_num (int fpp_regnum)
1182{
1183 int fp_regnum;
1184
1185 fp_regnum = FP0_REGNUM +
1186 (fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM) * 2;
1187 return fp_regnum;
1188}
1189
1190static int
1191is_media_pseudo (int rn)
1192{
1193 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1194
1195 return (rn >= tdep->DR0_REGNUM
1196 && rn <= tdep->FV_LAST_REGNUM);
1197}
1198
1199int
1200sh64_get_gdb_regnum (int gcc_regnum, CORE_ADDR pc)
1201{
1202 return translate_insn_rn (gcc_regnum, pc_is_isa32 (pc));
1203}
1204
1205static int
1206sh64_media_reg_base_num (int reg_nr)
1207{
1208 int base_regnum = -1;
1209 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1210
1211 if (reg_nr >= tdep->DR0_REGNUM
1212 && reg_nr <= tdep->DR_LAST_REGNUM)
1213 base_regnum = dr_reg_base_num (reg_nr);
1214
1215 else if (reg_nr >= tdep->FPP0_REGNUM
1216 && reg_nr <= tdep->FPP_LAST_REGNUM)
1217 base_regnum = fpp_reg_base_num (reg_nr);
1218
1219 else if (reg_nr >= tdep->FV0_REGNUM
1220 && reg_nr <= tdep->FV_LAST_REGNUM)
1221 base_regnum = fv_reg_base_num (reg_nr);
1222
1223 return base_regnum;
1224}
1225
1226/* *INDENT-OFF* */
1227/*
1228 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1229 GDB_REGNUM BASE_REGNUM
1230 r0_c 221 0
1231 r1_c 222 1
1232 r2_c 223 2
1233 r3_c 224 3
1234 r4_c 225 4
1235 r5_c 226 5
1236 r6_c 227 6
1237 r7_c 228 7
1238 r8_c 229 8
1239 r9_c 230 9
1240 r10_c 231 10
1241 r11_c 232 11
1242 r12_c 233 12
1243 r13_c 234 13
1244 r14_c 235 14
1245 r15_c 236 15
1246
1247 pc_c 237 64
1248 gbr_c 238 16
1249 mach_c 239 17
1250 macl_c 240 17
1251 pr_c 241 18
1252 t_c 242 19
1253 fpscr_c 243 76
1254 fpul_c 244 109
1255
1256 fr0_c 245 77
1257 fr1_c 246 78
1258 fr2_c 247 79
1259 fr3_c 248 80
1260 fr4_c 249 81
1261 fr5_c 250 82
1262 fr6_c 251 83
1263 fr7_c 252 84
1264 fr8_c 253 85
1265 fr9_c 254 86
1266 fr10_c 255 87
1267 fr11_c 256 88
1268 fr12_c 257 89
1269 fr13_c 258 90
1270 fr14_c 259 91
1271 fr15_c 260 92
1272
1273 dr0_c 261 77
1274 dr2_c 262 79
1275 dr4_c 263 81
1276 dr6_c 264 83
1277 dr8_c 265 85
1278 dr10_c 266 87
1279 dr12_c 267 89
1280 dr14_c 268 91
1281
1282 fv0_c 269 77
1283 fv4_c 270 81
1284 fv8_c 271 85
1285 fv12_c 272 91
1286*/
1287/* *INDENT-ON* */
1288static int
1289sh64_compact_reg_base_num (int reg_nr)
1290{
1291 int base_regnum = -1;
1292 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1293
1294 /* general register N maps to general register N */
1295 if (reg_nr >= tdep->R0_C_REGNUM
1296 && reg_nr <= tdep->R_LAST_C_REGNUM)
1297 base_regnum = reg_nr - tdep->R0_C_REGNUM;
1298
1299 /* floating point register N maps to floating point register N */
1300 else if (reg_nr >= tdep->FP0_C_REGNUM
1301 && reg_nr <= tdep->FP_LAST_C_REGNUM)
1302 base_regnum = reg_nr - tdep->FP0_C_REGNUM + FP0_REGNUM;
1303
1304 /* double prec register N maps to base regnum for double prec register N */
1305 else if (reg_nr >= tdep->DR0_C_REGNUM
1306 && reg_nr <= tdep->DR_LAST_C_REGNUM)
1307 base_regnum = dr_reg_base_num (tdep->DR0_REGNUM
1308 + reg_nr - tdep->DR0_C_REGNUM);
1309
1310 /* vector N maps to base regnum for vector register N */
1311 else if (reg_nr >= tdep->FV0_C_REGNUM
1312 && reg_nr <= tdep->FV_LAST_C_REGNUM)
1313 base_regnum = fv_reg_base_num (tdep->FV0_REGNUM
1314 + reg_nr - tdep->FV0_C_REGNUM);
1315
1316 else if (reg_nr == tdep->PC_C_REGNUM)
1317 base_regnum = PC_REGNUM;
1318
1319 else if (reg_nr == tdep->GBR_C_REGNUM)
1320 base_regnum = 16;
1321
1322 else if (reg_nr == tdep->MACH_C_REGNUM
1323 || reg_nr == tdep->MACL_C_REGNUM)
1324 base_regnum = 17;
1325
1326 else if (reg_nr == tdep->PR_C_REGNUM)
1327 base_regnum = 18;
1328
1329 else if (reg_nr == tdep->T_C_REGNUM)
1330 base_regnum = 19;
1331
1332 else if (reg_nr == tdep->FPSCR_C_REGNUM)
1333 base_regnum = tdep->FPSCR_REGNUM; /*???? this register is a mess. */
1334
1335 else if (reg_nr == tdep->FPUL_C_REGNUM)
1336 base_regnum = FP0_REGNUM + 32;
1337
1338 return base_regnum;
1339}
1340
1341/* Given a register number RN (according to the gdb scheme) , return
1342 its corresponding architectural register. In media mode, only a
1343 subset of the registers is pseudo registers. For compact mode, all
1344 the registers are pseudo. */
1345static int
1346translate_rn_to_arch_reg_num (int rn, int media_mode)
1347{
1348
1349 if (media_mode)
1350 {
1351 if (!is_media_pseudo (rn))
1352 return rn;
1353 else
1354 return sh64_media_reg_base_num (rn);
1355 }
1356 else
1357 /* All compact registers are pseudo. */
1358 return sh64_compact_reg_base_num (rn);
1359}
1360
1361static int
1362sign_extend (int value, int bits)
1363{
1364 value = value & ((1 << bits) - 1);
1365 return (value & (1 << (bits - 1))
1366 ? value | (~((1 << bits) - 1))
1367 : value);
1368}
1369
cc17453a 1370static void
283150cd 1371sh64_nofp_frame_init_saved_regs (struct frame_info *fi)
cc17453a 1372{
ddde02bd 1373 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
cc17453a
EZ		 1374 int rn;
1375 int have_fp = 0;
283150cd
EZ		 1376 int fp_regnum;
1377 int sp_regnum;
1378 int depth;
1379 int pc;
1380 int opc;
1381 int insn;
1382 int r0_val = 0;
1383 int media_mode = 0;
1384 int insn_size;
1385 int gdb_register_number;
1386 int register_number;
da130f98 1387 char *dummy_regs = deprecated_generic_find_dummy_frame (fi->pc, fi->frame);
283150cd
EZ		 1388 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1389
1390 if (fi->saved_regs == NULL)
1391 frame_saved_regs_zalloc (fi);
1392 else
1393 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
1394
1395 if (dummy_regs)
1396 {
1397 /* DANGER! This is ONLY going to work if the char buffer format of
1398 the saved registers is byte-for-byte identical to the
1399 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1400 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
1401 return;
1402 }
1403
1404 fi->extra_info->leaf_function = 1;
1405 fi->extra_info->f_offset = 0;
1406
1407 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1408 where[rn] = -1;
1409
1410 depth = 0;
1411
1412 /* Loop around examining the prologue insns until we find something
1413 that does not appear to be part of the prologue. But give up
1414 after 20 of them, since we're getting silly then. */
1415
1416 pc = get_pc_function_start (fi->pc);
1417 if (!pc)
1418 {
1419 fi->pc = 0;
1420 return;
1421 }
1422
1423 if (pc_is_isa32 (pc))
1424 {
1425 media_mode = 1;
1426 insn_size = 4;
1427 }
1428 else
1429 {
1430 media_mode = 0;
1431 insn_size = 2;
1432 }
1433
1434 /* The frame pointer register is general register 14 in shmedia and
1435 shcompact modes. In sh compact it is a pseudo register. Same goes
1436 for the stack pointer register, which is register 15. */
1437 fp_regnum = translate_insn_rn (FP_REGNUM, media_mode);
1438 sp_regnum = translate_insn_rn (SP_REGNUM, media_mode);
1439
1440 for (opc = pc + (insn_size * 28); pc < opc; pc += insn_size)
1441 {
1442 insn = read_memory_integer (media_mode ? UNMAKE_ISA32_ADDR (pc) : pc,
1443 insn_size);
1444
1445 if (media_mode == 0)
1446 {
1447 if (IS_STS_PR (insn))
1448 {
1449 int next_insn = read_memory_integer (pc + insn_size, insn_size);
1450 if (IS_MOV_TO_R15 (next_insn))
1451 {
1452 int reg_nr = tdep->PR_C_REGNUM;
1453
1454 where[reg_nr] = depth - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2);
1455 fi->extra_info->leaf_function = 0;
1456 pc += insn_size;
1457 }
1458 }
1459 else if (IS_MOV_R14 (insn))
1460 {
1461 where[fp_regnum] = depth - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
1462 }
1463
1464 else if (IS_MOV_R0 (insn))
1465 {
1466 /* Put in R0 the offset from SP at which to store some
1467 registers. We are interested in this value, because it
1468 will tell us where the given registers are stored within
1469 the frame. */
1470 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
1471 }
1472 else if (IS_ADD_SP_R0 (insn))
1473 {
1474 /* This instruction still prepares r0, but we don't care.
1475 We already have the offset in r0_val. */
1476 }
1477 else if (IS_STS_R0 (insn))
1478 {
1479 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
1480 int reg_nr = tdep->PR_C_REGNUM;
1481 where[reg_nr] = depth - (r0_val - 4);
1482 r0_val -= 4;
1483 fi->extra_info->leaf_function = 0;
1484 }
1485 else if (IS_MOV_R14_R0 (insn))
1486 {
1487 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
1488 where[fp_regnum] = depth - (r0_val - 4);
1489 r0_val -= 4;
1490 }
1491
1492 else if (IS_ADD_SP (insn))
1493 {
1494 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1495 }
1496 else if (IS_MOV_SP_FP (insn))
1497 break;
1498 }
1499 else
1500 {
1501 if (IS_ADDIL_SP_MEDIA (insn)
1502 || IS_ADDI_SP_MEDIA (insn))
1503 {
1504 depth -= sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
1505 }
1506
1507 else if (IS_STQ_R18_R15 (insn))
1508 {
1509 where[tdep->PR_REGNUM] =
1510 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1511 fi->extra_info->leaf_function = 0;
1512 }
1513
1514 else if (IS_STL_R18_R15 (insn))
1515 {
1516 where[tdep->PR_REGNUM] =
1517 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1518 fi->extra_info->leaf_function = 0;
1519 }
1520
1521 else if (IS_STQ_R14_R15 (insn))
1522 {
1523 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1524 }
1525
1526 else if (IS_STL_R14_R15 (insn))
1527 {
1528 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1529 }
1530
1531 else if (IS_MOV_SP_FP_MEDIA (insn))
1532 break;
1533 }
1534 }
1535
1536 /* Now we know how deep things are, we can work out their addresses. */
1537 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1538 {
1539 register_number = translate_rn_to_arch_reg_num (rn, media_mode);
1540
1541 if (where[rn] >= 0)
1542 {
1543 if (rn == fp_regnum)
1544 have_fp = 1;
1545
1546 /* Watch out! saved_regs is only for the real registers, and
1547 doesn't include space for the pseudo registers. */
1548 fi->saved_regs[register_number]= fi->frame - where[rn] + depth;
1549
1550 }
1551 else
1552 fi->saved_regs[register_number] = 0;
1553 }
1554
1555 if (have_fp)
1556 {
1557 /* SP_REGNUM is 15. For shmedia 15 is the real register. For
1558 shcompact 15 is the arch register corresponding to the pseudo
1559 register r15 which still is the SP register. */
1560 /* The place on the stack where fp is stored contains the sp of
1561 the caller. */
1562 /* Again, saved_registers contains only space for the real registers,
1563 so we store in FP_REGNUM position. */
1564 int size;
1565 if (tdep->sh_abi == SH_ABI_32)
1566 size = 4;
1567 else
1568 size = REGISTER_RAW_SIZE (fp_regnum);
1569 fi->saved_regs[sp_regnum] = read_memory_integer (fi->saved_regs[fp_regnum], size);
1570 }
1571 else
1572 fi->saved_regs[sp_regnum] = fi->frame;
1573
1574 fi->extra_info->f_offset = depth - where[fp_regnum];
1575}
1576
1577static void
1578sh_fp_frame_init_saved_regs (struct frame_info *fi)
1579{
ddde02bd 1580 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
283150cd
EZ		 1581 int rn;
1582 int have_fp = 0;
cc17453a
EZ		 1583 int depth;
1584 int pc;
1585 int opc;
1586 int insn;
1587 int r3_val = 0;
da130f98 1588 char *dummy_regs = deprecated_generic_find_dummy_frame (fi->pc, fi->frame);
f81353e4 1589 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
cc17453a
EZ		 1590
1591 if (fi->saved_regs == NULL)
1592 frame_saved_regs_zalloc (fi);
1593 else
1594 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
1595
c906108c
SS		 1596 if (dummy_regs)
1597 {
1598 /* DANGER! This is ONLY going to work if the char buffer format of
c5aa993b
JM		 1599 the saved registers is byte-for-byte identical to the
1600 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
cc17453a 1601 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
c906108c
SS		 1602 return;
1603 }
1604
cc17453a
EZ		 1605 fi->extra_info->leaf_function = 1;
1606 fi->extra_info->f_offset = 0;
c906108c 1607
cd4bffcf 1608 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
c906108c
SS		 1609 where[rn] = -1;
1610
1611 depth = 0;
1612
1613 /* Loop around examining the prologue insns until we find something
1614 that does not appear to be part of the prologue. But give up
1615 after 20 of them, since we're getting silly then. */
1616
2bfa91ee
EZ		 1617 pc = get_pc_function_start (fi->pc);
1618 if (!pc)
c906108c 1619 {
2bfa91ee
EZ		 1620 fi->pc = 0;
1621 return;
1622 }
1623
1624 for (opc = pc + (2 * 28); pc < opc; pc += 2)
1625 {
1626 insn = read_memory_integer (pc, 2);
c906108c
SS		 1627 /* See where the registers will be saved to */
1628 if (IS_PUSH (insn))
1629 {
c906108c
SS		 1630 rn = GET_PUSHED_REG (insn);
1631 where[rn] = depth;
c906108c
SS		 1632 depth += 4;
1633 }
1634 else if (IS_STS (insn))
1635 {
f81353e4 1636 where[tdep->PR_REGNUM] = depth;
c906108c 1637 /* If we're storing the pr then this isn't a leaf */
cc17453a 1638 fi->extra_info->leaf_function = 0;
c906108c
SS		 1639 depth += 4;
1640 }
1641 else if (IS_MOV_R3 (insn))
1642 {
1643 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 1644 }
1645 else if (IS_SHLL_R3 (insn))
1646 {
1647 r3_val <<= 1;
c906108c
SS		 1648 }
1649 else if (IS_ADD_R3SP (insn))
1650 {
1651 depth += -r3_val;
c906108c
SS		 1652 }
1653 else if (IS_ADD_SP (insn))
1654 {
c906108c 1655 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 1656 }
1657 else if (IS_FMOV (insn))
1658 {
f81353e4 1659 if (read_register (tdep->FPSCR_REGNUM) & FPSCR_SZ)
c906108c
SS		 1660 {
1661 depth += 8;
1662 }
1663 else
1664 {
1665 depth += 4;
1666 }
1667 }
2bfa91ee
EZ		 1668 else if (IS_MOV_SP_FP (insn))
1669 break;
1670#if 0 /* This used to just stop when it found an instruction that
1671 was not considered part of the prologue. Now, we just
1672 keep going looking for likely instructions. */
c906108c
SS		 1673 else
1674 break;
2bfa91ee 1675#endif
c906108c
SS		 1676 }
1677
1678 /* Now we know how deep things are, we can work out their addresses */
1679
cd4bffcf 1680 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
c906108c
SS		 1681 {
1682 if (where[rn] >= 0)
1683 {
1684 if (rn == FP_REGNUM)
1685 have_fp = 1;
1686
cc17453a 1687 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
c906108c
SS		 1688 }
1689 else
1690 {
cc17453a 1691 fi->saved_regs[rn] = 0;
c906108c
SS		 1692 }
1693 }
1694
1695 if (have_fp)
1696 {
cd4bffcf
EZ		 1697 fi->saved_regs[SP_REGNUM] =
1698 read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
c906108c
SS		 1699 }
1700 else
1701 {
cc17453a 1702 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
c906108c
SS		 1703 }
1704
cc17453a 1705 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
c906108c
SS		 1706 /* Work out the return pc - either from the saved pr or the pr
1707 value */
1708}
1709
cc17453a
EZ		 1710/* Initialize the extra info saved in a FRAME */
1711static void
fba45db2 1712sh_init_extra_frame_info (int fromleaf, struct frame_info *fi)
c906108c 1713{
cc17453a
EZ		 1714
1715 fi->extra_info = (struct frame_extra_info *)
1716 frame_obstack_alloc (sizeof (struct frame_extra_info));
c906108c
SS		 1717
1718 if (fi->next)
1719 fi->pc = FRAME_SAVED_PC (fi->next);
1720
1721 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
1722 {
1723 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
c5aa993b
JM		 1724 by assuming it's always FP. */
1725 fi->frame = generic_read_register_dummy (fi->pc, fi->frame,
1726 SP_REGNUM);
cd4bffcf
EZ		 1727 fi->extra_info->return_pc = generic_read_register_dummy (fi->pc,
1728 fi->frame,
cc17453a
EZ		 1729 PC_REGNUM);
1730 fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4);
1731 fi->extra_info->leaf_function = 0;
c906108c
SS		 1732 return;
1733 }
1734 else
1735 {
cc17453a 1736 FRAME_INIT_SAVED_REGS (fi);
cd4bffcf
EZ		 1737 fi->extra_info->return_pc =
1738 sh_find_callers_reg (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM);
c906108c
SS		 1739 }
1740}
1741
283150cd
EZ		 1742static void
1743sh64_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1744{
1745 int media_mode = pc_is_isa32 (fi->pc);
1746
1747 fi->extra_info = (struct frame_extra_info *)
1748 frame_obstack_alloc (sizeof (struct frame_extra_info));
1749
1750 if (fi->next)
1751 fi->pc = FRAME_SAVED_PC (fi->next);
1752
1753 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
1754 {
1755 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1756 by assuming it's always FP. */
1757 fi->frame = generic_read_register_dummy (fi->pc, fi->frame,
1758 SP_REGNUM);
1759 fi->extra_info->return_pc =
1760 generic_read_register_dummy (fi->pc, fi->frame, PC_REGNUM);
1761 fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4);
1762 fi->extra_info->leaf_function = 0;
1763 return;
1764 }
1765 else
1766 {
1767 FRAME_INIT_SAVED_REGS (fi);
1768 fi->extra_info->return_pc =
1769 sh64_get_saved_pr (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM);
1770 }
1771}
1772
1773void
1774sh64_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp,
1775 struct frame_info *frame, int regnum,
1776 enum lval_type *lval)
1777{
1778 int media_mode;
1779 int live_regnum = regnum;
1780 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1781
1782 if (!target_has_registers)
1783 error ("No registers.");
1784
1785 /* Normal systems don't optimize out things with register numbers. */
1786 if (optimized != NULL)
1787 *optimized = 0;
1788
1789 if (addrp) /* default assumption: not found in memory */
1790 *addrp = 0;
1791
1792 if (raw_buffer)
1793 memset (raw_buffer, 0, sizeof (raw_buffer));
1794
1795 /* We must do this here, before the following while loop changes
1796 frame, and makes it NULL. If this is a media register number,
1797 but we are in compact mode, it will become the corresponding
1798 compact pseudo register. If there is no corresponding compact
1799 pseudo-register what do we do?*/
1800 media_mode = pc_is_isa32 (frame->pc);
1801 live_regnum = translate_insn_rn (regnum, media_mode);
1802
1803 /* Note: since the current frame's registers could only have been
1804 saved by frames INTERIOR TO the current frame, we skip examining
1805 the current frame itself: otherwise, we would be getting the
1806 previous frame's registers which were saved by the current frame. */
1807
1808 while (frame && ((frame = frame->next) != NULL))
1809 {
1810 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
1811 {
1812 if (lval) /* found it in a CALL_DUMMY frame */
1813 *lval = not_lval;
1814 if (raw_buffer)
1815 memcpy (raw_buffer,
da130f98
AC		 1816 (deprecated_generic_find_dummy_frame (frame->pc, frame->frame)
1817 + REGISTER_BYTE (regnum)),
283150cd
EZ		 1818 REGISTER_RAW_SIZE (regnum));
1819 return;
1820 }
1821
1822 FRAME_INIT_SAVED_REGS (frame);
1823 if (frame->saved_regs != NULL
1824 && frame->saved_regs[regnum] != 0)
1825 {
1826 if (lval) /* found it saved on the stack */
1827 *lval = lval_memory;
1828 if (regnum == SP_REGNUM)
1829 {
1830 if (raw_buffer) /* SP register treated specially */
1831 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum),
1832 frame->saved_regs[regnum]);
1833 }
1834 else
1835 { /* any other register */
1836
1837 if (addrp)
1838 *addrp = frame->saved_regs[regnum];
1839 if (raw_buffer)
1840 {
1841 int size;
1842 if (tdep->sh_abi == SH_ABI_32
1843 && (live_regnum == FP_REGNUM
1844 || live_regnum == tdep->PR_REGNUM))
1845 size = 4;
1846 else
1847 size = REGISTER_RAW_SIZE (live_regnum);
1848 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1849 read_memory (frame->saved_regs[regnum], raw_buffer, size);
1850 else
1851 read_memory (frame->saved_regs[regnum],
1852 raw_buffer
1853 + REGISTER_RAW_SIZE (live_regnum)
1854 - size,
1855 size);
1856 }
1857 }
1858 return;
1859 }
1860 }
1861
1862 /* If we get thru the loop to this point, it means the register was
1863 not saved in any frame. Return the actual live-register value. */
1864
1865 if (lval) /* found it in a live register */
1866 *lval = lval_register;
1867 if (addrp)
1868 *addrp = REGISTER_BYTE (live_regnum);
1869 if (raw_buffer)
1870 read_register_gen (live_regnum, raw_buffer);
1871}
1872
cc17453a
EZ		 1873/* Extract from an array REGBUF containing the (raw) register state
1874 the address in which a function should return its structure value,
1875 as a CORE_ADDR (or an expression that can be used as one). */
b3df3fff 1876static CORE_ADDR
0c8053b6 1877sh_extract_struct_value_address (char *regbuf)
cc17453a
EZ		 1878{
1879 return (extract_address ((regbuf), REGISTER_RAW_SIZE (0)));
1880}
1881
283150cd
EZ		 1882static CORE_ADDR
1883sh64_extract_struct_value_address (char *regbuf)
1884{
1885 return (extract_address ((regbuf + REGISTER_BYTE (STRUCT_RETURN_REGNUM)),
1886 REGISTER_RAW_SIZE (STRUCT_RETURN_REGNUM)));
1887}
1888
cc17453a 1889static CORE_ADDR
fba45db2 1890sh_frame_saved_pc (struct frame_info *frame)
cc17453a
EZ		 1891{
1892 return ((frame)->extra_info->return_pc);
1893}
1894
c906108c
SS		 1895/* Discard from the stack the innermost frame,
1896 restoring all saved registers. */
cc17453a 1897static void
fba45db2 1898sh_pop_frame (void)
c906108c
SS		 1899{
1900 register struct frame_info *frame = get_current_frame ();
1901 register CORE_ADDR fp;
1902 register int regnum;
c906108c
SS		 1903
1904 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
1905 generic_pop_dummy_frame ();
1906 else
c5aa993b
JM		 1907 {
1908 fp = FRAME_FP (frame);
cc17453a 1909 FRAME_INIT_SAVED_REGS (frame);
c906108c 1910
c5aa993b 1911 /* Copy regs from where they were saved in the frame */
cd4bffcf 1912 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
cc17453a 1913 if (frame->saved_regs[regnum])
cd4bffcf
EZ		 1914 write_register (regnum,
1915 read_memory_integer (frame->saved_regs[regnum], 4));
c906108c 1916
cc17453a 1917 write_register (PC_REGNUM, frame->extra_info->return_pc);
c5aa993b
JM		 1918 write_register (SP_REGNUM, fp + 4);
1919 }
c906108c
SS		 1920 flush_cached_frames ();
1921}
1922
283150cd
EZ		 1923/* Used in the 'return' command. */
1924static void
1925sh64_pop_frame (void)
1926{
1927 register struct frame_info *frame = get_current_frame ();
1928 register CORE_ADDR fp;
1929 register int regnum;
1930 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1931
1932 int media_mode = pc_is_isa32 (frame->pc);
1933
1934 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
1935 generic_pop_dummy_frame ();
1936 else
1937 {
1938 fp = FRAME_FP (frame);
1939 FRAME_INIT_SAVED_REGS (frame);
1940
1941 /* Copy regs from where they were saved in the frame */
1942 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
1943 if (frame->saved_regs[regnum])
1944 {
1945 int size;
1946 if (tdep->sh_abi == SH_ABI_32
1947 && (regnum == FP_REGNUM
1948 || regnum == tdep->PR_REGNUM))
1949 size = 4;
1950 else
1951 size = REGISTER_RAW_SIZE (translate_insn_rn (regnum,
1952 media_mode));
1953 write_register (regnum,
1954 read_memory_integer (frame->saved_regs[regnum],
1955 size));
1956 }
1957
1958 write_register (PC_REGNUM, frame->extra_info->return_pc);
1959 write_register (SP_REGNUM, fp + 8);
1960 }
1961 flush_cached_frames ();
1962}
1963
c906108c
SS		 1964/* Function: push_arguments
1965 Setup the function arguments for calling a function in the inferior.
1966
1967 On the Hitachi SH architecture, there are four registers (R4 to R7)
1968 which are dedicated for passing function arguments. Up to the first
1969 four arguments (depending on size) may go into these registers.
1970 The rest go on the stack.
1971
1972 Arguments that are smaller than 4 bytes will still take up a whole
1973 register or a whole 32-bit word on the stack, and will be
1974 right-justified in the register or the stack word. This includes
1975 chars, shorts, and small aggregate types.
1976
1977 Arguments that are larger than 4 bytes may be split between two or
1978 more registers. If there are not enough registers free, an argument
1979 may be passed partly in a register (or registers), and partly on the
1980 stack. This includes doubles, long longs, and larger aggregates.
1981 As far as I know, there is no upper limit to the size of aggregates
1982 that will be passed in this way; in other words, the convention of
1983 passing a pointer to a large aggregate instead of a copy is not used.
1984
1985 An exceptional case exists for struct arguments (and possibly other
1986 aggregates such as arrays) if the size is larger than 4 bytes but
1987 not a multiple of 4 bytes. In this case the argument is never split
1988 between the registers and the stack, but instead is copied in its
1989 entirety onto the stack, AND also copied into as many registers as
1990 there is room for. In other words, space in registers permitting,
1991 two copies of the same argument are passed in. As far as I can tell,
1992 only the one on the stack is used, although that may be a function
1993 of the level of compiler optimization. I suspect this is a compiler
1994 bug. Arguments of these odd sizes are left-justified within the
1995 word (as opposed to arguments smaller than 4 bytes, which are
1996 right-justified).
c5aa993b 1997
c906108c
SS		 1998 If the function is to return an aggregate type such as a struct, it
1999 is either returned in the normal return value register R0 (if its
2000 size is no greater than one byte), or else the caller must allocate
2001 space into which the callee will copy the return value (if the size
2002 is greater than one byte). In this case, a pointer to the return
2003 value location is passed into the callee in register R2, which does
2004 not displace any of the other arguments passed in via registers R4
2005 to R7. */
2006
cc17453a 2007static CORE_ADDR
34e9d9bb 2008sh_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
3bbfbb92 2009 int struct_return, CORE_ADDR struct_addr)
c906108c
SS		 2010{
2011 int stack_offset, stack_alloc;
2012 int argreg;
2013 int argnum;
2014 struct type *type;
2015 CORE_ADDR regval;
2016 char *val;
2017 char valbuf[4];
2018 int len;
2019 int odd_sized_struct;
f81353e4 2020 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
c906108c
SS		 2021
2022 /* first force sp to a 4-byte alignment */
2023 sp = sp & ~3;
2024
2025 /* The "struct return pointer" pseudo-argument has its own dedicated
2026 register */
2027 if (struct_return)
c5aa993b 2028 write_register (STRUCT_RETURN_REGNUM, struct_addr);
c906108c
SS		 2029
2030 /* Now make sure there's space on the stack */
cc17453a 2031 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
c5aa993b
JM		 2032 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
2033 sp -= stack_alloc; /* make room on stack for args */
c906108c 2034
c906108c
SS		 2035 /* Now load as many as possible of the first arguments into
2036 registers, and push the rest onto the stack. There are 16 bytes
2037 in four registers available. Loop thru args from first to last. */
2038
f81353e4 2039 argreg = tdep->ARG0_REGNUM;
c906108c
SS		 2040 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
2041 {
2042 type = VALUE_TYPE (args[argnum]);
c5aa993b
JM		 2043 len = TYPE_LENGTH (type);
2044 memset (valbuf, 0, sizeof (valbuf));
c906108c 2045 if (len < 4)
cc17453a
EZ		 2046 {
2047 /* value gets right-justified in the register or stack word */
c5aa993b
JM		 2048 memcpy (valbuf + (4 - len),
2049 (char *) VALUE_CONTENTS (args[argnum]), len);
2050 val = valbuf;
2051 }
c906108c 2052 else
c5aa993b 2053 val = (char *) VALUE_CONTENTS (args[argnum]);
c906108c
SS		 2054
2055 if (len > 4 && (len & 3) != 0)
c5aa993b
JM		 2056 odd_sized_struct = 1; /* such structs go entirely on stack */
2057 else
c906108c
SS		 2058 odd_sized_struct = 0;
2059 while (len > 0)
2060 {
f81353e4 2061 if (argreg > tdep->ARGLAST_REGNUM
3bbfbb92
EZ		 2062 || odd_sized_struct)
2063 {
2064 /* must go on the stack */
c906108c
SS		 2065 write_memory (sp + stack_offset, val, 4);
2066 stack_offset += 4;
2067 }
2068 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2069 That's because some *&^%$ things get passed on the stack
2070 AND in the registers! */
f81353e4 2071 if (argreg <= tdep->ARGLAST_REGNUM)
3bbfbb92
EZ		 2072 {
2073 /* there's room in a register */
c5aa993b 2074 regval = extract_address (val, REGISTER_RAW_SIZE (argreg));
c906108c
SS		 2075 write_register (argreg++, regval);
2076 }
2077 /* Store the value 4 bytes at a time. This means that things
2078 larger than 4 bytes may go partly in registers and partly
2079 on the stack. */
c5aa993b
JM		 2080 len -= REGISTER_RAW_SIZE (argreg);
2081 val += REGISTER_RAW_SIZE (argreg);
c906108c
SS		 2082 }
2083 }
2084 return sp;
2085}
2086
283150cd
EZ		 2087/* R2-R9 for integer types and integer equivalent (char, pointers) and
2088 non-scalar (struct, union) elements (even if the elements are
2089 floats).
2090 FR0-FR11 for single precision floating point (float)
2091 DR0-DR10 for double precision floating point (double)
2092
2093 If a float is argument number 3 (for instance) and arguments number
2094 1,2, and 4 are integer, the mapping will be:
2095 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
2096
2097 If a float is argument number 10 (for instance) and arguments number
2098 1 through 10 are integer, the mapping will be:
2099 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
2100 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
2101 I.e. there is hole in the stack.
2102
2103 Different rules apply for variable arguments functions, and for functions
2104 for which the prototype is not known. */
2105
2106static CORE_ADDR
2107sh64_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
2108 int struct_return, CORE_ADDR struct_addr)
2109{
2110 int stack_offset, stack_alloc;
2111 int int_argreg;
2112 int float_argreg;
2113 int double_argreg;
2114 int float_arg_index = 0;
2115 int double_arg_index = 0;
2116 int argnum;
2117 struct type *type;
2118 CORE_ADDR regval;
2119 char *val;
2120 char valbuf[8];
2121 char valbuf_tmp[8];
2122 int len;
2123 int argreg_size;
2124 int fp_args[12];
2125 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2126
2127 memset (fp_args, 0, sizeof (fp_args));
2128
2129 /* first force sp to a 8-byte alignment */
2130 sp = sp & ~7;
2131
2132 /* The "struct return pointer" pseudo-argument has its own dedicated
2133 register */
2134
2135 if (struct_return)
2136 write_register (STRUCT_RETURN_REGNUM, struct_addr);
2137
2138 /* Now make sure there's space on the stack */
2139 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
2140 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 7) & ~7);
2141 sp -= stack_alloc; /* make room on stack for args */
2142
2143 /* Now load as many as possible of the first arguments into
2144 registers, and push the rest onto the stack. There are 64 bytes
2145 in eight registers available. Loop thru args from first to last. */
2146
2147 int_argreg = tdep->ARG0_REGNUM;
2148 float_argreg = FP0_REGNUM;
2149 double_argreg = tdep->DR0_REGNUM;
2150
2151 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
2152 {
2153 type = VALUE_TYPE (args[argnum]);
2154 len = TYPE_LENGTH (type);
2155 memset (valbuf, 0, sizeof (valbuf));
2156
2157 if (TYPE_CODE (type) != TYPE_CODE_FLT)
2158 {
2159 argreg_size = REGISTER_RAW_SIZE (int_argreg);
2160
2161 if (len < argreg_size)
2162 {
2163 /* value gets right-justified in the register or stack word */
2164 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2165 memcpy (valbuf + argreg_size - len,
2166 (char *) VALUE_CONTENTS (args[argnum]), len);
2167 else
2168 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
2169
2170 val = valbuf;
2171 }
2172 else
2173 val = (char *) VALUE_CONTENTS (args[argnum]);
2174
2175 while (len > 0)
2176 {
2177 if (int_argreg > tdep->ARGLAST_REGNUM)
2178 {
2179 /* must go on the stack */
2180 write_memory (sp + stack_offset, val, argreg_size);
2181 stack_offset += 8;/*argreg_size;*/
2182 }
2183 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2184 That's because some *&^%$ things get passed on the stack
2185 AND in the registers! */
2186 if (int_argreg <= tdep->ARGLAST_REGNUM)
2187 {
2188 /* there's room in a register */
2189 regval = extract_address (val, argreg_size);
2190 write_register (int_argreg, regval);
2191 }
2192 /* Store the value 8 bytes at a time. This means that
2193 things larger than 8 bytes may go partly in registers
2194 and partly on the stack. FIXME: argreg is incremented
2195 before we use its size. */
2196 len -= argreg_size;
2197 val += argreg_size;
2198 int_argreg++;
2199 }
2200 }
2201 else
2202 {
2203 val = (char *) VALUE_CONTENTS (args[argnum]);
2204 if (len == 4)
2205 {
2206 /* Where is it going to be stored? */
2207 while (fp_args[float_arg_index])
2208 float_arg_index ++;
2209
2210 /* Now float_argreg points to the register where it
2211 should be stored. Are we still within the allowed
2212 register set? */
2213 if (float_arg_index <= tdep->FLOAT_ARGLAST_REGNUM)
2214 {
2215 /* Goes in FR0...FR11 */
2216 write_register_gen (FP0_REGNUM + float_arg_index, val);
2217 fp_args[float_arg_index] = 1;
2218 /* Skip the corresponding general argument register. */
2219 int_argreg ++;
2220 }
2221 else
2222 ;
2223 /* Store it as the integers, 8 bytes at the time, if
2224 necessary spilling on the stack. */
2225
2226 }
2227 else if (len == 8)
2228 {
2229 /* Where is it going to be stored? */
2230 while (fp_args[double_arg_index])
2231 double_arg_index += 2;
2232 /* Now double_argreg points to the register
2233 where it should be stored.
2234 Are we still within the allowed register set? */
2235 if (double_arg_index < tdep->FLOAT_ARGLAST_REGNUM)
2236 {
2237 /* Goes in DR0...DR10 */
2238 /* The numbering of the DRi registers is consecutive,
2239 i.e. includes odd numbers. */
2240 int double_register_offset = double_arg_index / 2;
2241 int regnum = tdep->DR0_REGNUM +
2242 double_register_offset;
2243#if 0
2244 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2245 {
2246 memset (valbuf_tmp, 0, sizeof (valbuf_tmp));
2247 REGISTER_CONVERT_TO_VIRTUAL (regnum,
2248 type, val, valbuf_tmp);
2249 val = valbuf_tmp;
2250 }
2251#endif
2252 /* Note: must use write_register_gen here instead
0818c12a
AC		 2253 of regcache_raw_write, because
2254 regcache_raw_write works only for real
2255 registers, not pseudo. write_register_gen will
2256 call the gdbarch function to do register
2257 writes, and that will properly know how to deal
2258 with pseudoregs. */
283150cd
EZ		 2259 write_register_gen (regnum, val);
2260 fp_args[double_arg_index] = 1;
2261 fp_args[double_arg_index + 1] = 1;
2262 /* Skip the corresponding general argument register. */
2263 int_argreg ++;
2264 }
2265 else
2266 ;
2267 /* Store it as the integers, 8 bytes at the time, if
2268 necessary spilling on the stack. */
2269 }
2270 }
2271 }
2272 return sp;
2273}
2274
c906108c
SS		 2275/* Function: push_return_address (pc)
2276 Set up the return address for the inferior function call.
2277 Needed for targets where we don't actually execute a JSR/BSR instruction */
2278
cc17453a 2279static CORE_ADDR
fba45db2 2280sh_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
c906108c 2281{
283150cd
EZ		 2282 write_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM,
2283 CALL_DUMMY_ADDRESS ());
c906108c
SS		 2284 return sp;
2285}
2286
2287/* Function: fix_call_dummy
2288 Poke the callee function's address into the destination part of
2289 the CALL_DUMMY. The address is actually stored in a data word
2290 following the actualy CALL_DUMMY instructions, which will load
2291 it into a register using PC-relative addressing. This function
2292 expects the CALL_DUMMY to look like this:
2293
c5aa993b
JM		 2294 mov.w @(2,PC), R8
2295 jsr @R8
2296 nop
2297 trap
2298 <destination>
2299 */
c906108c
SS		 2300
2301#if 0
2302void
fba45db2 2303sh_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
ea7c478f 2304 struct value **args, struct type *type, int gcc_p)
c906108c
SS		 2305{
2306 *(unsigned long *) (dummy + 8) = fun;
2307}
2308#endif
2309
cc17453a
EZ		 2310static int
2311sh_coerce_float_to_double (struct type *formal, struct type *actual)
2312{
2313 return 1;
2314}
c906108c 2315
cc17453a
EZ		 2316/* Find a function's return value in the appropriate registers (in
2317 regbuf), and copy it into valbuf. Extract from an array REGBUF
2318 containing the (raw) register state a function return value of type
2319 TYPE, and copy that, in virtual format, into VALBUF. */
2320static void
fba45db2 2321sh_extract_return_value (struct type *type, char *regbuf, char *valbuf)
c906108c 2322{
cc17453a 2323 int len = TYPE_LENGTH (type);
3116c80a
EZ		 2324 int return_register = R0_REGNUM;
2325 int offset;
2326
cc17453a 2327 if (len <= 4)
3116c80a 2328 {
d7449b42 2329 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3116c80a
EZ		 2330 offset = REGISTER_BYTE (return_register) + 4 - len;
2331 else
2332 offset = REGISTER_BYTE (return_register);
2333 memcpy (valbuf, regbuf + offset, len);
2334 }
cc17453a 2335 else if (len <= 8)
3116c80a 2336 {
d7449b42 2337 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3116c80a
EZ		 2338 offset = REGISTER_BYTE (return_register) + 8 - len;
2339 else
2340 offset = REGISTER_BYTE (return_register);
2341 memcpy (valbuf, regbuf + offset, len);
2342 }
2343 else
2344 error ("bad size for return value");
2345}
2346
2347static void
2348sh3e_sh4_extract_return_value (struct type *type, char *regbuf, char *valbuf)
2349{
2350 int return_register;
2351 int offset;
2352 int len = TYPE_LENGTH (type);
2353
2354 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2355 return_register = FP0_REGNUM;
2356 else
2357 return_register = R0_REGNUM;
2358
2359 if (len == 8 && TYPE_CODE (type) == TYPE_CODE_FLT)
2360 {
2361 DOUBLEST val;
778eb05e 2362 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
3116c80a
EZ		 2363 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2364 (char *) regbuf + REGISTER_BYTE (return_register),
2365 &val);
2366 else
2367 floatformat_to_doublest (&floatformat_ieee_double_big,
2368 (char *) regbuf + REGISTER_BYTE (return_register),
2369 &val);
2370 store_floating (valbuf, len, val);
2371 }
2372 else if (len <= 4)
2373 {
d7449b42 2374 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3116c80a
EZ		 2375 offset = REGISTER_BYTE (return_register) + 4 - len;
2376 else
2377 offset = REGISTER_BYTE (return_register);
2378 memcpy (valbuf, regbuf + offset, len);
2379 }
2380 else if (len <= 8)
2381 {
d7449b42 2382 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3116c80a
EZ		 2383 offset = REGISTER_BYTE (return_register) + 8 - len;
2384 else
2385 offset = REGISTER_BYTE (return_register);
2386 memcpy (valbuf, regbuf + offset, len);
2387 }
cc17453a
EZ		 2388 else
2389 error ("bad size for return value");
2390}
c906108c 2391
283150cd
EZ		 2392static void
2393sh64_extract_return_value (struct type *type, char *regbuf, char *valbuf)
2394{
2395 int offset;
2396 int return_register;
2397 int len = TYPE_LENGTH (type);
2398 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2399
2400 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2401 {
2402 if (len == 4)
2403 {
2404 /* Return value stored in FP0_REGNUM */
2405 return_register = FP0_REGNUM;
2406 offset = REGISTER_BYTE (return_register);
2407 memcpy (valbuf, (char *) regbuf + offset, len);
2408 }
2409 else if (len == 8)
2410 {
2411 /* return value stored in DR0_REGNUM */
2412 DOUBLEST val;
2413
2414 return_register = tdep->DR0_REGNUM;
2415 offset = REGISTER_BYTE (return_register);
2416
2417 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2418 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2419 (char *) regbuf + offset, &val);
2420 else
2421 floatformat_to_doublest (&floatformat_ieee_double_big,
2422 (char *) regbuf + offset, &val);
2423 store_floating (valbuf, len, val);
2424 }
2425 }
2426 else
2427 {
2428 if (len <= 8)
2429 {
2430 /* Result is in register 2. If smaller than 8 bytes, it is padded
2431 at the most significant end. */
2432 return_register = tdep->RETURN_REGNUM;
2433 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2434 offset = REGISTER_BYTE (return_register) +
2435 REGISTER_RAW_SIZE (return_register) - len;
2436 else
2437 offset = REGISTER_BYTE (return_register);
2438 memcpy (valbuf, (char *) regbuf + offset, len);
2439 }
2440 else
2441 error ("bad size for return value");
2442 }
2443}
2444
cc17453a
EZ		 2445/* Write into appropriate registers a function return value
2446 of type TYPE, given in virtual format.
2447 If the architecture is sh4 or sh3e, store a function's return value
2448 in the R0 general register or in the FP0 floating point register,
2449 depending on the type of the return value. In all the other cases
3bbfbb92 2450 the result is stored in r0, left-justified. */
cc17453a
EZ		 2451static void
2452sh_default_store_return_value (struct type *type, char *valbuf)
2453{
d19b71be
MS		 2454 char buf[32]; /* more than enough... */
2455
2456 if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (R0_REGNUM))
2457 {
2458 /* Add leading zeros to the value. */
2459 memset (buf, 0, REGISTER_RAW_SIZE (R0_REGNUM));
2460 memcpy (buf + REGISTER_RAW_SIZE (R0_REGNUM) - TYPE_LENGTH (type),
2461 valbuf, TYPE_LENGTH (type));
2462 write_register_bytes (REGISTER_BYTE (R0_REGNUM), buf,
2463 REGISTER_RAW_SIZE (R0_REGNUM));
2464 }
2465 else
2466 write_register_bytes (REGISTER_BYTE (R0_REGNUM), valbuf,
2467 TYPE_LENGTH (type));
cc17453a 2468}
c906108c 2469
cc17453a
EZ		 2470static void
2471sh3e_sh4_store_return_value (struct type *type, char *valbuf)
2472{
2473 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2474 write_register_bytes (REGISTER_BYTE (FP0_REGNUM),
2475 valbuf, TYPE_LENGTH (type));
2476 else
d19b71be 2477 sh_default_store_return_value (type, valbuf);
c906108c
SS		 2478}
2479
283150cd
EZ		 2480static void
2481sh64_store_return_value (struct type *type, char *valbuf)
2482{
2483 char buf[64]; /* more than enough... */
2484 int len = TYPE_LENGTH (type);
2485
2486 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2487 {
2488 if (len == 4)
2489 {
2490 /* Return value stored in FP0_REGNUM */
2491 write_register_gen (FP0_REGNUM, valbuf);
2492 }
2493 if (len == 8)
2494 {
2495 /* return value stored in DR0_REGNUM */
2496 /* FIXME: Implement */
2497 }
2498 }
2499 else
2500 {
2501 int return_register = gdbarch_tdep (current_gdbarch)->RETURN_REGNUM;
2502 int offset = 0;
2503
2504 if (len <= REGISTER_RAW_SIZE (return_register))
2505 {
2506 /* Pad with zeros. */
2507 memset (buf, 0, REGISTER_RAW_SIZE (return_register));
2508 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2509 offset = 0; /*REGISTER_RAW_SIZE (return_register) - len;*/
2510 else
2511 offset = REGISTER_RAW_SIZE (return_register) - len;
2512
2513 memcpy (buf + offset, valbuf, len);
2514 write_register_gen (return_register, buf);
2515 }
2516 else
2517 write_register_gen (return_register, valbuf);
2518 }
2519}
2520
c906108c
SS		 2521/* Print the registers in a form similar to the E7000 */
2522
2523static void
fba45db2 2524sh_generic_show_regs (void)
c906108c 2525{
f81353e4
EZ		 2526 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2527
cc17453a
EZ		 2528 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2529 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 2530 (long) read_register (tdep->SR_REGNUM),
2531 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 2532 (long) read_register (MACH_REGNUM),
2533 (long) read_register (MACL_REGNUM));
2534
2535 printf_filtered ("GBR=%08lx VBR=%08lx",
2536 (long) read_register (GBR_REGNUM),
2537 (long) read_register (VBR_REGNUM));
2538
2539 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2540 (long) read_register (0),
2541 (long) read_register (1),
2542 (long) read_register (2),
2543 (long) read_register (3),
2544 (long) read_register (4),
2545 (long) read_register (5),
2546 (long) read_register (6),
2547 (long) read_register (7));
2548 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2549 (long) read_register (8),
2550 (long) read_register (9),
2551 (long) read_register (10),
2552 (long) read_register (11),
2553 (long) read_register (12),
2554 (long) read_register (13),
2555 (long) read_register (14),
2556 (long) read_register (15));
2557}
c906108c 2558
cc17453a 2559static void
fba45db2 2560sh3_show_regs (void)
cc17453a 2561{
f81353e4
EZ		 2562 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2563
d4f3574e
SS		 2564 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2565 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 2566 (long) read_register (tdep->SR_REGNUM),
2567 (long) read_register (tdep->PR_REGNUM),
d4f3574e
SS		 2568 (long) read_register (MACH_REGNUM),
2569 (long) read_register (MACL_REGNUM));
2570
2571 printf_filtered ("GBR=%08lx VBR=%08lx",
2572 (long) read_register (GBR_REGNUM),
2573 (long) read_register (VBR_REGNUM));
cc17453a 2574 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 2575 (long) read_register (tdep->SSR_REGNUM),
2576 (long) read_register (tdep->SPC_REGNUM));
c906108c 2577
d4f3574e
SS		 2578 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2579 (long) read_register (0),
2580 (long) read_register (1),
2581 (long) read_register (2),
2582 (long) read_register (3),
2583 (long) read_register (4),
2584 (long) read_register (5),
2585 (long) read_register (6),
2586 (long) read_register (7));
2587 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2588 (long) read_register (8),
2589 (long) read_register (9),
2590 (long) read_register (10),
2591 (long) read_register (11),
2592 (long) read_register (12),
2593 (long) read_register (13),
2594 (long) read_register (14),
2595 (long) read_register (15));
c906108c
SS		 2596}
2597
53116e27 2598
cc17453a 2599static void
fba45db2 2600sh3e_show_regs (void)
cc17453a 2601{
f81353e4
EZ		 2602 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2603
cc17453a
EZ		 2604 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2605 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 2606 (long) read_register (tdep->SR_REGNUM),
2607 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 2608 (long) read_register (MACH_REGNUM),
2609 (long) read_register (MACL_REGNUM));
2610
2611 printf_filtered ("GBR=%08lx VBR=%08lx",
2612 (long) read_register (GBR_REGNUM),
2613 (long) read_register (VBR_REGNUM));
2614 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 2615 (long) read_register (tdep->SSR_REGNUM),
2616 (long) read_register (tdep->SPC_REGNUM));
cc17453a 2617 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
f81353e4
EZ		 2618 (long) read_register (tdep->FPUL_REGNUM),
2619 (long) read_register (tdep->FPSCR_REGNUM));
c906108c 2620
cc17453a
EZ		 2621 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2622 (long) read_register (0),
2623 (long) read_register (1),
2624 (long) read_register (2),
2625 (long) read_register (3),
2626 (long) read_register (4),
2627 (long) read_register (5),
2628 (long) read_register (6),
2629 (long) read_register (7));
2630 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2631 (long) read_register (8),
2632 (long) read_register (9),
2633 (long) read_register (10),
2634 (long) read_register (11),
2635 (long) read_register (12),
2636 (long) read_register (13),
2637 (long) read_register (14),
2638 (long) read_register (15));
2639
2640 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2641 (long) read_register (FP0_REGNUM + 0),
2642 (long) read_register (FP0_REGNUM + 1),
2643 (long) read_register (FP0_REGNUM + 2),
2644 (long) read_register (FP0_REGNUM + 3),
2645 (long) read_register (FP0_REGNUM + 4),
2646 (long) read_register (FP0_REGNUM + 5),
2647 (long) read_register (FP0_REGNUM + 6),
2648 (long) read_register (FP0_REGNUM + 7));
2649 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2650 (long) read_register (FP0_REGNUM + 8),
2651 (long) read_register (FP0_REGNUM + 9),
2652 (long) read_register (FP0_REGNUM + 10),
2653 (long) read_register (FP0_REGNUM + 11),
2654 (long) read_register (FP0_REGNUM + 12),
2655 (long) read_register (FP0_REGNUM + 13),
2656 (long) read_register (FP0_REGNUM + 14),
2657 (long) read_register (FP0_REGNUM + 15));
2658}
2659
2660static void
fba45db2 2661sh3_dsp_show_regs (void)
c906108c 2662{
f81353e4
EZ		 2663 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2664
cc17453a
EZ		 2665 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2666 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 2667 (long) read_register (tdep->SR_REGNUM),
2668 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 2669 (long) read_register (MACH_REGNUM),
2670 (long) read_register (MACL_REGNUM));
c906108c 2671
cc17453a
EZ		 2672 printf_filtered ("GBR=%08lx VBR=%08lx",
2673 (long) read_register (GBR_REGNUM),
2674 (long) read_register (VBR_REGNUM));
2675
2676 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 2677 (long) read_register (tdep->SSR_REGNUM),
2678 (long) read_register (tdep->SPC_REGNUM));
cc17453a
EZ		 2679
2680 printf_filtered (" DSR=%08lx",
f81353e4 2681 (long) read_register (tdep->DSR_REGNUM));
cc17453a
EZ		 2682
2683 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2684 (long) read_register (0),
2685 (long) read_register (1),
2686 (long) read_register (2),
2687 (long) read_register (3),
2688 (long) read_register (4),
2689 (long) read_register (5),
2690 (long) read_register (6),
2691 (long) read_register (7));
2692 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2693 (long) read_register (8),
2694 (long) read_register (9),
2695 (long) read_register (10),
2696 (long) read_register (11),
2697 (long) read_register (12),
2698 (long) read_register (13),
2699 (long) read_register (14),
2700 (long) read_register (15));
2701
2702 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
f81353e4
EZ		 2703 (long) read_register (tdep->A0G_REGNUM) & 0xff,
2704 (long) read_register (tdep->A0_REGNUM),
2705 (long) read_register (tdep->M0_REGNUM),
2706 (long) read_register (tdep->X0_REGNUM),
2707 (long) read_register (tdep->Y0_REGNUM),
2708 (long) read_register (tdep->RS_REGNUM),
2709 (long) read_register (tdep->MOD_REGNUM));
cc17453a 2710 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
f81353e4
EZ		 2711 (long) read_register (tdep->A1G_REGNUM) & 0xff,
2712 (long) read_register (tdep->A1_REGNUM),
2713 (long) read_register (tdep->M1_REGNUM),
2714 (long) read_register (tdep->X1_REGNUM),
2715 (long) read_register (tdep->Y1_REGNUM),
2716 (long) read_register (tdep->RE_REGNUM));
c906108c
SS		 2717}
2718
cc17453a 2719static void
fba45db2 2720sh4_show_regs (void)
cc17453a 2721{
f81353e4
EZ		 2722 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2723
2724 int pr = read_register (tdep->FPSCR_REGNUM) & 0x80000;
cc17453a
EZ		 2725 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2726 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 2727 (long) read_register (tdep->SR_REGNUM),
2728 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 2729 (long) read_register (MACH_REGNUM),
2730 (long) read_register (MACL_REGNUM));
2731
2732 printf_filtered ("GBR=%08lx VBR=%08lx",
2733 (long) read_register (GBR_REGNUM),
2734 (long) read_register (VBR_REGNUM));
2735 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 2736 (long) read_register (tdep->SSR_REGNUM),
2737 (long) read_register (tdep->SPC_REGNUM));
cc17453a 2738 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
f81353e4
EZ		 2739 (long) read_register (tdep->FPUL_REGNUM),
2740 (long) read_register (tdep->FPSCR_REGNUM));
cc17453a
EZ		 2741
2742 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2743 (long) read_register (0),
2744 (long) read_register (1),
2745 (long) read_register (2),
2746 (long) read_register (3),
2747 (long) read_register (4),
2748 (long) read_register (5),
2749 (long) read_register (6),
2750 (long) read_register (7));
2751 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2752 (long) read_register (8),
2753 (long) read_register (9),
2754 (long) read_register (10),
2755 (long) read_register (11),
2756 (long) read_register (12),
2757 (long) read_register (13),
2758 (long) read_register (14),
2759 (long) read_register (15));
2760
2761 printf_filtered ((pr
2762 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2763 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2764 (long) read_register (FP0_REGNUM + 0),
2765 (long) read_register (FP0_REGNUM + 1),
2766 (long) read_register (FP0_REGNUM + 2),
2767 (long) read_register (FP0_REGNUM + 3),
2768 (long) read_register (FP0_REGNUM + 4),
2769 (long) read_register (FP0_REGNUM + 5),
2770 (long) read_register (FP0_REGNUM + 6),
2771 (long) read_register (FP0_REGNUM + 7));
2772 printf_filtered ((pr
2773 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2774 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2775 (long) read_register (FP0_REGNUM + 8),
2776 (long) read_register (FP0_REGNUM + 9),
2777 (long) read_register (FP0_REGNUM + 10),
2778 (long) read_register (FP0_REGNUM + 11),
2779 (long) read_register (FP0_REGNUM + 12),
2780 (long) read_register (FP0_REGNUM + 13),
2781 (long) read_register (FP0_REGNUM + 14),
2782 (long) read_register (FP0_REGNUM + 15));
2783}
2784
2785static void
fba45db2 2786sh_dsp_show_regs (void)
cc17453a 2787{
f81353e4
EZ		 2788 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2789
cc17453a
EZ		 2790 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2791 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 2792 (long) read_register (tdep->SR_REGNUM),
2793 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 2794 (long) read_register (MACH_REGNUM),
2795 (long) read_register (MACL_REGNUM));
2796
2797 printf_filtered ("GBR=%08lx VBR=%08lx",
2798 (long) read_register (GBR_REGNUM),
2799 (long) read_register (VBR_REGNUM));
2800
2801 printf_filtered (" DSR=%08lx",
f81353e4 2802 (long) read_register (tdep->DSR_REGNUM));
cc17453a
EZ		 2803
2804 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2805 (long) read_register (0),
2806 (long) read_register (1),
2807 (long) read_register (2),
2808 (long) read_register (3),
2809 (long) read_register (4),
2810 (long) read_register (5),
2811 (long) read_register (6),
2812 (long) read_register (7));
2813 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2814 (long) read_register (8),
2815 (long) read_register (9),
2816 (long) read_register (10),
2817 (long) read_register (11),
2818 (long) read_register (12),
2819 (long) read_register (13),
2820 (long) read_register (14),
2821 (long) read_register (15));
2822
2823 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
f81353e4
EZ		 2824 (long) read_register (tdep->A0G_REGNUM) & 0xff,
2825 (long) read_register (tdep->A0_REGNUM),
2826 (long) read_register (tdep->M0_REGNUM),
2827 (long) read_register (tdep->X0_REGNUM),
2828 (long) read_register (tdep->Y0_REGNUM),
2829 (long) read_register (tdep->RS_REGNUM),
2830 (long) read_register (tdep->MOD_REGNUM));
cc17453a 2831 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
f81353e4
EZ		 2832 (long) read_register (tdep->A1G_REGNUM) & 0xff,
2833 (long) read_register (tdep->A1_REGNUM),
2834 (long) read_register (tdep->M1_REGNUM),
2835 (long) read_register (tdep->X1_REGNUM),
2836 (long) read_register (tdep->Y1_REGNUM),
2837 (long) read_register (tdep->RE_REGNUM));
cc17453a
EZ		 2838}
2839
283150cd
EZ		 2840static void
2841sh64_show_media_regs (void)
2842{
2843 int i;
2844 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2845
2846 printf_filtered ("PC=%s SR=%016llx \n",
2847 paddr (read_register (PC_REGNUM)),
2848 (long long) read_register (tdep->SR_REGNUM));
2849
2850 printf_filtered ("SSR=%016llx SPC=%016llx \n",
2851 (long long) read_register (tdep->SSR_REGNUM),
2852 (long long) read_register (tdep->SPC_REGNUM));
2853 printf_filtered ("FPSCR=%016lx\n ",
2854 (long) read_register (tdep->FPSCR_REGNUM));
2855
2856 for (i = 0; i < 64; i = i + 4)
2857 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
2858 i, i + 3,
2859 (long long) read_register (i + 0),
2860 (long long) read_register (i + 1),
2861 (long long) read_register (i + 2),
2862 (long long) read_register (i + 3));
2863
2864 printf_filtered ("\n");
2865
2866 for (i = 0; i < 64; i = i + 8)
2867 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2868 i, i + 7,
2869 (long) read_register (FP0_REGNUM + i + 0),
2870 (long) read_register (FP0_REGNUM + i + 1),
2871 (long) read_register (FP0_REGNUM + i + 2),
2872 (long) read_register (FP0_REGNUM + i + 3),
2873 (long) read_register (FP0_REGNUM + i + 4),
2874 (long) read_register (FP0_REGNUM + i + 5),
2875 (long) read_register (FP0_REGNUM + i + 6),
2876 (long) read_register (FP0_REGNUM + i + 7));
2877}
2878
2879static void
2880sh64_show_compact_regs (void)
2881{
2882 int i;
2883 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2884
2885 printf_filtered ("PC=%s \n",
2886 paddr (read_register (tdep->PC_C_REGNUM)));
2887
2888 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
2889 (long) read_register (tdep->GBR_C_REGNUM),
2890 (long) read_register (tdep->MACH_C_REGNUM),
2891 (long) read_register (tdep->MACL_C_REGNUM),
2892 (long) read_register (tdep->PR_C_REGNUM),
2893 (long) read_register (tdep->T_C_REGNUM));
2894 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
2895 (long) read_register (tdep->FPSCR_REGNUM),
2896 (long) read_register (tdep->FPUL_REGNUM));
2897
2898 for (i = 0; i < 16; i = i + 4)
2899 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
2900 i, i + 3,
2901 (long) read_register (i + 0),
2902 (long) read_register (i + 1),
2903 (long) read_register (i + 2),
2904 (long) read_register (i + 3));
2905
2906 printf_filtered ("\n");
2907
2908 for (i = 0; i < 16; i = i + 8)
2909 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2910 i, i + 7,
2911 (long) read_register (FP0_REGNUM + i + 0),
2912 (long) read_register (FP0_REGNUM + i + 1),
2913 (long) read_register (FP0_REGNUM + i + 2),
2914 (long) read_register (FP0_REGNUM + i + 3),
2915 (long) read_register (FP0_REGNUM + i + 4),
2916 (long) read_register (FP0_REGNUM + i + 5),
2917 (long) read_register (FP0_REGNUM + i + 6),
2918 (long) read_register (FP0_REGNUM + i + 7));
2919}
2920
2921/*FIXME!!! This only shows the registers for shmedia, excluding the
2922 pseudo registers. */
2923static void
2924sh64_show_regs (void)
2925{
2926 if (pc_is_isa32 (selected_frame->pc))
2927 sh64_show_media_regs ();
2928 else
2929 sh64_show_compact_regs ();
2930}
2931
53116e27
EZ		 2932void sh_show_regs_command (char *args, int from_tty)
2933{
2934 if (sh_show_regs)
2935 (*sh_show_regs)();
2936}
2937
cc17453a
EZ		 2938/* Index within `registers' of the first byte of the space for
2939 register N. */
2940static int
fba45db2 2941sh_default_register_byte (int reg_nr)
8db62801 2942{
cc17453a
EZ		 2943 return (reg_nr * 4);
2944}
2945
53116e27 2946static int
fba45db2 2947sh_sh4_register_byte (int reg_nr)
53116e27 2948{
f81353e4
EZ		 2949 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2950
2951 if (reg_nr >= tdep->DR0_REGNUM
2952 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27 2953 return (dr_reg_base_num (reg_nr) * 4);
f81353e4
EZ		 2954 else if (reg_nr >= tdep->FV0_REGNUM
2955 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 2956 return (fv_reg_base_num (reg_nr) * 4);
2957 else
2958 return (reg_nr * 4);
2959}
2960
283150cd
EZ		 2961/* *INDENT-OFF* */
2962/*
2963 SH MEDIA MODE (ISA 32)
2964 general registers (64-bit) 0-63
29650 r0, r1, r2, r3, r4, r5, r6, r7,
296664 r8, r9, r10, r11, r12, r13, r14, r15,
2967128 r16, r17, r18, r19, r20, r21, r22, r23,
2968192 r24, r25, r26, r27, r28, r29, r30, r31,
2969256 r32, r33, r34, r35, r36, r37, r38, r39,
2970320 r40, r41, r42, r43, r44, r45, r46, r47,
2971384 r48, r49, r50, r51, r52, r53, r54, r55,
2972448 r56, r57, r58, r59, r60, r61, r62, r63,
2973
2974 pc (64-bit) 64
2975512 pc,
2976
2977 status reg., saved status reg., saved pc reg. (64-bit) 65-67
2978520 sr, ssr, spc,
2979
2980 target registers (64-bit) 68-75
2981544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
2982
2983 floating point state control register (32-bit) 76
2984608 fpscr,
2985
2986 single precision floating point registers (32-bit) 77-140
2987612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
2988644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
2989676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
2990708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
2991740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
2992772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
2993804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
2994836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
2995
2996TOTAL SPACE FOR REGISTERS: 868 bytes
2997
2998From here on they are all pseudo registers: no memory allocated.
2999REGISTER_BYTE returns the register byte for the base register.
3000
3001 double precision registers (pseudo) 141-172
3002 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
3003 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
3004 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
3005 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
3006
3007 floating point pairs (pseudo) 173-204
3008 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
3009 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
3010 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
3011 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
3012
3013 floating point vectors (4 floating point regs) (pseudo) 205-220
3014 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
3015 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
3016
3017 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
3018 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
3019 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
3020 pc_c,
3021 gbr_c, mach_c, macl_c, pr_c, t_c,
3022 fpscr_c, fpul_c,
3023 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
3024 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
3025 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
3026 fv0_c, fv4_c, fv8_c, fv12_c
3027*/
3028/* *INDENT-ON* */
3029static int
3030sh_sh64_register_byte (int reg_nr)
3031{
3032 int base_regnum = -1;
3033 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3034
3035 /* If it is a pseudo register, get the number of the first floating
3036 point register that is part of it. */
3037 if (reg_nr >= tdep->DR0_REGNUM
3038 && reg_nr <= tdep->DR_LAST_REGNUM)
3039 base_regnum = dr_reg_base_num (reg_nr);
3040
3041 else if (reg_nr >= tdep->FPP0_REGNUM
3042 && reg_nr <= tdep->FPP_LAST_REGNUM)
3043 base_regnum = fpp_reg_base_num (reg_nr);
3044
3045 else if (reg_nr >= tdep->FV0_REGNUM
3046 && reg_nr <= tdep->FV_LAST_REGNUM)
3047 base_regnum = fv_reg_base_num (reg_nr);
3048
3049 /* sh compact pseudo register. FPSCR is a pathological case, need to
3050 treat it as special. */
3051 else if ((reg_nr >= tdep->R0_C_REGNUM
3052 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3053 && reg_nr != tdep->FPSCR_C_REGNUM)
3054 base_regnum = sh64_compact_reg_base_num (reg_nr);
3055
3056 /* Now return the offset in bytes within the register cache. */
3057 /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
3058 if (reg_nr >= tdep->DR0_REGNUM
3059 && reg_nr <= tdep->FV_LAST_REGNUM)
3060 return (base_regnum - FP0_REGNUM + 1) * 4
3061 + (tdep->TR7_REGNUM + 1) * 8;
3062
3063 /* sh compact pseudo register: general register */
3064 if ((reg_nr >= tdep->R0_C_REGNUM
3065 && reg_nr <= tdep->R_LAST_C_REGNUM))
3066 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3067 ? base_regnum * 8 + 4
3068 : base_regnum * 8);
3069
3070 /* sh compact pseudo register: */
3071 if (reg_nr == tdep->PC_C_REGNUM
3072 || reg_nr == tdep->GBR_C_REGNUM
3073 || reg_nr == tdep->MACL_C_REGNUM
3074 || reg_nr == tdep->PR_C_REGNUM)
3075 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3076 ? base_regnum * 8 + 4
3077 : base_regnum * 8);
3078
3079 if (reg_nr == tdep->MACH_C_REGNUM)
3080 return base_regnum * 8;
3081
3082 if (reg_nr == tdep->T_C_REGNUM)
3083 return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */
3084
3085 /* sh compact pseudo register: floating point register */
3086 else if (reg_nr >=tdep->FP0_C_REGNUM
3087 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3088 return (base_regnum - FP0_REGNUM) * 4
3089 + (tdep->TR7_REGNUM + 1) * 8 + 4;
3090
3091 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3092 /* This is complicated, for now return the beginning of the
3093 architectural FPSCR register. */
3094 return (tdep->TR7_REGNUM + 1) * 8;
3095
3096 else if (reg_nr == tdep->FPUL_C_REGNUM)
3097 return ((base_regnum - FP0_REGNUM) * 4 +
3098 (tdep->TR7_REGNUM + 1) * 8 + 4);
3099
3100 /* It is not a pseudo register. */
3101 /* It is a 64 bit register. */
3102 else if (reg_nr <= tdep->TR7_REGNUM)
3103 return reg_nr * 8;
3104
3105 /* It is a 32 bit register. */
3106 else
3107 if (reg_nr == tdep->FPSCR_REGNUM)
3108 return (tdep->FPSCR_REGNUM * 8);
3109
3110 /* It is floating point 32-bit register */
3111 else
3112 return ((tdep->TR7_REGNUM + 1) * 8
3113 + (reg_nr - FP0_REGNUM + 1) * 4);
3114}
3115
cc17453a
EZ		 3116/* Number of bytes of storage in the actual machine representation for
3117 register REG_NR. */
3118static int
fba45db2 3119sh_default_register_raw_size (int reg_nr)
cc17453a
EZ		 3120{
3121 return 4;
3122}
3123
53116e27 3124static int
fba45db2 3125sh_sh4_register_raw_size (int reg_nr)
53116e27 3126{
f81353e4
EZ		 3127 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3128
3129 if (reg_nr >= tdep->DR0_REGNUM
3130 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27 3131 return 8;
f81353e4
EZ		 3132 else if (reg_nr >= tdep->FV0_REGNUM
3133 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 3134 return 16;
3135 else
3136 return 4;
3137}
3138
283150cd
EZ		 3139static int
3140sh_sh64_register_raw_size (int reg_nr)
3141{
3142 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3143
3144 if ((reg_nr >= tdep->DR0_REGNUM
3145 && reg_nr <= tdep->DR_LAST_REGNUM)
3146 || (reg_nr >= tdep->FPP0_REGNUM
3147 && reg_nr <= tdep->FPP_LAST_REGNUM)
3148 || (reg_nr >= tdep->DR0_C_REGNUM
3149 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3150 || (reg_nr <= tdep->TR7_REGNUM))
3151 return 8;
3152
3153 else if ((reg_nr >= tdep->FV0_REGNUM
3154 && reg_nr <= tdep->FV_LAST_REGNUM)
3155 || (reg_nr >= tdep->FV0_C_REGNUM
3156 && reg_nr <= tdep->FV_LAST_C_REGNUM))
3157 return 16;
3158
3159 else /* this covers also the 32-bit SH compact registers. */
3160 return 4;
3161}
3162
cc17453a
EZ		 3163/* Number of bytes of storage in the program's representation
3164 for register N. */
3165static int
fba45db2 3166sh_register_virtual_size (int reg_nr)
cc17453a
EZ		 3167{
3168 return 4;
3169}
3170
283150cd
EZ		 3171/* ??????? FIXME */
3172static int
3173sh_sh64_register_virtual_size (int reg_nr)
3174{
3175 if (reg_nr >= FP0_REGNUM
3176 && reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM)
3177 return 4;
3178 else
3179 return 8;
3180}
3181
cc17453a
EZ		 3182/* Return the GDB type object for the "standard" data type
3183 of data in register N. */
cc17453a 3184static struct type *
fba45db2 3185sh_sh3e_register_virtual_type (int reg_nr)
cc17453a 3186{
f81353e4
EZ		 3187 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3188
cc17453a 3189 if ((reg_nr >= FP0_REGNUM
f81353e4
EZ		 3190 && (reg_nr <= tdep->FP_LAST_REGNUM))
3191 || (reg_nr == tdep->FPUL_REGNUM))
cc17453a 3192 return builtin_type_float;
8db62801 3193 else
cc17453a
EZ		 3194 return builtin_type_int;
3195}
3196
7f4dbe94
EZ		 3197static struct type *
3198sh_sh4_build_float_register_type (int high)
3199{
3200 struct type *temp;
3201
3202 temp = create_range_type (NULL, builtin_type_int, 0, high);
3203 return create_array_type (NULL, builtin_type_float, temp);
3204}
3205
53116e27 3206static struct type *
fba45db2 3207sh_sh4_register_virtual_type (int reg_nr)
53116e27 3208{
f81353e4
EZ		 3209 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3210
53116e27 3211 if ((reg_nr >= FP0_REGNUM
f81353e4
EZ		 3212 && (reg_nr <= tdep->FP_LAST_REGNUM))
3213 || (reg_nr == tdep->FPUL_REGNUM))
53116e27 3214 return builtin_type_float;
f81353e4
EZ		 3215 else if (reg_nr >= tdep->DR0_REGNUM
3216 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27 3217 return builtin_type_double;
f81353e4
EZ		 3218 else if (reg_nr >= tdep->FV0_REGNUM
3219 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 3220 return sh_sh4_build_float_register_type (3);
3221 else
3222 return builtin_type_int;
3223}
3224
283150cd
EZ		 3225static struct type *
3226sh_sh64_register_virtual_type (int reg_nr)
3227{
3228 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3229
3230 if ((reg_nr >= FP0_REGNUM
3231 && reg_nr <= tdep->FP_LAST_REGNUM)
3232 || (reg_nr >= tdep->FP0_C_REGNUM
3233 && reg_nr <= tdep->FP_LAST_C_REGNUM))
3234 return builtin_type_float;
3235 else if ((reg_nr >= tdep->DR0_REGNUM
3236 && reg_nr <= tdep->DR_LAST_REGNUM)
3237 || (reg_nr >= tdep->DR0_C_REGNUM
3238 && reg_nr <= tdep->DR_LAST_C_REGNUM))
3239 return builtin_type_double;
3240 else if (reg_nr >= tdep->FPP0_REGNUM
3241 && reg_nr <= tdep->FPP_LAST_REGNUM)
3242 return sh_sh4_build_float_register_type (1);
3243 else if ((reg_nr >= tdep->FV0_REGNUM
3244 && reg_nr <= tdep->FV_LAST_REGNUM)
3245 ||(reg_nr >= tdep->FV0_C_REGNUM
3246 && reg_nr <= tdep->FV_LAST_C_REGNUM))
3247 return sh_sh4_build_float_register_type (3);
3248 else if (reg_nr == tdep->FPSCR_REGNUM)
3249 return builtin_type_int;
3250 else if (reg_nr >= tdep->R0_C_REGNUM
3251 && reg_nr < tdep->FP0_C_REGNUM)
3252 return builtin_type_int;
3253 else
3254 return builtin_type_long_long;
3255}
3256
cc17453a 3257static struct type *
fba45db2 3258sh_default_register_virtual_type (int reg_nr)
cc17453a
EZ		 3259{
3260 return builtin_type_int;
3261}
3262
fb409745
EZ		 3263/* On the sh4, the DRi pseudo registers are problematic if the target
3264 is little endian. When the user writes one of those registers, for
3265 instance with 'ser var $dr0=1', we want the double to be stored
3266 like this:
3267 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3268 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3269
3270 This corresponds to little endian byte order & big endian word
3271 order. However if we let gdb write the register w/o conversion, it
3272 will write fr0 and fr1 this way:
3273 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3274 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3275 because it will consider fr0 and fr1 as a single LE stretch of memory.
3276
3277 To achieve what we want we must force gdb to store things in
3278 floatformat_ieee_double_littlebyte_bigword (which is defined in
3279 include/floatformat.h and libiberty/floatformat.c.
3280
3281 In case the target is big endian, there is no problem, the
3282 raw bytes will look like:
3283 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
3284 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3285
3286 The other pseudo registers (the FVs) also don't pose a problem
3287 because they are stored as 4 individual FP elements. */
3288
7bd872fe 3289static void
fb409745
EZ		 3290sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
3291 char *from, char *to)
3292{
f81353e4
EZ		 3293 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3294
3295 if (regnum >= tdep->DR0_REGNUM
3296 && regnum <= tdep->DR_LAST_REGNUM)
fb409745
EZ		 3297 {
3298 DOUBLEST val;
3299 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
3bbfbb92 3300 store_floating (to, TYPE_LENGTH (type), val);
fb409745
EZ		 3301 }
3302 else
3bbfbb92 3303 error ("sh_register_convert_to_virtual called with non DR register number");
fb409745
EZ		 3304}
3305
283150cd
EZ		 3306void
3307sh_sh64_register_convert_to_virtual (int regnum, struct type *type,
3308 char *from, char *to)
3309{
3310 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3311
3312 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
3313 {
3314 /* It is a no-op. */
3315 memcpy (to, from, REGISTER_RAW_SIZE (regnum));
3316 return;
3317 }
3318
3319 if ((regnum >= tdep->DR0_REGNUM
3320 && regnum <= tdep->DR_LAST_REGNUM)
3321 || (regnum >= tdep->DR0_C_REGNUM
3322 && regnum <= tdep->DR_LAST_C_REGNUM))
3323 {
3324 DOUBLEST val;
3325 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
3326 store_floating(to, TYPE_LENGTH(type), val);
3327 }
3328 else
3329 error("sh_register_convert_to_virtual called with non DR register number");
3330}
3331
3332static void
3333sh_sh4_register_convert_to_raw (struct type *type, int regnum,
d8124050 3334 const void *from, void *to)
283150cd
EZ		 3335{
3336 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3337
3338 if (regnum >= tdep->DR0_REGNUM
3339 && regnum <= tdep->DR_LAST_REGNUM)
3340 {
3341 DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
3342 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
3343 }
3344 else
3345 error("sh_register_convert_to_raw called with non DR register number");
3346}
3347
3348void
3349sh_sh64_register_convert_to_raw (struct type *type, int regnum,
d8124050 3350 const void *from, void *to)
fb409745 3351{
f81353e4
EZ		 3352 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3353
283150cd
EZ		 3354 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
3355 {
3356 /* It is a no-op. */
3357 memcpy (to, from, REGISTER_RAW_SIZE (regnum));
3358 return;
3359 }
3360
3361 if ((regnum >= tdep->DR0_REGNUM
3362 && regnum <= tdep->DR_LAST_REGNUM)
3363 || (regnum >= tdep->DR0_C_REGNUM
3364 && regnum <= tdep->DR_LAST_C_REGNUM))
fb409745
EZ		 3365 {
3366 DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
3367 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
3368 }
3369 else
3370 error("sh_register_convert_to_raw called with non DR register number");
3371}
3372
53116e27 3373void
d8124050
AC		 3374sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
3375 int reg_nr, void *buffer)
53116e27
EZ		 3376{
3377 int base_regnum, portion;
7bd872fe 3378 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
d8124050 3379 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
53116e27 3380
7bd872fe
EZ		 3381 if (reg_nr >= tdep->DR0_REGNUM
3382 && reg_nr <= tdep->DR_LAST_REGNUM)
3383 {
3384 base_regnum = dr_reg_base_num (reg_nr);
3385
3386 /* Build the value in the provided buffer. */
3387 /* Read the real regs for which this one is an alias. */
3388 for (portion = 0; portion < 2; portion++)
d8124050 3389 regcache_raw_read (regcache, base_regnum + portion,
0818c12a
AC		 3390 (temp_buffer
3391 + REGISTER_RAW_SIZE (base_regnum) * portion));
7bd872fe
EZ		 3392 /* We must pay attention to the endiannes. */
3393 sh_sh4_register_convert_to_virtual (reg_nr,
3394 REGISTER_VIRTUAL_TYPE (reg_nr),
3395 temp_buffer, buffer);
3396 }
3397 else if (reg_nr >= tdep->FV0_REGNUM
3398 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27 3399 {
7bd872fe
EZ		 3400 base_regnum = fv_reg_base_num (reg_nr);
3401
3402 /* Read the real regs for which this one is an alias. */
3403 for (portion = 0; portion < 4; portion++)
d8124050
AC		 3404 regcache_raw_read (regcache, base_regnum + portion,
3405 ((char *) buffer
3406 + REGISTER_RAW_SIZE (base_regnum) * portion));
53116e27
EZ		 3407 }
3408}
3409
7bd872fe 3410static void
d8124050
AC		 3411sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
3412 int reg_nr, void *buffer)
283150cd
EZ		 3413{
3414 int base_regnum;
3415 int portion;
3416 int offset = 0;
3417 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
d8124050 3418 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
283150cd
EZ		 3419
3420 if (reg_nr >= tdep->DR0_REGNUM
3421 && reg_nr <= tdep->DR_LAST_REGNUM)
3422 {
3423 base_regnum = dr_reg_base_num (reg_nr);
3424
3425 /* Build the value in the provided buffer. */
3426 /* DR regs are double precision registers obtained by
3427 concatenating 2 single precision floating point registers. */
3428 for (portion = 0; portion < 2; portion++)
d8124050 3429 regcache_raw_read (regcache, base_regnum + portion,
0818c12a
AC		 3430 (temp_buffer
3431 + REGISTER_RAW_SIZE (base_regnum) * portion));
283150cd
EZ		 3432
3433 /* We must pay attention to the endiannes. */
3434 sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr),
3435 temp_buffer, buffer);
3436
3437 }
3438
3439 else if (reg_nr >= tdep->FPP0_REGNUM
3440 && reg_nr <= tdep->FPP_LAST_REGNUM)
3441 {
3442 base_regnum = fpp_reg_base_num (reg_nr);
3443
3444 /* Build the value in the provided buffer. */
3445 /* FPP regs are pairs of single precision registers obtained by
3446 concatenating 2 single precision floating point registers. */
3447 for (portion = 0; portion < 2; portion++)
d8124050
AC		 3448 regcache_raw_read (regcache, base_regnum + portion,
3449 ((char *) buffer
0818c12a 3450 + REGISTER_RAW_SIZE (base_regnum) * portion));
283150cd
EZ		 3451 }
3452
3453 else if (reg_nr >= tdep->FV0_REGNUM
3454 && reg_nr <= tdep->FV_LAST_REGNUM)
3455 {
3456 base_regnum = fv_reg_base_num (reg_nr);
3457
3458 /* Build the value in the provided buffer. */
3459 /* FV regs are vectors of single precision registers obtained by
3460 concatenating 4 single precision floating point registers. */
3461 for (portion = 0; portion < 4; portion++)
d8124050
AC		 3462 regcache_raw_read (regcache, base_regnum + portion,
3463 ((char *) buffer
0818c12a 3464 + REGISTER_RAW_SIZE (base_regnum) * portion));
283150cd
EZ		 3465 }
3466
3467 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
3468 else if (reg_nr >= tdep->R0_C_REGNUM
3469 && reg_nr <= tdep->T_C_REGNUM)
3470 {
3471 base_regnum = sh64_compact_reg_base_num (reg_nr);
3472
3473 /* Build the value in the provided buffer. */
d8124050 3474 regcache_raw_read (regcache, base_regnum, temp_buffer);
283150cd
EZ		 3475 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3476 offset = 4;
3477 memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/
3478 }
3479
3480 else if (reg_nr >= tdep->FP0_C_REGNUM
3481 && reg_nr <= tdep->FP_LAST_C_REGNUM)
3482 {
3483 base_regnum = sh64_compact_reg_base_num (reg_nr);
3484
3485 /* Build the value in the provided buffer. */
3486 /* Floating point registers map 1-1 to the media fp regs,
3487 they have the same size and endienness. */
d8124050 3488 regcache_raw_read (regcache, base_regnum, buffer);
283150cd
EZ		 3489 }
3490
3491 else if (reg_nr >= tdep->DR0_C_REGNUM
3492 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3493 {
3494 base_regnum = sh64_compact_reg_base_num (reg_nr);
3495
3496 /* DR_C regs are double precision registers obtained by
3497 concatenating 2 single precision floating point registers. */
3498 for (portion = 0; portion < 2; portion++)
d8124050 3499 regcache_raw_read (regcache, base_regnum + portion,
0818c12a
AC		 3500 (temp_buffer
3501 + REGISTER_RAW_SIZE (base_regnum) * portion));
283150cd
EZ		 3502
3503 /* We must pay attention to the endiannes. */
3504 sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr),
3505 temp_buffer, buffer);
3506 }
3507
3508 else if (reg_nr >= tdep->FV0_C_REGNUM
3509 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3510 {
3511 base_regnum = sh64_compact_reg_base_num (reg_nr);
3512
3513 /* Build the value in the provided buffer. */
3514 /* FV_C regs are vectors of single precision registers obtained by
3515 concatenating 4 single precision floating point registers. */
3516 for (portion = 0; portion < 4; portion++)
d8124050
AC		 3517 regcache_raw_read (regcache, base_regnum + portion,
3518 ((char *) buffer
0818c12a 3519 + REGISTER_RAW_SIZE (base_regnum) * portion));
283150cd
EZ		 3520 }
3521
3522 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3523 {
3524 int fpscr_base_regnum;
3525 int sr_base_regnum;
3526 unsigned int fpscr_value;
3527 unsigned int sr_value;
3528 unsigned int fpscr_c_value;
3529 unsigned int fpscr_c_part1_value;
3530 unsigned int fpscr_c_part2_value;
3531
3532 fpscr_base_regnum = tdep->FPSCR_REGNUM;
3533 sr_base_regnum = tdep->SR_REGNUM;
3534
3535 /* Build the value in the provided buffer. */
3536 /* FPSCR_C is a very weird register that contains sparse bits
3537 from the FPSCR and the SR architectural registers.
3538 Specifically: */
3539 /* *INDENT-OFF* */
3540 /*
3541 FPSRC_C bit
3542 0 Bit 0 of FPSCR
3543 1 reserved
3544 2-17 Bit 2-18 of FPSCR
3545 18-20 Bits 12,13,14 of SR
3546 21-31 reserved
3547 */
3548 /* *INDENT-ON* */
3549 /* Get FPSCR into a local buffer */
d8124050 3550 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
283150cd
EZ		 3551 /* Get value as an int. */
3552 fpscr_value = extract_unsigned_integer (temp_buffer, 4);
3553 /* Get SR into a local buffer */
d8124050 3554 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
283150cd
EZ		 3555 /* Get value as an int. */
3556 sr_value = extract_unsigned_integer (temp_buffer, 4);
3557 /* Build the new value. */
3558 fpscr_c_part1_value = fpscr_value & 0x3fffd;
3559 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
3560 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
3561 /* Store that in out buffer!!! */
3562 store_unsigned_integer (buffer, 4, fpscr_c_value);
3563 /* FIXME There is surely an endianness gotcha here. */
3564 }
3565
3566 else if (reg_nr == tdep->FPUL_C_REGNUM)
3567 {
3568 base_regnum = sh64_compact_reg_base_num (reg_nr);
3569
3570 /* FPUL_C register is floating point register 32,
3571 same size, same endianness. */
d8124050 3572 regcache_raw_read (regcache, base_regnum, buffer);
283150cd
EZ		 3573 }
3574}
3575
53116e27 3576void
d8124050
AC		 3577sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3578 int reg_nr, const void *buffer)
53116e27
EZ		 3579{
3580 int base_regnum, portion;
7bd872fe 3581 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
d8124050 3582 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
53116e27 3583
f81353e4
EZ		 3584 if (reg_nr >= tdep->DR0_REGNUM
3585 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27
EZ		 3586 {
3587 base_regnum = dr_reg_base_num (reg_nr);
3588
7bd872fe
EZ		 3589 /* We must pay attention to the endiannes. */
3590 sh_sh4_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3591 buffer, temp_buffer);
3592
53116e27
EZ		 3593 /* Write the real regs for which this one is an alias. */
3594 for (portion = 0; portion < 2; portion++)
d8124050 3595 regcache_raw_write (regcache, base_regnum + portion,
0818c12a
AC		 3596 (temp_buffer
3597 + REGISTER_RAW_SIZE (base_regnum) * portion));
53116e27 3598 }
f81353e4
EZ		 3599 else if (reg_nr >= tdep->FV0_REGNUM
3600 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 3601 {
3602 base_regnum = fv_reg_base_num (reg_nr);
3603
3604 /* Write the real regs for which this one is an alias. */
3605 for (portion = 0; portion < 4; portion++)
d8124050
AC		 3606 regcache_raw_write (regcache, base_regnum + portion,
3607 ((char *) buffer
0818c12a 3608 + REGISTER_RAW_SIZE (base_regnum) * portion));
53116e27
EZ		 3609 }
3610}
3611
283150cd 3612void
d8124050
AC		 3613sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3614 int reg_nr, const void *buffer)
283150cd
EZ		 3615{
3616 int base_regnum, portion;
3617 int offset;
3618 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
d8124050 3619 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
283150cd
EZ		 3620
3621 if (reg_nr >= tdep->DR0_REGNUM
3622 && reg_nr <= tdep->DR_LAST_REGNUM)
3623 {
3624 base_regnum = dr_reg_base_num (reg_nr);
3625 /* We must pay attention to the endiannes. */
3626 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3627 buffer, temp_buffer);
3628
3629
3630 /* Write the real regs for which this one is an alias. */
3631 for (portion = 0; portion < 2; portion++)
d8124050 3632 regcache_raw_write (regcache, base_regnum + portion,
0818c12a
AC		 3633 (temp_buffer
3634 + REGISTER_RAW_SIZE (base_regnum) * portion));
283150cd
EZ		 3635 }
3636
3637 else if (reg_nr >= tdep->FPP0_REGNUM
3638 && reg_nr <= tdep->FPP_LAST_REGNUM)
3639 {
3640 base_regnum = fpp_reg_base_num (reg_nr);
3641
3642 /* Write the real regs for which this one is an alias. */
3643 for (portion = 0; portion < 2; portion++)
d8124050
AC		 3644 regcache_raw_write (regcache, base_regnum + portion,
3645 ((char *) buffer
0818c12a 3646 + REGISTER_RAW_SIZE (base_regnum) * portion));
283150cd
EZ		 3647 }
3648
3649 else if (reg_nr >= tdep->FV0_REGNUM
3650 && reg_nr <= tdep->FV_LAST_REGNUM)
3651 {
3652 base_regnum = fv_reg_base_num (reg_nr);
3653
3654 /* Write the real regs for which this one is an alias. */
3655 for (portion = 0; portion < 4; portion++)
d8124050
AC		 3656 regcache_raw_write (regcache, base_regnum + portion,
3657 ((char *) buffer
0818c12a 3658 + REGISTER_RAW_SIZE (base_regnum) * portion));
283150cd
EZ		 3659 }
3660
3661 /* sh compact general pseudo registers. 1-to-1 with a shmedia
3662 register but only 4 bytes of it. */
3663 else if (reg_nr >= tdep->R0_C_REGNUM
3664 && reg_nr <= tdep->T_C_REGNUM)
3665 {
3666 base_regnum = sh64_compact_reg_base_num (reg_nr);
3667 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
3668 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3669 offset = 4;
3670 else
3671 offset = 0;
3672 /* Let's read the value of the base register into a temporary
3673 buffer, so that overwriting the last four bytes with the new
3674 value of the pseudo will leave the upper 4 bytes unchanged. */
d8124050 3675 regcache_raw_read (regcache, base_regnum, temp_buffer);
283150cd
EZ		 3676 /* Write as an 8 byte quantity */
3677 memcpy (temp_buffer + offset, buffer, 4);
d8124050 3678 regcache_raw_write (regcache, base_regnum, temp_buffer);
283150cd
EZ		 3679 }
3680
3681 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
3682 registers. Both are 4 bytes. */
3683 else if (reg_nr >= tdep->FP0_C_REGNUM
3684 && reg_nr <= tdep->FP_LAST_C_REGNUM)
3685 {
3686 base_regnum = sh64_compact_reg_base_num (reg_nr);
d8124050 3687 regcache_raw_write (regcache, base_regnum, buffer);
283150cd
EZ		 3688 }
3689
3690 else if (reg_nr >= tdep->DR0_C_REGNUM
3691 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3692 {
3693 base_regnum = sh64_compact_reg_base_num (reg_nr);
3694 for (portion = 0; portion < 2; portion++)
3695 {
3696 /* We must pay attention to the endiannes. */
3697 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3698 buffer, temp_buffer);
3699
d8124050 3700 regcache_raw_write (regcache, base_regnum + portion,
0818c12a
AC		 3701 (temp_buffer
3702 + REGISTER_RAW_SIZE (base_regnum) * portion));
283150cd
EZ		 3703 }
3704 }
3705
3706 else if (reg_nr >= tdep->FV0_C_REGNUM
3707 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3708 {
3709 base_regnum = sh64_compact_reg_base_num (reg_nr);
3710
3711 for (portion = 0; portion < 4; portion++)
3712 {
d8124050
AC		 3713 regcache_raw_write (regcache, base_regnum + portion,
3714 ((char *) buffer
0818c12a 3715 + REGISTER_RAW_SIZE (base_regnum) * portion));
283150cd
EZ		 3716 }
3717 }
3718
3719 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3720 {
3721 int fpscr_base_regnum;
3722 int sr_base_regnum;
3723 unsigned int fpscr_value;
3724 unsigned int sr_value;
3725 unsigned int old_fpscr_value;
3726 unsigned int old_sr_value;
3727 unsigned int fpscr_c_value;
3728 unsigned int fpscr_mask;
3729 unsigned int sr_mask;
3730
3731 fpscr_base_regnum = tdep->FPSCR_REGNUM;
3732 sr_base_regnum = tdep->SR_REGNUM;
3733
3734 /* FPSCR_C is a very weird register that contains sparse bits
3735 from the FPSCR and the SR architectural registers.
3736 Specifically: */
3737 /* *INDENT-OFF* */
3738 /*
3739 FPSRC_C bit
3740 0 Bit 0 of FPSCR
3741 1 reserved
3742 2-17 Bit 2-18 of FPSCR
3743 18-20 Bits 12,13,14 of SR
3744 21-31 reserved
3745 */
3746 /* *INDENT-ON* */
3747 /* Get value as an int. */
3748 fpscr_c_value = extract_unsigned_integer (buffer, 4);
3749
3750 /* Build the new values. */
3751 fpscr_mask = 0x0003fffd;
3752 sr_mask = 0x001c0000;
3753
3754 fpscr_value = fpscr_c_value & fpscr_mask;
3755 sr_value = (fpscr_value & sr_mask) >> 6;
3756
d8124050 3757 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
283150cd
EZ		 3758 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4);
3759 old_fpscr_value &= 0xfffc0002;
3760 fpscr_value |= old_fpscr_value;
3761 store_unsigned_integer (temp_buffer, 4, fpscr_value);
d8124050 3762 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
283150cd 3763
d8124050 3764 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
283150cd
EZ		 3765 old_sr_value = extract_unsigned_integer (temp_buffer, 4);
3766 old_sr_value &= 0xffff8fff;
3767 sr_value |= old_sr_value;
3768 store_unsigned_integer (temp_buffer, 4, sr_value);
d8124050 3769 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
283150cd
EZ		 3770 }
3771
3772 else if (reg_nr == tdep->FPUL_C_REGNUM)
3773 {
3774 base_regnum = sh64_compact_reg_base_num (reg_nr);
d8124050 3775 regcache_raw_write (regcache, base_regnum, buffer);
283150cd
EZ		 3776 }
3777}
3778
3bbfbb92 3779/* Floating point vector of 4 float registers. */
53116e27
EZ		 3780static void
3781do_fv_register_info (int fv_regnum)
3782{
3783 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
3784 printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3785 fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM,
3786 (int) read_register (first_fp_reg_num),
3787 (int) read_register (first_fp_reg_num + 1),
3788 (int) read_register (first_fp_reg_num + 2),
3789 (int) read_register (first_fp_reg_num + 3));
3790}
3791
283150cd
EZ		 3792/* Floating point vector of 4 float registers, compact mode. */
3793static void
3794do_fv_c_register_info (int fv_regnum)
3795{
3796 int first_fp_reg_num = sh64_compact_reg_base_num (fv_regnum);
3797 printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3798 fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_C_REGNUM,
3799 (int) read_register (first_fp_reg_num),
3800 (int) read_register (first_fp_reg_num + 1),
3801 (int) read_register (first_fp_reg_num + 2),
3802 (int) read_register (first_fp_reg_num + 3));
3803}
3804
3805/* Pairs of single regs. The DR are instead double precision
3806 registers. */
3807static void
3808do_fpp_register_info (int fpp_regnum)
3809{
3810 int first_fp_reg_num = fpp_reg_base_num (fpp_regnum);
3811
3812 printf_filtered ("fpp%d\t0x%08x\t0x%08x\n",
3813 fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM,
3814 (int) read_register (first_fp_reg_num),
3815 (int) read_register (first_fp_reg_num + 1));
3816}
3817
3bbfbb92 3818/* Double precision registers. */
53116e27
EZ		 3819static void
3820do_dr_register_info (int dr_regnum)
3821{
3822 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
3823
3824 printf_filtered ("dr%d\t0x%08x%08x\n",
3825 dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM,
3826 (int) read_register (first_fp_reg_num),
3827 (int) read_register (first_fp_reg_num + 1));
3828}
3829
283150cd
EZ		 3830/* Double precision registers, compact mode. */
3831static void
3832do_dr_c_register_info (int dr_regnum)
3833{
3834 int first_fp_reg_num = sh64_compact_reg_base_num (dr_regnum);
3835
3836 printf_filtered ("dr%d_c\t0x%08x%08x\n",
3837 dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_C_REGNUM,
3838 (int) read_register (first_fp_reg_num),
3839 (int) read_register (first_fp_reg_num +1));
3840}
3841
3842/* General register in compact mode. */
3843static void
3844do_r_c_register_info (int r_c_regnum)
3845{
3846 int regnum = sh64_compact_reg_base_num (r_c_regnum);
3847
3848 printf_filtered ("r%d_c\t0x%08x\n",
3849 r_c_regnum - gdbarch_tdep (current_gdbarch)->R0_C_REGNUM,
3850 /*FIXME!!!*/ (int) read_register (regnum));
3851}
3852
3853/* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
3854 shmedia REGISTERS. */
3855/* Control registers, compact mode. */
3856static void
3857do_cr_c_register_info (int cr_c_regnum)
3858{
3859 switch (cr_c_regnum)
3860 {
3861 case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3862 break;
3863 case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3864 break;
3865 case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3866 break;
3867 case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3868 break;
3869 case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3870 break;
3871 case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3872 break;
3873 case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3874 break;
3875 case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum));
3876 break;
3877 }
3878}
3879
53116e27
EZ		 3880static void
3881sh_do_pseudo_register (int regnum)
3882{
f81353e4
EZ		 3883 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3884
53116e27 3885 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
8e65ff28
AC		 3886 internal_error (__FILE__, __LINE__,
3887 "Invalid pseudo register number %d\n", regnum);
f81353e4
EZ		 3888 else if (regnum >= tdep->DR0_REGNUM
3889 && regnum < tdep->DR_LAST_REGNUM)
53116e27 3890 do_dr_register_info (regnum);
f81353e4
EZ		 3891 else if (regnum >= tdep->FV0_REGNUM
3892 && regnum <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 3893 do_fv_register_info (regnum);
3894}
3895
53116e27
EZ		 3896static void
3897sh_do_fp_register (int regnum)
3898{ /* do values for FP (float) regs */
3899 char *raw_buffer;
3900 double flt; /* double extracted from raw hex data */
3901 int inv;
3902 int j;
3903
3904 /* Allocate space for the float. */
3905 raw_buffer = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM));
3906
3907 /* Get the data in raw format. */
cda5a58a 3908 if (!frame_register_read (selected_frame, regnum, raw_buffer))
53116e27
EZ		 3909 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
3910
3911 /* Get the register as a number */
3912 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
3913
3914 /* Print the name and some spaces. */
3915 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
3916 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
3917
3918 /* Print the value. */
93d56215
AC		 3919 if (inv)
3920 printf_filtered ("<invalid float>");
3921 else
3922 printf_filtered ("%-10.9g", flt);
53116e27
EZ		 3923
3924 /* Print the fp register as hex. */
3925 printf_filtered ("\t(raw 0x");
3926 for (j = 0; j < REGISTER_RAW_SIZE (regnum); j++)
3927 {
d7449b42 3928 register int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
53116e27
EZ		 3929 : REGISTER_RAW_SIZE (regnum) - 1 - j;
3930 printf_filtered ("%02x", (unsigned char) raw_buffer[idx]);
3931 }
3932 printf_filtered (")");
3933 printf_filtered ("\n");
3934}
3935
283150cd
EZ		 3936static void
3937sh64_do_pseudo_register (int regnum)
3938{
3939 /* All the sh64-compact mode registers are pseudo registers. */
3940 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3941
3942 if (regnum < NUM_REGS
3943 || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT)
3944 internal_error (__FILE__, __LINE__,
3945 "Invalid pseudo register number %d\n", regnum);
3946
3947 else if ((regnum >= tdep->DR0_REGNUM
3948 && regnum <= tdep->DR_LAST_REGNUM))
3949 do_dr_register_info (regnum);
3950
3951 else if ((regnum >= tdep->DR0_C_REGNUM
3952 && regnum <= tdep->DR_LAST_C_REGNUM))
3953 do_dr_c_register_info (regnum);
3954
3955 else if ((regnum >= tdep->FV0_REGNUM
3956 && regnum <= tdep->FV_LAST_REGNUM))
3957 do_fv_register_info (regnum);
3958
3959 else if ((regnum >= tdep->FV0_C_REGNUM
3960 && regnum <= tdep->FV_LAST_C_REGNUM))
3961 do_fv_c_register_info (regnum);
3962
3963 else if (regnum >= tdep->FPP0_REGNUM
3964 && regnum <= tdep->FPP_LAST_REGNUM)
3965 do_fpp_register_info (regnum);
3966
3967 else if (regnum >= tdep->R0_C_REGNUM
3968 && regnum <= tdep->R_LAST_C_REGNUM)
3969 do_r_c_register_info (regnum); /* FIXME, this function will not print the right format */
3970
3971 else if (regnum >= tdep->FP0_C_REGNUM
3972 && regnum <= tdep->FP_LAST_C_REGNUM)
3973 sh_do_fp_register (regnum); /* this should work also for pseudoregs */
3974
3975 else if (regnum >= tdep->PC_C_REGNUM
3976 && regnum <= tdep->FPUL_C_REGNUM)
3977 do_cr_c_register_info (regnum);
3978
3979}
3980
53116e27
EZ		 3981static void
3982sh_do_register (int regnum)
3983{
3984 char raw_buffer[MAX_REGISTER_RAW_SIZE];
3985
3986 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
3987 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
3988
3989 /* Get the data in raw format. */
cda5a58a 3990 if (!frame_register_read (selected_frame, regnum, raw_buffer))
53116e27
EZ		 3991 printf_filtered ("*value not available*\n");
3992
3993 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
3994 gdb_stdout, 'x', 1, 0, Val_pretty_default);
3995 printf_filtered ("\t");
3996 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
3997 gdb_stdout, 0, 1, 0, Val_pretty_default);
3998 printf_filtered ("\n");
3999}
4000
4001static void
4002sh_print_register (int regnum)
4003{
4004 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
8e65ff28
AC		 4005 internal_error (__FILE__, __LINE__,
4006 "Invalid register number %d\n", regnum);
53116e27 4007
e30839fe 4008 else if (regnum >= 0 && regnum < NUM_REGS)
53116e27
EZ		 4009 {
4010 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4011 sh_do_fp_register (regnum); /* FP regs */
4012 else
4013 sh_do_register (regnum); /* All other regs */
4014 }
4015
4016 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
3bbfbb92 4017 do_pseudo_register (regnum);
53116e27
EZ		 4018}
4019
4020void
4021sh_do_registers_info (int regnum, int fpregs)
4022{
4023 if (regnum != -1) /* do one specified register */
4024 {
4025 if (*(REGISTER_NAME (regnum)) == '\0')
4026 error ("Not a valid register for the current processor type");
4027
4028 sh_print_register (regnum);
4029 }
4030 else
4031 /* do all (or most) registers */
4032 {
4033 regnum = 0;
4034 while (regnum < NUM_REGS)
4035 {
4036 /* If the register name is empty, it is undefined for this
4037 processor, so don't display anything. */
4038 if (REGISTER_NAME (regnum) == NULL
4039 || *(REGISTER_NAME (regnum)) == '\0')
4040 {
4041 regnum++;
4042 continue;
4043 }
4044
4045 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4046 {
4047 if (fpregs)
4048 {
4049 /* true for "INFO ALL-REGISTERS" command */
4050 sh_do_fp_register (regnum); /* FP regs */
4051 regnum ++;
4052 }
4053 else
e6c42fda 4054 regnum += (gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
53116e27
EZ		 4055 }
4056 else
4057 {
4058 sh_do_register (regnum); /* All other regs */
4059 regnum++;
4060 }
4061 }
4062
4063 if (fpregs)
4064 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4065 {
3bbfbb92 4066 do_pseudo_register (regnum);
53116e27
EZ		 4067 regnum++;
4068 }
4069 }
4070}
4071
283150cd
EZ		 4072void
4073sh_compact_do_registers_info (int regnum, int fpregs)
4074{
4075 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4076 if (regnum != -1) /* do one specified register */
4077 {
4078 if (*(REGISTER_NAME (regnum)) == '\0')
4079 error ("Not a valid register for the current processor type");
4080
4081 if (regnum >= 0 && regnum < tdep->R0_C_REGNUM)
4082 error ("Not a valid register for the current processor mode.");
4083
4084 sh_print_register (regnum);
4085 }
4086 else
4087 /* do all compact registers */
4088 {
4089 regnum = tdep->R0_C_REGNUM;
4090 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4091 {
4092 do_pseudo_register (regnum);
4093 regnum++;
4094 }
4095 }
4096}
4097
4098void
4099sh64_do_registers_info (int regnum, int fpregs)
4100{
4101 if (pc_is_isa32 (selected_frame->pc))
4102 sh_do_registers_info (regnum, fpregs);
4103 else
4104 sh_compact_do_registers_info (regnum, fpregs);
4105}
4106
1a8629c7
MS		 4107#ifdef SVR4_SHARED_LIBS
4108
4109/* Fetch (and possibly build) an appropriate link_map_offsets structure
4110 for native i386 linux targets using the struct offsets defined in
4111 link.h (but without actual reference to that file).
4112
4113 This makes it possible to access i386-linux shared libraries from
4114 a gdb that was not built on an i386-linux host (for cross debugging).
4115 */
4116
4117struct link_map_offsets *
4118sh_linux_svr4_fetch_link_map_offsets (void)
4119{
4120 static struct link_map_offsets lmo;
4121 static struct link_map_offsets *lmp = 0;
4122
4123 if (lmp == 0)
4124 {
4125 lmp = &lmo;
4126
4127 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
4128
4129 lmo.r_map_offset = 4;
4130 lmo.r_map_size = 4;
4131
4132 lmo.link_map_size = 20; /* 552 not actual size but all we need */
4133
4134 lmo.l_addr_offset = 0;
4135 lmo.l_addr_size = 4;
4136
4137 lmo.l_name_offset = 4;
4138 lmo.l_name_size = 4;
4139
4140 lmo.l_next_offset = 12;
4141 lmo.l_next_size = 4;
4142
4143 lmo.l_prev_offset = 16;
4144 lmo.l_prev_size = 4;
4145 }
4146
4147 return lmp;
4148}
4149#endif /* SVR4_SHARED_LIBS */
4150
2f14585c
JR		 4151\f
4152enum
4153{
4154 DSP_DSR_REGNUM = 24,
4155 DSP_A0G_REGNUM,
4156 DSP_A0_REGNUM,
4157 DSP_A1G_REGNUM,
4158 DSP_A1_REGNUM,
4159 DSP_M0_REGNUM,
4160 DSP_M1_REGNUM,
4161 DSP_X0_REGNUM,
4162 DSP_X1_REGNUM,
4163 DSP_Y0_REGNUM,
4164 DSP_Y1_REGNUM,
4165
4166 DSP_MOD_REGNUM = 40,
4167
4168 DSP_RS_REGNUM = 43,
4169 DSP_RE_REGNUM,
4170
4171 DSP_R0_BANK_REGNUM = 51,
4172 DSP_R7_BANK_REGNUM = DSP_R0_BANK_REGNUM + 7
4173};
4174
4175static int
4176sh_dsp_register_sim_regno (int nr)
4177{
4178 if (legacy_register_sim_regno (nr) < 0)
4179 return legacy_register_sim_regno (nr);
4180 if (nr >= DSP_DSR_REGNUM && nr < DSP_Y1_REGNUM)
4181 return nr - DSP_DSR_REGNUM + SIM_SH_DSR_REGNUM;
4182 if (nr == DSP_MOD_REGNUM)
4183 return SIM_SH_MOD_REGNUM;
4184 if (nr == DSP_RS_REGNUM)
4185 return SIM_SH_RS_REGNUM;
4186 if (nr == DSP_RE_REGNUM)
4187 return SIM_SH_RE_REGNUM;
4188 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
4189 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
4190 return nr;
4191}
d658f924 4192\f
cc17453a
EZ		 4193static gdbarch_init_ftype sh_gdbarch_init;
4194
4195static struct gdbarch *
fba45db2 4196sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
cc17453a
EZ		 4197{
4198 static LONGEST sh_call_dummy_words[] = {0};
4199 struct gdbarch *gdbarch;
4200 struct gdbarch_tdep *tdep;
4201 gdbarch_register_name_ftype *sh_register_name;
4202 gdbarch_store_return_value_ftype *sh_store_return_value;
4203 gdbarch_register_virtual_type_ftype *sh_register_virtual_type;
70f80edf 4204 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
d658f924
JT		 4205
4206 /* Try to determine the ABI of the object we are loading. */
4207
4208 if (info.abfd != NULL)
4209 {
70f80edf
JT		 4210 osabi = gdbarch_lookup_osabi (info.abfd);
4211 /* If we get "unknown" back, just leave it that way. */
d658f924 4212 }
cc17453a
EZ		 4213
4214 /* Find a candidate among the list of pre-declared architectures. */
d658f924
JT		 4215 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4216 arches != NULL;
4217 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4218 {
4219 /* Make sure the ABI selection matches. */
4220 tdep = gdbarch_tdep (arches->gdbarch);
70f80edf 4221 if (tdep && tdep->osabi == osabi)
d658f924
JT		 4222 return arches->gdbarch;
4223 }
cc17453a
EZ		 4224
4225 /* None found, create a new architecture from the information
4226 provided. */
4227 tdep = XMALLOC (struct gdbarch_tdep);
4228 gdbarch = gdbarch_alloc (&info, tdep);
4229
70f80edf 4230 tdep->osabi = osabi;
d658f924 4231
cc17453a
EZ		 4232 /* Initialize the register numbers that are not common to all the
4233 variants to -1, if necessary thse will be overwritten in the case
4234 statement below. */
4235 tdep->FPUL_REGNUM = -1;
4236 tdep->FPSCR_REGNUM = -1;
3bbfbb92 4237 tdep->PR_REGNUM = 17;
c62a7c7b 4238 tdep->SR_REGNUM = 22;
cc17453a 4239 tdep->DSR_REGNUM = -1;
e6c42fda 4240 tdep->FP_LAST_REGNUM = -1;
cc17453a
EZ		 4241 tdep->A0G_REGNUM = -1;
4242 tdep->A0_REGNUM = -1;
4243 tdep->A1G_REGNUM = -1;
4244 tdep->A1_REGNUM = -1;
4245 tdep->M0_REGNUM = -1;
4246 tdep->M1_REGNUM = -1;
4247 tdep->X0_REGNUM = -1;
4248 tdep->X1_REGNUM = -1;
4249 tdep->Y0_REGNUM = -1;
4250 tdep->Y1_REGNUM = -1;
4251 tdep->MOD_REGNUM = -1;
4252 tdep->RS_REGNUM = -1;
4253 tdep->RE_REGNUM = -1;
4254 tdep->SSR_REGNUM = -1;
4255 tdep->SPC_REGNUM = -1;
53116e27 4256 tdep->DR0_REGNUM = -1;
e6c42fda 4257 tdep->DR_LAST_REGNUM = -1;
53116e27 4258 tdep->FV0_REGNUM = -1;
e6c42fda 4259 tdep->FV_LAST_REGNUM = -1;
3bbfbb92
EZ		 4260 tdep->ARG0_REGNUM = 4;
4261 tdep->ARGLAST_REGNUM = 7;
4262 tdep->RETURN_REGNUM = 0;
4263 tdep->FLOAT_ARGLAST_REGNUM = -1;
a38d2a54 4264
283150cd
EZ		 4265 tdep->sh_abi = SH_ABI_UNKNOWN;
4266
cc17453a 4267 set_gdbarch_fp0_regnum (gdbarch, -1);
53116e27
EZ		 4268 set_gdbarch_num_pseudo_regs (gdbarch, 0);
4269 set_gdbarch_max_register_raw_size (gdbarch, 4);
4270 set_gdbarch_max_register_virtual_size (gdbarch, 4);
ec920329 4271 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
a38d2a54 4272 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
88e04cc1 4273 set_gdbarch_num_regs (gdbarch, SH_DEFAULT_NUM_REGS);
a38d2a54
EZ		 4274 set_gdbarch_sp_regnum (gdbarch, 15);
4275 set_gdbarch_fp_regnum (gdbarch, 14);
4276 set_gdbarch_pc_regnum (gdbarch, 16);
4277 set_gdbarch_register_size (gdbarch, 4);
88e04cc1 4278 set_gdbarch_register_bytes (gdbarch, SH_DEFAULT_NUM_REGS * 4);
c5f7d19c 4279 set_gdbarch_do_registers_info (gdbarch, sh_do_registers_info);
eaf90c5d 4280 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
3bbfbb92
EZ		 4281 set_gdbarch_frame_chain (gdbarch, sh_frame_chain);
4282 set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
4283 set_gdbarch_init_extra_frame_info (gdbarch, sh_init_extra_frame_info);
26e9b323 4284 set_gdbarch_deprecated_extract_return_value (gdbarch, sh_extract_return_value);
3bbfbb92
EZ		 4285 set_gdbarch_push_arguments (gdbarch, sh_push_arguments);
4286 set_gdbarch_store_struct_return (gdbarch, sh_store_struct_return);
4287 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
26e9b323 4288 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
3bbfbb92 4289 set_gdbarch_pop_frame (gdbarch, sh_pop_frame);
2bf0cb65 4290 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2f14585c 4291 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
3bbfbb92
EZ		 4292 skip_prologue_hard_way = sh_skip_prologue_hard_way;
4293 do_pseudo_register = sh_do_pseudo_register;
cc17453a
EZ		 4294
4295 switch (info.bfd_arch_info->mach)
8db62801 4296 {
cc17453a
EZ		 4297 case bfd_mach_sh:
4298 sh_register_name = sh_sh_register_name;
4299 sh_show_regs = sh_generic_show_regs;
4300 sh_store_return_value = sh_default_store_return_value;
4301 sh_register_virtual_type = sh_default_register_virtual_type;
4302 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 4303 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4304 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4305 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 4306 break;
4307 case bfd_mach_sh2:
4308 sh_register_name = sh_sh_register_name;
4309 sh_show_regs = sh_generic_show_regs;
4310 sh_store_return_value = sh_default_store_return_value;
4311 sh_register_virtual_type = sh_default_register_virtual_type;
4312 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 4313 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4314 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4315 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 4316 break;
4317 case bfd_mach_sh_dsp:
4318 sh_register_name = sh_sh_dsp_register_name;
4319 sh_show_regs = sh_dsp_show_regs;
4320 sh_store_return_value = sh_default_store_return_value;
4321 sh_register_virtual_type = sh_default_register_virtual_type;
4322 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 4323 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4324 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4325 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
2f14585c 4326 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a
EZ		 4327 tdep->DSR_REGNUM = 24;
4328 tdep->A0G_REGNUM = 25;
4329 tdep->A0_REGNUM = 26;
4330 tdep->A1G_REGNUM = 27;
4331 tdep->A1_REGNUM = 28;
4332 tdep->M0_REGNUM = 29;
4333 tdep->M1_REGNUM = 30;
4334 tdep->X0_REGNUM = 31;
4335 tdep->X1_REGNUM = 32;
4336 tdep->Y0_REGNUM = 33;
4337 tdep->Y1_REGNUM = 34;
4338 tdep->MOD_REGNUM = 40;
4339 tdep->RS_REGNUM = 43;
4340 tdep->RE_REGNUM = 44;
4341 break;
4342 case bfd_mach_sh3:
4343 sh_register_name = sh_sh3_register_name;
4344 sh_show_regs = sh3_show_regs;
4345 sh_store_return_value = sh_default_store_return_value;
4346 sh_register_virtual_type = sh_default_register_virtual_type;
4347 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 4348 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4349 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4350 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 4351 tdep->SSR_REGNUM = 41;
4352 tdep->SPC_REGNUM = 42;
4353 break;
4354 case bfd_mach_sh3e:
4355 sh_register_name = sh_sh3e_register_name;
4356 sh_show_regs = sh3e_show_regs;
4357 sh_store_return_value = sh3e_sh4_store_return_value;
4358 sh_register_virtual_type = sh_sh3e_register_virtual_type;
4359 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
53116e27
EZ		 4360 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4361 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4362 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
26e9b323 4363 set_gdbarch_deprecated_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
cc17453a
EZ		 4364 set_gdbarch_fp0_regnum (gdbarch, 25);
4365 tdep->FPUL_REGNUM = 23;
4366 tdep->FPSCR_REGNUM = 24;
e6c42fda 4367 tdep->FP_LAST_REGNUM = 40;
cc17453a
EZ		 4368 tdep->SSR_REGNUM = 41;
4369 tdep->SPC_REGNUM = 42;
4370 break;
4371 case bfd_mach_sh3_dsp:
4372 sh_register_name = sh_sh3_dsp_register_name;
4373 sh_show_regs = sh3_dsp_show_regs;
4374 sh_store_return_value = sh_default_store_return_value;
4375 sh_register_virtual_type = sh_default_register_virtual_type;
4376 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 4377 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4378 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4379 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 4380 tdep->DSR_REGNUM = 24;
4381 tdep->A0G_REGNUM = 25;
4382 tdep->A0_REGNUM = 26;
4383 tdep->A1G_REGNUM = 27;
4384 tdep->A1_REGNUM = 28;
4385 tdep->M0_REGNUM = 29;
4386 tdep->M1_REGNUM = 30;
4387 tdep->X0_REGNUM = 31;
4388 tdep->X1_REGNUM = 32;
4389 tdep->Y0_REGNUM = 33;
4390 tdep->Y1_REGNUM = 34;
4391 tdep->MOD_REGNUM = 40;
4392 tdep->RS_REGNUM = 43;
4393 tdep->RE_REGNUM = 44;
4394 tdep->SSR_REGNUM = 41;
4395 tdep->SPC_REGNUM = 42;
4396 break;
4397 case bfd_mach_sh4:
53116e27
EZ		 4398 sh_register_name = sh_sh4_register_name;
4399 sh_show_regs = sh4_show_regs;
cc17453a 4400 sh_store_return_value = sh3e_sh4_store_return_value;
53116e27 4401 sh_register_virtual_type = sh_sh4_register_virtual_type;
cc17453a 4402 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
26e9b323 4403 set_gdbarch_deprecated_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
cc17453a 4404 set_gdbarch_fp0_regnum (gdbarch, 25);
53116e27
EZ		 4405 set_gdbarch_register_raw_size (gdbarch, sh_sh4_register_raw_size);
4406 set_gdbarch_register_virtual_size (gdbarch, sh_sh4_register_raw_size);
4407 set_gdbarch_register_byte (gdbarch, sh_sh4_register_byte);
4408 set_gdbarch_num_pseudo_regs (gdbarch, 12);
4409 set_gdbarch_max_register_raw_size (gdbarch, 4 * 4);
4410 set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4);
d8124050
AC		 4411 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
4412 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
cc17453a
EZ		 4413 tdep->FPUL_REGNUM = 23;
4414 tdep->FPSCR_REGNUM = 24;
e6c42fda 4415 tdep->FP_LAST_REGNUM = 40;
cc17453a
EZ		 4416 tdep->SSR_REGNUM = 41;
4417 tdep->SPC_REGNUM = 42;
53116e27 4418 tdep->DR0_REGNUM = 59;
e6c42fda 4419 tdep->DR_LAST_REGNUM = 66;
53116e27 4420 tdep->FV0_REGNUM = 67;
e6c42fda 4421 tdep->FV_LAST_REGNUM = 70;
cc17453a 4422 break;
283150cd
EZ		 4423 case bfd_mach_sh5:
4424 tdep->PR_REGNUM = 18;
4425 tdep->SR_REGNUM = 65;
4426 tdep->FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM;
4427 tdep->FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1;
4428 tdep->SSR_REGNUM = SIM_SH64_SSR_REGNUM;
4429 tdep->SPC_REGNUM = SIM_SH64_SPC_REGNUM;
4430 tdep->TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7;
4431 tdep->FPP0_REGNUM = 173;
4432 tdep->FPP_LAST_REGNUM = 204;
4433 tdep->DR0_REGNUM = 141;
4434 tdep->DR_LAST_REGNUM = 172;
4435 tdep->FV0_REGNUM = 205;
4436 tdep->FV_LAST_REGNUM = 220;
4437 tdep->R0_C_REGNUM = 221;
4438 tdep->R_LAST_C_REGNUM = 236;
4439 tdep->PC_C_REGNUM = 237;
4440 tdep->GBR_C_REGNUM = 238;
4441 tdep->MACH_C_REGNUM = 239;
4442 tdep->MACL_C_REGNUM = 240;
4443 tdep->PR_C_REGNUM = 241;
4444 tdep->T_C_REGNUM = 242;
4445 tdep->FPSCR_C_REGNUM = 243;
4446 tdep->FPUL_C_REGNUM = 244;
4447 tdep->FP0_C_REGNUM = 245;
4448 tdep->FP_LAST_C_REGNUM = 260;
4449 tdep->DR0_C_REGNUM = 261;
4450 tdep->DR_LAST_C_REGNUM = 268;
4451 tdep->FV0_C_REGNUM = 269;
4452 tdep->FV_LAST_C_REGNUM = 272;
4453 tdep->ARG0_REGNUM = 2;
4454 tdep->ARGLAST_REGNUM = 9;
4455 tdep->RETURN_REGNUM = 2;
4456 tdep->FLOAT_ARGLAST_REGNUM = 11;
4457
4458 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT);
4459 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
4460 set_gdbarch_pc_regnum (gdbarch, 64);
4461
4462 /* Determine the ABI */
4463 if (bfd_get_arch_size (info.abfd) == 64)
4464 {
4465 /* If the ABI is the 64-bit one, it can only be sh-media. */
4466 tdep->sh_abi = SH_ABI_64;
4467 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4468 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4469 }
4470 else
4471 {
4472 /* If the ABI is the 32-bit one it could be either media or
4473 compact. */
4474 tdep->sh_abi = SH_ABI_32;
4475 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4476 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4477 }
4478
4479 /* the number of real registers is the same whether we are in
4480 ISA16(compact) or ISA32(media). */
4481 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
4482 set_gdbarch_register_size (gdbarch, 8); /*????*/
4483 set_gdbarch_register_bytes (gdbarch,
4484 ((SIM_SH64_NR_FP_REGS + 1) * 4)
4485 + (SIM_SH64_NR_REGS - SIM_SH64_NR_FP_REGS -1) * 8);
4486
4487 sh_register_name = sh_sh64_register_name;
4488 sh_show_regs = sh64_show_regs;
4489 sh_register_virtual_type = sh_sh64_register_virtual_type;
4490 sh_store_return_value = sh64_store_return_value;
4491 skip_prologue_hard_way = sh64_skip_prologue_hard_way;
4492 do_pseudo_register = sh64_do_pseudo_register;
283150cd
EZ		 4493 set_gdbarch_register_raw_size (gdbarch, sh_sh64_register_raw_size);
4494 set_gdbarch_register_virtual_size (gdbarch, sh_sh64_register_raw_size);
4495 set_gdbarch_register_byte (gdbarch, sh_sh64_register_byte);
4496 /* This seems awfully wrong!*/
4497 /*set_gdbarch_max_register_raw_size (gdbarch, 8);*/
4498 /* should include the size of the pseudo regs. */
4499 set_gdbarch_max_register_raw_size (gdbarch, 4 * 4);
4500 /* Or should that go in the virtual_size? */
4501 /*set_gdbarch_max_register_virtual_size (gdbarch, 8);*/
4502 set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4);
d8124050
AC		 4503 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
4504 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
283150cd
EZ		 4505
4506 set_gdbarch_do_registers_info (gdbarch, sh64_do_registers_info);
4507 set_gdbarch_frame_init_saved_regs (gdbarch, sh64_nofp_frame_init_saved_regs);
4508 set_gdbarch_breakpoint_from_pc (gdbarch, sh_sh64_breakpoint_from_pc);
4509 set_gdbarch_init_extra_frame_info (gdbarch, sh64_init_extra_frame_info);
4510 set_gdbarch_frame_chain (gdbarch, sh64_frame_chain);
4511 set_gdbarch_get_saved_register (gdbarch, sh64_get_saved_register);
26e9b323 4512 set_gdbarch_deprecated_extract_return_value (gdbarch, sh64_extract_return_value);
283150cd
EZ		 4513 set_gdbarch_push_arguments (gdbarch, sh64_push_arguments);
4514 /*set_gdbarch_store_struct_return (gdbarch, sh64_store_struct_return);*/
26e9b323 4515 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh64_extract_struct_value_address);
283150cd
EZ		 4516 set_gdbarch_use_struct_convention (gdbarch, sh64_use_struct_convention);
4517 set_gdbarch_pop_frame (gdbarch, sh64_pop_frame);
4518 set_gdbarch_elf_make_msymbol_special (gdbarch,
4519 sh64_elf_make_msymbol_special);
4520 break;
cc17453a
EZ		 4521 default:
4522 sh_register_name = sh_generic_register_name;
4523 sh_show_regs = sh_generic_show_regs;
4524 sh_store_return_value = sh_default_store_return_value;
4525 sh_register_virtual_type = sh_default_register_virtual_type;
4526 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 4527 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4528 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4529 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a 4530 break;
8db62801 4531 }
cc17453a
EZ		 4532
4533 set_gdbarch_read_pc (gdbarch, generic_target_read_pc);
4534 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
4535 set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
cc17453a
EZ		 4536 set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
4537 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
4538
cc17453a 4539 set_gdbarch_register_name (gdbarch, sh_register_name);
cc17453a
EZ		 4540 set_gdbarch_register_virtual_type (gdbarch, sh_register_virtual_type);
4541
cc17453a
EZ		 4542 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
4543 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
cc17453a
EZ		 4544 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4545 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4546 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
a38d2a54 4547 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);/*??should be 8?*/
cc17453a
EZ		 4548
4549 set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
4550 set_gdbarch_call_dummy_length (gdbarch, 0);
4551 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
4552 set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
4553 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); /*???*/
4554 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
4555 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
4556 set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
4557 set_gdbarch_call_dummy_words (gdbarch, sh_call_dummy_words);
4558 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (sh_call_dummy_words));
4559 set_gdbarch_call_dummy_p (gdbarch, 1);
4560 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
cc17453a
EZ		 4561 set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
4562 set_gdbarch_coerce_float_to_double (gdbarch,
4563 sh_coerce_float_to_double);
4564
cc17453a
EZ		 4565 set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
4566 set_gdbarch_push_return_address (gdbarch, sh_push_return_address);
4567
cc17453a 4568 set_gdbarch_store_return_value (gdbarch, sh_store_return_value);
cc17453a
EZ		 4569 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
4570 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4571 set_gdbarch_decr_pc_after_break (gdbarch, 0);
4572 set_gdbarch_function_start_offset (gdbarch, 0);
cc17453a
EZ		 4573
4574 set_gdbarch_frame_args_skip (gdbarch, 0);
4575 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
cc17453a
EZ		 4576 set_gdbarch_frame_chain_valid (gdbarch, generic_file_frame_chain_valid);
4577 set_gdbarch_frame_saved_pc (gdbarch, sh_frame_saved_pc);
c347ee3e
MS		 4578 set_gdbarch_frame_args_address (gdbarch, default_frame_address);
4579 set_gdbarch_frame_locals_address (gdbarch, default_frame_address);
cc17453a
EZ		 4580 set_gdbarch_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
4581 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
4582 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
cc17453a 4583
70f80edf 4584 /* Hook in ABI-specific overrides, if they have been registered.
d658f924 4585
70f80edf
JT		 4586 FIXME: if the ABI is unknown, this is probably an embedded target,
4587 so we should not warn about this situation. */
4588 gdbarch_init_osabi (info, gdbarch, osabi);
d658f924 4589
cc17453a 4590 return gdbarch;
8db62801
EZ		 4591}
4592
d658f924
JT		 4593static void
4594sh_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
4595{
4596 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4597
4598 if (tdep == NULL)
4599 return;
4600
70f80edf
JT		 4601 fprintf_unfiltered (file, "sh_dump_tdep: OS ABI = %s\n",
4602 gdbarch_osabi_name (tdep->osabi));
d658f924
JT		 4603}
4604
c906108c 4605void
fba45db2 4606_initialize_sh_tdep (void)
c906108c
SS		 4607{
4608 struct cmd_list_element *c;
cc17453a 4609
d658f924 4610 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, sh_dump_tdep);
c906108c 4611
53116e27 4612 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
c906108c 4613}
GDB Binutils - Deliverables
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