projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* sh-tdep.c (sh_skip_prologue): Provide an upper limit on the function
[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
CommitLineData
85a453d5 1/* Target-dependent code for Renesas Super-H, for GDB.
0fd88904 2
0b302171 3 Copyright (C) 1993-2005, 2007-2012 Free Software Foundation, Inc.
c906108c 4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM		 7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
c5aa993b 10 (at your option) any later version.
c906108c 11
c5aa993b
JM		 12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b 17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c 19
c378eb4e
MS		 20/* Contributed by Steve Chamberlain
21 sac@cygnus.com. */
c906108c
SS		 22
23#include "defs.h"
24#include "frame.h"
1c0159e0
CV		 25#include "frame-base.h"
26#include "frame-unwind.h"
27#include "dwarf2-frame.h"
c906108c 28#include "symtab.h"
c906108c
SS		 29#include "gdbtypes.h"
30#include "gdbcmd.h"
31#include "gdbcore.h"
32#include "value.h"
33#include "dis-asm.h"
73c1f219 34#include "inferior.h"
c906108c 35#include "gdb_string.h"
1c0159e0 36#include "gdb_assert.h"
b4a20239 37#include "arch-utils.h"
fb409745 38#include "floatformat.h"
4e052eda 39#include "regcache.h"
d16aafd8 40#include "doublest.h"
4be87837 41#include "osabi.h"
dda63807 42#include "reggroups.h"
c9ac0a72 43#include "regset.h"
cb2cf4ce 44#include "objfiles.h"
c906108c 45
ab3b8126 46#include "sh-tdep.h"
04dcf5fa 47#include "sh64-tdep.h"
ab3b8126 48
d658f924 49#include "elf-bfd.h"
1a8629c7
MS		 50#include "solib-svr4.h"
51
55ff77ac 52/* sh flags */
283150cd 53#include "elf/sh.h"
fa8f86ff 54#include "dwarf2.h"
c378eb4e 55/* registers numbers shared with the simulator. */
1c922164 56#include "gdb/sim-sh.h"
283150cd 57
c055b101
CV		 58/* List of "set sh ..." and "show sh ..." commands. */
59static struct cmd_list_element *setshcmdlist = NULL;
60static struct cmd_list_element *showshcmdlist = NULL;
61
62static const char sh_cc_gcc[] = "gcc";
63static const char sh_cc_renesas[] = "renesas";
40478521 64static const char *const sh_cc_enum[] = {
c055b101
CV		 65 sh_cc_gcc,
66 sh_cc_renesas,
67 NULL
68};
69
70static const char *sh_active_calling_convention = sh_cc_gcc;
71
c458d6db 72static void (*sh_show_regs) (struct frame_info *);
cc17453a 73
da962468 74#define SH_NUM_REGS 67
88e04cc1 75
1c0159e0 76struct sh_frame_cache
cc17453a 77{
1c0159e0
CV		 78 /* Base address. */
79 CORE_ADDR base;
80 LONGEST sp_offset;
81 CORE_ADDR pc;
82
c378eb4e 83 /* Flag showing that a frame has been created in the prologue code. */
1c0159e0
CV		 84 int uses_fp;
85
86 /* Saved registers. */
87 CORE_ADDR saved_regs[SH_NUM_REGS];
88 CORE_ADDR saved_sp;
63978407 89};
c906108c 90
c055b101
CV		 91static int
92sh_is_renesas_calling_convention (struct type *func_type)
93{
ca193e27
TS		 94 int val = 0;
95
96 if (func_type)
97 {
98 func_type = check_typedef (func_type);
99
100 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
101 func_type = check_typedef (TYPE_TARGET_TYPE (func_type));
102
103 if (TYPE_CODE (func_type) == TYPE_CODE_FUNC
104 && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh)
105 val = 1;
106 }
107
108 if (sh_active_calling_convention == sh_cc_renesas)
109 val = 1;
110
111 return val;
c055b101
CV		 112}
113
fa88f677 114static const char *
d93859e2 115sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 116{
617daa0e
CV		 117 static char *register_names[] = {
118 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
119 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
120 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
121 "", "",
122 "", "", "", "", "", "", "", "",
123 "", "", "", "", "", "", "", "",
124 "", "",
125 "", "", "", "", "", "", "", "",
126 "", "", "", "", "", "", "", "",
da962468 127 "", "", "", "", "", "", "", "",
cc17453a
EZ		 128 };
129 if (reg_nr < 0)
130 return NULL;
131 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
132 return NULL;
133 return register_names[reg_nr];
134}
135
fa88f677 136static const char *
d93859e2 137sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 138{
617daa0e
CV		 139 static char *register_names[] = {
140 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
141 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
142 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
143 "", "",
144 "", "", "", "", "", "", "", "",
145 "", "", "", "", "", "", "", "",
146 "ssr", "spc",
cc17453a
EZ		 147 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
148 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
da962468 149 "", "", "", "", "", "", "", "",
cc17453a
EZ		 150 };
151 if (reg_nr < 0)
152 return NULL;
153 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
154 return NULL;
155 return register_names[reg_nr];
156}
157
fa88f677 158static const char *
d93859e2 159sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 160{
617daa0e
CV		 161 static char *register_names[] = {
162 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
163 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
164 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
cc17453a 165 "fpul", "fpscr",
617daa0e
CV		 166 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
167 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
168 "ssr", "spc",
cc17453a
EZ		 169 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
170 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468 171 "", "", "", "", "", "", "", "",
cc17453a
EZ		 172 };
173 if (reg_nr < 0)
174 return NULL;
175 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
176 return NULL;
177 return register_names[reg_nr];
178}
179
2d188dd3 180static const char *
d93859e2 181sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr)
2d188dd3 182{
617daa0e
CV		 183 static char *register_names[] = {
184 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
185 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
186 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
2d188dd3 187 "fpul", "fpscr",
617daa0e
CV		 188 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
189 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
190 "", "",
2d188dd3
NC		 191 "", "", "", "", "", "", "", "",
192 "", "", "", "", "", "", "", "",
da962468
CV		 193 "", "", "", "", "", "", "", "",
194 };
195 if (reg_nr < 0)
196 return NULL;
197 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
198 return NULL;
199 return register_names[reg_nr];
200}
201
202static const char *
d93859e2 203sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr)
da962468
CV		 204{
205 static char *register_names[] = {
206 /* general registers 0-15 */
207 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
208 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
209 /* 16 - 22 */
210 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
211 /* 23, 24 */
212 "fpul", "fpscr",
213 /* floating point registers 25 - 40 */
214 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
215 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
216 /* 41, 42 */
217 "", "",
218 /* 43 - 62. Banked registers. The bank number used is determined by
c378eb4e 219 the bank register (63). */
da962468
CV		 220 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
221 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
222 "machb", "ivnb", "prb", "gbrb", "maclb",
223 /* 63: register bank number, not a real register but used to
224 communicate the register bank currently get/set. This register
225 is hidden to the user, who manipulates it using the pseudo
226 register called "bank" (67). See below. */
227 "",
228 /* 64 - 66 */
229 "ibcr", "ibnr", "tbr",
230 /* 67: register bank number, the user visible pseudo register. */
231 "bank",
232 /* double precision (pseudo) 68 - 75 */
233 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
234 };
235 if (reg_nr < 0)
236 return NULL;
237 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
238 return NULL;
239 return register_names[reg_nr];
240}
241
242static const char *
d93859e2 243sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
da962468
CV		 244{
245 static char *register_names[] = {
246 /* general registers 0-15 */
247 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
248 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
249 /* 16 - 22 */
250 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
251 /* 23, 24 */
252 "", "",
253 /* floating point registers 25 - 40 */
254 "", "", "", "", "", "", "", "",
255 "", "", "", "", "", "", "", "",
256 /* 41, 42 */
257 "", "",
258 /* 43 - 62. Banked registers. The bank number used is determined by
c378eb4e 259 the bank register (63). */
da962468
CV		 260 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
261 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
262 "machb", "ivnb", "prb", "gbrb", "maclb",
263 /* 63: register bank number, not a real register but used to
264 communicate the register bank currently get/set. This register
265 is hidden to the user, who manipulates it using the pseudo
266 register called "bank" (67). See below. */
267 "",
268 /* 64 - 66 */
269 "ibcr", "ibnr", "tbr",
270 /* 67: register bank number, the user visible pseudo register. */
271 "bank",
272 /* double precision (pseudo) 68 - 75 */
273 "", "", "", "", "", "", "", "",
2d188dd3
NC		 274 };
275 if (reg_nr < 0)
276 return NULL;
277 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
278 return NULL;
279 return register_names[reg_nr];
280}
281
fa88f677 282static const char *
d93859e2 283sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 284{
617daa0e
CV		 285 static char *register_names[] = {
286 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
287 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
288 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
289 "", "dsr",
290 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
291 "y0", "y1", "", "", "", "", "", "mod",
292 "", "",
293 "rs", "re", "", "", "", "", "", "",
294 "", "", "", "", "", "", "", "",
da962468 295 "", "", "", "", "", "", "", "",
cc17453a
EZ		 296 };
297 if (reg_nr < 0)
298 return NULL;
299 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
300 return NULL;
301 return register_names[reg_nr];
302}
303
fa88f677 304static const char *
d93859e2 305sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 306{
617daa0e
CV		 307 static char *register_names[] = {
308 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
309 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
310 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
311 "", "dsr",
312 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
313 "y0", "y1", "", "", "", "", "", "mod",
314 "ssr", "spc",
315 "rs", "re", "", "", "", "", "", "",
026a72f8
CV		 316 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
317 "", "", "", "", "", "", "", "",
da962468 318 "", "", "", "", "", "", "", "",
cc17453a
EZ		 319 };
320 if (reg_nr < 0)
321 return NULL;
322 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
323 return NULL;
324 return register_names[reg_nr];
325}
326
fa88f677 327static const char *
d93859e2 328sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr)
53116e27 329{
617daa0e 330 static char *register_names[] = {
a38d2a54 331 /* general registers 0-15 */
617daa0e
CV		 332 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
333 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
a38d2a54 334 /* 16 - 22 */
617daa0e 335 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
a38d2a54 336 /* 23, 24 */
53116e27 337 "fpul", "fpscr",
a38d2a54 338 /* floating point registers 25 - 40 */
617daa0e
CV		 339 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
340 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
a38d2a54 341 /* 41, 42 */
617daa0e 342 "ssr", "spc",
a38d2a54 343 /* bank 0 43 - 50 */
53116e27 344 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
a38d2a54 345 /* bank 1 51 - 58 */
53116e27 346 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468 347 "", "", "", "", "", "", "", "",
c378eb4e 348 /* pseudo bank register. */
da962468 349 "",
a38d2a54 350 /* double precision (pseudo) 59 - 66 */
617daa0e 351 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
a38d2a54 352 /* vectors (pseudo) 67 - 70 */
617daa0e 353 "fv0", "fv4", "fv8", "fv12",
a38d2a54
EZ		 354 /* FIXME: missing XF 71 - 86 */
355 /* FIXME: missing XD 87 - 94 */
53116e27
EZ		 356 };
357 if (reg_nr < 0)
358 return NULL;
359 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
360 return NULL;
361 return register_names[reg_nr];
362}
363
474e5826 364static const char *
d93859e2 365sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
474e5826
CV		 366{
367 static char *register_names[] = {
368 /* general registers 0-15 */
369 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
370 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
371 /* 16 - 22 */
372 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
373 /* 23, 24 */
374 "", "",
375 /* floating point registers 25 - 40 -- not for nofpu target */
376 "", "", "", "", "", "", "", "",
377 "", "", "", "", "", "", "", "",
378 /* 41, 42 */
379 "ssr", "spc",
380 /* bank 0 43 - 50 */
381 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
382 /* bank 1 51 - 58 */
383 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468 384 "", "", "", "", "", "", "", "",
c378eb4e 385 /* pseudo bank register. */
da962468 386 "",
474e5826
CV		 387 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
388 "", "", "", "", "", "", "", "",
389 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
390 "", "", "", "",
391 };
392 if (reg_nr < 0)
393 return NULL;
394 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
395 return NULL;
396 return register_names[reg_nr];
397}
398
399static const char *
d93859e2 400sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
474e5826
CV		 401{
402 static char *register_names[] = {
403 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
404 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
405 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
406 "", "dsr",
407 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
408 "y0", "y1", "", "", "", "", "", "mod",
409 "ssr", "spc",
410 "rs", "re", "", "", "", "", "", "",
026a72f8
CV		 411 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
412 "", "", "", "", "", "", "", "",
da962468 413 "", "", "", "", "", "", "", "",
474e5826
CV		 414 };
415 if (reg_nr < 0)
416 return NULL;
417 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
418 return NULL;
419 return register_names[reg_nr];
420}
421
3117ed25 422static const unsigned char *
67d57894 423sh_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
cc17453a 424{
c378eb4e 425 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes. */
617daa0e
CV		 426 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
427
bac718a6
UW		 428 /* For remote stub targets, trapa #20 is used. */
429 if (strcmp (target_shortname, "remote") == 0)
430 {
431 static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 };
432 static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 };
433
67d57894 434 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
bac718a6
UW		 435 {
436 *lenptr = sizeof (big_remote_breakpoint);
437 return big_remote_breakpoint;
438 }
439 else
440 {
441 *lenptr = sizeof (little_remote_breakpoint);
442 return little_remote_breakpoint;
443 }
444 }
445
cc17453a
EZ		 446 *lenptr = sizeof (breakpoint);
447 return breakpoint;
448}
c906108c
SS		 449
450/* Prologue looks like
1c0159e0
CV		 451 mov.l r14,@-r15
452 sts.l pr,@-r15
453 mov.l <regs>,@-r15
454 sub <room_for_loca_vars>,r15
455 mov r15,r14
8db62801 456
c378eb4e 457 Actually it can be more complicated than this but that's it, basically. */
c906108c 458
1c0159e0
CV		 459#define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
460#define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
461
5f883edd
FF		 462/* JSR @Rm 0100mmmm00001011 */
463#define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
464
8db62801
EZ		 465/* STS.L PR,@-r15 0100111100100010
466 r15-4-->r15, PR-->(r15) */
c906108c 467#define IS_STS(x) ((x) == 0x4f22)
8db62801 468
03131d99
CV		 469/* STS.L MACL,@-r15 0100111100010010
470 r15-4-->r15, MACL-->(r15) */
471#define IS_MACL_STS(x) ((x) == 0x4f12)
472
8db62801
EZ		 473/* MOV.L Rm,@-r15 00101111mmmm0110
474 r15-4-->r15, Rm-->(R15) */
c906108c 475#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 476
8db62801
EZ		 477/* MOV r15,r14 0110111011110011
478 r15-->r14 */
c906108c 479#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ		 480
481/* ADD #imm,r15 01111111iiiiiiii
482 r15+imm-->r15 */
1c0159e0 483#define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 484
c906108c
SS		 485#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
486#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ		 487
488/* ADD r3,r15 0011111100111100
489 r15+r3-->r15 */
c906108c 490#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ		 491
492/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
8db62801 493 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
8db62801 494 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
f2ea0907 495/* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
c378eb4e 496 make this entirely clear. */
1c0159e0
CV		 497/* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
498#define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
499
500/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
501#define IS_MOV_ARG_TO_REG(x) \
502 (((x) & 0xf00f) == 0x6003 && \
503 ((x) & 0x00f0) >= 0x0040 && \
504 ((x) & 0x00f0) <= 0x0070)
505/* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
506#define IS_MOV_ARG_TO_IND_R14(x) \
507 (((x) & 0xff0f) == 0x2e02 && \
508 ((x) & 0x00f0) >= 0x0040 && \
509 ((x) & 0x00f0) <= 0x0070)
510/* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
511#define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
512 (((x) & 0xff00) == 0x1e00 && \
513 ((x) & 0x00f0) >= 0x0040 && \
514 ((x) & 0x00f0) <= 0x0070)
515
516/* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
517#define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
518/* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
519#define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
03131d99
CV		 520/* MOVI20 #imm20,Rn 0000nnnniiii0000 */
521#define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
1c0159e0
CV		 522/* SUB Rn,R15 00111111nnnn1000 */
523#define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
8db62801 524
1c0159e0 525#define FPSCR_SZ (1 << 20)
cc17453a 526
c378eb4e 527/* The following instructions are used for epilogue testing. */
1c0159e0
CV		 528#define IS_RESTORE_FP(x) ((x) == 0x6ef6)
529#define IS_RTS(x) ((x) == 0x000b)
530#define IS_LDS(x) ((x) == 0x4f26)
03131d99 531#define IS_MACL_LDS(x) ((x) == 0x4f16)
1c0159e0
CV		 532#define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
533#define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
534#define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
cc17453a 535
cc17453a 536static CORE_ADDR
e17a4113 537sh_analyze_prologue (struct gdbarch *gdbarch,
5cbb9812 538 CORE_ADDR pc, CORE_ADDR limit_pc,
d2ca4222 539 struct sh_frame_cache *cache, ULONGEST fpscr)
617daa0e 540{
e17a4113 541 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1c0159e0 542 ULONGEST inst;
1c0159e0
CV		 543 int offset;
544 int sav_offset = 0;
c906108c 545 int r3_val = 0;
1c0159e0 546 int reg, sav_reg = -1;
cc17453a 547
1c0159e0 548 cache->uses_fp = 0;
5cbb9812 549 for (; pc < limit_pc; pc += 2)
cc17453a 550 {
e17a4113 551 inst = read_memory_unsigned_integer (pc, 2, byte_order);
c378eb4e 552 /* See where the registers will be saved to. */
f2ea0907 553 if (IS_PUSH (inst))
cc17453a 554 {
1c0159e0
CV		 555 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
556 cache->sp_offset += 4;
cc17453a 557 }
f2ea0907 558 else if (IS_STS (inst))
cc17453a 559 {
1c0159e0
CV		 560 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
561 cache->sp_offset += 4;
cc17453a 562 }
03131d99
CV		 563 else if (IS_MACL_STS (inst))
564 {
565 cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
566 cache->sp_offset += 4;
567 }
f2ea0907 568 else if (IS_MOV_R3 (inst))
cc17453a 569 {
f2ea0907 570 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
cc17453a 571 }
f2ea0907 572 else if (IS_SHLL_R3 (inst))
cc17453a
EZ		 573 {
574 r3_val <<= 1;
575 }
f2ea0907 576 else if (IS_ADD_R3SP (inst))
cc17453a 577 {
1c0159e0 578 cache->sp_offset += -r3_val;
cc17453a 579 }
f2ea0907 580 else if (IS_ADD_IMM_SP (inst))
cc17453a 581 {
1c0159e0
CV		 582 offset = ((inst & 0xff) ^ 0x80) - 0x80;
583 cache->sp_offset -= offset;
c906108c 584 }
1c0159e0 585 else if (IS_MOVW_PCREL_TO_REG (inst))
617daa0e 586 {
1c0159e0
CV		 587 if (sav_reg < 0)
588 {
589 reg = GET_TARGET_REG (inst);
590 if (reg < 14)
591 {
592 sav_reg = reg;
a2b4a96c 593 offset = (inst & 0xff) << 1;
1c0159e0 594 sav_offset =
e17a4113 595 read_memory_integer ((pc + 4) + offset, 2, byte_order);
1c0159e0
CV		 596 }
597 }
c906108c 598 }
1c0159e0 599 else if (IS_MOVL_PCREL_TO_REG (inst))
617daa0e 600 {
1c0159e0
CV		 601 if (sav_reg < 0)
602 {
a2b4a96c 603 reg = GET_TARGET_REG (inst);
1c0159e0
CV		 604 if (reg < 14)
605 {
606 sav_reg = reg;
a2b4a96c 607 offset = (inst & 0xff) << 2;
1c0159e0 608 sav_offset =
e17a4113
UW		 609 read_memory_integer (((pc & 0xfffffffc) + 4) + offset,
610 4, byte_order);
1c0159e0
CV		 611 }
612 }
c906108c 613 }
5cbb9812
TS		 614 else if (IS_MOVI20 (inst)
615 && (pc + 2 < limit_pc))
03131d99
CV		 616 {
617 if (sav_reg < 0)
618 {
619 reg = GET_TARGET_REG (inst);
620 if (reg < 14)
621 {
622 sav_reg = reg;
623 sav_offset = GET_SOURCE_REG (inst) << 16;
c378eb4e 624 /* MOVI20 is a 32 bit instruction! */
03131d99 625 pc += 2;
e17a4113
UW		 626 sav_offset
627 |= read_memory_unsigned_integer (pc, 2, byte_order);
03131d99
CV		 628 /* Now sav_offset contains an unsigned 20 bit value.
629 It must still get sign extended. */
630 if (sav_offset & 0x00080000)
631 sav_offset |= 0xfff00000;
632 }
633 }
634 }
1c0159e0 635 else if (IS_SUB_REG_FROM_SP (inst))
617daa0e 636 {
1c0159e0
CV		 637 reg = GET_SOURCE_REG (inst);
638 if (sav_reg > 0 && reg == sav_reg)
639 {
640 sav_reg = -1;
641 }
642 cache->sp_offset += sav_offset;
c906108c 643 }
f2ea0907 644 else if (IS_FPUSH (inst))
c906108c 645 {
d2ca4222 646 if (fpscr & FPSCR_SZ)
c906108c 647 {
1c0159e0 648 cache->sp_offset += 8;
c906108c
SS		 649 }
650 else
651 {
1c0159e0 652 cache->sp_offset += 4;
c906108c
SS		 653 }
654 }
f2ea0907 655 else if (IS_MOV_SP_FP (inst))
617daa0e 656 {
5cbb9812
TS		 657 pc += 2;
658 /* Don't go any further than six more instructions. */
659 limit_pc = min (limit_pc, pc + (2 * 6));
660
960ccd7d 661 cache->uses_fp = 1;
1c0159e0
CV		 662 /* At this point, only allow argument register moves to other
663 registers or argument register moves to @(X,fp) which are
664 moving the register arguments onto the stack area allocated
665 by a former add somenumber to SP call. Don't allow moving
c378eb4e 666 to an fp indirect address above fp + cache->sp_offset. */
5cbb9812 667 for (; pc < limit_pc; pc += 2)
1c0159e0 668 {
e17a4113 669 inst = read_memory_integer (pc, 2, byte_order);
1c0159e0 670 if (IS_MOV_ARG_TO_IND_R14 (inst))
617daa0e 671 {
1c0159e0
CV		 672 reg = GET_SOURCE_REG (inst);
673 if (cache->sp_offset > 0)
617daa0e 674 cache->saved_regs[reg] = cache->sp_offset;
1c0159e0
CV		 675 }
676 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
617daa0e 677 {
1c0159e0
CV		 678 reg = GET_SOURCE_REG (inst);
679 offset = (inst & 0xf) * 4;
680 if (cache->sp_offset > offset)
681 cache->saved_regs[reg] = cache->sp_offset - offset;
682 }
683 else if (IS_MOV_ARG_TO_REG (inst))
617daa0e 684 continue;
1c0159e0
CV		 685 else
686 break;
687 }
688 break;
689 }
5f883edd
FF		 690 else if (IS_JSR (inst))
691 {
692 /* We have found a jsr that has been scheduled into the prologue.
693 If we continue the scan and return a pc someplace after this,
694 then setting a breakpoint on this function will cause it to
695 appear to be called after the function it is calling via the
696 jsr, which will be very confusing. Most likely the next
697 instruction is going to be IS_MOV_SP_FP in the delay slot. If
c378eb4e 698 so, note that before returning the current pc. */
5cbb9812
TS		 699 if (pc + 2 < limit_pc)
700 {
701 inst = read_memory_integer (pc + 2, 2, byte_order);
702 if (IS_MOV_SP_FP (inst))
703 cache->uses_fp = 1;
704 }
5f883edd
FF		 705 break;
706 }
c378eb4e
MS		 707#if 0 /* This used to just stop when it found an instruction
708 that was not considered part of the prologue. Now,
709 we just keep going looking for likely
710 instructions. */
c906108c
SS		 711 else
712 break;
2bfa91ee 713#endif
c906108c
SS		 714 }
715
1c0159e0
CV		 716 return pc;
717}
c906108c 718
c378eb4e 719/* Skip any prologue before the guts of a function. */
1c0159e0 720static CORE_ADDR
8a8bc27f 721sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
c906108c 722{
5cbb9812 723 CORE_ADDR post_prologue_pc, func_addr, func_end_addr, limit_pc;
1c0159e0
CV		 724 struct sh_frame_cache cache;
725
726 /* See if we can determine the end of the prologue via the symbol table.
727 If so, then return either PC, or the PC after the prologue, whichever
728 is greater. */
5cbb9812 729 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr))
8a8bc27f
TS		 730 {
731 post_prologue_pc = skip_prologue_using_sal (gdbarch, func_addr);
732 if (post_prologue_pc != 0)
733 return max (pc, post_prologue_pc);
734 }
cc17453a 735
8a8bc27f
TS		 736 /* Can't determine prologue from the symbol table, need to examine
737 instructions. */
c906108c 738
5cbb9812
TS		 739 /* Find an upper limit on the function prologue using the debug
740 information. If the debug information could not be used to provide
741 that bound, then use an arbitrary large number as the upper bound. */
742 limit_pc = skip_prologue_using_sal (gdbarch, pc);
743 if (limit_pc == 0)
744 /* Don't go any further than 28 instructions. */
745 limit_pc = pc + (2 * 28);
746
747 /* Do not allow limit_pc to be past the function end, if we know
748 where that end is... */
749 if (func_end_addr != 0)
750 limit_pc = min (limit_pc, func_end_addr);
751
1c0159e0 752 cache.sp_offset = -4;
5cbb9812 753 post_prologue_pc = sh_analyze_prologue (gdbarch, pc, limit_pc, &cache, 0);
8a8bc27f
TS		 754 if (cache.uses_fp)
755 pc = post_prologue_pc;
c906108c 756
1c0159e0
CV		 757 return pc;
758}
759
2e952408 760/* The ABI says:
9a5cef92
EZ		 761
762 Aggregate types not bigger than 8 bytes that have the same size and
763 alignment as one of the integer scalar types are returned in the
764 same registers as the integer type they match.
765
766 For example, a 2-byte aligned structure with size 2 bytes has the
767 same size and alignment as a short int, and will be returned in R0.
768 A 4-byte aligned structure with size 8 bytes has the same size and
769 alignment as a long long int, and will be returned in R0 and R1.
770
771 When an aggregate type is returned in R0 and R1, R0 contains the
772 first four bytes of the aggregate, and R1 contains the
c378eb4e 773 remainder. If the size of the aggregate type is not a multiple of 4
9a5cef92 774 bytes, the aggregate is tail-padded up to a multiple of 4
c378eb4e 775 bytes. The value of the padding is undefined. For little-endian
9a5cef92
EZ		 776 targets the padding will appear at the most significant end of the
777 last element, for big-endian targets the padding appears at the
778 least significant end of the last element.
779
c378eb4e 780 All other aggregate types are returned by address. The caller
9a5cef92 781 function passes the address of an area large enough to hold the
c378eb4e 782 aggregate value in R2. The called function stores the result in
7fe958be 783 this location.
9a5cef92
EZ		 784
785 To reiterate, structs smaller than 8 bytes could also be returned
786 in memory, if they don't pass the "same size and alignment as an
787 integer type" rule.
788
789 For example, in
790
791 struct s { char c[3]; } wibble;
792 struct s foo(void) { return wibble; }
793
794 the return value from foo() will be in memory, not
795 in R0, because there is no 3-byte integer type.
796
7fe958be
EZ		 797 Similarly, in
798
799 struct s { char c[2]; } wibble;
800 struct s foo(void) { return wibble; }
801
802 because a struct containing two chars has alignment 1, that matches
803 type char, but size 2, that matches type short. There's no integer
804 type that has alignment 1 and size 2, so the struct is returned in
c378eb4e 805 memory. */
9a5cef92 806
1c0159e0 807static int
c055b101 808sh_use_struct_convention (int renesas_abi, struct type *type)
1c0159e0
CV		 809{
810 int len = TYPE_LENGTH (type);
811 int nelem = TYPE_NFIELDS (type);
3f997a97 812
c055b101
CV		 813 /* The Renesas ABI returns aggregate types always on stack. */
814 if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT
815 || TYPE_CODE (type) == TYPE_CODE_UNION))
816 return 1;
817
3f997a97
CV		 818 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
819 fit in two registers anyway) use struct convention. */
820 if (len != 1 && len != 2 && len != 4 && len != 8)
821 return 1;
822
823 /* Scalar types and aggregate types with exactly one field are aligned
824 by definition. They are returned in registers. */
825 if (nelem <= 1)
826 return 0;
827
828 /* If the first field in the aggregate has the same length as the entire
829 aggregate type, the type is returned in registers. */
830 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
831 return 0;
832
833 /* If the size of the aggregate is 8 bytes and the first field is
834 of size 4 bytes its alignment is equal to long long's alignment,
835 so it's returned in registers. */
836 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
837 return 0;
838
839 /* Otherwise use struct convention. */
840 return 1;
283150cd
EZ		 841}
842
c055b101
CV		 843static int
844sh_use_struct_convention_nofpu (int renesas_abi, struct type *type)
845{
846 /* The Renesas ABI returns long longs/doubles etc. always on stack. */
847 if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8)
848 return 1;
849 return sh_use_struct_convention (renesas_abi, type);
850}
851
19f59343
MS		 852static CORE_ADDR
853sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
854{
855 return sp & ~3;
856}
857
55ff77ac 858/* Function: push_dummy_call (formerly push_arguments)
c906108c
SS		 859 Setup the function arguments for calling a function in the inferior.
860
85a453d5 861 On the Renesas SH architecture, there are four registers (R4 to R7)
c906108c
SS		 862 which are dedicated for passing function arguments. Up to the first
863 four arguments (depending on size) may go into these registers.
864 The rest go on the stack.
865
6df2bf50
MS		 866 MVS: Except on SH variants that have floating point registers.
867 In that case, float and double arguments are passed in the same
868 manner, but using FP registers instead of GP registers.
869
c906108c
SS		 870 Arguments that are smaller than 4 bytes will still take up a whole
871 register or a whole 32-bit word on the stack, and will be
872 right-justified in the register or the stack word. This includes
873 chars, shorts, and small aggregate types.
874
875 Arguments that are larger than 4 bytes may be split between two or
876 more registers. If there are not enough registers free, an argument
877 may be passed partly in a register (or registers), and partly on the
c378eb4e 878 stack. This includes doubles, long longs, and larger aggregates.
c906108c
SS		 879 As far as I know, there is no upper limit to the size of aggregates
880 that will be passed in this way; in other words, the convention of
881 passing a pointer to a large aggregate instead of a copy is not used.
882
6df2bf50 883 MVS: The above appears to be true for the SH variants that do not
55ff77ac 884 have an FPU, however those that have an FPU appear to copy the
6df2bf50
MS		 885 aggregate argument onto the stack (and not place it in registers)
886 if it is larger than 16 bytes (four GP registers).
887
c906108c
SS		 888 An exceptional case exists for struct arguments (and possibly other
889 aggregates such as arrays) if the size is larger than 4 bytes but
890 not a multiple of 4 bytes. In this case the argument is never split
891 between the registers and the stack, but instead is copied in its
892 entirety onto the stack, AND also copied into as many registers as
893 there is room for. In other words, space in registers permitting,
894 two copies of the same argument are passed in. As far as I can tell,
895 only the one on the stack is used, although that may be a function
896 of the level of compiler optimization. I suspect this is a compiler
897 bug. Arguments of these odd sizes are left-justified within the
898 word (as opposed to arguments smaller than 4 bytes, which are
899 right-justified).
c5aa993b 900
c906108c
SS		 901 If the function is to return an aggregate type such as a struct, it
902 is either returned in the normal return value register R0 (if its
903 size is no greater than one byte), or else the caller must allocate
904 space into which the callee will copy the return value (if the size
905 is greater than one byte). In this case, a pointer to the return
906 value location is passed into the callee in register R2, which does
907 not displace any of the other arguments passed in via registers R4
c378eb4e 908 to R7. */
c906108c 909
c378eb4e 910/* Helper function to justify value in register according to endianess. */
e5e33cd9 911static char *
d93859e2 912sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len)
e5e33cd9
CV		 913{
914 static char valbuf[4];
915
617daa0e 916 memset (valbuf, 0, sizeof (valbuf));
e5e33cd9
CV		 917 if (len < 4)
918 {
c378eb4e 919 /* value gets right-justified in the register or stack word. */
d93859e2 920 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
0fd88904 921 memcpy (valbuf + (4 - len), (char *) value_contents (val), len);
e5e33cd9 922 else
0fd88904 923 memcpy (valbuf, (char *) value_contents (val), len);
e5e33cd9
CV		 924 return valbuf;
925 }
0fd88904 926 return (char *) value_contents (val);
617daa0e 927}
e5e33cd9 928
c378eb4e 929/* Helper function to eval number of bytes to allocate on stack. */
e5e33cd9
CV		 930static CORE_ADDR
931sh_stack_allocsize (int nargs, struct value **args)
932{
933 int stack_alloc = 0;
934 while (nargs-- > 0)
4991999e 935 stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3);
e5e33cd9
CV		 936 return stack_alloc;
937}
938
939/* Helper functions for getting the float arguments right. Registers usage
940 depends on the ABI and the endianess. The comments should enlighten how
c378eb4e 941 it's intended to work. */
e5e33cd9 942
c378eb4e 943/* This array stores which of the float arg registers are already in use. */
e5e33cd9
CV		 944static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
945
c378eb4e 946/* This function just resets the above array to "no reg used so far". */
e5e33cd9
CV		 947static void
948sh_init_flt_argreg (void)
949{
950 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
951}
952
953/* This function returns the next register to use for float arg passing.
954 It returns either a valid value between FLOAT_ARG0_REGNUM and
955 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
956 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
957
958 Note that register number 0 in flt_argreg_array corresponds with the
959 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
960 29) the parity of the register number is preserved, which is important
c378eb4e 961 for the double register passing test (see the "argreg & 1" test below). */
e5e33cd9 962static int
c055b101 963sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type)
e5e33cd9
CV		 964{
965 int argreg;
966
c378eb4e 967 /* First search for the next free register. */
617daa0e
CV		 968 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
969 ++argreg)
e5e33cd9
CV		 970 if (!flt_argreg_array[argreg])
971 break;
972
c378eb4e 973 /* No register left? */
e5e33cd9
CV		 974 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
975 return FLOAT_ARGLAST_REGNUM + 1;
976
977 if (len == 8)
978 {
c378eb4e 979 /* Doubles are always starting in a even register number. */
e5e33cd9 980 if (argreg & 1)
617daa0e 981 {
c055b101
CV		 982 /* In gcc ABI, the skipped register is lost for further argument
983 passing now. Not so in Renesas ABI. */
984 if (!sh_is_renesas_calling_convention (func_type))
985 flt_argreg_array[argreg] = 1;
e5e33cd9
CV		 986
987 ++argreg;
988
c378eb4e 989 /* No register left? */
e5e33cd9
CV		 990 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
991 return FLOAT_ARGLAST_REGNUM + 1;
992 }
c378eb4e 993 /* Also mark the next register as used. */
e5e33cd9
CV		 994 flt_argreg_array[argreg + 1] = 1;
995 }
c055b101
CV		 996 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
997 && !sh_is_renesas_calling_convention (func_type))
e5e33cd9 998 {
c378eb4e 999 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
e5e33cd9
CV		 1000 if (!flt_argreg_array[argreg + 1])
1001 ++argreg;
1002 }
1003 flt_argreg_array[argreg] = 1;
1004 return FLOAT_ARG0_REGNUM + argreg;
1005}
1006
afce3d2a
CV		 1007/* Helper function which figures out, if a type is treated like a float type.
1008
2e952408 1009 The FPU ABIs have a special way how to treat types as float types.
afce3d2a
CV		 1010 Structures with exactly one member, which is of type float or double, are
1011 treated exactly as the base types float or double:
1012
1013 struct sf {
1014 float f;
1015 };
1016
1017 struct sd {
1018 double d;
1019 };
1020
1021 are handled the same way as just
1022
1023 float f;
1024
1025 double d;
1026
1027 As a result, arguments of these struct types are pushed into floating point
1028 registers exactly as floats or doubles, using the same decision algorithm.
1029
1030 The same is valid if these types are used as function return types. The
1031 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1032 or even using struct convention as it is for other structs. */
1033
1034static int
1035sh_treat_as_flt_p (struct type *type)
1036{
1037 int len = TYPE_LENGTH (type);
1038
1039 /* Ordinary float types are obviously treated as float. */
1040 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1041 return 1;
1042 /* Otherwise non-struct types are not treated as float. */
1043 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
1044 return 0;
1045 /* Otherwise structs with more than one memeber are not treated as float. */
1046 if (TYPE_NFIELDS (type) != 1)
1047 return 0;
1048 /* Otherwise if the type of that member is float, the whole type is
1049 treated as float. */
1050 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
1051 return 1;
1052 /* Otherwise it's not treated as float. */
1053 return 0;
1054}
1055
cc17453a 1056static CORE_ADDR
617daa0e 1057sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
7d9b040b 1058 struct value *function,
617daa0e 1059 struct regcache *regcache,
6df2bf50 1060 CORE_ADDR bp_addr, int nargs,
617daa0e 1061 struct value **args,
6df2bf50
MS		 1062 CORE_ADDR sp, int struct_return,
1063 CORE_ADDR struct_addr)
1064{
e17a4113 1065 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e5e33cd9
CV		 1066 int stack_offset = 0;
1067 int argreg = ARG0_REGNUM;
8748518b 1068 int flt_argreg = 0;
6df2bf50 1069 int argnum;
c055b101 1070 struct type *func_type = value_type (function);
6df2bf50
MS		 1071 struct type *type;
1072 CORE_ADDR regval;
1073 char *val;
8748518b 1074 int len, reg_size = 0;
afce3d2a
CV		 1075 int pass_on_stack = 0;
1076 int treat_as_flt;
c055b101
CV		 1077 int last_reg_arg = INT_MAX;
1078
1079 /* The Renesas ABI expects all varargs arguments, plus the last
1080 non-vararg argument to be on the stack, no matter how many
1081 registers have been used so far. */
1082 if (sh_is_renesas_calling_convention (func_type)
876cecd0 1083 && TYPE_VARARGS (func_type))
c055b101 1084 last_reg_arg = TYPE_NFIELDS (func_type) - 2;
6df2bf50 1085
c378eb4e 1086 /* First force sp to a 4-byte alignment. */
6df2bf50
MS		 1087 sp = sh_frame_align (gdbarch, sp);
1088
c378eb4e 1089 /* Make room on stack for args. */
e5e33cd9
CV		 1090 sp -= sh_stack_allocsize (nargs, args);
1091
c378eb4e 1092 /* Initialize float argument mechanism. */
e5e33cd9 1093 sh_init_flt_argreg ();
6df2bf50
MS		 1094
1095 /* Now load as many as possible of the first arguments into
1096 registers, and push the rest onto the stack. There are 16 bytes
1097 in four registers available. Loop thru args from first to last. */
e5e33cd9 1098 for (argnum = 0; argnum < nargs; argnum++)
6df2bf50 1099 {
4991999e 1100 type = value_type (args[argnum]);
6df2bf50 1101 len = TYPE_LENGTH (type);
d93859e2 1102 val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
e5e33cd9
CV		 1103
1104 /* Some decisions have to be made how various types are handled.
c378eb4e 1105 This also differs in different ABIs. */
e5e33cd9 1106 pass_on_stack = 0;
e5e33cd9 1107
c378eb4e 1108 /* Find out the next register to use for a floating point value. */
afce3d2a
CV		 1109 treat_as_flt = sh_treat_as_flt_p (type);
1110 if (treat_as_flt)
c055b101
CV		 1111 flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type);
1112 /* In Renesas ABI, long longs and aggregate types are always passed
1113 on stack. */
1114 else if (sh_is_renesas_calling_convention (func_type)
1115 && ((TYPE_CODE (type) == TYPE_CODE_INT && len == 8)
1116 || TYPE_CODE (type) == TYPE_CODE_STRUCT
1117 || TYPE_CODE (type) == TYPE_CODE_UNION))
1118 pass_on_stack = 1;
afce3d2a
CV		 1119 /* In contrast to non-FPU CPUs, arguments are never split between
1120 registers and stack. If an argument doesn't fit in the remaining
1121 registers it's always pushed entirely on the stack. */
1122 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
1123 pass_on_stack = 1;
48db5a3c 1124
6df2bf50
MS		 1125 while (len > 0)
1126 {
afce3d2a
CV		 1127 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
1128 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
c055b101
CV		 1129 || pass_on_stack))
1130 || argnum > last_reg_arg)
617daa0e 1131 {
c378eb4e 1132 /* The data goes entirely on the stack, 4-byte aligned. */
e5e33cd9
CV		 1133 reg_size = (len + 3) & ~3;
1134 write_memory (sp + stack_offset, val, reg_size);
1135 stack_offset += reg_size;
6df2bf50 1136 }
afce3d2a 1137 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
6df2bf50 1138 {
e5e33cd9
CV		 1139 /* Argument goes in a float argument register. */
1140 reg_size = register_size (gdbarch, flt_argreg);
e17a4113 1141 regval = extract_unsigned_integer (val, reg_size, byte_order);
2e952408
CV		 1142 /* In little endian mode, float types taking two registers
1143 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1144 be stored swapped in the argument registers. The below
1145 code first writes the first 32 bits in the next but one
1146 register, increments the val and len values accordingly
1147 and then proceeds as normal by writing the second 32 bits
c378eb4e 1148 into the next register. */
b47193f7 1149 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
2e952408
CV		 1150 && TYPE_LENGTH (type) == 2 * reg_size)
1151 {
1152 regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
1153 regval);
1154 val += reg_size;
1155 len -= reg_size;
c378eb4e
MS		 1156 regval = extract_unsigned_integer (val, reg_size,
1157 byte_order);
2e952408 1158 }
6df2bf50
MS		 1159 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
1160 }
afce3d2a 1161 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
e5e33cd9 1162 {
6df2bf50 1163 /* there's room in a register */
e5e33cd9 1164 reg_size = register_size (gdbarch, argreg);
e17a4113 1165 regval = extract_unsigned_integer (val, reg_size, byte_order);
6df2bf50
MS		 1166 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1167 }
c378eb4e
MS		 1168 /* Store the value one register at a time or in one step on
1169 stack. */
e5e33cd9
CV		 1170 len -= reg_size;
1171 val += reg_size;
6df2bf50
MS		 1172 }
1173 }
1174
c055b101
CV		 1175 if (struct_return)
1176 {
1177 if (sh_is_renesas_calling_convention (func_type))
1178 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1179 the stack and store the struct return address there. */
e17a4113 1180 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
c055b101
CV		 1181 else
1182 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1183 its own dedicated register. */
1184 regcache_cooked_write_unsigned (regcache,
1185 STRUCT_RETURN_REGNUM, struct_addr);
1186 }
1187
c378eb4e 1188 /* Store return address. */
55ff77ac 1189 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
6df2bf50
MS		 1190
1191 /* Update stack pointer. */
3e8c568d 1192 regcache_cooked_write_unsigned (regcache,
b47193f7 1193 gdbarch_sp_regnum (gdbarch), sp);
6df2bf50
MS		 1194
1195 return sp;
1196}
1197
1198static CORE_ADDR
617daa0e 1199sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
7d9b040b 1200 struct value *function,
617daa0e
CV		 1201 struct regcache *regcache,
1202 CORE_ADDR bp_addr,
1203 int nargs, struct value **args,
1204 CORE_ADDR sp, int struct_return,
6df2bf50 1205 CORE_ADDR struct_addr)
c906108c 1206{
e17a4113 1207 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e5e33cd9
CV		 1208 int stack_offset = 0;
1209 int argreg = ARG0_REGNUM;
c906108c 1210 int argnum;
c055b101 1211 struct type *func_type = value_type (function);
c906108c
SS		 1212 struct type *type;
1213 CORE_ADDR regval;
1214 char *val;
c055b101
CV		 1215 int len, reg_size = 0;
1216 int pass_on_stack = 0;
1217 int last_reg_arg = INT_MAX;
1218
1219 /* The Renesas ABI expects all varargs arguments, plus the last
1220 non-vararg argument to be on the stack, no matter how many
1221 registers have been used so far. */
1222 if (sh_is_renesas_calling_convention (func_type)
876cecd0 1223 && TYPE_VARARGS (func_type))
c055b101 1224 last_reg_arg = TYPE_NFIELDS (func_type) - 2;
c906108c 1225
c378eb4e 1226 /* First force sp to a 4-byte alignment. */
19f59343 1227 sp = sh_frame_align (gdbarch, sp);
c906108c 1228
c378eb4e 1229 /* Make room on stack for args. */
e5e33cd9 1230 sp -= sh_stack_allocsize (nargs, args);
c906108c 1231
c906108c
SS		 1232 /* Now load as many as possible of the first arguments into
1233 registers, and push the rest onto the stack. There are 16 bytes
1234 in four registers available. Loop thru args from first to last. */
e5e33cd9 1235 for (argnum = 0; argnum < nargs; argnum++)
617daa0e 1236 {
4991999e 1237 type = value_type (args[argnum]);
c5aa993b 1238 len = TYPE_LENGTH (type);
d93859e2 1239 val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
c906108c 1240
c055b101 1241 /* Some decisions have to be made how various types are handled.
c378eb4e 1242 This also differs in different ABIs. */
c055b101
CV		 1243 pass_on_stack = 0;
1244 /* Renesas ABI pushes doubles and long longs entirely on stack.
1245 Same goes for aggregate types. */
1246 if (sh_is_renesas_calling_convention (func_type)
1247 && ((TYPE_CODE (type) == TYPE_CODE_INT && len >= 8)
1248 || (TYPE_CODE (type) == TYPE_CODE_FLT && len >= 8)
1249 || TYPE_CODE (type) == TYPE_CODE_STRUCT
1250 || TYPE_CODE (type) == TYPE_CODE_UNION))
1251 pass_on_stack = 1;
c906108c
SS		 1252 while (len > 0)
1253 {
c055b101
CV		 1254 if (argreg > ARGLAST_REGNUM || pass_on_stack
1255 || argnum > last_reg_arg)
617daa0e 1256 {
e5e33cd9 1257 /* The remainder of the data goes entirely on the stack,
c378eb4e 1258 4-byte aligned. */
e5e33cd9
CV		 1259 reg_size = (len + 3) & ~3;
1260 write_memory (sp + stack_offset, val, reg_size);
617daa0e 1261 stack_offset += reg_size;
c906108c 1262 }
e5e33cd9 1263 else if (argreg <= ARGLAST_REGNUM)
617daa0e 1264 {
c378eb4e 1265 /* There's room in a register. */
e5e33cd9 1266 reg_size = register_size (gdbarch, argreg);
e17a4113 1267 regval = extract_unsigned_integer (val, reg_size, byte_order);
48db5a3c 1268 regcache_cooked_write_unsigned (regcache, argreg++, regval);
c906108c 1269 }
e5e33cd9
CV		 1270 /* Store the value reg_size bytes at a time. This means that things
1271 larger than reg_size bytes may go partly in registers and partly
c906108c 1272 on the stack. */
e5e33cd9
CV		 1273 len -= reg_size;
1274 val += reg_size;
c906108c
SS		 1275 }
1276 }
48db5a3c 1277
c055b101
CV		 1278 if (struct_return)
1279 {
1280 if (sh_is_renesas_calling_convention (func_type))
1281 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1282 the stack and store the struct return address there. */
e17a4113 1283 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
c055b101
CV		 1284 else
1285 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1286 its own dedicated register. */
1287 regcache_cooked_write_unsigned (regcache,
1288 STRUCT_RETURN_REGNUM, struct_addr);
1289 }
1290
c378eb4e 1291 /* Store return address. */
55ff77ac 1292 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
48db5a3c
CV		 1293
1294 /* Update stack pointer. */
3e8c568d 1295 regcache_cooked_write_unsigned (regcache,
b47193f7 1296 gdbarch_sp_regnum (gdbarch), sp);
48db5a3c 1297
c906108c
SS		 1298 return sp;
1299}
1300
cc17453a
EZ		 1301/* Find a function's return value in the appropriate registers (in
1302 regbuf), and copy it into valbuf. Extract from an array REGBUF
1303 containing the (raw) register state a function return value of type
1304 TYPE, and copy that, in virtual format, into VALBUF. */
1305static void
3ffc5b9b
CV		 1306sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache,
1307 void *valbuf)
c906108c 1308{
e17a4113
UW		 1309 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1310 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
cc17453a 1311 int len = TYPE_LENGTH (type);
3116c80a
EZ		 1312 int return_register = R0_REGNUM;
1313 int offset;
617daa0e 1314
cc17453a 1315 if (len <= 4)
3116c80a 1316 {
48db5a3c
CV		 1317 ULONGEST c;
1318
1319 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
e17a4113 1320 store_unsigned_integer (valbuf, len, byte_order, c);
3116c80a 1321 }
48db5a3c 1322 else if (len == 8)
3116c80a 1323 {
48db5a3c
CV		 1324 int i, regnum = R0_REGNUM;
1325 for (i = 0; i < len; i += 4)
617daa0e 1326 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
3116c80a
EZ		 1327 }
1328 else
8a3fe4f8 1329 error (_("bad size for return value"));
3116c80a
EZ		 1330}
1331
1332static void
3ffc5b9b
CV		 1333sh_extract_return_value_fpu (struct type *type, struct regcache *regcache,
1334 void *valbuf)
3116c80a 1335{
d93859e2 1336 struct gdbarch *gdbarch = get_regcache_arch (regcache);
afce3d2a 1337 if (sh_treat_as_flt_p (type))
3116c80a 1338 {
48db5a3c 1339 int len = TYPE_LENGTH (type);
d93859e2 1340 int i, regnum = gdbarch_fp0_regnum (gdbarch);
48db5a3c 1341 for (i = 0; i < len; i += 4)
d93859e2 1342 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
c378eb4e
MS		 1343 regcache_raw_read (regcache, regnum++,
1344 (char *) valbuf + len - 4 - i);
2e952408
CV		 1345 else
1346 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
3116c80a 1347 }
cc17453a 1348 else
3ffc5b9b 1349 sh_extract_return_value_nofpu (type, regcache, valbuf);
cc17453a 1350}
c906108c 1351
cc17453a
EZ		 1352/* Write into appropriate registers a function return value
1353 of type TYPE, given in virtual format.
1354 If the architecture is sh4 or sh3e, store a function's return value
1355 in the R0 general register or in the FP0 floating point register,
c378eb4e
MS		 1356 depending on the type of the return value. In all the other cases
1357 the result is stored in r0, left-justified. */
cc17453a 1358static void
3ffc5b9b
CV		 1359sh_store_return_value_nofpu (struct type *type, struct regcache *regcache,
1360 const void *valbuf)
cc17453a 1361{
e17a4113
UW		 1362 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1363 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
48db5a3c
CV		 1364 ULONGEST val;
1365 int len = TYPE_LENGTH (type);
d19b71be 1366
48db5a3c 1367 if (len <= 4)
d19b71be 1368 {
e17a4113 1369 val = extract_unsigned_integer (valbuf, len, byte_order);
48db5a3c 1370 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
d19b71be
MS		 1371 }
1372 else
48db5a3c
CV		 1373 {
1374 int i, regnum = R0_REGNUM;
1375 for (i = 0; i < len; i += 4)
617daa0e 1376 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
48db5a3c 1377 }
cc17453a 1378}
c906108c 1379
cc17453a 1380static void
3ffc5b9b
CV		 1381sh_store_return_value_fpu (struct type *type, struct regcache *regcache,
1382 const void *valbuf)
cc17453a 1383{
d93859e2 1384 struct gdbarch *gdbarch = get_regcache_arch (regcache);
afce3d2a 1385 if (sh_treat_as_flt_p (type))
48db5a3c
CV		 1386 {
1387 int len = TYPE_LENGTH (type);
d93859e2 1388 int i, regnum = gdbarch_fp0_regnum (gdbarch);
48db5a3c 1389 for (i = 0; i < len; i += 4)
d93859e2 1390 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
c8a3b559
CV		 1391 regcache_raw_write (regcache, regnum++,
1392 (char *) valbuf + len - 4 - i);
1393 else
1394 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
48db5a3c 1395 }
cc17453a 1396 else
3ffc5b9b 1397 sh_store_return_value_nofpu (type, regcache, valbuf);
c906108c
SS		 1398}
1399
c0409442 1400static enum return_value_convention
c055b101
CV		 1401sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *func_type,
1402 struct type *type, struct regcache *regcache,
18cf8b5b 1403 gdb_byte *readbuf, const gdb_byte *writebuf)
c0409442 1404{
c055b101
CV		 1405 if (sh_use_struct_convention_nofpu (
1406 sh_is_renesas_calling_convention (func_type), type))
c0409442
CV		 1407 return RETURN_VALUE_STRUCT_CONVENTION;
1408 if (writebuf)
3ffc5b9b 1409 sh_store_return_value_nofpu (type, regcache, writebuf);
c0409442 1410 else if (readbuf)
3ffc5b9b 1411 sh_extract_return_value_nofpu (type, regcache, readbuf);
c0409442
CV		 1412 return RETURN_VALUE_REGISTER_CONVENTION;
1413}
1414
1415static enum return_value_convention
c055b101
CV		 1416sh_return_value_fpu (struct gdbarch *gdbarch, struct type *func_type,
1417 struct type *type, struct regcache *regcache,
18cf8b5b 1418 gdb_byte *readbuf, const gdb_byte *writebuf)
c0409442 1419{
c055b101
CV		 1420 if (sh_use_struct_convention (
1421 sh_is_renesas_calling_convention (func_type), type))
c0409442
CV		 1422 return RETURN_VALUE_STRUCT_CONVENTION;
1423 if (writebuf)
3ffc5b9b 1424 sh_store_return_value_fpu (type, regcache, writebuf);
c0409442 1425 else if (readbuf)
3ffc5b9b 1426 sh_extract_return_value_fpu (type, regcache, readbuf);
c0409442
CV		 1427 return RETURN_VALUE_REGISTER_CONVENTION;
1428}
1429
c378eb4e 1430/* Print the registers in a form similar to the E7000. */
c906108c
SS		 1431
1432static void
c458d6db 1433sh_generic_show_regs (struct frame_info *frame)
c906108c 1434{
c458d6db
UW		 1435 printf_filtered
1436 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1437 phex (get_frame_register_unsigned (frame,
1438 gdbarch_pc_regnum
1439 (get_frame_arch (frame))), 4),
c458d6db
UW		 1440 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1441 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1442 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
cc17453a 1443
c458d6db
UW		 1444 printf_filtered
1445 (" GBR %08lx VBR %08lx MACL %08lx\n",
1446 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1447 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1448 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
cc17453a 1449
617daa0e 1450 printf_filtered
a6b0a3f3 1451 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1452 (long) get_frame_register_unsigned (frame, 0),
1453 (long) get_frame_register_unsigned (frame, 1),
1454 (long) get_frame_register_unsigned (frame, 2),
1455 (long) get_frame_register_unsigned (frame, 3),
1456 (long) get_frame_register_unsigned (frame, 4),
1457 (long) get_frame_register_unsigned (frame, 5),
1458 (long) get_frame_register_unsigned (frame, 6),
1459 (long) get_frame_register_unsigned (frame, 7));
1460 printf_filtered
1461 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1462 (long) get_frame_register_unsigned (frame, 8),
1463 (long) get_frame_register_unsigned (frame, 9),
1464 (long) get_frame_register_unsigned (frame, 10),
1465 (long) get_frame_register_unsigned (frame, 11),
1466 (long) get_frame_register_unsigned (frame, 12),
1467 (long) get_frame_register_unsigned (frame, 13),
1468 (long) get_frame_register_unsigned (frame, 14),
1469 (long) get_frame_register_unsigned (frame, 15));
cc17453a 1470}
c906108c 1471
cc17453a 1472static void
c458d6db 1473sh3_show_regs (struct frame_info *frame)
cc17453a 1474{
c458d6db
UW		 1475 printf_filtered
1476 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1477 phex (get_frame_register_unsigned (frame,
1478 gdbarch_pc_regnum
1479 (get_frame_arch (frame))), 4),
c458d6db
UW		 1480 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1481 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1482 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1483
1484 printf_filtered
1485 (" GBR %08lx VBR %08lx MACL %08lx\n",
1486 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1487 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1488 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1489 printf_filtered
1490 (" SSR %08lx SPC %08lx\n",
1491 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1492 (long) get_frame_register_unsigned (frame, SPC_REGNUM));
c906108c 1493
617daa0e 1494 printf_filtered
a6b0a3f3 1495 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1496 (long) get_frame_register_unsigned (frame, 0),
1497 (long) get_frame_register_unsigned (frame, 1),
1498 (long) get_frame_register_unsigned (frame, 2),
1499 (long) get_frame_register_unsigned (frame, 3),
1500 (long) get_frame_register_unsigned (frame, 4),
1501 (long) get_frame_register_unsigned (frame, 5),
1502 (long) get_frame_register_unsigned (frame, 6),
1503 (long) get_frame_register_unsigned (frame, 7));
1504 printf_filtered
1505 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1506 (long) get_frame_register_unsigned (frame, 8),
1507 (long) get_frame_register_unsigned (frame, 9),
1508 (long) get_frame_register_unsigned (frame, 10),
1509 (long) get_frame_register_unsigned (frame, 11),
1510 (long) get_frame_register_unsigned (frame, 12),
1511 (long) get_frame_register_unsigned (frame, 13),
1512 (long) get_frame_register_unsigned (frame, 14),
1513 (long) get_frame_register_unsigned (frame, 15));
c906108c
SS		 1514}
1515
2d188dd3 1516static void
c458d6db 1517sh2e_show_regs (struct frame_info *frame)
2d188dd3 1518{
b47193f7 1519 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1520 printf_filtered
1521 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1522 phex (get_frame_register_unsigned (frame,
1523 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1524 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1525 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1526 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1527
1528 printf_filtered
1529 (" GBR %08lx VBR %08lx MACL %08lx\n",
1530 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1531 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1532 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1533 printf_filtered
1534 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1535 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1536 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1537 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1538 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
617daa0e
CV		 1539
1540 printf_filtered
a6b0a3f3 1541 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1542 (long) get_frame_register_unsigned (frame, 0),
1543 (long) get_frame_register_unsigned (frame, 1),
1544 (long) get_frame_register_unsigned (frame, 2),
1545 (long) get_frame_register_unsigned (frame, 3),
1546 (long) get_frame_register_unsigned (frame, 4),
1547 (long) get_frame_register_unsigned (frame, 5),
1548 (long) get_frame_register_unsigned (frame, 6),
1549 (long) get_frame_register_unsigned (frame, 7));
1550 printf_filtered
1551 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1552 (long) get_frame_register_unsigned (frame, 8),
1553 (long) get_frame_register_unsigned (frame, 9),
1554 (long) get_frame_register_unsigned (frame, 10),
1555 (long) get_frame_register_unsigned (frame, 11),
1556 (long) get_frame_register_unsigned (frame, 12),
1557 (long) get_frame_register_unsigned (frame, 13),
1558 (long) get_frame_register_unsigned (frame, 14),
1559 (long) get_frame_register_unsigned (frame, 15));
1560
1561 printf_filtered
1562 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1563 (long) get_frame_register_unsigned
b47193f7 1564 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1565 (long) get_frame_register_unsigned
b47193f7 1566 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1567 (long) get_frame_register_unsigned
b47193f7 1568 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1569 (long) get_frame_register_unsigned
b47193f7 1570 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1571 (long) get_frame_register_unsigned
b47193f7 1572 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1573 (long) get_frame_register_unsigned
b47193f7 1574 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1575 (long) get_frame_register_unsigned
b47193f7 1576 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1577 (long) get_frame_register_unsigned
b47193f7 1578 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 1579 printf_filtered
1580 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1581 (long) get_frame_register_unsigned
b47193f7 1582 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 1583 (long) get_frame_register_unsigned
b47193f7 1584 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 1585 (long) get_frame_register_unsigned
b47193f7 1586 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 1587 (long) get_frame_register_unsigned
b47193f7 1588 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 1589 (long) get_frame_register_unsigned
b47193f7 1590 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 1591 (long) get_frame_register_unsigned
b47193f7 1592 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 1593 (long) get_frame_register_unsigned
b47193f7 1594 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 1595 (long) get_frame_register_unsigned
b47193f7 1596 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
2d188dd3
NC		 1597}
1598
da962468 1599static void
c458d6db 1600sh2a_show_regs (struct frame_info *frame)
da962468 1601{
b47193f7 1602 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1603 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1604
1605 printf_filtered
1606 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1607 phex (get_frame_register_unsigned (frame,
1608 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1609 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1610 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1611 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1612
1613 printf_filtered
1614 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1615 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1616 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1617 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1618 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1619 printf_filtered
1620 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1621 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1622 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1623 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1624 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1625
1626 printf_filtered
1627 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1628 (long) get_frame_register_unsigned (frame, 0),
1629 (long) get_frame_register_unsigned (frame, 1),
1630 (long) get_frame_register_unsigned (frame, 2),
1631 (long) get_frame_register_unsigned (frame, 3),
1632 (long) get_frame_register_unsigned (frame, 4),
1633 (long) get_frame_register_unsigned (frame, 5),
1634 (long) get_frame_register_unsigned (frame, 6),
1635 (long) get_frame_register_unsigned (frame, 7));
1636 printf_filtered
1637 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1638 (long) get_frame_register_unsigned (frame, 8),
1639 (long) get_frame_register_unsigned (frame, 9),
1640 (long) get_frame_register_unsigned (frame, 10),
1641 (long) get_frame_register_unsigned (frame, 11),
1642 (long) get_frame_register_unsigned (frame, 12),
1643 (long) get_frame_register_unsigned (frame, 13),
1644 (long) get_frame_register_unsigned (frame, 14),
1645 (long) get_frame_register_unsigned (frame, 15));
1646
1647 printf_filtered
1648 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1649 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1650 (long) get_frame_register_unsigned
b47193f7 1651 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1652 (long) get_frame_register_unsigned
b47193f7 1653 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1654 (long) get_frame_register_unsigned
b47193f7 1655 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1656 (long) get_frame_register_unsigned
b47193f7 1657 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1658 (long) get_frame_register_unsigned
b47193f7 1659 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1660 (long) get_frame_register_unsigned
b47193f7 1661 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1662 (long) get_frame_register_unsigned
b47193f7 1663 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1664 (long) get_frame_register_unsigned
b47193f7 1665 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 1666 printf_filtered
1667 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1668 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1669 (long) get_frame_register_unsigned
b47193f7 1670 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 1671 (long) get_frame_register_unsigned
b47193f7 1672 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 1673 (long) get_frame_register_unsigned
b47193f7 1674 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 1675 (long) get_frame_register_unsigned
b47193f7 1676 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 1677 (long) get_frame_register_unsigned
b47193f7 1678 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 1679 (long) get_frame_register_unsigned
b47193f7 1680 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 1681 (long) get_frame_register_unsigned
b47193f7 1682 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 1683 (long) get_frame_register_unsigned
b47193f7 1684 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
c458d6db
UW		 1685 printf_filtered
1686 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1687 printf_filtered
1688 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1689 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1690 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1691 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1692 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1693 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1694 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1695 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1696 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1697 printf_filtered
1698 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1699 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1700 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1701 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1702 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1703 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1704 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1705 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1706 printf_filtered
1707 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1708 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1709 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1710 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1711 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1712 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
da962468
CV		 1713}
1714
1715static void
c458d6db 1716sh2a_nofpu_show_regs (struct frame_info *frame)
da962468 1717{
c458d6db
UW		 1718 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1719
1720 printf_filtered
1721 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1722 phex (get_frame_register_unsigned (frame,
1723 gdbarch_pc_regnum
1724 (get_frame_arch (frame))), 4),
c458d6db
UW		 1725 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1726 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1727 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1728
1729 printf_filtered
1730 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1731 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1732 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1733 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1734 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1735 printf_filtered
1736 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1737 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1738 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1739 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1740 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1741
1742 printf_filtered
1743 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1744 (long) get_frame_register_unsigned (frame, 0),
1745 (long) get_frame_register_unsigned (frame, 1),
1746 (long) get_frame_register_unsigned (frame, 2),
1747 (long) get_frame_register_unsigned (frame, 3),
1748 (long) get_frame_register_unsigned (frame, 4),
1749 (long) get_frame_register_unsigned (frame, 5),
1750 (long) get_frame_register_unsigned (frame, 6),
1751 (long) get_frame_register_unsigned (frame, 7));
1752 printf_filtered
1753 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1754 (long) get_frame_register_unsigned (frame, 8),
1755 (long) get_frame_register_unsigned (frame, 9),
1756 (long) get_frame_register_unsigned (frame, 10),
1757 (long) get_frame_register_unsigned (frame, 11),
1758 (long) get_frame_register_unsigned (frame, 12),
1759 (long) get_frame_register_unsigned (frame, 13),
1760 (long) get_frame_register_unsigned (frame, 14),
1761 (long) get_frame_register_unsigned (frame, 15));
1762
1763 printf_filtered
1764 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1765 printf_filtered
1766 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1767 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1768 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1769 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1770 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1771 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1772 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1773 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1774 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1775 printf_filtered
1776 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1777 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1778 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1779 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1780 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1781 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1782 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1783 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1784 printf_filtered
1785 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1786 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1787 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1788 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1789 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1790 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
da962468
CV		 1791}
1792
cc17453a 1793static void
c458d6db 1794sh3e_show_regs (struct frame_info *frame)
cc17453a 1795{
b47193f7 1796 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1797 printf_filtered
1798 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1799 phex (get_frame_register_unsigned (frame,
1800 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1801 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1802 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1803 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1804
1805 printf_filtered
1806 (" GBR %08lx VBR %08lx MACL %08lx\n",
1807 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1808 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1809 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1810 printf_filtered
1811 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1812 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1813 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1814 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1815 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
c906108c 1816
617daa0e 1817 printf_filtered
a6b0a3f3 1818 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1819 (long) get_frame_register_unsigned (frame, 0),
1820 (long) get_frame_register_unsigned (frame, 1),
1821 (long) get_frame_register_unsigned (frame, 2),
1822 (long) get_frame_register_unsigned (frame, 3),
1823 (long) get_frame_register_unsigned (frame, 4),
1824 (long) get_frame_register_unsigned (frame, 5),
1825 (long) get_frame_register_unsigned (frame, 6),
1826 (long) get_frame_register_unsigned (frame, 7));
1827 printf_filtered
1828 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1829 (long) get_frame_register_unsigned (frame, 8),
1830 (long) get_frame_register_unsigned (frame, 9),
1831 (long) get_frame_register_unsigned (frame, 10),
1832 (long) get_frame_register_unsigned (frame, 11),
1833 (long) get_frame_register_unsigned (frame, 12),
1834 (long) get_frame_register_unsigned (frame, 13),
1835 (long) get_frame_register_unsigned (frame, 14),
1836 (long) get_frame_register_unsigned (frame, 15));
1837
1838 printf_filtered
1839 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1840 (long) get_frame_register_unsigned
b47193f7 1841 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1842 (long) get_frame_register_unsigned
b47193f7 1843 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1844 (long) get_frame_register_unsigned
b47193f7 1845 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1846 (long) get_frame_register_unsigned
b47193f7 1847 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1848 (long) get_frame_register_unsigned
b47193f7 1849 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1850 (long) get_frame_register_unsigned
b47193f7 1851 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1852 (long) get_frame_register_unsigned
b47193f7 1853 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1854 (long) get_frame_register_unsigned
b47193f7 1855 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 1856 printf_filtered
1857 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1858 (long) get_frame_register_unsigned
b47193f7 1859 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 1860 (long) get_frame_register_unsigned
b47193f7 1861 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 1862 (long) get_frame_register_unsigned
b47193f7 1863 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 1864 (long) get_frame_register_unsigned
b47193f7 1865 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 1866 (long) get_frame_register_unsigned
b47193f7 1867 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 1868 (long) get_frame_register_unsigned
b47193f7 1869 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 1870 (long) get_frame_register_unsigned
b47193f7 1871 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 1872 (long) get_frame_register_unsigned
b47193f7 1873 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
cc17453a
EZ		 1874}
1875
1876static void
c458d6db 1877sh3_dsp_show_regs (struct frame_info *frame)
c906108c 1878{
c458d6db
UW		 1879 printf_filtered
1880 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1881 phex (get_frame_register_unsigned (frame,
1882 gdbarch_pc_regnum
1883 (get_frame_arch (frame))), 4),
c458d6db
UW		 1884 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1885 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1886 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
c906108c 1887
c458d6db
UW		 1888 printf_filtered
1889 (" GBR %08lx VBR %08lx MACL %08lx\n",
1890 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1891 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1892 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
cc17453a 1893
c458d6db
UW		 1894 printf_filtered
1895 (" SSR %08lx SPC %08lx DSR %08lx\n",
1896 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1897 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1898 (long) get_frame_register_unsigned (frame, DSR_REGNUM));
617daa0e
CV		 1899
1900 printf_filtered
a6b0a3f3 1901 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1902 (long) get_frame_register_unsigned (frame, 0),
1903 (long) get_frame_register_unsigned (frame, 1),
1904 (long) get_frame_register_unsigned (frame, 2),
1905 (long) get_frame_register_unsigned (frame, 3),
1906 (long) get_frame_register_unsigned (frame, 4),
1907 (long) get_frame_register_unsigned (frame, 5),
1908 (long) get_frame_register_unsigned (frame, 6),
1909 (long) get_frame_register_unsigned (frame, 7));
1910 printf_filtered
1911 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1912 (long) get_frame_register_unsigned (frame, 8),
1913 (long) get_frame_register_unsigned (frame, 9),
1914 (long) get_frame_register_unsigned (frame, 10),
1915 (long) get_frame_register_unsigned (frame, 11),
1916 (long) get_frame_register_unsigned (frame, 12),
1917 (long) get_frame_register_unsigned (frame, 13),
1918 (long) get_frame_register_unsigned (frame, 14),
1919 (long) get_frame_register_unsigned (frame, 15));
617daa0e
CV		 1920
1921 printf_filtered
1922 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
c458d6db
UW		 1923 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
1924 (long) get_frame_register_unsigned (frame, A0_REGNUM),
1925 (long) get_frame_register_unsigned (frame, M0_REGNUM),
1926 (long) get_frame_register_unsigned (frame, X0_REGNUM),
1927 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
1928 (long) get_frame_register_unsigned (frame, RS_REGNUM),
1929 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
1930 printf_filtered
1931 ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1932 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
1933 (long) get_frame_register_unsigned (frame, A1_REGNUM),
1934 (long) get_frame_register_unsigned (frame, M1_REGNUM),
1935 (long) get_frame_register_unsigned (frame, X1_REGNUM),
1936 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
1937 (long) get_frame_register_unsigned (frame, RE_REGNUM));
c906108c
SS		 1938}
1939
cc17453a 1940static void
c458d6db 1941sh4_show_regs (struct frame_info *frame)
cc17453a 1942{
b47193f7 1943 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1944 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1945
1946 printf_filtered
1947 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1948 phex (get_frame_register_unsigned (frame,
1949 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1950 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1951 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1952 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1953
1954 printf_filtered
1955 (" GBR %08lx VBR %08lx MACL %08lx\n",
1956 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1957 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1958 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1959 printf_filtered
1960 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1961 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1962 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1963 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1964 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1965
1966 printf_filtered
1967 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1968 (long) get_frame_register_unsigned (frame, 0),
1969 (long) get_frame_register_unsigned (frame, 1),
1970 (long) get_frame_register_unsigned (frame, 2),
1971 (long) get_frame_register_unsigned (frame, 3),
1972 (long) get_frame_register_unsigned (frame, 4),
1973 (long) get_frame_register_unsigned (frame, 5),
1974 (long) get_frame_register_unsigned (frame, 6),
1975 (long) get_frame_register_unsigned (frame, 7));
1976 printf_filtered
1977 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1978 (long) get_frame_register_unsigned (frame, 8),
1979 (long) get_frame_register_unsigned (frame, 9),
1980 (long) get_frame_register_unsigned (frame, 10),
1981 (long) get_frame_register_unsigned (frame, 11),
1982 (long) get_frame_register_unsigned (frame, 12),
1983 (long) get_frame_register_unsigned (frame, 13),
1984 (long) get_frame_register_unsigned (frame, 14),
1985 (long) get_frame_register_unsigned (frame, 15));
1986
1987 printf_filtered
1988 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1989 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1990 (long) get_frame_register_unsigned
b47193f7 1991 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1992 (long) get_frame_register_unsigned
b47193f7 1993 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1994 (long) get_frame_register_unsigned
b47193f7 1995 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1996 (long) get_frame_register_unsigned
b47193f7 1997 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1998 (long) get_frame_register_unsigned
b47193f7 1999 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 2000 (long) get_frame_register_unsigned
b47193f7 2001 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 2002 (long) get_frame_register_unsigned
b47193f7 2003 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 2004 (long) get_frame_register_unsigned
b47193f7 2005 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 2006 printf_filtered
2007 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2008 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 2009 (long) get_frame_register_unsigned
b47193f7 2010 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 2011 (long) get_frame_register_unsigned
b47193f7 2012 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 2013 (long) get_frame_register_unsigned
b47193f7 2014 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 2015 (long) get_frame_register_unsigned
b47193f7 2016 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 2017 (long) get_frame_register_unsigned
b47193f7 2018 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 2019 (long) get_frame_register_unsigned
b47193f7 2020 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 2021 (long) get_frame_register_unsigned
b47193f7 2022 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 2023 (long) get_frame_register_unsigned
b47193f7 2024 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
cc17453a
EZ		 2025}
2026
474e5826 2027static void
c458d6db 2028sh4_nofpu_show_regs (struct frame_info *frame)
474e5826 2029{
c458d6db
UW		 2030 printf_filtered
2031 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 2032 phex (get_frame_register_unsigned (frame,
2033 gdbarch_pc_regnum
2034 (get_frame_arch (frame))), 4),
c458d6db
UW		 2035 (long) get_frame_register_unsigned (frame, SR_REGNUM),
2036 (long) get_frame_register_unsigned (frame, PR_REGNUM),
2037 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
2038
2039 printf_filtered
2040 (" GBR %08lx VBR %08lx MACL %08lx\n",
2041 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2042 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2043 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
2044 printf_filtered
2045 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
2046 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
2047 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
2048 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
2049 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
2050
2051 printf_filtered
2052 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2053 (long) get_frame_register_unsigned (frame, 0),
2054 (long) get_frame_register_unsigned (frame, 1),
2055 (long) get_frame_register_unsigned (frame, 2),
2056 (long) get_frame_register_unsigned (frame, 3),
2057 (long) get_frame_register_unsigned (frame, 4),
2058 (long) get_frame_register_unsigned (frame, 5),
2059 (long) get_frame_register_unsigned (frame, 6),
2060 (long) get_frame_register_unsigned (frame, 7));
2061 printf_filtered
2062 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2063 (long) get_frame_register_unsigned (frame, 8),
2064 (long) get_frame_register_unsigned (frame, 9),
2065 (long) get_frame_register_unsigned (frame, 10),
2066 (long) get_frame_register_unsigned (frame, 11),
2067 (long) get_frame_register_unsigned (frame, 12),
2068 (long) get_frame_register_unsigned (frame, 13),
2069 (long) get_frame_register_unsigned (frame, 14),
2070 (long) get_frame_register_unsigned (frame, 15));
474e5826
CV		 2071}
2072
cc17453a 2073static void
c458d6db 2074sh_dsp_show_regs (struct frame_info *frame)
cc17453a 2075{
c458d6db
UW		 2076 printf_filtered
2077 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 2078 phex (get_frame_register_unsigned (frame,
2079 gdbarch_pc_regnum
2080 (get_frame_arch (frame))), 4),
c458d6db
UW		 2081 (long) get_frame_register_unsigned (frame, SR_REGNUM),
2082 (long) get_frame_register_unsigned (frame, PR_REGNUM),
2083 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
a6b0a3f3 2084
c458d6db
UW		 2085 printf_filtered
2086 (" GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n",
2087 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2088 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2089 (long) get_frame_register_unsigned (frame, DSR_REGNUM),
2090 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
617daa0e
CV		 2091
2092 printf_filtered
a6b0a3f3 2093 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 2094 (long) get_frame_register_unsigned (frame, 0),
2095 (long) get_frame_register_unsigned (frame, 1),
2096 (long) get_frame_register_unsigned (frame, 2),
2097 (long) get_frame_register_unsigned (frame, 3),
2098 (long) get_frame_register_unsigned (frame, 4),
2099 (long) get_frame_register_unsigned (frame, 5),
2100 (long) get_frame_register_unsigned (frame, 6),
2101 (long) get_frame_register_unsigned (frame, 7));
2102 printf_filtered
2103 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2104 (long) get_frame_register_unsigned (frame, 8),
2105 (long) get_frame_register_unsigned (frame, 9),
2106 (long) get_frame_register_unsigned (frame, 10),
2107 (long) get_frame_register_unsigned (frame, 11),
2108 (long) get_frame_register_unsigned (frame, 12),
2109 (long) get_frame_register_unsigned (frame, 13),
2110 (long) get_frame_register_unsigned (frame, 14),
2111 (long) get_frame_register_unsigned (frame, 15));
617daa0e
CV		 2112
2113 printf_filtered
2114 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
c458d6db
UW		 2115 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
2116 (long) get_frame_register_unsigned (frame, A0_REGNUM),
2117 (long) get_frame_register_unsigned (frame, M0_REGNUM),
2118 (long) get_frame_register_unsigned (frame, X0_REGNUM),
2119 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
2120 (long) get_frame_register_unsigned (frame, RS_REGNUM),
2121 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
cc17453a 2122 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
c458d6db
UW		 2123 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
2124 (long) get_frame_register_unsigned (frame, A1_REGNUM),
2125 (long) get_frame_register_unsigned (frame, M1_REGNUM),
2126 (long) get_frame_register_unsigned (frame, X1_REGNUM),
2127 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
2128 (long) get_frame_register_unsigned (frame, RE_REGNUM));
cc17453a
EZ		 2129}
2130
a78f21af
AC		 2131static void
2132sh_show_regs_command (char *args, int from_tty)
53116e27
EZ		 2133{
2134 if (sh_show_regs)
c458d6db 2135 (*sh_show_regs) (get_current_frame ());
53116e27
EZ		 2136}
2137
da962468
CV		 2138static struct type *
2139sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
2140{
b47193f7 2141 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
da962468 2142 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
0dfff4cb 2143 return builtin_type (gdbarch)->builtin_float;
da962468 2144 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
0dfff4cb 2145 return builtin_type (gdbarch)->builtin_double;
da962468 2146 else
0dfff4cb 2147 return builtin_type (gdbarch)->builtin_int;
da962468
CV		 2148}
2149
cc17453a
EZ		 2150/* Return the GDB type object for the "standard" data type
2151 of data in register N. */
cc17453a 2152static struct type *
48db5a3c 2153sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a 2154{
b47193f7 2155 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
617daa0e 2156 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
0dfff4cb 2157 return builtin_type (gdbarch)->builtin_float;
8db62801 2158 else
0dfff4cb 2159 return builtin_type (gdbarch)->builtin_int;
cc17453a
EZ		 2160}
2161
7f4dbe94 2162static struct type *
0dfff4cb 2163sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high)
7f4dbe94 2164{
e3506a9f
UW		 2165 return lookup_array_range_type (builtin_type (gdbarch)->builtin_float,
2166 0, high);
7f4dbe94
EZ		 2167}
2168
53116e27 2169static struct type *
48db5a3c 2170sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
53116e27 2171{
b47193f7 2172 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
617daa0e 2173 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
0dfff4cb 2174 return builtin_type (gdbarch)->builtin_float;
617daa0e 2175 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
0dfff4cb 2176 return builtin_type (gdbarch)->builtin_double;
617daa0e 2177 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
0dfff4cb 2178 return sh_sh4_build_float_register_type (gdbarch, 3);
53116e27 2179 else
0dfff4cb 2180 return builtin_type (gdbarch)->builtin_int;
53116e27
EZ		 2181}
2182
cc17453a 2183static struct type *
48db5a3c 2184sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a 2185{
0dfff4cb 2186 return builtin_type (gdbarch)->builtin_int;
cc17453a
EZ		 2187}
2188
dda63807
AS		 2189/* Is a register in a reggroup?
2190 The default code in reggroup.c doesn't identify system registers, some
2191 float registers or any of the vector registers.
2192 TODO: sh2a and dsp registers. */
63807e1d 2193static int
dda63807
AS		 2194sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2195 struct reggroup *reggroup)
2196{
b47193f7
UW		 2197 if (gdbarch_register_name (gdbarch, regnum) == NULL
2198 || *gdbarch_register_name (gdbarch, regnum) == '\0')
dda63807
AS		 2199 return 0;
2200
2201 if (reggroup == float_reggroup
2202 && (regnum == FPUL_REGNUM
2203 || regnum == FPSCR_REGNUM))
2204 return 1;
2205
2206 if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
2207 {
2208 if (reggroup == vector_reggroup || reggroup == float_reggroup)
2209 return 1;
2210 if (reggroup == general_reggroup)
2211 return 0;
2212 }
2213
2214 if (regnum == VBR_REGNUM
2215 || regnum == SR_REGNUM
2216 || regnum == FPSCR_REGNUM
2217 || regnum == SSR_REGNUM
2218 || regnum == SPC_REGNUM)
2219 {
2220 if (reggroup == system_reggroup)
2221 return 1;
2222 if (reggroup == general_reggroup)
2223 return 0;
2224 }
2225
2226 /* The default code can cope with any other registers. */
2227 return default_register_reggroup_p (gdbarch, regnum, reggroup);
2228}
2229
fb409745 2230/* On the sh4, the DRi pseudo registers are problematic if the target
c378eb4e 2231 is little endian. When the user writes one of those registers, for
fb409745
EZ		 2232 instance with 'ser var $dr0=1', we want the double to be stored
2233 like this:
2234 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2235 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2236
2237 This corresponds to little endian byte order & big endian word
2238 order. However if we let gdb write the register w/o conversion, it
2239 will write fr0 and fr1 this way:
2240 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2241 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2242 because it will consider fr0 and fr1 as a single LE stretch of memory.
2243
2244 To achieve what we want we must force gdb to store things in
2245 floatformat_ieee_double_littlebyte_bigword (which is defined in
2246 include/floatformat.h and libiberty/floatformat.c.
2247
2248 In case the target is big endian, there is no problem, the
2249 raw bytes will look like:
2250 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
2251 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2252
2253 The other pseudo registers (the FVs) also don't pose a problem
c378eb4e 2254 because they are stored as 4 individual FP elements. */
fb409745 2255
7bd872fe 2256static void
b66ba949
CV		 2257sh_register_convert_to_virtual (int regnum, struct type *type,
2258 char *from, char *to)
55ff77ac 2259{
617daa0e 2260 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
283150cd
EZ		 2261 {
2262 DOUBLEST val;
617daa0e
CV		 2263 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2264 from, &val);
55ff77ac 2265 store_typed_floating (to, type, val);
283150cd
EZ		 2266 }
2267 else
617daa0e
CV		 2268 error
2269 ("sh_register_convert_to_virtual called with non DR register number");
283150cd
EZ		 2270}
2271
2272static void
b66ba949
CV		 2273sh_register_convert_to_raw (struct type *type, int regnum,
2274 const void *from, void *to)
283150cd 2275{
617daa0e 2276 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
283150cd 2277 {
48db5a3c 2278 DOUBLEST val = extract_typed_floating (from, type);
617daa0e
CV		 2279 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2280 &val, to);
283150cd
EZ		 2281 }
2282 else
8a3fe4f8 2283 error (_("sh_register_convert_to_raw called with non DR register number"));
283150cd
EZ		 2284}
2285
c378eb4e 2286/* For vectors of 4 floating point registers. */
1c0159e0 2287static int
d93859e2 2288fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum)
1c0159e0
CV		 2289{
2290 int fp_regnum;
2291
d93859e2 2292 fp_regnum = gdbarch_fp0_regnum (gdbarch)
3e8c568d 2293 + (fv_regnum - FV0_REGNUM) * 4;
1c0159e0
CV		 2294 return fp_regnum;
2295}
2296
c378eb4e 2297/* For double precision floating point registers, i.e 2 fp regs. */
1c0159e0 2298static int
d93859e2 2299dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum)
1c0159e0
CV		 2300{
2301 int fp_regnum;
2302
d93859e2 2303 fp_regnum = gdbarch_fp0_regnum (gdbarch)
3e8c568d 2304 + (dr_regnum - DR0_REGNUM) * 2;
1c0159e0
CV		 2305 return fp_regnum;
2306}
2307
05d1431c
PA		 2308/* Concatenate PORTIONS contiguous raw registers starting at
2309 BASE_REGNUM into BUFFER. */
2310
2311static enum register_status
2312pseudo_register_read_portions (struct gdbarch *gdbarch,
2313 struct regcache *regcache,
2314 int portions,
2315 int base_regnum, gdb_byte *buffer)
2316{
2317 int portion;
2318
2319 for (portion = 0; portion < portions; portion++)
2320 {
2321 enum register_status status;
2322 gdb_byte *b;
2323
2324 b = buffer + register_size (gdbarch, base_regnum) * portion;
2325 status = regcache_raw_read (regcache, base_regnum + portion, b);
2326 if (status != REG_VALID)
2327 return status;
2328 }
2329
2330 return REG_VALID;
2331}
2332
2333static enum register_status
d8124050 2334sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
18cf8b5b 2335 int reg_nr, gdb_byte *buffer)
53116e27 2336{
05d1431c 2337 int base_regnum;
d9d9c31f 2338 char temp_buffer[MAX_REGISTER_SIZE];
05d1431c 2339 enum register_status status;
53116e27 2340
9bed62d7 2341 if (reg_nr == PSEUDO_BANK_REGNUM)
05d1431c
PA		 2342 return regcache_raw_read (regcache, BANK_REGNUM, buffer);
2343 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
7bd872fe 2344 {
d93859e2 2345 base_regnum = dr_reg_base_num (gdbarch, reg_nr);
7bd872fe 2346
c378eb4e 2347 /* Build the value in the provided buffer. */
7bd872fe 2348 /* Read the real regs for which this one is an alias. */
05d1431c
PA		 2349 status = pseudo_register_read_portions (gdbarch, regcache,
2350 2, base_regnum, temp_buffer);
2351 if (status == REG_VALID)
2352 {
2353 /* We must pay attention to the endiannes. */
2354 sh_register_convert_to_virtual (reg_nr,
2355 register_type (gdbarch, reg_nr),
2356 temp_buffer, buffer);
2357 }
2358 return status;
7bd872fe 2359 }
617daa0e 2360 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27 2361 {
d93859e2 2362 base_regnum = fv_reg_base_num (gdbarch, reg_nr);
7bd872fe
EZ		 2363
2364 /* Read the real regs for which this one is an alias. */
05d1431c
PA		 2365 return pseudo_register_read_portions (gdbarch, regcache,
2366 4, base_regnum, buffer);
53116e27 2367 }
05d1431c
PA		 2368 else
2369 gdb_assert_not_reached ("invalid pseudo register number");
53116e27
EZ		 2370}
2371
a78f21af 2372static void
d8124050 2373sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
18cf8b5b 2374 int reg_nr, const gdb_byte *buffer)
53116e27
EZ		 2375{
2376 int base_regnum, portion;
d9d9c31f 2377 char temp_buffer[MAX_REGISTER_SIZE];
53116e27 2378
9bed62d7
CV		 2379 if (reg_nr == PSEUDO_BANK_REGNUM)
2380 {
2381 /* When the bank register is written to, the whole register bank
2382 is switched and all values in the bank registers must be read
c378eb4e 2383 from the target/sim again. We're just invalidating the regcache
9bed62d7
CV		 2384 so that a re-read happens next time it's necessary. */
2385 int bregnum;
2386
2387 regcache_raw_write (regcache, BANK_REGNUM, buffer);
2388 for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum)
9c5ea4d9 2389 regcache_invalidate (regcache, bregnum);
9bed62d7
CV		 2390 }
2391 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
53116e27 2392 {
d93859e2 2393 base_regnum = dr_reg_base_num (gdbarch, reg_nr);
53116e27 2394
c378eb4e 2395 /* We must pay attention to the endiannes. */
7b9ee6a8 2396 sh_register_convert_to_raw (register_type (gdbarch, reg_nr),
b66ba949 2397 reg_nr, buffer, temp_buffer);
7bd872fe 2398
53116e27
EZ		 2399 /* Write the real regs for which this one is an alias. */
2400 for (portion = 0; portion < 2; portion++)
617daa0e 2401 regcache_raw_write (regcache, base_regnum + portion,
0818c12a 2402 (temp_buffer
617daa0e
CV		 2403 + register_size (gdbarch,
2404 base_regnum) * portion));
53116e27 2405 }
617daa0e 2406 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27 2407 {
d93859e2 2408 base_regnum = fv_reg_base_num (gdbarch, reg_nr);
53116e27
EZ		 2409
2410 /* Write the real regs for which this one is an alias. */
2411 for (portion = 0; portion < 4; portion++)
d8124050
AC		 2412 regcache_raw_write (regcache, base_regnum + portion,
2413 ((char *) buffer
617daa0e
CV		 2414 + register_size (gdbarch,
2415 base_regnum) * portion));
53116e27
EZ		 2416 }
2417}
2418
2f14585c 2419static int
e7faf938 2420sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr)
2f14585c 2421{
e7faf938
MD		 2422 if (legacy_register_sim_regno (gdbarch, nr) < 0)
2423 return legacy_register_sim_regno (gdbarch, nr);
f2ea0907
CV		 2424 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
2425 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
2426 if (nr == MOD_REGNUM)
2f14585c 2427 return SIM_SH_MOD_REGNUM;
f2ea0907 2428 if (nr == RS_REGNUM)
2f14585c 2429 return SIM_SH_RS_REGNUM;
f2ea0907 2430 if (nr == RE_REGNUM)
2f14585c 2431 return SIM_SH_RE_REGNUM;
76cd2bd9
CV		 2432 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
2433 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2f14585c
JR		 2434 return nr;
2435}
1c0159e0 2436
da962468 2437static int
e7faf938 2438sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr)
da962468
CV		 2439{
2440 switch (nr)
2441 {
2442 case TBR_REGNUM:
2443 return SIM_SH_TBR_REGNUM;
2444 case IBNR_REGNUM:
2445 return SIM_SH_IBNR_REGNUM;
2446 case IBCR_REGNUM:
2447 return SIM_SH_IBCR_REGNUM;
2448 case BANK_REGNUM:
2449 return SIM_SH_BANK_REGNUM;
2450 case MACLB_REGNUM:
2451 return SIM_SH_BANK_MACL_REGNUM;
2452 case GBRB_REGNUM:
2453 return SIM_SH_BANK_GBR_REGNUM;
2454 case PRB_REGNUM:
2455 return SIM_SH_BANK_PR_REGNUM;
2456 case IVNB_REGNUM:
2457 return SIM_SH_BANK_IVN_REGNUM;
2458 case MACHB_REGNUM:
2459 return SIM_SH_BANK_MACH_REGNUM;
2460 default:
2461 break;
2462 }
e7faf938 2463 return legacy_register_sim_regno (gdbarch, nr);
da962468
CV		 2464}
2465
357d3800
AS		 2466/* Set up the register unwinding such that call-clobbered registers are
2467 not displayed in frames >0 because the true value is not certain.
2468 The 'undefined' registers will show up as 'not available' unless the
2469 CFI says otherwise.
2470
2471 This function is currently set up for SH4 and compatible only. */
2472
2473static void
2474sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
aff37fc1 2475 struct dwarf2_frame_state_reg *reg,
4a4e5149 2476 struct frame_info *this_frame)
357d3800
AS		 2477{
2478 /* Mark the PC as the destination for the return address. */
b47193f7 2479 if (regnum == gdbarch_pc_regnum (gdbarch))
357d3800
AS		 2480 reg->how = DWARF2_FRAME_REG_RA;
2481
2482 /* Mark the stack pointer as the call frame address. */
b47193f7 2483 else if (regnum == gdbarch_sp_regnum (gdbarch))
357d3800
AS		 2484 reg->how = DWARF2_FRAME_REG_CFA;
2485
2486 /* The above was taken from the default init_reg in dwarf2-frame.c
2487 while the below is SH specific. */
2488
2489 /* Caller save registers. */
2490 else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7)
2491 || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11)
2492 || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5)
2493 || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2)
2494 || (regnum == MACH_REGNUM)
2495 || (regnum == MACL_REGNUM)
2496 || (regnum == FPUL_REGNUM)
2497 || (regnum == SR_REGNUM))
2498 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2499
2500 /* Callee save registers. */
2501 else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15)
2502 || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15)
2503 || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8)
2504 || (regnum == FV0_REGNUM+3))
2505 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
2506
2507 /* Other registers. These are not in the ABI and may or may not
2508 mean anything in frames >0 so don't show them. */
2509 else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15)
2510 || (regnum == GBR_REGNUM)
2511 || (regnum == VBR_REGNUM)
2512 || (regnum == FPSCR_REGNUM)
2513 || (regnum == SSR_REGNUM)
2514 || (regnum == SPC_REGNUM))
2515 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2516}
2517
1c0159e0
CV		 2518static struct sh_frame_cache *
2519sh_alloc_frame_cache (void)
2520{
2521 struct sh_frame_cache *cache;
2522 int i;
2523
2524 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
2525
2526 /* Base address. */
2527 cache->base = 0;
2528 cache->saved_sp = 0;
2529 cache->sp_offset = 0;
2530 cache->pc = 0;
2531
2532 /* Frameless until proven otherwise. */
2533 cache->uses_fp = 0;
617daa0e 2534
1c0159e0
CV		 2535 /* Saved registers. We initialize these to -1 since zero is a valid
2536 offset (that's where fp is supposed to be stored). */
2537 for (i = 0; i < SH_NUM_REGS; i++)
2538 {
2539 cache->saved_regs[i] = -1;
2540 }
617daa0e 2541
1c0159e0 2542 return cache;
617daa0e 2543}
1c0159e0
CV		 2544
2545static struct sh_frame_cache *
94afd7a6 2546sh_frame_cache (struct frame_info *this_frame, void **this_cache)
1c0159e0 2547{
e17a4113 2548 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1c0159e0
CV		 2549 struct sh_frame_cache *cache;
2550 CORE_ADDR current_pc;
2551 int i;
2552
2553 if (*this_cache)
2554 return *this_cache;
2555
2556 cache = sh_alloc_frame_cache ();
2557 *this_cache = cache;
2558
2559 /* In principle, for normal frames, fp holds the frame pointer,
2560 which holds the base address for the current stack frame.
2561 However, for functions that don't need it, the frame pointer is
2562 optional. For these "frameless" functions the frame pointer is
c378eb4e 2563 actually the frame pointer of the calling frame. */
94afd7a6 2564 cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM);
1c0159e0
CV		 2565 if (cache->base == 0)
2566 return cache;
2567
94afd7a6
UW		 2568 cache->pc = get_frame_func (this_frame);
2569 current_pc = get_frame_pc (this_frame);
1c0159e0 2570 if (cache->pc != 0)
d2ca4222
UW		 2571 {
2572 ULONGEST fpscr;
9fc05685
KB		 2573
2574 /* Check for the existence of the FPSCR register. If it exists,
2575 fetch its value for use in prologue analysis. Passing a zero
2576 value is the best choice for architecture variants upon which
2577 there's no FPSCR register. */
2578 if (gdbarch_register_reggroup_p (gdbarch, FPSCR_REGNUM, all_reggroup))
2579 fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM);
2580 else
2581 fpscr = 0;
2582
e17a4113 2583 sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, fpscr);
d2ca4222 2584 }
617daa0e 2585
1c0159e0
CV		 2586 if (!cache->uses_fp)
2587 {
2588 /* We didn't find a valid frame, which means that CACHE->base
2589 currently holds the frame pointer for our calling frame. If
2590 we're at the start of a function, or somewhere half-way its
2591 prologue, the function's frame probably hasn't been fully
2592 setup yet. Try to reconstruct the base address for the stack
2593 frame by looking at the stack pointer. For truly "frameless"
2594 functions this might work too. */
94afd7a6 2595 cache->base = get_frame_register_unsigned
e17a4113 2596 (this_frame, gdbarch_sp_regnum (gdbarch));
1c0159e0
CV		 2597 }
2598
2599 /* Now that we have the base address for the stack frame we can
2600 calculate the value of sp in the calling frame. */
2601 cache->saved_sp = cache->base + cache->sp_offset;
2602
2603 /* Adjust all the saved registers such that they contain addresses
2604 instead of offsets. */
2605 for (i = 0; i < SH_NUM_REGS; i++)
2606 if (cache->saved_regs[i] != -1)
2607 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
2608
2609 return cache;
2610}
2611
94afd7a6
UW		 2612static struct value *
2613sh_frame_prev_register (struct frame_info *this_frame,
2614 void **this_cache, int regnum)
1c0159e0 2615{
94afd7a6
UW		 2616 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2617 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
1c0159e0
CV		 2618
2619 gdb_assert (regnum >= 0);
2620
b47193f7 2621 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
94afd7a6 2622 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
1c0159e0
CV		 2623
2624 /* The PC of the previous frame is stored in the PR register of
2625 the current frame. Frob regnum so that we pull the value from
2626 the correct place. */
b47193f7 2627 if (regnum == gdbarch_pc_regnum (gdbarch))
1c0159e0
CV		 2628 regnum = PR_REGNUM;
2629
2630 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
94afd7a6
UW		 2631 return frame_unwind_got_memory (this_frame, regnum,
2632 cache->saved_regs[regnum]);
1c0159e0 2633
94afd7a6 2634 return frame_unwind_got_register (this_frame, regnum, regnum);
1c0159e0
CV		 2635}
2636
2637static void
94afd7a6 2638sh_frame_this_id (struct frame_info *this_frame, void **this_cache,
617daa0e
CV		 2639 struct frame_id *this_id)
2640{
94afd7a6 2641 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
1c0159e0
CV		 2642
2643 /* This marks the outermost frame. */
2644 if (cache->base == 0)
2645 return;
2646
2647 *this_id = frame_id_build (cache->saved_sp, cache->pc);
617daa0e 2648}
1c0159e0 2649
617daa0e 2650static const struct frame_unwind sh_frame_unwind = {
1c0159e0 2651 NORMAL_FRAME,
8fbca658 2652 default_frame_unwind_stop_reason,
1c0159e0 2653 sh_frame_this_id,
94afd7a6
UW		 2654 sh_frame_prev_register,
2655 NULL,
2656 default_frame_sniffer
1c0159e0
CV		 2657};
2658
1c0159e0
CV		 2659static CORE_ADDR
2660sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2661{
3e8c568d 2662 return frame_unwind_register_unsigned (next_frame,
b47193f7 2663 gdbarch_sp_regnum (gdbarch));
1c0159e0
CV		 2664}
2665
2666static CORE_ADDR
2667sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2668{
3e8c568d 2669 return frame_unwind_register_unsigned (next_frame,
b47193f7 2670 gdbarch_pc_regnum (gdbarch));
1c0159e0
CV		 2671}
2672
2673static struct frame_id
94afd7a6 2674sh_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1c0159e0 2675{
94afd7a6
UW		 2676 CORE_ADDR sp = get_frame_register_unsigned (this_frame,
2677 gdbarch_sp_regnum (gdbarch));
2678 return frame_id_build (sp, get_frame_pc (this_frame));
1c0159e0
CV		 2679}
2680
2681static CORE_ADDR
94afd7a6 2682sh_frame_base_address (struct frame_info *this_frame, void **this_cache)
617daa0e 2683{
94afd7a6 2684 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
617daa0e 2685
1c0159e0
CV		 2686 return cache->base;
2687}
617daa0e
CV		 2688
2689static const struct frame_base sh_frame_base = {
1c0159e0
CV		 2690 &sh_frame_unwind,
2691 sh_frame_base_address,
2692 sh_frame_base_address,
2693 sh_frame_base_address
617daa0e 2694};
1c0159e0 2695
cb2cf4ce
TS		 2696static struct sh_frame_cache *
2697sh_make_stub_cache (struct frame_info *this_frame)
2698{
2699 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2700 struct sh_frame_cache *cache;
2701
2702 cache = sh_alloc_frame_cache ();
2703
2704 cache->saved_sp
2705 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
2706
2707 return cache;
2708}
2709
2710static void
2711sh_stub_this_id (struct frame_info *this_frame, void **this_cache,
2712 struct frame_id *this_id)
2713{
2714 struct sh_frame_cache *cache;
2715
2716 if (*this_cache == NULL)
2717 *this_cache = sh_make_stub_cache (this_frame);
2718 cache = *this_cache;
2719
2720 *this_id = frame_id_build (cache->saved_sp, get_frame_pc (this_frame));
2721}
2722
2723static int
2724sh_stub_unwind_sniffer (const struct frame_unwind *self,
2725 struct frame_info *this_frame,
2726 void **this_prologue_cache)
2727{
2728 CORE_ADDR addr_in_block;
2729
2730 addr_in_block = get_frame_address_in_block (this_frame);
2731 if (in_plt_section (addr_in_block, NULL))
2732 return 1;
2733
2734 return 0;
2735}
2736
2737static const struct frame_unwind sh_stub_unwind =
2738{
2739 NORMAL_FRAME,
2740 default_frame_unwind_stop_reason,
2741 sh_stub_this_id,
2742 sh_frame_prev_register,
2743 NULL,
2744 sh_stub_unwind_sniffer
2745};
2746
1c0159e0
CV		 2747/* The epilogue is defined here as the area at the end of a function,
2748 either on the `ret' instruction itself or after an instruction which
c378eb4e 2749 destroys the function's stack frame. */
1c0159e0
CV		 2750static int
2751sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2752{
e17a4113 2753 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1c0159e0
CV		 2754 CORE_ADDR func_addr = 0, func_end = 0;
2755
2756 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2757 {
2758 ULONGEST inst;
2759 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2760 for a nop and some fixed data (e.g. big offsets) which are
617daa0e 2761 unfortunately also treated as part of the function (which
c378eb4e 2762 means, they are below func_end. */
1c0159e0
CV		 2763 CORE_ADDR addr = func_end - 28;
2764 if (addr < func_addr + 4)
617daa0e 2765 addr = func_addr + 4;
1c0159e0
CV		 2766 if (pc < addr)
2767 return 0;
2768
c378eb4e 2769 /* First search forward until hitting an rts. */
1c0159e0 2770 while (addr < func_end
e17a4113 2771 && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order)))
1c0159e0
CV		 2772 addr += 2;
2773 if (addr >= func_end)
617daa0e 2774 return 0;
1c0159e0
CV		 2775
2776 /* At this point we should find a mov.l @r15+,r14 instruction,
2777 either before or after the rts. If not, then the function has
c378eb4e 2778 probably no "normal" epilogue and we bail out here. */
e17a4113
UW		 2779 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2780 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2,
2781 byte_order)))
617daa0e 2782 addr -= 2;
e17a4113
UW		 2783 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2,
2784 byte_order)))
1c0159e0
CV		 2785 return 0;
2786
e17a4113 2787 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
03131d99 2788
c378eb4e 2789 /* Step over possible lds.l @r15+,macl. */
03131d99
CV		 2790 if (IS_MACL_LDS (inst))
2791 {
2792 addr -= 2;
e17a4113 2793 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
03131d99
CV		 2794 }
2795
c378eb4e 2796 /* Step over possible lds.l @r15+,pr. */
1c0159e0 2797 if (IS_LDS (inst))
617daa0e 2798 {
1c0159e0 2799 addr -= 2;
e17a4113 2800 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
1c0159e0
CV		 2801 }
2802
c378eb4e 2803 /* Step over possible mov r14,r15. */
1c0159e0 2804 if (IS_MOV_FP_SP (inst))
617daa0e 2805 {
1c0159e0 2806 addr -= 2;
e17a4113 2807 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
1c0159e0
CV		 2808 }
2809
2810 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
c378eb4e 2811 instructions. */
1c0159e0 2812 while (addr > func_addr + 4
617daa0e 2813 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
1c0159e0
CV		 2814 {
2815 addr -= 2;
e17a4113 2816 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
1c0159e0
CV		 2817 }
2818
03131d99
CV		 2819 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2820 That's allowed for the epilogue. */
2821 if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
2822 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
2823 && addr > func_addr + 6
e17a4113
UW		 2824 && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2,
2825 byte_order)))
03131d99
CV		 2826 addr -= 4;
2827
1c0159e0
CV		 2828 if (pc >= addr)
2829 return 1;
2830 }
2831 return 0;
2832}
c9ac0a72
AS		 2833
2834
2835/* Supply register REGNUM from the buffer specified by REGS and LEN
2836 in the register set REGSET to register cache REGCACHE.
2837 REGTABLE specifies where each register can be found in REGS.
2838 If REGNUM is -1, do this for all registers in REGSET. */
2839
2840void
2841sh_corefile_supply_regset (const struct regset *regset,
2842 struct regcache *regcache,
2843 int regnum, const void *regs, size_t len)
2844{
2845 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2846 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2847 const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
2848 ? tdep->core_gregmap
2849 : tdep->core_fpregmap);
2850 int i;
2851
2852 for (i = 0; regmap[i].regnum != -1; i++)
2853 {
2854 if ((regnum == -1 || regnum == regmap[i].regnum)
2855 && regmap[i].offset + 4 <= len)
2856 regcache_raw_supply (regcache, regmap[i].regnum,
2857 (char *)regs + regmap[i].offset);
2858 }
2859}
2860
2861/* Collect register REGNUM in the register set REGSET from register cache
2862 REGCACHE into the buffer specified by REGS and LEN.
2863 REGTABLE specifies where each register can be found in REGS.
2864 If REGNUM is -1, do this for all registers in REGSET. */
2865
2866void
2867sh_corefile_collect_regset (const struct regset *regset,
2868 const struct regcache *regcache,
2869 int regnum, void *regs, size_t len)
2870{
2871 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2872 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2873 const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
2874 ? tdep->core_gregmap
2875 : tdep->core_fpregmap);
2876 int i;
2877
2878 for (i = 0; regmap[i].regnum != -1; i++)
2879 {
2880 if ((regnum == -1 || regnum == regmap[i].regnum)
2881 && regmap[i].offset + 4 <= len)
2882 regcache_raw_collect (regcache, regmap[i].regnum,
2883 (char *)regs + regmap[i].offset);
2884 }
2885}
2886
2887/* The following two regsets have the same contents, so it is tempting to
2888 unify them, but they are distiguished by their address, so don't. */
2889
2890struct regset sh_corefile_gregset =
2891{
2892 NULL,
2893 sh_corefile_supply_regset,
2894 sh_corefile_collect_regset
2895};
2896
2897static struct regset sh_corefile_fpregset =
2898{
2899 NULL,
2900 sh_corefile_supply_regset,
2901 sh_corefile_collect_regset
2902};
2903
2904static const struct regset *
2905sh_regset_from_core_section (struct gdbarch *gdbarch, const char *sect_name,
2906 size_t sect_size)
2907{
2908 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2909
2910 if (tdep->core_gregmap && strcmp (sect_name, ".reg") == 0)
2911 return &sh_corefile_gregset;
2912
2913 if (tdep->core_fpregmap && strcmp (sect_name, ".reg2") == 0)
2914 return &sh_corefile_fpregset;
2915
2916 return NULL;
2917}
ccf00f21 2918\f
cc17453a
EZ		 2919
2920static struct gdbarch *
fba45db2 2921sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
cc17453a 2922{
cc17453a 2923 struct gdbarch *gdbarch;
c9ac0a72 2924 struct gdbarch_tdep *tdep;
d658f924 2925
55ff77ac
CV		 2926 sh_show_regs = sh_generic_show_regs;
2927 switch (info.bfd_arch_info->mach)
2928 {
617daa0e
CV		 2929 case bfd_mach_sh2e:
2930 sh_show_regs = sh2e_show_regs;
2931 break;
da962468
CV		 2932 case bfd_mach_sh2a:
2933 sh_show_regs = sh2a_show_regs;
2934 break;
2935 case bfd_mach_sh2a_nofpu:
2936 sh_show_regs = sh2a_nofpu_show_regs;
2937 break;
617daa0e
CV		 2938 case bfd_mach_sh_dsp:
2939 sh_show_regs = sh_dsp_show_regs;
2940 break;
55ff77ac 2941
617daa0e 2942 case bfd_mach_sh3:
46e8a76b
AS		 2943 case bfd_mach_sh3_nommu:
2944 case bfd_mach_sh2a_nofpu_or_sh3_nommu:
617daa0e
CV		 2945 sh_show_regs = sh3_show_regs;
2946 break;
55ff77ac 2947
617daa0e 2948 case bfd_mach_sh3e:
46e8a76b 2949 case bfd_mach_sh2a_or_sh3e:
617daa0e
CV		 2950 sh_show_regs = sh3e_show_regs;
2951 break;
55ff77ac 2952
617daa0e 2953 case bfd_mach_sh3_dsp:
474e5826 2954 case bfd_mach_sh4al_dsp:
617daa0e
CV		 2955 sh_show_regs = sh3_dsp_show_regs;
2956 break;
55ff77ac 2957
617daa0e 2958 case bfd_mach_sh4:
474e5826 2959 case bfd_mach_sh4a:
46e8a76b 2960 case bfd_mach_sh2a_or_sh4:
617daa0e
CV		 2961 sh_show_regs = sh4_show_regs;
2962 break;
55ff77ac 2963
474e5826 2964 case bfd_mach_sh4_nofpu:
46e8a76b 2965 case bfd_mach_sh4_nommu_nofpu:
474e5826 2966 case bfd_mach_sh4a_nofpu:
46e8a76b 2967 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
474e5826
CV		 2968 sh_show_regs = sh4_nofpu_show_regs;
2969 break;
2970
617daa0e
CV		 2971 case bfd_mach_sh5:
2972 sh_show_regs = sh64_show_regs;
c378eb4e 2973 /* SH5 is handled entirely in sh64-tdep.c. */
617daa0e 2974 return sh64_gdbarch_init (info, arches);
55ff77ac
CV		 2975 }
2976
4be87837
DJ		 2977 /* If there is already a candidate, use it. */
2978 arches = gdbarch_list_lookup_by_info (arches, &info);
2979 if (arches != NULL)
2980 return arches->gdbarch;
cc17453a
EZ		 2981
2982 /* None found, create a new architecture from the information
c378eb4e 2983 provided. */
c9ac0a72
AS		 2984 tdep = XZALLOC (struct gdbarch_tdep);
2985 gdbarch = gdbarch_alloc (&info, tdep);
cc17453a 2986
48db5a3c
CV		 2987 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2988 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
ec920329 2989 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c
CV		 2990 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2991 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2992 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2993 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
a38d2a54 2994 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c 2995
f2ea0907 2996 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
a38d2a54 2997 set_gdbarch_sp_regnum (gdbarch, 15);
a38d2a54 2998 set_gdbarch_pc_regnum (gdbarch, 16);
48db5a3c
CV		 2999 set_gdbarch_fp0_regnum (gdbarch, -1);
3000 set_gdbarch_num_pseudo_regs (gdbarch, 0);
3001
1c0159e0 3002 set_gdbarch_register_type (gdbarch, sh_default_register_type);
dda63807 3003 set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p);
1c0159e0 3004
eaf90c5d 3005 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
48db5a3c 3006
9dae60cc 3007 set_gdbarch_print_insn (gdbarch, print_insn_sh);
2f14585c 3008 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
48db5a3c 3009
c0409442 3010 set_gdbarch_return_value (gdbarch, sh_return_value_nofpu);
1c0159e0 3011
48db5a3c
CV		 3012 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
3013 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
48db5a3c 3014
1c0159e0
CV		 3015 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
3016
48db5a3c
CV		 3017 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3018
19f59343 3019 set_gdbarch_frame_align (gdbarch, sh_frame_align);
1c0159e0
CV		 3020 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
3021 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
94afd7a6 3022 set_gdbarch_dummy_id (gdbarch, sh_dummy_id);
1c0159e0
CV		 3023 frame_base_set_default (gdbarch, &sh_frame_base);
3024
617daa0e 3025 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
cc17453a 3026
357d3800
AS		 3027 dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg);
3028
c9ac0a72
AS		 3029 set_gdbarch_regset_from_core_section (gdbarch, sh_regset_from_core_section);
3030
cc17453a 3031 switch (info.bfd_arch_info->mach)
8db62801 3032 {
cc17453a 3033 case bfd_mach_sh:
48db5a3c 3034 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
cc17453a 3035 break;
1c0159e0 3036
cc17453a 3037 case bfd_mach_sh2:
48db5a3c 3038 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
617daa0e 3039 break;
1c0159e0 3040
2d188dd3 3041 case bfd_mach_sh2e:
c378eb4e 3042 /* doubles on sh2e and sh3e are actually 4 byte. */
48db5a3c
CV		 3043 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3044
3045 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
48db5a3c 3046 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2d188dd3 3047 set_gdbarch_fp0_regnum (gdbarch, 25);
c0409442 3048 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 3049 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2d188dd3 3050 break;
1c0159e0 3051
da962468
CV		 3052 case bfd_mach_sh2a:
3053 set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
3054 set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
3055 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
3056
3057 set_gdbarch_fp0_regnum (gdbarch, 25);
3058 set_gdbarch_num_pseudo_regs (gdbarch, 9);
3059 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
3060 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
c0409442 3061 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
da962468
CV		 3062 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
3063 break;
3064
3065 case bfd_mach_sh2a_nofpu:
3066 set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
3067 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
3068
3069 set_gdbarch_num_pseudo_regs (gdbarch, 1);
3070 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
3071 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
3072 break;
3073
cc17453a 3074 case bfd_mach_sh_dsp:
48db5a3c 3075 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2f14585c 3076 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a 3077 break;
1c0159e0 3078
cc17453a 3079 case bfd_mach_sh3:
4e6cbc38
AS		 3080 case bfd_mach_sh3_nommu:
3081 case bfd_mach_sh2a_nofpu_or_sh3_nommu:
48db5a3c 3082 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
cc17453a 3083 break;
1c0159e0 3084
cc17453a 3085 case bfd_mach_sh3e:
4e6cbc38 3086 case bfd_mach_sh2a_or_sh3e:
c378eb4e 3087 /* doubles on sh2e and sh3e are actually 4 byte. */
48db5a3c
CV		 3088 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3089
3090 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
48db5a3c 3091 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
cc17453a 3092 set_gdbarch_fp0_regnum (gdbarch, 25);
c0409442 3093 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 3094 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
cc17453a 3095 break;
1c0159e0 3096
cc17453a 3097 case bfd_mach_sh3_dsp:
48db5a3c 3098 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
48db5a3c 3099 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a 3100 break;
1c0159e0 3101
cc17453a 3102 case bfd_mach_sh4:
474e5826 3103 case bfd_mach_sh4a:
46e8a76b 3104 case bfd_mach_sh2a_or_sh4:
48db5a3c 3105 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
48db5a3c 3106 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
cc17453a 3107 set_gdbarch_fp0_regnum (gdbarch, 25);
da962468 3108 set_gdbarch_num_pseudo_regs (gdbarch, 13);
d8124050
AC		 3109 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
3110 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
c0409442 3111 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 3112 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
cc17453a 3113 break;
1c0159e0 3114
474e5826
CV		 3115 case bfd_mach_sh4_nofpu:
3116 case bfd_mach_sh4a_nofpu:
4e6cbc38
AS		 3117 case bfd_mach_sh4_nommu_nofpu:
3118 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
474e5826
CV		 3119 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
3120 break;
3121
3122 case bfd_mach_sh4al_dsp:
3123 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
3124 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
3125 break;
3126
cc17453a 3127 default:
b58cbbf2 3128 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
cc17453a 3129 break;
8db62801 3130 }
cc17453a 3131
4be87837
DJ		 3132 /* Hook in ABI-specific overrides, if they have been registered. */
3133 gdbarch_init_osabi (info, gdbarch);
d658f924 3134
94afd7a6 3135 dwarf2_append_unwinders (gdbarch);
cb2cf4ce 3136 frame_unwind_append_unwinder (gdbarch, &sh_stub_unwind);
94afd7a6 3137 frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind);
1c0159e0 3138
cc17453a 3139 return gdbarch;
8db62801
EZ		 3140}
3141
c055b101
CV		 3142static void
3143show_sh_command (char *args, int from_tty)
3144{
3145 help_list (showshcmdlist, "show sh ", all_commands, gdb_stdout);
3146}
3147
3148static void
3149set_sh_command (char *args, int from_tty)
3150{
3151 printf_unfiltered
3152 ("\"set sh\" must be followed by an appropriate subcommand.\n");
3153 help_list (setshcmdlist, "set sh ", all_commands, gdb_stdout);
3154}
3155
c378eb4e 3156extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
a78f21af 3157
c906108c 3158void
fba45db2 3159_initialize_sh_tdep (void)
c906108c
SS		 3160{
3161 struct cmd_list_element *c;
617daa0e 3162
f2ea0907 3163 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
c906108c 3164
1bedd215 3165 add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers"));
c055b101
CV		 3166
3167 add_prefix_cmd ("sh", no_class, set_sh_command, "SH specific commands.",
3168 &setshcmdlist, "set sh ", 0, &setlist);
3169 add_prefix_cmd ("sh", no_class, show_sh_command, "SH specific commands.",
3170 &showshcmdlist, "show sh ", 0, &showlist);
3171
3172 add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum,
3173 &sh_active_calling_convention,
3174 _("Set calling convention used when calling target "
3175 "functions from GDB."),
3176 _("Show calling convention used when calling target "
3177 "functions from GDB."),
3178 _("gcc - Use GCC calling convention (default).\n"
3179 "renesas - Enforce Renesas calling convention."),
3180 NULL, NULL,
3181 &setshcmdlist, &showshcmdlist);
c906108c 3182}
GDB Binutils - Deliverables
This page took 1.715486 seconds and 4 git commands to generate.