2003-10-10 Dave Brolley <brolley@redhat.com>
[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
CommitLineData
85a453d5 1/* Target-dependent code for Renesas Super-H, for GDB.
1e698235 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3116c80a 3 Free Software Foundation, Inc.
c906108c 4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
c906108c 11
c5aa993b
JM
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b
JM
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
c906108c
SS
21
22/*
c5aa993b
JM
23 Contributed by Steve Chamberlain
24 sac@cygnus.com
c906108c
SS
25 */
26
27#include "defs.h"
28#include "frame.h"
1c0159e0
CV
29#include "frame-base.h"
30#include "frame-unwind.h"
31#include "dwarf2-frame.h"
c906108c
SS
32#include "symtab.h"
33#include "symfile.h"
34#include "gdbtypes.h"
35#include "gdbcmd.h"
36#include "gdbcore.h"
37#include "value.h"
38#include "dis-asm.h"
73c1f219 39#include "inferior.h"
c906108c 40#include "gdb_string.h"
1c0159e0 41#include "gdb_assert.h"
b4a20239 42#include "arch-utils.h"
fb409745 43#include "floatformat.h"
4e052eda 44#include "regcache.h"
d16aafd8 45#include "doublest.h"
4be87837 46#include "osabi.h"
c906108c 47
ab3b8126
JT
48#include "sh-tdep.h"
49
d658f924 50#include "elf-bfd.h"
1a8629c7
MS
51#include "solib-svr4.h"
52
55ff77ac 53/* sh flags */
283150cd
EZ
54#include "elf/sh.h"
55/* registers numbers shared with the simulator */
1c922164 56#include "gdb/sim-sh.h"
283150cd 57
55ff77ac 58static void (*sh_show_regs) (void);
cc17453a 59
f2ea0907 60#define SH_NUM_REGS 59
88e04cc1 61
1c0159e0 62struct sh_frame_cache
cc17453a 63{
1c0159e0
CV
64 /* Base address. */
65 CORE_ADDR base;
66 LONGEST sp_offset;
67 CORE_ADDR pc;
68
69 /* Flag showing that a frame has been created in the prologue code. */
70 int uses_fp;
71
72 /* Saved registers. */
73 CORE_ADDR saved_regs[SH_NUM_REGS];
74 CORE_ADDR saved_sp;
63978407 75};
c906108c 76
fa88f677 77static const char *
cc17453a 78sh_generic_register_name (int reg_nr)
c5aa993b 79{
617daa0e
CV
80 static char *register_names[] = {
81 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
82 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
83 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
cc17453a 84 "fpul", "fpscr",
617daa0e
CV
85 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
86 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
87 "ssr", "spc",
cc17453a
EZ
88 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
89 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
90 };
91 if (reg_nr < 0)
92 return NULL;
93 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
94 return NULL;
95 return register_names[reg_nr];
96}
97
fa88f677 98static const char *
cc17453a
EZ
99sh_sh_register_name (int reg_nr)
100{
617daa0e
CV
101 static char *register_names[] = {
102 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
103 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
104 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
105 "", "",
106 "", "", "", "", "", "", "", "",
107 "", "", "", "", "", "", "", "",
108 "", "",
109 "", "", "", "", "", "", "", "",
110 "", "", "", "", "", "", "", "",
cc17453a
EZ
111 };
112 if (reg_nr < 0)
113 return NULL;
114 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
115 return NULL;
116 return register_names[reg_nr];
117}
118
fa88f677 119static const char *
cc17453a
EZ
120sh_sh3_register_name (int reg_nr)
121{
617daa0e
CV
122 static char *register_names[] = {
123 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
124 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
125 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
126 "", "",
127 "", "", "", "", "", "", "", "",
128 "", "", "", "", "", "", "", "",
129 "ssr", "spc",
cc17453a
EZ
130 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
131 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
132 };
133 if (reg_nr < 0)
134 return NULL;
135 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
136 return NULL;
137 return register_names[reg_nr];
138}
139
fa88f677 140static const char *
cc17453a
EZ
141sh_sh3e_register_name (int reg_nr)
142{
617daa0e
CV
143 static char *register_names[] = {
144 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
145 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
146 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
cc17453a 147 "fpul", "fpscr",
617daa0e
CV
148 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
149 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
150 "ssr", "spc",
cc17453a
EZ
151 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
152 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
153 };
154 if (reg_nr < 0)
155 return NULL;
156 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
157 return NULL;
158 return register_names[reg_nr];
159}
160
2d188dd3
NC
161static const char *
162sh_sh2e_register_name (int reg_nr)
163{
617daa0e
CV
164 static char *register_names[] = {
165 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
166 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
167 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
2d188dd3 168 "fpul", "fpscr",
617daa0e
CV
169 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
170 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
171 "", "",
2d188dd3
NC
172 "", "", "", "", "", "", "", "",
173 "", "", "", "", "", "", "", "",
174 };
175 if (reg_nr < 0)
176 return NULL;
177 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
178 return NULL;
179 return register_names[reg_nr];
180}
181
fa88f677 182static const char *
cc17453a
EZ
183sh_sh_dsp_register_name (int reg_nr)
184{
617daa0e
CV
185 static char *register_names[] = {
186 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
187 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
188 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
189 "", "dsr",
190 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
191 "y0", "y1", "", "", "", "", "", "mod",
192 "", "",
193 "rs", "re", "", "", "", "", "", "",
194 "", "", "", "", "", "", "", "",
cc17453a
EZ
195 };
196 if (reg_nr < 0)
197 return NULL;
198 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
199 return NULL;
200 return register_names[reg_nr];
201}
202
fa88f677 203static const char *
cc17453a
EZ
204sh_sh3_dsp_register_name (int reg_nr)
205{
617daa0e
CV
206 static char *register_names[] = {
207 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
208 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
209 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
210 "", "dsr",
211 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
212 "y0", "y1", "", "", "", "", "", "mod",
213 "ssr", "spc",
214 "rs", "re", "", "", "", "", "", "",
215 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
216 "", "", "", "", "", "", "", "",
cc17453a
EZ
217 };
218 if (reg_nr < 0)
219 return NULL;
220 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
221 return NULL;
222 return register_names[reg_nr];
223}
224
fa88f677 225static const char *
53116e27
EZ
226sh_sh4_register_name (int reg_nr)
227{
617daa0e 228 static char *register_names[] = {
a38d2a54 229 /* general registers 0-15 */
617daa0e
CV
230 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
231 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
a38d2a54 232 /* 16 - 22 */
617daa0e 233 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
a38d2a54 234 /* 23, 24 */
53116e27 235 "fpul", "fpscr",
a38d2a54 236 /* floating point registers 25 - 40 */
617daa0e
CV
237 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
238 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
a38d2a54 239 /* 41, 42 */
617daa0e 240 "ssr", "spc",
a38d2a54 241 /* bank 0 43 - 50 */
53116e27 242 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
a38d2a54 243 /* bank 1 51 - 58 */
53116e27 244 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
a38d2a54 245 /* double precision (pseudo) 59 - 66 */
617daa0e 246 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
a38d2a54 247 /* vectors (pseudo) 67 - 70 */
617daa0e 248 "fv0", "fv4", "fv8", "fv12",
a38d2a54
EZ
249 /* FIXME: missing XF 71 - 86 */
250 /* FIXME: missing XD 87 - 94 */
53116e27
EZ
251 };
252 if (reg_nr < 0)
253 return NULL;
254 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
255 return NULL;
256 return register_names[reg_nr];
257}
258
3117ed25 259static const unsigned char *
fba45db2 260sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
cc17453a
EZ
261{
262 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
617daa0e
CV
263 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
264
cc17453a
EZ
265 *lenptr = sizeof (breakpoint);
266 return breakpoint;
267}
c906108c
SS
268
269/* Prologue looks like
1c0159e0
CV
270 mov.l r14,@-r15
271 sts.l pr,@-r15
272 mov.l <regs>,@-r15
273 sub <room_for_loca_vars>,r15
274 mov r15,r14
8db62801 275
1c0159e0 276 Actually it can be more complicated than this but that's it, basically.
c5aa993b 277 */
c906108c 278
1c0159e0
CV
279#define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
280#define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
281
8db62801
EZ
282/* STS.L PR,@-r15 0100111100100010
283 r15-4-->r15, PR-->(r15) */
c906108c 284#define IS_STS(x) ((x) == 0x4f22)
8db62801
EZ
285
286/* MOV.L Rm,@-r15 00101111mmmm0110
287 r15-4-->r15, Rm-->(R15) */
c906108c 288#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 289
8db62801
EZ
290/* MOV r15,r14 0110111011110011
291 r15-->r14 */
c906108c 292#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ
293
294/* ADD #imm,r15 01111111iiiiiiii
295 r15+imm-->r15 */
1c0159e0 296#define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 297
c906108c
SS
298#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
299#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ
300
301/* ADD r3,r15 0011111100111100
302 r15+r3-->r15 */
c906108c 303#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ
304
305/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
8db62801 306 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
8db62801 307 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
f2ea0907
CV
308/* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
309 make this entirely clear. */
1c0159e0
CV
310/* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
311#define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
312
313/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
314#define IS_MOV_ARG_TO_REG(x) \
315 (((x) & 0xf00f) == 0x6003 && \
316 ((x) & 0x00f0) >= 0x0040 && \
317 ((x) & 0x00f0) <= 0x0070)
318/* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
319#define IS_MOV_ARG_TO_IND_R14(x) \
320 (((x) & 0xff0f) == 0x2e02 && \
321 ((x) & 0x00f0) >= 0x0040 && \
322 ((x) & 0x00f0) <= 0x0070)
323/* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
324#define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
325 (((x) & 0xff00) == 0x1e00 && \
326 ((x) & 0x00f0) >= 0x0040 && \
327 ((x) & 0x00f0) <= 0x0070)
328
329/* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
330#define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
331/* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
332#define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
333/* SUB Rn,R15 00111111nnnn1000 */
334#define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
8db62801 335
1c0159e0 336#define FPSCR_SZ (1 << 20)
cc17453a 337
1c0159e0
CV
338/* The following instructions are used for epilogue testing. */
339#define IS_RESTORE_FP(x) ((x) == 0x6ef6)
340#define IS_RTS(x) ((x) == 0x000b)
341#define IS_LDS(x) ((x) == 0x4f26)
342#define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
343#define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
344#define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
cc17453a 345
cc17453a
EZ
346/* Disassemble an instruction. */
347static int
617daa0e 348gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
c906108c 349{
1c509ca8
JR
350 info->endian = TARGET_BYTE_ORDER;
351 return print_insn_sh (memaddr, info);
283150cd
EZ
352}
353
cc17453a 354static CORE_ADDR
1c0159e0
CV
355sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
356 struct sh_frame_cache *cache)
617daa0e 357{
1c0159e0
CV
358 ULONGEST inst;
359 CORE_ADDR opc;
360 int offset;
361 int sav_offset = 0;
c906108c 362 int r3_val = 0;
1c0159e0 363 int reg, sav_reg = -1;
cc17453a 364
1c0159e0
CV
365 if (pc >= current_pc)
366 return current_pc;
cc17453a 367
1c0159e0 368 cache->uses_fp = 0;
cc17453a
EZ
369 for (opc = pc + (2 * 28); pc < opc; pc += 2)
370 {
1c0159e0 371 inst = read_memory_unsigned_integer (pc, 2);
cc17453a 372 /* See where the registers will be saved to */
f2ea0907 373 if (IS_PUSH (inst))
cc17453a 374 {
1c0159e0
CV
375 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
376 cache->sp_offset += 4;
cc17453a 377 }
f2ea0907 378 else if (IS_STS (inst))
cc17453a 379 {
1c0159e0
CV
380 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
381 cache->sp_offset += 4;
cc17453a 382 }
f2ea0907 383 else if (IS_MOV_R3 (inst))
cc17453a 384 {
f2ea0907 385 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
cc17453a 386 }
f2ea0907 387 else if (IS_SHLL_R3 (inst))
cc17453a
EZ
388 {
389 r3_val <<= 1;
390 }
f2ea0907 391 else if (IS_ADD_R3SP (inst))
cc17453a 392 {
1c0159e0 393 cache->sp_offset += -r3_val;
cc17453a 394 }
f2ea0907 395 else if (IS_ADD_IMM_SP (inst))
cc17453a 396 {
1c0159e0
CV
397 offset = ((inst & 0xff) ^ 0x80) - 0x80;
398 cache->sp_offset -= offset;
c906108c 399 }
1c0159e0 400 else if (IS_MOVW_PCREL_TO_REG (inst))
617daa0e 401 {
1c0159e0
CV
402 if (sav_reg < 0)
403 {
404 reg = GET_TARGET_REG (inst);
405 if (reg < 14)
406 {
407 sav_reg = reg;
408 offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
409 sav_offset =
617daa0e 410 read_memory_integer (((pc + 4) & ~3) + offset, 2);
1c0159e0
CV
411 }
412 }
c906108c 413 }
1c0159e0 414 else if (IS_MOVL_PCREL_TO_REG (inst))
617daa0e 415 {
1c0159e0
CV
416 if (sav_reg < 0)
417 {
418 reg = (inst & 0x0f00) >> 8;
419 if (reg < 14)
420 {
421 sav_reg = reg;
422 offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
423 sav_offset =
617daa0e 424 read_memory_integer (((pc + 4) & ~3) + offset, 4);
1c0159e0
CV
425 }
426 }
c906108c 427 }
1c0159e0 428 else if (IS_SUB_REG_FROM_SP (inst))
617daa0e 429 {
1c0159e0
CV
430 reg = GET_SOURCE_REG (inst);
431 if (sav_reg > 0 && reg == sav_reg)
432 {
433 sav_reg = -1;
434 }
435 cache->sp_offset += sav_offset;
c906108c 436 }
f2ea0907 437 else if (IS_FPUSH (inst))
c906108c 438 {
f2ea0907 439 if (read_register (FPSCR_REGNUM) & FPSCR_SZ)
c906108c 440 {
1c0159e0 441 cache->sp_offset += 8;
c906108c
SS
442 }
443 else
444 {
1c0159e0 445 cache->sp_offset += 4;
c906108c
SS
446 }
447 }
f2ea0907 448 else if (IS_MOV_SP_FP (inst))
617daa0e 449 {
1c0159e0
CV
450 if (!cache->uses_fp)
451 cache->uses_fp = 1;
452 /* At this point, only allow argument register moves to other
453 registers or argument register moves to @(X,fp) which are
454 moving the register arguments onto the stack area allocated
455 by a former add somenumber to SP call. Don't allow moving
456 to an fp indirect address above fp + cache->sp_offset. */
457 pc += 2;
458 for (opc = pc + 12; pc < opc; pc += 2)
459 {
460 inst = read_memory_integer (pc, 2);
461 if (IS_MOV_ARG_TO_IND_R14 (inst))
617daa0e 462 {
1c0159e0
CV
463 reg = GET_SOURCE_REG (inst);
464 if (cache->sp_offset > 0)
617daa0e 465 cache->saved_regs[reg] = cache->sp_offset;
1c0159e0
CV
466 }
467 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
617daa0e 468 {
1c0159e0
CV
469 reg = GET_SOURCE_REG (inst);
470 offset = (inst & 0xf) * 4;
471 if (cache->sp_offset > offset)
472 cache->saved_regs[reg] = cache->sp_offset - offset;
473 }
474 else if (IS_MOV_ARG_TO_REG (inst))
617daa0e 475 continue;
1c0159e0
CV
476 else
477 break;
478 }
479 break;
480 }
617daa0e
CV
481#if 0 /* This used to just stop when it found an instruction that
482 was not considered part of the prologue. Now, we just
483 keep going looking for likely instructions. */
c906108c
SS
484 else
485 break;
2bfa91ee 486#endif
c906108c
SS
487 }
488
1c0159e0
CV
489 return pc;
490}
c906108c 491
1c0159e0 492/* Skip any prologue before the guts of a function */
c906108c 493
1c0159e0
CV
494/* Skip the prologue using the debug information. If this fails we'll
495 fall back on the 'guess' method below. */
496static CORE_ADDR
497after_prologue (CORE_ADDR pc)
498{
499 struct symtab_and_line sal;
500 CORE_ADDR func_addr, func_end;
c906108c 501
1c0159e0
CV
502 /* If we can not find the symbol in the partial symbol table, then
503 there is no hope we can determine the function's start address
504 with this code. */
505 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
506 return 0;
c906108c 507
1c0159e0
CV
508 /* Get the line associated with FUNC_ADDR. */
509 sal = find_pc_line (func_addr, 0);
510
511 /* There are only two cases to consider. First, the end of the source line
512 is within the function bounds. In that case we return the end of the
513 source line. Second is the end of the source line extends beyond the
514 bounds of the current function. We need to use the slow code to
515 examine instructions in that case. */
516 if (sal.end < func_end)
517 return sal.end;
518 else
519 return 0;
c906108c
SS
520}
521
1c0159e0
CV
522static CORE_ADDR
523sh_skip_prologue (CORE_ADDR start_pc)
c906108c 524{
1c0159e0
CV
525 CORE_ADDR pc;
526 struct sh_frame_cache cache;
527
528 /* See if we can determine the end of the prologue via the symbol table.
529 If so, then return either PC, or the PC after the prologue, whichever
530 is greater. */
531 pc = after_prologue (start_pc);
cc17453a 532
1c0159e0
CV
533 /* If after_prologue returned a useful address, then use it. Else
534 fall back on the instruction skipping code. */
535 if (pc)
536 return max (pc, start_pc);
c906108c 537
1c0159e0
CV
538 cache.sp_offset = -4;
539 pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache);
540 if (!cache.uses_fp)
541 return start_pc;
c906108c 542
1c0159e0
CV
543 return pc;
544}
545
9a5cef92
EZ
546/* Should call_function allocate stack space for a struct return?
547
548 The ABI says:
549
550 Aggregate types not bigger than 8 bytes that have the same size and
551 alignment as one of the integer scalar types are returned in the
552 same registers as the integer type they match.
553
554 For example, a 2-byte aligned structure with size 2 bytes has the
555 same size and alignment as a short int, and will be returned in R0.
556 A 4-byte aligned structure with size 8 bytes has the same size and
557 alignment as a long long int, and will be returned in R0 and R1.
558
559 When an aggregate type is returned in R0 and R1, R0 contains the
560 first four bytes of the aggregate, and R1 contains the
561 remainder. If the size of the aggregate type is not a multiple of 4
562 bytes, the aggregate is tail-padded up to a multiple of 4
563 bytes. The value of the padding is undefined. For little-endian
564 targets the padding will appear at the most significant end of the
565 last element, for big-endian targets the padding appears at the
566 least significant end of the last element.
567
568 All other aggregate types are returned by address. The caller
569 function passes the address of an area large enough to hold the
570 aggregate value in R2. The called function stores the result in
7fe958be 571 this location.
9a5cef92
EZ
572
573 To reiterate, structs smaller than 8 bytes could also be returned
574 in memory, if they don't pass the "same size and alignment as an
575 integer type" rule.
576
577 For example, in
578
579 struct s { char c[3]; } wibble;
580 struct s foo(void) { return wibble; }
581
582 the return value from foo() will be in memory, not
583 in R0, because there is no 3-byte integer type.
584
7fe958be
EZ
585 Similarly, in
586
587 struct s { char c[2]; } wibble;
588 struct s foo(void) { return wibble; }
589
590 because a struct containing two chars has alignment 1, that matches
591 type char, but size 2, that matches type short. There's no integer
592 type that has alignment 1 and size 2, so the struct is returned in
593 memory.
594
9a5cef92
EZ
595*/
596
1c0159e0
CV
597static int
598sh_use_struct_convention (int gcc_p, struct type *type)
599{
600 int len = TYPE_LENGTH (type);
601 int nelem = TYPE_NFIELDS (type);
3f997a97
CV
602
603 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
604 fit in two registers anyway) use struct convention. */
605 if (len != 1 && len != 2 && len != 4 && len != 8)
606 return 1;
607
608 /* Scalar types and aggregate types with exactly one field are aligned
609 by definition. They are returned in registers. */
610 if (nelem <= 1)
611 return 0;
612
613 /* If the first field in the aggregate has the same length as the entire
614 aggregate type, the type is returned in registers. */
615 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
616 return 0;
617
618 /* If the size of the aggregate is 8 bytes and the first field is
619 of size 4 bytes its alignment is equal to long long's alignment,
620 so it's returned in registers. */
621 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
622 return 0;
623
624 /* Otherwise use struct convention. */
625 return 1;
283150cd
EZ
626}
627
cc17453a
EZ
628/* Extract from an array REGBUF containing the (raw) register state
629 the address in which a function should return its structure value,
630 as a CORE_ADDR (or an expression that can be used as one). */
b3df3fff 631static CORE_ADDR
48db5a3c 632sh_extract_struct_value_address (struct regcache *regcache)
cc17453a 633{
48db5a3c 634 ULONGEST addr;
1c0159e0 635
48db5a3c
CV
636 regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
637 return addr;
cc17453a
EZ
638}
639
19f59343
MS
640static CORE_ADDR
641sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
642{
643 return sp & ~3;
644}
645
55ff77ac 646/* Function: push_dummy_call (formerly push_arguments)
c906108c
SS
647 Setup the function arguments for calling a function in the inferior.
648
85a453d5 649 On the Renesas SH architecture, there are four registers (R4 to R7)
c906108c
SS
650 which are dedicated for passing function arguments. Up to the first
651 four arguments (depending on size) may go into these registers.
652 The rest go on the stack.
653
6df2bf50
MS
654 MVS: Except on SH variants that have floating point registers.
655 In that case, float and double arguments are passed in the same
656 manner, but using FP registers instead of GP registers.
657
c906108c
SS
658 Arguments that are smaller than 4 bytes will still take up a whole
659 register or a whole 32-bit word on the stack, and will be
660 right-justified in the register or the stack word. This includes
661 chars, shorts, and small aggregate types.
662
663 Arguments that are larger than 4 bytes may be split between two or
664 more registers. If there are not enough registers free, an argument
665 may be passed partly in a register (or registers), and partly on the
666 stack. This includes doubles, long longs, and larger aggregates.
667 As far as I know, there is no upper limit to the size of aggregates
668 that will be passed in this way; in other words, the convention of
669 passing a pointer to a large aggregate instead of a copy is not used.
670
6df2bf50 671 MVS: The above appears to be true for the SH variants that do not
55ff77ac 672 have an FPU, however those that have an FPU appear to copy the
6df2bf50
MS
673 aggregate argument onto the stack (and not place it in registers)
674 if it is larger than 16 bytes (four GP registers).
675
c906108c
SS
676 An exceptional case exists for struct arguments (and possibly other
677 aggregates such as arrays) if the size is larger than 4 bytes but
678 not a multiple of 4 bytes. In this case the argument is never split
679 between the registers and the stack, but instead is copied in its
680 entirety onto the stack, AND also copied into as many registers as
681 there is room for. In other words, space in registers permitting,
682 two copies of the same argument are passed in. As far as I can tell,
683 only the one on the stack is used, although that may be a function
684 of the level of compiler optimization. I suspect this is a compiler
685 bug. Arguments of these odd sizes are left-justified within the
686 word (as opposed to arguments smaller than 4 bytes, which are
687 right-justified).
c5aa993b 688
c906108c
SS
689 If the function is to return an aggregate type such as a struct, it
690 is either returned in the normal return value register R0 (if its
691 size is no greater than one byte), or else the caller must allocate
692 space into which the callee will copy the return value (if the size
693 is greater than one byte). In this case, a pointer to the return
694 value location is passed into the callee in register R2, which does
695 not displace any of the other arguments passed in via registers R4
696 to R7. */
697
e5e33cd9
CV
698/* Helper function to justify value in register according to endianess. */
699static char *
700sh_justify_value_in_reg (struct value *val, int len)
701{
702 static char valbuf[4];
703
617daa0e 704 memset (valbuf, 0, sizeof (valbuf));
e5e33cd9
CV
705 if (len < 4)
706 {
707 /* value gets right-justified in the register or stack word */
708 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
709 memcpy (valbuf + (4 - len), (char *) VALUE_CONTENTS (val), len);
710 else
711 memcpy (valbuf, (char *) VALUE_CONTENTS (val), len);
712 return valbuf;
713 }
714 return (char *) VALUE_CONTENTS (val);
617daa0e 715}
e5e33cd9
CV
716
717/* Helper function to eval number of bytes to allocate on stack. */
718static CORE_ADDR
719sh_stack_allocsize (int nargs, struct value **args)
720{
721 int stack_alloc = 0;
722 while (nargs-- > 0)
723 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[nargs])) + 3) & ~3);
724 return stack_alloc;
725}
726
727/* Helper functions for getting the float arguments right. Registers usage
728 depends on the ABI and the endianess. The comments should enlighten how
729 it's intended to work. */
730
731/* This array stores which of the float arg registers are already in use. */
732static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
733
734/* This function just resets the above array to "no reg used so far". */
735static void
736sh_init_flt_argreg (void)
737{
738 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
739}
740
741/* This function returns the next register to use for float arg passing.
742 It returns either a valid value between FLOAT_ARG0_REGNUM and
743 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
744 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
745
746 Note that register number 0 in flt_argreg_array corresponds with the
747 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
748 29) the parity of the register number is preserved, which is important
749 for the double register passing test (see the "argreg & 1" test below). */
750static int
751sh_next_flt_argreg (int len)
752{
753 int argreg;
754
755 /* First search for the next free register. */
617daa0e
CV
756 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
757 ++argreg)
e5e33cd9
CV
758 if (!flt_argreg_array[argreg])
759 break;
760
761 /* No register left? */
762 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
763 return FLOAT_ARGLAST_REGNUM + 1;
764
765 if (len == 8)
766 {
767 /* Doubles are always starting in a even register number. */
768 if (argreg & 1)
617daa0e 769 {
e5e33cd9
CV
770 flt_argreg_array[argreg] = 1;
771
772 ++argreg;
773
617daa0e 774 /* No register left? */
e5e33cd9
CV
775 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
776 return FLOAT_ARGLAST_REGNUM + 1;
777 }
778 /* Also mark the next register as used. */
779 flt_argreg_array[argreg + 1] = 1;
780 }
781 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
782 {
783 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
784 if (!flt_argreg_array[argreg + 1])
785 ++argreg;
786 }
787 flt_argreg_array[argreg] = 1;
788 return FLOAT_ARG0_REGNUM + argreg;
789}
790
cc17453a 791static CORE_ADDR
617daa0e 792sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
6df2bf50 793 CORE_ADDR func_addr,
617daa0e 794 struct regcache *regcache,
6df2bf50 795 CORE_ADDR bp_addr, int nargs,
617daa0e 796 struct value **args,
6df2bf50
MS
797 CORE_ADDR sp, int struct_return,
798 CORE_ADDR struct_addr)
799{
e5e33cd9
CV
800 int stack_offset = 0;
801 int argreg = ARG0_REGNUM;
8748518b 802 int flt_argreg = 0;
6df2bf50
MS
803 int argnum;
804 struct type *type;
805 CORE_ADDR regval;
806 char *val;
8748518b 807 int len, reg_size = 0;
e5e33cd9 808 int pass_on_stack;
6df2bf50
MS
809
810 /* first force sp to a 4-byte alignment */
811 sp = sh_frame_align (gdbarch, sp);
812
6df2bf50 813 if (struct_return)
1c0159e0 814 regcache_cooked_write_unsigned (regcache,
617daa0e 815 STRUCT_RETURN_REGNUM, struct_addr);
6df2bf50 816
e5e33cd9
CV
817 /* make room on stack for args */
818 sp -= sh_stack_allocsize (nargs, args);
819
820 /* Initialize float argument mechanism. */
821 sh_init_flt_argreg ();
6df2bf50
MS
822
823 /* Now load as many as possible of the first arguments into
824 registers, and push the rest onto the stack. There are 16 bytes
825 in four registers available. Loop thru args from first to last. */
e5e33cd9 826 for (argnum = 0; argnum < nargs; argnum++)
6df2bf50
MS
827 {
828 type = VALUE_TYPE (args[argnum]);
829 len = TYPE_LENGTH (type);
e5e33cd9
CV
830 val = sh_justify_value_in_reg (args[argnum], len);
831
832 /* Some decisions have to be made how various types are handled.
833 This also differs in different ABIs. */
834 pass_on_stack = 0;
835 if (len > 16)
617daa0e 836 pass_on_stack = 1; /* Types bigger than 16 bytes are passed on stack. */
e5e33cd9
CV
837
838 /* Find out the next register to use for a floating point value. */
839 if (TYPE_CODE (type) == TYPE_CODE_FLT)
617daa0e 840 flt_argreg = sh_next_flt_argreg (len);
48db5a3c 841
6df2bf50
MS
842 while (len > 0)
843 {
617daa0e 844 if ((TYPE_CODE (type) == TYPE_CODE_FLT
e5e33cd9 845 && flt_argreg > FLOAT_ARGLAST_REGNUM)
617daa0e
CV
846 || argreg > ARGLAST_REGNUM || pass_on_stack)
847 {
e5e33cd9
CV
848 /* The remainder of the data goes entirely on the stack,
849 4-byte aligned. */
850 reg_size = (len + 3) & ~3;
851 write_memory (sp + stack_offset, val, reg_size);
852 stack_offset += reg_size;
6df2bf50 853 }
e5e33cd9
CV
854 else if (TYPE_CODE (type) == TYPE_CODE_FLT
855 && flt_argreg <= FLOAT_ARGLAST_REGNUM)
6df2bf50 856 {
e5e33cd9
CV
857 /* Argument goes in a float argument register. */
858 reg_size = register_size (gdbarch, flt_argreg);
859 regval = extract_unsigned_integer (val, reg_size);
6df2bf50
MS
860 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
861 }
55ff77ac 862 else if (argreg <= ARGLAST_REGNUM)
e5e33cd9 863 {
6df2bf50 864 /* there's room in a register */
e5e33cd9
CV
865 reg_size = register_size (gdbarch, argreg);
866 regval = extract_unsigned_integer (val, reg_size);
6df2bf50
MS
867 regcache_cooked_write_unsigned (regcache, argreg++, regval);
868 }
e5e33cd9
CV
869 /* Store the value reg_size bytes at a time. This means that things
870 larger than reg_size bytes may go partly in registers and partly
6df2bf50 871 on the stack. */
e5e33cd9
CV
872 len -= reg_size;
873 val += reg_size;
6df2bf50
MS
874 }
875 }
876
877 /* Store return address. */
55ff77ac 878 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
6df2bf50
MS
879
880 /* Update stack pointer. */
881 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
882
883 return sp;
884}
885
886static CORE_ADDR
617daa0e 887sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
6df2bf50 888 CORE_ADDR func_addr,
617daa0e
CV
889 struct regcache *regcache,
890 CORE_ADDR bp_addr,
891 int nargs, struct value **args,
892 CORE_ADDR sp, int struct_return,
6df2bf50 893 CORE_ADDR struct_addr)
c906108c 894{
e5e33cd9
CV
895 int stack_offset = 0;
896 int argreg = ARG0_REGNUM;
c906108c
SS
897 int argnum;
898 struct type *type;
899 CORE_ADDR regval;
900 char *val;
e5e33cd9 901 int len, reg_size;
c906108c
SS
902
903 /* first force sp to a 4-byte alignment */
19f59343 904 sp = sh_frame_align (gdbarch, sp);
c906108c 905
c906108c 906 if (struct_return)
55ff77ac 907 regcache_cooked_write_unsigned (regcache,
617daa0e 908 STRUCT_RETURN_REGNUM, struct_addr);
c906108c 909
e5e33cd9
CV
910 /* make room on stack for args */
911 sp -= sh_stack_allocsize (nargs, args);
c906108c 912
c906108c
SS
913 /* Now load as many as possible of the first arguments into
914 registers, and push the rest onto the stack. There are 16 bytes
915 in four registers available. Loop thru args from first to last. */
e5e33cd9 916 for (argnum = 0; argnum < nargs; argnum++)
617daa0e 917 {
c906108c 918 type = VALUE_TYPE (args[argnum]);
c5aa993b 919 len = TYPE_LENGTH (type);
e5e33cd9 920 val = sh_justify_value_in_reg (args[argnum], len);
c906108c 921
c906108c
SS
922 while (len > 0)
923 {
e5e33cd9 924 if (argreg > ARGLAST_REGNUM)
617daa0e 925 {
e5e33cd9
CV
926 /* The remainder of the data goes entirely on the stack,
927 4-byte aligned. */
928 reg_size = (len + 3) & ~3;
929 write_memory (sp + stack_offset, val, reg_size);
617daa0e 930 stack_offset += reg_size;
c906108c 931 }
e5e33cd9 932 else if (argreg <= ARGLAST_REGNUM)
617daa0e 933 {
3bbfbb92 934 /* there's room in a register */
e5e33cd9
CV
935 reg_size = register_size (gdbarch, argreg);
936 regval = extract_unsigned_integer (val, reg_size);
48db5a3c 937 regcache_cooked_write_unsigned (regcache, argreg++, regval);
c906108c 938 }
e5e33cd9
CV
939 /* Store the value reg_size bytes at a time. This means that things
940 larger than reg_size bytes may go partly in registers and partly
c906108c 941 on the stack. */
e5e33cd9
CV
942 len -= reg_size;
943 val += reg_size;
c906108c
SS
944 }
945 }
48db5a3c
CV
946
947 /* Store return address. */
55ff77ac 948 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
48db5a3c
CV
949
950 /* Update stack pointer. */
951 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
952
c906108c
SS
953 return sp;
954}
955
cc17453a
EZ
956/* Find a function's return value in the appropriate registers (in
957 regbuf), and copy it into valbuf. Extract from an array REGBUF
958 containing the (raw) register state a function return value of type
959 TYPE, and copy that, in virtual format, into VALBUF. */
960static void
48db5a3c
CV
961sh_default_extract_return_value (struct type *type, struct regcache *regcache,
962 void *valbuf)
c906108c 963{
cc17453a 964 int len = TYPE_LENGTH (type);
3116c80a
EZ
965 int return_register = R0_REGNUM;
966 int offset;
617daa0e 967
cc17453a 968 if (len <= 4)
3116c80a 969 {
48db5a3c
CV
970 ULONGEST c;
971
972 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
973 store_unsigned_integer (valbuf, len, c);
3116c80a 974 }
48db5a3c 975 else if (len == 8)
3116c80a 976 {
48db5a3c
CV
977 int i, regnum = R0_REGNUM;
978 for (i = 0; i < len; i += 4)
617daa0e 979 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
3116c80a
EZ
980 }
981 else
982 error ("bad size for return value");
983}
984
985static void
48db5a3c
CV
986sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache,
987 void *valbuf)
3116c80a 988{
3116c80a 989 if (TYPE_CODE (type) == TYPE_CODE_FLT)
3116c80a 990 {
48db5a3c
CV
991 int len = TYPE_LENGTH (type);
992 int i, regnum = FP0_REGNUM;
993 for (i = 0; i < len; i += 4)
617daa0e 994 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
3116c80a 995 }
cc17453a 996 else
48db5a3c 997 sh_default_extract_return_value (type, regcache, valbuf);
cc17453a 998}
c906108c 999
cc17453a
EZ
1000/* Write into appropriate registers a function return value
1001 of type TYPE, given in virtual format.
1002 If the architecture is sh4 or sh3e, store a function's return value
1003 in the R0 general register or in the FP0 floating point register,
1004 depending on the type of the return value. In all the other cases
3bbfbb92 1005 the result is stored in r0, left-justified. */
cc17453a 1006static void
48db5a3c
CV
1007sh_default_store_return_value (struct type *type, struct regcache *regcache,
1008 const void *valbuf)
cc17453a 1009{
48db5a3c
CV
1010 ULONGEST val;
1011 int len = TYPE_LENGTH (type);
d19b71be 1012
48db5a3c 1013 if (len <= 4)
d19b71be 1014 {
48db5a3c
CV
1015 val = extract_unsigned_integer (valbuf, len);
1016 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
d19b71be
MS
1017 }
1018 else
48db5a3c
CV
1019 {
1020 int i, regnum = R0_REGNUM;
1021 for (i = 0; i < len; i += 4)
617daa0e 1022 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
48db5a3c 1023 }
cc17453a 1024}
c906108c 1025
cc17453a 1026static void
48db5a3c
CV
1027sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache,
1028 const void *valbuf)
cc17453a 1029{
617daa0e 1030 if (TYPE_CODE (type) == TYPE_CODE_FLT)
48db5a3c
CV
1031 {
1032 int len = TYPE_LENGTH (type);
1033 int i, regnum = FP0_REGNUM;
1034 for (i = 0; i < len; i += 4)
617daa0e 1035 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
48db5a3c 1036 }
cc17453a 1037 else
48db5a3c 1038 sh_default_store_return_value (type, regcache, valbuf);
c906108c
SS
1039}
1040
1041/* Print the registers in a form similar to the E7000 */
1042
1043static void
fba45db2 1044sh_generic_show_regs (void)
c906108c 1045{
cc17453a
EZ
1046 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1047 paddr (read_register (PC_REGNUM)),
55ff77ac
CV
1048 (long) read_register (SR_REGNUM),
1049 (long) read_register (PR_REGNUM),
cc17453a
EZ
1050 (long) read_register (MACH_REGNUM),
1051 (long) read_register (MACL_REGNUM));
1052
1053 printf_filtered ("GBR=%08lx VBR=%08lx",
1054 (long) read_register (GBR_REGNUM),
1055 (long) read_register (VBR_REGNUM));
1056
617daa0e
CV
1057 printf_filtered
1058 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1059 (long) read_register (0), (long) read_register (1),
1060 (long) read_register (2), (long) read_register (3),
1061 (long) read_register (4), (long) read_register (5),
1062 (long) read_register (6), (long) read_register (7));
cc17453a 1063 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV
1064 (long) read_register (8), (long) read_register (9),
1065 (long) read_register (10), (long) read_register (11),
1066 (long) read_register (12), (long) read_register (13),
1067 (long) read_register (14), (long) read_register (15));
cc17453a 1068}
c906108c 1069
cc17453a 1070static void
fba45db2 1071sh3_show_regs (void)
cc17453a 1072{
d4f3574e
SS
1073 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1074 paddr (read_register (PC_REGNUM)),
55ff77ac
CV
1075 (long) read_register (SR_REGNUM),
1076 (long) read_register (PR_REGNUM),
d4f3574e
SS
1077 (long) read_register (MACH_REGNUM),
1078 (long) read_register (MACL_REGNUM));
1079
1080 printf_filtered ("GBR=%08lx VBR=%08lx",
1081 (long) read_register (GBR_REGNUM),
1082 (long) read_register (VBR_REGNUM));
cc17453a 1083 printf_filtered (" SSR=%08lx SPC=%08lx",
617daa0e 1084 (long) read_register (SSR_REGNUM),
f2ea0907 1085 (long) read_register (SPC_REGNUM));
c906108c 1086
617daa0e
CV
1087 printf_filtered
1088 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1089 (long) read_register (0), (long) read_register (1),
1090 (long) read_register (2), (long) read_register (3),
1091 (long) read_register (4), (long) read_register (5),
1092 (long) read_register (6), (long) read_register (7));
d4f3574e 1093 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV
1094 (long) read_register (8), (long) read_register (9),
1095 (long) read_register (10), (long) read_register (11),
1096 (long) read_register (12), (long) read_register (13),
1097 (long) read_register (14), (long) read_register (15));
c906108c
SS
1098}
1099
53116e27 1100
2d188dd3
NC
1101static void
1102sh2e_show_regs (void)
1103{
1104 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1105 paddr (read_register (PC_REGNUM)),
1106 (long) read_register (SR_REGNUM),
1107 (long) read_register (PR_REGNUM),
1108 (long) read_register (MACH_REGNUM),
1109 (long) read_register (MACL_REGNUM));
1110
1111 printf_filtered ("GBR=%08lx VBR=%08lx",
1112 (long) read_register (GBR_REGNUM),
1113 (long) read_register (VBR_REGNUM));
1114 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
617daa0e
CV
1115 (long) read_register (FPUL_REGNUM),
1116 (long) read_register (FPSCR_REGNUM));
1117
1118 printf_filtered
1119 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1120 (long) read_register (0), (long) read_register (1),
1121 (long) read_register (2), (long) read_register (3),
1122 (long) read_register (4), (long) read_register (5),
1123 (long) read_register (6), (long) read_register (7));
2d188dd3 1124 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV
1125 (long) read_register (8), (long) read_register (9),
1126 (long) read_register (10), (long) read_register (11),
1127 (long) read_register (12), (long) read_register (13),
1128 (long) read_register (14), (long) read_register (15));
1129
1130 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1131 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
2d188dd3
NC
1132}
1133
cc17453a 1134static void
fba45db2 1135sh3e_show_regs (void)
cc17453a
EZ
1136{
1137 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1138 paddr (read_register (PC_REGNUM)),
55ff77ac
CV
1139 (long) read_register (SR_REGNUM),
1140 (long) read_register (PR_REGNUM),
cc17453a
EZ
1141 (long) read_register (MACH_REGNUM),
1142 (long) read_register (MACL_REGNUM));
1143
1144 printf_filtered ("GBR=%08lx VBR=%08lx",
1145 (long) read_register (GBR_REGNUM),
1146 (long) read_register (VBR_REGNUM));
1147 printf_filtered (" SSR=%08lx SPC=%08lx",
f2ea0907
CV
1148 (long) read_register (SSR_REGNUM),
1149 (long) read_register (SPC_REGNUM));
cc17453a 1150 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
f2ea0907
CV
1151 (long) read_register (FPUL_REGNUM),
1152 (long) read_register (FPSCR_REGNUM));
c906108c 1153
617daa0e
CV
1154 printf_filtered
1155 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1156 (long) read_register (0), (long) read_register (1),
1157 (long) read_register (2), (long) read_register (3),
1158 (long) read_register (4), (long) read_register (5),
1159 (long) read_register (6), (long) read_register (7));
cc17453a 1160 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV
1161 (long) read_register (8), (long) read_register (9),
1162 (long) read_register (10), (long) read_register (11),
1163 (long) read_register (12), (long) read_register (13),
1164 (long) read_register (14), (long) read_register (15));
1165
1166 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1167 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
cc17453a
EZ
1168}
1169
1170static void
fba45db2 1171sh3_dsp_show_regs (void)
c906108c 1172{
cc17453a
EZ
1173 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1174 paddr (read_register (PC_REGNUM)),
55ff77ac
CV
1175 (long) read_register (SR_REGNUM),
1176 (long) read_register (PR_REGNUM),
cc17453a
EZ
1177 (long) read_register (MACH_REGNUM),
1178 (long) read_register (MACL_REGNUM));
c906108c 1179
cc17453a
EZ
1180 printf_filtered ("GBR=%08lx VBR=%08lx",
1181 (long) read_register (GBR_REGNUM),
1182 (long) read_register (VBR_REGNUM));
1183
1184 printf_filtered (" SSR=%08lx SPC=%08lx",
f2ea0907
CV
1185 (long) read_register (SSR_REGNUM),
1186 (long) read_register (SPC_REGNUM));
cc17453a 1187
617daa0e
CV
1188 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1189
1190 printf_filtered
1191 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1192 (long) read_register (0), (long) read_register (1),
1193 (long) read_register (2), (long) read_register (3),
1194 (long) read_register (4), (long) read_register (5),
1195 (long) read_register (6), (long) read_register (7));
cc17453a 1196 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV
1197 (long) read_register (8), (long) read_register (9),
1198 (long) read_register (10), (long) read_register (11),
1199 (long) read_register (12), (long) read_register (13),
1200 (long) read_register (14), (long) read_register (15));
1201
1202 printf_filtered
1203 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1204 (long) read_register (A0G_REGNUM) & 0xff,
1205 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1206 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1207 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
cc17453a 1208 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
f2ea0907
CV
1209 (long) read_register (A1G_REGNUM) & 0xff,
1210 (long) read_register (A1_REGNUM),
1211 (long) read_register (M1_REGNUM),
1212 (long) read_register (X1_REGNUM),
1213 (long) read_register (Y1_REGNUM),
1214 (long) read_register (RE_REGNUM));
c906108c
SS
1215}
1216
cc17453a 1217static void
fba45db2 1218sh4_show_regs (void)
cc17453a 1219{
f2ea0907 1220 int pr = read_register (FPSCR_REGNUM) & 0x80000;
cc17453a
EZ
1221 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1222 paddr (read_register (PC_REGNUM)),
55ff77ac
CV
1223 (long) read_register (SR_REGNUM),
1224 (long) read_register (PR_REGNUM),
cc17453a
EZ
1225 (long) read_register (MACH_REGNUM),
1226 (long) read_register (MACL_REGNUM));
1227
1228 printf_filtered ("GBR=%08lx VBR=%08lx",
1229 (long) read_register (GBR_REGNUM),
1230 (long) read_register (VBR_REGNUM));
1231 printf_filtered (" SSR=%08lx SPC=%08lx",
f2ea0907
CV
1232 (long) read_register (SSR_REGNUM),
1233 (long) read_register (SPC_REGNUM));
cc17453a 1234 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
f2ea0907
CV
1235 (long) read_register (FPUL_REGNUM),
1236 (long) read_register (FPSCR_REGNUM));
cc17453a 1237
617daa0e
CV
1238 printf_filtered
1239 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1240 (long) read_register (0), (long) read_register (1),
1241 (long) read_register (2), (long) read_register (3),
1242 (long) read_register (4), (long) read_register (5),
1243 (long) read_register (6), (long) read_register (7));
cc17453a 1244 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV
1245 (long) read_register (8), (long) read_register (9),
1246 (long) read_register (10), (long) read_register (11),
1247 (long) read_register (12), (long) read_register (13),
1248 (long) read_register (14), (long) read_register (15));
cc17453a
EZ
1249
1250 printf_filtered ((pr
1251 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
617daa0e
CV
1252 :
1253 "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
cc17453a
EZ
1254 (long) read_register (FP0_REGNUM + 0),
1255 (long) read_register (FP0_REGNUM + 1),
1256 (long) read_register (FP0_REGNUM + 2),
1257 (long) read_register (FP0_REGNUM + 3),
1258 (long) read_register (FP0_REGNUM + 4),
1259 (long) read_register (FP0_REGNUM + 5),
1260 (long) read_register (FP0_REGNUM + 6),
1261 (long) read_register (FP0_REGNUM + 7));
617daa0e
CV
1262 printf_filtered ((pr ?
1263 "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" :
1264 "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
cc17453a
EZ
1265 (long) read_register (FP0_REGNUM + 8),
1266 (long) read_register (FP0_REGNUM + 9),
1267 (long) read_register (FP0_REGNUM + 10),
1268 (long) read_register (FP0_REGNUM + 11),
1269 (long) read_register (FP0_REGNUM + 12),
1270 (long) read_register (FP0_REGNUM + 13),
1271 (long) read_register (FP0_REGNUM + 14),
1272 (long) read_register (FP0_REGNUM + 15));
1273}
1274
1275static void
fba45db2 1276sh_dsp_show_regs (void)
cc17453a
EZ
1277{
1278 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1279 paddr (read_register (PC_REGNUM)),
55ff77ac
CV
1280 (long) read_register (SR_REGNUM),
1281 (long) read_register (PR_REGNUM),
cc17453a
EZ
1282 (long) read_register (MACH_REGNUM),
1283 (long) read_register (MACL_REGNUM));
1284
1285 printf_filtered ("GBR=%08lx VBR=%08lx",
1286 (long) read_register (GBR_REGNUM),
1287 (long) read_register (VBR_REGNUM));
1288
617daa0e
CV
1289 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1290
1291 printf_filtered
1292 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1293 (long) read_register (0), (long) read_register (1),
1294 (long) read_register (2), (long) read_register (3),
1295 (long) read_register (4), (long) read_register (5),
1296 (long) read_register (6), (long) read_register (7));
cc17453a 1297 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV
1298 (long) read_register (8), (long) read_register (9),
1299 (long) read_register (10), (long) read_register (11),
1300 (long) read_register (12), (long) read_register (13),
1301 (long) read_register (14), (long) read_register (15));
1302
1303 printf_filtered
1304 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1305 (long) read_register (A0G_REGNUM) & 0xff,
1306 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1307 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1308 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
cc17453a 1309 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
f2ea0907
CV
1310 (long) read_register (A1G_REGNUM) & 0xff,
1311 (long) read_register (A1_REGNUM),
1312 (long) read_register (M1_REGNUM),
1313 (long) read_register (X1_REGNUM),
1314 (long) read_register (Y1_REGNUM),
1315 (long) read_register (RE_REGNUM));
cc17453a
EZ
1316}
1317
a78f21af
AC
1318static void
1319sh_show_regs_command (char *args, int from_tty)
53116e27
EZ
1320{
1321 if (sh_show_regs)
617daa0e 1322 (*sh_show_regs) ();
53116e27
EZ
1323}
1324
cc17453a
EZ
1325/* Return the GDB type object for the "standard" data type
1326 of data in register N. */
cc17453a 1327static struct type *
48db5a3c 1328sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a
EZ
1329{
1330 if ((reg_nr >= FP0_REGNUM
617daa0e 1331 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
cc17453a 1332 return builtin_type_float;
8db62801 1333 else
cc17453a
EZ
1334 return builtin_type_int;
1335}
1336
7f4dbe94
EZ
1337static struct type *
1338sh_sh4_build_float_register_type (int high)
1339{
1340 struct type *temp;
1341
1342 temp = create_range_type (NULL, builtin_type_int, 0, high);
1343 return create_array_type (NULL, builtin_type_float, temp);
1344}
1345
53116e27 1346static struct type *
48db5a3c 1347sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
53116e27
EZ
1348{
1349 if ((reg_nr >= FP0_REGNUM
617daa0e 1350 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
53116e27 1351 return builtin_type_float;
617daa0e 1352 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
53116e27 1353 return builtin_type_double;
617daa0e 1354 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27
EZ
1355 return sh_sh4_build_float_register_type (3);
1356 else
1357 return builtin_type_int;
1358}
1359
cc17453a 1360static struct type *
48db5a3c 1361sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a
EZ
1362{
1363 return builtin_type_int;
1364}
1365
fb409745
EZ
1366/* On the sh4, the DRi pseudo registers are problematic if the target
1367 is little endian. When the user writes one of those registers, for
1368 instance with 'ser var $dr0=1', we want the double to be stored
1369 like this:
1370 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1371 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1372
1373 This corresponds to little endian byte order & big endian word
1374 order. However if we let gdb write the register w/o conversion, it
1375 will write fr0 and fr1 this way:
1376 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1377 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1378 because it will consider fr0 and fr1 as a single LE stretch of memory.
1379
1380 To achieve what we want we must force gdb to store things in
1381 floatformat_ieee_double_littlebyte_bigword (which is defined in
1382 include/floatformat.h and libiberty/floatformat.c.
1383
1384 In case the target is big endian, there is no problem, the
1385 raw bytes will look like:
1386 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1387 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1388
1389 The other pseudo registers (the FVs) also don't pose a problem
1390 because they are stored as 4 individual FP elements. */
1391
7bd872fe 1392static void
fb409745 1393sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
617daa0e 1394 char *from, char *to)
55ff77ac 1395{
617daa0e 1396 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
283150cd
EZ
1397 {
1398 DOUBLEST val;
617daa0e
CV
1399 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1400 from, &val);
55ff77ac 1401 store_typed_floating (to, type, val);
283150cd
EZ
1402 }
1403 else
617daa0e
CV
1404 error
1405 ("sh_register_convert_to_virtual called with non DR register number");
283150cd
EZ
1406}
1407
1408static void
1409sh_sh4_register_convert_to_raw (struct type *type, int regnum,
d8124050 1410 const void *from, void *to)
283150cd 1411{
617daa0e 1412 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
283150cd 1413 {
48db5a3c 1414 DOUBLEST val = extract_typed_floating (from, type);
617daa0e
CV
1415 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1416 &val, to);
283150cd
EZ
1417 }
1418 else
617daa0e 1419 error ("sh_register_convert_to_raw called with non DR register number");
283150cd
EZ
1420}
1421
1c0159e0
CV
1422/* For vectors of 4 floating point registers. */
1423static int
1424fv_reg_base_num (int fv_regnum)
1425{
1426 int fp_regnum;
1427
617daa0e 1428 fp_regnum = FP0_REGNUM + (fv_regnum - FV0_REGNUM) * 4;
1c0159e0
CV
1429 return fp_regnum;
1430}
1431
1432/* For double precision floating point registers, i.e 2 fp regs.*/
1433static int
1434dr_reg_base_num (int dr_regnum)
1435{
1436 int fp_regnum;
1437
617daa0e 1438 fp_regnum = FP0_REGNUM + (dr_regnum - DR0_REGNUM) * 2;
1c0159e0
CV
1439 return fp_regnum;
1440}
1441
a78f21af 1442static void
d8124050
AC
1443sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1444 int reg_nr, void *buffer)
53116e27
EZ
1445{
1446 int base_regnum, portion;
d9d9c31f 1447 char temp_buffer[MAX_REGISTER_SIZE];
53116e27 1448
617daa0e 1449 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
7bd872fe
EZ
1450 {
1451 base_regnum = dr_reg_base_num (reg_nr);
1452
617daa0e 1453 /* Build the value in the provided buffer. */
7bd872fe
EZ
1454 /* Read the real regs for which this one is an alias. */
1455 for (portion = 0; portion < 2; portion++)
617daa0e 1456 regcache_raw_read (regcache, base_regnum + portion,
0818c12a 1457 (temp_buffer
617daa0e
CV
1458 + register_size (gdbarch,
1459 base_regnum) * portion));
7bd872fe
EZ
1460 /* We must pay attention to the endiannes. */
1461 sh_sh4_register_convert_to_virtual (reg_nr,
617daa0e
CV
1462 gdbarch_register_type (gdbarch,
1463 reg_nr),
7bd872fe
EZ
1464 temp_buffer, buffer);
1465 }
617daa0e 1466 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27 1467 {
7bd872fe
EZ
1468 base_regnum = fv_reg_base_num (reg_nr);
1469
1470 /* Read the real regs for which this one is an alias. */
1471 for (portion = 0; portion < 4; portion++)
617daa0e 1472 regcache_raw_read (regcache, base_regnum + portion,
d8124050 1473 ((char *) buffer
617daa0e
CV
1474 + register_size (gdbarch,
1475 base_regnum) * portion));
53116e27
EZ
1476 }
1477}
1478
a78f21af 1479static void
d8124050
AC
1480sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1481 int reg_nr, const void *buffer)
53116e27
EZ
1482{
1483 int base_regnum, portion;
d9d9c31f 1484 char temp_buffer[MAX_REGISTER_SIZE];
53116e27 1485
617daa0e 1486 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
53116e27
EZ
1487 {
1488 base_regnum = dr_reg_base_num (reg_nr);
1489
7bd872fe 1490 /* We must pay attention to the endiannes. */
617daa0e
CV
1491 sh_sh4_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
1492 reg_nr, buffer, temp_buffer);
7bd872fe 1493
53116e27
EZ
1494 /* Write the real regs for which this one is an alias. */
1495 for (portion = 0; portion < 2; portion++)
617daa0e 1496 regcache_raw_write (regcache, base_regnum + portion,
0818c12a 1497 (temp_buffer
617daa0e
CV
1498 + register_size (gdbarch,
1499 base_regnum) * portion));
53116e27 1500 }
617daa0e 1501 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27
EZ
1502 {
1503 base_regnum = fv_reg_base_num (reg_nr);
1504
1505 /* Write the real regs for which this one is an alias. */
1506 for (portion = 0; portion < 4; portion++)
d8124050
AC
1507 regcache_raw_write (regcache, base_regnum + portion,
1508 ((char *) buffer
617daa0e
CV
1509 + register_size (gdbarch,
1510 base_regnum) * portion));
53116e27
EZ
1511 }
1512}
1513
3bbfbb92 1514/* Floating point vector of 4 float registers. */
53116e27 1515static void
48db5a3c
CV
1516do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1517 int fv_regnum)
53116e27
EZ
1518{
1519 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
617daa0e
CV
1520 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1521 fv_regnum - FV0_REGNUM,
1522 (int) read_register (first_fp_reg_num),
1523 (int) read_register (first_fp_reg_num + 1),
1524 (int) read_register (first_fp_reg_num + 2),
1525 (int) read_register (first_fp_reg_num + 3));
53116e27
EZ
1526}
1527
3bbfbb92 1528/* Double precision registers. */
53116e27 1529static void
48db5a3c
CV
1530do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1531 int dr_regnum)
53116e27
EZ
1532{
1533 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1534
617daa0e
CV
1535 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
1536 dr_regnum - DR0_REGNUM,
53116e27
EZ
1537 (int) read_register (first_fp_reg_num),
1538 (int) read_register (first_fp_reg_num + 1));
1539}
1540
1541static void
48db5a3c
CV
1542sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
1543 int regnum)
53116e27
EZ
1544{
1545 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
8e65ff28
AC
1546 internal_error (__FILE__, __LINE__,
1547 "Invalid pseudo register number %d\n", regnum);
617daa0e 1548 else if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
48db5a3c 1549 do_dr_register_info (gdbarch, file, regnum);
617daa0e 1550 else if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
48db5a3c 1551 do_fv_register_info (gdbarch, file, regnum);
53116e27
EZ
1552}
1553
53116e27 1554static void
48db5a3c 1555sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
53116e27
EZ
1556{ /* do values for FP (float) regs */
1557 char *raw_buffer;
617daa0e 1558 double flt; /* double extracted from raw hex data */
53116e27
EZ
1559 int inv;
1560 int j;
1561
1562 /* Allocate space for the float. */
48db5a3c 1563 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
53116e27
EZ
1564
1565 /* Get the data in raw format. */
48db5a3c 1566 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
53116e27
EZ
1567 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1568
617daa0e 1569 /* Get the register as a number */
53116e27
EZ
1570 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1571
1572 /* Print the name and some spaces. */
48db5a3c
CV
1573 fputs_filtered (REGISTER_NAME (regnum), file);
1574 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
53116e27
EZ
1575
1576 /* Print the value. */
93d56215 1577 if (inv)
48db5a3c 1578 fprintf_filtered (file, "<invalid float>");
93d56215 1579 else
48db5a3c 1580 fprintf_filtered (file, "%-10.9g", flt);
53116e27
EZ
1581
1582 /* Print the fp register as hex. */
48db5a3c
CV
1583 fprintf_filtered (file, "\t(raw 0x");
1584 for (j = 0; j < register_size (gdbarch, regnum); j++)
53116e27 1585 {
221c12ff
AC
1586 int idx = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1587 ? j
1588 : register_size (gdbarch, regnum) - 1 - j);
48db5a3c 1589 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
53116e27 1590 }
48db5a3c
CV
1591 fprintf_filtered (file, ")");
1592 fprintf_filtered (file, "\n");
53116e27
EZ
1593}
1594
1595static void
48db5a3c 1596sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
53116e27 1597{
123a958e 1598 char raw_buffer[MAX_REGISTER_SIZE];
53116e27 1599
48db5a3c
CV
1600 fputs_filtered (REGISTER_NAME (regnum), file);
1601 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
53116e27
EZ
1602
1603 /* Get the data in raw format. */
48db5a3c
CV
1604 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1605 fprintf_filtered (file, "*value not available*\n");
617daa0e 1606
48db5a3c
CV
1607 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1608 file, 'x', 1, 0, Val_pretty_default);
1609 fprintf_filtered (file, "\t");
1610 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1611 file, 0, 1, 0, Val_pretty_default);
1612 fprintf_filtered (file, "\n");
53116e27
EZ
1613}
1614
1615static void
48db5a3c 1616sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
53116e27
EZ
1617{
1618 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
8e65ff28
AC
1619 internal_error (__FILE__, __LINE__,
1620 "Invalid register number %d\n", regnum);
53116e27 1621
e30839fe 1622 else if (regnum >= 0 && regnum < NUM_REGS)
53116e27 1623 {
617daa0e
CV
1624 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1625 TYPE_CODE_FLT)
48db5a3c 1626 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
53116e27 1627 else
48db5a3c 1628 sh_do_register (gdbarch, file, regnum); /* All other regs */
53116e27
EZ
1629 }
1630
1631 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
48db5a3c 1632 {
55ff77ac 1633 sh_print_pseudo_register (gdbarch, file, regnum);
48db5a3c 1634 }
53116e27
EZ
1635}
1636
a78f21af 1637static void
48db5a3c
CV
1638sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
1639 struct frame_info *frame, int regnum, int fpregs)
53116e27
EZ
1640{
1641 if (regnum != -1) /* do one specified register */
1642 {
1643 if (*(REGISTER_NAME (regnum)) == '\0')
1644 error ("Not a valid register for the current processor type");
1645
48db5a3c 1646 sh_print_register (gdbarch, file, regnum);
53116e27
EZ
1647 }
1648 else
1649 /* do all (or most) registers */
1650 {
1651 regnum = 0;
1652 while (regnum < NUM_REGS)
1653 {
1654 /* If the register name is empty, it is undefined for this
1655 processor, so don't display anything. */
1656 if (REGISTER_NAME (regnum) == NULL
1657 || *(REGISTER_NAME (regnum)) == '\0')
617daa0e 1658 {
53116e27
EZ
1659 regnum++;
1660 continue;
1661 }
1662
617daa0e
CV
1663 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1664 TYPE_CODE_FLT)
53116e27
EZ
1665 {
1666 if (fpregs)
1667 {
1668 /* true for "INFO ALL-REGISTERS" command */
48db5a3c 1669 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
617daa0e 1670 regnum++;
53116e27
EZ
1671 }
1672 else
f2ea0907 1673 regnum += (FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
53116e27
EZ
1674 }
1675 else
1676 {
48db5a3c 1677 sh_do_register (gdbarch, file, regnum); /* All other regs */
53116e27
EZ
1678 regnum++;
1679 }
1680 }
1681
1682 if (fpregs)
1683 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1684 {
55ff77ac 1685 sh_print_pseudo_register (gdbarch, file, regnum);
53116e27
EZ
1686 regnum++;
1687 }
1688 }
1689}
1690
1a8629c7
MS
1691#ifdef SVR4_SHARED_LIBS
1692
1693/* Fetch (and possibly build) an appropriate link_map_offsets structure
1694 for native i386 linux targets using the struct offsets defined in
1695 link.h (but without actual reference to that file).
1696
1697 This makes it possible to access i386-linux shared libraries from
1698 a gdb that was not built on an i386-linux host (for cross debugging).
1699 */
1700
1701struct link_map_offsets *
1702sh_linux_svr4_fetch_link_map_offsets (void)
1703{
1704 static struct link_map_offsets lmo;
1705 static struct link_map_offsets *lmp = 0;
1706
1707 if (lmp == 0)
1708 {
1709 lmp = &lmo;
1710
1711 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
1712
1713 lmo.r_map_offset = 4;
617daa0e 1714 lmo.r_map_size = 4;
1a8629c7
MS
1715
1716 lmo.link_map_size = 20; /* 552 not actual size but all we need */
1717
1718 lmo.l_addr_offset = 0;
617daa0e 1719 lmo.l_addr_size = 4;
1a8629c7
MS
1720
1721 lmo.l_name_offset = 4;
617daa0e 1722 lmo.l_name_size = 4;
1a8629c7
MS
1723
1724 lmo.l_next_offset = 12;
617daa0e 1725 lmo.l_next_size = 4;
1a8629c7
MS
1726
1727 lmo.l_prev_offset = 16;
617daa0e 1728 lmo.l_prev_size = 4;
1a8629c7
MS
1729 }
1730
617daa0e 1731 return lmp;
1a8629c7
MS
1732}
1733#endif /* SVR4_SHARED_LIBS */
1734
2f14585c
JR
1735static int
1736sh_dsp_register_sim_regno (int nr)
1737{
1738 if (legacy_register_sim_regno (nr) < 0)
1739 return legacy_register_sim_regno (nr);
f2ea0907
CV
1740 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
1741 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
1742 if (nr == MOD_REGNUM)
2f14585c 1743 return SIM_SH_MOD_REGNUM;
f2ea0907 1744 if (nr == RS_REGNUM)
2f14585c 1745 return SIM_SH_RS_REGNUM;
f2ea0907 1746 if (nr == RE_REGNUM)
2f14585c 1747 return SIM_SH_RE_REGNUM;
f2ea0907
CV
1748 if (nr >= R0_BANK_REGNUM && nr <= R7_BANK_REGNUM)
1749 return nr - R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2f14585c
JR
1750 return nr;
1751}
1c0159e0
CV
1752
1753static struct sh_frame_cache *
1754sh_alloc_frame_cache (void)
1755{
1756 struct sh_frame_cache *cache;
1757 int i;
1758
1759 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
1760
1761 /* Base address. */
1762 cache->base = 0;
1763 cache->saved_sp = 0;
1764 cache->sp_offset = 0;
1765 cache->pc = 0;
1766
1767 /* Frameless until proven otherwise. */
1768 cache->uses_fp = 0;
617daa0e 1769
1c0159e0
CV
1770 /* Saved registers. We initialize these to -1 since zero is a valid
1771 offset (that's where fp is supposed to be stored). */
1772 for (i = 0; i < SH_NUM_REGS; i++)
1773 {
1774 cache->saved_regs[i] = -1;
1775 }
617daa0e 1776
1c0159e0 1777 return cache;
617daa0e 1778}
1c0159e0
CV
1779
1780static struct sh_frame_cache *
1781sh_frame_cache (struct frame_info *next_frame, void **this_cache)
1782{
1783 struct sh_frame_cache *cache;
1784 CORE_ADDR current_pc;
1785 int i;
1786
1787 if (*this_cache)
1788 return *this_cache;
1789
1790 cache = sh_alloc_frame_cache ();
1791 *this_cache = cache;
1792
1793 /* In principle, for normal frames, fp holds the frame pointer,
1794 which holds the base address for the current stack frame.
1795 However, for functions that don't need it, the frame pointer is
1796 optional. For these "frameless" functions the frame pointer is
1797 actually the frame pointer of the calling frame. */
1798 cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
1799 if (cache->base == 0)
1800 return cache;
1801
1802 cache->pc = frame_func_unwind (next_frame);
1803 current_pc = frame_pc_unwind (next_frame);
1804 if (cache->pc != 0)
1805 sh_analyze_prologue (cache->pc, current_pc, cache);
617daa0e 1806
1c0159e0
CV
1807 if (!cache->uses_fp)
1808 {
1809 /* We didn't find a valid frame, which means that CACHE->base
1810 currently holds the frame pointer for our calling frame. If
1811 we're at the start of a function, or somewhere half-way its
1812 prologue, the function's frame probably hasn't been fully
1813 setup yet. Try to reconstruct the base address for the stack
1814 frame by looking at the stack pointer. For truly "frameless"
1815 functions this might work too. */
1816 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
1817 }
1818
1819 /* Now that we have the base address for the stack frame we can
1820 calculate the value of sp in the calling frame. */
1821 cache->saved_sp = cache->base + cache->sp_offset;
1822
1823 /* Adjust all the saved registers such that they contain addresses
1824 instead of offsets. */
1825 for (i = 0; i < SH_NUM_REGS; i++)
1826 if (cache->saved_regs[i] != -1)
1827 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
1828
1829 return cache;
1830}
1831
1832static void
1833sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1834 int regnum, int *optimizedp,
1835 enum lval_type *lvalp, CORE_ADDR *addrp,
1836 int *realnump, void *valuep)
1837{
1838 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1839
1840 gdb_assert (regnum >= 0);
1841
1842 if (regnum == SP_REGNUM && cache->saved_sp)
1843 {
1844 *optimizedp = 0;
1845 *lvalp = not_lval;
1846 *addrp = 0;
1847 *realnump = -1;
1848 if (valuep)
617daa0e
CV
1849 {
1850 /* Store the value. */
1851 store_unsigned_integer (valuep, 4, cache->saved_sp);
1852 }
1c0159e0
CV
1853 return;
1854 }
1855
1856 /* The PC of the previous frame is stored in the PR register of
1857 the current frame. Frob regnum so that we pull the value from
1858 the correct place. */
1859 if (regnum == PC_REGNUM)
1860 regnum = PR_REGNUM;
1861
1862 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
1863 {
1864 *optimizedp = 0;
1865 *lvalp = lval_memory;
1866 *addrp = cache->saved_regs[regnum];
1867 *realnump = -1;
1868 if (valuep)
617daa0e
CV
1869 {
1870 /* Read the value in from memory. */
1871 read_memory (*addrp, valuep,
1872 register_size (current_gdbarch, regnum));
1873 }
1c0159e0
CV
1874 return;
1875 }
1876
1877 frame_register_unwind (next_frame, regnum,
617daa0e 1878 optimizedp, lvalp, addrp, realnump, valuep);
1c0159e0
CV
1879}
1880
1881static void
1882sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
617daa0e
CV
1883 struct frame_id *this_id)
1884{
1c0159e0
CV
1885 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1886
1887 /* This marks the outermost frame. */
1888 if (cache->base == 0)
1889 return;
1890
1891 *this_id = frame_id_build (cache->saved_sp, cache->pc);
617daa0e 1892}
1c0159e0 1893
617daa0e 1894static const struct frame_unwind sh_frame_unwind = {
1c0159e0
CV
1895 NORMAL_FRAME,
1896 sh_frame_this_id,
1897 sh_frame_prev_register
1898};
1899
1900static const struct frame_unwind *
1901sh_frame_sniffer (struct frame_info *next_frame)
1902{
1903 return &sh_frame_unwind;
1904}
1905
1906static CORE_ADDR
1907sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1908{
1909 return frame_unwind_register_unsigned (next_frame, SP_REGNUM);
1910}
1911
1912static CORE_ADDR
1913sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1914{
1915 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
1916}
1917
1918static struct frame_id
1919sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1920{
1921 return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
1922 frame_pc_unwind (next_frame));
1923}
1924
1925static CORE_ADDR
1926sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
617daa0e 1927{
1c0159e0 1928 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
617daa0e 1929
1c0159e0
CV
1930 return cache->base;
1931}
617daa0e
CV
1932
1933static const struct frame_base sh_frame_base = {
1c0159e0
CV
1934 &sh_frame_unwind,
1935 sh_frame_base_address,
1936 sh_frame_base_address,
1937 sh_frame_base_address
617daa0e 1938};
1c0159e0
CV
1939
1940/* The epilogue is defined here as the area at the end of a function,
1941 either on the `ret' instruction itself or after an instruction which
1942 destroys the function's stack frame. */
1943static int
1944sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1945{
1946 CORE_ADDR func_addr = 0, func_end = 0;
1947
1948 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1949 {
1950 ULONGEST inst;
1951 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
1952 for a nop and some fixed data (e.g. big offsets) which are
617daa0e
CV
1953 unfortunately also treated as part of the function (which
1954 means, they are below func_end. */
1c0159e0
CV
1955 CORE_ADDR addr = func_end - 28;
1956 if (addr < func_addr + 4)
617daa0e 1957 addr = func_addr + 4;
1c0159e0
CV
1958 if (pc < addr)
1959 return 0;
1960
1961 /* First search forward until hitting an rts. */
1962 while (addr < func_end
617daa0e 1963 && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
1c0159e0
CV
1964 addr += 2;
1965 if (addr >= func_end)
617daa0e 1966 return 0;
1c0159e0
CV
1967
1968 /* At this point we should find a mov.l @r15+,r14 instruction,
1969 either before or after the rts. If not, then the function has
617daa0e 1970 probably no "normal" epilogue and we bail out here. */
1c0159e0
CV
1971 inst = read_memory_unsigned_integer (addr - 2, 2);
1972 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
617daa0e 1973 addr -= 2;
1c0159e0
CV
1974 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
1975 return 0;
1976
1977 /* Step over possible lds.l @r15+,pr. */
1978 inst = read_memory_unsigned_integer (addr - 2, 2);
1979 if (IS_LDS (inst))
617daa0e 1980 {
1c0159e0
CV
1981 addr -= 2;
1982 inst = read_memory_unsigned_integer (addr - 2, 2);
1983 }
1984
1985 /* Step over possible mov r14,r15. */
1986 if (IS_MOV_FP_SP (inst))
617daa0e 1987 {
1c0159e0
CV
1988 addr -= 2;
1989 inst = read_memory_unsigned_integer (addr - 2, 2);
1990 }
1991
1992 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
1993 instructions. */
1994 while (addr > func_addr + 4
617daa0e 1995 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
1c0159e0
CV
1996 {
1997 addr -= 2;
1998 inst = read_memory_unsigned_integer (addr - 2, 2);
1999 }
2000
2001 if (pc >= addr)
2002 return 1;
2003 }
2004 return 0;
2005}
2006
cc17453a
EZ
2007static gdbarch_init_ftype sh_gdbarch_init;
2008
2009static struct gdbarch *
fba45db2 2010sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
cc17453a 2011{
cc17453a 2012 struct gdbarch *gdbarch;
d658f924 2013
55ff77ac
CV
2014 sh_show_regs = sh_generic_show_regs;
2015 switch (info.bfd_arch_info->mach)
2016 {
617daa0e
CV
2017 case bfd_mach_sh2e:
2018 sh_show_regs = sh2e_show_regs;
2019 break;
2020 case bfd_mach_sh_dsp:
2021 sh_show_regs = sh_dsp_show_regs;
2022 break;
55ff77ac 2023
617daa0e
CV
2024 case bfd_mach_sh3:
2025 sh_show_regs = sh3_show_regs;
2026 break;
55ff77ac 2027
617daa0e
CV
2028 case bfd_mach_sh3e:
2029 sh_show_regs = sh3e_show_regs;
2030 break;
55ff77ac 2031
617daa0e
CV
2032 case bfd_mach_sh3_dsp:
2033 sh_show_regs = sh3_dsp_show_regs;
2034 break;
55ff77ac 2035
617daa0e
CV
2036 case bfd_mach_sh4:
2037 sh_show_regs = sh4_show_regs;
2038 break;
55ff77ac 2039
617daa0e
CV
2040 case bfd_mach_sh5:
2041 sh_show_regs = sh64_show_regs;
2042 /* SH5 is handled entirely in sh64-tdep.c */
2043 return sh64_gdbarch_init (info, arches);
55ff77ac
CV
2044 }
2045
4be87837
DJ
2046 /* If there is already a candidate, use it. */
2047 arches = gdbarch_list_lookup_by_info (arches, &info);
2048 if (arches != NULL)
2049 return arches->gdbarch;
cc17453a
EZ
2050
2051 /* None found, create a new architecture from the information
2052 provided. */
f2ea0907 2053 gdbarch = gdbarch_alloc (&info, NULL);
cc17453a 2054
48db5a3c
CV
2055 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2056 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
ec920329 2057 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c
CV
2058 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2059 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2060 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2061 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
a38d2a54 2062 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c 2063
f2ea0907 2064 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
a38d2a54 2065 set_gdbarch_sp_regnum (gdbarch, 15);
a38d2a54 2066 set_gdbarch_pc_regnum (gdbarch, 16);
48db5a3c
CV
2067 set_gdbarch_fp0_regnum (gdbarch, -1);
2068 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2069
1c0159e0
CV
2070 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2071
2072 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
2073
eaf90c5d 2074 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
3bbfbb92 2075 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
48db5a3c 2076
2bf0cb65 2077 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2f14585c 2078 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
48db5a3c
CV
2079
2080 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2081
1c0159e0
CV
2082 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
2083 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
2084 set_gdbarch_extract_struct_value_address (gdbarch,
2085 sh_extract_struct_value_address);
2086
48db5a3c
CV
2087 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2088 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2089 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2090 set_gdbarch_function_start_offset (gdbarch, 0);
2091
1c0159e0
CV
2092 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2093
48db5a3c 2094 set_gdbarch_frame_args_skip (gdbarch, 0);
1c0159e0
CV
2095 set_gdbarch_frameless_function_invocation (gdbarch,
2096 frameless_look_for_prologue);
48db5a3c
CV
2097 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2098
19f59343 2099 set_gdbarch_frame_align (gdbarch, sh_frame_align);
1c0159e0
CV
2100 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2101 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2102 set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2103 frame_base_set_default (gdbarch, &sh_frame_base);
2104
617daa0e 2105 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
cc17453a
EZ
2106
2107 switch (info.bfd_arch_info->mach)
8db62801 2108 {
cc17453a 2109 case bfd_mach_sh:
48db5a3c 2110 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
cc17453a 2111 break;
1c0159e0 2112
cc17453a 2113 case bfd_mach_sh2:
48db5a3c 2114 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
617daa0e 2115 break;
1c0159e0 2116
2d188dd3 2117 case bfd_mach_sh2e:
48db5a3c
CV
2118 /* doubles on sh2e and sh3e are actually 4 byte. */
2119 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2120
2121 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
48db5a3c 2122 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2d188dd3 2123 set_gdbarch_fp0_regnum (gdbarch, 25);
48db5a3c 2124 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
617daa0e
CV
2125 set_gdbarch_extract_return_value (gdbarch,
2126 sh3e_sh4_extract_return_value);
6df2bf50 2127 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2d188dd3 2128 break;
1c0159e0 2129
cc17453a 2130 case bfd_mach_sh_dsp:
48db5a3c 2131 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2f14585c 2132 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a 2133 break;
1c0159e0 2134
cc17453a 2135 case bfd_mach_sh3:
48db5a3c 2136 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
cc17453a 2137 break;
1c0159e0 2138
cc17453a 2139 case bfd_mach_sh3e:
48db5a3c
CV
2140 /* doubles on sh2e and sh3e are actually 4 byte. */
2141 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2142
2143 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
48db5a3c 2144 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
cc17453a 2145 set_gdbarch_fp0_regnum (gdbarch, 25);
48db5a3c 2146 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
617daa0e
CV
2147 set_gdbarch_extract_return_value (gdbarch,
2148 sh3e_sh4_extract_return_value);
6df2bf50 2149 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
cc17453a 2150 break;
1c0159e0 2151
cc17453a 2152 case bfd_mach_sh3_dsp:
48db5a3c 2153 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
48db5a3c 2154 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a 2155 break;
1c0159e0 2156
cc17453a 2157 case bfd_mach_sh4:
48db5a3c 2158 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
48db5a3c 2159 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
cc17453a 2160 set_gdbarch_fp0_regnum (gdbarch, 25);
53116e27 2161 set_gdbarch_num_pseudo_regs (gdbarch, 12);
d8124050
AC
2162 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2163 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
48db5a3c 2164 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
617daa0e
CV
2165 set_gdbarch_extract_return_value (gdbarch,
2166 sh3e_sh4_extract_return_value);
6df2bf50 2167 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
cc17453a 2168 break;
1c0159e0 2169
cc17453a 2170 default:
48db5a3c 2171 set_gdbarch_register_name (gdbarch, sh_generic_register_name);
cc17453a 2172 break;
8db62801 2173 }
cc17453a 2174
4be87837
DJ
2175 /* Hook in ABI-specific overrides, if they have been registered. */
2176 gdbarch_init_osabi (info, gdbarch);
d658f924 2177
1c0159e0
CV
2178 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2179 frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2180
cc17453a 2181 return gdbarch;
8db62801
EZ
2182}
2183
617daa0e 2184extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
a78f21af 2185
c906108c 2186void
fba45db2 2187_initialize_sh_tdep (void)
c906108c
SS
2188{
2189 struct cmd_list_element *c;
617daa0e 2190
f2ea0907 2191 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
c906108c 2192
53116e27 2193 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
c906108c 2194}
This page took 0.52052 seconds and 4 git commands to generate.